diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/bin/openbtl_olimex_stm32e407.elf b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/bin/openbtl_olimex_stm32e407.elf index e5f2a67c..e843df6b 100644 Binary files a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/bin/openbtl_olimex_stm32e407.elf and b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/bin/openbtl_olimex_stm32e407.elf differ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/bin/openbtl_olimex_stm32e407.map b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/bin/openbtl_olimex_stm32e407.map index 9645b556..aa5dfcca 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/bin/openbtl_olimex_stm32e407.map +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/bin/openbtl_olimex_stm32e407.map @@ -1008,8 +1008,6 @@ Discarded input sections 0x00000000 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o .text.RCC_AHB3PeriphClockCmd 0x00000000 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o - .text.RCC_AHB1PeriphResetCmd - 0x00000000 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o .text.RCC_AHB2PeriphResetCmd 0x00000000 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o .text.RCC_AHB3PeriphResetCmd @@ -1306,24 +1304,10 @@ Discarded input sections 0x00000000 0xc THUMB Debug/../../obj/stm32f4xx_syscfg.o .text.SYSCFG_EXTILineConfig 0x00000000 0x40 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .text.SYSCFG_ETH_MediaInterfaceConfig - 0x00000000 0xc THUMB Debug/../../obj/stm32f4xx_syscfg.o .text.SYSCFG_CompensationCellCmd 0x00000000 0xc THUMB Debug/../../obj/stm32f4xx_syscfg.o .text.SYSCFG_GetCompensationCellStatus 0x00000000 0x10 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_frame 0x00000000 0x88 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_info 0x00000000 0x2b7 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_abbrev 0x00000000 0x177 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_loc 0x00000000 0xe6 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_aranges - 0x00000000 0x48 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_ranges 0x00000000 0x38 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_line 0x00000000 0x27d THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_str 0x00000000 0x354 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_syscfg.o - .ARM.attributes - 0x00000000 0x33 THUMB Debug/../../obj/stm32f4xx_syscfg.o .text 0x00000000 0x0 THUMB Debug/../../obj/stm32f4xx_tim.o .data 0x00000000 0x0 THUMB Debug/../../obj/stm32f4xx_tim.o .bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f4xx_tim.o @@ -1600,6 +1584,209 @@ Discarded input sections .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_wwdg.o .ARM.attributes 0x00000000 0x33 THUMB Debug/../../obj/stm32f4xx_wwdg.o + .text 0x00000000 0x0 THUMB Debug/../../obj/stm32_eth.o + .data 0x00000000 0x0 THUMB Debug/../../obj/stm32_eth.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_HandleTxPkt + 0x00000000 0x12c THUMB Debug/../../obj/stm32_eth.o + .text.ETH_HandleRxPkt + 0x00000000 0x120 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DropRxPkt + 0x00000000 0x64 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_PHYLoopBackCmd + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetFlowControlBusyStatus + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_InitiatePauseControlFrame + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_BackPressureActivationCmd + 0x00000000 0x28 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetMACFlagStatus + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetMACITStatus + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MACITConfig + 0x00000000 0x24 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MACAddressConfig + 0x00000000 0x34 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetMACAddress + 0x00000000 0x34 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MACAddressPerfectFilterCmd + 0x00000000 0x28 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MACAddressFilterConfig + 0x00000000 0x1c THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MACAddressMaskBytesFilterConfig + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescChainInit + 0x00000000 0xc4 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescRingInit + 0x00000000 0xc4 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMATxDescFlagStatus + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMATxDescCollisionCount + 0x00000000 0x8 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetDMATxDescOwnBit + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescTransmitITConfig + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescFrameSegmentConfig + 0x00000000 0x8 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescChecksumInsertionConfig + 0x00000000 0x8 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescCRCCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescEndOfRingCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescSecondAddressChainedCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescShortFramePaddingCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescTimeStampCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescBufferSizeConfig + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMARxDescChainInit + 0x00000000 0xdc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMARxDescRingInit + 0x00000000 0x14c THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMARxDescFlagStatus + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetDMARxDescOwnBit + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMARxDescFrameLength + 0x00000000 0x8 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetRxPktSize + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMARxDescReceiveITConfig + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMARxDescEndOfRingCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMARxDescSecondAddressChainedCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMARxDescBufferSize + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMAFlagStatus + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMAClearFlag + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMAITStatus + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMAClearITPendingBit + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetTransmitProcessState + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetReceiveProcessState + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetFlushTransmitFIFOStatus + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMAITConfig + 0x00000000 0x24 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMAOverflowStatus + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetRxOverflowMissedFrameCounter + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetBufferUnavailableMissedFrameCounter + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetCurrentTxDescStartAddress + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetCurrentRxDescStartAddress + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetCurrentTxBufferAddress + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetCurrentRxBufferAddress + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_ResumeDMATransmission + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_ResumeDMAReception + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_ResetWakeUpFrameFilterRegisterPointer + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetWakeUpFrameFilterRegister + 0x00000000 0x2c THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GlobalUnicastWakeUpCmd + 0x00000000 0x28 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetPMTFlagStatus + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_WakeUpFrameDetectionCmd + 0x00000000 0x28 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MagicPacketDetectionCmd + 0x00000000 0x28 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_PowerDownCmd + 0x00000000 0x28 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MMCCounterFreezeCmd + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MMCResetOnReadCmd + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MMCCounterRolloverCmd + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MMCCountersReset + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MMCITConfig + 0x00000000 0x64 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetMMCITStatus + 0x00000000 0x60 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetMMCRegister + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_EnablePTPTimeStampAddend + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_EnablePTPTimeStampInterruptTrigger + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_EnablePTPTimeStampUpdate + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_InitializePTPTimeStamp + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_PTPUpdateMethodConfig + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_PTPTimeStampCmd + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetPTPFlagStatus + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetPTPSubSecondIncrement + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetPTPTimeStampUpdate + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetPTPTimeStampAddend + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetPTPTargetTime + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetPTPRegister + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMAPTPTxDescChainInit + 0x00000000 0x120 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMAPTPRxDescChainInit + 0x00000000 0x12c THUMB Debug/../../obj/stm32_eth.o + .text.ETH_HandlePTPTxPkt + 0x00000000 0x1dc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_HandlePTPRxPkt + 0x00000000 0x14c THUMB Debug/../../obj/stm32_eth.o + .bss.DMARxDescToGet + 0x00000000 0x4 THUMB Debug/../../obj/stm32_eth.o + .bss.DMAPTPTxDescToSet + 0x00000000 0x4 THUMB Debug/../../obj/stm32_eth.o + .bss.DMATxDescToSet + 0x00000000 0x4 THUMB Debug/../../obj/stm32_eth.o + .bss.DMAPTPRxDescToGet + 0x00000000 0x4 THUMB Debug/../../obj/stm32_eth.o + .text 0x00000000 0x0 THUMB Debug/../../obj/clock-arch.o + .data 0x00000000 0x0 THUMB Debug/../../obj/clock-arch.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/clock-arch.o + .text.clock_time + 0x00000000 0x8 THUMB Debug/../../obj/clock-arch.o + .debug_frame 0x00000000 0x2c THUMB Debug/../../obj/clock-arch.o + .debug_info 0x00000000 0xbc THUMB Debug/../../obj/clock-arch.o + .debug_abbrev 0x00000000 0x73 THUMB Debug/../../obj/clock-arch.o + .debug_loc 0x00000000 0x20 THUMB Debug/../../obj/clock-arch.o + .debug_aranges + 0x00000000 0x20 THUMB Debug/../../obj/clock-arch.o + .debug_ranges 0x00000000 0x10 THUMB Debug/../../obj/clock-arch.o + .debug_line 0x00000000 0xe8 THUMB Debug/../../obj/clock-arch.o + .debug_str 0x00000000 0x1a8 THUMB Debug/../../obj/clock-arch.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/clock-arch.o + .ARM.attributes + 0x00000000 0x33 THUMB Debug/../../obj/clock-arch.o + .text 0x00000000 0x0 THUMB Debug/../../obj/netdev.o + .data 0x00000000 0x0 THUMB Debug/../../obj/netdev.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/netdev.o .text 0x00000000 0x0 THUMB Debug/../../obj/hooks.o .data 0x00000000 0x0 THUMB Debug/../../obj/hooks.o .bss 0x00000000 0x0 THUMB Debug/../../obj/hooks.o @@ -1680,6 +1867,98 @@ Discarded input sections .text 0x00000000 0x0 THUMB Debug/../../obj/unicode.o .data 0x00000000 0x0 THUMB Debug/../../obj/unicode.o .bss 0x00000000 0x0 THUMB Debug/../../obj/unicode.o + .text 0x00000000 0x0 THUMB Debug/../../obj/uip.o + .data 0x00000000 0x0 THUMB Debug/../../obj/uip.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/uip.o + .text.uip_setipid + 0x00000000 0xc THUMB Debug/../../obj/uip.o + .text.uip_unlisten + 0x00000000 0x38 THUMB Debug/../../obj/uip.o + .text.uip_connect + 0x00000000 0x108 THUMB Debug/../../obj/uip.o + .text.uip_udpchksum + 0x00000000 0xc THUMB Debug/../../obj/uip.o + .text.uip_chksum + 0x00000000 0x18 THUMB Debug/../../obj/uip.o + .text 0x00000000 0x0 THUMB Debug/../../obj/uip_arp.o + .data 0x00000000 0x0 THUMB Debug/../../obj/uip_arp.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/uip_arp.o + .text.uip_arp_init + 0x00000000 0x40 THUMB Debug/../../obj/uip_arp.o + .text 0x00000000 0x0 THUMB Debug/../../obj/uip_timer.o + .data 0x00000000 0x0 THUMB Debug/../../obj/uip_timer.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/uip_timer.o + .text.timer_set + 0x00000000 0x10 THUMB Debug/../../obj/uip_timer.o + .text.timer_reset + 0x00000000 0xc THUMB Debug/../../obj/uip_timer.o + .text.timer_restart + 0x00000000 0xc THUMB Debug/../../obj/uip_timer.o + .text.timer_expired + 0x00000000 0x18 THUMB Debug/../../obj/uip_timer.o + .debug_frame 0x00000000 0x74 THUMB Debug/../../obj/uip_timer.o + .debug_info 0x00000000 0x144 THUMB Debug/../../obj/uip_timer.o + .debug_abbrev 0x00000000 0xf0 THUMB Debug/../../obj/uip_timer.o + .debug_loc 0x00000000 0xdb THUMB Debug/../../obj/uip_timer.o + .debug_aranges + 0x00000000 0x38 THUMB Debug/../../obj/uip_timer.o + .debug_ranges 0x00000000 0x28 THUMB Debug/../../obj/uip_timer.o + .debug_line 0x00000000 0x127 THUMB Debug/../../obj/uip_timer.o + .debug_str 0x00000000 0x189 THUMB Debug/../../obj/uip_timer.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/uip_timer.o + .ARM.attributes + 0x00000000 0x33 THUMB Debug/../../obj/uip_timer.o + .text 0x00000000 0x0 THUMB Debug/../../obj/uip-fw.o + .data 0x00000000 0x0 THUMB Debug/../../obj/uip-fw.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/uip-fw.o + .text.uip_fw_init + 0x00000000 0x34 THUMB Debug/../../obj/uip-fw.o + .text.uip_fw_output + 0x00000000 0xe8 THUMB Debug/../../obj/uip-fw.o + .text.uip_fw_forward + 0x00000000 0x1dc THUMB Debug/../../obj/uip-fw.o + .text.uip_fw_register + 0x00000000 0x10 THUMB Debug/../../obj/uip-fw.o + .text.uip_fw_default + 0x00000000 0xc THUMB Debug/../../obj/uip-fw.o + .text.uip_fw_periodic + 0x00000000 0x28 THUMB Debug/../../obj/uip-fw.o + .bss.netifs 0x00000000 0x4 THUMB Debug/../../obj/uip-fw.o + .bss.defaultnetif + 0x00000000 0x4 THUMB Debug/../../obj/uip-fw.o + .bss.fwcache 0x00000000 0x1c THUMB Debug/../../obj/uip-fw.o + .debug_frame 0x00000000 0x90 THUMB Debug/../../obj/uip-fw.o + .debug_info 0x00000000 0x71a THUMB Debug/../../obj/uip-fw.o + .debug_abbrev 0x00000000 0x295 THUMB Debug/../../obj/uip-fw.o + .debug_loc 0x00000000 0x18c THUMB Debug/../../obj/uip-fw.o + .debug_aranges + 0x00000000 0x48 THUMB Debug/../../obj/uip-fw.o + .debug_ranges 0x00000000 0x68 THUMB Debug/../../obj/uip-fw.o + .debug_line 0x00000000 0x246 THUMB Debug/../../obj/uip-fw.o + .debug_str 0x00000000 0x3bf THUMB Debug/../../obj/uip-fw.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/uip-fw.o + .ARM.attributes + 0x00000000 0x33 THUMB Debug/../../obj/uip-fw.o + .text 0x00000000 0x0 THUMB Debug/../../obj/uiplib.o + .data 0x00000000 0x0 THUMB Debug/../../obj/uiplib.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/uiplib.o + .text.uiplib_ipaddrconv + 0x00000000 0x370 THUMB Debug/../../obj/uiplib.o + .debug_frame 0x00000000 0x2c THUMB Debug/../../obj/uiplib.o + .debug_info 0x00000000 0xef THUMB Debug/../../obj/uiplib.o + .debug_abbrev 0x00000000 0x6f THUMB Debug/../../obj/uiplib.o + .debug_loc 0x00000000 0xf89 THUMB Debug/../../obj/uiplib.o + .debug_aranges + 0x00000000 0x20 THUMB Debug/../../obj/uiplib.o + .debug_ranges 0x00000000 0x10 THUMB Debug/../../obj/uiplib.o + .debug_line 0x00000000 0x177 THUMB Debug/../../obj/uiplib.o + .debug_str 0x00000000 0x1b5 THUMB Debug/../../obj/uiplib.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/uiplib.o + .ARM.attributes + 0x00000000 0x33 THUMB Debug/../../obj/uiplib.o + .text 0x00000000 0x0 THUMB Debug/../../obj/net.o + .data 0x00000000 0x0 THUMB Debug/../../obj/net.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/net.o .text 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) .data 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) .bss 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) @@ -2054,8 +2333,6 @@ Discarded input sections 0x00000000 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) .text.libc.memcpy_small 0x00000000 0x1c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) - .text.libc.memset - 0x00000000 0x70 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) .text.libc.__aeabi_memset 0x00000000 0x74 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) .text.libc.setjmp @@ -2424,11 +2701,11 @@ Memory Configuration Name Origin Length Attributes UNPLACED_SECTIONS 0xffffffff 0x00000000 xw -FLASH 0x08000000 0x00008000 xr +FLASH 0x08000000 0x0000c000 xr DATA_SRAM 0x10000000 0x00010000 xw SYSTEM 0x1fff0000 0x00007a10 xw OPTION 0x1fffc000 0x00000008 xw -RAM 0x20000000 0x00004000 xw +RAM 0x20000000 0x00006000 xw SRAM1 0x20000000 0x0001c000 xw SRAM2 0x2001c000 0x00004000 xw APB1 0x40000000 0x00008000 xw @@ -2450,9 +2727,9 @@ CM3_System_Control_Space 0xe000e000 0x00001000 xw Linker script and memory map - 0x08006abc __do_debug_operation = __do_debug_operation_mempoll + 0x08008fdc __do_debug_operation = __do_debug_operation_mempoll 0x08000000 __FLASH_segment_start__ = 0x8000000 - 0x08008000 __FLASH_segment_end__ = 0x8008000 + 0x0800c000 __FLASH_segment_end__ = 0x800c000 0x10000000 __DATA_SRAM_segment_start__ = 0x10000000 0x10010000 __DATA_SRAM_segment_end__ = 0x10010000 0x1fff0000 __SYSTEM_segment_start__ = 0x1fff0000 @@ -2460,7 +2737,7 @@ Linker script and memory map 0x1fffc000 __OPTION_segment_start__ = 0x1fffc000 0x1fffc008 __OPTION_segment_end__ = 0x1fffc008 0x20000000 __RAM_segment_start__ = 0x20000000 - 0x20004000 __RAM_segment_end__ = 0x20004000 + 0x20006000 __RAM_segment_end__ = 0x20006000 0x20000000 __SRAM1_segment_start__ = 0x20000000 0x2001c000 __SRAM1_segment_end__ = 0x2001c000 0x2001c000 __SRAM2_segment_start__ = 0x2001c000 @@ -2535,7 +2812,7 @@ Linker script and memory map 0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= __FLASH_segment_end__)), error: .init is too large to fit in FLASH memory segment) 0x08000328 __text_load_start__ = ALIGN (__init_end__, 0x4) -.text 0x08000328 0x67d8 +.text 0x08000328 0x8cf8 0x08000328 __text_start__ = . *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*) .glue_7 0x00000000 0x0 linker stubs @@ -2644,356 +2921,468 @@ Linker script and memory map .text.RCC_APB2PeriphClockCmd 0x08001e38 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o 0x08001e38 RCC_APB2PeriphClockCmd - .text.RCC_APB2PeriphResetCmd + .text.RCC_AHB1PeriphResetCmd 0x08001e5c 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o - 0x08001e5c RCC_APB2PeriphResetCmd + 0x08001e5c RCC_AHB1PeriphResetCmd + .text.RCC_APB2PeriphResetCmd + 0x08001e80 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o + 0x08001e80 RCC_APB2PeriphResetCmd .text.SDIO_DeInit - 0x08001e80 0x1c THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001e80 SDIO_DeInit + 0x08001ea4 0x1c THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001ea4 SDIO_DeInit .text.SDIO_Init - 0x08001e9c 0x34 THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001e9c SDIO_Init + 0x08001ec0 0x34 THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001ec0 SDIO_Init .text.SDIO_ClockCmd - 0x08001ed0 0xc THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001ed0 SDIO_ClockCmd + 0x08001ef4 0xc THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001ef4 SDIO_ClockCmd .text.SDIO_SetPowerState - 0x08001edc 0xc THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001edc SDIO_SetPowerState + 0x08001f00 0xc THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001f00 SDIO_SetPowerState .text.SDIO_GetPowerState - 0x08001ee8 0x10 THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001ee8 SDIO_GetPowerState + 0x08001f0c 0x10 THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001f0c SDIO_GetPowerState .text.SDIO_SendCommand - 0x08001ef8 0x30 THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001ef8 SDIO_SendCommand + 0x08001f1c 0x30 THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001f1c SDIO_SendCommand .text.SDIO_GetCommandResponse - 0x08001f28 0x10 THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001f28 SDIO_GetCommandResponse + 0x08001f4c 0x10 THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001f4c SDIO_GetCommandResponse .text.SDIO_GetResponse - 0x08001f38 0x1c THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001f38 SDIO_GetResponse + 0x08001f5c 0x1c THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001f5c SDIO_GetResponse .text.SDIO_DataConfig - 0x08001f54 0x30 THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001f54 SDIO_DataConfig + 0x08001f78 0x30 THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001f78 SDIO_DataConfig .text.SDIO_ReadData - 0x08001f84 0x10 THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001f84 SDIO_ReadData + 0x08001fa8 0x10 THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001fa8 SDIO_ReadData .text.SDIO_WriteData - 0x08001f94 0x10 THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001f94 SDIO_WriteData + 0x08001fb8 0x10 THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001fb8 SDIO_WriteData .text.SDIO_GetFlagStatus - 0x08001fa4 0x14 THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001fa4 SDIO_GetFlagStatus + 0x08001fc8 0x14 THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001fc8 SDIO_GetFlagStatus .text.SDIO_ClearFlag - 0x08001fb8 0xc THUMB Debug/../../obj/stm32f4xx_sdio.o - 0x08001fb8 SDIO_ClearFlag + 0x08001fdc 0xc THUMB Debug/../../obj/stm32f4xx_sdio.o + 0x08001fdc SDIO_ClearFlag + .text.SYSCFG_ETH_MediaInterfaceConfig + 0x08001fe8 0xc THUMB Debug/../../obj/stm32f4xx_syscfg.o + 0x08001fe8 SYSCFG_ETH_MediaInterfaceConfig .text.USART_Init - 0x08001fc4 0x108 THUMB Debug/../../obj/stm32f4xx_usart.o - 0x08001fc4 USART_Init + 0x08001ff4 0x108 THUMB Debug/../../obj/stm32f4xx_usart.o + 0x08001ff4 USART_Init .text.USART_Cmd - 0x080020cc 0x20 THUMB Debug/../../obj/stm32f4xx_usart.o - 0x080020cc USART_Cmd + 0x080020fc 0x20 THUMB Debug/../../obj/stm32f4xx_usart.o + 0x080020fc USART_Cmd .text.USART_SendData - 0x080020ec 0xc THUMB Debug/../../obj/stm32f4xx_usart.o - 0x080020ec USART_SendData + 0x0800211c 0xc THUMB Debug/../../obj/stm32f4xx_usart.o + 0x0800211c USART_SendData .text.USART_ReceiveData - 0x080020f8 0xc THUMB Debug/../../obj/stm32f4xx_usart.o - 0x080020f8 USART_ReceiveData + 0x08002128 0xc THUMB Debug/../../obj/stm32f4xx_usart.o + 0x08002128 USART_ReceiveData .text.USART_GetFlagStatus - 0x08002104 0xc THUMB Debug/../../obj/stm32f4xx_usart.o - 0x08002104 USART_GetFlagStatus + 0x08002134 0xc THUMB Debug/../../obj/stm32f4xx_usart.o + 0x08002134 USART_GetFlagStatus + .text.ETH_DeInit + 0x08002140 0x1c THUMB Debug/../../obj/stm32_eth.o + 0x08002140 ETH_DeInit + .text.ETH_StructInit + 0x0800215c 0xa8 THUMB Debug/../../obj/stm32_eth.o + 0x0800215c ETH_StructInit + .text.ETH_ReadPHYRegister + 0x08002204 0x78 THUMB Debug/../../obj/stm32_eth.o + 0x08002204 ETH_ReadPHYRegister + .text.ETH_WritePHYRegister + 0x0800227c 0x70 THUMB Debug/../../obj/stm32_eth.o + 0x0800227c ETH_WritePHYRegister + .text.ETH_Init + 0x080022ec 0x2f0 THUMB Debug/../../obj/stm32_eth.o + 0x080022ec ETH_Init + .text.ETH_MACTransmissionCmd + 0x080025dc 0x28 THUMB Debug/../../obj/stm32_eth.o + 0x080025dc ETH_MACTransmissionCmd + .text.ETH_MACReceptionCmd + 0x08002604 0x28 THUMB Debug/../../obj/stm32_eth.o + 0x08002604 ETH_MACReceptionCmd + .text.ETH_SoftwareReset + 0x0800262c 0x14 THUMB Debug/../../obj/stm32_eth.o + 0x0800262c ETH_SoftwareReset + .text.ETH_GetSoftwareResetStatus + 0x08002640 0x10 THUMB Debug/../../obj/stm32_eth.o + 0x08002640 ETH_GetSoftwareResetStatus + .text.ETH_FlushTransmitFIFO + 0x08002650 0x14 THUMB Debug/../../obj/stm32_eth.o + 0x08002650 ETH_FlushTransmitFIFO + .text.ETH_DMATransmissionCmd + 0x08002664 0x28 THUMB Debug/../../obj/stm32_eth.o + 0x08002664 ETH_DMATransmissionCmd + .text.ETH_DMAReceptionCmd + 0x0800268c 0x28 THUMB Debug/../../obj/stm32_eth.o + 0x0800268c ETH_DMAReceptionCmd + .text.ETH_Start + 0x080026b4 0x28 THUMB Debug/../../obj/stm32_eth.o + 0x080026b4 ETH_Start + .text.netdev_init + 0x080026dc 0x294 THUMB Debug/../../obj/netdev.o + 0x080026dc netdev_init + .text.netdev_init_mac + 0x08002970 0x30 THUMB Debug/../../obj/netdev.o + 0x08002970 netdev_init_mac + .text.netdev_read + 0x080029a0 0x5c THUMB Debug/../../obj/netdev.o + 0x080029a0 netdev_read + .text.netdev_send + 0x080029fc 0x70 THUMB Debug/../../obj/netdev.o + 0x080029fc netdev_send .text.FileIsFirmwareUpdateRequestedHook - 0x08002110 0x48 THUMB Debug/../../obj/hooks.o - 0x08002110 FileIsFirmwareUpdateRequestedHook + 0x08002a6c 0x48 THUMB Debug/../../obj/hooks.o + 0x08002a6c FileIsFirmwareUpdateRequestedHook .text.FileGetFirmwareFilenameHook - 0x08002158 0xc THUMB Debug/../../obj/hooks.o - 0x08002158 FileGetFirmwareFilenameHook + 0x08002ab4 0xc THUMB Debug/../../obj/hooks.o + 0x08002ab4 FileGetFirmwareFilenameHook .text.FileFirmwareUpdateStartedHook - 0x08002164 0x38 THUMB Debug/../../obj/hooks.o - 0x08002164 FileFirmwareUpdateStartedHook + 0x08002ac0 0x38 THUMB Debug/../../obj/hooks.o + 0x08002ac0 FileFirmwareUpdateStartedHook .text.FileFirmwareUpdateCompletedHook - 0x0800219c 0x44 THUMB Debug/../../obj/hooks.o - 0x0800219c FileFirmwareUpdateCompletedHook + 0x08002af8 0x44 THUMB Debug/../../obj/hooks.o + 0x08002af8 FileFirmwareUpdateCompletedHook .text.FileFirmwareUpdateErrorHook - 0x080021e0 0x20 THUMB Debug/../../obj/hooks.o - 0x080021e0 FileFirmwareUpdateErrorHook + 0x08002b3c 0x20 THUMB Debug/../../obj/hooks.o + 0x08002b3c FileFirmwareUpdateErrorHook .text.FileFirmwareUpdateLogHook - 0x08002200 0x68 THUMB Debug/../../obj/hooks.o - 0x08002200 FileFirmwareUpdateLogHook - .text.main 0x08002268 0xe0 THUMB Debug/../../obj/main.o - 0x08002268 main + 0x08002b5c 0x68 THUMB Debug/../../obj/hooks.o + 0x08002b5c FileFirmwareUpdateLogHook + .text.main 0x08002bc4 0xe0 THUMB Debug/../../obj/main.o + 0x08002bc4 main .text.UnusedISR - 0x08002348 0x14 THUMB Debug/../../obj/vectors.o - 0x08002348 UnusedISR + 0x08002ca4 0x14 THUMB Debug/../../obj/vectors.o + 0x08002ca4 UnusedISR .text.CpuStartUserProgram - 0x0800235c 0x2c THUMB Debug/../../obj/cpu.o - 0x0800235c CpuStartUserProgram + 0x08002cb8 0x30 THUMB Debug/../../obj/cpu.o + 0x08002cb8 CpuStartUserProgram .text.CpuMemCopy - 0x08002388 0x60 THUMB Debug/../../obj/cpu.o - 0x08002388 CpuMemCopy + 0x08002ce8 0x60 THUMB Debug/../../obj/cpu.o + 0x08002ce8 CpuMemCopy .text.CpuReset - 0x080023e8 0x8 THUMB Debug/../../obj/cpu.o - 0x080023e8 CpuReset + 0x08002d48 0x8 THUMB Debug/../../obj/cpu.o + 0x08002d48 CpuReset .text.FlashGetSector - 0x080023f0 0x170 THUMB Debug/../../obj/flash.o + 0x08002d50 0x150 THUMB Debug/../../obj/flash.o .text.FlashWriteBlock - 0x08002560 0xa4 THUMB Debug/../../obj/flash.o + 0x08002ea0 0xa4 THUMB Debug/../../obj/flash.o .text.FlashInitBlock - 0x08002604 0x30 THUMB Debug/../../obj/flash.o + 0x08002f44 0x30 THUMB Debug/../../obj/flash.o .text.FlashSwitchBlock - 0x08002634 0x54 THUMB Debug/../../obj/flash.o + 0x08002f74 0x54 THUMB Debug/../../obj/flash.o .text.FlashAddToBlock - 0x08002688 0x130 THUMB Debug/../../obj/flash.o + 0x08002fc8 0x130 THUMB Debug/../../obj/flash.o .text.FlashInit - 0x080027b8 0x1c THUMB Debug/../../obj/flash.o - 0x080027b8 FlashInit + 0x080030f8 0x1c THUMB Debug/../../obj/flash.o + 0x080030f8 FlashInit .text.FlashWrite - 0x080027d4 0x64 THUMB Debug/../../obj/flash.o - 0x080027d4 FlashWrite + 0x08003114 0x64 THUMB Debug/../../obj/flash.o + 0x08003114 FlashWrite .text.FlashErase - 0x08002838 0x120 THUMB Debug/../../obj/flash.o - 0x08002838 FlashErase + 0x08003178 0x120 THUMB Debug/../../obj/flash.o + 0x08003178 FlashErase .text.FlashWriteChecksum - 0x08002958 0x5c THUMB Debug/../../obj/flash.o - 0x08002958 FlashWriteChecksum + 0x08003298 0x5c THUMB Debug/../../obj/flash.o + 0x08003298 FlashWriteChecksum .text.FlashVerifyChecksum - 0x080029b4 0x68 THUMB Debug/../../obj/flash.o - 0x080029b4 FlashVerifyChecksum + 0x080032f4 0x68 THUMB Debug/../../obj/flash.o + 0x080032f4 FlashVerifyChecksum .text.FlashDone - 0x08002a1c 0x50 THUMB Debug/../../obj/flash.o - 0x08002a1c FlashDone - .text.NvmInit 0x08002a6c 0x8 THUMB Debug/../../obj/nvm.o - 0x08002a6c NvmInit + 0x0800335c 0x50 THUMB Debug/../../obj/flash.o + 0x0800335c FlashDone + .text.FlashGetUserProgBaseAddress + 0x080033ac 0xc THUMB Debug/../../obj/flash.o + 0x080033ac FlashGetUserProgBaseAddress + .text.NvmInit 0x080033b8 0x8 THUMB Debug/../../obj/nvm.o + 0x080033b8 NvmInit .text.NvmWrite - 0x08002a74 0x8 THUMB Debug/../../obj/nvm.o - 0x08002a74 NvmWrite + 0x080033c0 0x8 THUMB Debug/../../obj/nvm.o + 0x080033c0 NvmWrite .text.NvmErase - 0x08002a7c 0x8 THUMB Debug/../../obj/nvm.o - 0x08002a7c NvmErase + 0x080033c8 0x8 THUMB Debug/../../obj/nvm.o + 0x080033c8 NvmErase .text.NvmVerifyChecksum - 0x08002a84 0x8 THUMB Debug/../../obj/nvm.o - 0x08002a84 NvmVerifyChecksum - .text.NvmDone 0x08002a8c 0x14 THUMB Debug/../../obj/nvm.o - 0x08002a8c NvmDone + 0x080033d0 0x8 THUMB Debug/../../obj/nvm.o + 0x080033d0 NvmVerifyChecksum + .text.NvmDone 0x080033d8 0x14 THUMB Debug/../../obj/nvm.o + 0x080033d8 NvmDone .text.TimerReset - 0x08002aa0 0x10 THUMB Debug/../../obj/timer.o - 0x08002aa0 TimerReset + 0x080033ec 0x10 THUMB Debug/../../obj/timer.o + 0x080033ec TimerReset .text.TimerInit - 0x08002ab0 0x30 THUMB Debug/../../obj/timer.o - 0x08002ab0 TimerInit + 0x080033fc 0x30 THUMB Debug/../../obj/timer.o + 0x080033fc TimerInit .text.TimerUpdate - 0x08002ae0 0x24 THUMB Debug/../../obj/timer.o - 0x08002ae0 TimerUpdate + 0x0800342c 0x24 THUMB Debug/../../obj/timer.o + 0x0800342c TimerUpdate .text.TimerGet - 0x08002b04 0x14 THUMB Debug/../../obj/timer.o - 0x08002b04 TimerGet + 0x08003450 0x14 THUMB Debug/../../obj/timer.o + 0x08003450 TimerGet .text.UartReceiveByte - 0x08002b18 0x34 THUMB Debug/../../obj/uart.o + 0x08003464 0x34 THUMB Debug/../../obj/uart.o .text.UartTransmitByte - 0x08002b4c 0x48 THUMB Debug/../../obj/uart.o + 0x08003498 0x48 THUMB Debug/../../obj/uart.o .text.UartInit - 0x08002b94 0x44 THUMB Debug/../../obj/uart.o - 0x08002b94 UartInit + 0x080034e0 0x44 THUMB Debug/../../obj/uart.o + 0x080034e0 UartInit .text.UartTransmitPacket - 0x08002bd8 0xe4 THUMB Debug/../../obj/uart.o - 0x08002bd8 UartTransmitPacket + 0x08003524 0xe4 THUMB Debug/../../obj/uart.o + 0x08003524 UartTransmitPacket .text.UartReceivePacket - 0x08002cbc 0xb0 THUMB Debug/../../obj/uart.o - 0x08002cbc UartReceivePacket - .text.CanInit 0x08002d6c 0x1b4 THUMB Debug/../../obj/can.o - 0x08002d6c CanInit + 0x08003608 0xb0 THUMB Debug/../../obj/uart.o + 0x08003608 UartReceivePacket + .text.CanInit 0x080036b8 0x1b4 THUMB Debug/../../obj/can.o + 0x080036b8 CanInit .text.CanTransmitPacket - 0x08002f20 0xac THUMB Debug/../../obj/can.o - 0x08002f20 CanTransmitPacket + 0x0800386c 0xac THUMB Debug/../../obj/can.o + 0x0800386c CanTransmitPacket .text.CanReceivePacket - 0x08002fcc 0x98 THUMB Debug/../../obj/can.o - 0x08002fcc CanReceivePacket + 0x08003918 0x98 THUMB Debug/../../obj/can.o + 0x08003918 CanReceivePacket .text.AssertFailure - 0x08003064 0x1c THUMB Debug/../../obj/assert.o - 0x08003064 AssertFailure + 0x080039b0 0x1c THUMB Debug/../../obj/assert.o + 0x080039b0 AssertFailure .text.BackDoorCheck - 0x08003080 0x50 THUMB Debug/../../obj/backdoor.o - 0x08003080 BackDoorCheck + 0x080039cc 0x54 THUMB Debug/../../obj/backdoor.o + 0x080039cc BackDoorCheck .text.BackDoorInit - 0x080030d0 0x24 THUMB Debug/../../obj/backdoor.o - 0x080030d0 BackDoorInit + 0x08003a20 0x24 THUMB Debug/../../obj/backdoor.o + 0x08003a20 BackDoorInit .text.BootInit - 0x080030f4 0x1c THUMB Debug/../../obj/boot.o - 0x080030f4 BootInit + 0x08003a44 0x1c THUMB Debug/../../obj/boot.o + 0x08003a44 BootInit .text.BootTask - 0x08003110 0x18 THUMB Debug/../../obj/boot.o - 0x08003110 BootTask - .text.ComInit 0x08003128 0x48 THUMB Debug/../../obj/com.o - 0x08003128 ComInit - .text.ComTask 0x08003170 0x58 THUMB Debug/../../obj/com.o - 0x08003170 ComTask - .text.ComFree 0x080031c8 0x4 THUMB Debug/../../obj/com.o - 0x080031c8 ComFree + 0x08003a60 0x18 THUMB Debug/../../obj/boot.o + 0x08003a60 BootTask + .text.ComInit 0x08003a78 0x54 THUMB Debug/../../obj/com.o + 0x08003a78 ComInit + .text.ComTask 0x08003acc 0x84 THUMB Debug/../../obj/com.o + 0x08003acc ComTask + .text.ComFree 0x08003b50 0x4 THUMB Debug/../../obj/com.o + 0x08003b50 ComFree .text.ComTransmitPacket - 0x080031cc 0x38 THUMB Debug/../../obj/com.o - 0x080031cc ComTransmitPacket + 0x08003b54 0x4c THUMB Debug/../../obj/com.o + 0x08003b54 ComTransmitPacket .text.ComGetActiveInterfaceMaxRxLen - 0x08003204 0x28 THUMB Debug/../../obj/com.o - 0x08003204 ComGetActiveInterfaceMaxRxLen + 0x08003ba0 0x20 THUMB Debug/../../obj/com.o + 0x08003ba0 ComGetActiveInterfaceMaxRxLen .text.ComGetActiveInterfaceMaxTxLen - 0x0800322c 0x28 THUMB Debug/../../obj/com.o - 0x0800322c ComGetActiveInterfaceMaxTxLen + 0x08003bc0 0x20 THUMB Debug/../../obj/com.o + 0x08003bc0 ComGetActiveInterfaceMaxTxLen .text.ComSetConnectEntryState - 0x08003254 0x10 THUMB Debug/../../obj/com.o - 0x08003254 ComSetConnectEntryState + 0x08003be0 0x10 THUMB Debug/../../obj/com.o + 0x08003be0 ComSetConnectEntryState .text.ComIsConnected - 0x08003264 0x8 THUMB Debug/../../obj/com.o - 0x08003264 ComIsConnected - .text.CopInit 0x0800326c 0x4 THUMB Debug/../../obj/cop.o - 0x0800326c CopInit + 0x08003bf0 0x8 THUMB Debug/../../obj/com.o + 0x08003bf0 ComIsConnected + .text.CopInit 0x08003bf8 0x4 THUMB Debug/../../obj/cop.o + 0x08003bf8 CopInit .text.CopService - 0x08003270 0x4 THUMB Debug/../../obj/cop.o - 0x08003270 CopService + 0x08003bfc 0x4 THUMB Debug/../../obj/cop.o + 0x08003bfc CopService .text.XcpProtectResources - 0x08003274 0x10 THUMB Debug/../../obj/xcp.o + 0x08003c00 0x10 THUMB Debug/../../obj/xcp.o .text.XcpSetCtoError - 0x08003284 0x1c THUMB Debug/../../obj/xcp.o - .text.XcpInit 0x080032a0 0x20 THUMB Debug/../../obj/xcp.o - 0x080032a0 XcpInit + 0x08003c10 0x1c THUMB Debug/../../obj/xcp.o + .text.XcpInit 0x08003c2c 0x20 THUMB Debug/../../obj/xcp.o + 0x08003c2c XcpInit .text.XcpIsConnected - 0x080032c0 0x14 THUMB Debug/../../obj/xcp.o - 0x080032c0 XcpIsConnected + 0x08003c4c 0x14 THUMB Debug/../../obj/xcp.o + 0x08003c4c XcpIsConnected .text.XcpPacketTransmitted - 0x080032d4 0x14 THUMB Debug/../../obj/xcp.o - 0x080032d4 XcpPacketTransmitted + 0x08003c60 0x14 THUMB Debug/../../obj/xcp.o + 0x08003c60 XcpPacketTransmitted .text.XcpPacketReceived - 0x080032e8 0x438 THUMB Debug/../../obj/xcp.o - 0x080032e8 XcpPacketReceived + 0x08003c74 0x438 THUMB Debug/../../obj/xcp.o + 0x08003c74 XcpPacketReceived .text.FileLibLongToIntString - 0x08003720 0x50 THUMB Debug/../../obj/file.o + 0x080040ac 0x50 THUMB Debug/../../obj/file.o .text.FileLibHexStringToByte - 0x08003770 0x70 THUMB Debug/../../obj/file.o + 0x080040fc 0x70 THUMB Debug/../../obj/file.o .text.FileLibByteNibbleToChar - 0x080037e0 0x1c THUMB Debug/../../obj/file.o + 0x0800416c 0x1c THUMB Debug/../../obj/file.o .text.FileLibByteToHexString - 0x080037fc 0x24 THUMB Debug/../../obj/file.o + 0x08004188 0x24 THUMB Debug/../../obj/file.o .text.FileInit - 0x08003820 0x30 THUMB Debug/../../obj/file.o - 0x08003820 FileInit + 0x080041ac 0x30 THUMB Debug/../../obj/file.o + 0x080041ac FileInit .text.FileIsIdle - 0x08003850 0x14 THUMB Debug/../../obj/file.o - 0x08003850 FileIsIdle + 0x080041dc 0x14 THUMB Debug/../../obj/file.o + 0x080041dc FileIsIdle .text.FileHandleFirmwareUpdateRequest - 0x08003864 0x3c THUMB Debug/../../obj/file.o - 0x08003864 FileHandleFirmwareUpdateRequest + 0x080041f0 0x3c THUMB Debug/../../obj/file.o + 0x080041f0 FileHandleFirmwareUpdateRequest .text.FileSrecGetLineType - 0x080038a0 0x44 THUMB Debug/../../obj/file.o - 0x080038a0 FileSrecGetLineType + 0x0800422c 0x44 THUMB Debug/../../obj/file.o + 0x0800422c FileSrecGetLineType .text.FileSrecVerifyChecksum - 0x080038e4 0x94 THUMB Debug/../../obj/file.o - 0x080038e4 FileSrecVerifyChecksum + 0x08004270 0x94 THUMB Debug/../../obj/file.o + 0x08004270 FileSrecVerifyChecksum .text.FileSrecParseLine - 0x08003978 0x1a4 THUMB Debug/../../obj/file.o - 0x08003978 FileSrecParseLine + 0x08004304 0x1a4 THUMB Debug/../../obj/file.o + 0x08004304 FileSrecParseLine .text.FileTask - 0x08003b1c 0x4b4 THUMB Debug/../../obj/file.o - 0x08003b1c FileTask - .text.mem_cpy 0x08003fd0 0x54 THUMB Debug/../../obj/ff.o - .text.mem_set 0x08004024 0x38 THUMB Debug/../../obj/ff.o - .text.chk_chr 0x0800405c 0x18 THUMB Debug/../../obj/ff.o + 0x080044a8 0x4b4 THUMB Debug/../../obj/file.o + 0x080044a8 FileTask + .text.mem_cpy 0x0800495c 0x54 THUMB Debug/../../obj/ff.o + .text.mem_set 0x080049b0 0x38 THUMB Debug/../../obj/ff.o + .text.chk_chr 0x080049e8 0x18 THUMB Debug/../../obj/ff.o .text.ld_clust - 0x08004074 0x20 THUMB Debug/../../obj/ff.o + 0x08004a00 0x20 THUMB Debug/../../obj/ff.o .text.st_clust - 0x08004094 0x18 THUMB Debug/../../obj/ff.o - .text.sum_sfn 0x080040ac 0xa4 THUMB Debug/../../obj/ff.o + 0x08004a20 0x18 THUMB Debug/../../obj/ff.o + .text.sum_sfn 0x08004a38 0xa4 THUMB Debug/../../obj/ff.o .text.validate - 0x08004150 0x44 THUMB Debug/../../obj/ff.o + 0x08004adc 0x44 THUMB Debug/../../obj/ff.o .text.check_fs - 0x08004194 0xa8 THUMB Debug/../../obj/ff.o + 0x08004b20 0xa8 THUMB Debug/../../obj/ff.o .text.chk_mounted - 0x0800423c 0x400 THUMB Debug/../../obj/ff.o + 0x08004bc8 0x400 THUMB Debug/../../obj/ff.o .text.get_fileinfo - 0x0800463c 0x248 THUMB Debug/../../obj/ff.o + 0x08004fc8 0x248 THUMB Debug/../../obj/ff.o .text.sync_window - 0x08004884 0xd8 THUMB Debug/../../obj/ff.o + 0x08005210 0xd8 THUMB Debug/../../obj/ff.o .text.move_window - 0x0800495c 0x3c THUMB Debug/../../obj/ff.o - .text.sync_fs 0x08004998 0xd4 THUMB Debug/../../obj/ff.o + 0x080052e8 0x3c THUMB Debug/../../obj/ff.o + .text.sync_fs 0x08005324 0xd4 THUMB Debug/../../obj/ff.o .text.clust2sect - 0x08004a6c 0x20 THUMB Debug/../../obj/ff.o - 0x08004a6c clust2sect - .text.get_fat 0x08004a8c 0x110 THUMB Debug/../../obj/ff.o - 0x08004a8c get_fat - .text.dir_sdi 0x08004b9c 0xac THUMB Debug/../../obj/ff.o - .text.put_fat 0x08004c48 0x134 THUMB Debug/../../obj/ff.o - 0x08004c48 put_fat + 0x080053f8 0x20 THUMB Debug/../../obj/ff.o + 0x080053f8 clust2sect + .text.get_fat 0x08005418 0x110 THUMB Debug/../../obj/ff.o + 0x08005418 get_fat + .text.dir_sdi 0x08005528 0xac THUMB Debug/../../obj/ff.o + .text.put_fat 0x080055d4 0x134 THUMB Debug/../../obj/ff.o + 0x080055d4 put_fat .text.create_chain - 0x08004d7c 0xc8 THUMB Debug/../../obj/ff.o + 0x08005708 0xc8 THUMB Debug/../../obj/ff.o .text.dir_next - 0x08004e44 0x150 THUMB Debug/../../obj/ff.o + 0x080057d0 0x150 THUMB Debug/../../obj/ff.o .text.dir_find - 0x08004f94 0x478 THUMB Debug/../../obj/ff.o + 0x08005920 0x478 THUMB Debug/../../obj/ff.o .text.follow_path - 0x0800540c 0x408 THUMB Debug/../../obj/ff.o + 0x08005d98 0x408 THUMB Debug/../../obj/ff.o .text.dir_remove - 0x08005814 0x5c THUMB Debug/../../obj/ff.o + 0x080061a0 0x5c THUMB Debug/../../obj/ff.o .text.dir_read - 0x08005870 0x2c4 THUMB Debug/../../obj/ff.o + 0x080061fc 0x2c4 THUMB Debug/../../obj/ff.o .text.remove_chain - 0x08005b34 0x7c THUMB Debug/../../obj/ff.o + 0x080064c0 0x7c THUMB Debug/../../obj/ff.o .text.gen_numname - 0x08005bb0 0x140 THUMB Debug/../../obj/ff.o - 0x08005bb0 gen_numname + 0x0800653c 0x140 THUMB Debug/../../obj/ff.o + 0x0800653c gen_numname .text.dir_register - 0x08005cf0 0x298 THUMB Debug/../../obj/ff.o - .text.f_mount 0x08005f88 0x34 THUMB Debug/../../obj/ff.o - 0x08005f88 f_mount - .text.f_open 0x08005fbc 0x1a4 THUMB Debug/../../obj/ff.o - 0x08005fbc f_open - .text.f_read 0x08006160 0x1c8 THUMB Debug/../../obj/ff.o - 0x08006160 f_read - .text.f_write 0x08006328 0x204 THUMB Debug/../../obj/ff.o - 0x08006328 f_write - .text.f_sync 0x0800652c 0xb4 THUMB Debug/../../obj/ff.o - 0x0800652c f_sync - .text.f_close 0x080065e0 0x18 THUMB Debug/../../obj/ff.o - 0x080065e0 f_close - .text.f_lseek 0x080065f8 0x1bc THUMB Debug/../../obj/ff.o - 0x080065f8 f_lseek - .text.f_stat 0x080067b4 0x50 THUMB Debug/../../obj/ff.o - 0x080067b4 f_stat + 0x0800667c 0x298 THUMB Debug/../../obj/ff.o + .text.f_mount 0x08006914 0x34 THUMB Debug/../../obj/ff.o + 0x08006914 f_mount + .text.f_open 0x08006948 0x1a4 THUMB Debug/../../obj/ff.o + 0x08006948 f_open + .text.f_read 0x08006aec 0x1c8 THUMB Debug/../../obj/ff.o + 0x08006aec f_read + .text.f_write 0x08006cb4 0x204 THUMB Debug/../../obj/ff.o + 0x08006cb4 f_write + .text.f_sync 0x08006eb8 0xb4 THUMB Debug/../../obj/ff.o + 0x08006eb8 f_sync + .text.f_close 0x08006f6c 0x18 THUMB Debug/../../obj/ff.o + 0x08006f6c f_close + .text.f_lseek 0x08006f84 0x1bc THUMB Debug/../../obj/ff.o + 0x08006f84 f_lseek + .text.f_stat 0x08007140 0x50 THUMB Debug/../../obj/ff.o + 0x08007140 f_stat .text.f_unlink - 0x08006804 0xd4 THUMB Debug/../../obj/ff.o - 0x08006804 f_unlink - .text.f_gets 0x080068d8 0x60 THUMB Debug/../../obj/ff.o - 0x080068d8 f_gets - .text.f_putc 0x08006938 0x38 THUMB Debug/../../obj/ff.o - 0x08006938 f_putc - .text.f_puts 0x08006970 0x38 THUMB Debug/../../obj/ff.o - 0x08006970 f_puts + 0x08007190 0xd4 THUMB Debug/../../obj/ff.o + 0x08007190 f_unlink + .text.f_gets 0x08007264 0x60 THUMB Debug/../../obj/ff.o + 0x08007264 f_gets + .text.f_putc 0x080072c4 0x38 THUMB Debug/../../obj/ff.o + 0x080072c4 f_putc + .text.f_puts 0x080072fc 0x38 THUMB Debug/../../obj/ff.o + 0x080072fc f_puts .text.ff_convert - 0x080069a8 0x78 THUMB Debug/../../obj/unicode.o - 0x080069a8 ff_convert + 0x08007334 0x78 THUMB Debug/../../obj/unicode.o + 0x08007334 ff_convert .text.ff_wtoupper - 0x08006a20 0x34 THUMB Debug/../../obj/unicode.o - 0x08006a20 ff_wtoupper + 0x080073ac 0x34 THUMB Debug/../../obj/unicode.o + 0x080073ac ff_wtoupper + .text.chksum 0x080073e0 0xc8 THUMB Debug/../../obj/uip.o + .text.uip_add32 + 0x080074a8 0x7c THUMB Debug/../../obj/uip.o + 0x080074a8 uip_add32 + .text.uip_add_rcv_nxt + 0x08007524 0x30 THUMB Debug/../../obj/uip.o + .text.uip_init + 0x08007554 0x38 THUMB Debug/../../obj/uip.o + 0x08007554 uip_init + .text.uip_listen + 0x0800758c 0x38 THUMB Debug/../../obj/uip.o + 0x0800758c uip_listen + .text.htons 0x080075c4 0xc THUMB Debug/../../obj/uip.o + 0x080075c4 htons + .text.upper_layer_chksum + 0x080075d0 0x40 THUMB Debug/../../obj/uip.o + .text.uip_tcpchksum + 0x08007610 0xc THUMB Debug/../../obj/uip.o + 0x08007610 uip_tcpchksum + .text.uip_ipchksum + 0x0800761c 0x24 THUMB Debug/../../obj/uip.o + 0x0800761c uip_ipchksum + .text.uip_process + 0x08007640 0xd28 THUMB Debug/../../obj/uip.o + 0x08007640 uip_process + .text.uip_send + 0x08008368 0x2c THUMB Debug/../../obj/uip.o + 0x08008368 uip_send + .text.uip_arp_update + 0x08008394 0x40c THUMB Debug/../../obj/uip_arp.o + .text.uip_arp_timer + 0x080087a0 0x74 THUMB Debug/../../obj/uip_arp.o + 0x080087a0 uip_arp_timer + .text.uip_arp_arpin + 0x08008814 0x14c THUMB Debug/../../obj/uip_arp.o + 0x08008814 uip_arp_arpin + .text.uip_arp_out + 0x08008960 0x314 THUMB Debug/../../obj/uip_arp.o + 0x08008960 uip_arp_out + .text.NetInit 0x08008c74 0x78 THUMB Debug/../../obj/net.o + 0x08008c74 NetInit + .text.NetTransmitPacket + 0x08008cec 0x80 THUMB Debug/../../obj/net.o + 0x08008cec NetTransmitPacket + .text.NetReceivePacket + 0x08008d6c 0x118 THUMB Debug/../../obj/net.o + 0x08008d6c NetReceivePacket + .text.NetApp 0x08008e84 0x80 THUMB Debug/../../obj/net.o + 0x08008e84 NetApp .text.libc.isdigit - 0x08006a54 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) - 0x08006a54 isdigit + 0x08008f04 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) + 0x08008f04 isdigit .text.libc.toupper - 0x08006a64 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) - 0x08006a64 toupper + 0x08008f14 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) + 0x08008f14 toupper .text.libc.memcpy - 0x08006a74 0x48 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) - 0x08006a74 __aeabi_memcpy - 0x08006a74 __aeabi_memcpy4 - 0x08006a74 __aeabi_memcpy8 - 0x08006a74 memcpy + 0x08008f24 0x48 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + 0x08008f24 __aeabi_memcpy + 0x08008f24 __aeabi_memcpy4 + 0x08008f24 __aeabi_memcpy8 + 0x08008f24 memcpy + .text.libc.memset + 0x08008f6c 0x70 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + 0x08008f6c memset .text.libdebugio.__do_debug_operation_mempoll - 0x08006abc 0x3c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - 0x08006abc __do_debug_operation_mempoll + 0x08008fdc 0x3c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + 0x08008fdc __do_debug_operation_mempoll .text.libc.__debug_io_lock - 0x08006af8 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) - 0x08006af8 __debug_io_lock + 0x08009018 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + 0x08009018 __debug_io_lock .text.libc.__debug_io_unlock - 0x08006afc 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) - 0x08006afc __debug_io_unlock - 0x08006b00 __text_end__ = (__text_start__ + SIZEOF (.text)) - 0x08006b00 __text_load_end__ = __text_end__ + 0x0800901c 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + 0x0800901c __debug_io_unlock + 0x08009020 __text_end__ = (__text_start__ + SIZEOF (.text)) + 0x08009020 __text_load_end__ = __text_end__ .vfp11_veneer 0x00000000 0x0 .vfp11_veneer 0x00000000 0x0 linker stubs @@ -3004,92 +3393,98 @@ Linker script and memory map .iplt 0x00000000 0x0 .iplt 0x00000000 0x0 THUMB Debug/../../obj/mmc.o 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= __FLASH_segment_end__)), error: .text is too large to fit in FLASH memory segment) - 0x08006b00 __dtors_load_start__ = ALIGN (__text_end__, 0x4) + 0x08009020 __dtors_load_start__ = ALIGN (__text_end__, 0x4) -.dtors 0x08006b00 0x0 - 0x08006b00 __dtors_start__ = . +.dtors 0x08009020 0x0 + 0x08009020 __dtors_start__ = . *(SORT(.dtors.*)) *(.dtors) *(.fini_array .fini_array.*) - 0x08006b00 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors)) - 0x08006b00 __dtors_load_end__ = __dtors_end__ + 0x08009020 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors)) + 0x08009020 __dtors_load_end__ = __dtors_end__ 0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= __FLASH_segment_end__)), error: .dtors is too large to fit in FLASH memory segment) - 0x08006b00 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4) + 0x08009020 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4) -.ctors 0x08006b00 0x0 - 0x08006b00 __ctors_start__ = . +.ctors 0x08009020 0x0 + 0x08009020 __ctors_start__ = . *(SORT(.ctors.*)) *(.ctors) *(.init_array .init_array.*) - 0x08006b00 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors)) - 0x08006b00 __ctors_load_end__ = __ctors_end__ + 0x08009020 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors)) + 0x08009020 __ctors_load_end__ = __ctors_end__ 0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= __FLASH_segment_end__)), error: .ctors is too large to fit in FLASH memory segment) - 0x08006b00 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4) + 0x08009020 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4) -.rodata 0x08006b00 0xa10 - 0x08006b00 __rodata_start__ = . +.rodata 0x08009020 0xa78 + 0x08009020 __rodata_start__ = . *(.rodata .rodata.* .gnu.linkonce.r.*) + .rodata.str1.4 + 0x08009020 0x6b THUMB Debug/../../obj/netdev.o + 0x6c (size before relaxing) + *fill* 0x0800908b 0x1 00 .rodata.firmwareFilename - 0x08006b00 0x20 THUMB Debug/../../obj/hooks.o + 0x0800908c 0x20 THUMB Debug/../../obj/hooks.o .rodata.str1.4 - 0x08006b20 0xd THUMB Debug/../../obj/hooks.o + 0x080090ac 0xd THUMB Debug/../../obj/hooks.o 0x10 (size before relaxing) - *fill* 0x08006b2d 0x3 00 + *fill* 0x080090b9 0x3 00 .rodata.str1.4 - 0x08006b30 0x8c THUMB Debug/../../obj/vectors.o + 0x080090bc 0x8c THUMB Debug/../../obj/vectors.o .rodata.flashSectorNumToMask - 0x08006bbc 0x30 THUMB Debug/../../obj/flash.o + 0x08009148 0x30 THUMB Debug/../../obj/flash.o .rodata.flashLayout - 0x08006bec 0x78 THUMB Debug/../../obj/flash.o + 0x08009178 0x6c THUMB Debug/../../obj/flash.o .rodata.str1.4 - 0x08006c64 0x7e THUMB Debug/../../obj/uart.o + 0x080091e4 0x7e THUMB Debug/../../obj/uart.o 0x80 (size before relaxing) - *fill* 0x08006ce2 0x2 00 + *fill* 0x08009262 0x2 00 .rodata.str1.4 - 0x08006ce4 0x7d THUMB Debug/../../obj/can.o + 0x08009264 0x7d THUMB Debug/../../obj/can.o 0x80 (size before relaxing) - *fill* 0x08006d61 0x3 00 + *fill* 0x080092e1 0x3 00 .rodata.canTiming - 0x08006d64 0x24 THUMB Debug/../../obj/can.o + 0x080092e4 0x24 THUMB Debug/../../obj/can.o .rodata.xcpStationId - 0x08006d88 0x8 THUMB Debug/../../obj/xcp.o + 0x08009308 0x8 THUMB Debug/../../obj/xcp.o .rodata.str1.4 - 0x08006d90 0x219 THUMB Debug/../../obj/file.o + 0x08009310 0x219 THUMB Debug/../../obj/file.o 0x220 (size before relaxing) - *fill* 0x08006fa9 0x3 00 + *fill* 0x08009529 0x3 00 .rodata.str1.4 - 0x08006fac 0x14 THUMB Debug/../../obj/ff.o - .rodata.ExCvt 0x08006fc0 0x80 THUMB Debug/../../obj/ff.o + 0x0800952c 0x14 THUMB Debug/../../obj/ff.o + .rodata.ExCvt 0x08009540 0x80 THUMB Debug/../../obj/ff.o .rodata.LfnOfs - 0x08007040 0x10 THUMB Debug/../../obj/ff.o + 0x080095c0 0x10 THUMB Debug/../../obj/ff.o .rodata.tbl_lower.3809 - 0x08007050 0x1e0 THUMB Debug/../../obj/unicode.o - .rodata.Tbl 0x08007230 0x100 THUMB Debug/../../obj/unicode.o + 0x080095d0 0x1e0 THUMB Debug/../../obj/unicode.o + .rodata.Tbl 0x080097b0 0x100 THUMB Debug/../../obj/unicode.o .rodata.tbl_upper.3810 - 0x08007330 0x1e0 THUMB Debug/../../obj/unicode.o - 0x08007510 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata)) - 0x08007510 __rodata_load_end__ = __rodata_end__ + 0x080098b0 0x1e0 THUMB Debug/../../obj/unicode.o + .rodata.broadcast_ethaddr + 0x08009a90 0x8 THUMB Debug/../../obj/uip_arp.o + 0x08009a98 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata)) + 0x08009a98 __rodata_load_end__ = __rodata_end__ .rel.dyn 0x08000000 0x0 .rel.iplt 0x00000000 0x0 THUMB Debug/../../obj/mmc.o 0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= __FLASH_segment_end__)), error: .rodata is too large to fit in FLASH memory segment) - 0x08007510 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4) + 0x08009a98 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4) -.ARM.exidx 0x08007510 0x0 - 0x08007510 __ARM.exidx_start__ = . - 0x08007510 __exidx_start = __ARM.exidx_start__ +.ARM.exidx 0x08009a98 0x0 + 0x08009a98 __ARM.exidx_start__ = . + 0x08009a98 __exidx_start = __ARM.exidx_start__ *(.ARM.exidx .ARM.exidx.*) - 0x08007510 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx)) - 0x08007510 __exidx_end = __ARM.exidx_end__ - 0x08007510 __ARM.exidx_load_end__ = __ARM.exidx_end__ + 0x08009a98 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx)) + 0x08009a98 __exidx_end = __ARM.exidx_end__ + 0x08009a98 __ARM.exidx_load_end__ = __ARM.exidx_end__ 0x00000001 . = ASSERT (((__ARM.exidx_end__ >= __FLASH_segment_start__) && (__ARM.exidx_end__ <= __FLASH_segment_end__)), error: .ARM.exidx is too large to fit in FLASH memory segment) - 0x08007510 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4) + 0x08009a98 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4) -.fast 0x20000000 0x0 load address 0x08007510 +.fast 0x20000000 0x0 load address 0x08009a98 0x20000000 __fast_start__ = . *(.fast .fast.*) 0x20000000 __fast_end__ = (__fast_start__ + SIZEOF (.fast)) - 0x08007510 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast)) + 0x08009a98 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast)) 0x00000001 . = ASSERT (((__fast_load_end__ >= __FLASH_segment_start__) && (__fast_load_end__ <= __FLASH_segment_end__)), error: .fast is too large to fit in FLASH memory segment) .fast_run 0x20000000 0x0 @@ -3098,9 +3493,9 @@ Linker script and memory map 0x20000000 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run)) 0x20000000 __fast_run_load_end__ = __fast_run_end__ 0x00000001 . = ASSERT (((__fast_run_end__ >= __RAM_segment_start__) && (__fast_run_end__ <= __RAM_segment_end__)), error: .fast_run is too large to fit in RAM memory segment) - 0x08007510 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4) + 0x08009a98 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4) -.data 0x20000000 0x19 load address 0x08007510 +.data 0x20000000 0x19 load address 0x08009a98 0x20000000 __data_start__ = . *(.data .data.* .gnu.linkonce.d.*) .data.DMAEndOfTransfer @@ -3112,13 +3507,13 @@ Linker script and memory map .data.comActiveInterface 0x20000018 0x1 THUMB Debug/../../obj/com.o 0x20000019 __data_end__ = (__data_start__ + SIZEOF (.data)) - 0x08007529 __data_load_end__ = (__data_load_start__ + SIZEOF (.data)) + 0x08009ab1 __data_load_end__ = (__data_load_start__ + SIZEOF (.data)) .igot.plt 0x00000000 0x0 .igot.plt 0x00000000 0x0 THUMB Debug/../../obj/mmc.o 0x00000001 . = ASSERT (((__data_load_end__ >= __FLASH_segment_start__) && (__data_load_end__ <= __FLASH_segment_end__)), error: .data is too large to fit in FLASH memory segment) -.data_run 0x20000000 0x19 load address 0x08007510 +.data_run 0x20000000 0x19 load address 0x08009a98 0x20000000 __data_run_start__ = . 0x20000019 . = MAX ((__data_run_start__ + SIZEOF (.data)), .) *fill* 0x20000000 0x19 00 @@ -3127,7 +3522,7 @@ Linker script and memory map 0x00000001 . = ASSERT (((__data_run_end__ >= __RAM_segment_start__) && (__data_run_end__ <= __RAM_segment_end__)), error: .data_run is too large to fit in RAM memory segment) 0x2000001c __bss_load_start__ = ALIGN (__data_run_end__, 0x4) -.bss 0x2000001c 0x1028 +.bss 0x2000001c 0x2558 0x2000001c __bss_start__ = . *(.bss .bss.* .gnu.linkonce.b.*) .bss.TransferError @@ -3150,121 +3545,193 @@ Linker script and memory map 0x200000d8 0x14 THUMB Debug/../../obj/mmc.o .bss.StopCondition 0x200000ec 0x4 THUMB Debug/../../obj/mmc.o - .bss.logfile 0x200000f0 0x228 THUMB Debug/../../obj/hooks.o + *fill* 0x200000f0 0x10 00 + .bss.EnetDmaRx + 0x20000100 0x80 THUMB Debug/../../obj/netdev.o + 0x20000100 EnetDmaRx + .bss.RxBuff 0x20000180 0x640 THUMB Debug/../../obj/netdev.o + 0x20000180 RxBuff + *fill* 0x200007c0 0x40 00 + .bss.EnetDmaTx + 0x20000800 0x80 THUMB Debug/../../obj/netdev.o + 0x20000800 EnetDmaTx + .bss.TxBuff 0x20000880 0x640 THUMB Debug/../../obj/netdev.o + 0x20000880 TxBuff + .bss.logfile 0x20000ec0 0x228 THUMB Debug/../../obj/hooks.o .bss.bootBlockInfo - 0x20000318 0x204 THUMB Debug/../../obj/flash.o + 0x200010e8 0x204 THUMB Debug/../../obj/flash.o .bss.blockInfo - 0x2000051c 0x204 THUMB Debug/../../obj/flash.o + 0x200012ec 0x204 THUMB Debug/../../obj/flash.o .bss.millisecond_counter - 0x20000720 0x4 THUMB Debug/../../obj/timer.o - .bss.xcpCtoReqPacket.7332 - 0x20000724 0x44 THUMB Debug/../../obj/uart.o - .bss.xcpCtoRxInProgress.7334 - 0x20000768 0x1 THUMB Debug/../../obj/uart.o - .bss.xcpCtoRxLength.7333 - 0x20000769 0x1 THUMB Debug/../../obj/uart.o - *fill* 0x2000076a 0x2 00 + 0x200014f0 0x4 THUMB Debug/../../obj/timer.o + .bss.xcpCtoReqPacket.7334 + 0x200014f4 0x44 THUMB Debug/../../obj/uart.o + .bss.xcpCtoRxLength.7335 + 0x20001538 0x1 THUMB Debug/../../obj/uart.o + .bss.xcpCtoRxInProgress.7336 + 0x20001539 0x1 THUMB Debug/../../obj/uart.o + *fill* 0x2000153a 0x2 00 .bss.assert_failure_file - 0x2000076c 0x4 THUMB Debug/../../obj/assert.o + 0x2000153c 0x4 THUMB Debug/../../obj/assert.o .bss.assert_failure_line - 0x20000770 0x4 THUMB Debug/../../obj/assert.o + 0x20001540 0x4 THUMB Debug/../../obj/assert.o .bss.backdoorOpen - 0x20000774 0x1 THUMB Debug/../../obj/backdoor.o - *fill* 0x20000775 0x3 00 + 0x20001544 0x1 THUMB Debug/../../obj/backdoor.o + *fill* 0x20001545 0x3 00 .bss.backdoorOpenTime - 0x20000778 0x4 THUMB Debug/../../obj/backdoor.o + 0x20001548 0x4 THUMB Debug/../../obj/backdoor.o .bss.comEntryStateConnect - 0x2000077c 0x1 THUMB Debug/../../obj/com.o - *fill* 0x2000077d 0x3 00 - .bss.xcpCtoReqPacket.3953 - 0x20000780 0x40 THUMB Debug/../../obj/com.o - .bss.xcpInfo 0x200007c0 0x4c THUMB Debug/../../obj/xcp.o + 0x2000154c 0x1 THUMB Debug/../../obj/com.o + *fill* 0x2000154d 0x3 00 + .bss.xcpCtoReqPacket.3969 + 0x20001550 0x40 THUMB Debug/../../obj/com.o + .bss.xcpInfo 0x20001590 0x4c THUMB Debug/../../obj/xcp.o .bss.loggingStr - 0x2000080c 0x40 THUMB Debug/../../obj/file.o + 0x200015dc 0x40 THUMB Debug/../../obj/file.o .bss.firmwareUpdateState - 0x2000084c 0x1 THUMB Debug/../../obj/file.o - *fill* 0x2000084d 0x3 00 + 0x2000161c 0x1 THUMB Debug/../../obj/file.o + *fill* 0x2000161d 0x3 00 .bss.eraseInfo - 0x20000850 0x8 THUMB Debug/../../obj/file.o + 0x20001620 0x8 THUMB Debug/../../obj/file.o .bss.fatFsObjects - 0x20000858 0x458 THUMB Debug/../../obj/file.o + 0x20001628 0x458 THUMB Debug/../../obj/file.o .bss.lineParseObject - 0x20000cb0 0x184 THUMB Debug/../../obj/file.o - .bss.LfnBuf 0x20000e34 0x200 THUMB Debug/../../obj/ff.o - .bss.Fsid 0x20001034 0x2 THUMB Debug/../../obj/ff.o - *fill* 0x20001036 0x2 00 - .bss.FatFs 0x20001038 0x4 THUMB Debug/../../obj/ff.o + 0x20001a80 0x184 THUMB Debug/../../obj/file.o + .bss.LfnBuf 0x20001c04 0x200 THUMB Debug/../../obj/ff.o + .bss.Fsid 0x20001e04 0x2 THUMB Debug/../../obj/ff.o + *fill* 0x20001e06 0x2 00 + .bss.FatFs 0x20001e08 0x4 THUMB Debug/../../obj/ff.o + .bss.uip_conn 0x20001e0c 0x4 THUMB Debug/../../obj/uip.o + 0x20001e0c uip_conn + .bss.uip_conns + 0x20001e10 0x68 THUMB Debug/../../obj/uip.o + 0x20001e10 uip_conns + .bss.uip_netmask + 0x20001e78 0x4 THUMB Debug/../../obj/uip.o + 0x20001e78 uip_netmask + .bss.uip_len 0x20001e7c 0x2 THUMB Debug/../../obj/uip.o + 0x20001e7c uip_len + .bss.ipid 0x20001e7e 0x2 THUMB Debug/../../obj/uip.o + .bss.uip_draddr + 0x20001e80 0x4 THUMB Debug/../../obj/uip.o + 0x20001e80 uip_draddr + .bss.uip_slen 0x20001e84 0x2 THUMB Debug/../../obj/uip.o + 0x20001e84 uip_slen + *fill* 0x20001e86 0x2 00 + .bss.uip_buf 0x20001e88 0x644 THUMB Debug/../../obj/uip.o + 0x20001e88 uip_buf + .bss.uip_appdata + 0x200024cc 0x4 THUMB Debug/../../obj/uip.o + 0x200024cc uip_appdata + .bss.iss 0x200024d0 0x4 THUMB Debug/../../obj/uip.o + .bss.uip_hostaddr + 0x200024d4 0x4 THUMB Debug/../../obj/uip.o + 0x200024d4 uip_hostaddr + .bss.uip_flags + 0x200024d8 0x1 THUMB Debug/../../obj/uip.o + 0x200024d8 uip_flags + *fill* 0x200024d9 0x3 00 + .bss.uip_acc32 + 0x200024dc 0x4 THUMB Debug/../../obj/uip.o + 0x200024dc uip_acc32 + .bss.lastport 0x200024e0 0x2 THUMB Debug/../../obj/uip.o + .bss.tmp16 0x200024e2 0x2 THUMB Debug/../../obj/uip.o + .bss.uip_ethaddr + 0x200024e4 0x8 THUMB Debug/../../obj/uip.o + 0x200024e4 uip_ethaddr + .bss.c 0x200024ec 0x1 THUMB Debug/../../obj/uip.o + *fill* 0x200024ed 0x3 00 + .bss.uip_listenports + 0x200024f0 0x4 THUMB Debug/../../obj/uip.o + 0x200024f0 uip_listenports + .bss.uip_sappdata + 0x200024f4 0x4 THUMB Debug/../../obj/uip.o + 0x200024f4 uip_sappdata + .bss.opt 0x200024f8 0x1 THUMB Debug/../../obj/uip.o + .bss.i 0x200024f9 0x1 THUMB Debug/../../obj/uip_arp.o + .bss.tmpage 0x200024fa 0x1 THUMB Debug/../../obj/uip_arp.o + *fill* 0x200024fb 0x1 00 + .bss.arp_table + 0x200024fc 0x60 THUMB Debug/../../obj/uip_arp.o + .bss.c 0x2000255c 0x1 THUMB Debug/../../obj/uip_arp.o + .bss.arptime 0x2000255d 0x1 THUMB Debug/../../obj/uip_arp.o + *fill* 0x2000255e 0x2 00 + .bss.ipaddr 0x20002560 0x4 THUMB Debug/../../obj/uip_arp.o + .bss.ARPTimerTimeOut + 0x20002564 0x4 THUMB Debug/../../obj/net.o + .bss.periodicTimerTimeOut + 0x20002568 0x4 THUMB Debug/../../obj/net.o .bss.libdebugio.dbgCommWord - 0x2000103c 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - 0x2000103c dbgCommWord + 0x2000256c 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + 0x2000256c dbgCommWord .bss.libdebugio.dbgCntrlWord_mempoll - 0x20001040 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - 0x20001040 dbgCntrlWord_mempoll + 0x20002570 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + 0x20002570 dbgCntrlWord_mempoll *(COMMON) - 0x20001044 __bss_end__ = (__bss_start__ + SIZEOF (.bss)) - 0x20001044 __bss_load_end__ = __bss_end__ + 0x20002574 __bss_end__ = (__bss_start__ + SIZEOF (.bss)) + 0x20002574 __bss_load_end__ = __bss_end__ 0x00000001 . = ASSERT (((__bss_end__ >= __RAM_segment_start__) && (__bss_end__ <= __RAM_segment_end__)), error: .bss is too large to fit in RAM memory segment) - 0x20001044 __non_init_load_start__ = ALIGN (__bss_end__, 0x4) + 0x20002574 __non_init_load_start__ = ALIGN (__bss_end__, 0x4) -.non_init 0x20001044 0x0 - 0x20001044 __non_init_start__ = . +.non_init 0x20002574 0x0 + 0x20002574 __non_init_start__ = . *(.non_init .non_init.*) - 0x20001044 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init)) - 0x20001044 __non_init_load_end__ = __non_init_end__ + 0x20002574 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init)) + 0x20002574 __non_init_load_end__ = __non_init_end__ 0x00000001 . = ASSERT (((__non_init_end__ >= __RAM_segment_start__) && (__non_init_end__ <= __RAM_segment_end__)), error: .non_init is too large to fit in RAM memory segment) - 0x20001044 __heap_load_start__ = ALIGN (__non_init_end__, 0x4) + 0x20002574 __heap_load_start__ = ALIGN (__non_init_end__, 0x4) -.heap 0x20001044 0x800 - 0x20001044 __heap_start__ = . +.heap 0x20002574 0x800 + 0x20002574 __heap_start__ = . *(.heap .heap.*) - 0x20001844 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4) - *fill* 0x20001044 0x800 00 - 0x20001844 __heap_end__ = (__heap_start__ + SIZEOF (.heap)) - 0x20001844 __heap_load_end__ = __heap_end__ + 0x20002d74 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4) + *fill* 0x20002574 0x800 00 + 0x20002d74 __heap_end__ = (__heap_start__ + SIZEOF (.heap)) + 0x20002d74 __heap_load_end__ = __heap_end__ 0x00000001 . = ASSERT (((__heap_end__ >= __RAM_segment_start__) && (__heap_end__ <= __RAM_segment_end__)), error: .heap is too large to fit in RAM memory segment) - 0x20001844 __stack_load_start__ = ALIGN (__heap_end__, 0x4) + 0x20002d74 __stack_load_start__ = ALIGN (__heap_end__, 0x4) -.stack 0x20001844 0x800 - 0x20001844 __stack_start__ = . +.stack 0x20002d74 0x800 + 0x20002d74 __stack_start__ = . *(.stack .stack.*) - 0x20002044 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4) - *fill* 0x20001844 0x800 00 - 0x20002044 __stack_end__ = (__stack_start__ + SIZEOF (.stack)) - 0x20002044 __stack_load_end__ = __stack_end__ + 0x20003574 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4) + *fill* 0x20002d74 0x800 00 + 0x20003574 __stack_end__ = (__stack_start__ + SIZEOF (.stack)) + 0x20003574 __stack_load_end__ = __stack_end__ 0x00000001 . = ASSERT (((__stack_end__ >= __RAM_segment_start__) && (__stack_end__ <= __RAM_segment_end__)), error: .stack is too large to fit in RAM memory segment) - 0x20002044 __stack_process_load_start__ = ALIGN (__stack_end__, 0x4) + 0x20003574 __stack_process_load_start__ = ALIGN (__stack_end__, 0x4) -.stack_process 0x20002044 0x0 - 0x20002044 __stack_process_start__ = . +.stack_process 0x20003574 0x0 + 0x20003574 __stack_process_start__ = . *(.stack_process .stack_process.*) - 0x20002044 . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4) - 0x20002044 __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process)) - 0x20002044 __stack_process_load_end__ = __stack_process_end__ + 0x20003574 . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4) + 0x20003574 __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process)) + 0x20003574 __stack_process_load_end__ = __stack_process_end__ 0x00000001 . = ASSERT (((__stack_process_end__ >= __RAM_segment_start__) && (__stack_process_end__ <= __RAM_segment_end__)), error: .stack_process is too large to fit in RAM memory segment) - 0x20002044 __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4) + 0x20003574 __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4) -.tbss 0x20002044 0x0 - 0x20002044 __tbss_start__ = . +.tbss 0x20003574 0x0 + 0x20003574 __tbss_start__ = . *(.tbss .tbss.*) - 0x20002044 __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss)) - 0x20002044 __tbss_load_end__ = __tbss_end__ + 0x20003574 __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss)) + 0x20003574 __tbss_load_end__ = __tbss_end__ 0x00000001 . = ASSERT (((__tbss_end__ >= __RAM_segment_start__) && (__tbss_end__ <= __RAM_segment_end__)), error: .tbss is too large to fit in RAM memory segment) - 0x0800752c __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + 0x08009ab4 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) -.tdata 0x20002044 0x0 load address 0x0800752c - 0x20002044 __tdata_start__ = . +.tdata 0x20003574 0x0 load address 0x08009ab4 + 0x20003574 __tdata_start__ = . *(.tdata .tdata.*) - 0x20002044 __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata)) - 0x0800752c __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata)) - 0x0800752c __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata)) + 0x20003574 __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata)) + 0x08009ab4 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata)) + 0x08009ab4 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata)) 0x00000001 . = ASSERT (((__tdata_load_end__ >= __FLASH_segment_start__) && (__tdata_load_end__ <= __FLASH_segment_end__)), error: .tdata is too large to fit in FLASH memory segment) -.tdata_run 0x20002044 0x0 - 0x20002044 __tdata_run_start__ = . - 0x20002044 . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .) - 0x20002044 __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run)) - 0x20002044 __tdata_run_load_end__ = __tdata_run_end__ - 0x20002044 __RAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run)) +.tdata_run 0x20003574 0x0 + 0x20003574 __tdata_run_start__ = . + 0x20003574 . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .) + 0x20003574 __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run)) + 0x20003574 __tdata_run_load_end__ = __tdata_run_end__ + 0x20003574 __RAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run)) 0x00000001 . = ASSERT (((__tdata_run_end__ >= __RAM_segment_start__) && (__tdata_run_end__ <= __RAM_segment_end__)), error: .tdata_run is too large to fit in RAM memory segment) START GROUP LOAD THUMB Debug/../../obj/mmc.o @@ -3300,6 +3767,9 @@ LOAD THUMB Debug/../../obj/stm32f4xx_syscfg.o LOAD THUMB Debug/../../obj/stm32f4xx_tim.o LOAD THUMB Debug/../../obj/stm32f4xx_usart.o LOAD THUMB Debug/../../obj/stm32f4xx_wwdg.o +LOAD THUMB Debug/../../obj/stm32_eth.o +LOAD THUMB Debug/../../obj/clock-arch.o +LOAD THUMB Debug/../../obj/netdev.o LOAD THUMB Debug/../../obj/hooks.o LOAD THUMB Debug/../../obj/main.o LOAD THUMB Debug/../../obj/cstart.o @@ -3319,6 +3789,12 @@ LOAD THUMB Debug/../../obj/xcp.o LOAD THUMB Debug/../../obj/file.o LOAD THUMB Debug/../../obj/ff.o LOAD THUMB Debug/../../obj/unicode.o +LOAD THUMB Debug/../../obj/uip.o +LOAD THUMB Debug/../../obj/uip_arp.o +LOAD THUMB Debug/../../obj/uip_timer.o +LOAD THUMB Debug/../../obj/uip-fw.o +LOAD THUMB Debug/../../obj/uiplib.o +LOAD THUMB Debug/../../obj/net.o LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcm_v7em_t_le_eabi.a LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v7em_t_le_eabi.a LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a @@ -3329,128 +3805,152 @@ LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib END GROUP OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/ide/../bin/openbtl_olimex_stm32e407.elf elf32-littlearm) -.debug_frame 0x00000000 0x3bec +.debug_frame 0x00000000 0x4778 .debug_frame 0x00000000 0x4e0 THUMB Debug/../../obj/mmc.o .debug_frame 0x000004e0 0x38 THUMB Debug/../../obj/system_stm32f4xx.o .debug_frame 0x00000518 0x2c8 THUMB Debug/../../obj/stm32f4xx_flash.o .debug_frame 0x000007e0 0x124 THUMB Debug/../../obj/stm32f4xx_gpio.o .debug_frame 0x00000904 0x30c THUMB Debug/../../obj/stm32f4xx_rcc.o .debug_frame 0x00000c10 0x228 THUMB Debug/../../obj/stm32f4xx_sdio.o - .debug_frame 0x00000e38 0x224 THUMB Debug/../../obj/stm32f4xx_usart.o - .debug_frame 0x0000105c 0xb8 THUMB Debug/../../obj/hooks.o - .debug_frame 0x00001114 0x34 THUMB Debug/../../obj/main.o - .debug_frame 0x00001148 0x2c THUMB Debug/../../obj/vectors.o - .debug_frame 0x00001174 0x6c THUMB Debug/../../obj/cpu.o - .debug_frame 0x000011e0 0x154 THUMB Debug/../../obj/flash.o - .debug_frame 0x00001334 0x9c THUMB Debug/../../obj/nvm.o - .debug_frame 0x000013d0 0x68 THUMB Debug/../../obj/timer.o - .debug_frame 0x00001438 0xb4 THUMB Debug/../../obj/uart.o - .debug_frame 0x000014ec 0x6c THUMB Debug/../../obj/can.o - .debug_frame 0x00001558 0x2c THUMB Debug/../../obj/assert.o - .debug_frame 0x00001584 0x48 THUMB Debug/../../obj/backdoor.o - .debug_frame 0x000015cc 0x48 THUMB Debug/../../obj/boot.o - .debug_frame 0x00001614 0xec THUMB Debug/../../obj/com.o - .debug_frame 0x00001700 0x30 THUMB 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0xd6 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + .debug_info 0x00006311 0x2b7 THUMB Debug/../../obj/stm32f4xx_syscfg.o + .debug_info 0x000065c8 0xc4b THUMB Debug/../../obj/stm32f4xx_usart.o + .debug_info 0x00007213 0x1ffe THUMB Debug/../../obj/stm32_eth.o + .debug_info 0x00009211 0x15cf THUMB Debug/../../obj/netdev.o + .debug_info 0x0000a7e0 0x838 THUMB Debug/../../obj/hooks.o + .debug_info 0x0000b018 0x509 THUMB Debug/../../obj/main.o + .debug_info 0x0000b521 0x10a THUMB Debug/../../obj/cstart.o + .debug_info 0x0000b62b 0x13f THUMB Debug/../../obj/vectors.o + .debug_info 0x0000b76a 0x1fd THUMB Debug/../../obj/cpu.o + .debug_info 0x0000b967 0xa1c THUMB Debug/../../obj/flash.o + .debug_info 0x0000c383 0x252 THUMB Debug/../../obj/nvm.o + .debug_info 0x0000c5d5 0x195 THUMB Debug/../../obj/timer.o + .debug_info 0x0000c76a 0x66d THUMB Debug/../../obj/uart.o + .debug_info 0x0000cdd7 0x581 THUMB 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0x000034aa 0x243 THUMB Debug/../../obj/net.o + .debug_abbrev 0x000036ed 0xcb C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) + .debug_abbrev 0x000037b8 0x3e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_abbrev 0x000037f6 0x28 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) -.debug_loc 0x00000000 0xed86 +.debug_loc 0x00000000 0x1173d .debug_loc 0x00000000 0x2289 THUMB Debug/../../obj/mmc.o .debug_loc 0x00002289 0x1a7 THUMB Debug/../../obj/system_stm32f4xx.o .debug_loc 0x00002430 0x83a THUMB Debug/../../obj/stm32f4xx_flash.o .debug_loc 0x00002c6a 0x445 THUMB Debug/../../obj/stm32f4xx_gpio.o .debug_loc 0x000030af 0xdb0 THUMB Debug/../../obj/stm32f4xx_rcc.o .debug_loc 0x00003e5f 0x2f8 THUMB Debug/../../obj/stm32f4xx_sdio.o - .debug_loc 0x00004157 0xaeb THUMB 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Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) -.debug_aranges 0x00000000 0x13b0 +.debug_aranges 0x00000000 0x1878 .debug_aranges 0x00000000 0x140 THUMB Debug/../../obj/mmc.o .debug_aranges @@ -3464,169 +3964,205 @@ OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossw .debug_aranges 0x00000488 0x108 THUMB Debug/../../obj/stm32f4xx_sdio.o .debug_aranges - 0x00000590 0x100 THUMB Debug/../../obj/stm32f4xx_usart.o + 0x00000590 0x48 THUMB Debug/../../obj/stm32f4xx_syscfg.o .debug_aranges - 0x00000690 0x48 THUMB Debug/../../obj/hooks.o + 0x000005d8 0x100 THUMB Debug/../../obj/stm32f4xx_usart.o .debug_aranges - 0x000006d8 0x20 THUMB Debug/../../obj/main.o + 0x000006d8 0x330 THUMB Debug/../../obj/stm32_eth.o .debug_aranges - 0x000006f8 0x20 THUMB Debug/../../obj/cstart.o + 0x00000a08 0x38 THUMB Debug/../../obj/netdev.o .debug_aranges - 0x00000718 0x20 THUMB Debug/../../obj/vectors.o + 0x00000a40 0x48 THUMB Debug/../../obj/hooks.o .debug_aranges - 0x00000738 0x30 THUMB Debug/../../obj/cpu.o + 0x00000a88 0x20 THUMB Debug/../../obj/main.o .debug_aranges - 0x00000768 0x70 THUMB Debug/../../obj/flash.o + 0x00000aa8 0x20 THUMB Debug/../../obj/cstart.o .debug_aranges - 0x000007d8 0x40 THUMB Debug/../../obj/nvm.o + 0x00000ac8 0x20 THUMB Debug/../../obj/vectors.o .debug_aranges - 0x00000818 0x38 THUMB Debug/../../obj/timer.o + 0x00000ae8 0x30 THUMB Debug/../../obj/cpu.o .debug_aranges - 0x00000850 0x40 THUMB Debug/../../obj/uart.o + 0x00000b18 0x78 THUMB Debug/../../obj/flash.o .debug_aranges - 0x00000890 0x30 THUMB Debug/../../obj/can.o + 0x00000b90 0x40 THUMB Debug/../../obj/nvm.o .debug_aranges - 0x000008c0 0x20 THUMB Debug/../../obj/assert.o + 0x00000bd0 0x38 THUMB Debug/../../obj/timer.o .debug_aranges - 0x000008e0 0x28 THUMB Debug/../../obj/backdoor.o + 0x00000c08 0x40 THUMB Debug/../../obj/uart.o .debug_aranges - 0x00000908 0x28 THUMB Debug/../../obj/boot.o + 0x00000c48 0x30 THUMB Debug/../../obj/can.o .debug_aranges - 0x00000930 0x68 THUMB Debug/../../obj/com.o + 0x00000c78 0x20 THUMB Debug/../../obj/assert.o .debug_aranges - 0x00000998 0x28 THUMB Debug/../../obj/cop.o + 0x00000c98 0x28 THUMB Debug/../../obj/backdoor.o .debug_aranges - 0x000009c0 0x48 THUMB Debug/../../obj/xcp.o + 0x00000cc0 0x28 THUMB Debug/../../obj/boot.o .debug_aranges - 0x00000a08 0x70 THUMB Debug/../../obj/file.o + 0x00000ce8 0x68 THUMB Debug/../../obj/com.o .debug_aranges - 0x00000a78 0x190 THUMB Debug/../../obj/ff.o + 0x00000d50 0x28 THUMB Debug/../../obj/cop.o .debug_aranges - 0x00000c08 0x28 THUMB Debug/../../obj/unicode.o + 0x00000d78 0x48 THUMB Debug/../../obj/xcp.o .debug_aranges - 0x00000c30 0x508 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) + 0x00000dc0 0x70 THUMB Debug/../../obj/file.o .debug_aranges - 0x00001138 0x218 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + 0x00000e30 0x190 THUMB Debug/../../obj/ff.o .debug_aranges - 0x00001350 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + 0x00000fc0 0x28 THUMB Debug/../../obj/unicode.o + .debug_aranges + 0x00000fe8 0x98 THUMB Debug/../../obj/uip.o + .debug_aranges + 0x00001080 0x40 THUMB Debug/../../obj/uip_arp.o + .debug_aranges + 0x000010c0 0x38 THUMB Debug/../../obj/net.o + .debug_aranges + 0x000010f8 0x508 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) + .debug_aranges + 0x00001600 0x218 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_aranges + 0x00001818 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) -.debug_ranges 0x00000000 0x1480 +.debug_ranges 0x00000000 0x18e8 .debug_ranges 0x00000000 0x1f0 THUMB Debug/../../obj/mmc.o .debug_ranges 0x000001f0 0x18 THUMB Debug/../../obj/system_stm32f4xx.o .debug_ranges 0x00000208 0x108 THUMB Debug/../../obj/stm32f4xx_flash.o .debug_ranges 0x00000310 0x78 THUMB Debug/../../obj/stm32f4xx_gpio.o .debug_ranges 0x00000388 0x170 THUMB Debug/../../obj/stm32f4xx_rcc.o .debug_ranges 0x000004f8 0xf8 THUMB Debug/../../obj/stm32f4xx_sdio.o - .debug_ranges 0x000005f0 0xf0 THUMB Debug/../../obj/stm32f4xx_usart.o - .debug_ranges 0x000006e0 0x38 THUMB Debug/../../obj/hooks.o - .debug_ranges 0x00000718 0x10 THUMB Debug/../../obj/main.o - .debug_ranges 0x00000728 0x10 THUMB Debug/../../obj/vectors.o - .debug_ranges 0x00000738 0x20 THUMB Debug/../../obj/cpu.o - .debug_ranges 0x00000758 0x90 THUMB Debug/../../obj/flash.o - .debug_ranges 0x000007e8 0x30 THUMB Debug/../../obj/nvm.o - .debug_ranges 0x00000818 0x28 THUMB Debug/../../obj/timer.o - .debug_ranges 0x00000840 0x30 THUMB Debug/../../obj/uart.o - .debug_ranges 0x00000870 0x50 THUMB Debug/../../obj/can.o - .debug_ranges 0x000008c0 0x10 THUMB Debug/../../obj/assert.o - .debug_ranges 0x000008d0 0x18 THUMB Debug/../../obj/backdoor.o - .debug_ranges 0x000008e8 0x18 THUMB Debug/../../obj/boot.o - .debug_ranges 0x00000900 0x58 THUMB Debug/../../obj/com.o - .debug_ranges 0x00000958 0x18 THUMB Debug/../../obj/cop.o - .debug_ranges 0x00000970 0x80 THUMB Debug/../../obj/xcp.o - .debug_ranges 0x000009f0 0x60 THUMB Debug/../../obj/file.o - .debug_ranges 0x00000a50 0x2c8 THUMB Debug/../../obj/ff.o - .debug_ranges 0x00000d18 0x18 THUMB Debug/../../obj/unicode.o - .debug_ranges 0x00000d30 0x4f8 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) - .debug_ranges 0x00001228 0x208 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - .debug_ranges 0x00001430 0x50 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + .debug_ranges 0x000005f0 0x38 THUMB Debug/../../obj/stm32f4xx_syscfg.o + .debug_ranges 0x00000628 0xf0 THUMB Debug/../../obj/stm32f4xx_usart.o + .debug_ranges 0x00000718 0x320 THUMB Debug/../../obj/stm32_eth.o + .debug_ranges 0x00000a38 0x28 THUMB Debug/../../obj/netdev.o + .debug_ranges 0x00000a60 0x38 THUMB Debug/../../obj/hooks.o + .debug_ranges 0x00000a98 0x10 THUMB Debug/../../obj/main.o + .debug_ranges 0x00000aa8 0x10 THUMB Debug/../../obj/vectors.o + .debug_ranges 0x00000ab8 0x20 THUMB Debug/../../obj/cpu.o + .debug_ranges 0x00000ad8 0x98 THUMB Debug/../../obj/flash.o + .debug_ranges 0x00000b70 0x30 THUMB Debug/../../obj/nvm.o + .debug_ranges 0x00000ba0 0x28 THUMB Debug/../../obj/timer.o + .debug_ranges 0x00000bc8 0x30 THUMB Debug/../../obj/uart.o + .debug_ranges 0x00000bf8 0x50 THUMB Debug/../../obj/can.o + .debug_ranges 0x00000c48 0x10 THUMB Debug/../../obj/assert.o + .debug_ranges 0x00000c58 0x18 THUMB Debug/../../obj/backdoor.o + .debug_ranges 0x00000c70 0x18 THUMB Debug/../../obj/boot.o + .debug_ranges 0x00000c88 0x58 THUMB Debug/../../obj/com.o + .debug_ranges 0x00000ce0 0x18 THUMB Debug/../../obj/cop.o + .debug_ranges 0x00000cf8 0x80 THUMB Debug/../../obj/xcp.o + .debug_ranges 0x00000d78 0x60 THUMB Debug/../../obj/file.o + .debug_ranges 0x00000dd8 0x2c8 THUMB Debug/../../obj/ff.o + .debug_ranges 0x000010a0 0x18 THUMB Debug/../../obj/unicode.o + .debug_ranges 0x000010b8 0x88 THUMB Debug/../../obj/uip.o + .debug_ranges 0x00001140 0x30 THUMB Debug/../../obj/uip_arp.o + .debug_ranges 0x00001170 0x28 THUMB Debug/../../obj/net.o + .debug_ranges 0x00001198 0x4f8 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) + .debug_ranges 0x00001690 0x208 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_ranges 0x00001898 0x50 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) -.debug_line 0x00000000 0x609d +.debug_line 0x00000000 0x7e07 .debug_line 0x00000000 0xb5b THUMB Debug/../../obj/mmc.o .debug_line 0x00000b5b 0x21c THUMB Debug/../../obj/system_stm32f4xx.o .debug_line 0x00000d77 0x49f THUMB Debug/../../obj/stm32f4xx_flash.o .debug_line 0x00001216 0x3ae THUMB Debug/../../obj/stm32f4xx_gpio.o .debug_line 0x000015c4 0x590 THUMB Debug/../../obj/stm32f4xx_rcc.o .debug_line 0x00001b54 0x45f THUMB Debug/../../obj/stm32f4xx_sdio.o - .debug_line 0x00001fb3 0x4a2 THUMB Debug/../../obj/stm32f4xx_usart.o - .debug_line 0x00002455 0x2d5 THUMB Debug/../../obj/hooks.o - .debug_line 0x0000272a 0x269 THUMB Debug/../../obj/main.o - .debug_line 0x00002993 0x17f THUMB Debug/../../obj/cstart.o - .debug_line 0x00002b12 0x10a THUMB Debug/../../obj/vectors.o - .debug_line 0x00002c1c 0x150 THUMB Debug/../../obj/cpu.o - .debug_line 0x00002d6c 0x391 THUMB Debug/../../obj/flash.o - .debug_line 0x000030fd 0x137 THUMB Debug/../../obj/nvm.o - .debug_line 0x00003234 0x1a3 THUMB Debug/../../obj/timer.o - .debug_line 0x000033d7 0x305 THUMB Debug/../../obj/uart.o - .debug_line 0x000036dc 0x1a0 THUMB Debug/../../obj/can.o - .debug_line 0x0000387c 0xdf THUMB Debug/../../obj/assert.o - .debug_line 0x0000395b 0x117 THUMB Debug/../../obj/backdoor.o - .debug_line 0x00003a72 0x11b THUMB Debug/../../obj/boot.o - .debug_line 0x00003b8d 0x1b1 THUMB Debug/../../obj/com.o - .debug_line 0x00003d3e 0xaf THUMB Debug/../../obj/cop.o - .debug_line 0x00003ded 0x200 THUMB Debug/../../obj/xcp.o - .debug_line 0x00003fed 0x3d7 THUMB Debug/../../obj/file.o - .debug_line 0x000043c4 0xfc5 THUMB Debug/../../obj/ff.o - .debug_line 0x00005389 0x19d THUMB Debug/../../obj/unicode.o - .debug_line 0x00005526 0x5b3 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) - .debug_line 0x00005ad9 0x550 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - .debug_line 0x00006029 0x74 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + .debug_line 0x00001fb3 0x27d THUMB Debug/../../obj/stm32f4xx_syscfg.o + .debug_line 0x00002230 0x4a2 THUMB Debug/../../obj/stm32f4xx_usart.o + .debug_line 0x000026d2 0xcd9 THUMB Debug/../../obj/stm32_eth.o + .debug_line 0x000033ab 0x3b3 THUMB Debug/../../obj/netdev.o + .debug_line 0x0000375e 0x2d5 THUMB Debug/../../obj/hooks.o + .debug_line 0x00003a33 0x269 THUMB Debug/../../obj/main.o + .debug_line 0x00003c9c 0x17f THUMB Debug/../../obj/cstart.o + .debug_line 0x00003e1b 0x10a THUMB Debug/../../obj/vectors.o + .debug_line 0x00003f25 0x15b THUMB Debug/../../obj/cpu.o + .debug_line 0x00004080 0x3a0 THUMB Debug/../../obj/flash.o + .debug_line 0x00004420 0x137 THUMB Debug/../../obj/nvm.o + .debug_line 0x00004557 0x1a3 THUMB Debug/../../obj/timer.o + .debug_line 0x000046fa 0x305 THUMB Debug/../../obj/uart.o + .debug_line 0x000049ff 0x1a0 THUMB Debug/../../obj/can.o + .debug_line 0x00004b9f 0xdf THUMB Debug/../../obj/assert.o + .debug_line 0x00004c7e 0x117 THUMB Debug/../../obj/backdoor.o + .debug_line 0x00004d95 0x11b THUMB Debug/../../obj/boot.o + .debug_line 0x00004eb0 0x1bf THUMB Debug/../../obj/com.o + .debug_line 0x0000506f 0xaf THUMB Debug/../../obj/cop.o + .debug_line 0x0000511e 0x200 THUMB Debug/../../obj/xcp.o + .debug_line 0x0000531e 0x3d7 THUMB Debug/../../obj/file.o + .debug_line 0x000056f5 0xfc5 THUMB Debug/../../obj/ff.o + .debug_line 0x000066ba 0x19d THUMB Debug/../../obj/unicode.o + .debug_line 0x00006857 0x57e THUMB Debug/../../obj/uip.o + .debug_line 0x00006dd5 0x2a6 THUMB Debug/../../obj/uip_arp.o + .debug_line 0x0000707b 0x215 THUMB Debug/../../obj/net.o + .debug_line 0x00007290 0x5b3 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) + .debug_line 0x00007843 0x550 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_line 0x00007d93 0x74 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) -.debug_str 0x00000000 0x4ca0 - .debug_str 0x00000000 0x1460 THUMB Debug/../../obj/mmc.o +.debug_str 0x00000000 0x698f + .debug_str 0x00000000 0x145b THUMB Debug/../../obj/mmc.o 0x1526 (size before relaxing) - .debug_str 0x00001460 0x276 THUMB Debug/../../obj/system_stm32f4xx.o + .debug_str 0x0000145b 0x276 THUMB Debug/../../obj/system_stm32f4xx.o 0x3f7 (size before relaxing) - .debug_str 0x000016d6 0x424 THUMB Debug/../../obj/stm32f4xx_flash.o + .debug_str 0x000016d1 0x424 THUMB Debug/../../obj/stm32f4xx_flash.o 0x5f1 (size before relaxing) - .debug_str 0x00001afa 0x1c8 THUMB Debug/../../obj/stm32f4xx_gpio.o + .debug_str 0x00001af5 0x1c2 THUMB Debug/../../obj/stm32f4xx_gpio.o 0x508 (size before relaxing) - .debug_str 0x00001cc2 0x59f THUMB Debug/../../obj/stm32f4xx_rcc.o + .debug_str 0x00001cb7 0x59f THUMB Debug/../../obj/stm32f4xx_rcc.o 0x8b7 (size before relaxing) - .debug_str 0x00002261 0x21d THUMB Debug/../../obj/stm32f4xx_sdio.o + .debug_str 0x00002256 0x21d THUMB Debug/../../obj/stm32f4xx_sdio.o 0x6a0 (size before relaxing) - .debug_str 0x0000247e 0x488 THUMB Debug/../../obj/stm32f4xx_usart.o + .debug_str 0x00002473 0x1b4 THUMB Debug/../../obj/stm32f4xx_syscfg.o + 0x354 (size before relaxing) + .debug_str 0x00002627 0x488 THUMB Debug/../../obj/stm32f4xx_usart.o 0x70d (size before relaxing) - .debug_str 0x00002906 0x3a1 THUMB Debug/../../obj/hooks.o + .debug_str 0x00002aaf 0x12bb THUMB Debug/../../obj/stm32_eth.o + 0x1565 (size before relaxing) + .debug_str 0x00003d6a 0x227 THUMB Debug/../../obj/netdev.o + 0xcb6 (size before relaxing) + .debug_str 0x00003f91 0x398 THUMB Debug/../../obj/hooks.o 0x5b9 (size before relaxing) - .debug_str 0x00002ca7 0x81 THUMB Debug/../../obj/main.o + .debug_str 0x00004329 0x81 THUMB Debug/../../obj/main.o 0x40e (size before relaxing) - .debug_str 0x00002d28 0xd4 THUMB Debug/../../obj/vectors.o + .debug_str 0x000043aa 0xbb THUMB Debug/../../obj/vectors.o 0x1ea (size before relaxing) - .debug_str 0x00002dfc 0x113 THUMB Debug/../../obj/cpu.o - 0x23e (size before relaxing) - .debug_str 0x00002f0f 0x221 THUMB Debug/../../obj/flash.o - 0x4da (size before relaxing) - .debug_str 0x00003130 0x9f THUMB Debug/../../obj/nvm.o + .debug_str 0x00004465 0x12f THUMB Debug/../../obj/cpu.o + 0x25a (size before relaxing) + .debug_str 0x00004594 0x221 THUMB Debug/../../obj/flash.o + 0x4f6 (size before relaxing) + .debug_str 0x000047b5 0x9f THUMB Debug/../../obj/nvm.o 0x240 (size before relaxing) - .debug_str 0x000031cf 0xca THUMB Debug/../../obj/timer.o + .debug_str 0x00004854 0xca THUMB Debug/../../obj/timer.o 0x235 (size before relaxing) - .debug_str 0x00003299 0x11e THUMB Debug/../../obj/uart.o + .debug_str 0x0000491e 0x11e THUMB Debug/../../obj/uart.o 0x428 (size before relaxing) - .debug_str 0x000033b7 0x19a THUMB Debug/../../obj/can.o + .debug_str 0x00004a3c 0x19a THUMB Debug/../../obj/can.o 0x33f (size before relaxing) - .debug_str 0x00003551 0x9b THUMB Debug/../../obj/assert.o + .debug_str 0x00004bd6 0x9b THUMB Debug/../../obj/assert.o 0x1df (size before relaxing) - .debug_str 0x000035ec 0xe8 THUMB Debug/../../obj/backdoor.o + .debug_str 0x00004c71 0xe8 THUMB Debug/../../obj/backdoor.o 0x226 (size before relaxing) - .debug_str 0x000036d4 0x9b THUMB Debug/../../obj/boot.o + .debug_str 0x00004d59 0x9b THUMB Debug/../../obj/boot.o 0x1fe (size before relaxing) - .debug_str 0x0000376f 0x1cf THUMB Debug/../../obj/com.o - 0x396 (size before relaxing) - .debug_str 0x0000393e 0x70 THUMB Debug/../../obj/cop.o + .debug_str 0x00004df4 0x1fa THUMB Debug/../../obj/com.o + 0x3c1 (size before relaxing) + .debug_str 0x00004fee 0x70 THUMB Debug/../../obj/cop.o 0x190 (size before relaxing) - .debug_str 0x000039ae 0x224 THUMB Debug/../../obj/xcp.o + .debug_str 0x0000505e 0x21d THUMB Debug/../../obj/xcp.o 0x444 (size before relaxing) - .debug_str 0x00003bd2 0x31b THUMB Debug/../../obj/file.o + .debug_str 0x0000527b 0x31b THUMB Debug/../../obj/file.o 0x7e9 (size before relaxing) - .debug_str 0x00003eed 0x31a THUMB Debug/../../obj/ff.o + .debug_str 0x00005596 0x31a THUMB Debug/../../obj/ff.o 0x758 (size before relaxing) - .debug_str 0x00004207 0xa5 THUMB Debug/../../obj/unicode.o + .debug_str 0x000058b0 0xa5 THUMB Debug/../../obj/unicode.o 0x171 (size before relaxing) - .debug_str 0x000042ac 0x56f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) + .debug_str 0x00005955 0x3ff THUMB Debug/../../obj/uip.o + 0x5ca (size before relaxing) + .debug_str 0x00005d54 0x184 THUMB Debug/../../obj/uip_arp.o + 0x37a (size before relaxing) + .debug_str 0x00005ed8 0xc3 THUMB Debug/../../obj/net.o + 0x413 (size before relaxing) + .debug_str 0x00005f9b 0x56f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) 0x655 (size before relaxing) - .debug_str 0x0000481b 0x3b3 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_str 0x0000650a 0x3b3 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) 0x3fc (size before relaxing) - .debug_str 0x00004bce 0xd2 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + .debug_str 0x000068bd 0xd2 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) 0x11b (size before relaxing) .comment 0x00000000 0x4e @@ -3637,7 +4173,10 @@ OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossw .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_gpio.o .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_rcc.o .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_sdio.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_syscfg.o .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_usart.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32_eth.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/netdev.o .comment 0x00000000 0x4f THUMB Debug/../../obj/hooks.o .comment 0x00000000 0x4f THUMB Debug/../../obj/main.o .comment 0x00000000 0x4f THUMB Debug/../../obj/vectors.o @@ -3656,6 +4195,9 @@ OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossw .comment 0x00000000 0x4f THUMB Debug/../../obj/file.o .comment 0x00000000 0x4f THUMB Debug/../../obj/ff.o .comment 0x00000000 0x4f THUMB Debug/../../obj/unicode.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/uip.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/uip_arp.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/net.o .comment 0x00000000 0x4f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) .comment 0x00000000 0x4f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) .comment 0x00000000 0x4f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) @@ -3675,50 +4217,62 @@ OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossw .ARM.attributes 0x000000ff 0x33 THUMB Debug/../../obj/stm32f4xx_sdio.o .ARM.attributes - 0x00000132 0x33 THUMB Debug/../../obj/stm32f4xx_usart.o + 0x00000132 0x33 THUMB Debug/../../obj/stm32f4xx_syscfg.o .ARM.attributes - 0x00000165 0x33 THUMB Debug/../../obj/hooks.o + 0x00000165 0x33 THUMB Debug/../../obj/stm32f4xx_usart.o .ARM.attributes - 0x00000198 0x33 THUMB Debug/../../obj/main.o + 0x00000198 0x33 THUMB Debug/../../obj/stm32_eth.o .ARM.attributes - 0x000001cb 0x27 THUMB Debug/../../obj/cstart.o + 0x000001cb 0x33 THUMB Debug/../../obj/netdev.o .ARM.attributes - 0x000001f2 0x33 THUMB Debug/../../obj/vectors.o + 0x000001fe 0x33 THUMB Debug/../../obj/hooks.o .ARM.attributes - 0x00000225 0x33 THUMB Debug/../../obj/cpu.o + 0x00000231 0x33 THUMB Debug/../../obj/main.o .ARM.attributes - 0x00000258 0x33 THUMB Debug/../../obj/flash.o + 0x00000264 0x27 THUMB Debug/../../obj/cstart.o .ARM.attributes - 0x0000028b 0x33 THUMB Debug/../../obj/nvm.o + 0x0000028b 0x33 THUMB Debug/../../obj/vectors.o .ARM.attributes - 0x000002be 0x33 THUMB Debug/../../obj/timer.o + 0x000002be 0x33 THUMB Debug/../../obj/cpu.o .ARM.attributes - 0x000002f1 0x33 THUMB Debug/../../obj/uart.o + 0x000002f1 0x33 THUMB Debug/../../obj/flash.o .ARM.attributes - 0x00000324 0x33 THUMB Debug/../../obj/can.o + 0x00000324 0x33 THUMB Debug/../../obj/nvm.o .ARM.attributes - 0x00000357 0x33 THUMB Debug/../../obj/assert.o + 0x00000357 0x33 THUMB Debug/../../obj/timer.o .ARM.attributes - 0x0000038a 0x33 THUMB Debug/../../obj/backdoor.o + 0x0000038a 0x33 THUMB Debug/../../obj/uart.o .ARM.attributes - 0x000003bd 0x33 THUMB Debug/../../obj/boot.o + 0x000003bd 0x33 THUMB Debug/../../obj/can.o .ARM.attributes - 0x000003f0 0x33 THUMB Debug/../../obj/com.o + 0x000003f0 0x33 THUMB Debug/../../obj/assert.o .ARM.attributes - 0x00000423 0x33 THUMB Debug/../../obj/cop.o + 0x00000423 0x33 THUMB Debug/../../obj/backdoor.o .ARM.attributes - 0x00000456 0x33 THUMB Debug/../../obj/xcp.o + 0x00000456 0x33 THUMB Debug/../../obj/boot.o .ARM.attributes - 0x00000489 0x33 THUMB Debug/../../obj/file.o + 0x00000489 0x33 THUMB Debug/../../obj/com.o .ARM.attributes - 0x000004bc 0x33 THUMB Debug/../../obj/ff.o + 0x000004bc 0x33 THUMB Debug/../../obj/cop.o .ARM.attributes - 0x000004ef 0x33 THUMB Debug/../../obj/unicode.o + 0x000004ef 0x33 THUMB Debug/../../obj/xcp.o .ARM.attributes - 0x00000522 0x2e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) + 0x00000522 0x33 THUMB Debug/../../obj/file.o .ARM.attributes - 0x00000550 0x1e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + 0x00000555 0x33 THUMB Debug/../../obj/ff.o .ARM.attributes - 0x0000056e 0x2e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + 0x00000588 0x33 THUMB Debug/../../obj/unicode.o .ARM.attributes - 0x0000059c 0x2e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + 0x000005bb 0x33 THUMB Debug/../../obj/uip.o + .ARM.attributes + 0x000005ee 0x33 THUMB Debug/../../obj/uip_arp.o + .ARM.attributes + 0x00000621 0x33 THUMB Debug/../../obj/net.o + .ARM.attributes + 0x00000654 0x2e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2.o) + .ARM.attributes + 0x00000682 0x1e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .ARM.attributes + 0x000006a0 0x2e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .ARM.attributes + 0x000006ce 0x2e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/bin/openbtl_olimex_stm32e407.srec b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/bin/openbtl_olimex_stm32e407.srec index ea822848..5534d261 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/bin/openbtl_olimex_stm32e407.srec +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/bin/openbtl_olimex_stm32e407.srec @@ -1,29 +1,29 @@ S02B0000433A2F576F726B2F736F6674776172652F4F70656E424C542F5461726765742F44656D6F2F41524DEF -S315080000004420002017020008492300084923000855 -S315080000104923000849230008492300084923000802 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+S31508009A4063216421652166216721682169216A21CC +S31508009A506B216C216D216E216F2121FF22FF23FFCF +S31508009A6024FF25FF26FF27FF28FF29FF2AFF2BFFB4 +S31508009A702CFF2DFF2EFF2FFF30FF31FF32FF33FF64 +S31508009A8034FF35FF36FF37FF38FF39FF3AFF00004E +S30D08009A90FFFFFFFFFFFF0000C6 +S31508009A9801000000010000000000000001020304A4 +S30E08009AA80102030406070809047B S70508000217D9 diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/blt_conf.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/blt_conf.h index 0ad3490b..3acb7769 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/blt_conf.h +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/blt_conf.h @@ -108,6 +108,82 @@ #define BOOT_COM_UART_CHANNEL_INDEX (5) +/* The NET communication interface for firmware updates via TCP/IP is selected by setting + * the BOOT_COM_NET_ENABLE configurable to 1. The maximum amount of data bytes in a + * message for data transmission and reception is set through BOOT_COM_NET_TX_MAX_DATA + * and BOOT_COM_NET_RX_MAX_DATA, respectively. The default IP address is configured + * with the macros BOOT_COM_NET_IPADDRx. The default netmask is configued with the macros + * BOOT_COM_NET_NETMASKx. The default gateway is configured with the macros + * BOOT_COM_NET_GATEWAYx. The bootloader acts and a TCP/IP server. The port the server + * listen on for connections is configured with BOOT_COM_NET_PORT. + */ +/** \brief Enable/disable the NET transport layer. */ +#define BOOT_COM_NET_ENABLE (1) +/** \brief Configure number of bytes in the target->host data packet. */ +#define BOOT_COM_NET_TX_MAX_DATA (64) +/** \brief Configure number of bytes in the host->target data packet. */ +#define BOOT_COM_NET_RX_MAX_DATA (64) +/** \brief Configure the port that the TCP/IP server listens on */ +#define BOOT_COM_NET_PORT (1000) +/** \brief Configure the 1st byte of the IP address */ +#define BOOT_COM_NET_IPADDR0 (169) +/** \brief Configure the 2nd byte of the IP address */ +#define BOOT_COM_NET_IPADDR1 (254) +/** \brief Configure the 3rd byte of the IP address */ +#define BOOT_COM_NET_IPADDR2 (19) +/** \brief Configure the 4th byte of the IP address */ +#define BOOT_COM_NET_IPADDR3 (63) +/** \brief Configure the 1st byte of the network mask */ +#define BOOT_COM_NET_NETMASK0 (255) +/** \brief Configure the 2nd byte of the network mask */ +#define BOOT_COM_NET_NETMASK1 (255) +/** \brief Configure the 3rd byte of the network mask */ +#define BOOT_COM_NET_NETMASK2 (0) +/** \brief Configure the 4th byte of the network mask */ +#define BOOT_COM_NET_NETMASK3 (0) +/** \brief Configure the 1st byte of the gateway address */ +#define BOOT_COM_NET_GATEWAY0 (169) +/** \brief Configure the 2nd byte of the gateway address */ +#define BOOT_COM_NET_GATEWAY1 (254) +/** \brief Configure the 3rd byte of the gateway address */ +#define BOOT_COM_NET_GATEWAY2 (19) +/** \brief Configure the 4th byte of the gateway address */ +#define BOOT_COM_NET_GATEWAY3 (1) +/** \brief Enable/disable a hook function that is called when the IP address is about + * to be set. This allows a dynamic override of the BOOT_COM_NET_IPADDRx values. + */ +#define BOOT_COM_NET_IPADDR_HOOK_ENABLE (0) +/** \brief Enable/disable a hook function that is called when the netmask is about + * to be set. This allows a dynamic override of the BOOT_COM_NET_NETMASKx values. + */ +#define BOOT_COM_NET_NETMASK_HOOK_ENABLE (0) +/** \brief Enable/disable a hook function that is called when the gateway address is + * about to be set. This allows a dynamic override of the BOOT_COM_NET_GATEWAYx + * values. + */ +#define BOOT_COM_NET_GATEWAY_HOOK_ENABLE (0) + + +/**************************************************************************************** +* B A C K D O O R C O N F I G U R A T I O N +****************************************************************************************/ +#if (BOOT_COM_NET_ENABLE > 0) +/* Override the default time that the backdoor is open if firmware updates via TCP/IP + * are supported. in this case a reactivation of the bootloader results in a re- + * initialization of the ethernet MAC. when directly connected to the ethernet port of + * a PC this will go relatively fast (depending on what MS Windows is being used), but + * when connected to the network via a router this can take several seconds. feel free to + * shorten/lengthen this time for finetuning. the only downside of a long backdoor open + * time is that the starting of the user program will also be delayed for this time. + * + * Also note that when the target is directly connected to the ethernet port of a PC, + * the checkbox "Automatically retry socket connection" should be checked in the + * Microboot settings. if connecting via a router the uncheck this checkbox. + */ +#define BACKDOOR_ENTRY_TIMEOUT_MS (10000) +#endif + + /**************************************************************************************** * F I L E S Y S T E M I N T E R F A C E C O N F I G U R A T I O N ****************************************************************************************/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/ide/stm32f407_crossworks.hzp b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/ide/stm32f407_crossworks.hzp index 969b3fdd..742ba27c 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/ide/stm32f407_crossworks.hzp +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/ide/stm32f407_crossworks.hzp @@ -1,7 +1,7 @@ - + @@ -79,6 +79,17 @@ + + + + + + + + + + + @@ -128,7 +139,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/ide/stm32f407_crossworks.hzs b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/ide/stm32f407_crossworks.hzs index 62341ea5..7c9710fb 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/ide/stm32f407_crossworks.hzs +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/ide/stm32f407_crossworks.hzs @@ -64,7 +64,7 @@ - + - + diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/ethernetlib/inc/stm32_eth.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/ethernetlib/inc/stm32_eth.h new file mode 100644 index 00000000..578d8baa --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/ethernetlib/inc/stm32_eth.h @@ -0,0 +1,1610 @@ +/** + ****************************************************************************** + * @file stm32_eth.h + * @author MCD Application Team + * @version V1.0.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the Ethernet + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ETH_H +#define __STM32_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" /* STM32 registers */ + +/** @addtogroup STM32_ETH_Driver + * @{ + */ + +/** @defgroup ETH_Exported_Types + * @{ + */ + +/** + * @brief ETH MAC Init structure definition + */ +typedef struct { +/** + * @brief / * MAC + */ + uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation with the external PHY */ + uint32_t ETH_Watchdog; /*!< Enable/disable Watchdog timer */ + uint32_t ETH_Jabber; /*!< Enable/disable Jabber timer */ + uint32_t ETH_InterFrameGap; /*!< Selects minimum IFG between frames during transmission */ + uint32_t ETH_CarrierSense; /*!< Enable/disable Carrier Sense */ + uint32_t ETH_Speed; /*!< Indicates the Ethernet speed: 10/100 Mbps */ + uint32_t ETH_ReceiveOwn; /*!< Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */ + uint32_t ETH_LoopbackMode; /*!< Enable/disable internal MAC MII Loopback mode */ + uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */ + uint32_t ETH_ChecksumOffload; /*!< Enable/disable the calculation of complement sum of all received Ethernet frame payloads */ + uint32_t ETH_RetryTransmission; /*!< Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */ + uint32_t ETH_AutomaticPadCRCStrip; /*!< Enable/disable Automatic MAC Pad/CRC Stripping */ + uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value */ + uint32_t ETH_DeferralCheck; /*!< Enable/disable deferral check function (Half-Duplex mode) */ + uint32_t ETH_ReceiveAll; /*!< Enable/disable all frames reception by the MAC (No fitering)*/ + uint32_t ETH_SourceAddrFilter; /*!< Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */ + uint32_t ETH_PassControlFrames; /*!< Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */ + uint32_t ETH_BroadcastFramesReception; /*!< Enable/disable reception of Broadcast Frames */ + uint32_t ETH_DestinationAddrFilter; /*!< Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */ + uint32_t ETH_PromiscuousMode; /*!< Enable/disable Promiscuous Mode */ + uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */ + uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter */ + uint32_t ETH_HashTableHigh; /*!< This field contains the higher 32 bits of Hash table. */ + uint32_t ETH_HashTableLow; /*!< This field contains the lower 32 bits of Hash table. */ + uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame */ + uint32_t ETH_ZeroQuantaPause; /*!< Enable/disable the automatic generation of Zero-Quanta Pause Control frames */ + uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */ + uint32_t ETH_UnicastPauseFrameDetect; /*!< Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */ + uint32_t ETH_ReceiveFlowControl; /*!< Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */ + uint32_t ETH_TransmitFlowControl; /*!< Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */ + uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */ + uint32_t ETH_VLANTagIdentifier; /*!< VLAN tag identifier for receive frames */ + +/** + * @brief / * DMA + */ + uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Enable/disable Dropping of TCP/IP Checksum Error Frames */ + uint32_t ETH_ReceiveStoreForward; /*!< Enable/disable Receive store and forward */ + uint32_t ETH_FlushReceivedFrame; /*!< Enable/disable flushing of received frames */ + uint32_t ETH_TransmitStoreForward; /*!< Enable/disable Transmit store and forward */ + uint32_t ETH_TransmitThresholdControl; /*!< Selects the Transmit Threshold Control */ + uint32_t ETH_ForwardErrorFrames; /*!< Enable/disable forward to DMA of all frames except runt error frames */ + uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */ + uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO */ + uint32_t ETH_SecondFrameOperate; /*!< Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */ + uint32_t ETH_AddressAlignedBeats; /*!< Enable/disable Address Aligned Beats */ + uint32_t ETH_FixedBurst; /*!< Enable/disable the AHB Master interface fixed burst transfers */ + uint32_t ETH_RxDMABurstLength; /*!< Indicate the maximum number of beats to be transferred in one Rx DMA transaction */ + uint32_t ETH_TxDMABurstLength; /*!< Indicate the maximum number of beats to be transferred in one Tx DMA transaction */ + uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + uint32_t ETH_DMAArbitration; /*!< Selects DMA Tx/Rx arbitration */ +}ETH_InitTypeDef; + +/**--------------------------------------------------------------------------**/ +/** + * @brief DMA descriptors types + */ +/**--------------------------------------------------------------------------**/ + +/** + * @brief ETH DMA Desciptors data structure definition + */ +typedef struct { + uint32_t Status; /*!< Status */ + uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ +} ETH_DMADESCTypeDef; + +/** + * @} + */ + +/** @defgroup ETH_Exported_Constants + * @{ + */ +/**--------------------------------------------------------------------------**/ +/** + * @brief ETH Frames defines + */ +/**--------------------------------------------------------------------------**/ + +/** @defgroup ENET_Buffers_setting + * @{ + */ +#define ETH_MAX_PACKET_SIZE 1520 /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /*!< Ethernet CRC */ +#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ +#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA descriptors registers bits definition + */ +/**--------------------------------------------------------------------------**/ + +/* DMA Tx Desciptor -----------------------------------------------------------*/ +/**---------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ---------------------------------------------------------------------------------------------**/ + +/** + * @brief Bit definition of TDES0 register: DMA Tx descriptor status register + */ +#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */ +#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */ +#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */ +#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ +#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ +#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ +#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */ +#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ +#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ + +/** + * @brief Bit definition of TDES1 register + */ +#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ + +/** + * @brief Bit definition of TDES2 register + */ +#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of TDES3 register + */ +#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/** + * @} + */ + + +/** @defgroup DMA_Rx_descriptor + * @{ + */ + +/**-------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + -------------------------------------------------------------------------------------------------------------------**/ + +/** + * @brief Bit definition of RDES0 register: DMA Rx descriptor status register + */ +#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */ +#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/** + * @brief Bit definition of RDES1 register + */ +#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ + +/** + * @brief Bit definition of RDES2 register + */ +#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of RDES3 register + */ +#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/**--------------------------------------------------------------------------**/ +/** + * @brief Desciption of common PHY registers + */ +/**--------------------------------------------------------------------------**/ + +/** + * @} + */ + +/** @defgroup PHY_Read_write_Timeouts + * @{ + */ +#define PHY_READ_TO ((uint32_t)0x0004FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) + +/** + * @} + */ + +/** @defgroup PHY_Reset_Delay + * @{ + */ +#define PHY_ResetDelay ((uint32_t)0x04000000) + +/** + * @} + */ + +/** @defgroup PHY_Config_Delay + * @{ + */ +#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) + +/** + * @} + */ + +/** @defgroup PHY_Register_address + * @{ + */ +#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */ +#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */ + +/** + * @} + */ + +/** @defgroup PHY_basic_Control_register + * @{ + */ +#define PHY_Reset ((u16)0x8000) /*!< PHY Reset */ +#define PHY_Loopback ((u16)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((u16)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((u16)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_Powerdown ((u16)0x0800) /*!< Select the power down mode */ +#define PHY_Isolate ((u16)0x0400) /*!< Isolate PHY from MII */ + +/** + * @} + */ + +/** @defgroup PHY_basic_status_register + * @{ + */ +#define PHY_AutoNego_Complete ((u16)0x0020) /*!< Auto-Negotioation process completed */ +#define PHY_Linked_Status ((u16)0x0004) /*!< Valid link established */ +#define PHY_Jabber_detection ((u16)0x0002) /*!< Jabber condition detected */ + +/** + * @} + */ + +/** @defgroup PHY_status_register + * @{ + */ +/* The PHY status register value change from a PHY to another so the user have + to update this value depending on the used external PHY */ +/** + * @brief For LAN8700 + */ +//#define PHY_SR 31 /*!< Tranceiver Status Register */ +/** + * @brief For DP83848 + */ +#define PHY_SR 16 /*!< Tranceiver Status Register */ + +/* The Speed and Duplex mask values change from a PHY to another so the user have to update + this value depending on the used external PHY */ +/** + * @brief For LAN8700 + */ +//#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */ +//#define PHY_Duplex_Status ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */ + +/** + * @brief For DP83848 + */ +#define PHY_Speed_Status ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */ +#define PHY_Duplex_Status ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */ +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) +#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \ + ((REG) == PHY_BSR) || \ + ((REG) == PHY_SR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief MAC defines + */ +/**--------------------------------------------------------------------------**/ + +/** + * @} + */ + +/** @defgroup ETH_AutoNegotiation + * @{ + */ +#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) +#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) +#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \ + ((CMD) == ETH_AutoNegotiation_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_watchdog + * @{ + */ +#define ETH_Watchdog_Enable ((uint32_t)0x00000000) +#define ETH_Watchdog_Disable ((uint32_t)0x00800000) +#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \ + ((CMD) == ETH_Watchdog_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Jabber + * @{ + */ +#define ETH_Jabber_Enable ((uint32_t)0x00000000) +#define ETH_Jabber_Disable ((uint32_t)0x00400000) +#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \ + ((CMD) == ETH_Jabber_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Inter_Frame_Gap + * @{ + */ +#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ +#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \ + ((GAP) == ETH_InterFrameGap_88Bit) || \ + ((GAP) == ETH_InterFrameGap_80Bit) || \ + ((GAP) == ETH_InterFrameGap_72Bit) || \ + ((GAP) == ETH_InterFrameGap_64Bit) || \ + ((GAP) == ETH_InterFrameGap_56Bit) || \ + ((GAP) == ETH_InterFrameGap_48Bit) || \ + ((GAP) == ETH_InterFrameGap_40Bit)) + +/** + * @} + */ + +/** @defgroup ETH_Carrier_Sense + * @{ + */ +#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) +#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) +#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \ + ((CMD) == ETH_CarrierSense_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Speed + * @{ + */ +#define ETH_Speed_10M ((uint32_t)0x00000000) +#define ETH_Speed_100M ((uint32_t)0x00004000) +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \ + ((SPEED) == ETH_Speed_100M)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Own + * @{ + */ +#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) +#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) +#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \ + ((CMD) == ETH_ReceiveOwn_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Loop_back_Mode + * @{ + */ +#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) +#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) +#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \ + ((CMD) == ETH_LoopbackMode_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Duplex_mode + * @{ + */ +#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) +#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) +#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \ + ((MODE) == ETH_Mode_HalfDuplex)) + +/** + * @} + */ + +/** @defgroup ETH_Checksum_Offload + * @{ + */ +#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) +#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) +#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \ + ((CMD) == ETH_ChecksumOffload_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Retry_Transmission + * @{ + */ +#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) +#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) +#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \ + ((CMD) == ETH_RetryTransmission_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Automatic_Pad_CRC_Strip + * @{ + */ +#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) +#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \ + ((CMD) == ETH_AutomaticPadCRCStrip_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Back-Off_limit + * @{ + */ +#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) +#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) +#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) +#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) +#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \ + ((LIMIT) == ETH_BackOffLimit_8) || \ + ((LIMIT) == ETH_BackOffLimit_4) || \ + ((LIMIT) == ETH_BackOffLimit_1)) + +/** + * @} + */ + +/** @defgroup ETH_Deferral_Check + * @{ + */ +#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) +#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) +#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \ + ((CMD) == ETH_DeferralCheck_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_All + * @{ + */ +#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) +#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \ + ((CMD) == ETH_ReceiveAll_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Source_Addr_Filter + * @{ + */ +#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) +#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) +#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Pass_Control_Frames + * @{ + */ +#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ +#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter)) + +/** + * @} + */ + +/** @defgroup ETH_Broadcast_Frames_Reception + * @{ + */ +#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) +#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \ + ((CMD) == ETH_BroadcastFramesReception_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Destination_Addr_Filter + * @{ + */ +#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) +#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \ + ((FILTER) == ETH_DestinationAddrFilter_Inverse)) + +/** + * @} + */ + +/** @defgroup ETH_Promiscuous_Mode + * @{ + */ +#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) +#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) +#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \ + ((CMD) == ETH_PromiscuousMode_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_multicast_frames_filter + * @{ + */ +#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) +#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) +#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \ + ((FILTER) == ETH_MulticastFramesFilter_None)) + + +/** + * @} + */ + +/** @defgroup ETH_unicast_frames_filter + * @{ + */ +#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) +#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_Perfect)) + +/** + * @} + */ + +/** @defgroup ETH_Pause_Time + * @{ + */ +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) + +/** + * @} + */ + +/** @defgroup ETH_Zero_Quanta_Pause + * @{ + */ +#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) +#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \ + ((CMD) == ETH_ZeroQuantaPause_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Pause_Low_Threshold + * @{ + */ +#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ +#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus256)) + +/** + * @} + */ + +/** @defgroup ETH_Unicast_Pause_Frame_Detect + * @{ + */ +#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) +#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \ + ((CMD) == ETH_UnicastPauseFrameDetect_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Flow_Control + * @{ + */ +#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \ + ((CMD) == ETH_ReceiveFlowControl_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Transmit_Flow_Control + * @{ + */ +#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) +#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) +#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \ + ((CMD) == ETH_TransmitFlowControl_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_VLAN_Tag_Comparison + * @{ + */ +#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) +#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) +#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \ + ((COMPARISON) == ETH_VLANTagComparison_16Bit)) +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) + +/** + * @} + */ + +/** @defgroup ETH_MAC_Flags + * @{ + */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ +#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ + ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ + ((FLAG) == ETH_MAC_FLAG_PMT)) +/** + * @} + */ + +/** @defgroup ETH_MAC_Interrupts + * @{ + */ +#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ +#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ + ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ + ((IT) == ETH_MAC_IT_PMT)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses + * @{ + */ +#define ETH_MAC_Address0 ((uint32_t)0x00000000) +#define ETH_MAC_Address1 ((uint32_t)0x00000008) +#define ETH_MAC_Address2 ((uint32_t)0x00000010) +#define ETH_MAC_Address3 ((uint32_t)0x00000018) +#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \ + ((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) +#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter:_SA_DA_filed_of_received_frames + * @{ + */ +#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) +#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) +#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \ + ((FILTER) == ETH_MAC_AddressFilter_DA)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter:_Mask_bytes + * @{ + */ +#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ +#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \ + ((MASK) == ETH_MAC_AddressMask_Byte5) || \ + ((MASK) == ETH_MAC_AddressMask_Byte4) || \ + ((MASK) == ETH_MAC_AddressMask_Byte3) || \ + ((MASK) == ETH_MAC_AddressMask_Byte2) || \ + ((MASK) == ETH_MAC_AddressMask_Byte1)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA Desciptors defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_flags + * @{ + */ +#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \ + ((FLAG) == ETH_DMATxDesc_IC) || \ + ((FLAG) == ETH_DMATxDesc_LS) || \ + ((FLAG) == ETH_DMATxDesc_FS) || \ + ((FLAG) == ETH_DMATxDesc_DC) || \ + ((FLAG) == ETH_DMATxDesc_DP) || \ + ((FLAG) == ETH_DMATxDesc_TTSE) || \ + ((FLAG) == ETH_DMATxDesc_TER) || \ + ((FLAG) == ETH_DMATxDesc_TCH) || \ + ((FLAG) == ETH_DMATxDesc_TTSS) || \ + ((FLAG) == ETH_DMATxDesc_IHE) || \ + ((FLAG) == ETH_DMATxDesc_ES) || \ + ((FLAG) == ETH_DMATxDesc_JT) || \ + ((FLAG) == ETH_DMATxDesc_FF) || \ + ((FLAG) == ETH_DMATxDesc_PCE) || \ + ((FLAG) == ETH_DMATxDesc_LCA) || \ + ((FLAG) == ETH_DMATxDesc_NC) || \ + ((FLAG) == ETH_DMATxDesc_LCO) || \ + ((FLAG) == ETH_DMATxDesc_EC) || \ + ((FLAG) == ETH_DMATxDesc_VF) || \ + ((FLAG) == ETH_DMATxDesc_CC) || \ + ((FLAG) == ETH_DMATxDesc_ED) || \ + ((FLAG) == ETH_DMATxDesc_UF) || \ + ((FLAG) == ETH_DMATxDesc_DB)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_segment + * @{ + */ +#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */ +#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \ + ((SEGMENT) == ETH_DMATxDesc_FirstSegment)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control + * @{ + */ +#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ +#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull)) +/** + * @brief ETH DMA Tx Desciptor buffer size + */ +#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_flags + * @{ + */ +#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \ + ((FLAG) == ETH_DMARxDesc_AFM) || \ + ((FLAG) == ETH_DMARxDesc_ES) || \ + ((FLAG) == ETH_DMARxDesc_DE) || \ + ((FLAG) == ETH_DMARxDesc_SAF) || \ + ((FLAG) == ETH_DMARxDesc_LE) || \ + ((FLAG) == ETH_DMARxDesc_OE) || \ + ((FLAG) == ETH_DMARxDesc_VLAN) || \ + ((FLAG) == ETH_DMARxDesc_FS) || \ + ((FLAG) == ETH_DMARxDesc_LS) || \ + ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \ + ((FLAG) == ETH_DMARxDesc_LC) || \ + ((FLAG) == ETH_DMARxDesc_FT) || \ + ((FLAG) == ETH_DMARxDesc_RWT) || \ + ((FLAG) == ETH_DMARxDesc_RE) || \ + ((FLAG) == ETH_DMARxDesc_DBE) || \ + ((FLAG) == ETH_DMARxDesc_CE) || \ + ((FLAG) == ETH_DMARxDesc_MAMPCE)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_buffers_ + * @{ + */ +#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ +#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \ + ((BUFFER) == ETH_DMARxDesc_Buffer2)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame + * @{ + */ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) +#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \ + ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Receive_Store_Forward + * @{ + */ +#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \ + ((CMD) == ETH_ReceiveStoreForward_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Flush_Received_Frame + * @{ + */ +#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) +#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \ + ((CMD) == ETH_FlushReceivedFrame_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Store_Forward + * @{ + */ +#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) +#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) +#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \ + ((CMD) == ETH_TransmitStoreForward_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Threshold_Control + * @{ + */ +#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes)) +/** + * @} + */ + +/** @defgroup ETH_Forward_Error_Frames + * @{ + */ +#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) +#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \ + ((CMD) == ETH_ForwardErrorFrames_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Forward_Undersized_Good_Frames + * @{ + */ +#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) +#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \ + ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Threshold_Control + * @{ + */ +#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ +#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes)) +/** + * @} + */ + +/** @defgroup ETH_Second_Frame_Operate + * @{ + */ +#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) +#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) +#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \ + ((CMD) == ETH_SecondFrameOperate_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Address_Aligned_Beats + * @{ + */ +#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) +#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \ + ((CMD) == ETH_AddressAlignedBeats_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Fixed_Burst + * @{ + */ +#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) +#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) +#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \ + ((CMD) == ETH_FixedBurst_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Rx_DMA_Burst_Length + * @{ + */ +#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat)) + +/** + * @} + */ + +/** @defgroup ETH_Tx_DMA_Burst_Length + * @{ + */ +#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat)) +/** + * @brief ETH DMA Desciptor SkipLength + */ +#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Arbitration + * @{ + */ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) +#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \ + ((RATIO) == ETH_DMAArbitration_RxPriorTx)) +/** + * @} + */ + +/** @defgroup ETH_DMA_Flags + * @{ + */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ +#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */ +#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */ +#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ + +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) +#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ + ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \ + ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \ + ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ + ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ + ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ + ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ + ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ + ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ + ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ + ((FLAG) == ETH_DMA_FLAG_T)) +/** + * @} + */ + +/** @defgroup ETH_DMA_Interrupts + * @{ + */ +#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ +#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ +#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */ +#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */ +#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ + +#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ + ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ + ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ + ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ + ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ + ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ + ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ + ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ + ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_transmit_process_state_ + * @{ + */ +#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ + +/** + * @} + */ + + +/** @defgroup ETH_DMA_receive_process_state_ + * @{ + */ +#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the recieve frame into host memory */ + +/** + * @} + */ + +/** @defgroup ETH_DMA_overflow_ + * @{ + */ +#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ +#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \ + ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet PMT defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_PMT_Flags + * @{ + */ +#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ + ((FLAG) == ETH_PMT_FLAG_MPR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet MMC defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_MMC_Tx_Interrupts + * @{ + */ +#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ + +/** + * @} + */ + +/** @defgroup ETH_MMC_Rx_Interrupts + * @{ + */ +#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ +#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ + ((IT) != 0x00)) +#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ + ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ + ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) +/** + * @} + */ + +/** @defgroup ETH_MMC_Registers + * @{ + */ +#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */ +#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */ +#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */ +#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */ +#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */ +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */ +#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */ +#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */ +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */ + +/** + * @brief ETH MMC registers + */ +#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \ + ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \ + ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \ + ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \ + ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \ + ((REG) == ETH_MMCRGUFCR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet PTP defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_PTP_time_update_method + * @{ + */ +#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */ +#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */ +#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \ + ((UPDATE) == ETH_PTP_CoarseUpdate)) + +/** + * @} + */ + + +/** @defgroup ETH_PTP_Flags + * @{ + */ +#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */ +#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \ + ((FLAG) == ETH_PTP_FLAG_TSITE) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTU) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTI)) +/** + * @brief ETH PTP subsecond increment + */ +#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) + +/** + * @} + */ + + +/** @defgroup ETH_PTP_time_sign + * @{ + */ +#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */ +#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */ +#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \ + ((SIGN) == ETH_PTP_NegativeTime)) + +/** + * @brief ETH PTP time stamp low update + */ +#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) + +/** + * @brief ETH PTP registers + */ +#define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */ +#define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */ +#define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */ +#define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */ +#define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */ +#define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */ +#define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */ +#define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */ +#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ +#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \ + ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \ + ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \ + ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \ + ((REG) == ETH_PTPTTLR)) + +/** + * @} + */ + + +/** + * @} + */ + +/** @defgroup ETH_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions + * @{ + */ +void ETH_DeInit(void); +uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress); +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +void ETH_Start(void); +uint32_t ETH_HandleTxPkt(u8 *ppkt, u16 FrameLength); +uint32_t ETH_HandleRxPkt(u8 *ppkt); +uint32_t ETH_GetRxPktSize(void); +void ETH_DropRxPkt(void); + +/** + * @brief PHY + */ +u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg); +uint32_t ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue); +uint32_t ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState); + +/** + * @brief MAC + */ +void ETH_MACTransmissionCmd(FunctionalState NewState); +void ETH_MACReceptionCmd(FunctionalState NewState); +FlagStatus ETH_GetFlowControlBusyStatus(void); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState NewState); +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); +void ETH_MACAddressConfig(uint32_t MacAddr, u8 *Addr); +void ETH_GetMACAddress(uint32_t MacAddr, u8 *Addr); +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); + +/** + * @brief DMA Tx/Rx descriptors + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, uint32_t TxBuffCount); +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, uint32_t TxBuffCount); +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, uint32_t RxBuffCount); +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, uint32_t RxBuffCount); +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); + +/** + * @brief DMA + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); +uint32_t ETH_GetTransmitProcessState(void); +uint32_t ETH_GetReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); +void ETH_DMATransmissionCmd(FunctionalState NewState); +void ETH_DMAReceptionCmd(FunctionalState NewState); +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); +uint32_t ETH_GetRxOverflowMissedFrameCounter(void); +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); +uint32_t ETH_GetCurrentTxDescStartAddress(void); +uint32_t ETH_GetCurrentRxDescStartAddress(void); +uint32_t ETH_GetCurrentTxBufferAddress(void); +uint32_t ETH_GetCurrentRxBufferAddress(void); +void ETH_ResumeDMATransmission(void); +void ETH_ResumeDMAReception(void); + +/** + * @brief PMT + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); +void ETH_MagicPacketDetectionCmd(FunctionalState NewState); +void ETH_PowerDownCmd(FunctionalState NewState); + +/** + * @brief MMC + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState); +void ETH_MMCResetOnReadCmd(FunctionalState NewState); +void ETH_MMCCounterRolloverCmd(FunctionalState NewState); +void ETH_MMCCountersReset(void); +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); + +/** + * @brief PTP + */ +uint32_t ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, uint32_t *PTPTxTab); +uint32_t ETH_HandlePTPRxPkt(u8 *ppkt, uint32_t *PTPRxTab); +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, uint32_t TxBuffCount); +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, uint32_t RxBuffCount); +void ETH_EnablePTPTimeStampAddend(void); +void ETH_EnablePTPTimeStampInterruptTrigger(void); +void ETH_EnablePTPTimeStampUpdate(void); +void ETH_InitializePTPTimeStamp(void); +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod); +void ETH_PTPTimeStampCmd(FunctionalState NewState); +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG); +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue); +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); +void ETH_SetPTPTimeStampAddend(uint32_t Value); +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue); +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ETH_H */ +/** + * @} + */ + + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/ethernetlib/src/stm32_eth.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/ethernetlib/src/stm32_eth.c new file mode 100644 index 00000000..119b4dbf --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/ethernetlib/src/stm32_eth.c @@ -0,0 +1,3056 @@ +/** + ****************************************************************************** + * @file stm32_eth.c + * @author MCD Application Team + * @version V1.0.0 + * @date 06/19/2009 + * @brief This file provides all the ETH firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_eth.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32_ETH_Driver + * @brief ETH driver modules + * @{ + */ + +/** @defgroup ETH_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup ETH_Private_Defines + * @{ + */ +/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */ +ETH_DMADESCTypeDef *DMATxDescToSet; +ETH_DMADESCTypeDef *DMARxDescToGet; +ETH_DMADESCTypeDef *DMAPTPTxDescToSet; +ETH_DMADESCTypeDef *DMAPTPRxDescToGet; + +/* ETHERNET MAC address offsets */ +#define ETH_MAC_AddrHighBase (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_AddrLowBase (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_Mask ((uint32_t)0xFFFFFFE3) +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_Mask ((uint32_t)0xFF20810F) +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_Mask ((uint32_t)0x0000FF41) +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_Mask ((uint32_t)0xF8DE3F23) +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WakeupRegisterLength 8 +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RxOverflowMissedFramesCounterShift 17 +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATxDesc_CollisionCountShift 3 +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATxDesc_BufferSize2Shift 16 +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARxDesc_FrameLengthShift 16 +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARxDesc_Buffer2SizeShift 16 +/* ETHERNET errors */ +#define ETH_ERROR ((uint32_t)0) +#define ETH_SUCCESS ((uint32_t)1) +/** + * @} + */ + +/** @defgroup ETH_Private_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ETHERNET peripheral registers to their + * default reset values. + * @param None + * @retval : None + */ +void ETH_DeInit(void) +{ + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE); +} + +/** + * @brief Initializes the ETHERNET peripheral according to the specified + * parameters in the ETH_InitStruct . + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure + * that contains the configuration information for the + * specified ETHERNET peripheral. + * @param PHYAddress: external PHY address + * @retval : ETH_ERROR: Ethernet initialization failed + * ETH_SUCCESS: Ethernet successfully initialized + */ +uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) +{ + uint32_t RegValue = 0, tmpreg = 0; + __IO uint32_t i = 0; + RCC_ClocksTypeDef rcc_clocks; + uint32_t hclk = 120000000; + __IO uint32_t timeout = 0; + /* Check the parameters */ + /* MAC --------------------------*/ + assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation)); + assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog)); + assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber)); + assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap)); + assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense)); + assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed)); + assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn)); + assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode)); + assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode)); + assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload)); + assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission)); + assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip)); + assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit)); + assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck)); + assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll)); + assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter)); + assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames)); + assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception)); + assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter)); + assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode)); + assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); + assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter)); + assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime)); + assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause)); + assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold)); + assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect)); + assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl)); + assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl)); + assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison)); + assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier)); + /* DMA --------------------------*/ + assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame)); + assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward)); + assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame)); + assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward)); + assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl)); + assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames)); + assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames)); + assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl)); + assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate)); + assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats)); + assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst)); + assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength)); + assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); + assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); + assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); + /*-------------------------------- MAC Config ------------------------------*/ + /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/ + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg &= MACMIIAR_CR_Mask; + /* Get hclk frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + hclk = rcc_clocks.HCLK_Frequency; + /* Set CR bits depending on hclk value */ + if((hclk >= 20000000)&&(hclk < 35000000)) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; + } + else if((hclk >= 35000000)&&(hclk < 60000000)) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; + } + else if((hclk >= 60000000)&&(hclk <= 100000000)) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else /*if((hclk >= 100000000)&&(hclk <= 120000000)) */ + { + /* CSR Clock Range between 100-120 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; + } + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + ETH->MACMIIAR = (uint32_t)tmpreg; + /*-------------------- PHY initialization and configuration ----------------*/ + /* Put the PHY in reset mode */ + if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + + /* Delay to assure PHY reset */ + for(i = PHY_ResetDelay; i != 0; i--) + { + } + + if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) + { + /* We wait for linked satus... */ + do + { + timeout++; + } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Reset Timeout counter */ + timeout = 0; + + /* Enable Auto-Negotiation */ + if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + + /* Wait until the autonegotiation will be completed */ + do + { + timeout++; + } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Reset Timeout counter */ + timeout = 0; + + /* Read the result of the autonegotiation */ + RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR); + + /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */ + if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET) + { + /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */ + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + + } + else + { + /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */ + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + } + /* Configure the MAC with the speed fixed by the autonegotiation process */ + if(RegValue & PHY_Speed_Status) + { + /* Set Ethernet speed to 10M following the autonegotiation */ + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + } + else + { + /* Set Ethernet speed to 100M following the autonegotiation */ + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + } + } + else + { + if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) | + (uint16_t)(ETH_InitStruct->ETH_Speed >> 1)))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + /* Delay to assure PHY configuration */ + for(i = PHY_ConfigDelay; i != 0; i--) + { + } + } + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = ETH->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg &= MACCR_CLEAR_Mask; + /* Set the WD bit according to ETH_Watchdog value */ + /* Set the JD: bit according to ETH_Jabber value */ + /* Set the IFG bit according to ETH_InterFrameGap value */ + /* Set the DCRS bit according to ETH_CarrierSense value */ + /* Set the FES bit according to ETH_Speed value */ + /* Set the DO bit according to ETH_ReceiveOwn value */ + /* Set the LM bit according to ETH_LoopbackMode value */ + /* Set the DM bit according to ETH_Mode value */ + /* Set the IPC bit according to ETH_ChecksumOffload value */ + /* Set the DR bit according to ETH_RetryTransmission value */ + /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ + /* Set the BL bit according to ETH_BackOffLimit value */ + /* Set the DC bit according to ETH_DeferralCheck value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | + ETH_InitStruct->ETH_Jabber | + ETH_InitStruct->ETH_InterFrameGap | + ETH_InitStruct->ETH_CarrierSense | + ETH_InitStruct->ETH_Speed | + ETH_InitStruct->ETH_ReceiveOwn | + ETH_InitStruct->ETH_LoopbackMode | + ETH_InitStruct->ETH_Mode | + ETH_InitStruct->ETH_ChecksumOffload | + ETH_InitStruct->ETH_RetryTransmission | + ETH_InitStruct->ETH_AutomaticPadCRCStrip | + ETH_InitStruct->ETH_BackOffLimit | + ETH_InitStruct->ETH_DeferralCheck); + /* Write to ETHERNET MACCR */ + ETH->MACCR = (uint32_t)tmpreg; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Set the RA bit according to ETH_ReceiveAll value */ + /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */ + /* Set the PCF bit according to ETH_PassControlFrames value */ + /* Set the DBF bit according to ETH_BroadcastFramesReception value */ + /* Set the DAIF bit according to ETH_DestinationAddrFilter value */ + /* Set the PR bit according to ETH_PromiscuousMode value */ + /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */ + /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */ + /* Write to ETHERNET MACFFR */ + ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | + ETH_InitStruct->ETH_SourceAddrFilter | + ETH_InitStruct->ETH_PassControlFrames | + ETH_InitStruct->ETH_BroadcastFramesReception | + ETH_InitStruct->ETH_DestinationAddrFilter | + ETH_InitStruct->ETH_PromiscuousMode | + ETH_InitStruct->ETH_MulticastFramesFilter | + ETH_InitStruct->ETH_UnicastFramesFilter); + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ + /* Write to ETHERNET MACHTHR */ + ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh; + /* Write to ETHERNET MACHTLR */ + ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + /* Get the ETHERNET MACFCR value */ + tmpreg = ETH->MACFCR; + /* Clear xx bits */ + tmpreg &= MACFCR_CLEAR_Mask; + + /* Set the PT bit according to ETH_PauseTime value */ + /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */ + /* Set the PLT bit according to ETH_PauseLowThreshold value */ + /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */ + /* Set the RFE bit according to ETH_ReceiveFlowControl value */ + /* Set the TFE bit according to ETH_TransmitFlowControl value */ + tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | + ETH_InitStruct->ETH_ZeroQuantaPause | + ETH_InitStruct->ETH_PauseLowThreshold | + ETH_InitStruct->ETH_UnicastPauseFrameDetect | + ETH_InitStruct->ETH_ReceiveFlowControl | + ETH_InitStruct->ETH_TransmitFlowControl); + /* Write to ETHERNET MACFCR */ + ETH->MACFCR = (uint32_t)tmpreg; + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ + /* Set the ETV bit according to ETH_VLANTagComparison value */ + /* Set the VL bit according to ETH_VLANTagIdentifier value */ + ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | + ETH_InitStruct->ETH_VLANTagIdentifier); + + /*-------------------------------- DMA Config ------------------------------*/ + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg = ETH->DMAOMR; + /* Clear xx bits */ + tmpreg &= DMAOMR_CLEAR_Mask; + + /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */ + /* Set the RSF bit according to ETH_ReceiveStoreForward value */ + /* Set the DFF bit according to ETH_FlushReceivedFrame value */ + /* Set the TSF bit according to ETH_TransmitStoreForward value */ + /* Set the TTC bit according to ETH_TransmitThresholdControl value */ + /* Set the FEF bit according to ETH_ForwardErrorFrames value */ + /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */ + /* Set the RTC bit according to ETH_ReceiveThresholdControl value */ + /* Set the OSF bit according to ETH_SecondFrameOperate value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | + ETH_InitStruct->ETH_ReceiveStoreForward | + ETH_InitStruct->ETH_FlushReceivedFrame | + ETH_InitStruct->ETH_TransmitStoreForward | + ETH_InitStruct->ETH_TransmitThresholdControl | + ETH_InitStruct->ETH_ForwardErrorFrames | + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | + ETH_InitStruct->ETH_ReceiveThresholdControl | + ETH_InitStruct->ETH_SecondFrameOperate); + /* Write to ETHERNET DMAOMR */ + ETH->DMAOMR = (uint32_t)tmpreg; + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + /* Set the AAL bit according to ETH_AddressAlignedBeats value */ + /* Set the FB bit according to ETH_FixedBurst value */ + /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */ + /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */ + /* Set the DSL bit according to ETH_DesciptorSkipLength value */ + /* Set the PR and DA bits according to ETH_DMAArbitration value */ + ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | + ETH_InitStruct->ETH_FixedBurst | + ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + ETH_InitStruct->ETH_TxDMABurstLength | + (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | + ETH_InitStruct->ETH_DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + /* Return Ethernet configuration success */ + return ETH_SUCCESS; +} + +/** + * @brief Fills each ETH_InitStruct member with its default value. + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure + * which will be initialized. + * @retval : None + */ +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct) +{ + /* ETH_InitStruct members default value */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + /*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable; + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; + ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; +} + +/** + * @brief Enables ENET MAC and DMA reception/transmission + * @param None + * @retval : None + */ +void ETH_Start(void) +{ + /* Enable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionCmd(ENABLE); + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(); + /* Enable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionCmd(ENABLE); + + /* Start DMA transmission */ + ETH_DMATransmissionCmd(ENABLE); + /* Start DMA reception */ + ETH_DMAReceptionCmd(ENABLE); +} + +/** + * @brief Transmits a packet, from application buffer, pointed by ppkt. + * @param ppkt: pointer to application packet buffer to transmit. + * @param FrameLength: Tx Packet size. + * @retval : ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission + */ +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) +{ + uint32_t offset = 0; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); + } + + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + /* Chained Mode */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Receives a packet and copies it to memory pointed by ppkt. + * @param ppkt: pointer to application packet receive buffer. + * @retval : ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct + */ +uint32_t ETH_HandleRxPkt(uint8_t *ppkt) +{ + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + } + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + /* Return Frame Length/ERROR */ + return (framelength); +} + +/** + * @brief Get the size of received the received packet. + * @param None + * @retval : framelength: received packet size + */ +uint32_t ETH_GetRxPktSize(void) +{ + uint32_t frameLength = 0; + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the size of the packet: including 4 bytes of the CRC */ + frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); + } + + /* Return Frame Length */ + return frameLength; +} + +/** + * @brief Drop a Received packet (too small packet, etc...) + * @param None + * @retval : None + */ +void ETH_DropRxPkt(void) +{ + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read: this will + be the first Rx descriptor in this case */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } +} + +/*--------------------------------- PHY ------------------------------------*/ +/** + * @brief Read a PHY register + * @param PHYAddress: PHY device address, is the index of one of supported + * 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg: PHY register address, is the index of one of the 32 + * PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR : Tranceiver Basic Control Register + * @arg PHY_BSR : Tranceiver Basic Status Register + * @arg PHY_SR : Tranceiver Status Register + * @arg More PHY register could be read depending on the used PHY + * @retval : ETH_ERROR: in case of timeout + * MAC MIIDR register value: Data read from the selected PHY register (correct read ) + */ +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) +{ + uint32_t tmpreg = 0; +__IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_Mask; + /* Prepare the MII address register value */ + tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } + + /* Return data register value */ + return (uint16_t)(ETH->MACMIIDR); +} + +/** + * @brief Write to a PHY register + * @param PHYAddress: PHY device address, is the index of one of supported + * 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg: PHY register address, is the index of one of the 32 + * PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR : Tranceiver Control Register + * @arg More PHY register could be written depending on the used PHY + * @param PHYValue: the value to write + * @retval : ETH_ERROR: in case of timeout + * ETH_SUCCESS: for correct write + */ +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_Mask; + /* Prepare the MII register address value */ + tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Give the value to the MII data register */ + ETH->MACMIIDR = PHYValue; + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_WRITE_TO) + { + return ETH_ERROR; + } + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Enables or disables the PHY loopBack mode. + * @param PHYAddress: PHY device address, is the index of one of supported + * 32 PHY devices. + * This parameter can be one of the following values: + * @param NewState: new state of the PHY loopBack mode. + * This parameter can be: ENABLE or DISABLE. + * Note: Don't be confused with ETH_MACLoopBackCmd function + * which enables internal loopback at MII level + * @retval : ETH_ERROR: in case of bad PHY configuration + * ETH_SUCCESS: for correct PHY configuration + */ +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the PHY configuration to update it */ + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + + if (NewState != DISABLE) + { + /* Enable the PHY loopback mode */ + tmpreg |= PHY_Loopback; + } + else + { + /* Disable the PHY loopback mode: normal mode */ + tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); + } + /* Update the PHY control register with the new configuration */ + if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) + { + return ETH_SUCCESS; + } + else + { + /* Return SUCCESS */ + return ETH_ERROR; + } +} + +/*--------------------------------- MAC ------------------------------------*/ +/** + * @brief Enables or disables the MAC transmission. + * @param NewState: new state of the MAC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACTransmissionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC transmission */ + ETH->MACCR |= ETH_MACCR_TE; + } + else + { + /* Disable the MAC transmission */ + ETH->MACCR &= ~ETH_MACCR_TE; + } +} + +/** + * @brief Enables or disables the MAC reception. + * @param NewState: new state of the MAC reception. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACReceptionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC reception */ + ETH->MACCR |= ETH_MACCR_RE; + } + else + { + /* Disable the MAC reception */ + ETH->MACCR &= ~ETH_MACCR_RE; + } +} + +/** + * @brief Checks whether the ETHERNET flow control busy bit is set or not. + * @param None + * @retval : The new state of flow control busy status bit (SET or RESET). + */ +FlagStatus ETH_GetFlowControlBusyStatus(void) +{ + FlagStatus bitstatus = RESET; + /* The Flow Control register should not be written to until this bit is cleared */ + if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Initiate a Pause Control Frame (Full-duplex only). + * @param None + * @retval : None + */ +void ETH_InitiatePauseControlFrame(void) +{ + /* When Set In full duplex MAC initiates pause control frame */ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; +} + +/** + * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). + * @param NewState: new state of the MAC BackPressure operation activation. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_BackPressureActivationCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Activate the MAC BackPressure operation */ + /* In Half duplex: during backpressure, when the MAC receives a new frame, + the transmitter starts sending a JAM pattern resulting in a collision */ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; + } + else + { + /* Desactivate the MAC BackPressure operation */ + ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; + } +} + +/** + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param ETH_MAC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag + * @retval : The new state of ETHERNET MAC flag (SET or RESET). + */ +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); + if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. + * @param ETH_MAC_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt + * @arg ETH_MAC_IT_MMCR : MMC receive interrupt + * @arg ETH_MAC_IT_MMC : MMC interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval : The new state of ETHERNET MAC interrupt (SET or RESET). + */ +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); + if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the specified ETHERNET MAC interrupts. + * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @param NewState: new state of the specified ETHERNET MAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_IT(ETH_MAC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC interrupts */ + ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); + } + else + { + /* Disable the selected ETHERNET MAC interrupts */ + ETH->MACIMR |= ETH_MAC_IT; + } +} + +/** + * @brief Configures the selected MAC address. + * @param MacAddr: The MAC addres to configure. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Addr: Pointer on MAC address buffer data (6 bytes). + * @retval : None + */ +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Calculate the selectecd MAC address high register */ + tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + /* Load the selectecd MAC address high register */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg; + /* Calculate the selectecd MAC address low register */ + tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + + /* Load the selectecd MAC address low register */ + (*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg; +} + +/** + * @brief Get the selected MAC address. + * @param MacAddr: The MAC addres to return. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Addr: Pointer on MAC address buffer data (6 bytes). + * @retval : None + */ +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Get the selectecd MAC address high register */ + tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)); + + /* Calculate the selectecd MAC address buffer */ + Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[4] = (tmpreg & (uint8_t)0xFF); + /* Load the selectecd MAC address low register */ + tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)); + /* Calculate the selectecd MAC address buffer */ + Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); + Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); + Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF); + Addr[0] = (tmpreg & (uint8_t)0xFF); +} + +/** + * @brief Enables or disables the Address filter module uses the specified + * ETHERNET MAC address for perfect filtering + * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param NewState: new state of the specified ETHERNET MAC address use. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE; + } + else + { + /* Disable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE); + } +} + +/** + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Filter: specifies the used frame received field for comparaison + * This parameter can be one of the following values: + * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare + * with the SA fields of the received frame. + * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare + * with the DA fields of the received frame. + * @retval : None + */ +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter)); + + if (Filter != ETH_MAC_AddressFilter_DA) + { + /* The selected ETHERNET MAC address is used to compare with the SA fields of the + received frame. */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA; + } + else + { + /* The selected ETHERNET MAC address is used to compare with the DA fields of the + received frame. */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA); + } +} + +/** + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param MaskByte: specifies the used address bytes for comparaison + * This parameter can be any combination of the following values: + * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8]. + * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0]. + * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24]. + * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16]. + * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8]. + * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0]. + * @retval : None + */ +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte)); + + /* Clear MBC bits in the selected MAC address high register */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC); + /* Set the selected Filetr mask bytes */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte; +} +/*------------------------ DMA Tx/Rx Desciptors -----------------------------*/ + +/** + * @brief Initializes the DMA Tx descriptors in chain mode. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff: Pointer on the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval : None + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Second Address Chained bit */ + DMATxDesc->Status = ETH_DMATxDesc_TCH; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Initializes the DMA Tx descriptors in ring mode. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff1: Pointer on the first TxBuffer1 list + * @param TxBuff2: Pointer on the first TxBuffer2 list + * @param TxBuffCount: Number of the used Tx desc in the list + * Note: see decriptor skip length defined in ETH_DMA_InitStruct + * for the number of Words to skip between two unchained descriptors. + * @retval : None + */ +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (TxBuffCount-1)) + { + /* Set Transmit End of Ring bit */ + DMATxDesc->Status = ETH_DMATxDesc_TER; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param ETH_DMATxDescFlag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMATxDesc_IC : Interrupt on completetion + * @arg ETH_DMATxDesc_LS : Last Segment + * @arg ETH_DMATxDesc_FS : First Segment + * @arg ETH_DMATxDesc_DC : Disable CRC + * @arg ETH_DMATxDesc_DP : Disable Pad + * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable + * @arg ETH_DMATxDesc_TER : Transmit End of Ring + * @arg ETH_DMATxDesc_TCH : Second Address Chained + * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status + * @arg ETH_DMATxDesc_IHE : IP Header Error + * @arg ETH_DMATxDesc_ES : Error summary + * @arg ETH_DMATxDesc_JT : Jabber Timeout + * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush + * @arg ETH_DMATxDesc_PCE : Payload Checksum Error + * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission + * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver + * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision + * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions + * @arg ETH_DMATxDesc_VF : VLAN Frame + * @arg ETH_DMATxDesc_CC : Collision Count + * @arg ETH_DMATxDesc_ED : Excessive Deferral + * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory + * @arg ETH_DMATxDesc_DB : Deferred Bit + * @retval : The new state of ETH_DMATxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag)); + + if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @retval : The Transmit descriptor collision counter value. + */ +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift); +} + +/** + * @brief Set the specified DMA Tx Desc Own bit. + * @param DMATxDesc: Pointer on a Tx desc + * @retval : None + */ +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) +{ + /* Set the DMA Tx Desc Own bit */ + DMATxDesc->Status |= ETH_DMATxDesc_OWN; +} + +/** + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * @param DMATxDesc: Pointer on a Tx desc + * @param NewState: new state of the DMA Tx Desc transmit interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status |= ETH_DMATxDesc_IC; + } + else + { + /* Disable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC); + } +} + +/** + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * @param DMATxDesc: Pointer on a Tx desc + * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment + * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment + * @retval : None + */ +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment)); + + /* Selects the DMA Tx Desc Frame segment */ + DMATxDesc->Status |= DMATxDesc_FrameSegment; +} + +/** + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass + * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * @retval : None + */ +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum)); + + /* Set the selected DMA Tx desc checksum insertion control */ + DMATxDesc->Status |= DMATxDesc_Checksum; +} + +/** + * @brief Enables or disables the DMA Tx Desc CRC. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc CRC. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc CRC */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); + } + else + { + /* Disable the selected DMA Tx Desc CRC */ + DMATxDesc->Status |= ETH_DMATxDesc_DC; + } +} + +/** + * @brief Enables or disables the DMA Tx Desc end of ring. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc end of ring. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status |= ETH_DMATxDesc_TER; + } + else + { + /* Disable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); + } +} + +/** + * @brief Enables or disables the DMA Tx Desc second address chained. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc second address chained. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status |= ETH_DMATxDesc_TCH; + } + else + { + /* Disable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); + } +} + +/** + * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc padding for + * frame shorter than 64 bytes. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); + } + else + { + /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/ + DMATxDesc->Status |= ETH_DMATxDesc_DP; + } +} + +/** + * @brief Enables or disables the DMA Tx Desc time stamp. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc time stamp. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + } + else + { + /* Disable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); + } +} + +/** + * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. + * @param DMATxDesc: Pointer on a Tx desc + * @param BufferSize1: specifies the Tx desc buffer1 size. + * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used). + * @retval : None + */ +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1)); + assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2)); + + /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */ + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift)); +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff: Pointer on the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval : None + */ +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Initializes the DMA Rx descriptors in ring mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff1: Pointer on the first RxBuffer1 list + * @param RxBuff2: Pointer on the first RxBuffer2 list + * @param RxBuffCount: Number of the used Rx desc in the list + * Note: see decriptor skip length defined in ETH_DMA_InitStruct + * for the number of Words to skip between two unchained descriptors. + * @retval : None + */ +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + /* Set Buffer1 size */ + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (RxBuffCount-1)) + { + /* Set Receive End of Ring bit */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param ETH_DMARxDescFlag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame + * @arg ETH_DMARxDesc_ES: Error summary + * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame + * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame + * @arg ETH_DMARxDesc_LE: Frame size not matching with length field + * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow + * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame + * @arg ETH_DMARxDesc_FS: First descriptor of the frame + * @arg ETH_DMARxDesc_LS: Last descriptor of the frame + * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * @arg ETH_DMARxDesc_LC: Late collision occurred during reception + * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3 + * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception + * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface + * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits + * @arg ETH_DMARxDesc_CE: CRC error + * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * @retval : The new state of ETH_DMARxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag)); + if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Set the specified DMA Rx Desc Own bit. + * @param DMARxDesc: Pointer on a Rx desc + * @retval : None + */ +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) +{ + /* Set the DMA Rx Desc Own bit */ + DMARxDesc->Status |= ETH_DMARxDesc_OWN; +} + +/** + * @brief Returns the specified DMA Rx Desc frame length. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @retval : The Rx descriptor received frame length. + */ +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift); +} + +/** + * @brief Enables or disables the specified DMA Rx Desc receive interrupt. + * @param DMARxDesc: Pointer on a Rx desc + * @param NewState: new state of the specified DMA Rx Desc interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC); + } + else + { + /* Disable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; + } +} + +/** + * @brief Enables or disables the DMA Rx Desc end of ring. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param NewState: new state of the specified DMA Rx Desc end of ring. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + else + { + /* Disable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); + } +} + +/** + * @brief Enables or disables the DMA Rx Desc second address chained. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param NewState: new state of the specified DMA Rx Desc second address chained. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + } + else + { + /* Disable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); + } +} + +/** + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer. + * This parameter can be any one of the following values: + * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1 + * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 + * @retval : The Receive descriptor frame length. + */ +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer)); + + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) + { + /* Return the DMA Rx Desc buffer2 size */ + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift); + } + else + { + /* Return the DMA Rx Desc buffer1 size */ + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + } +} + +/*--------------------------------- DMA ------------------------------------*/ +/** + * @brief Resets all MAC subsystem internal registers and logic. + * @param None + * @retval : None + */ +void ETH_SoftwareReset(void) +{ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + ETH->DMABMR |= ETH_DMABMR_SR; +} + +/** + * @brief Checks whether the ETHERNET software reset bit is set or not. + * @param None + * @retval : The new state of DMA Bus Mode register SR bit (SET or RESET). + */ +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param ETH_DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag + * @arg ETH_DMA_FLAG_PMT : PMT flag + * @arg ETH_DMA_FLAG_MMC : MMC flag + * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access + * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr + * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ET : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Underflow flag + * @arg ETH_DMA_FLAG_RO : Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag + * @retval : The new state of ETH_DMA_FLAG (SET or RESET). + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG)); + if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the ETHERNET’s DMA pending flag. + * @param ETH_DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ETI : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag + * @arg ETH_DMA_FLAG_RO : Receive Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag + * @retval : None + */ +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG)); + + /* Clear the selected ETHERNET DMA FLAG */ + ETH->DMASR = (uint32_t) ETH_DMA_FLAG; +} + +/** + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * @param ETH_DMA_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt + * @arg ETH_DMA_IT_PMT : PMT interrupt + * @arg ETH_DMA_IT_MMC : MMC interrupt + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @retval : The new state of ETH_DMA_IT (SET or RESET). + */ +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT)); + if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the ETHERNET’s DMA IT pending bit. + * @param ETH_DMA_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ETI : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt + * @arg ETH_DMA_IT_RO : Receive Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @retval : None + */ +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + + /* Clear the selected ETHERNET DMA IT */ + ETH->DMASR = (uint32_t) ETH_DMA_IT; +} + +/** + * @brief Returns the ETHERNET DMA Transmit Process State. + * @param None + * @retval : The new ETHERNET DMA Transmit Process State: + * This can be one of the following values: + * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued + * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor + * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status + * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory + * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe + * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor + */ +uint32_t ETH_GetTransmitProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); +} + +/** + * @brief Returns the ETHERNET DMA Receive Process State. + * @param None + * @retval : The new ETHERNET DMA Receive Process State: + * This can be one of the following values: + * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued + * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor + * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet + * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable + * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor + * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory + */ +uint32_t ETH_GetReceiveProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); +} + +/** + * @brief Clears the ETHERNET transmit FIFO. + * @param None + * @retval : None + */ +void ETH_FlushTransmitFIFO(void) +{ + /* Set the Flush Transmit FIFO bit */ + ETH->DMAOMR |= ETH_DMAOMR_FTF; +} + +/** + * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. + * @param None + * @retval : The new state of ETHERNET flush transmit FIFO bit (SET or RESET). + */ +FlagStatus ETH_GetFlushTransmitFIFOStatus(void) +{ + FlagStatus bitstatus = RESET; + if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the DMA transmission. + * @param NewState: new state of the DMA transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATransmissionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transmission */ + ETH->DMAOMR |= ETH_DMAOMR_ST; + } + else + { + /* Disable the DMA transmission */ + ETH->DMAOMR &= ~ETH_DMAOMR_ST; + } +} + +/** + * @brief Enables or disables the DMA reception. + * @param NewState: new state of the DMA reception. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMAReceptionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA reception */ + ETH->DMAOMR |= ETH_DMAOMR_SR; + } + else + { + /* Disable the DMA reception */ + ETH->DMAOMR &= ~ETH_DMAOMR_SR; + } +} + +/** + * @brief Enables or disables the specified ETHERNET DMA interrupts. + * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @param NewState: new state of the specified ETHERNET DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET DMA interrupts */ + ETH->DMAIER |= ETH_DMA_IT; + } + else + { + /* Disable the selected ETHERNET DMA interrupts */ + ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT); + } +} + +/** + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter + * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter + * @retval : The new state of ETHERNET DMA overflow Flag (SET or RESET). + */ +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow)); + + if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. + * @param None + * @retval : The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_GetRxOverflowMissedFrameCounter(void) +{ + return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift)); +} + +/** + * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. + * @param None + * @retval : The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) +{ + return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); +} + +/** + * @brief Get the ETHERNET DMA DMACHTDR register value. + * @param None + * @retval : The value of the current Tx desc start address. + */ +uint32_t ETH_GetCurrentTxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHTDR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHRDR register value. + * @param None + * @retval : The value of the current Rx desc start address. + */ +uint32_t ETH_GetCurrentRxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHRDR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHTBAR register value. + * @param None + * @retval : The value of the current Tx desc buffer address. + */ +uint32_t ETH_GetCurrentTxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHTBAR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHRBAR register value. + * @param None + * @retval : The value of the current Rx desc buffer address. + */ +uint32_t ETH_GetCurrentRxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHRBAR)); +} + +/** + * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand + * register: (the data written could be anything). This forces + * the DMA to resume transmission. + * @param None + * @retval : None. + */ +void ETH_ResumeDMATransmission(void) +{ + ETH->DMATPDR = 0; +} + +/** + * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand + * register: (the data written could be anything). This forces + * the DMA to resume reception. + * @param None + * @retval : None. + */ +void ETH_ResumeDMAReception(void) +{ + ETH->DMARPDR = 0; +} + +/*--------------------------------- PMT ------------------------------------*/ +/** + * @brief Reset Wakeup frame filter register pointer. + * @param None + * @retval : None + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; +} + +/** + * @brief Populates the remote wakeup frame registers. + * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer + * data (8 words). + * @retval : None + */ +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) +{ + uint32_t i = 0; + + /* Fill Remote Wake-up Frame Filter register with Buffer data */ + for(i =0; iMACRWUFFR = Buffer[i]; + } +} + +/** + * @brief Enables or disables any unicast packet filtered by the MAC + * (DAF) address recognition to be a wake-up frame. + * @param NewState: new state of the MAC Global Unicast Wake-Up. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; + } + else + { + /* Disable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; + } +} + +/** + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * @param ETH_PMT_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset + * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPR : Magic Packet Received + * @retval : The new state of ETHERNET PMT Flag (SET or RESET). + */ +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG)); + + if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the MAC Wake-Up Frame Detection. + * @param NewState: new state of the MAC Wake-Up Frame Detection. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; + } + else + { + /* Disable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + } +} + +/** + * @brief Enables or disables the MAC Magic Packet Detection. + * @param NewState: new state of the MAC Magic Packet Detection. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MagicPacketDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Magic Packet Detection */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; + } + else + { + /* Disable the MAC Magic Packet Detection */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + } +} + +/** + * @brief Enables or disables the MAC Power Down. + * @param NewState: new state of the MAC Power Down. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_PowerDownCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Power Down */ + /* This puts the MAC in power down mode */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; + } + else + { + /* Disable the MAC Power Down */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; + } +} + +/*--------------------------------- MMC ------------------------------------*/ +/** + * @brief Enables or disables the MMC Counter Freeze. + * @param NewState: new state of the MMC Counter Freeze. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MMC Counter Freeze */ + ETH->MMCCR |= ETH_MMCCR_MCF; + } + else + { + /* Disable the MMC Counter Freeze */ + ETH->MMCCR &= ~ETH_MMCCR_MCF; + } +} + +/** + * @brief Enables or disables the MMC Reset On Read. + * @param NewState: new state of the MMC Reset On Read. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCResetOnReadCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MMC Counter reset on read */ + ETH->MMCCR |= ETH_MMCCR_ROR; + } + else + { + /* Disable the MMC Counter reset on read */ + ETH->MMCCR &= ~ETH_MMCCR_ROR; + } +} + +/** + * @brief Enables or disables the MMC Counter Stop Rollover. + * @param NewState: new state of the MMC Counter Stop Rollover. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCCounterRolloverCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Disable the MMC Counter Stop Rollover */ + ETH->MMCCR &= ~ETH_MMCCR_CSR; + } + else + { + /* Enable the MMC Counter Stop Rollover */ + ETH->MMCCR |= ETH_MMCCR_CSR; + } +} + +/** + * @brief Resets the MMC Counters. + * @param None + * @retval : None + */ +void ETH_MMCCountersReset(void) +{ + /* Resets the MMC Counters */ + ETH->MMCCR |= ETH_MMCCR_CR; +} + +/** + * @brief Enables or disables the specified ETHERNET MMC interrupts. + * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt + * sources to be enabled or disabled. + * This parameter can be any combination of Tx interrupt or + * any combination of Rx interrupt (but not both)of the following values: + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value + * @param NewState: new state of the specified ETHERNET MMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + /* Remove egister mak from IT */ + ETH_MMC_IT &= 0xEFFFFFFF; + + /* ETHERNET MMC Rx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCRIMR |= ETH_MMC_IT; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCTIMR |= ETH_MMC_IT; + } + } +} + +/** + * @brief Checks whether the specified ETHERNET MMC IT is set or not. + * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value + * @retval : The value of ETHERNET MMC IT (SET or RESET). + */ +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); + + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + /* ETHERNET MMC Rx interrupts selected */ + /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ + if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ + if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/** + * @brief Get the specified ETHERNET MMC register value. + * @param ETH_MMCReg: specifies the ETHERNET MMC register. + * This parameter can be one of the following values: + * @arg ETH_MMCCR : MMC CR register + * @arg ETH_MMCRIR : MMC RIR register + * @arg ETH_MMCTIR : MMC TIR register + * @arg ETH_MMCRIMR : MMC RIMR register + * @arg ETH_MMCTIMR : MMC TIMR register + * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register + * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register + * @arg ETH_MMCTGFCR : MMC TGFCR register + * @arg ETH_MMCRFCECR : MMC RFCECR register + * @arg ETH_MMCRFAECR : MMC RFAECR register + * @arg ETH_MMCRGUFCR : MMC RGUFCRregister + * @retval : The value of ETHERNET MMC Register value. + */ +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) +{ + /* Check the parameters */ + assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg)); + + /* Return the selected register value */ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); +} +/*--------------------------------- PTP ------------------------------------*/ + +/** + * @brief Updated the PTP block for fine correction with the Time Stamp + * Addend register value. + * @param None + * @retval : None + */ +void ETH_EnablePTPTimeStampAddend(void) +{ + /* Enable the PTP block update with the Time Stamp Addend register value */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; +} + +/** + * @brief Enable the PTP Time Stamp interrupt trigger + * @param None + * @retval : None + */ +void ETH_EnablePTPTimeStampInterruptTrigger(void) +{ + /* Enable the PTP target time interrupt */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; +} + +/** + * @brief Updated the PTP system time with the Time Stamp Update register + * value. + * @param None + * @retval : None + */ +void ETH_EnablePTPTimeStampUpdate(void) +{ + /* Enable the PTP system time update with the Time Stamp Update register value */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; +} + +/** + * @brief Initialize the PTP Time Stamp + * @param None + * @retval : None + */ +void ETH_InitializePTPTimeStamp(void) +{ + /* Initialize the PTP Time Stamp */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; +} + +/** + * @brief Selects the PTP Update method + * @param UpdateMethod: the PTP Update method + * This parameter can be one of the following values: + * @arg ETH_PTP_FineUpdate : Fine Update method + * @arg ETH_PTP_CoarseUpdate : Coarse Update method + * @retval : None + */ +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_UPDATE(UpdateMethod)); + + if (UpdateMethod != ETH_PTP_CoarseUpdate) + { + /* Enable the PTP Fine Update method */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; + } + else + { + /* Disable the PTP Coarse Update method */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); + } +} + +/** + * @brief Enables or disables the PTP time stamp for transmit and receive frames. + * @param NewState: new state of the PTP time stamp for transmit and receive frames + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_PTPTimeStampCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSE; + } + else + { + /* Disable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); + } +} + +/** + * @brief Checks whether the specified ETHERNET PTP flag is set or not. + * @param ETH_PTP_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PTP_FLAG_TSARU : Addend Register Update + * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable + * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update + * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize + * @retval : The new state of ETHERNET PTP Flag (SET or RESET). + */ +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG)); + + if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Sets the system time Sub-Second Increment value. + * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value. + * @retval : None + */ +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue)); + /* Set the PTP Sub-Second Increment Register */ + ETH->PTPSSIR = SubSecondValue; +} + +/** + * @brief Sets the Time Stamp update sign and values. + * @param Sign: specifies the PTP Time update value sign. + * This parameter can be one of the following values: + * @arg ETH_PTP_PositiveTime : positive time value. + * @arg ETH_PTP_NegativeTime : negative time value. + * @param SecondValue: specifies the PTP Time update second value. + * @param SubSecondValue: specifies the PTP Time update sub-second value. + * this is a 31 bit value. bit32 correspond to the sign. + * @retval : None + */ +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); + assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); + /* Set the PTP Time Update High Register */ + ETH->PTPTSHUR = SecondValue; + + /* Set the PTP Time Update Low Register with sign */ + ETH->PTPTSLUR = Sign | SubSecondValue; +} + +/** + * @brief Sets the Time Stamp Addend value. + * @param Value: specifies the PTP Time Stamp Addend Register value. + * @retval : None + */ +void ETH_SetPTPTimeStampAddend(uint32_t Value) +{ + /* Set the PTP Time Stamp Addend Register */ + ETH->PTPTSAR = Value; +} + +/** + * @brief Sets the Target Time registers values. + * @param HighValue: specifies the PTP Target Time High Register value. + * @param LowValue: specifies the PTP Target Time Low Register value. + * @retval : None + */ +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) +{ + /* Set the PTP Target Time High Register */ + ETH->PTPTTHR = HighValue; + /* Set the PTP Target Time Low Register */ + ETH->PTPTTLR = LowValue; +} + +/** + * @brief Get the specified ETHERNET PTP register value. + * @param ETH_PTPReg: specifies the ETHERNET PTP register. + * This parameter can be one of the following values: + * @arg ETH_PTPTSCR : Sub-Second Increment Register + * @arg ETH_PTPSSIR : Sub-Second Increment Register + * @arg ETH_PTPTSHR : Time Stamp High Register + * @arg ETH_PTPTSLR : Time Stamp Low Register + * @arg ETH_PTPTSHUR : Time Stamp High Update Register + * @arg ETH_PTPTSLUR : Time Stamp Low Update Register + * @arg ETH_PTPTSAR : Time Stamp Addend Register + * @arg ETH_PTPTTHR : Target Time High Register + * @arg ETH_PTPTTLR : Target Time Low Register + * @retval : The value of ETHERNET PTP Register value. + */ +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg)); + + /* Return the selected register value */ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); +} + +/** + * @brief Initializes the DMA Tx descriptors in chain mode with PTP. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list + * @param TxBuff: Pointer on the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval : None + */ +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + DMAPTPTxDescToSet = DMAPTPTxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab+i; + /* Set Second Address Chained bit and enable PTP */ + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } + /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */ + (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; + (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; + } + /* Store on the last DMAPTPTxDescTab desc status record the first list address */ + (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab; + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list + * @param RxBuff: Pointer on the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval : None + */ +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */ + (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; + (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; + } + /* Store on the last DMAPTPRxDescTab desc status record the first list address */ + (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab; + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Transmits a packet, from application buffer, pointed by ppkt with + * Time Stamp values. + * @param ppkt: pointer to application packet buffer to transmit. + * @param FrameLength: Tx Packet size. + * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values. + * @retval : ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission + */ +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) +{ + uint32_t offset = 0, timeout = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); + } + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + /* Wait for ETH_DMATxDesc_TTSS flag to be set */ + do + { + timeout++; + } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Clear the DMATxDescToSet status register TTSS flag */ + DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; + *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; + *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; + /* Update the ENET DMA current descriptor */ + /* Chained Mode */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr); + if(DMAPTPTxDescToSet->Status != 0) + { + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status); + } + else + { + DMAPTPTxDescToSet++; + } + } + else /* Ring Mode */ + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read: this will + be the first Tx descriptor in this case */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Receives a packet and copies it to memory pointed by ppkt with + * Time Stamp values. + * @param ppkt: pointer to application packet receive buffer. + * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values. + * @retval : ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct + */ +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) +{ + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ENET or CPU */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + } + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; + *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr); + if(DMAPTPRxDescToGet->Status != 0) + { + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status); + } + else + { + DMAPTPRxDescToGet++; + } + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return Frame Length/ERROR */ + return (framelength); +} +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/clock-arch.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/clock-arch.c new file mode 100644 index 00000000..1e213136 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/clock-arch.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.c,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * Implementation of architecture-specific clock functionality + * \author + * Adam Dunkels + */ + +#include "clock-arch.h" +#include "boot.h" + +/*---------------------------------------------------------------------------*/ +clock_time_t +clock_time(void) +{ + return (clock_time_t)TimerGet(); +} +/*---------------------------------------------------------------------------*/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/clock-arch.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/clock-arch.h new file mode 100644 index 00000000..aa97f0e7 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/clock-arch.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +typedef int clock_time_t; +#define CLOCK_CONF_SECOND 1000 + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/netdev.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/netdev.c new file mode 100644 index 00000000..09d0d2a7 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/netdev.c @@ -0,0 +1,451 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Author: Adam Dunkels + * + * $Id: netdev.c,v 1.8 2006/06/07 08:39:58 adam Exp $ + */ + + +/*---------------------------------------------------------------------------*/ +#include "uip.h" +#include "uip_arp.h" +#include "boot.h" +#include "stm32f4xx.h" /* STM32 registers */ +#include "stm32f4xx_conf.h" /* STM32 peripheral drivers */ +#include "stm32_eth.h" /* STM32 ethernet library */ +#include /* for memcpy */ + + +/*---------------------------------------------------------------------------*/ +#define NETDEV_DEFAULT_MACADDR0 (0x08) +#define NETDEV_DEFAULT_MACADDR1 (0x00) +#define NETDEV_DEFAULT_MACADDR2 (0x27) +#define NETDEV_DEFAULT_MACADDR3 (0x69) +#define NETDEV_DEFAULT_MACADDR4 (0x5B) +#define NETDEV_DEFAULT_MACADDR5 (0x45) + + +/*---------------------------------------------------------------------------*/ +static void netdev_TxDscrInit(void); +static void netdev_RxDscrInit(void); + +/*---------------------------------------------------------------------------*/ +typedef union _TranDesc0_t +{ + uint32_t Data; + struct { + uint32_t DB : 1; + uint32_t UF : 1; + uint32_t ED : 1; + uint32_t CC : 4; + uint32_t VF : 1; + uint32_t EC : 1; + uint32_t LC : 1; + uint32_t NC : 1; + uint32_t LSC : 1; + uint32_t IPE : 1; + uint32_t FF : 1; + uint32_t JT : 1; + uint32_t ES : 1; + uint32_t IHE : 1; + uint32_t : 3; + uint32_t TCH : 1; + uint32_t TER : 1; + uint32_t CIC : 2; + uint32_t : 2; + uint32_t DP : 1; + uint32_t DC : 1; + uint32_t FS : 1; + uint32_t LSEG : 1; + uint32_t IC : 1; + uint32_t OWN : 1; + }; +} TranDesc0_t, * pTranDesc0_t; + +typedef union _TranDesc1_t +{ + uint32_t Data; + struct { + uint32_t TBS1 :13; + uint32_t : 3; + uint32_t TBS2 :12; + uint32_t : 3; + }; +} TranDesc1_t, * pTranDesc1_t; + +typedef union _RecDesc0_t +{ + uint32_t Data; + struct { + uint32_t RMAM_PCE : 1; + uint32_t CE : 1; + uint32_t DE : 1; + uint32_t RE : 1; + uint32_t RWT : 1; + uint32_t FT : 1; + uint32_t LC : 1; + uint32_t IPHCE : 1; + uint32_t LS : 1; + uint32_t FS : 1; + uint32_t VLAN : 1; + uint32_t OE : 1; + uint32_t LE : 1; + uint32_t SAF : 1; + uint32_t DERR : 1; + uint32_t ES : 1; + uint32_t FL :14; + uint32_t AFM : 1; + uint32_t OWN : 1; + }; +} RecDesc0_t, * pRecDesc0_t; + +typedef union _recDesc1_t +{ + uint32_t Data; + struct { + uint32_t RBS1 :13; + uint32_t : 1; + uint32_t RCH : 1; + uint32_t RER : 1; + uint32_t RBS2 :14; + uint32_t DIC : 1; + }; +} RecDesc1_t, * pRecDesc1_t; + +typedef union _EnetDmaDesc_t +{ + uint32_t Data[4]; + // Rx DMA descriptor + struct + { + RecDesc0_t RxDesc0; + RecDesc1_t RxDesc1; + uint32_t * pBuffer; + union + { + uint32_t * pBuffer2; + union _EnetDmaDesc_t * pEnetDmaNextDesc; + }; + } Rx; + // Tx DMA descriptor + struct + { + TranDesc0_t TxDesc0; + TranDesc1_t TxDesc1; + uint32_t * pBuffer1; + union + { + uint32_t * pBuffer2; + union _EnetDmaDesc_t * pEnetDmaNextDesc; + }; + } Tx; +} EnetDmaDesc_t, * pEnetDmaDesc_t; + + +/*---------------------------------------------------------------------------*/ +uint8_t RxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4))); +uint8_t TxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4))); + +EnetDmaDesc_t EnetDmaRx __attribute__((aligned (128))); +EnetDmaDesc_t EnetDmaTx __attribute__ ((aligned (128))); + + +/*---------------------------------------------------------------------------*/ +void netdev_init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + ETH_InitTypeDef ETH_InitStructure; + + /* Enable ETHERNET clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx | + RCC_AHB1Periph_ETH_MAC_Rx | RCC_AHB1Periph_ETH_MAC_PTP, ENABLE); + + + /* Enable GPIOs clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | + RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG, ENABLE); + + /* Enable SYSCFG clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + /*Select RMII Interface*/ + SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII); + + /* ETHERNET pins configuration */ + /* PA + ETH_RMII_REF_CLK: PA1 + ETH_RMII_MDIO: PA2 + ETH_RMII_MDINT: PA3 + ETH_RMII_CRS_DV: PA7 + */ + + /* Configure PA1, PA2, PA3 and PA7*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_7; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Connect PA1, PA2, PA3 and PA7 to ethernet module*/ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH); + + /* PB + ETH_RMII_TX_EN: PG11 + */ + + /* Configure PG11*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* Connect PG11 to ethernet module*/ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH); + + /* PC + ETH_RMII_MDC: PC1 + ETH_RMII_RXD0: PC4 + ETH_RMII_RXD1: PC5 + */ + + /* Configure PC1, PC4 and PC5*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Connect PC1, PC4 and PC5 to ethernet module*/ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH); + + /* PG + ETH_RMII_TXD0: PG13 + ETH_RMII_TXD1: PG14 + */ + + /* Configure PG13 and PG14*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* Connect PG13 and PG14 to ethernet module*/ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH); + + /* Reset ETHERNET on AHB Bus */ + ETH_DeInit(); + + /* Software reset */ + ETH_SoftwareReset(); + + /* Wait for software reset */ + while(ETH_GetSoftwareResetStatus()==SET); + + /* ETHERNET Configuration ------------------------------------------------------*/ + /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */ + ETH_StructInit(Ð_InitStructure); + + /* Fill ETH_InitStructure parametrs */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable ; + ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; + ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable; + ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; + ETH_InitStructure.ETH_Speed = ETH_Speed_100M; + + unsigned int PhyAddr; + union { + uint32_t HI_LO; + struct + { + uint16_t LO; + uint16_t HI; + }; + } PHYID; + for(PhyAddr = 0; 32 > PhyAddr; PhyAddr++) + { + // datasheet for the ks8721bl ethernet controller (http://www.micrel.com/_PDF/Ethernet/datasheets/ks8721bl-sl.pdf) + // page 20 --> PHY Identifier 1 and 2 + PHYID.HI = ETH_ReadPHYRegister(PhyAddr,2); // 0x0022 + PHYID.LO = ETH_ReadPHYRegister(PhyAddr,3); // 0x1619 + if ((0x00221619 == PHYID.HI_LO) || (0x0007C0F1 == PHYID.HI_LO)) + break; + } + if (32 < PhyAddr) + { + ASSERT_RT(BLT_FALSE); + } + /* Configure Ethernet */ + if(0 == ETH_Init(Ð_InitStructure, PhyAddr)) + { + ASSERT_RT(BLT_FALSE); + } + + netdev_TxDscrInit(); + netdev_RxDscrInit(); + ETH_Start(); +} + + +/*---------------------------------------------------------------------------*/ +void netdev_init_mac(void) +{ + struct uip_eth_addr macAddress; + + /* set the default MAC address */ + macAddress.addr[0] = NETDEV_DEFAULT_MACADDR0; + macAddress.addr[1] = NETDEV_DEFAULT_MACADDR1; + macAddress.addr[2] = NETDEV_DEFAULT_MACADDR2; + macAddress.addr[3] = NETDEV_DEFAULT_MACADDR3; + macAddress.addr[4] = NETDEV_DEFAULT_MACADDR4; + macAddress.addr[5] = NETDEV_DEFAULT_MACADDR5; + uip_setethaddr(macAddress); +} + + +/*---------------------------------------------------------------------------*/ +unsigned int netdev_read(void) +{ + uint32_t size; + /*check for validity*/ + if(0 == EnetDmaRx.Rx.RxDesc0.OWN) + { + /*Get the size of the packet*/ + size = EnetDmaRx.Rx.RxDesc0.FL; // CRC + memcpy(uip_buf, RxBuff, size); //string.h library*/ + } + else + { + return 0; + } + /* Give the buffer back to ENET */ + EnetDmaRx.Rx.RxDesc0.OWN = 1; + /* Start the receive operation */ + ETH->DMARPDR = 1; + /* Return no error */ + return size; +} + + +/*---------------------------------------------------------------------------*/ +void netdev_send(void) +{ + while(EnetDmaTx.Tx.TxDesc0.OWN); + + /* Copy the application buffer to the driver buffer + Using this MEMCOPY_L2L_BY4 makes the copy routine faster + than memcpy */ + memcpy(TxBuff, uip_buf, uip_len); + + /* Assign ENET address to Temp Tx Array */ + EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff; + + /* Setting the Frame Length*/ + EnetDmaTx.Tx.TxDesc0.Data = 0; + EnetDmaTx.Tx.TxDesc0.TCH = 1; + EnetDmaTx.Tx.TxDesc0.LSEG = 1; + EnetDmaTx.Tx.TxDesc0.FS = 1; + EnetDmaTx.Tx.TxDesc0.DC = 0; + EnetDmaTx.Tx.TxDesc0.DP = 0; + + EnetDmaTx.Tx.TxDesc1.Data = 0; + EnetDmaTx.Tx.TxDesc1.TBS1 = (uip_len&0xFFF); + + /* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/ + EnetDmaTx.Tx.TxDesc0.OWN = 1; + + /* Start the transmit operation */ + ETH->DMATPDR = 1; +} + + +/*---------------------------------------------------------------------------*/ +static void netdev_RxDscrInit(void) +{ + /* Initialization */ + /* Assign temp Rx array to the ENET buffer */ + EnetDmaRx.Rx.pBuffer = (uint32_t *)RxBuff; + + /* Initialize RX ENET Status and control */ + EnetDmaRx.Rx.RxDesc0.Data = 0; + + /* Initialize the next descriptor- In our case its single descriptor */ + EnetDmaRx.Rx.pEnetDmaNextDesc = &EnetDmaRx; + + EnetDmaRx.Rx.RxDesc1.Data = 0; + EnetDmaRx.Rx.RxDesc1.RER = 0; // end of ring + EnetDmaRx.Rx.RxDesc1.RCH = 1; // end of ring + + /* Set the max packet size */ + EnetDmaRx.Rx.RxDesc1.RBS1 = UIP_CONF_BUFFER_SIZE; + + /* Setting the VALID bit */ + EnetDmaRx.Rx.RxDesc0.OWN = 1; + /* Setting the RX NEXT Descriptor Register inside the ENET */ + ETH->DMARDLAR = (uint32_t)&EnetDmaRx; +} + + +/*---------------------------------------------------------------------------*/ +static void netdev_TxDscrInit(void) +{ + /* ENET Start Address */ + EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff; + + /* Next Descriptor Address */ + EnetDmaTx.Tx.pEnetDmaNextDesc = &EnetDmaTx; + + /* Initialize ENET status and control */ + EnetDmaTx.Tx.TxDesc0.TCH = 1; + EnetDmaTx.Tx.TxDesc0.Data = 0; + EnetDmaTx.Tx.TxDesc1.Data = 0; + /* Tx next set to Tx descriptor base */ + ETH->DMATDLAR = (uint32_t)&EnetDmaTx; + +} diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/netdev.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/netdev.h new file mode 100644 index 00000000..4ea59ce5 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/netdev.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Adam Dunkels. + * 4. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: netdev.h,v 1.1 2002/01/10 06:22:56 adam Exp $ + * + */ + +#ifndef __NETDEV_H__ +#define __NETDEV_H__ + +void netdev_init(void); +void netdev_init_mac(void); +unsigned int netdev_read(void); +void netdev_send(void); + +#endif /* __NETDEV_H__ */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/uip-conf.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/uip-conf.h new file mode 100644 index 00000000..fd9ba0dd --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Boot/lib/uip/uip-conf.h @@ -0,0 +1,151 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef unsigned char u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef unsigned short u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 1 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 1 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1600 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 0 + +/* Here we include the header file for the application(s) we use in + our project. */ +#include "boot.h" +#include "net.h" + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/bin/demoprog_olimex_stm32e407.elf b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/bin/demoprog_olimex_stm32e407.elf index 7c2bf8ff..2764b8f5 100644 Binary files a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/bin/demoprog_olimex_stm32e407.elf and b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/bin/demoprog_olimex_stm32e407.elf differ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/bin/demoprog_olimex_stm32e407.map b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/bin/demoprog_olimex_stm32e407.map index 84fd44ac..53443c5b 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/bin/demoprog_olimex_stm32e407.map +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/bin/demoprog_olimex_stm32e407.map @@ -1,5 +1,7 @@ Archive member included because of file (symbol) +C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + THUMB Debug/../../obj/netdev.o (memcpy) C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) (__do_debug_operation_mempoll) C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) @@ -961,8 +963,6 @@ Discarded input sections 0x00000000 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o .text.RCC_AHB3PeriphClockCmd 0x00000000 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o - .text.RCC_AHB1PeriphResetCmd - 0x00000000 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o .text.RCC_AHB2PeriphResetCmd 0x00000000 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o .text.RCC_AHB3PeriphResetCmd @@ -1297,24 +1297,10 @@ Discarded input sections 0x00000000 0xc THUMB Debug/../../obj/stm32f4xx_syscfg.o .text.SYSCFG_EXTILineConfig 0x00000000 0x40 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .text.SYSCFG_ETH_MediaInterfaceConfig - 0x00000000 0xc THUMB Debug/../../obj/stm32f4xx_syscfg.o .text.SYSCFG_CompensationCellCmd 0x00000000 0xc THUMB Debug/../../obj/stm32f4xx_syscfg.o .text.SYSCFG_GetCompensationCellStatus 0x00000000 0x10 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_frame 0x00000000 0x88 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_info 0x00000000 0x2b7 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_abbrev 0x00000000 0x177 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_loc 0x00000000 0xe6 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_aranges - 0x00000000 0x48 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_ranges 0x00000000 0x38 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_line 0x00000000 0x27d THUMB Debug/../../obj/stm32f4xx_syscfg.o - .debug_str 0x00000000 0x354 THUMB Debug/../../obj/stm32f4xx_syscfg.o - .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_syscfg.o - .ARM.attributes - 0x00000000 0x33 THUMB Debug/../../obj/stm32f4xx_syscfg.o .text 0x00000000 0x0 THUMB Debug/../../obj/stm32f4xx_tim.o .data 0x00000000 0x0 THUMB Debug/../../obj/stm32f4xx_tim.o .bss 0x00000000 0x0 THUMB Debug/../../obj/stm32f4xx_tim.o @@ -1593,6 +1579,209 @@ Discarded input sections .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_wwdg.o .ARM.attributes 0x00000000 0x33 THUMB Debug/../../obj/stm32f4xx_wwdg.o + .text 0x00000000 0x0 THUMB Debug/../../obj/stm32_eth.o + .data 0x00000000 0x0 THUMB Debug/../../obj/stm32_eth.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_HandleTxPkt + 0x00000000 0x12c THUMB Debug/../../obj/stm32_eth.o + .text.ETH_HandleRxPkt + 0x00000000 0x120 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DropRxPkt + 0x00000000 0x64 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_PHYLoopBackCmd + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetFlowControlBusyStatus + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_InitiatePauseControlFrame + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_BackPressureActivationCmd + 0x00000000 0x28 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetMACFlagStatus + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetMACITStatus + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MACITConfig + 0x00000000 0x24 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MACAddressConfig + 0x00000000 0x34 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetMACAddress + 0x00000000 0x34 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MACAddressPerfectFilterCmd + 0x00000000 0x28 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MACAddressFilterConfig + 0x00000000 0x1c THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MACAddressMaskBytesFilterConfig + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescChainInit + 0x00000000 0xc4 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescRingInit + 0x00000000 0xc4 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMATxDescFlagStatus + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMATxDescCollisionCount + 0x00000000 0x8 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetDMATxDescOwnBit + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescTransmitITConfig + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescFrameSegmentConfig + 0x00000000 0x8 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescChecksumInsertionConfig + 0x00000000 0x8 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescCRCCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescEndOfRingCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescSecondAddressChainedCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescShortFramePaddingCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescTimeStampCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMATxDescBufferSizeConfig + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMARxDescChainInit + 0x00000000 0xdc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMARxDescRingInit + 0x00000000 0x14c THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMARxDescFlagStatus + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetDMARxDescOwnBit + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMARxDescFrameLength + 0x00000000 0x8 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetRxPktSize + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMARxDescReceiveITConfig + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMARxDescEndOfRingCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMARxDescSecondAddressChainedCmd + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMARxDescBufferSize + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMAFlagStatus + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMAClearFlag + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMAITStatus + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMAClearITPendingBit + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetTransmitProcessState + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetReceiveProcessState + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetFlushTransmitFIFOStatus + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMAITConfig + 0x00000000 0x24 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetDMAOverflowStatus + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetRxOverflowMissedFrameCounter + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetBufferUnavailableMissedFrameCounter + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetCurrentTxDescStartAddress + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetCurrentRxDescStartAddress + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetCurrentTxBufferAddress + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetCurrentRxBufferAddress + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_ResumeDMATransmission + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_ResumeDMAReception + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_ResetWakeUpFrameFilterRegisterPointer + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetWakeUpFrameFilterRegister + 0x00000000 0x2c THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GlobalUnicastWakeUpCmd + 0x00000000 0x28 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetPMTFlagStatus + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_WakeUpFrameDetectionCmd + 0x00000000 0x28 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MagicPacketDetectionCmd + 0x00000000 0x28 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_PowerDownCmd + 0x00000000 0x28 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MMCCounterFreezeCmd + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MMCResetOnReadCmd + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MMCCounterRolloverCmd + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MMCCountersReset + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_MMCITConfig + 0x00000000 0x64 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetMMCITStatus + 0x00000000 0x60 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetMMCRegister + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_EnablePTPTimeStampAddend + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_EnablePTPTimeStampInterruptTrigger + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_EnablePTPTimeStampUpdate + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_InitializePTPTimeStamp + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_PTPUpdateMethodConfig + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_PTPTimeStampCmd + 0x00000000 0x30 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetPTPFlagStatus + 0x00000000 0x18 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetPTPSubSecondIncrement + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetPTPTimeStampUpdate + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetPTPTimeStampAddend + 0x00000000 0x10 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_SetPTPTargetTime + 0x00000000 0x14 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_GetPTPRegister + 0x00000000 0xc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMAPTPTxDescChainInit + 0x00000000 0x120 THUMB Debug/../../obj/stm32_eth.o + .text.ETH_DMAPTPRxDescChainInit + 0x00000000 0x12c THUMB Debug/../../obj/stm32_eth.o + .text.ETH_HandlePTPTxPkt + 0x00000000 0x1dc THUMB Debug/../../obj/stm32_eth.o + .text.ETH_HandlePTPRxPkt + 0x00000000 0x14c THUMB Debug/../../obj/stm32_eth.o + .bss.DMARxDescToGet + 0x00000000 0x4 THUMB Debug/../../obj/stm32_eth.o + .bss.DMAPTPTxDescToSet + 0x00000000 0x4 THUMB Debug/../../obj/stm32_eth.o + .bss.DMATxDescToSet + 0x00000000 0x4 THUMB Debug/../../obj/stm32_eth.o + .bss.DMAPTPRxDescToGet + 0x00000000 0x4 THUMB Debug/../../obj/stm32_eth.o + .text 0x00000000 0x0 THUMB Debug/../../obj/clock-arch.o + .data 0x00000000 0x0 THUMB Debug/../../obj/clock-arch.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/clock-arch.o + .text.clock_time + 0x00000000 0x8 THUMB Debug/../../obj/clock-arch.o + .debug_frame 0x00000000 0x2c THUMB Debug/../../obj/clock-arch.o + .debug_info 0x00000000 0xcf THUMB Debug/../../obj/clock-arch.o + .debug_abbrev 0x00000000 0x8b THUMB Debug/../../obj/clock-arch.o + .debug_loc 0x00000000 0x20 THUMB Debug/../../obj/clock-arch.o + .debug_aranges + 0x00000000 0x20 THUMB Debug/../../obj/clock-arch.o + .debug_ranges 0x00000000 0x10 THUMB Debug/../../obj/clock-arch.o + .debug_line 0x00000000 0x14e THUMB Debug/../../obj/clock-arch.o + .debug_str 0x00000000 0x1c5 THUMB Debug/../../obj/clock-arch.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/clock-arch.o + .ARM.attributes + 0x00000000 0x33 THUMB Debug/../../obj/clock-arch.o + .text 0x00000000 0x0 THUMB Debug/../../obj/netdev.o + .data 0x00000000 0x0 THUMB Debug/../../obj/netdev.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/netdev.o .text 0x00000000 0x0 THUMB Debug/../../obj/boot.o .data 0x00000000 0x0 THUMB Debug/../../obj/boot.o .bss 0x00000000 0x0 THUMB Debug/../../obj/boot.o @@ -1626,6 +1815,119 @@ Discarded input sections .text 0x00000000 0x0 THUMB Debug/../../obj/vectors.o .data 0x00000000 0x0 THUMB Debug/../../obj/vectors.o .bss 0x00000000 0x0 THUMB Debug/../../obj/vectors.o + .text 0x00000000 0x0 THUMB Debug/../../obj/net.o + .data 0x00000000 0x0 THUMB Debug/../../obj/net.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/net.o + .text 0x00000000 0x0 THUMB Debug/../../obj/uip.o + .data 0x00000000 0x0 THUMB Debug/../../obj/uip.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/uip.o + .text.uip_setipid + 0x00000000 0xc THUMB Debug/../../obj/uip.o + .text.uip_unlisten + 0x00000000 0x38 THUMB Debug/../../obj/uip.o + .text.uip_connect + 0x00000000 0x108 THUMB Debug/../../obj/uip.o + .text.uip_udpchksum + 0x00000000 0xc THUMB Debug/../../obj/uip.o + .text.uip_chksum + 0x00000000 0x18 THUMB Debug/../../obj/uip.o + .text.uip_send + 0x00000000 0x2c THUMB Debug/../../obj/uip.o + .text 0x00000000 0x0 THUMB Debug/../../obj/uip_arp.o + .data 0x00000000 0x0 THUMB Debug/../../obj/uip_arp.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/uip_arp.o + .text.uip_arp_init + 0x00000000 0x40 THUMB Debug/../../obj/uip_arp.o + .text 0x00000000 0x0 THUMB Debug/../../obj/uip_timer.o + .data 0x00000000 0x0 THUMB Debug/../../obj/uip_timer.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/uip_timer.o + .text.timer_set + 0x00000000 0x10 THUMB Debug/../../obj/uip_timer.o + .text.timer_reset + 0x00000000 0xc THUMB Debug/../../obj/uip_timer.o + .text.timer_restart + 0x00000000 0xc THUMB Debug/../../obj/uip_timer.o + .text.timer_expired + 0x00000000 0x18 THUMB Debug/../../obj/uip_timer.o + .debug_frame 0x00000000 0x74 THUMB Debug/../../obj/uip_timer.o + .debug_info 0x00000000 0x144 THUMB Debug/../../obj/uip_timer.o + .debug_abbrev 0x00000000 0xf0 THUMB Debug/../../obj/uip_timer.o + .debug_loc 0x00000000 0xdb THUMB Debug/../../obj/uip_timer.o + .debug_aranges + 0x00000000 0x38 THUMB Debug/../../obj/uip_timer.o + .debug_ranges 0x00000000 0x28 THUMB Debug/../../obj/uip_timer.o + .debug_line 0x00000000 0x127 THUMB Debug/../../obj/uip_timer.o + .debug_str 0x00000000 0x189 THUMB Debug/../../obj/uip_timer.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/uip_timer.o + .ARM.attributes + 0x00000000 0x33 THUMB Debug/../../obj/uip_timer.o + .text 0x00000000 0x0 THUMB Debug/../../obj/uip-fw.o + .data 0x00000000 0x0 THUMB Debug/../../obj/uip-fw.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/uip-fw.o + .text.uip_fw_init + 0x00000000 0x34 THUMB Debug/../../obj/uip-fw.o + .text.uip_fw_output + 0x00000000 0xe8 THUMB Debug/../../obj/uip-fw.o + .text.uip_fw_forward + 0x00000000 0x1dc THUMB Debug/../../obj/uip-fw.o + .text.uip_fw_register + 0x00000000 0x10 THUMB Debug/../../obj/uip-fw.o + .text.uip_fw_default + 0x00000000 0xc THUMB Debug/../../obj/uip-fw.o + .text.uip_fw_periodic + 0x00000000 0x28 THUMB Debug/../../obj/uip-fw.o + .bss.netifs 0x00000000 0x4 THUMB Debug/../../obj/uip-fw.o + .bss.defaultnetif + 0x00000000 0x4 THUMB Debug/../../obj/uip-fw.o + .bss.fwcache 0x00000000 0x1c THUMB Debug/../../obj/uip-fw.o + .debug_frame 0x00000000 0x90 THUMB Debug/../../obj/uip-fw.o + .debug_info 0x00000000 0x6f7 THUMB Debug/../../obj/uip-fw.o + .debug_abbrev 0x00000000 0x295 THUMB Debug/../../obj/uip-fw.o + .debug_loc 0x00000000 0x18c THUMB Debug/../../obj/uip-fw.o + .debug_aranges + 0x00000000 0x48 THUMB Debug/../../obj/uip-fw.o + .debug_ranges 0x00000000 0x68 THUMB Debug/../../obj/uip-fw.o + .debug_line 0x00000000 0x246 THUMB Debug/../../obj/uip-fw.o + .debug_str 0x00000000 0x389 THUMB Debug/../../obj/uip-fw.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/uip-fw.o + .ARM.attributes + 0x00000000 0x33 THUMB Debug/../../obj/uip-fw.o + .text 0x00000000 0x0 THUMB Debug/../../obj/uiplib.o + .data 0x00000000 0x0 THUMB Debug/../../obj/uiplib.o + .bss 0x00000000 0x0 THUMB Debug/../../obj/uiplib.o + .text.uiplib_ipaddrconv + 0x00000000 0x370 THUMB Debug/../../obj/uiplib.o + .debug_frame 0x00000000 0x2c THUMB Debug/../../obj/uiplib.o + .debug_info 0x00000000 0xc5 THUMB Debug/../../obj/uiplib.o + .debug_abbrev 0x00000000 0x64 THUMB Debug/../../obj/uiplib.o + .debug_loc 0x00000000 0xf89 THUMB Debug/../../obj/uiplib.o + .debug_aranges + 0x00000000 0x20 THUMB Debug/../../obj/uiplib.o + .debug_ranges 0x00000000 0x10 THUMB Debug/../../obj/uiplib.o + .debug_line 0x00000000 0x177 THUMB Debug/../../obj/uiplib.o + .debug_str 0x00000000 0x177 THUMB Debug/../../obj/uiplib.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/uiplib.o + .ARM.attributes + 0x00000000 0x33 THUMB Debug/../../obj/uiplib.o + .text.libc 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .data.libc 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .bss.libc 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .text.libc.longjmp + 0x00000000 0x14 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .text.libc.memcpy_fast + 0x00000000 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .text.libc.memcpy_small + 0x00000000 0x1c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .text.libc.__aeabi_memset + 0x00000000 0x74 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .text.libc.setjmp + 0x00000000 0xc C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .text.libc.strcpy + 0x00000000 0x4c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .text.libc.strcmp + 0x00000000 0x58 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .text.libc.strlen + 0x00000000 0x70 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) .text 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) .data 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) .bss 0x00000000 0x0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) @@ -1788,7 +2090,7 @@ Memory Configuration Name Origin Length Attributes UNPLACED_SECTIONS 0xffffffff 0x00000000 xw -FLASH 0x08008000 0x000f8000 xr +FLASH 0x0800c000 0x000f4000 xr DATA_SRAM 0x10000000 0x00010000 xw SYSTEM 0x1fff0000 0x00007a10 xw OPTION 0x1fffc000 0x00000008 xw @@ -1814,8 +2116,8 @@ CM3_System_Control_Space 0xe000e000 0x00001000 xw Linker script and memory map - 0x080090a4 __do_debug_operation = __do_debug_operation_mempoll - 0x08008000 __FLASH_segment_start__ = 0x8008000 + 0x0800f4c4 __do_debug_operation = __do_debug_operation_mempoll + 0x0800c000 __FLASH_segment_start__ = 0x800c000 0x08100000 __FLASH_segment_end__ = 0x8100000 0x10000000 __DATA_SRAM_segment_start__ = 0x10000000 0x10010000 __DATA_SRAM_segment_end__ = 0x10010000 @@ -1875,141 +2177,250 @@ Linker script and memory map 0x20000000 __vectors_ram_end__ = (__vectors_ram_start__ + SIZEOF (.vectors_ram)) 0x20000000 __vectors_ram_load_end__ = __vectors_ram_end__ 0x00000001 . = ASSERT (((__vectors_ram_end__ >= __RAM_segment_start__) && (__vectors_ram_end__ <= __RAM_segment_end__)), error: .vectors_ram is too large to fit in RAM memory segment) - 0x08008000 __vectors_load_start__ = ALIGN (__FLASH_segment_start__, 0x100) + 0x0800c000 __vectors_load_start__ = ALIGN (__FLASH_segment_start__, 0x100) -.vectors 0x08008000 0x18c - 0x08008000 __vectors_start__ = . +.vectors 0x0800c000 0x18c + 0x0800c000 __vectors_start__ = . *(.vectors .vectors.*) - .vectors 0x08008000 0x18c THUMB Debug/../../obj/vectors.o - 0x08008000 _vectors - 0x0800818c __vectors_end__ = (__vectors_start__ + SIZEOF (.vectors)) - 0x0800818c __vectors_load_end__ = __vectors_end__ + .vectors 0x0800c000 0x18c THUMB Debug/../../obj/vectors.o + 0x0800c000 _vectors + 0x0800c18c __vectors_end__ = (__vectors_start__ + SIZEOF (.vectors)) + 0x0800c18c __vectors_load_end__ = __vectors_end__ 0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= __FLASH_segment_end__)), error: .vectors is too large to fit in FLASH memory segment) - 0x0800818c __init_load_start__ = ALIGN (__vectors_end__, 0x4) + 0x0800c18c __init_load_start__ = ALIGN (__vectors_end__, 0x4) -.init 0x0800818c 0x154 - 0x0800818c __init_start__ = . +.init 0x0800c18c 0x154 + 0x0800c18c __init_start__ = . *(.init .init.*) - .init 0x0800818c 0x154 THUMB Debug/../../obj/cstart.o - 0x0800818c _start - 0x0800820e exit - 0x08008232 reset_handler - 0x080082e0 __init_end__ = (__init_start__ + SIZEOF (.init)) - 0x080082e0 __init_load_end__ = __init_end__ + .init 0x0800c18c 0x154 THUMB Debug/../../obj/cstart.o + 0x0800c18c _start + 0x0800c20e exit + 0x0800c232 reset_handler + 0x0800c2e0 __init_end__ = (__init_start__ + SIZEOF (.init)) + 0x0800c2e0 __init_load_end__ = __init_end__ 0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= __FLASH_segment_end__)), error: .init is too large to fit in FLASH memory segment) - 0x080082e0 __text_load_start__ = ALIGN (__init_end__, 0x4) + 0x0800c2e0 __text_load_start__ = ALIGN (__init_end__, 0x4) -.text 0x080082e0 0xe08 - 0x080082e0 __text_start__ = . +.text 0x0800c2e0 0x3228 + 0x0800c2e0 __text_start__ = . *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*) .glue_7 0x00000000 0x0 linker stubs .glue_7t 0x00000000 0x0 linker stubs .text.SystemInit - 0x080082e0 0x118 THUMB Debug/../../obj/system_stm32f4xx.o - 0x080082e0 SystemInit + 0x0800c2e0 0x118 THUMB Debug/../../obj/system_stm32f4xx.o + 0x0800c2e0 SystemInit .text.CAN_DeInit - 0x080083f8 0x44 THUMB Debug/../../obj/stm32f4xx_can.o - 0x080083f8 CAN_DeInit + 0x0800c3f8 0x44 THUMB Debug/../../obj/stm32f4xx_can.o + 0x0800c3f8 CAN_DeInit .text.CAN_Init - 0x0800843c 0x11c THUMB Debug/../../obj/stm32f4xx_can.o - 0x0800843c CAN_Init + 0x0800c43c 0x11c THUMB Debug/../../obj/stm32f4xx_can.o + 0x0800c43c CAN_Init .text.CAN_FilterInit - 0x08008558 0x134 THUMB Debug/../../obj/stm32f4xx_can.o - 0x08008558 CAN_FilterInit + 0x0800c558 0x134 THUMB Debug/../../obj/stm32f4xx_can.o + 0x0800c558 CAN_FilterInit .text.CAN_StructInit - 0x0800868c 0x28 THUMB Debug/../../obj/stm32f4xx_can.o - 0x0800868c CAN_StructInit + 0x0800c68c 0x28 THUMB Debug/../../obj/stm32f4xx_can.o + 0x0800c68c CAN_StructInit .text.CAN_Receive - 0x080086b4 0xbc THUMB Debug/../../obj/stm32f4xx_can.o - 0x080086b4 CAN_Receive + 0x0800c6b4 0xbc THUMB Debug/../../obj/stm32f4xx_can.o + 0x0800c6b4 CAN_Receive .text.CAN_MessagePending - 0x08008770 0x1c THUMB Debug/../../obj/stm32f4xx_can.o - 0x08008770 CAN_MessagePending + 0x0800c770 0x1c THUMB Debug/../../obj/stm32f4xx_can.o + 0x0800c770 CAN_MessagePending .text.GPIO_Init - 0x0800878c 0x160 THUMB Debug/../../obj/stm32f4xx_gpio.o - 0x0800878c GPIO_Init + 0x0800c78c 0x160 THUMB Debug/../../obj/stm32f4xx_gpio.o + 0x0800c78c GPIO_Init .text.GPIO_SetBits - 0x080088ec 0x4 THUMB Debug/../../obj/stm32f4xx_gpio.o - 0x080088ec GPIO_SetBits + 0x0800c8ec 0x4 THUMB Debug/../../obj/stm32f4xx_gpio.o + 0x0800c8ec GPIO_SetBits .text.GPIO_ResetBits - 0x080088f0 0x4 THUMB Debug/../../obj/stm32f4xx_gpio.o - 0x080088f0 GPIO_ResetBits + 0x0800c8f0 0x4 THUMB Debug/../../obj/stm32f4xx_gpio.o + 0x0800c8f0 GPIO_ResetBits .text.GPIO_PinAFConfig - 0x080088f4 0x38 THUMB Debug/../../obj/stm32f4xx_gpio.o - 0x080088f4 GPIO_PinAFConfig + 0x0800c8f4 0x38 THUMB Debug/../../obj/stm32f4xx_gpio.o + 0x0800c8f4 GPIO_PinAFConfig .text.RCC_GetClocksFreq - 0x0800892c 0xd8 THUMB Debug/../../obj/stm32f4xx_rcc.o - 0x0800892c RCC_GetClocksFreq + 0x0800c92c 0xd8 THUMB Debug/../../obj/stm32f4xx_rcc.o + 0x0800c92c RCC_GetClocksFreq .text.RCC_AHB1PeriphClockCmd - 0x08008a04 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o - 0x08008a04 RCC_AHB1PeriphClockCmd + 0x0800ca04 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o + 0x0800ca04 RCC_AHB1PeriphClockCmd .text.RCC_APB1PeriphClockCmd - 0x08008a28 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o - 0x08008a28 RCC_APB1PeriphClockCmd + 0x0800ca28 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o + 0x0800ca28 RCC_APB1PeriphClockCmd .text.RCC_APB2PeriphClockCmd - 0x08008a4c 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o - 0x08008a4c RCC_APB2PeriphClockCmd + 0x0800ca4c 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o + 0x0800ca4c RCC_APB2PeriphClockCmd + .text.RCC_AHB1PeriphResetCmd + 0x0800ca70 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o + 0x0800ca70 RCC_AHB1PeriphResetCmd .text.RCC_APB1PeriphResetCmd - 0x08008a70 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o - 0x08008a70 RCC_APB1PeriphResetCmd + 0x0800ca94 0x24 THUMB Debug/../../obj/stm32f4xx_rcc.o + 0x0800ca94 RCC_APB1PeriphResetCmd + .text.SYSCFG_ETH_MediaInterfaceConfig + 0x0800cab8 0xc THUMB Debug/../../obj/stm32f4xx_syscfg.o + 0x0800cab8 SYSCFG_ETH_MediaInterfaceConfig .text.USART_Init - 0x08008a94 0x108 THUMB Debug/../../obj/stm32f4xx_usart.o - 0x08008a94 USART_Init + 0x0800cac4 0x108 THUMB Debug/../../obj/stm32f4xx_usart.o + 0x0800cac4 USART_Init .text.USART_Cmd - 0x08008b9c 0x20 THUMB Debug/../../obj/stm32f4xx_usart.o - 0x08008b9c USART_Cmd + 0x0800cbcc 0x20 THUMB Debug/../../obj/stm32f4xx_usart.o + 0x0800cbcc USART_Cmd .text.USART_ReceiveData - 0x08008bbc 0xc THUMB Debug/../../obj/stm32f4xx_usart.o - 0x08008bbc USART_ReceiveData + 0x0800cbec 0xc THUMB Debug/../../obj/stm32f4xx_usart.o + 0x0800cbec USART_ReceiveData .text.USART_GetFlagStatus - 0x08008bc8 0xc THUMB Debug/../../obj/stm32f4xx_usart.o - 0x08008bc8 USART_GetFlagStatus - .text.BootActivate - 0x08008bd4 0x28 THUMB Debug/../../obj/boot.o + 0x0800cbf8 0xc THUMB Debug/../../obj/stm32f4xx_usart.o + 0x0800cbf8 USART_GetFlagStatus + .text.ETH_DeInit + 0x0800cc04 0x1c THUMB Debug/../../obj/stm32_eth.o + 0x0800cc04 ETH_DeInit + .text.ETH_StructInit + 0x0800cc20 0xa8 THUMB Debug/../../obj/stm32_eth.o + 0x0800cc20 ETH_StructInit + .text.ETH_ReadPHYRegister + 0x0800ccc8 0x78 THUMB Debug/../../obj/stm32_eth.o + 0x0800ccc8 ETH_ReadPHYRegister + .text.ETH_WritePHYRegister + 0x0800cd40 0x70 THUMB Debug/../../obj/stm32_eth.o + 0x0800cd40 ETH_WritePHYRegister + .text.ETH_Init + 0x0800cdb0 0x2f0 THUMB Debug/../../obj/stm32_eth.o + 0x0800cdb0 ETH_Init + .text.ETH_MACTransmissionCmd + 0x0800d0a0 0x28 THUMB Debug/../../obj/stm32_eth.o + 0x0800d0a0 ETH_MACTransmissionCmd + .text.ETH_MACReceptionCmd + 0x0800d0c8 0x28 THUMB Debug/../../obj/stm32_eth.o + 0x0800d0c8 ETH_MACReceptionCmd + .text.ETH_SoftwareReset + 0x0800d0f0 0x14 THUMB Debug/../../obj/stm32_eth.o + 0x0800d0f0 ETH_SoftwareReset + .text.ETH_GetSoftwareResetStatus + 0x0800d104 0x10 THUMB Debug/../../obj/stm32_eth.o + 0x0800d104 ETH_GetSoftwareResetStatus + .text.ETH_FlushTransmitFIFO + 0x0800d114 0x14 THUMB Debug/../../obj/stm32_eth.o + 0x0800d114 ETH_FlushTransmitFIFO + .text.ETH_DMATransmissionCmd + 0x0800d128 0x28 THUMB Debug/../../obj/stm32_eth.o + 0x0800d128 ETH_DMATransmissionCmd + .text.ETH_DMAReceptionCmd + 0x0800d150 0x28 THUMB Debug/../../obj/stm32_eth.o + 0x0800d150 ETH_DMAReceptionCmd + .text.ETH_Start + 0x0800d178 0x28 THUMB Debug/../../obj/stm32_eth.o + 0x0800d178 ETH_Start + .text.netdev_init + 0x0800d1a0 0x26c THUMB Debug/../../obj/netdev.o + 0x0800d1a0 netdev_init + .text.netdev_init_mac + 0x0800d40c 0x30 THUMB Debug/../../obj/netdev.o + 0x0800d40c netdev_init_mac + .text.netdev_read + 0x0800d43c 0x5c THUMB Debug/../../obj/netdev.o + 0x0800d43c netdev_read + .text.netdev_send + 0x0800d498 0x70 THUMB Debug/../../obj/netdev.o + 0x0800d498 netdev_send .text.UartReceiveByte - 0x08008bfc 0x34 THUMB Debug/../../obj/boot.o + 0x0800d508 0x34 THUMB Debug/../../obj/boot.o .text.BootComInit - 0x08008c30 0x224 THUMB Debug/../../obj/boot.o - 0x08008c30 BootComInit + 0x0800d53c 0x224 THUMB Debug/../../obj/boot.o + 0x0800d53c BootComInit + .text.BootActivate + 0x0800d760 0x28 THUMB Debug/../../obj/boot.o + 0x0800d760 BootActivate .text.BootComCheckActivationRequest - 0x08008e54 0xf0 THUMB Debug/../../obj/boot.o - 0x08008e54 BootComCheckActivationRequest + 0x0800d788 0xf0 THUMB Debug/../../obj/boot.o + 0x0800d788 BootComCheckActivationRequest .text.IrqInterruptEnable - 0x08008f44 0x4 THUMB Debug/../../obj/irq.o - 0x08008f44 IrqInterruptEnable - .text.LedInit 0x08008f48 0x50 THUMB Debug/../../obj/led.o - 0x08008f48 LedInit + 0x0800d878 0x4 THUMB Debug/../../obj/irq.o + 0x0800d878 IrqInterruptEnable + .text.LedInit 0x0800d87c 0x50 THUMB Debug/../../obj/led.o + 0x0800d87c LedInit .text.LedToggle - 0x08008f98 0x70 THUMB Debug/../../obj/led.o - 0x08008f98 LedToggle - .text.main 0x08009008 0x20 THUMB Debug/../../obj/main.o - 0x08009008 main + 0x0800d8cc 0x70 THUMB Debug/../../obj/led.o + 0x0800d8cc LedToggle + .text.main 0x0800d93c 0x28 THUMB Debug/../../obj/main.o + 0x0800d93c main .text.TimerSet - 0x08009028 0xc THUMB Debug/../../obj/timer.o - 0x08009028 TimerSet + 0x0800d964 0xc THUMB Debug/../../obj/timer.o + 0x0800d964 TimerSet .text.TimerInit - 0x08009034 0x4c THUMB Debug/../../obj/timer.o - 0x08009034 TimerInit + 0x0800d970 0x4c THUMB Debug/../../obj/timer.o + 0x0800d970 TimerInit .text.TimerGet - 0x08009080 0xc THUMB Debug/../../obj/timer.o - 0x08009080 TimerGet + 0x0800d9bc 0xc THUMB Debug/../../obj/timer.o + 0x0800d9bc TimerGet .text.TimerISRHandler - 0x0800908c 0x14 THUMB Debug/../../obj/timer.o - 0x0800908c TimerISRHandler + 0x0800d9c8 0x14 THUMB Debug/../../obj/timer.o + 0x0800d9c8 TimerISRHandler .text.UnusedISR - 0x080090a0 0x4 THUMB Debug/../../obj/vectors.o - 0x080090a0 UnusedISR + 0x0800d9dc 0x4 THUMB Debug/../../obj/vectors.o + 0x0800d9dc UnusedISR + .text.NetInit 0x0800d9e0 0x78 THUMB Debug/../../obj/net.o + 0x0800d9e0 NetInit + .text.NetApp 0x0800da58 0x38 THUMB Debug/../../obj/net.o + 0x0800da58 NetApp + .text.NetTask 0x0800da90 0x114 THUMB Debug/../../obj/net.o + 0x0800da90 NetTask + .text.chksum 0x0800dba4 0xc8 THUMB Debug/../../obj/uip.o + .text.uip_add32 + 0x0800dc6c 0x7c THUMB Debug/../../obj/uip.o + 0x0800dc6c uip_add32 + .text.uip_add_rcv_nxt + 0x0800dce8 0x30 THUMB Debug/../../obj/uip.o + .text.uip_init + 0x0800dd18 0x38 THUMB Debug/../../obj/uip.o + 0x0800dd18 uip_init + .text.uip_listen + 0x0800dd50 0x38 THUMB Debug/../../obj/uip.o + 0x0800dd50 uip_listen + .text.htons 0x0800dd88 0xc THUMB Debug/../../obj/uip.o + 0x0800dd88 htons + .text.upper_layer_chksum + 0x0800dd94 0x40 THUMB Debug/../../obj/uip.o + .text.uip_tcpchksum + 0x0800ddd4 0xc THUMB Debug/../../obj/uip.o + 0x0800ddd4 uip_tcpchksum + .text.uip_ipchksum + 0x0800dde0 0x24 THUMB Debug/../../obj/uip.o + 0x0800dde0 uip_ipchksum + .text.uip_process + 0x0800de04 0xd28 THUMB Debug/../../obj/uip.o + 0x0800de04 uip_process + .text.uip_arp_update + 0x0800eb2c 0x40c THUMB Debug/../../obj/uip_arp.o + .text.uip_arp_timer + 0x0800ef38 0x74 THUMB Debug/../../obj/uip_arp.o + 0x0800ef38 uip_arp_timer + .text.uip_arp_arpin + 0x0800efac 0x14c THUMB Debug/../../obj/uip_arp.o + 0x0800efac uip_arp_arpin + .text.uip_arp_out + 0x0800f0f8 0x314 THUMB Debug/../../obj/uip_arp.o + 0x0800f0f8 uip_arp_out + .text.libc.memcpy + 0x0800f40c 0x48 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + 0x0800f40c __aeabi_memcpy + 0x0800f40c __aeabi_memcpy4 + 0x0800f40c __aeabi_memcpy8 + 0x0800f40c memcpy + .text.libc.memset + 0x0800f454 0x70 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + 0x0800f454 memset .text.libdebugio.__do_debug_operation_mempoll - 0x080090a4 0x3c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - 0x080090a4 __do_debug_operation_mempoll + 0x0800f4c4 0x3c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + 0x0800f4c4 __do_debug_operation_mempoll .text.libc.__debug_io_lock - 0x080090e0 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) - 0x080090e0 __debug_io_lock + 0x0800f500 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + 0x0800f500 __debug_io_lock .text.libc.__debug_io_unlock - 0x080090e4 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) - 0x080090e4 __debug_io_unlock - 0x080090e8 __text_end__ = (__text_start__ + SIZEOF (.text)) - 0x080090e8 __text_load_end__ = __text_end__ + 0x0800f504 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + 0x0800f504 __debug_io_unlock + 0x0800f508 __text_end__ = (__text_start__ + SIZEOF (.text)) + 0x0800f508 __text_load_end__ = __text_end__ .vfp11_veneer 0x00000000 0x0 .vfp11_veneer 0x00000000 0x0 linker stubs @@ -2020,56 +2431,58 @@ Linker script and memory map .iplt 0x00000000 0x0 .iplt 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f4xx.o 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= __FLASH_segment_end__)), error: .text is too large to fit in FLASH memory segment) - 0x080090e8 __dtors_load_start__ = ALIGN (__text_end__, 0x4) + 0x0800f508 __dtors_load_start__ = ALIGN (__text_end__, 0x4) -.dtors 0x080090e8 0x0 - 0x080090e8 __dtors_start__ = . +.dtors 0x0800f508 0x0 + 0x0800f508 __dtors_start__ = . *(SORT(.dtors.*)) *(.dtors) *(.fini_array .fini_array.*) - 0x080090e8 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors)) - 0x080090e8 __dtors_load_end__ = __dtors_end__ + 0x0800f508 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors)) + 0x0800f508 __dtors_load_end__ = __dtors_end__ 0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= __FLASH_segment_end__)), error: .dtors is too large to fit in FLASH memory segment) - 0x080090e8 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4) + 0x0800f508 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4) -.ctors 0x080090e8 0x0 - 0x080090e8 __ctors_start__ = . +.ctors 0x0800f508 0x0 + 0x0800f508 __ctors_start__ = . *(SORT(.ctors.*)) *(.ctors) *(.init_array .init_array.*) - 0x080090e8 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors)) - 0x080090e8 __ctors_load_end__ = __ctors_end__ + 0x0800f508 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors)) + 0x0800f508 __ctors_load_end__ = __ctors_end__ 0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= __FLASH_segment_end__)), error: .ctors is too large to fit in FLASH memory segment) - 0x080090e8 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4) + 0x0800f508 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4) -.rodata 0x080090e8 0x24 - 0x080090e8 __rodata_start__ = . +.rodata 0x0800f508 0x2c + 0x0800f508 __rodata_start__ = . *(.rodata .rodata.* .gnu.linkonce.r.*) .rodata.canTiming - 0x080090e8 0x24 THUMB Debug/../../obj/boot.o - 0x0800910c __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata)) - 0x0800910c __rodata_load_end__ = __rodata_end__ + 0x0800f508 0x24 THUMB Debug/../../obj/boot.o + .rodata.broadcast_ethaddr + 0x0800f52c 0x8 THUMB Debug/../../obj/uip_arp.o + 0x0800f534 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata)) + 0x0800f534 __rodata_load_end__ = __rodata_end__ -.rel.dyn 0x08008000 0x0 +.rel.dyn 0x0800c000 0x0 .rel.iplt 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f4xx.o 0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= __FLASH_segment_end__)), error: .rodata is too large to fit in FLASH memory segment) - 0x0800910c __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4) + 0x0800f534 __ARM.exidx_load_start__ = ALIGN (__rodata_end__, 0x4) -.ARM.exidx 0x0800910c 0x0 - 0x0800910c __ARM.exidx_start__ = . - 0x0800910c __exidx_start = __ARM.exidx_start__ +.ARM.exidx 0x0800f534 0x0 + 0x0800f534 __ARM.exidx_start__ = . + 0x0800f534 __exidx_start = __ARM.exidx_start__ *(.ARM.exidx .ARM.exidx.*) - 0x0800910c __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx)) - 0x0800910c __exidx_end = __ARM.exidx_end__ - 0x0800910c __ARM.exidx_load_end__ = __ARM.exidx_end__ + 0x0800f534 __ARM.exidx_end__ = (__ARM.exidx_start__ + SIZEOF (.ARM.exidx)) + 0x0800f534 __exidx_end = __ARM.exidx_end__ + 0x0800f534 __ARM.exidx_load_end__ = __ARM.exidx_end__ 0x00000001 . = ASSERT (((__ARM.exidx_end__ >= __FLASH_segment_start__) && (__ARM.exidx_end__ <= __FLASH_segment_end__)), error: .ARM.exidx is too large to fit in FLASH memory segment) - 0x0800910c __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4) + 0x0800f534 __fast_load_start__ = ALIGN (__ARM.exidx_end__, 0x4) -.fast 0x20000000 0x0 load address 0x0800910c +.fast 0x20000000 0x0 load address 0x0800f534 0x20000000 __fast_start__ = . *(.fast .fast.*) 0x20000000 __fast_end__ = (__fast_start__ + SIZEOF (.fast)) - 0x0800910c __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast)) + 0x0800f534 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast)) 0x00000001 . = ASSERT (((__fast_load_end__ >= __FLASH_segment_start__) && (__fast_load_end__ <= __FLASH_segment_end__)), error: .fast is too large to fit in FLASH memory segment) .fast_run 0x20000000 0x0 @@ -2078,9 +2491,9 @@ Linker script and memory map 0x20000000 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run)) 0x20000000 __fast_run_load_end__ = __fast_run_end__ 0x00000001 . = ASSERT (((__fast_run_end__ >= __RAM_segment_start__) && (__fast_run_end__ <= __RAM_segment_end__)), error: .fast_run is too large to fit in RAM memory segment) - 0x0800910c __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4) + 0x0800f534 __data_load_start__ = ALIGN ((__fast_load_start__ + SIZEOF (.fast)), 0x4) -.data 0x20000000 0x14 load address 0x0800910c +.data 0x20000000 0x14 load address 0x0800f534 0x20000000 __data_start__ = . *(.data .data.* .gnu.linkonce.d.*) .data.SystemCoreClock @@ -2089,13 +2502,13 @@ Linker script and memory map .data.APBAHBPrescTable 0x20000004 0x10 THUMB Debug/../../obj/stm32f4xx_rcc.o 0x20000014 __data_end__ = (__data_start__ + SIZEOF (.data)) - 0x08009120 __data_load_end__ = (__data_load_start__ + SIZEOF (.data)) + 0x0800f548 __data_load_end__ = (__data_load_start__ + SIZEOF (.data)) .igot.plt 0x00000000 0x0 .igot.plt 0x00000000 0x0 THUMB Debug/../../obj/system_stm32f4xx.o 0x00000001 . = ASSERT (((__data_load_end__ >= __FLASH_segment_start__) && (__data_load_end__ <= __FLASH_segment_end__)), error: .data is too large to fit in FLASH memory segment) -.data_run 0x20000000 0x14 load address 0x0800910c +.data_run 0x20000000 0x14 load address 0x0800f534 0x20000000 __data_run_start__ = . 0x20000014 . = MAX ((__data_run_start__ + SIZEOF (.data)), .) *fill* 0x20000000 0x14 00 @@ -2104,94 +2517,166 @@ Linker script and memory map 0x00000001 . = ASSERT (((__data_run_end__ >= __RAM_segment_start__) && (__data_run_end__ <= __RAM_segment_end__)), error: .data_run is too large to fit in RAM memory segment) 0x20000014 __bss_load_start__ = ALIGN (__data_run_end__, 0x4) -.bss 0x20000014 0x5c +.bss 0x20000014 0x15a0 0x20000014 __bss_start__ = . *(.bss .bss.* .gnu.linkonce.b.*) - .bss.xcpCtoReqPacket.7036 - 0x20000014 0x44 THUMB Debug/../../obj/boot.o - .bss.xcpCtoRxLength.7037 - 0x20000058 0x1 THUMB Debug/../../obj/boot.o - .bss.xcpCtoRxInProgress.7038 - 0x20000059 0x1 THUMB Debug/../../obj/boot.o - *fill* 0x2000005a 0x2 00 - .bss.timer_counter_last.7017 - 0x2000005c 0x4 THUMB Debug/../../obj/led.o - .bss.led_toggle_state.7016 - 0x20000060 0x1 THUMB Debug/../../obj/led.o - *fill* 0x20000061 0x3 00 + *fill* 0x20000014 0x6c 00 + .bss.EnetDmaRx + 0x20000080 0x80 THUMB Debug/../../obj/netdev.o + 0x20000080 EnetDmaRx + .bss.RxBuff 0x20000100 0x640 THUMB Debug/../../obj/netdev.o + 0x20000100 RxBuff + *fill* 0x20000740 0x40 00 + .bss.EnetDmaTx + 0x20000780 0x80 THUMB Debug/../../obj/netdev.o + 0x20000780 EnetDmaTx + .bss.TxBuff 0x20000800 0x640 THUMB Debug/../../obj/netdev.o + 0x20000800 TxBuff + .bss.xcpCtoReqPacket.7047 + 0x20000e40 0x44 THUMB Debug/../../obj/boot.o + .bss.xcpCtoRxLength.7048 + 0x20000e84 0x1 THUMB Debug/../../obj/boot.o + .bss.xcpCtoRxInProgress.7049 + 0x20000e85 0x1 THUMB Debug/../../obj/boot.o + *fill* 0x20000e86 0x2 00 + .bss.timer_counter_last.7028 + 0x20000e88 0x4 THUMB Debug/../../obj/led.o + .bss.led_toggle_state.7027 + 0x20000e8c 0x1 THUMB Debug/../../obj/led.o + *fill* 0x20000e8d 0x3 00 .bss.millisecond_counter - 0x20000064 0x4 THUMB Debug/../../obj/timer.o + 0x20000e90 0x4 THUMB Debug/../../obj/timer.o + .bss.ARPTimerTimeOut + 0x20000e94 0x4 THUMB Debug/../../obj/net.o + .bss.periodicTimerTimeOut + 0x20000e98 0x4 THUMB Debug/../../obj/net.o + .bss.uip_conn 0x20000e9c 0x4 THUMB Debug/../../obj/uip.o + 0x20000e9c uip_conn + .bss.uip_conns + 0x20000ea0 0x20 THUMB Debug/../../obj/uip.o + 0x20000ea0 uip_conns + .bss.uip_netmask + 0x20000ec0 0x4 THUMB Debug/../../obj/uip.o + 0x20000ec0 uip_netmask + .bss.uip_len 0x20000ec4 0x2 THUMB Debug/../../obj/uip.o + 0x20000ec4 uip_len + .bss.ipid 0x20000ec6 0x2 THUMB Debug/../../obj/uip.o + .bss.uip_draddr + 0x20000ec8 0x4 THUMB Debug/../../obj/uip.o + 0x20000ec8 uip_draddr + .bss.uip_slen 0x20000ecc 0x2 THUMB Debug/../../obj/uip.o + 0x20000ecc uip_slen + *fill* 0x20000ece 0x2 00 + .bss.uip_buf 0x20000ed0 0x644 THUMB Debug/../../obj/uip.o + 0x20000ed0 uip_buf + .bss.uip_appdata + 0x20001514 0x4 THUMB Debug/../../obj/uip.o + 0x20001514 uip_appdata + .bss.iss 0x20001518 0x4 THUMB Debug/../../obj/uip.o + .bss.uip_hostaddr + 0x2000151c 0x4 THUMB Debug/../../obj/uip.o + 0x2000151c uip_hostaddr + .bss.uip_flags + 0x20001520 0x1 THUMB Debug/../../obj/uip.o + 0x20001520 uip_flags + *fill* 0x20001521 0x3 00 + .bss.uip_acc32 + 0x20001524 0x4 THUMB Debug/../../obj/uip.o + 0x20001524 uip_acc32 + .bss.lastport 0x20001528 0x2 THUMB Debug/../../obj/uip.o + .bss.tmp16 0x2000152a 0x2 THUMB Debug/../../obj/uip.o + .bss.uip_ethaddr + 0x2000152c 0x8 THUMB Debug/../../obj/uip.o + 0x2000152c uip_ethaddr + .bss.c 0x20001534 0x1 THUMB Debug/../../obj/uip.o + *fill* 0x20001535 0x3 00 + .bss.uip_listenports + 0x20001538 0x4 THUMB Debug/../../obj/uip.o + 0x20001538 uip_listenports + .bss.uip_sappdata + 0x2000153c 0x4 THUMB Debug/../../obj/uip.o + 0x2000153c uip_sappdata + .bss.opt 0x20001540 0x1 THUMB Debug/../../obj/uip.o + .bss.i 0x20001541 0x1 THUMB Debug/../../obj/uip_arp.o + .bss.tmpage 0x20001542 0x1 THUMB Debug/../../obj/uip_arp.o + *fill* 0x20001543 0x1 00 + .bss.arp_table + 0x20001544 0x60 THUMB Debug/../../obj/uip_arp.o + .bss.c 0x200015a4 0x1 THUMB Debug/../../obj/uip_arp.o + .bss.arptime 0x200015a5 0x1 THUMB Debug/../../obj/uip_arp.o + *fill* 0x200015a6 0x2 00 + .bss.ipaddr 0x200015a8 0x4 THUMB Debug/../../obj/uip_arp.o .bss.libdebugio.dbgCommWord - 0x20000068 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - 0x20000068 dbgCommWord + 0x200015ac 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + 0x200015ac dbgCommWord .bss.libdebugio.dbgCntrlWord_mempoll - 0x2000006c 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - 0x2000006c dbgCntrlWord_mempoll + 0x200015b0 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + 0x200015b0 dbgCntrlWord_mempoll *(COMMON) - 0x20000070 __bss_end__ = (__bss_start__ + SIZEOF (.bss)) - 0x20000070 __bss_load_end__ = __bss_end__ + 0x200015b4 __bss_end__ = (__bss_start__ + SIZEOF (.bss)) + 0x200015b4 __bss_load_end__ = __bss_end__ 0x00000001 . = ASSERT (((__bss_end__ >= __RAM_segment_start__) && (__bss_end__ <= __RAM_segment_end__)), error: .bss is too large to fit in RAM memory segment) - 0x20000070 __non_init_load_start__ = ALIGN (__bss_end__, 0x4) + 0x200015b4 __non_init_load_start__ = ALIGN (__bss_end__, 0x4) -.non_init 0x20000070 0x0 - 0x20000070 __non_init_start__ = . +.non_init 0x200015b4 0x0 + 0x200015b4 __non_init_start__ = . *(.non_init .non_init.*) - 0x20000070 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init)) - 0x20000070 __non_init_load_end__ = __non_init_end__ + 0x200015b4 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init)) + 0x200015b4 __non_init_load_end__ = __non_init_end__ 0x00000001 . = ASSERT (((__non_init_end__ >= __RAM_segment_start__) && (__non_init_end__ <= __RAM_segment_end__)), error: .non_init is too large to fit in RAM memory segment) - 0x20000070 __heap_load_start__ = ALIGN (__non_init_end__, 0x4) + 0x200015b4 __heap_load_start__ = ALIGN (__non_init_end__, 0x4) -.heap 0x20000070 0x800 - 0x20000070 __heap_start__ = . +.heap 0x200015b4 0x800 + 0x200015b4 __heap_start__ = . *(.heap .heap.*) - 0x20000870 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4) - *fill* 0x20000070 0x800 00 - 0x20000870 __heap_end__ = (__heap_start__ + SIZEOF (.heap)) - 0x20000870 __heap_load_end__ = __heap_end__ + 0x20001db4 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4) + *fill* 0x200015b4 0x800 00 + 0x20001db4 __heap_end__ = (__heap_start__ + SIZEOF (.heap)) + 0x20001db4 __heap_load_end__ = __heap_end__ 0x00000001 . = ASSERT (((__heap_end__ >= __RAM_segment_start__) && (__heap_end__ <= __RAM_segment_end__)), error: .heap is too large to fit in RAM memory segment) - 0x20000870 __stack_load_start__ = ALIGN (__heap_end__, 0x4) + 0x20001db4 __stack_load_start__ = ALIGN (__heap_end__, 0x4) -.stack 0x20000870 0x800 - 0x20000870 __stack_start__ = . +.stack 0x20001db4 0x800 + 0x20001db4 __stack_start__ = . *(.stack .stack.*) - 0x20001070 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4) - *fill* 0x20000870 0x800 00 - 0x20001070 __stack_end__ = (__stack_start__ + SIZEOF (.stack)) - 0x20001070 __stack_load_end__ = __stack_end__ + 0x200025b4 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4) + *fill* 0x20001db4 0x800 00 + 0x200025b4 __stack_end__ = (__stack_start__ + SIZEOF (.stack)) + 0x200025b4 __stack_load_end__ = __stack_end__ 0x00000001 . = ASSERT (((__stack_end__ >= __RAM_segment_start__) && (__stack_end__ <= __RAM_segment_end__)), error: .stack is too large to fit in RAM memory segment) - 0x20001070 __stack_process_load_start__ = ALIGN (__stack_end__, 0x4) + 0x200025b4 __stack_process_load_start__ = ALIGN (__stack_end__, 0x4) -.stack_process 0x20001070 0x0 - 0x20001070 __stack_process_start__ = . +.stack_process 0x200025b4 0x0 + 0x200025b4 __stack_process_start__ = . *(.stack_process .stack_process.*) - 0x20001070 . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4) - 0x20001070 __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process)) - 0x20001070 __stack_process_load_end__ = __stack_process_end__ + 0x200025b4 . = ALIGN (MAX ((__stack_process_start__ + __STACKSIZE_PROCESS__), .), 0x4) + 0x200025b4 __stack_process_end__ = (__stack_process_start__ + SIZEOF (.stack_process)) + 0x200025b4 __stack_process_load_end__ = __stack_process_end__ 0x00000001 . = ASSERT (((__stack_process_end__ >= __RAM_segment_start__) && (__stack_process_end__ <= __RAM_segment_end__)), error: .stack_process is too large to fit in RAM memory segment) - 0x20001070 __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4) + 0x200025b4 __tbss_load_start__ = ALIGN (__stack_process_end__, 0x4) -.tbss 0x20001070 0x0 - 0x20001070 __tbss_start__ = . +.tbss 0x200025b4 0x0 + 0x200025b4 __tbss_start__ = . *(.tbss .tbss.*) - 0x20001070 __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss)) - 0x20001070 __tbss_load_end__ = __tbss_end__ + 0x200025b4 __tbss_end__ = (__tbss_start__ + SIZEOF (.tbss)) + 0x200025b4 __tbss_load_end__ = __tbss_end__ 0x00000001 . = ASSERT (((__tbss_end__ >= __RAM_segment_start__) && (__tbss_end__ <= __RAM_segment_end__)), error: .tbss is too large to fit in RAM memory segment) - 0x08009120 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + 0x0800f548 __tdata_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) -.tdata 0x20001070 0x0 load address 0x08009120 - 0x20001070 __tdata_start__ = . +.tdata 0x200025b4 0x0 load address 0x0800f548 + 0x200025b4 __tdata_start__ = . *(.tdata .tdata.*) - 0x20001070 __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata)) - 0x08009120 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata)) - 0x08009120 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata)) + 0x200025b4 __tdata_end__ = (__tdata_start__ + SIZEOF (.tdata)) + 0x0800f548 __tdata_load_end__ = (__tdata_load_start__ + SIZEOF (.tdata)) + 0x0800f548 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.tdata)) 0x00000001 . = ASSERT (((__tdata_load_end__ >= __FLASH_segment_start__) && (__tdata_load_end__ <= __FLASH_segment_end__)), error: .tdata is too large to fit in FLASH memory segment) -.tdata_run 0x20001070 0x0 - 0x20001070 __tdata_run_start__ = . - 0x20001070 . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .) - 0x20001070 __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run)) - 0x20001070 __tdata_run_load_end__ = __tdata_run_end__ - 0x20001070 __RAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run)) +.tdata_run 0x200025b4 0x0 + 0x200025b4 __tdata_run_start__ = . + 0x200025b4 . = MAX ((__tdata_run_start__ + SIZEOF (.tdata)), .) + 0x200025b4 __tdata_run_end__ = (__tdata_run_start__ + SIZEOF (.tdata_run)) + 0x200025b4 __tdata_run_load_end__ = __tdata_run_end__ + 0x200025b4 __RAM_segment_used_end__ = (ALIGN (__tbss_end__, 0x4) + SIZEOF (.tdata_run)) 0x00000001 . = ASSERT (((__tdata_run_end__ >= __RAM_segment_start__) && (__tdata_run_end__ <= __RAM_segment_end__)), error: .tdata_run is too large to fit in RAM memory segment) START GROUP LOAD THUMB Debug/../../obj/system_stm32f4xx.o @@ -2226,6 +2711,9 @@ LOAD THUMB Debug/../../obj/stm32f4xx_syscfg.o LOAD THUMB Debug/../../obj/stm32f4xx_tim.o LOAD THUMB Debug/../../obj/stm32f4xx_usart.o LOAD THUMB Debug/../../obj/stm32f4xx_wwdg.o +LOAD THUMB Debug/../../obj/stm32_eth.o +LOAD THUMB Debug/../../obj/clock-arch.o +LOAD THUMB Debug/../../obj/netdev.o LOAD THUMB Debug/../../obj/boot.o LOAD THUMB Debug/../../obj/cstart.o LOAD THUMB Debug/../../obj/irq.o @@ -2233,6 +2721,12 @@ LOAD THUMB Debug/../../obj/led.o LOAD THUMB Debug/../../obj/main.o LOAD THUMB Debug/../../obj/timer.o LOAD THUMB Debug/../../obj/vectors.o +LOAD THUMB Debug/../../obj/net.o +LOAD THUMB Debug/../../obj/uip.o +LOAD THUMB Debug/../../obj/uip_arp.o +LOAD THUMB Debug/../../obj/uip_timer.o +LOAD THUMB Debug/../../obj/uip-fw.o +LOAD THUMB Debug/../../obj/uiplib.o LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libcm_v7em_t_le_eabi.a LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libm_v7em_t_le_eabi.a LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a @@ -2243,66 +2737,91 @@ LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib END GROUP OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/ide/../bin/demoprog_olimex_stm32e407.elf elf32-littlearm) -.debug_frame 0x00000000 0x1274 +.debug_frame 0x00000000 0x1eec .debug_frame 0x00000000 0x38 THUMB Debug/../../obj/system_stm32f4xx.o .debug_frame 0x00000038 0x1e4 THUMB Debug/../../obj/stm32f4xx_can.o .debug_frame 0x0000021c 0x124 THUMB Debug/../../obj/stm32f4xx_gpio.o .debug_frame 0x00000340 0x30c THUMB Debug/../../obj/stm32f4xx_rcc.o - .debug_frame 0x0000064c 0x224 THUMB Debug/../../obj/stm32f4xx_usart.o - .debug_frame 0x00000870 0x8c THUMB Debug/../../obj/boot.o - .debug_frame 0x000008fc 0x40 THUMB Debug/../../obj/irq.o - .debug_frame 0x0000093c 0x50 THUMB Debug/../../obj/led.o - .debug_frame 0x0000098c 0x2c THUMB Debug/../../obj/main.o - .debug_frame 0x000009b8 0x6c THUMB Debug/../../obj/timer.o - .debug_frame 0x00000a24 0x20 THUMB Debug/../../obj/vectors.o - .debug_frame 0x00000a44 0x790 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - .debug_frame 0x000011d4 0xa0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + .debug_frame 0x0000064c 0x88 THUMB Debug/../../obj/stm32f4xx_syscfg.o + .debug_frame 0x000006d4 0x224 THUMB Debug/../../obj/stm32f4xx_usart.o + .debug_frame 0x000008f8 0x76c THUMB Debug/../../obj/stm32_eth.o + .debug_frame 0x00001064 0x94 THUMB Debug/../../obj/netdev.o + .debug_frame 0x000010f8 0x8c THUMB Debug/../../obj/boot.o + .debug_frame 0x00001184 0x40 THUMB Debug/../../obj/irq.o + .debug_frame 0x000011c4 0x50 THUMB Debug/../../obj/led.o + .debug_frame 0x00001214 0x2c THUMB Debug/../../obj/main.o + .debug_frame 0x00001240 0x6c THUMB Debug/../../obj/timer.o + .debug_frame 0x000012ac 0x20 THUMB Debug/../../obj/vectors.o + .debug_frame 0x000012cc 0x64 THUMB Debug/../../obj/net.o + .debug_frame 0x00001330 0x1b0 THUMB Debug/../../obj/uip.o + .debug_frame 0x000014e0 0xbc THUMB Debug/../../obj/uip_arp.o + .debug_frame 0x0000159c 0x120 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .debug_frame 0x000016bc 0x790 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_frame 0x00001e4c 0xa0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) -.debug_info 0x00000000 0x5ba0 +.debug_info 0x00000000 0xac5a .debug_info 0x00000000 0x473 THUMB Debug/../../obj/system_stm32f4xx.o .debug_info 0x00000473 0xdf4 THUMB Debug/../../obj/stm32f4xx_can.o .debug_info 0x00001267 0x809 THUMB Debug/../../obj/stm32f4xx_gpio.o .debug_info 0x00001a70 0xda0 THUMB Debug/../../obj/stm32f4xx_rcc.o - .debug_info 0x00002810 0xc4b THUMB Debug/../../obj/stm32f4xx_usart.o - .debug_info 0x0000345b 0x1160 THUMB Debug/../../obj/boot.o - .debug_info 0x000045bb 0xe2 THUMB Debug/../../obj/cstart.o - .debug_info 0x0000469d 0x127 THUMB Debug/../../obj/irq.o - .debug_info 0x000047c4 0x3ec THUMB Debug/../../obj/led.o - .debug_info 0x00004bb0 0x144 THUMB Debug/../../obj/main.o - .debug_info 0x00004cf4 0x775 THUMB Debug/../../obj/timer.o - .debug_info 0x00005469 0x102 THUMB Debug/../../obj/vectors.o - .debug_info 0x0000556b 0x55f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - .debug_info 0x00005aca 0xd6 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + .debug_info 0x00002810 0x2b7 THUMB Debug/../../obj/stm32f4xx_syscfg.o + .debug_info 0x00002ac7 0xc4b THUMB Debug/../../obj/stm32f4xx_usart.o + .debug_info 0x00003712 0x1ffe THUMB Debug/../../obj/stm32_eth.o + .debug_info 0x00005710 0x1550 THUMB Debug/../../obj/netdev.o + .debug_info 0x00006c60 0x1161 THUMB Debug/../../obj/boot.o + .debug_info 0x00007dc1 0xe2 THUMB Debug/../../obj/cstart.o + .debug_info 0x00007ea3 0x127 THUMB Debug/../../obj/irq.o + .debug_info 0x00007fca 0x3ec THUMB Debug/../../obj/led.o + .debug_info 0x000083b6 0x16a THUMB Debug/../../obj/main.o + .debug_info 0x00008520 0x775 THUMB Debug/../../obj/timer.o + .debug_info 0x00008c95 0x102 THUMB Debug/../../obj/vectors.o + .debug_info 0x00008d97 0x551 THUMB Debug/../../obj/net.o + .debug_info 0x000092e8 0xca9 THUMB Debug/../../obj/uip.o + .debug_info 0x00009f91 0x694 THUMB Debug/../../obj/uip_arp.o + .debug_info 0x0000a625 0x55f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_info 0x0000ab84 0xd6 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) -.debug_abbrev 0x00000000 0x126c +.debug_abbrev 0x00000000 0x1f76 .debug_abbrev 0x00000000 0x158 THUMB Debug/../../obj/system_stm32f4xx.o .debug_abbrev 0x00000158 0x23e THUMB Debug/../../obj/stm32f4xx_can.o .debug_abbrev 0x00000396 0x210 THUMB Debug/../../obj/stm32f4xx_gpio.o .debug_abbrev 0x000005a6 0x229 THUMB Debug/../../obj/stm32f4xx_rcc.o - .debug_abbrev 0x000007cf 0x1fc THUMB Debug/../../obj/stm32f4xx_usart.o - .debug_abbrev 0x000009cb 0x2d6 THUMB Debug/../../obj/boot.o - .debug_abbrev 0x00000ca1 0x14 THUMB Debug/../../obj/cstart.o - .debug_abbrev 0x00000cb5 0x8d THUMB Debug/../../obj/irq.o - .debug_abbrev 0x00000d42 0x17d THUMB Debug/../../obj/led.o - .debug_abbrev 0x00000ebf 0x9c THUMB Debug/../../obj/main.o - .debug_abbrev 0x00000f5b 0x1db THUMB Debug/../../obj/timer.o - .debug_abbrev 0x00001136 0xd0 THUMB Debug/../../obj/vectors.o - .debug_abbrev 0x00001206 0x3e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - .debug_abbrev 0x00001244 0x28 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + .debug_abbrev 0x000007cf 0x177 THUMB Debug/../../obj/stm32f4xx_syscfg.o + .debug_abbrev 0x00000946 0x1fc THUMB Debug/../../obj/stm32f4xx_usart.o + .debug_abbrev 0x00000b42 0x28e THUMB Debug/../../obj/stm32_eth.o + .debug_abbrev 0x00000dd0 0x32a THUMB Debug/../../obj/netdev.o + .debug_abbrev 0x000010fa 0x2d8 THUMB Debug/../../obj/boot.o + .debug_abbrev 0x000013d2 0x14 THUMB Debug/../../obj/cstart.o + .debug_abbrev 0x000013e6 0x8d THUMB Debug/../../obj/irq.o + .debug_abbrev 0x00001473 0x17d THUMB Debug/../../obj/led.o + .debug_abbrev 0x000015f0 0x9c THUMB Debug/../../obj/main.o + .debug_abbrev 0x0000168c 0x1db THUMB Debug/../../obj/timer.o + .debug_abbrev 0x00001867 0xd0 THUMB Debug/../../obj/vectors.o + .debug_abbrev 0x00001937 0x17a THUMB Debug/../../obj/net.o + .debug_abbrev 0x00001ab1 0x293 THUMB Debug/../../obj/uip.o + .debug_abbrev 0x00001d44 0x1cc THUMB Debug/../../obj/uip_arp.o + .debug_abbrev 0x00001f10 0x3e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_abbrev 0x00001f4e 0x28 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) -.debug_loc 0x00000000 0x3734 +.debug_loc 0x00000000 0x607f .debug_loc 0x00000000 0x1a7 THUMB Debug/../../obj/system_stm32f4xx.o .debug_loc 0x000001a7 0xf06 THUMB Debug/../../obj/stm32f4xx_can.o .debug_loc 0x000010ad 0x445 THUMB Debug/../../obj/stm32f4xx_gpio.o .debug_loc 0x000014f2 0xdb0 THUMB Debug/../../obj/stm32f4xx_rcc.o - .debug_loc 0x000022a2 0xaeb THUMB Debug/../../obj/stm32f4xx_usart.o - .debug_loc 0x00002d8d 0x109 THUMB Debug/../../obj/boot.o - .debug_loc 0x00002e96 0x6a THUMB Debug/../../obj/led.o - .debug_loc 0x00002f00 0x20 THUMB Debug/../../obj/main.o - .debug_loc 0x00002f20 0x20 THUMB Debug/../../obj/timer.o - .debug_loc 0x00002f40 0x7f4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_loc 0x000022a2 0xe6 THUMB Debug/../../obj/stm32f4xx_syscfg.o + .debug_loc 0x00002388 0xaeb THUMB Debug/../../obj/stm32f4xx_usart.o + .debug_loc 0x00002e73 0x1bd0 THUMB Debug/../../obj/stm32_eth.o + .debug_loc 0x00004a43 0xaa THUMB Debug/../../obj/netdev.o + .debug_loc 0x00004aed 0x109 THUMB Debug/../../obj/boot.o + .debug_loc 0x00004bf6 0x6a THUMB Debug/../../obj/led.o + .debug_loc 0x00004c60 0x20 THUMB Debug/../../obj/main.o + .debug_loc 0x00004c80 0x20 THUMB Debug/../../obj/timer.o + .debug_loc 0x00004ca0 0xd9 THUMB Debug/../../obj/net.o + .debug_loc 0x00004d79 0x64e THUMB Debug/../../obj/uip.o + .debug_loc 0x000053c7 0x4c4 THUMB Debug/../../obj/uip_arp.o + .debug_loc 0x0000588b 0x7f4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) -.debug_aranges 0x00000000 0x7b8 +.debug_aranges 0x00000000 0xc70 .debug_aranges 0x00000000 0x28 THUMB Debug/../../obj/system_stm32f4xx.o .debug_aranges @@ -2312,83 +2831,119 @@ OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossw .debug_aranges 0x00000190 0x180 THUMB Debug/../../obj/stm32f4xx_rcc.o .debug_aranges - 0x00000310 0x100 THUMB Debug/../../obj/stm32f4xx_usart.o + 0x00000310 0x48 THUMB Debug/../../obj/stm32f4xx_syscfg.o .debug_aranges - 0x00000410 0x38 THUMB Debug/../../obj/boot.o + 0x00000358 0x100 THUMB Debug/../../obj/stm32f4xx_usart.o .debug_aranges - 0x00000448 0x20 THUMB Debug/../../obj/cstart.o + 0x00000458 0x330 THUMB Debug/../../obj/stm32_eth.o .debug_aranges - 0x00000468 0x30 THUMB Debug/../../obj/irq.o + 0x00000788 0x38 THUMB Debug/../../obj/netdev.o .debug_aranges - 0x00000498 0x28 THUMB Debug/../../obj/led.o + 0x000007c0 0x38 THUMB Debug/../../obj/boot.o .debug_aranges - 0x000004c0 0x20 THUMB Debug/../../obj/main.o + 0x000007f8 0x20 THUMB Debug/../../obj/cstart.o .debug_aranges - 0x000004e0 0x40 THUMB Debug/../../obj/timer.o + 0x00000818 0x30 THUMB Debug/../../obj/irq.o .debug_aranges - 0x00000520 0x20 THUMB Debug/../../obj/vectors.o + 0x00000848 0x28 THUMB Debug/../../obj/led.o .debug_aranges - 0x00000540 0x218 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + 0x00000870 0x20 THUMB Debug/../../obj/main.o .debug_aranges - 0x00000758 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + 0x00000890 0x40 THUMB Debug/../../obj/timer.o + .debug_aranges + 0x000008d0 0x20 THUMB Debug/../../obj/vectors.o + .debug_aranges + 0x000008f0 0x30 THUMB Debug/../../obj/net.o + .debug_aranges + 0x00000920 0x98 THUMB Debug/../../obj/uip.o + .debug_aranges + 0x000009b8 0x40 THUMB Debug/../../obj/uip_arp.o + .debug_aranges + 0x000009f8 0x218 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_aranges + 0x00000c10 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) -.debug_ranges 0x00000000 0x728 +.debug_ranges 0x00000000 0xb80 .debug_ranges 0x00000000 0x18 THUMB Debug/../../obj/system_stm32f4xx.o .debug_ranges 0x00000018 0xd0 THUMB Debug/../../obj/stm32f4xx_can.o .debug_ranges 0x000000e8 0x78 THUMB Debug/../../obj/stm32f4xx_gpio.o .debug_ranges 0x00000160 0x170 THUMB Debug/../../obj/stm32f4xx_rcc.o - .debug_ranges 0x000002d0 0xf0 THUMB Debug/../../obj/stm32f4xx_usart.o - .debug_ranges 0x000003c0 0x88 THUMB Debug/../../obj/boot.o - .debug_ranges 0x00000448 0x20 THUMB Debug/../../obj/irq.o - .debug_ranges 0x00000468 0x18 THUMB Debug/../../obj/led.o - .debug_ranges 0x00000480 0x10 THUMB Debug/../../obj/main.o - .debug_ranges 0x00000490 0x30 THUMB Debug/../../obj/timer.o - .debug_ranges 0x000004c0 0x10 THUMB Debug/../../obj/vectors.o - .debug_ranges 0x000004d0 0x208 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - .debug_ranges 0x000006d8 0x50 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + .debug_ranges 0x000002d0 0x38 THUMB Debug/../../obj/stm32f4xx_syscfg.o + .debug_ranges 0x00000308 0xf0 THUMB Debug/../../obj/stm32f4xx_usart.o + .debug_ranges 0x000003f8 0x320 THUMB Debug/../../obj/stm32_eth.o + .debug_ranges 0x00000718 0x28 THUMB Debug/../../obj/netdev.o + .debug_ranges 0x00000740 0x88 THUMB Debug/../../obj/boot.o + .debug_ranges 0x000007c8 0x20 THUMB Debug/../../obj/irq.o + .debug_ranges 0x000007e8 0x18 THUMB Debug/../../obj/led.o + .debug_ranges 0x00000800 0x10 THUMB Debug/../../obj/main.o + .debug_ranges 0x00000810 0x30 THUMB Debug/../../obj/timer.o + .debug_ranges 0x00000840 0x10 THUMB Debug/../../obj/vectors.o + .debug_ranges 0x00000850 0x20 THUMB Debug/../../obj/net.o + .debug_ranges 0x00000870 0x88 THUMB Debug/../../obj/uip.o + .debug_ranges 0x000008f8 0x30 THUMB Debug/../../obj/uip_arp.o + .debug_ranges 0x00000928 0x208 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_ranges 0x00000b30 0x50 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) -.debug_line 0x00000000 0x27c9 +.debug_line 0x00000000 0x445e .debug_line 0x00000000 0x21b THUMB Debug/../../obj/system_stm32f4xx.o .debug_line 0x0000021b 0x55e THUMB Debug/../../obj/stm32f4xx_can.o .debug_line 0x00000779 0x3ae THUMB Debug/../../obj/stm32f4xx_gpio.o .debug_line 0x00000b27 0x590 THUMB Debug/../../obj/stm32f4xx_rcc.o - .debug_line 0x000010b7 0x4a2 THUMB Debug/../../obj/stm32f4xx_usart.o - .debug_line 0x00001559 0x2f7 THUMB Debug/../../obj/boot.o - .debug_line 0x00001850 0x127 THUMB Debug/../../obj/cstart.o - .debug_line 0x00001977 0x169 THUMB Debug/../../obj/irq.o - .debug_line 0x00001ae0 0x220 THUMB Debug/../../obj/led.o - .debug_line 0x00001d00 0x1da THUMB Debug/../../obj/main.o - .debug_line 0x00001eda 0x20a THUMB Debug/../../obj/timer.o - .debug_line 0x000020e4 0x121 THUMB Debug/../../obj/vectors.o - .debug_line 0x00002205 0x550 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) - .debug_line 0x00002755 0x74 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + .debug_line 0x000010b7 0x27d THUMB Debug/../../obj/stm32f4xx_syscfg.o + .debug_line 0x00001334 0x4a2 THUMB Debug/../../obj/stm32f4xx_usart.o + .debug_line 0x000017d6 0xcd9 THUMB Debug/../../obj/stm32_eth.o + .debug_line 0x000024af 0x35a THUMB Debug/../../obj/netdev.o + .debug_line 0x00002809 0x2f7 THUMB Debug/../../obj/boot.o + .debug_line 0x00002b00 0x127 THUMB Debug/../../obj/cstart.o + .debug_line 0x00002c27 0x169 THUMB Debug/../../obj/irq.o + .debug_line 0x00002d90 0x220 THUMB Debug/../../obj/led.o + .debug_line 0x00002fb0 0x1e9 THUMB Debug/../../obj/main.o + .debug_line 0x00003199 0x20a THUMB Debug/../../obj/timer.o + .debug_line 0x000033a3 0x121 THUMB Debug/../../obj/vectors.o + .debug_line 0x000034c4 0x1ef THUMB Debug/../../obj/net.o + .debug_line 0x000036b3 0x541 THUMB Debug/../../obj/uip.o + .debug_line 0x00003bf4 0x2a6 THUMB Debug/../../obj/uip_arp.o + .debug_line 0x00003e9a 0x550 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_line 0x000043ea 0x74 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) -.debug_str 0x00000000 0x2653 +.debug_str 0x00000000 0x42fd .debug_str 0x00000000 0x356 THUMB Debug/../../obj/system_stm32f4xx.o 0x3a3 (size before relaxing) .debug_str 0x00000356 0x5b4 THUMB Debug/../../obj/stm32f4xx_can.o 0x793 (size before relaxing) - .debug_str 0x0000090a 0x390 THUMB Debug/../../obj/stm32f4xx_gpio.o + .debug_str 0x0000090a 0x38a THUMB Debug/../../obj/stm32f4xx_gpio.o 0x508 (size before relaxing) - .debug_str 0x00000c9a 0x5bc THUMB Debug/../../obj/stm32f4xx_rcc.o + .debug_str 0x00000c94 0x5bc THUMB Debug/../../obj/stm32f4xx_rcc.o 0x8b7 (size before relaxing) - .debug_str 0x00001256 0x488 THUMB Debug/../../obj/stm32f4xx_usart.o + .debug_str 0x00001250 0x1b4 THUMB Debug/../../obj/stm32f4xx_syscfg.o + 0x354 (size before relaxing) + .debug_str 0x00001404 0x488 THUMB Debug/../../obj/stm32f4xx_usart.o 0x70d (size before relaxing) - .debug_str 0x000016de 0x253 THUMB Debug/../../obj/boot.o + .debug_str 0x0000188c 0x12bb THUMB Debug/../../obj/stm32_eth.o + 0x1565 (size before relaxing) + .debug_str 0x00002b47 0x226 THUMB Debug/../../obj/netdev.o + 0xc8f (size before relaxing) + .debug_str 0x00002d6d 0x23b THUMB Debug/../../obj/boot.o 0x920 (size before relaxing) - .debug_str 0x00001931 0xc7 THUMB Debug/../../obj/irq.o + .debug_str 0x00002fa8 0xc7 THUMB Debug/../../obj/irq.o 0x1fc (size before relaxing) - .debug_str 0x000019f8 0xb1 THUMB Debug/../../obj/led.o + .debug_str 0x0000306f 0xb1 THUMB Debug/../../obj/led.o 0x3ec (size before relaxing) - .debug_str 0x00001aa9 0x70 THUMB Debug/../../obj/main.o - 0x204 (size before relaxing) - .debug_str 0x00001b19 0x622 THUMB Debug/../../obj/timer.o + .debug_str 0x00003120 0x80 THUMB Debug/../../obj/main.o + 0x214 (size before relaxing) + .debug_str 0x000031a0 0x622 THUMB Debug/../../obj/timer.o 0x823 (size before relaxing) - .debug_str 0x0000213b 0x93 THUMB Debug/../../obj/vectors.o + .debug_str 0x000037c2 0x93 THUMB Debug/../../obj/vectors.o 0x1c8 (size before relaxing) - .debug_str 0x000021ce 0x3b3 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .debug_str 0x00003855 0x1d4 THUMB Debug/../../obj/net.o + 0x3bd (size before relaxing) + .debug_str 0x00003a29 0x2f8 THUMB Debug/../../obj/uip.o + 0x56a (size before relaxing) + .debug_str 0x00003d21 0x157 THUMB Debug/../../obj/uip_arp.o + 0x344 (size before relaxing) + .debug_str 0x00003e78 0x3b3 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) 0x3fc (size before relaxing) - .debug_str 0x00002581 0xd2 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + .debug_str 0x0000422b 0xd2 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) 0x11b (size before relaxing) .comment 0x00000000 0x4e @@ -2397,13 +2952,19 @@ OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossw .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_can.o .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_gpio.o .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_rcc.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_syscfg.o .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32f4xx_usart.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/stm32_eth.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/netdev.o .comment 0x00000000 0x4f THUMB Debug/../../obj/boot.o .comment 0x00000000 0x4f THUMB Debug/../../obj/irq.o .comment 0x00000000 0x4f THUMB Debug/../../obj/led.o .comment 0x00000000 0x4f THUMB Debug/../../obj/main.o .comment 0x00000000 0x4f THUMB Debug/../../obj/timer.o .comment 0x00000000 0x4f THUMB Debug/../../obj/vectors.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/net.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/uip.o + .comment 0x00000000 0x4f THUMB Debug/../../obj/uip_arp.o .comment 0x00000000 0x4f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) .comment 0x00000000 0x4f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) @@ -2418,22 +2979,36 @@ OUTPUT(C:/Work/software/OpenBLT/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossw .ARM.attributes 0x00000099 0x33 THUMB Debug/../../obj/stm32f4xx_rcc.o .ARM.attributes - 0x000000cc 0x33 THUMB Debug/../../obj/stm32f4xx_usart.o + 0x000000cc 0x33 THUMB Debug/../../obj/stm32f4xx_syscfg.o .ARM.attributes - 0x000000ff 0x33 THUMB Debug/../../obj/boot.o + 0x000000ff 0x33 THUMB Debug/../../obj/stm32f4xx_usart.o .ARM.attributes - 0x00000132 0x27 THUMB Debug/../../obj/cstart.o + 0x00000132 0x33 THUMB Debug/../../obj/stm32_eth.o .ARM.attributes - 0x00000159 0x33 THUMB Debug/../../obj/irq.o + 0x00000165 0x33 THUMB Debug/../../obj/netdev.o .ARM.attributes - 0x0000018c 0x33 THUMB Debug/../../obj/led.o + 0x00000198 0x33 THUMB Debug/../../obj/boot.o .ARM.attributes - 0x000001bf 0x33 THUMB Debug/../../obj/main.o + 0x000001cb 0x27 THUMB Debug/../../obj/cstart.o .ARM.attributes - 0x000001f2 0x33 THUMB Debug/../../obj/timer.o + 0x000001f2 0x33 THUMB Debug/../../obj/irq.o .ARM.attributes - 0x00000225 0x33 THUMB Debug/../../obj/vectors.o + 0x00000225 0x33 THUMB Debug/../../obj/led.o .ARM.attributes - 0x00000258 0x2e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + 0x00000258 0x33 THUMB Debug/../../obj/main.o .ARM.attributes - 0x00000286 0x2e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) + 0x0000028b 0x33 THUMB Debug/../../obj/timer.o + .ARM.attributes + 0x000002be 0x33 THUMB Debug/../../obj/vectors.o + .ARM.attributes + 0x000002f1 0x33 THUMB Debug/../../obj/net.o + .ARM.attributes + 0x00000324 0x33 THUMB Debug/../../obj/uip.o + .ARM.attributes + 0x00000357 0x33 THUMB Debug/../../obj/uip_arp.o + .ARM.attributes + 0x0000038a 0x1e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_v7em_t_le_eabi.a(libc2_asm.o) + .ARM.attributes + 0x000003a8 0x2e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libdebugio_v7em_t_le_eabi.a(libdebugio.o) + .ARM.attributes + 0x000003d6 0x2e C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.3/lib/libc_user_libc_v7em_t_le_eabi.a(user_libc.o) diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/bin/demoprog_olimex_stm32e407.srec b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/bin/demoprog_olimex_stm32e407.srec index 9dda9a51..3d710917 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/bin/demoprog_olimex_stm32e407.srec +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/bin/demoprog_olimex_stm32e407.srec @@ -1,279 +1,857 @@ S02B0000433A2F576F726B2F736F6674776172652F4F70656E424C542F5461726765742F44656D6F2F41524DEF -S315080080007010002033820008A1900008A190000893 -S31508008010A1900008A1900008A1900008A19000086E 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+S3150800F5180B040C040C050D050E050F050F06100641 +S3110800F52810071008FFFFFFFFFFFF0000A0 +S3150800F534007A030A0000000001020304010203041E +S3090800F5440607080997 +S7050800C233FD diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/boot.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/boot.c index c05d146b..8c3d10af 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/boot.c +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/boot.c @@ -87,7 +87,7 @@ void BootComCheckActivationRequest(void) ** \return none. ** ****************************************************************************************/ -static void BootActivate(void) +void BootActivate(void) { /* perform software reset to activate the bootoader again */ NVIC_SystemReset(); diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/boot.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/boot.h index b3e3f8c1..26623a6f 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/boot.h +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/boot.h @@ -38,6 +38,7 @@ ****************************************************************************************/ void BootComInit(void); void BootComCheckActivationRequest(void); +void BootActivate(void); #endif /* BOOT_H */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/header.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/header.h index 5eb9a804..9c2a298f 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/header.h +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/header.h @@ -43,6 +43,7 @@ #include "irq.h" /* IRQ driver */ #include "led.h" /* LED driver */ #include "timer.h" /* Timer driver */ +#include "net.h" /* TCP/IP server application */ #endif /* HEADER_H */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/ide/stm32f407_crossworks.hzp b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/ide/stm32f407_crossworks.hzp index 0c3a3192..79a4421f 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/ide/stm32f407_crossworks.hzp +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/ide/stm32f407_crossworks.hzp @@ -1,7 +1,7 @@ - + @@ -75,6 +75,17 @@ + + + + + + + + + + + @@ -88,6 +99,31 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/ide/stm32f407_crossworks.hzs b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/ide/stm32f407_crossworks.hzs index 324f7084..be6b5f0e 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/ide/stm32f407_crossworks.hzs +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/ide/stm32f407_crossworks.hzs @@ -66,7 +66,7 @@ - + - + diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/ethernetlib/inc/stm32_eth.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/ethernetlib/inc/stm32_eth.h new file mode 100644 index 00000000..578d8baa --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/ethernetlib/inc/stm32_eth.h @@ -0,0 +1,1610 @@ +/** + ****************************************************************************** + * @file stm32_eth.h + * @author MCD Application Team + * @version V1.0.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the Ethernet + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ETH_H +#define __STM32_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" /* STM32 registers */ + +/** @addtogroup STM32_ETH_Driver + * @{ + */ + +/** @defgroup ETH_Exported_Types + * @{ + */ + +/** + * @brief ETH MAC Init structure definition + */ +typedef struct { +/** + * @brief / * MAC + */ + uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation with the external PHY */ + uint32_t ETH_Watchdog; /*!< Enable/disable Watchdog timer */ + uint32_t ETH_Jabber; /*!< Enable/disable Jabber timer */ + uint32_t ETH_InterFrameGap; /*!< Selects minimum IFG between frames during transmission */ + uint32_t ETH_CarrierSense; /*!< Enable/disable Carrier Sense */ + uint32_t ETH_Speed; /*!< Indicates the Ethernet speed: 10/100 Mbps */ + uint32_t ETH_ReceiveOwn; /*!< Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */ + uint32_t ETH_LoopbackMode; /*!< Enable/disable internal MAC MII Loopback mode */ + uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */ + uint32_t ETH_ChecksumOffload; /*!< Enable/disable the calculation of complement sum of all received Ethernet frame payloads */ + uint32_t ETH_RetryTransmission; /*!< Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */ + uint32_t ETH_AutomaticPadCRCStrip; /*!< Enable/disable Automatic MAC Pad/CRC Stripping */ + uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value */ + uint32_t ETH_DeferralCheck; /*!< Enable/disable deferral check function (Half-Duplex mode) */ + uint32_t ETH_ReceiveAll; /*!< Enable/disable all frames reception by the MAC (No fitering)*/ + uint32_t ETH_SourceAddrFilter; /*!< Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */ + uint32_t ETH_PassControlFrames; /*!< Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */ + uint32_t ETH_BroadcastFramesReception; /*!< Enable/disable reception of Broadcast Frames */ + uint32_t ETH_DestinationAddrFilter; /*!< Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */ + uint32_t ETH_PromiscuousMode; /*!< Enable/disable Promiscuous Mode */ + uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */ + uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter */ + uint32_t ETH_HashTableHigh; /*!< This field contains the higher 32 bits of Hash table. */ + uint32_t ETH_HashTableLow; /*!< This field contains the lower 32 bits of Hash table. */ + uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame */ + uint32_t ETH_ZeroQuantaPause; /*!< Enable/disable the automatic generation of Zero-Quanta Pause Control frames */ + uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */ + uint32_t ETH_UnicastPauseFrameDetect; /*!< Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */ + uint32_t ETH_ReceiveFlowControl; /*!< Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */ + uint32_t ETH_TransmitFlowControl; /*!< Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */ + uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */ + uint32_t ETH_VLANTagIdentifier; /*!< VLAN tag identifier for receive frames */ + +/** + * @brief / * DMA + */ + uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Enable/disable Dropping of TCP/IP Checksum Error Frames */ + uint32_t ETH_ReceiveStoreForward; /*!< Enable/disable Receive store and forward */ + uint32_t ETH_FlushReceivedFrame; /*!< Enable/disable flushing of received frames */ + uint32_t ETH_TransmitStoreForward; /*!< Enable/disable Transmit store and forward */ + uint32_t ETH_TransmitThresholdControl; /*!< Selects the Transmit Threshold Control */ + uint32_t ETH_ForwardErrorFrames; /*!< Enable/disable forward to DMA of all frames except runt error frames */ + uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */ + uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO */ + uint32_t ETH_SecondFrameOperate; /*!< Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */ + uint32_t ETH_AddressAlignedBeats; /*!< Enable/disable Address Aligned Beats */ + uint32_t ETH_FixedBurst; /*!< Enable/disable the AHB Master interface fixed burst transfers */ + uint32_t ETH_RxDMABurstLength; /*!< Indicate the maximum number of beats to be transferred in one Rx DMA transaction */ + uint32_t ETH_TxDMABurstLength; /*!< Indicate the maximum number of beats to be transferred in one Tx DMA transaction */ + uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + uint32_t ETH_DMAArbitration; /*!< Selects DMA Tx/Rx arbitration */ +}ETH_InitTypeDef; + +/**--------------------------------------------------------------------------**/ +/** + * @brief DMA descriptors types + */ +/**--------------------------------------------------------------------------**/ + +/** + * @brief ETH DMA Desciptors data structure definition + */ +typedef struct { + uint32_t Status; /*!< Status */ + uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ +} ETH_DMADESCTypeDef; + +/** + * @} + */ + +/** @defgroup ETH_Exported_Constants + * @{ + */ +/**--------------------------------------------------------------------------**/ +/** + * @brief ETH Frames defines + */ +/**--------------------------------------------------------------------------**/ + +/** @defgroup ENET_Buffers_setting + * @{ + */ +#define ETH_MAX_PACKET_SIZE 1520 /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /*!< Ethernet CRC */ +#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ +#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA descriptors registers bits definition + */ +/**--------------------------------------------------------------------------**/ + +/* DMA Tx Desciptor -----------------------------------------------------------*/ +/**---------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ---------------------------------------------------------------------------------------------**/ + +/** + * @brief Bit definition of TDES0 register: DMA Tx descriptor status register + */ +#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */ +#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */ +#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */ +#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ +#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ +#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ +#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */ +#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ +#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ + +/** + * @brief Bit definition of TDES1 register + */ +#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ + +/** + * @brief Bit definition of TDES2 register + */ +#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of TDES3 register + */ +#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/** + * @} + */ + + +/** @defgroup DMA_Rx_descriptor + * @{ + */ + +/**-------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + -------------------------------------------------------------------------------------------------------------------**/ + +/** + * @brief Bit definition of RDES0 register: DMA Rx descriptor status register + */ +#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */ +#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/** + * @brief Bit definition of RDES1 register + */ +#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ + +/** + * @brief Bit definition of RDES2 register + */ +#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of RDES3 register + */ +#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/**--------------------------------------------------------------------------**/ +/** + * @brief Desciption of common PHY registers + */ +/**--------------------------------------------------------------------------**/ + +/** + * @} + */ + +/** @defgroup PHY_Read_write_Timeouts + * @{ + */ +#define PHY_READ_TO ((uint32_t)0x0004FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) + +/** + * @} + */ + +/** @defgroup PHY_Reset_Delay + * @{ + */ +#define PHY_ResetDelay ((uint32_t)0x04000000) + +/** + * @} + */ + +/** @defgroup PHY_Config_Delay + * @{ + */ +#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) + +/** + * @} + */ + +/** @defgroup PHY_Register_address + * @{ + */ +#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */ +#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */ + +/** + * @} + */ + +/** @defgroup PHY_basic_Control_register + * @{ + */ +#define PHY_Reset ((u16)0x8000) /*!< PHY Reset */ +#define PHY_Loopback ((u16)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((u16)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((u16)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_Powerdown ((u16)0x0800) /*!< Select the power down mode */ +#define PHY_Isolate ((u16)0x0400) /*!< Isolate PHY from MII */ + +/** + * @} + */ + +/** @defgroup PHY_basic_status_register + * @{ + */ +#define PHY_AutoNego_Complete ((u16)0x0020) /*!< Auto-Negotioation process completed */ +#define PHY_Linked_Status ((u16)0x0004) /*!< Valid link established */ +#define PHY_Jabber_detection ((u16)0x0002) /*!< Jabber condition detected */ + +/** + * @} + */ + +/** @defgroup PHY_status_register + * @{ + */ +/* The PHY status register value change from a PHY to another so the user have + to update this value depending on the used external PHY */ +/** + * @brief For LAN8700 + */ +//#define PHY_SR 31 /*!< Tranceiver Status Register */ +/** + * @brief For DP83848 + */ +#define PHY_SR 16 /*!< Tranceiver Status Register */ + +/* The Speed and Duplex mask values change from a PHY to another so the user have to update + this value depending on the used external PHY */ +/** + * @brief For LAN8700 + */ +//#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */ +//#define PHY_Duplex_Status ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */ + +/** + * @brief For DP83848 + */ +#define PHY_Speed_Status ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */ +#define PHY_Duplex_Status ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */ +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) +#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \ + ((REG) == PHY_BSR) || \ + ((REG) == PHY_SR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief MAC defines + */ +/**--------------------------------------------------------------------------**/ + +/** + * @} + */ + +/** @defgroup ETH_AutoNegotiation + * @{ + */ +#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) +#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) +#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \ + ((CMD) == ETH_AutoNegotiation_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_watchdog + * @{ + */ +#define ETH_Watchdog_Enable ((uint32_t)0x00000000) +#define ETH_Watchdog_Disable ((uint32_t)0x00800000) +#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \ + ((CMD) == ETH_Watchdog_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Jabber + * @{ + */ +#define ETH_Jabber_Enable ((uint32_t)0x00000000) +#define ETH_Jabber_Disable ((uint32_t)0x00400000) +#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \ + ((CMD) == ETH_Jabber_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Inter_Frame_Gap + * @{ + */ +#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ +#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \ + ((GAP) == ETH_InterFrameGap_88Bit) || \ + ((GAP) == ETH_InterFrameGap_80Bit) || \ + ((GAP) == ETH_InterFrameGap_72Bit) || \ + ((GAP) == ETH_InterFrameGap_64Bit) || \ + ((GAP) == ETH_InterFrameGap_56Bit) || \ + ((GAP) == ETH_InterFrameGap_48Bit) || \ + ((GAP) == ETH_InterFrameGap_40Bit)) + +/** + * @} + */ + +/** @defgroup ETH_Carrier_Sense + * @{ + */ +#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) +#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) +#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \ + ((CMD) == ETH_CarrierSense_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Speed + * @{ + */ +#define ETH_Speed_10M ((uint32_t)0x00000000) +#define ETH_Speed_100M ((uint32_t)0x00004000) +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \ + ((SPEED) == ETH_Speed_100M)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Own + * @{ + */ +#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) +#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) +#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \ + ((CMD) == ETH_ReceiveOwn_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Loop_back_Mode + * @{ + */ +#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) +#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) +#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \ + ((CMD) == ETH_LoopbackMode_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Duplex_mode + * @{ + */ +#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) +#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) +#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \ + ((MODE) == ETH_Mode_HalfDuplex)) + +/** + * @} + */ + +/** @defgroup ETH_Checksum_Offload + * @{ + */ +#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) +#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) +#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \ + ((CMD) == ETH_ChecksumOffload_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Retry_Transmission + * @{ + */ +#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) +#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) +#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \ + ((CMD) == ETH_RetryTransmission_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Automatic_Pad_CRC_Strip + * @{ + */ +#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) +#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \ + ((CMD) == ETH_AutomaticPadCRCStrip_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Back-Off_limit + * @{ + */ +#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) +#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) +#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) +#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) +#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \ + ((LIMIT) == ETH_BackOffLimit_8) || \ + ((LIMIT) == ETH_BackOffLimit_4) || \ + ((LIMIT) == ETH_BackOffLimit_1)) + +/** + * @} + */ + +/** @defgroup ETH_Deferral_Check + * @{ + */ +#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) +#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) +#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \ + ((CMD) == ETH_DeferralCheck_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_All + * @{ + */ +#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) +#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \ + ((CMD) == ETH_ReceiveAll_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Source_Addr_Filter + * @{ + */ +#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) +#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) +#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Pass_Control_Frames + * @{ + */ +#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ +#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter)) + +/** + * @} + */ + +/** @defgroup ETH_Broadcast_Frames_Reception + * @{ + */ +#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) +#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \ + ((CMD) == ETH_BroadcastFramesReception_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Destination_Addr_Filter + * @{ + */ +#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) +#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \ + ((FILTER) == ETH_DestinationAddrFilter_Inverse)) + +/** + * @} + */ + +/** @defgroup ETH_Promiscuous_Mode + * @{ + */ +#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) +#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) +#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \ + ((CMD) == ETH_PromiscuousMode_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_multicast_frames_filter + * @{ + */ +#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) +#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) +#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \ + ((FILTER) == ETH_MulticastFramesFilter_None)) + + +/** + * @} + */ + +/** @defgroup ETH_unicast_frames_filter + * @{ + */ +#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) +#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_Perfect)) + +/** + * @} + */ + +/** @defgroup ETH_Pause_Time + * @{ + */ +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) + +/** + * @} + */ + +/** @defgroup ETH_Zero_Quanta_Pause + * @{ + */ +#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) +#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \ + ((CMD) == ETH_ZeroQuantaPause_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Pause_Low_Threshold + * @{ + */ +#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ +#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus256)) + +/** + * @} + */ + +/** @defgroup ETH_Unicast_Pause_Frame_Detect + * @{ + */ +#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) +#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \ + ((CMD) == ETH_UnicastPauseFrameDetect_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Flow_Control + * @{ + */ +#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \ + ((CMD) == ETH_ReceiveFlowControl_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Transmit_Flow_Control + * @{ + */ +#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) +#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) +#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \ + ((CMD) == ETH_TransmitFlowControl_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_VLAN_Tag_Comparison + * @{ + */ +#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) +#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) +#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \ + ((COMPARISON) == ETH_VLANTagComparison_16Bit)) +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) + +/** + * @} + */ + +/** @defgroup ETH_MAC_Flags + * @{ + */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ +#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ + ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ + ((FLAG) == ETH_MAC_FLAG_PMT)) +/** + * @} + */ + +/** @defgroup ETH_MAC_Interrupts + * @{ + */ +#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ +#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ + ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ + ((IT) == ETH_MAC_IT_PMT)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses + * @{ + */ +#define ETH_MAC_Address0 ((uint32_t)0x00000000) +#define ETH_MAC_Address1 ((uint32_t)0x00000008) +#define ETH_MAC_Address2 ((uint32_t)0x00000010) +#define ETH_MAC_Address3 ((uint32_t)0x00000018) +#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \ + ((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) +#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter:_SA_DA_filed_of_received_frames + * @{ + */ +#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) +#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) +#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \ + ((FILTER) == ETH_MAC_AddressFilter_DA)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter:_Mask_bytes + * @{ + */ +#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ +#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \ + ((MASK) == ETH_MAC_AddressMask_Byte5) || \ + ((MASK) == ETH_MAC_AddressMask_Byte4) || \ + ((MASK) == ETH_MAC_AddressMask_Byte3) || \ + ((MASK) == ETH_MAC_AddressMask_Byte2) || \ + ((MASK) == ETH_MAC_AddressMask_Byte1)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA Desciptors defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_flags + * @{ + */ +#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \ + ((FLAG) == ETH_DMATxDesc_IC) || \ + ((FLAG) == ETH_DMATxDesc_LS) || \ + ((FLAG) == ETH_DMATxDesc_FS) || \ + ((FLAG) == ETH_DMATxDesc_DC) || \ + ((FLAG) == ETH_DMATxDesc_DP) || \ + ((FLAG) == ETH_DMATxDesc_TTSE) || \ + ((FLAG) == ETH_DMATxDesc_TER) || \ + ((FLAG) == ETH_DMATxDesc_TCH) || \ + ((FLAG) == ETH_DMATxDesc_TTSS) || \ + ((FLAG) == ETH_DMATxDesc_IHE) || \ + ((FLAG) == ETH_DMATxDesc_ES) || \ + ((FLAG) == ETH_DMATxDesc_JT) || \ + ((FLAG) == ETH_DMATxDesc_FF) || \ + ((FLAG) == ETH_DMATxDesc_PCE) || \ + ((FLAG) == ETH_DMATxDesc_LCA) || \ + ((FLAG) == ETH_DMATxDesc_NC) || \ + ((FLAG) == ETH_DMATxDesc_LCO) || \ + ((FLAG) == ETH_DMATxDesc_EC) || \ + ((FLAG) == ETH_DMATxDesc_VF) || \ + ((FLAG) == ETH_DMATxDesc_CC) || \ + ((FLAG) == ETH_DMATxDesc_ED) || \ + ((FLAG) == ETH_DMATxDesc_UF) || \ + ((FLAG) == ETH_DMATxDesc_DB)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_segment + * @{ + */ +#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */ +#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \ + ((SEGMENT) == ETH_DMATxDesc_FirstSegment)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control + * @{ + */ +#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ +#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull)) +/** + * @brief ETH DMA Tx Desciptor buffer size + */ +#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_flags + * @{ + */ +#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \ + ((FLAG) == ETH_DMARxDesc_AFM) || \ + ((FLAG) == ETH_DMARxDesc_ES) || \ + ((FLAG) == ETH_DMARxDesc_DE) || \ + ((FLAG) == ETH_DMARxDesc_SAF) || \ + ((FLAG) == ETH_DMARxDesc_LE) || \ + ((FLAG) == ETH_DMARxDesc_OE) || \ + ((FLAG) == ETH_DMARxDesc_VLAN) || \ + ((FLAG) == ETH_DMARxDesc_FS) || \ + ((FLAG) == ETH_DMARxDesc_LS) || \ + ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \ + ((FLAG) == ETH_DMARxDesc_LC) || \ + ((FLAG) == ETH_DMARxDesc_FT) || \ + ((FLAG) == ETH_DMARxDesc_RWT) || \ + ((FLAG) == ETH_DMARxDesc_RE) || \ + ((FLAG) == ETH_DMARxDesc_DBE) || \ + ((FLAG) == ETH_DMARxDesc_CE) || \ + ((FLAG) == ETH_DMARxDesc_MAMPCE)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_buffers_ + * @{ + */ +#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ +#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \ + ((BUFFER) == ETH_DMARxDesc_Buffer2)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame + * @{ + */ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) +#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \ + ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Receive_Store_Forward + * @{ + */ +#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \ + ((CMD) == ETH_ReceiveStoreForward_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Flush_Received_Frame + * @{ + */ +#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) +#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \ + ((CMD) == ETH_FlushReceivedFrame_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Store_Forward + * @{ + */ +#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) +#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) +#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \ + ((CMD) == ETH_TransmitStoreForward_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Threshold_Control + * @{ + */ +#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes)) +/** + * @} + */ + +/** @defgroup ETH_Forward_Error_Frames + * @{ + */ +#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) +#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \ + ((CMD) == ETH_ForwardErrorFrames_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Forward_Undersized_Good_Frames + * @{ + */ +#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) +#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \ + ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Threshold_Control + * @{ + */ +#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ +#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes)) +/** + * @} + */ + +/** @defgroup ETH_Second_Frame_Operate + * @{ + */ +#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) +#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) +#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \ + ((CMD) == ETH_SecondFrameOperate_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Address_Aligned_Beats + * @{ + */ +#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) +#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \ + ((CMD) == ETH_AddressAlignedBeats_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Fixed_Burst + * @{ + */ +#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) +#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) +#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \ + ((CMD) == ETH_FixedBurst_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Rx_DMA_Burst_Length + * @{ + */ +#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat)) + +/** + * @} + */ + +/** @defgroup ETH_Tx_DMA_Burst_Length + * @{ + */ +#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat)) +/** + * @brief ETH DMA Desciptor SkipLength + */ +#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Arbitration + * @{ + */ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) +#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \ + ((RATIO) == ETH_DMAArbitration_RxPriorTx)) +/** + * @} + */ + +/** @defgroup ETH_DMA_Flags + * @{ + */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ +#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */ +#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */ +#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ + +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) +#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ + ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \ + ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \ + ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ + ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ + ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ + ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ + ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ + ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ + ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ + ((FLAG) == ETH_DMA_FLAG_T)) +/** + * @} + */ + +/** @defgroup ETH_DMA_Interrupts + * @{ + */ +#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ +#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ +#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */ +#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */ +#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ + +#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ + ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ + ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ + ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ + ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ + ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ + ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ + ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ + ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_transmit_process_state_ + * @{ + */ +#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ + +/** + * @} + */ + + +/** @defgroup ETH_DMA_receive_process_state_ + * @{ + */ +#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the recieve frame into host memory */ + +/** + * @} + */ + +/** @defgroup ETH_DMA_overflow_ + * @{ + */ +#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ +#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \ + ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet PMT defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_PMT_Flags + * @{ + */ +#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ + ((FLAG) == ETH_PMT_FLAG_MPR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet MMC defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_MMC_Tx_Interrupts + * @{ + */ +#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ + +/** + * @} + */ + +/** @defgroup ETH_MMC_Rx_Interrupts + * @{ + */ +#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ +#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ + ((IT) != 0x00)) +#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ + ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ + ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) +/** + * @} + */ + +/** @defgroup ETH_MMC_Registers + * @{ + */ +#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */ +#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */ +#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */ +#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */ +#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */ +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */ +#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */ +#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */ +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */ + +/** + * @brief ETH MMC registers + */ +#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \ + ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \ + ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \ + ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \ + ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \ + ((REG) == ETH_MMCRGUFCR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet PTP defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_PTP_time_update_method + * @{ + */ +#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */ +#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */ +#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \ + ((UPDATE) == ETH_PTP_CoarseUpdate)) + +/** + * @} + */ + + +/** @defgroup ETH_PTP_Flags + * @{ + */ +#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */ +#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \ + ((FLAG) == ETH_PTP_FLAG_TSITE) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTU) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTI)) +/** + * @brief ETH PTP subsecond increment + */ +#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) + +/** + * @} + */ + + +/** @defgroup ETH_PTP_time_sign + * @{ + */ +#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */ +#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */ +#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \ + ((SIGN) == ETH_PTP_NegativeTime)) + +/** + * @brief ETH PTP time stamp low update + */ +#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) + +/** + * @brief ETH PTP registers + */ +#define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */ +#define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */ +#define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */ +#define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */ +#define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */ +#define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */ +#define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */ +#define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */ +#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ +#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \ + ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \ + ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \ + ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \ + ((REG) == ETH_PTPTTLR)) + +/** + * @} + */ + + +/** + * @} + */ + +/** @defgroup ETH_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions + * @{ + */ +void ETH_DeInit(void); +uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress); +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +void ETH_Start(void); +uint32_t ETH_HandleTxPkt(u8 *ppkt, u16 FrameLength); +uint32_t ETH_HandleRxPkt(u8 *ppkt); +uint32_t ETH_GetRxPktSize(void); +void ETH_DropRxPkt(void); + +/** + * @brief PHY + */ +u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg); +uint32_t ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue); +uint32_t ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState); + +/** + * @brief MAC + */ +void ETH_MACTransmissionCmd(FunctionalState NewState); +void ETH_MACReceptionCmd(FunctionalState NewState); +FlagStatus ETH_GetFlowControlBusyStatus(void); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState NewState); +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); +void ETH_MACAddressConfig(uint32_t MacAddr, u8 *Addr); +void ETH_GetMACAddress(uint32_t MacAddr, u8 *Addr); +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); + +/** + * @brief DMA Tx/Rx descriptors + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, uint32_t TxBuffCount); +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, uint32_t TxBuffCount); +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, uint32_t RxBuffCount); +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, uint32_t RxBuffCount); +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); + +/** + * @brief DMA + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); +uint32_t ETH_GetTransmitProcessState(void); +uint32_t ETH_GetReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); +void ETH_DMATransmissionCmd(FunctionalState NewState); +void ETH_DMAReceptionCmd(FunctionalState NewState); +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); +uint32_t ETH_GetRxOverflowMissedFrameCounter(void); +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); +uint32_t ETH_GetCurrentTxDescStartAddress(void); +uint32_t ETH_GetCurrentRxDescStartAddress(void); +uint32_t ETH_GetCurrentTxBufferAddress(void); +uint32_t ETH_GetCurrentRxBufferAddress(void); +void ETH_ResumeDMATransmission(void); +void ETH_ResumeDMAReception(void); + +/** + * @brief PMT + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); +void ETH_MagicPacketDetectionCmd(FunctionalState NewState); +void ETH_PowerDownCmd(FunctionalState NewState); + +/** + * @brief MMC + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState); +void ETH_MMCResetOnReadCmd(FunctionalState NewState); +void ETH_MMCCounterRolloverCmd(FunctionalState NewState); +void ETH_MMCCountersReset(void); +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); + +/** + * @brief PTP + */ +uint32_t ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, uint32_t *PTPTxTab); +uint32_t ETH_HandlePTPRxPkt(u8 *ppkt, uint32_t *PTPRxTab); +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, uint32_t TxBuffCount); +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, uint32_t RxBuffCount); +void ETH_EnablePTPTimeStampAddend(void); +void ETH_EnablePTPTimeStampInterruptTrigger(void); +void ETH_EnablePTPTimeStampUpdate(void); +void ETH_InitializePTPTimeStamp(void); +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod); +void ETH_PTPTimeStampCmd(FunctionalState NewState); +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG); +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue); +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); +void ETH_SetPTPTimeStampAddend(uint32_t Value); +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue); +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ETH_H */ +/** + * @} + */ + + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/ethernetlib/src/stm32_eth.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/ethernetlib/src/stm32_eth.c new file mode 100644 index 00000000..119b4dbf --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/ethernetlib/src/stm32_eth.c @@ -0,0 +1,3056 @@ +/** + ****************************************************************************** + * @file stm32_eth.c + * @author MCD Application Team + * @version V1.0.0 + * @date 06/19/2009 + * @brief This file provides all the ETH firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_eth.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32_ETH_Driver + * @brief ETH driver modules + * @{ + */ + +/** @defgroup ETH_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup ETH_Private_Defines + * @{ + */ +/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */ +ETH_DMADESCTypeDef *DMATxDescToSet; +ETH_DMADESCTypeDef *DMARxDescToGet; +ETH_DMADESCTypeDef *DMAPTPTxDescToSet; +ETH_DMADESCTypeDef *DMAPTPRxDescToGet; + +/* ETHERNET MAC address offsets */ +#define ETH_MAC_AddrHighBase (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_AddrLowBase (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_Mask ((uint32_t)0xFFFFFFE3) +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_Mask ((uint32_t)0xFF20810F) +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_Mask ((uint32_t)0x0000FF41) +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_Mask ((uint32_t)0xF8DE3F23) +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WakeupRegisterLength 8 +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RxOverflowMissedFramesCounterShift 17 +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATxDesc_CollisionCountShift 3 +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATxDesc_BufferSize2Shift 16 +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARxDesc_FrameLengthShift 16 +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARxDesc_Buffer2SizeShift 16 +/* ETHERNET errors */ +#define ETH_ERROR ((uint32_t)0) +#define ETH_SUCCESS ((uint32_t)1) +/** + * @} + */ + +/** @defgroup ETH_Private_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ETHERNET peripheral registers to their + * default reset values. + * @param None + * @retval : None + */ +void ETH_DeInit(void) +{ + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE); +} + +/** + * @brief Initializes the ETHERNET peripheral according to the specified + * parameters in the ETH_InitStruct . + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure + * that contains the configuration information for the + * specified ETHERNET peripheral. + * @param PHYAddress: external PHY address + * @retval : ETH_ERROR: Ethernet initialization failed + * ETH_SUCCESS: Ethernet successfully initialized + */ +uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) +{ + uint32_t RegValue = 0, tmpreg = 0; + __IO uint32_t i = 0; + RCC_ClocksTypeDef rcc_clocks; + uint32_t hclk = 120000000; + __IO uint32_t timeout = 0; + /* Check the parameters */ + /* MAC --------------------------*/ + assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation)); + assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog)); + assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber)); + assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap)); + assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense)); + assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed)); + assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn)); + assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode)); + assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode)); + assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload)); + assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission)); + assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip)); + assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit)); + assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck)); + assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll)); + assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter)); + assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames)); + assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception)); + assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter)); + assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode)); + assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); + assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter)); + assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime)); + assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause)); + assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold)); + assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect)); + assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl)); + assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl)); + assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison)); + assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier)); + /* DMA --------------------------*/ + assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame)); + assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward)); + assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame)); + assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward)); + assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl)); + assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames)); + assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames)); + assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl)); + assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate)); + assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats)); + assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst)); + assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength)); + assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); + assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); + assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); + /*-------------------------------- MAC Config ------------------------------*/ + /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/ + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg &= MACMIIAR_CR_Mask; + /* Get hclk frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + hclk = rcc_clocks.HCLK_Frequency; + /* Set CR bits depending on hclk value */ + if((hclk >= 20000000)&&(hclk < 35000000)) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; + } + else if((hclk >= 35000000)&&(hclk < 60000000)) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; + } + else if((hclk >= 60000000)&&(hclk <= 100000000)) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else /*if((hclk >= 100000000)&&(hclk <= 120000000)) */ + { + /* CSR Clock Range between 100-120 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; + } + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + ETH->MACMIIAR = (uint32_t)tmpreg; + /*-------------------- PHY initialization and configuration ----------------*/ + /* Put the PHY in reset mode */ + if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + + /* Delay to assure PHY reset */ + for(i = PHY_ResetDelay; i != 0; i--) + { + } + + if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) + { + /* We wait for linked satus... */ + do + { + timeout++; + } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Reset Timeout counter */ + timeout = 0; + + /* Enable Auto-Negotiation */ + if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + + /* Wait until the autonegotiation will be completed */ + do + { + timeout++; + } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Reset Timeout counter */ + timeout = 0; + + /* Read the result of the autonegotiation */ + RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR); + + /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */ + if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET) + { + /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */ + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + + } + else + { + /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */ + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + } + /* Configure the MAC with the speed fixed by the autonegotiation process */ + if(RegValue & PHY_Speed_Status) + { + /* Set Ethernet speed to 10M following the autonegotiation */ + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + } + else + { + /* Set Ethernet speed to 100M following the autonegotiation */ + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + } + } + else + { + if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) | + (uint16_t)(ETH_InitStruct->ETH_Speed >> 1)))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + /* Delay to assure PHY configuration */ + for(i = PHY_ConfigDelay; i != 0; i--) + { + } + } + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = ETH->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg &= MACCR_CLEAR_Mask; + /* Set the WD bit according to ETH_Watchdog value */ + /* Set the JD: bit according to ETH_Jabber value */ + /* Set the IFG bit according to ETH_InterFrameGap value */ + /* Set the DCRS bit according to ETH_CarrierSense value */ + /* Set the FES bit according to ETH_Speed value */ + /* Set the DO bit according to ETH_ReceiveOwn value */ + /* Set the LM bit according to ETH_LoopbackMode value */ + /* Set the DM bit according to ETH_Mode value */ + /* Set the IPC bit according to ETH_ChecksumOffload value */ + /* Set the DR bit according to ETH_RetryTransmission value */ + /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ + /* Set the BL bit according to ETH_BackOffLimit value */ + /* Set the DC bit according to ETH_DeferralCheck value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | + ETH_InitStruct->ETH_Jabber | + ETH_InitStruct->ETH_InterFrameGap | + ETH_InitStruct->ETH_CarrierSense | + ETH_InitStruct->ETH_Speed | + ETH_InitStruct->ETH_ReceiveOwn | + ETH_InitStruct->ETH_LoopbackMode | + ETH_InitStruct->ETH_Mode | + ETH_InitStruct->ETH_ChecksumOffload | + ETH_InitStruct->ETH_RetryTransmission | + ETH_InitStruct->ETH_AutomaticPadCRCStrip | + ETH_InitStruct->ETH_BackOffLimit | + ETH_InitStruct->ETH_DeferralCheck); + /* Write to ETHERNET MACCR */ + ETH->MACCR = (uint32_t)tmpreg; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Set the RA bit according to ETH_ReceiveAll value */ + /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */ + /* Set the PCF bit according to ETH_PassControlFrames value */ + /* Set the DBF bit according to ETH_BroadcastFramesReception value */ + /* Set the DAIF bit according to ETH_DestinationAddrFilter value */ + /* Set the PR bit according to ETH_PromiscuousMode value */ + /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */ + /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */ + /* Write to ETHERNET MACFFR */ + ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | + ETH_InitStruct->ETH_SourceAddrFilter | + ETH_InitStruct->ETH_PassControlFrames | + ETH_InitStruct->ETH_BroadcastFramesReception | + ETH_InitStruct->ETH_DestinationAddrFilter | + ETH_InitStruct->ETH_PromiscuousMode | + ETH_InitStruct->ETH_MulticastFramesFilter | + ETH_InitStruct->ETH_UnicastFramesFilter); + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ + /* Write to ETHERNET MACHTHR */ + ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh; + /* Write to ETHERNET MACHTLR */ + ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + /* Get the ETHERNET MACFCR value */ + tmpreg = ETH->MACFCR; + /* Clear xx bits */ + tmpreg &= MACFCR_CLEAR_Mask; + + /* Set the PT bit according to ETH_PauseTime value */ + /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */ + /* Set the PLT bit according to ETH_PauseLowThreshold value */ + /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */ + /* Set the RFE bit according to ETH_ReceiveFlowControl value */ + /* Set the TFE bit according to ETH_TransmitFlowControl value */ + tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | + ETH_InitStruct->ETH_ZeroQuantaPause | + ETH_InitStruct->ETH_PauseLowThreshold | + ETH_InitStruct->ETH_UnicastPauseFrameDetect | + ETH_InitStruct->ETH_ReceiveFlowControl | + ETH_InitStruct->ETH_TransmitFlowControl); + /* Write to ETHERNET MACFCR */ + ETH->MACFCR = (uint32_t)tmpreg; + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ + /* Set the ETV bit according to ETH_VLANTagComparison value */ + /* Set the VL bit according to ETH_VLANTagIdentifier value */ + ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | + ETH_InitStruct->ETH_VLANTagIdentifier); + + /*-------------------------------- DMA Config ------------------------------*/ + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg = ETH->DMAOMR; + /* Clear xx bits */ + tmpreg &= DMAOMR_CLEAR_Mask; + + /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */ + /* Set the RSF bit according to ETH_ReceiveStoreForward value */ + /* Set the DFF bit according to ETH_FlushReceivedFrame value */ + /* Set the TSF bit according to ETH_TransmitStoreForward value */ + /* Set the TTC bit according to ETH_TransmitThresholdControl value */ + /* Set the FEF bit according to ETH_ForwardErrorFrames value */ + /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */ + /* Set the RTC bit according to ETH_ReceiveThresholdControl value */ + /* Set the OSF bit according to ETH_SecondFrameOperate value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | + ETH_InitStruct->ETH_ReceiveStoreForward | + ETH_InitStruct->ETH_FlushReceivedFrame | + ETH_InitStruct->ETH_TransmitStoreForward | + ETH_InitStruct->ETH_TransmitThresholdControl | + ETH_InitStruct->ETH_ForwardErrorFrames | + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | + ETH_InitStruct->ETH_ReceiveThresholdControl | + ETH_InitStruct->ETH_SecondFrameOperate); + /* Write to ETHERNET DMAOMR */ + ETH->DMAOMR = (uint32_t)tmpreg; + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + /* Set the AAL bit according to ETH_AddressAlignedBeats value */ + /* Set the FB bit according to ETH_FixedBurst value */ + /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */ + /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */ + /* Set the DSL bit according to ETH_DesciptorSkipLength value */ + /* Set the PR and DA bits according to ETH_DMAArbitration value */ + ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | + ETH_InitStruct->ETH_FixedBurst | + ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + ETH_InitStruct->ETH_TxDMABurstLength | + (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | + ETH_InitStruct->ETH_DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + /* Return Ethernet configuration success */ + return ETH_SUCCESS; +} + +/** + * @brief Fills each ETH_InitStruct member with its default value. + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure + * which will be initialized. + * @retval : None + */ +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct) +{ + /* ETH_InitStruct members default value */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + /*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable; + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; + ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; +} + +/** + * @brief Enables ENET MAC and DMA reception/transmission + * @param None + * @retval : None + */ +void ETH_Start(void) +{ + /* Enable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionCmd(ENABLE); + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(); + /* Enable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionCmd(ENABLE); + + /* Start DMA transmission */ + ETH_DMATransmissionCmd(ENABLE); + /* Start DMA reception */ + ETH_DMAReceptionCmd(ENABLE); +} + +/** + * @brief Transmits a packet, from application buffer, pointed by ppkt. + * @param ppkt: pointer to application packet buffer to transmit. + * @param FrameLength: Tx Packet size. + * @retval : ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission + */ +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) +{ + uint32_t offset = 0; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); + } + + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + /* Chained Mode */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Receives a packet and copies it to memory pointed by ppkt. + * @param ppkt: pointer to application packet receive buffer. + * @retval : ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct + */ +uint32_t ETH_HandleRxPkt(uint8_t *ppkt) +{ + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + } + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + /* Return Frame Length/ERROR */ + return (framelength); +} + +/** + * @brief Get the size of received the received packet. + * @param None + * @retval : framelength: received packet size + */ +uint32_t ETH_GetRxPktSize(void) +{ + uint32_t frameLength = 0; + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the size of the packet: including 4 bytes of the CRC */ + frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); + } + + /* Return Frame Length */ + return frameLength; +} + +/** + * @brief Drop a Received packet (too small packet, etc...) + * @param None + * @retval : None + */ +void ETH_DropRxPkt(void) +{ + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read: this will + be the first Rx descriptor in this case */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } +} + +/*--------------------------------- PHY ------------------------------------*/ +/** + * @brief Read a PHY register + * @param PHYAddress: PHY device address, is the index of one of supported + * 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg: PHY register address, is the index of one of the 32 + * PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR : Tranceiver Basic Control Register + * @arg PHY_BSR : Tranceiver Basic Status Register + * @arg PHY_SR : Tranceiver Status Register + * @arg More PHY register could be read depending on the used PHY + * @retval : ETH_ERROR: in case of timeout + * MAC MIIDR register value: Data read from the selected PHY register (correct read ) + */ +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) +{ + uint32_t tmpreg = 0; +__IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_Mask; + /* Prepare the MII address register value */ + tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } + + /* Return data register value */ + return (uint16_t)(ETH->MACMIIDR); +} + +/** + * @brief Write to a PHY register + * @param PHYAddress: PHY device address, is the index of one of supported + * 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg: PHY register address, is the index of one of the 32 + * PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR : Tranceiver Control Register + * @arg More PHY register could be written depending on the used PHY + * @param PHYValue: the value to write + * @retval : ETH_ERROR: in case of timeout + * ETH_SUCCESS: for correct write + */ +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_Mask; + /* Prepare the MII register address value */ + tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Give the value to the MII data register */ + ETH->MACMIIDR = PHYValue; + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_WRITE_TO) + { + return ETH_ERROR; + } + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Enables or disables the PHY loopBack mode. + * @param PHYAddress: PHY device address, is the index of one of supported + * 32 PHY devices. + * This parameter can be one of the following values: + * @param NewState: new state of the PHY loopBack mode. + * This parameter can be: ENABLE or DISABLE. + * Note: Don't be confused with ETH_MACLoopBackCmd function + * which enables internal loopback at MII level + * @retval : ETH_ERROR: in case of bad PHY configuration + * ETH_SUCCESS: for correct PHY configuration + */ +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the PHY configuration to update it */ + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + + if (NewState != DISABLE) + { + /* Enable the PHY loopback mode */ + tmpreg |= PHY_Loopback; + } + else + { + /* Disable the PHY loopback mode: normal mode */ + tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); + } + /* Update the PHY control register with the new configuration */ + if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) + { + return ETH_SUCCESS; + } + else + { + /* Return SUCCESS */ + return ETH_ERROR; + } +} + +/*--------------------------------- MAC ------------------------------------*/ +/** + * @brief Enables or disables the MAC transmission. + * @param NewState: new state of the MAC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACTransmissionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC transmission */ + ETH->MACCR |= ETH_MACCR_TE; + } + else + { + /* Disable the MAC transmission */ + ETH->MACCR &= ~ETH_MACCR_TE; + } +} + +/** + * @brief Enables or disables the MAC reception. + * @param NewState: new state of the MAC reception. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACReceptionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC reception */ + ETH->MACCR |= ETH_MACCR_RE; + } + else + { + /* Disable the MAC reception */ + ETH->MACCR &= ~ETH_MACCR_RE; + } +} + +/** + * @brief Checks whether the ETHERNET flow control busy bit is set or not. + * @param None + * @retval : The new state of flow control busy status bit (SET or RESET). + */ +FlagStatus ETH_GetFlowControlBusyStatus(void) +{ + FlagStatus bitstatus = RESET; + /* The Flow Control register should not be written to until this bit is cleared */ + if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Initiate a Pause Control Frame (Full-duplex only). + * @param None + * @retval : None + */ +void ETH_InitiatePauseControlFrame(void) +{ + /* When Set In full duplex MAC initiates pause control frame */ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; +} + +/** + * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). + * @param NewState: new state of the MAC BackPressure operation activation. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_BackPressureActivationCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Activate the MAC BackPressure operation */ + /* In Half duplex: during backpressure, when the MAC receives a new frame, + the transmitter starts sending a JAM pattern resulting in a collision */ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; + } + else + { + /* Desactivate the MAC BackPressure operation */ + ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; + } +} + +/** + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param ETH_MAC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag + * @retval : The new state of ETHERNET MAC flag (SET or RESET). + */ +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); + if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. + * @param ETH_MAC_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt + * @arg ETH_MAC_IT_MMCR : MMC receive interrupt + * @arg ETH_MAC_IT_MMC : MMC interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval : The new state of ETHERNET MAC interrupt (SET or RESET). + */ +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); + if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the specified ETHERNET MAC interrupts. + * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @param NewState: new state of the specified ETHERNET MAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_IT(ETH_MAC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC interrupts */ + ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); + } + else + { + /* Disable the selected ETHERNET MAC interrupts */ + ETH->MACIMR |= ETH_MAC_IT; + } +} + +/** + * @brief Configures the selected MAC address. + * @param MacAddr: The MAC addres to configure. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Addr: Pointer on MAC address buffer data (6 bytes). + * @retval : None + */ +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Calculate the selectecd MAC address high register */ + tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + /* Load the selectecd MAC address high register */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg; + /* Calculate the selectecd MAC address low register */ + tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + + /* Load the selectecd MAC address low register */ + (*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg; +} + +/** + * @brief Get the selected MAC address. + * @param MacAddr: The MAC addres to return. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Addr: Pointer on MAC address buffer data (6 bytes). + * @retval : None + */ +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Get the selectecd MAC address high register */ + tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)); + + /* Calculate the selectecd MAC address buffer */ + Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[4] = (tmpreg & (uint8_t)0xFF); + /* Load the selectecd MAC address low register */ + tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)); + /* Calculate the selectecd MAC address buffer */ + Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); + Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); + Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF); + Addr[0] = (tmpreg & (uint8_t)0xFF); +} + +/** + * @brief Enables or disables the Address filter module uses the specified + * ETHERNET MAC address for perfect filtering + * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param NewState: new state of the specified ETHERNET MAC address use. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE; + } + else + { + /* Disable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE); + } +} + +/** + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Filter: specifies the used frame received field for comparaison + * This parameter can be one of the following values: + * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare + * with the SA fields of the received frame. + * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare + * with the DA fields of the received frame. + * @retval : None + */ +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter)); + + if (Filter != ETH_MAC_AddressFilter_DA) + { + /* The selected ETHERNET MAC address is used to compare with the SA fields of the + received frame. */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA; + } + else + { + /* The selected ETHERNET MAC address is used to compare with the DA fields of the + received frame. */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA); + } +} + +/** + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param MaskByte: specifies the used address bytes for comparaison + * This parameter can be any combination of the following values: + * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8]. + * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0]. + * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24]. + * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16]. + * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8]. + * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0]. + * @retval : None + */ +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte)); + + /* Clear MBC bits in the selected MAC address high register */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC); + /* Set the selected Filetr mask bytes */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte; +} +/*------------------------ DMA Tx/Rx Desciptors -----------------------------*/ + +/** + * @brief Initializes the DMA Tx descriptors in chain mode. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff: Pointer on the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval : None + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Second Address Chained bit */ + DMATxDesc->Status = ETH_DMATxDesc_TCH; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Initializes the DMA Tx descriptors in ring mode. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff1: Pointer on the first TxBuffer1 list + * @param TxBuff2: Pointer on the first TxBuffer2 list + * @param TxBuffCount: Number of the used Tx desc in the list + * Note: see decriptor skip length defined in ETH_DMA_InitStruct + * for the number of Words to skip between two unchained descriptors. + * @retval : None + */ +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (TxBuffCount-1)) + { + /* Set Transmit End of Ring bit */ + DMATxDesc->Status = ETH_DMATxDesc_TER; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param ETH_DMATxDescFlag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMATxDesc_IC : Interrupt on completetion + * @arg ETH_DMATxDesc_LS : Last Segment + * @arg ETH_DMATxDesc_FS : First Segment + * @arg ETH_DMATxDesc_DC : Disable CRC + * @arg ETH_DMATxDesc_DP : Disable Pad + * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable + * @arg ETH_DMATxDesc_TER : Transmit End of Ring + * @arg ETH_DMATxDesc_TCH : Second Address Chained + * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status + * @arg ETH_DMATxDesc_IHE : IP Header Error + * @arg ETH_DMATxDesc_ES : Error summary + * @arg ETH_DMATxDesc_JT : Jabber Timeout + * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush + * @arg ETH_DMATxDesc_PCE : Payload Checksum Error + * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission + * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver + * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision + * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions + * @arg ETH_DMATxDesc_VF : VLAN Frame + * @arg ETH_DMATxDesc_CC : Collision Count + * @arg ETH_DMATxDesc_ED : Excessive Deferral + * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory + * @arg ETH_DMATxDesc_DB : Deferred Bit + * @retval : The new state of ETH_DMATxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag)); + + if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @retval : The Transmit descriptor collision counter value. + */ +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift); +} + +/** + * @brief Set the specified DMA Tx Desc Own bit. + * @param DMATxDesc: Pointer on a Tx desc + * @retval : None + */ +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) +{ + /* Set the DMA Tx Desc Own bit */ + DMATxDesc->Status |= ETH_DMATxDesc_OWN; +} + +/** + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * @param DMATxDesc: Pointer on a Tx desc + * @param NewState: new state of the DMA Tx Desc transmit interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status |= ETH_DMATxDesc_IC; + } + else + { + /* Disable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC); + } +} + +/** + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * @param DMATxDesc: Pointer on a Tx desc + * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment + * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment + * @retval : None + */ +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment)); + + /* Selects the DMA Tx Desc Frame segment */ + DMATxDesc->Status |= DMATxDesc_FrameSegment; +} + +/** + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass + * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * @retval : None + */ +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum)); + + /* Set the selected DMA Tx desc checksum insertion control */ + DMATxDesc->Status |= DMATxDesc_Checksum; +} + +/** + * @brief Enables or disables the DMA Tx Desc CRC. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc CRC. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc CRC */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); + } + else + { + /* Disable the selected DMA Tx Desc CRC */ + DMATxDesc->Status |= ETH_DMATxDesc_DC; + } +} + +/** + * @brief Enables or disables the DMA Tx Desc end of ring. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc end of ring. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status |= ETH_DMATxDesc_TER; + } + else + { + /* Disable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); + } +} + +/** + * @brief Enables or disables the DMA Tx Desc second address chained. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc second address chained. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status |= ETH_DMATxDesc_TCH; + } + else + { + /* Disable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); + } +} + +/** + * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc padding for + * frame shorter than 64 bytes. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); + } + else + { + /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/ + DMATxDesc->Status |= ETH_DMATxDesc_DP; + } +} + +/** + * @brief Enables or disables the DMA Tx Desc time stamp. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc time stamp. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + } + else + { + /* Disable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); + } +} + +/** + * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. + * @param DMATxDesc: Pointer on a Tx desc + * @param BufferSize1: specifies the Tx desc buffer1 size. + * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used). + * @retval : None + */ +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1)); + assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2)); + + /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */ + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift)); +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff: Pointer on the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval : None + */ +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Initializes the DMA Rx descriptors in ring mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff1: Pointer on the first RxBuffer1 list + * @param RxBuff2: Pointer on the first RxBuffer2 list + * @param RxBuffCount: Number of the used Rx desc in the list + * Note: see decriptor skip length defined in ETH_DMA_InitStruct + * for the number of Words to skip between two unchained descriptors. + * @retval : None + */ +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + /* Set Buffer1 size */ + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (RxBuffCount-1)) + { + /* Set Receive End of Ring bit */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param ETH_DMARxDescFlag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame + * @arg ETH_DMARxDesc_ES: Error summary + * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame + * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame + * @arg ETH_DMARxDesc_LE: Frame size not matching with length field + * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow + * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame + * @arg ETH_DMARxDesc_FS: First descriptor of the frame + * @arg ETH_DMARxDesc_LS: Last descriptor of the frame + * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * @arg ETH_DMARxDesc_LC: Late collision occurred during reception + * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3 + * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception + * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface + * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits + * @arg ETH_DMARxDesc_CE: CRC error + * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * @retval : The new state of ETH_DMARxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag)); + if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Set the specified DMA Rx Desc Own bit. + * @param DMARxDesc: Pointer on a Rx desc + * @retval : None + */ +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) +{ + /* Set the DMA Rx Desc Own bit */ + DMARxDesc->Status |= ETH_DMARxDesc_OWN; +} + +/** + * @brief Returns the specified DMA Rx Desc frame length. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @retval : The Rx descriptor received frame length. + */ +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift); +} + +/** + * @brief Enables or disables the specified DMA Rx Desc receive interrupt. + * @param DMARxDesc: Pointer on a Rx desc + * @param NewState: new state of the specified DMA Rx Desc interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC); + } + else + { + /* Disable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; + } +} + +/** + * @brief Enables or disables the DMA Rx Desc end of ring. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param NewState: new state of the specified DMA Rx Desc end of ring. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + else + { + /* Disable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); + } +} + +/** + * @brief Enables or disables the DMA Rx Desc second address chained. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param NewState: new state of the specified DMA Rx Desc second address chained. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + } + else + { + /* Disable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); + } +} + +/** + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer. + * This parameter can be any one of the following values: + * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1 + * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 + * @retval : The Receive descriptor frame length. + */ +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer)); + + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) + { + /* Return the DMA Rx Desc buffer2 size */ + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift); + } + else + { + /* Return the DMA Rx Desc buffer1 size */ + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + } +} + +/*--------------------------------- DMA ------------------------------------*/ +/** + * @brief Resets all MAC subsystem internal registers and logic. + * @param None + * @retval : None + */ +void ETH_SoftwareReset(void) +{ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + ETH->DMABMR |= ETH_DMABMR_SR; +} + +/** + * @brief Checks whether the ETHERNET software reset bit is set or not. + * @param None + * @retval : The new state of DMA Bus Mode register SR bit (SET or RESET). + */ +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param ETH_DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag + * @arg ETH_DMA_FLAG_PMT : PMT flag + * @arg ETH_DMA_FLAG_MMC : MMC flag + * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access + * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr + * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ET : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Underflow flag + * @arg ETH_DMA_FLAG_RO : Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag + * @retval : The new state of ETH_DMA_FLAG (SET or RESET). + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG)); + if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the ETHERNET’s DMA pending flag. + * @param ETH_DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ETI : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag + * @arg ETH_DMA_FLAG_RO : Receive Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag + * @retval : None + */ +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG)); + + /* Clear the selected ETHERNET DMA FLAG */ + ETH->DMASR = (uint32_t) ETH_DMA_FLAG; +} + +/** + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * @param ETH_DMA_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt + * @arg ETH_DMA_IT_PMT : PMT interrupt + * @arg ETH_DMA_IT_MMC : MMC interrupt + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @retval : The new state of ETH_DMA_IT (SET or RESET). + */ +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT)); + if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the ETHERNET’s DMA IT pending bit. + * @param ETH_DMA_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ETI : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt + * @arg ETH_DMA_IT_RO : Receive Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @retval : None + */ +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + + /* Clear the selected ETHERNET DMA IT */ + ETH->DMASR = (uint32_t) ETH_DMA_IT; +} + +/** + * @brief Returns the ETHERNET DMA Transmit Process State. + * @param None + * @retval : The new ETHERNET DMA Transmit Process State: + * This can be one of the following values: + * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued + * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor + * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status + * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory + * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe + * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor + */ +uint32_t ETH_GetTransmitProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); +} + +/** + * @brief Returns the ETHERNET DMA Receive Process State. + * @param None + * @retval : The new ETHERNET DMA Receive Process State: + * This can be one of the following values: + * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued + * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor + * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet + * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable + * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor + * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory + */ +uint32_t ETH_GetReceiveProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); +} + +/** + * @brief Clears the ETHERNET transmit FIFO. + * @param None + * @retval : None + */ +void ETH_FlushTransmitFIFO(void) +{ + /* Set the Flush Transmit FIFO bit */ + ETH->DMAOMR |= ETH_DMAOMR_FTF; +} + +/** + * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. + * @param None + * @retval : The new state of ETHERNET flush transmit FIFO bit (SET or RESET). + */ +FlagStatus ETH_GetFlushTransmitFIFOStatus(void) +{ + FlagStatus bitstatus = RESET; + if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the DMA transmission. + * @param NewState: new state of the DMA transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATransmissionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transmission */ + ETH->DMAOMR |= ETH_DMAOMR_ST; + } + else + { + /* Disable the DMA transmission */ + ETH->DMAOMR &= ~ETH_DMAOMR_ST; + } +} + +/** + * @brief Enables or disables the DMA reception. + * @param NewState: new state of the DMA reception. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMAReceptionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA reception */ + ETH->DMAOMR |= ETH_DMAOMR_SR; + } + else + { + /* Disable the DMA reception */ + ETH->DMAOMR &= ~ETH_DMAOMR_SR; + } +} + +/** + * @brief Enables or disables the specified ETHERNET DMA interrupts. + * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @param NewState: new state of the specified ETHERNET DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET DMA interrupts */ + ETH->DMAIER |= ETH_DMA_IT; + } + else + { + /* Disable the selected ETHERNET DMA interrupts */ + ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT); + } +} + +/** + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter + * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter + * @retval : The new state of ETHERNET DMA overflow Flag (SET or RESET). + */ +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow)); + + if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. + * @param None + * @retval : The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_GetRxOverflowMissedFrameCounter(void) +{ + return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift)); +} + +/** + * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. + * @param None + * @retval : The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) +{ + return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); +} + +/** + * @brief Get the ETHERNET DMA DMACHTDR register value. + * @param None + * @retval : The value of the current Tx desc start address. + */ +uint32_t ETH_GetCurrentTxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHTDR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHRDR register value. + * @param None + * @retval : The value of the current Rx desc start address. + */ +uint32_t ETH_GetCurrentRxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHRDR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHTBAR register value. + * @param None + * @retval : The value of the current Tx desc buffer address. + */ +uint32_t ETH_GetCurrentTxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHTBAR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHRBAR register value. + * @param None + * @retval : The value of the current Rx desc buffer address. + */ +uint32_t ETH_GetCurrentRxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHRBAR)); +} + +/** + * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand + * register: (the data written could be anything). This forces + * the DMA to resume transmission. + * @param None + * @retval : None. + */ +void ETH_ResumeDMATransmission(void) +{ + ETH->DMATPDR = 0; +} + +/** + * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand + * register: (the data written could be anything). This forces + * the DMA to resume reception. + * @param None + * @retval : None. + */ +void ETH_ResumeDMAReception(void) +{ + ETH->DMARPDR = 0; +} + +/*--------------------------------- PMT ------------------------------------*/ +/** + * @brief Reset Wakeup frame filter register pointer. + * @param None + * @retval : None + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; +} + +/** + * @brief Populates the remote wakeup frame registers. + * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer + * data (8 words). + * @retval : None + */ +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) +{ + uint32_t i = 0; + + /* Fill Remote Wake-up Frame Filter register with Buffer data */ + for(i =0; iMACRWUFFR = Buffer[i]; + } +} + +/** + * @brief Enables or disables any unicast packet filtered by the MAC + * (DAF) address recognition to be a wake-up frame. + * @param NewState: new state of the MAC Global Unicast Wake-Up. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; + } + else + { + /* Disable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; + } +} + +/** + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * @param ETH_PMT_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset + * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPR : Magic Packet Received + * @retval : The new state of ETHERNET PMT Flag (SET or RESET). + */ +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG)); + + if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the MAC Wake-Up Frame Detection. + * @param NewState: new state of the MAC Wake-Up Frame Detection. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; + } + else + { + /* Disable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + } +} + +/** + * @brief Enables or disables the MAC Magic Packet Detection. + * @param NewState: new state of the MAC Magic Packet Detection. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MagicPacketDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Magic Packet Detection */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; + } + else + { + /* Disable the MAC Magic Packet Detection */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + } +} + +/** + * @brief Enables or disables the MAC Power Down. + * @param NewState: new state of the MAC Power Down. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_PowerDownCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Power Down */ + /* This puts the MAC in power down mode */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; + } + else + { + /* Disable the MAC Power Down */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; + } +} + +/*--------------------------------- MMC ------------------------------------*/ +/** + * @brief Enables or disables the MMC Counter Freeze. + * @param NewState: new state of the MMC Counter Freeze. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MMC Counter Freeze */ + ETH->MMCCR |= ETH_MMCCR_MCF; + } + else + { + /* Disable the MMC Counter Freeze */ + ETH->MMCCR &= ~ETH_MMCCR_MCF; + } +} + +/** + * @brief Enables or disables the MMC Reset On Read. + * @param NewState: new state of the MMC Reset On Read. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCResetOnReadCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MMC Counter reset on read */ + ETH->MMCCR |= ETH_MMCCR_ROR; + } + else + { + /* Disable the MMC Counter reset on read */ + ETH->MMCCR &= ~ETH_MMCCR_ROR; + } +} + +/** + * @brief Enables or disables the MMC Counter Stop Rollover. + * @param NewState: new state of the MMC Counter Stop Rollover. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCCounterRolloverCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Disable the MMC Counter Stop Rollover */ + ETH->MMCCR &= ~ETH_MMCCR_CSR; + } + else + { + /* Enable the MMC Counter Stop Rollover */ + ETH->MMCCR |= ETH_MMCCR_CSR; + } +} + +/** + * @brief Resets the MMC Counters. + * @param None + * @retval : None + */ +void ETH_MMCCountersReset(void) +{ + /* Resets the MMC Counters */ + ETH->MMCCR |= ETH_MMCCR_CR; +} + +/** + * @brief Enables or disables the specified ETHERNET MMC interrupts. + * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt + * sources to be enabled or disabled. + * This parameter can be any combination of Tx interrupt or + * any combination of Rx interrupt (but not both)of the following values: + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value + * @param NewState: new state of the specified ETHERNET MMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + /* Remove egister mak from IT */ + ETH_MMC_IT &= 0xEFFFFFFF; + + /* ETHERNET MMC Rx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCRIMR |= ETH_MMC_IT; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCTIMR |= ETH_MMC_IT; + } + } +} + +/** + * @brief Checks whether the specified ETHERNET MMC IT is set or not. + * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value + * @retval : The value of ETHERNET MMC IT (SET or RESET). + */ +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); + + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + /* ETHERNET MMC Rx interrupts selected */ + /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ + if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ + if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/** + * @brief Get the specified ETHERNET MMC register value. + * @param ETH_MMCReg: specifies the ETHERNET MMC register. + * This parameter can be one of the following values: + * @arg ETH_MMCCR : MMC CR register + * @arg ETH_MMCRIR : MMC RIR register + * @arg ETH_MMCTIR : MMC TIR register + * @arg ETH_MMCRIMR : MMC RIMR register + * @arg ETH_MMCTIMR : MMC TIMR register + * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register + * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register + * @arg ETH_MMCTGFCR : MMC TGFCR register + * @arg ETH_MMCRFCECR : MMC RFCECR register + * @arg ETH_MMCRFAECR : MMC RFAECR register + * @arg ETH_MMCRGUFCR : MMC RGUFCRregister + * @retval : The value of ETHERNET MMC Register value. + */ +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) +{ + /* Check the parameters */ + assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg)); + + /* Return the selected register value */ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); +} +/*--------------------------------- PTP ------------------------------------*/ + +/** + * @brief Updated the PTP block for fine correction with the Time Stamp + * Addend register value. + * @param None + * @retval : None + */ +void ETH_EnablePTPTimeStampAddend(void) +{ + /* Enable the PTP block update with the Time Stamp Addend register value */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; +} + +/** + * @brief Enable the PTP Time Stamp interrupt trigger + * @param None + * @retval : None + */ +void ETH_EnablePTPTimeStampInterruptTrigger(void) +{ + /* Enable the PTP target time interrupt */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; +} + +/** + * @brief Updated the PTP system time with the Time Stamp Update register + * value. + * @param None + * @retval : None + */ +void ETH_EnablePTPTimeStampUpdate(void) +{ + /* Enable the PTP system time update with the Time Stamp Update register value */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; +} + +/** + * @brief Initialize the PTP Time Stamp + * @param None + * @retval : None + */ +void ETH_InitializePTPTimeStamp(void) +{ + /* Initialize the PTP Time Stamp */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; +} + +/** + * @brief Selects the PTP Update method + * @param UpdateMethod: the PTP Update method + * This parameter can be one of the following values: + * @arg ETH_PTP_FineUpdate : Fine Update method + * @arg ETH_PTP_CoarseUpdate : Coarse Update method + * @retval : None + */ +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_UPDATE(UpdateMethod)); + + if (UpdateMethod != ETH_PTP_CoarseUpdate) + { + /* Enable the PTP Fine Update method */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; + } + else + { + /* Disable the PTP Coarse Update method */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); + } +} + +/** + * @brief Enables or disables the PTP time stamp for transmit and receive frames. + * @param NewState: new state of the PTP time stamp for transmit and receive frames + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_PTPTimeStampCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSE; + } + else + { + /* Disable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); + } +} + +/** + * @brief Checks whether the specified ETHERNET PTP flag is set or not. + * @param ETH_PTP_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PTP_FLAG_TSARU : Addend Register Update + * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable + * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update + * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize + * @retval : The new state of ETHERNET PTP Flag (SET or RESET). + */ +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG)); + + if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Sets the system time Sub-Second Increment value. + * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value. + * @retval : None + */ +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue)); + /* Set the PTP Sub-Second Increment Register */ + ETH->PTPSSIR = SubSecondValue; +} + +/** + * @brief Sets the Time Stamp update sign and values. + * @param Sign: specifies the PTP Time update value sign. + * This parameter can be one of the following values: + * @arg ETH_PTP_PositiveTime : positive time value. + * @arg ETH_PTP_NegativeTime : negative time value. + * @param SecondValue: specifies the PTP Time update second value. + * @param SubSecondValue: specifies the PTP Time update sub-second value. + * this is a 31 bit value. bit32 correspond to the sign. + * @retval : None + */ +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); + assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); + /* Set the PTP Time Update High Register */ + ETH->PTPTSHUR = SecondValue; + + /* Set the PTP Time Update Low Register with sign */ + ETH->PTPTSLUR = Sign | SubSecondValue; +} + +/** + * @brief Sets the Time Stamp Addend value. + * @param Value: specifies the PTP Time Stamp Addend Register value. + * @retval : None + */ +void ETH_SetPTPTimeStampAddend(uint32_t Value) +{ + /* Set the PTP Time Stamp Addend Register */ + ETH->PTPTSAR = Value; +} + +/** + * @brief Sets the Target Time registers values. + * @param HighValue: specifies the PTP Target Time High Register value. + * @param LowValue: specifies the PTP Target Time Low Register value. + * @retval : None + */ +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) +{ + /* Set the PTP Target Time High Register */ + ETH->PTPTTHR = HighValue; + /* Set the PTP Target Time Low Register */ + ETH->PTPTTLR = LowValue; +} + +/** + * @brief Get the specified ETHERNET PTP register value. + * @param ETH_PTPReg: specifies the ETHERNET PTP register. + * This parameter can be one of the following values: + * @arg ETH_PTPTSCR : Sub-Second Increment Register + * @arg ETH_PTPSSIR : Sub-Second Increment Register + * @arg ETH_PTPTSHR : Time Stamp High Register + * @arg ETH_PTPTSLR : Time Stamp Low Register + * @arg ETH_PTPTSHUR : Time Stamp High Update Register + * @arg ETH_PTPTSLUR : Time Stamp Low Update Register + * @arg ETH_PTPTSAR : Time Stamp Addend Register + * @arg ETH_PTPTTHR : Target Time High Register + * @arg ETH_PTPTTLR : Target Time Low Register + * @retval : The value of ETHERNET PTP Register value. + */ +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg)); + + /* Return the selected register value */ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); +} + +/** + * @brief Initializes the DMA Tx descriptors in chain mode with PTP. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list + * @param TxBuff: Pointer on the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval : None + */ +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + DMAPTPTxDescToSet = DMAPTPTxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab+i; + /* Set Second Address Chained bit and enable PTP */ + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } + /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */ + (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; + (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; + } + /* Store on the last DMAPTPTxDescTab desc status record the first list address */ + (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab; + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list + * @param RxBuff: Pointer on the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval : None + */ +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */ + (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; + (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; + } + /* Store on the last DMAPTPRxDescTab desc status record the first list address */ + (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab; + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Transmits a packet, from application buffer, pointed by ppkt with + * Time Stamp values. + * @param ppkt: pointer to application packet buffer to transmit. + * @param FrameLength: Tx Packet size. + * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values. + * @retval : ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission + */ +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) +{ + uint32_t offset = 0, timeout = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); + } + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + /* Wait for ETH_DMATxDesc_TTSS flag to be set */ + do + { + timeout++; + } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Clear the DMATxDescToSet status register TTSS flag */ + DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; + *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; + *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; + /* Update the ENET DMA current descriptor */ + /* Chained Mode */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr); + if(DMAPTPTxDescToSet->Status != 0) + { + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status); + } + else + { + DMAPTPTxDescToSet++; + } + } + else /* Ring Mode */ + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read: this will + be the first Tx descriptor in this case */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Receives a packet and copies it to memory pointed by ppkt with + * Time Stamp values. + * @param ppkt: pointer to application packet receive buffer. + * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values. + * @retval : ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct + */ +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) +{ + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ENET or CPU */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + } + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; + *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr); + if(DMAPTPRxDescToGet->Status != 0) + { + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status); + } + else + { + DMAPTPRxDescToGet++; + } + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return Frame Length/ERROR */ + return (framelength); +} +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/clock-arch.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/clock-arch.c new file mode 100644 index 00000000..d8225115 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/clock-arch.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.c,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * Implementation of architecture-specific clock functionality + * \author + * Adam Dunkels + */ + +#include "clock-arch.h" +#include "header.h" + +/*---------------------------------------------------------------------------*/ +clock_time_t +clock_time(void) +{ + return (clock_time_t)TimerGet(); +} +/*---------------------------------------------------------------------------*/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/clock-arch.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/clock-arch.h new file mode 100644 index 00000000..aa97f0e7 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/clock-arch.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +typedef int clock_time_t; +#define CLOCK_CONF_SECOND 1000 + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/netdev.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/netdev.c new file mode 100644 index 00000000..3ce42bdf --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/netdev.c @@ -0,0 +1,442 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Author: Adam Dunkels + * + * $Id: netdev.c,v 1.8 2006/06/07 08:39:58 adam Exp $ + */ + + +/*---------------------------------------------------------------------------*/ +#include "uip.h" +#include "uip_arp.h" +#include "header.h" +#include "stm32_eth.h" /* STM32 ethernet library */ +#include /* for memcpy */ + + +/*---------------------------------------------------------------------------*/ +#define NETDEV_DEFAULT_MACADDR0 (0x08) +#define NETDEV_DEFAULT_MACADDR1 (0x00) +#define NETDEV_DEFAULT_MACADDR2 (0x27) +#define NETDEV_DEFAULT_MACADDR3 (0x69) +#define NETDEV_DEFAULT_MACADDR4 (0x5B) +#define NETDEV_DEFAULT_MACADDR5 (0x45) + + +/*---------------------------------------------------------------------------*/ +static void netdev_TxDscrInit(void); +static void netdev_RxDscrInit(void); + +/*---------------------------------------------------------------------------*/ +typedef union _TranDesc0_t +{ + uint32_t Data; + struct { + uint32_t DB : 1; + uint32_t UF : 1; + uint32_t ED : 1; + uint32_t CC : 4; + uint32_t VF : 1; + uint32_t EC : 1; + uint32_t LC : 1; + uint32_t NC : 1; + uint32_t LSC : 1; + uint32_t IPE : 1; + uint32_t FF : 1; + uint32_t JT : 1; + uint32_t ES : 1; + uint32_t IHE : 1; + uint32_t : 3; + uint32_t TCH : 1; + uint32_t TER : 1; + uint32_t CIC : 2; + uint32_t : 2; + uint32_t DP : 1; + uint32_t DC : 1; + uint32_t FS : 1; + uint32_t LSEG : 1; + uint32_t IC : 1; + uint32_t OWN : 1; + }; +} TranDesc0_t, * pTranDesc0_t; + +typedef union _TranDesc1_t +{ + uint32_t Data; + struct { + uint32_t TBS1 :13; + uint32_t : 3; + uint32_t TBS2 :12; + uint32_t : 3; + }; +} TranDesc1_t, * pTranDesc1_t; + +typedef union _RecDesc0_t +{ + uint32_t Data; + struct { + uint32_t RMAM_PCE : 1; + uint32_t CE : 1; + uint32_t DE : 1; + uint32_t RE : 1; + uint32_t RWT : 1; + uint32_t FT : 1; + uint32_t LC : 1; + uint32_t IPHCE : 1; + uint32_t LS : 1; + uint32_t FS : 1; + uint32_t VLAN : 1; + uint32_t OE : 1; + uint32_t LE : 1; + uint32_t SAF : 1; + uint32_t DERR : 1; + uint32_t ES : 1; + uint32_t FL :14; + uint32_t AFM : 1; + uint32_t OWN : 1; + }; +} RecDesc0_t, * pRecDesc0_t; + +typedef union _recDesc1_t +{ + uint32_t Data; + struct { + uint32_t RBS1 :13; + uint32_t : 1; + uint32_t RCH : 1; + uint32_t RER : 1; + uint32_t RBS2 :14; + uint32_t DIC : 1; + }; +} RecDesc1_t, * pRecDesc1_t; + +typedef union _EnetDmaDesc_t +{ + uint32_t Data[4]; + // Rx DMA descriptor + struct + { + RecDesc0_t RxDesc0; + RecDesc1_t RxDesc1; + uint32_t * pBuffer; + union + { + uint32_t * pBuffer2; + union _EnetDmaDesc_t * pEnetDmaNextDesc; + }; + } Rx; + // Tx DMA descriptor + struct + { + TranDesc0_t TxDesc0; + TranDesc1_t TxDesc1; + uint32_t * pBuffer1; + union + { + uint32_t * pBuffer2; + union _EnetDmaDesc_t * pEnetDmaNextDesc; + }; + } Tx; +} EnetDmaDesc_t, * pEnetDmaDesc_t; + + +/*---------------------------------------------------------------------------*/ +uint8_t RxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4))); +uint8_t TxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4))); + +EnetDmaDesc_t EnetDmaRx __attribute__((aligned (128))); +EnetDmaDesc_t EnetDmaTx __attribute__ ((aligned (128))); + + +/*---------------------------------------------------------------------------*/ +void netdev_init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + ETH_InitTypeDef ETH_InitStructure; + + /* Enable ETHERNET clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx | + RCC_AHB1Periph_ETH_MAC_Rx | RCC_AHB1Periph_ETH_MAC_PTP, ENABLE); + + + /* Enable GPIOs clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | + RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG, ENABLE); + + /* Enable SYSCFG clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + /*Select RMII Interface*/ + SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII); + + /* ETHERNET pins configuration */ + /* PA + ETH_RMII_REF_CLK: PA1 + ETH_RMII_MDIO: PA2 + ETH_RMII_MDINT: PA3 + ETH_RMII_CRS_DV: PA7 + */ + + /* Configure PA1, PA2, PA3 and PA7*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_7; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Connect PA1, PA2, PA3 and PA7 to ethernet module*/ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH); + + /* PB + ETH_RMII_TX_EN: PG11 + */ + + /* Configure PG11*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* Connect PG11 to ethernet module*/ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH); + + /* PC + ETH_RMII_MDC: PC1 + ETH_RMII_RXD0: PC4 + ETH_RMII_RXD1: PC5 + */ + + /* Configure PC1, PC4 and PC5*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Connect PC1, PC4 and PC5 to ethernet module*/ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH); + + /* PG + ETH_RMII_TXD0: PG13 + ETH_RMII_TXD1: PG14 + */ + + /* Configure PG13 and PG14*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* Connect PG13 and PG14 to ethernet module*/ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH); + + /* Reset ETHERNET on AHB Bus */ + ETH_DeInit(); + + /* Software reset */ + ETH_SoftwareReset(); + + /* Wait for software reset */ + while(ETH_GetSoftwareResetStatus()==SET); + + /* ETHERNET Configuration ------------------------------------------------------*/ + /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */ + ETH_StructInit(Ð_InitStructure); + + /* Fill ETH_InitStructure parametrs */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable ; + ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; + ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable; + ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; + ETH_InitStructure.ETH_Speed = ETH_Speed_100M; + + unsigned int PhyAddr; + union { + uint32_t HI_LO; + struct + { + uint16_t LO; + uint16_t HI; + }; + } PHYID; + for(PhyAddr = 0; 32 > PhyAddr; PhyAddr++) + { + // datasheet for the ks8721bl ethernet controller (http://www.micrel.com/_PDF/Ethernet/datasheets/ks8721bl-sl.pdf) + // page 20 --> PHY Identifier 1 and 2 + PHYID.HI = ETH_ReadPHYRegister(PhyAddr,2); // 0x0022 + PHYID.LO = ETH_ReadPHYRegister(PhyAddr,3); // 0x1619 + if ((0x00221619 == PHYID.HI_LO) || (0x0007C0F1 == PHYID.HI_LO)) + break; + } + /* Configure Ethernet */ + ETH_Init(Ð_InitStructure, PhyAddr); + + netdev_TxDscrInit(); + netdev_RxDscrInit(); + ETH_Start(); +} + + +/*---------------------------------------------------------------------------*/ +void netdev_init_mac(void) +{ + struct uip_eth_addr macAddress; + + /* set the default MAC address */ + macAddress.addr[0] = NETDEV_DEFAULT_MACADDR0; + macAddress.addr[1] = NETDEV_DEFAULT_MACADDR1; + macAddress.addr[2] = NETDEV_DEFAULT_MACADDR2; + macAddress.addr[3] = NETDEV_DEFAULT_MACADDR3; + macAddress.addr[4] = NETDEV_DEFAULT_MACADDR4; + macAddress.addr[5] = NETDEV_DEFAULT_MACADDR5; + uip_setethaddr(macAddress); +} + + +/*---------------------------------------------------------------------------*/ +unsigned int netdev_read(void) +{ + uint32_t size; + /*check for validity*/ + if(0 == EnetDmaRx.Rx.RxDesc0.OWN) + { + /*Get the size of the packet*/ + size = EnetDmaRx.Rx.RxDesc0.FL; // CRC + memcpy(uip_buf, RxBuff, size); //string.h library*/ + } + else + { + return 0; + } + /* Give the buffer back to ENET */ + EnetDmaRx.Rx.RxDesc0.OWN = 1; + /* Start the receive operation */ + ETH->DMARPDR = 1; + /* Return no error */ + return size; +} + + +/*---------------------------------------------------------------------------*/ +void netdev_send(void) +{ + while(EnetDmaTx.Tx.TxDesc0.OWN); + + /* Copy the application buffer to the driver buffer + Using this MEMCOPY_L2L_BY4 makes the copy routine faster + than memcpy */ + memcpy(TxBuff, uip_buf, uip_len); + + /* Assign ENET address to Temp Tx Array */ + EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff; + + /* Setting the Frame Length*/ + EnetDmaTx.Tx.TxDesc0.Data = 0; + EnetDmaTx.Tx.TxDesc0.TCH = 1; + EnetDmaTx.Tx.TxDesc0.LSEG = 1; + EnetDmaTx.Tx.TxDesc0.FS = 1; + EnetDmaTx.Tx.TxDesc0.DC = 0; + EnetDmaTx.Tx.TxDesc0.DP = 0; + + EnetDmaTx.Tx.TxDesc1.Data = 0; + EnetDmaTx.Tx.TxDesc1.TBS1 = (uip_len&0xFFF); + + /* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/ + EnetDmaTx.Tx.TxDesc0.OWN = 1; + + /* Start the transmit operation */ + ETH->DMATPDR = 1; +} + + +/*---------------------------------------------------------------------------*/ +static void netdev_RxDscrInit(void) +{ + /* Initialization */ + /* Assign temp Rx array to the ENET buffer */ + EnetDmaRx.Rx.pBuffer = (uint32_t *)RxBuff; + + /* Initialize RX ENET Status and control */ + EnetDmaRx.Rx.RxDesc0.Data = 0; + + /* Initialize the next descriptor- In our case its single descriptor */ + EnetDmaRx.Rx.pEnetDmaNextDesc = &EnetDmaRx; + + EnetDmaRx.Rx.RxDesc1.Data = 0; + EnetDmaRx.Rx.RxDesc1.RER = 0; // end of ring + EnetDmaRx.Rx.RxDesc1.RCH = 1; // end of ring + + /* Set the max packet size */ + EnetDmaRx.Rx.RxDesc1.RBS1 = UIP_CONF_BUFFER_SIZE; + + /* Setting the VALID bit */ + EnetDmaRx.Rx.RxDesc0.OWN = 1; + /* Setting the RX NEXT Descriptor Register inside the ENET */ + ETH->DMARDLAR = (uint32_t)&EnetDmaRx; +} + + +/*---------------------------------------------------------------------------*/ +static void netdev_TxDscrInit(void) +{ + /* ENET Start Address */ + EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff; + + /* Next Descriptor Address */ + EnetDmaTx.Tx.pEnetDmaNextDesc = &EnetDmaTx; + + /* Initialize ENET status and control */ + EnetDmaTx.Tx.TxDesc0.TCH = 1; + EnetDmaTx.Tx.TxDesc0.Data = 0; + EnetDmaTx.Tx.TxDesc1.Data = 0; + /* Tx next set to Tx descriptor base */ + ETH->DMATDLAR = (uint32_t)&EnetDmaTx; + +} diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/netdev.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/netdev.h new file mode 100644 index 00000000..4ea59ce5 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/netdev.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Adam Dunkels. + * 4. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: netdev.h,v 1.1 2002/01/10 06:22:56 adam Exp $ + * + */ + +#ifndef __NETDEV_H__ +#define __NETDEV_H__ + +void netdev_init(void); +void netdev_init_mac(void); +unsigned int netdev_read(void); +void netdev_send(void); + +#endif /* __NETDEV_H__ */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/uip-conf.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/uip-conf.h new file mode 100644 index 00000000..fd9ba0dd --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/lib/uip/uip-conf.h @@ -0,0 +1,151 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef unsigned char u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef unsigned short u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 1 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 1 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1600 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 0 + +/* Here we include the header file for the application(s) we use in + our project. */ +#include "boot.h" +#include "net.h" + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/main.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/main.c index 9658bea4..c0b2e668 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/main.c +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/main.c @@ -53,6 +53,8 @@ void main(void) { /* initialize the microcontroller */ Init(); + /* initialize the network application */ + NetInit(); /* initialize the bootloader interface */ BootComInit(); @@ -61,6 +63,8 @@ void main(void) { /* toggle LED with a fixed frequency */ LedToggle(); + /* run the network task */ + NetTask(); /* check for bootloader activation request */ BootComCheckActivationRequest(); } diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/memory.x b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/memory.x index e8d2c90f..63d40407 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/memory.x +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/memory.x @@ -1,7 +1,7 @@ MEMORY { UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0 - FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 0x00100000-0x8000 + FLASH (rx) : ORIGIN = 0x0800C000, LENGTH = 0x00100000-0xC000 DATA_SRAM (wx) : ORIGIN = 0x10000000, LENGTH = 0x00010000 SYSTEM (wx) : ORIGIN = 0x1fff0000, LENGTH = 0x00007a10 OPTION (wx) : ORIGIN = 0x1fffc000, LENGTH = 0x00000008 @@ -28,7 +28,7 @@ MEMORY SECTIONS { - __FLASH_segment_start__ = 0x08008000; + __FLASH_segment_start__ = 0x0800C000; __FLASH_segment_end__ = 0x08100000; __DATA_SRAM_segment_start__ = 0x10000000; __DATA_SRAM_segment_end__ = 0x10010000; diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/net.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/net.c new file mode 100644 index 00000000..39728207 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/net.c @@ -0,0 +1,211 @@ +/************************************************************************************//** +* \file Demo\ARMCM3_LM3S_EK_LM3S6965_IAR\Prog\net.c +* \brief Network application for the uIP TCP/IP stack. +* \ingroup Prog_ARMCM3_LM3S_EK_LM3S6965_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2014 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ +#include "netdev.h" +#include "uip.h" +#include "uip_arp.h" + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Delta time for the uIP periodic timer. */ +#define NET_UIP_PERIODIC_TIMER_MS (500) +/** \brief Delta time for the uIP ARP timer. */ +#define NET_UIP_ARP_TIMER_MS (10000) +/** \brief Macro for accessing the Ethernet header information in the buffer */ +#define NET_UIP_HEADER_BUF ((struct uip_eth_hdr *)&uip_buf[0]) + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Holds the time out value of the uIP periodic timer. */ +static unsigned long periodicTimerTimeOut; +/** \brief Holds the time out value of the uIP ARP timer. */ +static unsigned long ARPTimerTimeOut; + + +/************************************************************************************//** +** \brief Initializes the TCP/IP network communication interface. +** \return none. +** +****************************************************************************************/ +void NetInit(void) +{ + uip_ipaddr_t ipaddr; + + /* initialize the network device */ + netdev_init(); + /* initialize the timer variables */ + periodicTimerTimeOut = TimerGet() + NET_UIP_PERIODIC_TIMER_MS; + ARPTimerTimeOut = TimerGet() + NET_UIP_ARP_TIMER_MS; + /* initialize the uIP TCP/IP stack. */ + uip_init(); + /* set the IP address */ + uip_ipaddr(ipaddr, BOOT_COM_NET_IPADDR0, BOOT_COM_NET_IPADDR1, BOOT_COM_NET_IPADDR2, + BOOT_COM_NET_IPADDR3); + uip_sethostaddr(ipaddr); + /* set the network mask */ + uip_ipaddr(ipaddr, BOOT_COM_NET_NETMASK0, BOOT_COM_NET_NETMASK1, BOOT_COM_NET_NETMASK2, + BOOT_COM_NET_NETMASK3); + uip_setnetmask(ipaddr); + /* set the gateway address */ + uip_ipaddr(ipaddr, BOOT_COM_NET_GATEWAY0, BOOT_COM_NET_GATEWAY1, BOOT_COM_NET_GATEWAY2, + BOOT_COM_NET_GATEWAY3); + uip_setdraddr(ipaddr); + /* start listening on the configured port for XCP transfers on TCP/IP */ + uip_listen(HTONS(BOOT_COM_NET_PORT)); + /* initialize the MAC and set the MAC address */ + netdev_init_mac(); +} /*** end of NetInit ***/ + + +/************************************************************************************//** +** \brief The uIP network application that detects the XCP connect command on the +** port used by the bootloader. This indicates that the bootloader should +** be activated. +** \return none. +** +****************************************************************************************/ +void NetApp(void) +{ + unsigned char *newDataPtr; + + if (uip_connected()) + { + return; + } + + if (uip_newdata()) + { + /* a new XCP command was received. check if this is the connect command and in this + * case activate the bootloader. with XCP on TCP/IP the first 4 bytes contain a + * counter value in which we are not really interested. + */ + newDataPtr = uip_appdata; + newDataPtr += 4; + /* check if this was an XCP CONNECT command */ + if ((newDataPtr[0] == 0xff) && (newDataPtr[1] == 0x00)) + { + /* connection request received so start the bootloader */ + BootActivate(); + } + } +} /*** end of NetApp ***/ + + +/************************************************************************************//** +** \brief Runs the TCP/IP server task. +** \return none. +** +****************************************************************************************/ +void NetTask(void) +{ + unsigned long connection; + unsigned long packetLen; + + /* check for an RX packet and read it. */ + packetLen = netdev_read(); + if(packetLen > 0) + { + /* set uip_len for uIP stack usage */ + uip_len = (unsigned short)packetLen; + + /* process incoming IP packets here. */ + if(NET_UIP_HEADER_BUF->type == htons(UIP_ETHTYPE_IP)) + { + uip_arp_ipin(); + uip_input(); + /* if the above function invocation resulted in data that + * should be sent out on the network, the global variable + * uip_len is set to a value > 0. + */ + if(uip_len > 0) + { + uip_arp_out(); + netdev_send(); + uip_len = 0; + } + } + /* process incoming ARP packets here. */ + else if(NET_UIP_HEADER_BUF->type == htons(UIP_ETHTYPE_ARP)) + { + uip_arp_arpin(); + + /* if the above function invocation resulted in data that + * should be sent out on the network, the global variable + * uip_len is set to a value > 0. + */ + if(uip_len > 0) + { + netdev_send(); + uip_len = 0; + } + } + } + + /* process TCP/IP Periodic Timer here. */ + if (TimerGet() >= periodicTimerTimeOut) + { + periodicTimerTimeOut += NET_UIP_PERIODIC_TIMER_MS; + for (connection = 0; connection < UIP_CONNS; connection++) + { + uip_periodic(connection); + /* If the above function invocation resulted in data that + * should be sent out on the network, the global variable + * uip_len is set to a value > 0. + */ + if(uip_len > 0) + { + uip_arp_out(); + netdev_send(); + uip_len = 0; + } + } + } + + /* process ARP Timer here. */ + if (TimerGet() >= ARPTimerTimeOut) + { + ARPTimerTimeOut += NET_UIP_ARP_TIMER_MS; + uip_arp_timer(); + } +} /*** end of NetServerTask ***/ + + +/*********************************** end of net.c **************************************/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/net.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/net.h new file mode 100644 index 00000000..538e6664 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_Crossworks/Prog/net.h @@ -0,0 +1,66 @@ +/************************************************************************************//** +* \file Demo\ARMCM3_LM3S_EK_LM3S6965_IAR\Prog\net.h +* \brief Network application for the uIP TCP/IP stack. +* \ingroup Prog_ARMCM3_LM3S_EK_LM3S6965_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2014 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef NET_H +#define NET_H + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +#ifndef UIP_APPCALL +#define UIP_APPCALL NetApp +#endif /* UIP_APPCALL */ + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Define the uip_tcp_appstate_t datatype. This is the state of our tcp/ip + * application, and the memory required for this state is allocated together + * with each TCP connection. One application state for each TCP connection. + */ +typedef struct net_state +{ + unsigned char unused; +} uip_tcp_appstate_t; + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void NetInit(void); +void NetApp(void); +void NetTask(void); + + +#endif /* NET_H */ +/*********************************** end of net.h **************************************/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/bin/openbtl_olimex_stm32e407.elf b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/bin/openbtl_olimex_stm32e407.elf index 29a4d198..d6c34888 100644 Binary files a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/bin/openbtl_olimex_stm32e407.elf and b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/bin/openbtl_olimex_stm32e407.elf differ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/bin/openbtl_olimex_stm32e407.map b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/bin/openbtl_olimex_stm32e407.map index 810b0e20..40e700a0 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/bin/openbtl_olimex_stm32e407.map +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/bin/openbtl_olimex_stm32e407.map @@ -7,43 +7,45 @@ start address 0x08000000 Program Header: LOAD off 0x00008000 vaddr 0x08000000 paddr 0x08000000 align 2**15 - filesz 0x00005e50 memsz 0x00005e50 flags r-x - LOAD off 0x00010000 vaddr 0x20000000 paddr 0x08005e50 align 2**15 - filesz 0x00000020 memsz 0x0000183c flags rw- + filesz 0x00007f98 memsz 0x00007f98 flags r-x + LOAD off 0x00010000 vaddr 0x20000000 paddr 0x08007f98 align 2**15 + filesz 0x00000020 memsz 0x00000020 flags rw- + LOAD off 0x00010080 vaddr 0x20000080 paddr 0x08008080 align 2**15 + filesz 0x00000000 memsz 0x00002ce4 flags rw- private flags = 5000202: [Version5 EABI] [soft-float ABI] [has entry point] Sections: Idx Name Size VMA LMA File off Algn - 0 .text 00005e50 08000000 08000000 00008000 2**2 + 0 .text 00007f98 08000000 08000000 00008000 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE - 1 .data 00000020 20000000 08005e50 00010000 2**2 + 1 .data 00000020 20000000 08007f98 00010000 2**2 CONTENTS, ALLOC, LOAD, DATA - 2 .bss 0000181c 20000020 08005e70 00010020 2**3 + 2 .bss 00002ce4 20000080 08008080 00010080 2**7 ALLOC - 3 .debug_info 0000e1fa 00000000 00000000 00010020 2**0 + 3 .debug_info 00012d6c 00000000 00000000 00010020 2**0 CONTENTS, READONLY, DEBUGGING - 4 .debug_abbrev 000028bd 00000000 00000000 0001e21a 2**0 + 4 .debug_abbrev 00003711 00000000 00000000 00022d8c 2**0 CONTENTS, READONLY, DEBUGGING - 5 .debug_loc 00009eca 00000000 00000000 00020ad7 2**0 + 5 .debug_loc 0000b735 00000000 00000000 0002649d 2**0 CONTENTS, READONLY, DEBUGGING - 6 .debug_aranges 00000c10 00000000 00000000 0002a9a1 2**0 + 6 .debug_aranges 000010d8 00000000 00000000 00031bd2 2**0 CONTENTS, READONLY, DEBUGGING - 7 .debug_ranges 00000ba0 00000000 00000000 0002b5b1 2**0 + 7 .debug_ranges 00001008 00000000 00000000 00032caa 2**0 CONTENTS, READONLY, DEBUGGING - 8 .debug_line 000044b6 00000000 00000000 0002c151 2**0 + 8 .debug_line 00005d54 00000000 00000000 00033cb2 2**0 CONTENTS, READONLY, DEBUGGING - 9 .debug_str 00003a4f 00000000 00000000 00030607 2**0 + 9 .debug_str 0000553c 00000000 00000000 00039a06 2**0 CONTENTS, READONLY, DEBUGGING - 10 .comment 00000030 00000000 00000000 00034056 2**0 + 10 .comment 00000030 00000000 00000000 0003ef42 2**0 CONTENTS, READONLY - 11 .ARM.attributes 00000033 00000000 00000000 00034086 2**0 + 11 .ARM.attributes 00000033 00000000 00000000 0003ef72 2**0 CONTENTS, READONLY - 12 .debug_frame 00001f58 00000000 00000000 000340bc 2**2 + 12 .debug_frame 00002ab4 00000000 00000000 0003efa8 2**2 CONTENTS, READONLY, DEBUGGING SYMBOL TABLE: 08000000 l d .text 00000000 .text 20000000 l d .data 00000000 .data -20000020 l d .bss 00000000 .bss +20000080 l d .bss 00000000 .bss 00000000 l d .debug_info 00000000 .debug_info 00000000 l d .debug_abbrev 00000000 .debug_abbrev 00000000 l d .debug_loc 00000000 .debug_loc @@ -57,255 +59,335 @@ SYMBOL TABLE: 00000000 l df *ABS* 00000000 vectors.c 00000000 l df *ABS* 00000000 cstart.c 080001d4 l F .text 00000000 zero_loop2 -080053ea l F .text 00000000 zero_loop +08007482 l F .text 00000000 zero_loop 00000000 l df *ABS* 00000000 hooks.c -080054b0 l O .text 00000020 firmwareFilename -20000020 l O .bss 00000228 logfile +080075e8 l O .text 00000020 firmwareFilename +20000080 l O .bss 00000228 logfile 00000000 l df *ABS* 00000000 main.c 00000000 l df *ABS* 00000000 mmc.c 08000400 l F .text 0000004e CmdResp2Error 08000450 l F .text 00000130 CmdResp1Error 08000580 l F .text 0000024e SDEnWideBus -20000248 l O .bss 00000001 TransferError +200002a8 l O .bss 00000001 TransferError 20000000 l O .data 00000004 DMAEndOfTransfer -2000024c l O .bss 00000018 SDIO_DataInitStructure -20000264 l O .bss 00000010 CSD_Tab -20000274 l O .bss 00000004 CardType -20000278 l O .bss 00000010 CID_Tab -20000288 l O .bss 00000004 TransferEnd -2000028c l O .bss 00000018 SDIO_InitStructure -200002a4 l O .bss 00000004 RCA -200002a8 l O .bss 00000058 SDCardInfo -20000300 l O .bss 00000014 SDIO_CmdInitStructure +200002ac l O .bss 00000018 SDIO_DataInitStructure +200002c4 l O .bss 00000010 CSD_Tab +200002d4 l O .bss 00000004 CardType +200002d8 l O .bss 00000010 CID_Tab +200002e8 l O .bss 00000004 TransferEnd +200002ec l O .bss 00000018 SDIO_InitStructure +20000304 l O .bss 00000004 RCA +20000308 l O .bss 00000058 SDCardInfo +20000360 l O .bss 00000014 SDIO_CmdInitStructure 20000004 l O .data 00000001 Stat -20000314 l O .bss 00000004 StopCondition +20000374 l O .bss 00000004 StopCondition +00000000 l df *ABS* 00000000 stm32_eth.c +00000000 l df *ABS* 00000000 netdev.c 00000000 l df *ABS* 00000000 stm32f4xx_flash.c 00000000 l df *ABS* 00000000 stm32f4xx_gpio.c 00000000 l df *ABS* 00000000 stm32f4xx_rcc.c 20000008 l O .data 00000010 APBAHBPrescTable 00000000 l df *ABS* 00000000 stm32f4xx_sdio.c +00000000 l df *ABS* 00000000 stm32f4xx_syscfg.c 00000000 l df *ABS* 00000000 stm32f4xx_usart.c 00000000 l df *ABS* 00000000 system_stm32f4xx.c 00000000 l df *ABS* 00000000 ff.c -08001da8 l F .text 00000012 mem_cpy -08001dbc l F .text 0000001e ld_clust -08001ddc l F .text 0000001e sum_sfn -08001dfc l F .text 00000096 check_fs -08001e94 l F .text 00000076 sync_window -08001f0c l F .text 00000032 move_window -08001f40 l F .text 00000038 validate -08001f78 l F .text 00000394 chk_mounted -0800230c l F .text 0000012c get_fileinfo -08002438 l F .text 000000bc sync_fs -080025f8 l F .text 00000098 dir_sdi -080027a0 l F .text 000000cc create_chain -0800286c l F .text 0000012a dir_next -08002998 l F .text 000001a2 dir_find -08002b3c l F .text 00000332 follow_path -08002e70 l F .text 00000130 dir_read -08002fa0 l F .text 00000058 dir_remove -08002ff8 l F .text 0000006e remove_chain -08003100 l F .text 00000236 dir_register -20000318 l O .bss 00000200 LfnBuf -20000518 l O .bss 00000002 Fsid -080054f4 l O .text 00000080 ExCvt -08005574 l O .text 0000000d LfnOfs -2000051c l O .bss 00000004 FatFs +0800261c l F .text 00000012 mem_cpy +08002630 l F .text 0000001e ld_clust +08002650 l F .text 0000001e sum_sfn +08002670 l F .text 00000096 check_fs +08002708 l F .text 00000076 sync_window +08002780 l F .text 00000032 move_window +080027b4 l F .text 00000038 validate +080027ec l F .text 00000394 chk_mounted +08002b80 l F .text 0000012c get_fileinfo +08002cac l F .text 000000bc sync_fs +08002e6c l F .text 00000098 dir_sdi +08003014 l F .text 000000cc create_chain +080030e0 l F .text 0000012a dir_next +0800320c l F .text 000001a2 dir_find +080033b0 l F .text 00000332 follow_path +080036e4 l F .text 00000130 dir_read +08003814 l F .text 00000058 dir_remove +0800386c l F .text 0000006e remove_chain +08003974 l F .text 00000236 dir_register +20000378 l O .bss 00000200 LfnBuf +20000578 l O .bss 00000002 Fsid +08007640 l O .text 00000080 ExCvt +080076c0 l O .text 0000000d LfnOfs +2000057c l O .bss 00000004 FatFs 00000000 l df *ABS* 00000000 unicode.c -08005584 l O .text 000001e0 tbl_lower.4259 -08005764 l O .text 00000100 Tbl -08005864 l O .text 000001e0 tbl_upper.4260 +080076d0 l O .text 000001e0 tbl_lower.4259 +080078b0 l O .text 00000100 Tbl +080079b0 l O .text 000001e0 tbl_upper.4260 +00000000 l df *ABS* 00000000 uip.c +08004550 l F .text 0000004c chksum +0800459c l F .text 00000042 upper_layer_chksum +08004660 l F .text 00000030 uip_add_rcv_nxt +20000580 l O .bss 00000002 tmp16 +20000582 l O .bss 00000002 ipid +20000584 l O .bss 00000004 iss +20000588 l O .bss 00000002 lastport +20000594 l O .bss 00000001 c +20000595 l O .bss 00000001 opt +00000000 l df *ABS* 00000000 uip_arp.c +08005680 l F .text 00000116 uip_arp_update +20000596 l O .bss 00000001 i +20000597 l O .bss 00000001 tmpage +20000598 l O .bss 00000060 arp_table +08007b90 l O .text 00000006 broadcast_ethaddr +200005f8 l O .bss 00000001 c +200005f9 l O .bss 00000001 arptime +200005fc l O .bss 00000004 ipaddr 00000000 l df *ABS* 00000000 boot.c 00000000 l df *ABS* 00000000 com.c -20000520 l O .bss 00000001 comEntryStateConnect +20000600 l O .bss 00000001 comEntryStateConnect 20000018 l O .data 00000001 comActiveInterface -20000524 l O .bss 00000040 xcpCtoReqPacket.4403 +20000604 l O .bss 00000040 xcpCtoReqPacket.4419 +00000000 l df *ABS* 00000000 net.c +20000644 l O .bss 00000004 ARPTimerTimeOut +20000648 l O .bss 00000004 periodicTimerTimeOut 00000000 l df *ABS* 00000000 xcp.c -08003e40 l F .text 00000016 XcpSetCtoError -08005a44 l O .text 00000008 xcpStationId -20000564 l O .bss 0000004c xcpInfo +08005ec4 l F .text 00000016 XcpSetCtoError +08007b98 l O .text 00000008 xcpStationId +2000064c l O .bss 0000004c xcpInfo 00000000 l df *ABS* 00000000 backdoor.c -200005b0 l O .bss 00000001 backdoorOpen -200005b4 l O .bss 00000004 backdoorOpenTime +20000698 l O .bss 00000001 backdoorOpen +2000069c l O .bss 00000004 backdoorOpenTime 00000000 l df *ABS* 00000000 cop.c 00000000 l df *ABS* 00000000 file.c -08004294 l F .text 0000002e FileLibByteNibbleToChar -080042c4 l F .text 00000020 FileLibByteToHexString -080042e4 l F .text 00000046 FileLibLongToIntString -0800432c l F .text 00000066 FileLibHexStringToByte -200005b8 l O .bss 00000040 loggingStr -200005f8 l O .bss 00000001 firmwareUpdateState -200005fc l O .bss 00000008 eraseInfo -20000604 l O .bss 00000458 fatFsObjects -20000a5c l O .bss 00000184 lineParseObject +0800631c l F .text 0000002e FileLibByteNibbleToChar +0800634c l F .text 00000020 FileLibByteToHexString +0800636c l F .text 00000046 FileLibLongToIntString +080063b4 l F .text 00000066 FileLibHexStringToByte +200006a0 l O .bss 00000040 loggingStr +200006e0 l O .bss 00000001 firmwareUpdateState +200006e4 l O .bss 00000008 eraseInfo +200006ec l O .bss 00000458 fatFsObjects +20000b44 l O .bss 00000184 lineParseObject 00000000 l df *ABS* 00000000 assert.c -20000be0 l O .bss 00000004 assert_failure_file -20000be4 l O .bss 00000004 assert_failure_line +20000cc8 l O .bss 00000004 assert_failure_file +20000ccc l O .bss 00000004 assert_failure_line 00000000 l df *ABS* 00000000 can.c -08005c30 l O .text 00000024 canTiming +08007d84 l O .text 00000024 canTiming 00000000 l df *ABS* 00000000 cpu.c 00000000 l df *ABS* 00000000 flash.c -08004d98 l F .text 00000044 FlashGetSector -08004ddc l F .text 00000078 FlashWriteBlock -08004e54 l F .text 00000062 FlashSwitchBlock -08004eb8 l F .text 00000084 FlashAddToBlock -08005c54 l O .text 00000030 flashSectorNumToMask -08005c84 l O .text 00000078 flashLayout -20000be8 l O .bss 00000204 bootBlockInfo -20000dec l O .bss 00000204 blockInfo +08006e24 l F .text 00000044 FlashGetSector +08006e68 l F .text 00000078 FlashWriteBlock +08006ee0 l F .text 00000062 FlashSwitchBlock +08006f44 l F .text 00000084 FlashAddToBlock +08007da8 l O .text 00000030 flashSectorNumToMask +08007dd8 l O .text 0000006c flashLayout +20000cd0 l O .bss 00000204 bootBlockInfo +20000ed4 l O .bss 00000204 blockInfo 00000000 l df *ABS* 00000000 uart.c -08005140 l F .text 00000042 UartTransmitByte -08005184 l F .text 0000002c UartReceiveByte -20000ff0 l O .bss 00000041 xcpCtoReqPacket.7782 -20001034 l O .bss 00000001 xcpCtoRxLength.7783 -20001035 l O .bss 00000001 xcpCtoRxInProgress.7784 +080071d8 l F .text 00000042 UartTransmitByte +0800721c l F .text 0000002c UartReceiveByte +200010d8 l O .bss 00000041 xcpCtoReqPacket.7784 +2000111c l O .bss 00000001 xcpCtoRxLength.7785 +2000111d l O .bss 00000001 xcpCtoRxInProgress.7786 00000000 l df *ABS* 00000000 nvm.c 00000000 l df *ABS* 00000000 timer.c -20001038 l O .bss 00000004 millisecond_counter +20001120 l O .bss 00000004 millisecond_counter 00000000 l df *ABS* 00000000 memcpy-stub.c +00000000 l df *ABS* 00000000 memset.c 00000000 l df *ABS* 00000000 ctype_.c 00000000 l df *ABS* 00000000 00000800 l *ABS* 00000000 __STACKSIZE__ -08003d10 g F .text 00000044 ComInit -08004f58 g F .text 00000050 FlashWrite -08003bb0 g F .text 0000004e f_gets -08001678 g F .text 0000002c FLASH_Unlock -08004a90 g F .text 0000001c AssertFailure -0800250c g F .text 000000ea get_fat -08004cbc g F .text 00000088 CanReceivePacket -080053a8 g F .text 00000058 reset_handler -0800189c g F .text 00000028 GPIO_PinAFConfig -0800535c g F .text 00000022 TimerUpdate -08003e88 g F .text 00000010 XcpPacketTransmitted -08003d54 g F .text 00000054 ComTask -08001b64 g F .text 0000000c SDIO_ClearFlag +08005b28 g F .text 0000004c ComInit +08006fe4 g F .text 00000050 FlashWrite +08004424 g F .text 0000004e f_gets +08001ebc g F .text 0000002c FLASH_Unlock +08001b3c g F .text 00000012 ETH_FlushTransmitFIFO +08006b18 g F .text 0000001c AssertFailure +08002d80 g F .text 000000ea get_fat +08006d44 g F .text 00000088 CanReceivePacket +08007440 g F .text 00000058 reset_handler +080020e0 g F .text 00000028 GPIO_PinAFConfig +080073f4 g F .text 00000022 TimerUpdate +08005f0c g F .text 00000010 XcpPacketTransmitted +08001690 g F .text 0000009e ETH_StructInit +08005b74 g F .text 0000007c ComTask +080023cc g F .text 0000000c SDIO_ClearFlag 080014b8 g F .text 00000018 SD_GetStatus -080017c0 g F .text 0000003e FLASH_ProgramWord -08003e28 g F .text 0000000e ComSetConnectEntryState -08001a88 g F .text 0000000c SDIO_SetPowerState -08003cdc g F .text 0000001c BootInit -08004458 g F .text 00000038 FileSrecVerifyChecksum -08004268 g F .text 00000022 BackDoorInit -08001c7c g F .text 0000000c USART_GetFlagStatus -08004290 g F .text 00000002 CopService -08005e50 g .text 00000000 _etext +08002004 g F .text 0000003e FLASH_ProgramWord +08005c78 g F .text 0000000e ComSetConnectEntryState +080022f0 g F .text 0000000c SDIO_SetPowerState +08001808 g F .text 000002be ETH_Init +20001e90 g O .bss 00000002 uip_len +2000058c g O .bss 00000006 uip_ethaddr +080045e0 g F .text 0000007e uip_add32 +08005af4 g F .text 0000001c BootInit +080064e0 g F .text 00000038 FileSrecVerifyChecksum +080062f0 g F .text 00000022 BackDoorInit +08002250 g F .text 00000024 RCC_AHB1PeriphResetCmd +080024f0 g F .text 0000000c USART_GetFlagStatus +08006318 g F .text 00000002 CopService +08007f98 g .text 00000000 _etext 080012a4 g F .text 0000019a SD_WriteBlock -08003cac g F .text 0000002e ff_wtoupper -08005408 g F .text 000000a6 memcpy -08004610 g F .text 00000480 FileTask -0800534c g F .text 0000000e TimerReset +08004520 g F .text 0000002e ff_wtoupper +08001e0c g F .text 00000050 netdev_read +08004728 g F .text 00000f1e uip_process +080071cc g F .text 0000000a FlashGetUserProgBaseAddress +08001678 g F .text 00000018 ETH_DeInit +080074a0 g F .text 000000a6 memcpy +08006698 g F .text 00000480 FileTask +080073e4 g F .text 0000000e TimerReset 080014d0 g F .text 00000038 disk_initialize +20001e94 g O .bss 00000004 uip_sappdata +08001bc0 g F .text 00000226 netdev_init +20001e98 g O .bss 00000004 uip_acc32 +08004690 g F .text 00000024 uip_ipchksum 08000c20 g F .text 000002b6 SD_GetCardInfo -08001b50 g F .text 00000014 SDIO_GetFlagStatus -08001c74 g F .text 00000008 USART_ReceiveData -08003cf8 g F .text 00000018 BootTask +080023b8 g F .text 00000014 SDIO_GetFlagStatus +080024e8 g F .text 00000008 USART_ReceiveData +08005b10 g F .text 00000018 BootTask 0800148c g F .text 0000002c SD_GetState -08005034 g F .text 00000058 FlashWriteChecksum +080070c0 g F .text 00000058 FlashWriteChecksum 08000ed8 g F .text 00000084 SD_EnableWideBusOperation -080019e8 g F .text 00000024 RCC_APB2PeriphClockCmd -08001ad4 g F .text 0000000e SDIO_GetCommandResponse -08003dac g F .text 00000034 ComTransmitPacket -08001800 g F .text 00000090 GPIO_Init +0800222c g F .text 00000024 RCC_APB2PeriphClockCmd +0800233c g F .text 0000000e SDIO_GetCommandResponse +08005bf4 g F .text 0000004a ComTransmitPacket +08002044 g F .text 00000090 GPIO_Init 08001508 g F .text 00000032 disk_status -08004490 g F .text 0000017e FileSrecParseLine -08001c50 g F .text 0000001c USART_Cmd +08006518 g F .text 0000017e FileSrecParseLine +080046f4 g F .text 00000032 uip_listen +080024c4 g F .text 0000001c USART_Cmd +08001e5c g F .text 00000060 netdev_send 0800160c g F .text 00000062 disk_ioctl -080043d4 g F .text 00000036 FileHandleFirmwareUpdateRequest -080019c4 g F .text 00000024 RCC_APB1PeriphClockCmd -08003068 g F .text 00000098 gen_numname +0800645c g F .text 00000036 FileHandleFirmwareUpdateRequest +08002208 g F .text 00000024 RCC_APB1PeriphClockCmd +080038dc g F .text 00000098 gen_numname +20001e9c g O .bss 00000001 uip_flags +20001180 g O .bss 00000010 EnetDmaRx 08000280 g F .text 00000042 FileFirmwareUpdateCompletedHook -08003e74 g F .text 00000012 XcpIsConnected -08003af4 g F .text 000000bc f_unlink -080052f0 g F .text 00000008 NvmInit -08004f3c g F .text 0000001a FlashInit -080016a4 g F .text 00000012 FLASH_Lock -2000103c g .bss 00000000 _ebss -08003c00 g F .text 00000034 f_putc -08003c34 g F .text 0000002c f_puts -08005394 g F .text 00000012 UnusedISR -08001a7c g F .text 0000000c SDIO_ClockCmd -08003da8 g F .text 00000002 ComFree -08001b00 g F .text 00000030 SDIO_DataConfig -080051b0 g F .text 0000003e UartInit -080018c4 g F .text 000000da RCC_GetClocksFreq -08005300 g F .text 00000008 NvmErase -08001b70 g F .text 000000de USART_Init -20000020 g .bss 00000000 _bss -080038fc g F .text 00000014 f_close -080016c4 g F .text 00000054 FLASH_GetStatus -08003e98 g F .text 00000384 XcpPacketReceived -080016b8 g F .text 0000000c FLASH_ClearFlag -08001718 g F .text 00000038 FLASH_WaitForLastOperation -080034d0 g F .text 000001a8 f_read -080050f4 g F .text 0000004c FlashDone +08005ef8 g F .text 00000012 XcpIsConnected +08004368 g F .text 000000bc f_unlink +08001ac8 g F .text 00000026 ETH_MACTransmissionCmd +08007388 g F .text 00000008 NvmInit +08006fc8 g F .text 0000001a FlashInit +08001ee8 g F .text 00000012 FLASH_Lock +20002564 g .bss 00000000 _ebss +08004474 g F .text 00000034 f_putc +080044a8 g F .text 0000002c f_puts +0800742c g F .text 00000012 UnusedISR +080022e4 g F .text 0000000c SDIO_ClockCmd +08005bf0 g F .text 00000002 ComFree +08002368 g F .text 00000030 SDIO_DataConfig +08001b18 g F .text 00000012 ETH_SoftwareReset +080017a0 g F .text 00000068 ETH_WritePHYRegister +08007248 g F .text 0000003e UartInit +08002108 g F .text 000000da RCC_GetClocksFreq +08007398 g F .text 00000008 NvmErase +08001de8 g F .text 00000022 netdev_init_mac +080023e4 g F .text 000000de USART_Init +20000080 g .bss 00000000 _bss +08004170 g F .text 00000014 f_close +08001f08 g F .text 00000054 FLASH_GetStatus +08005f1c g F .text 00000384 XcpPacketReceived +080046b4 g F .text 0000000a uip_tcpchksum +08001efc g F .text 0000000c FLASH_ClearFlag +08001f5c g F .text 00000038 FLASH_WaitForLastOperation +08001b78 g F .text 00000026 ETH_DMAReceptionCmd +08003d44 g F .text 000001a8 f_read +08007180 g F .text 0000004c FlashDone 08000f88 g F .text 00000172 SD_Init 08000188 g F .text 00000064 EntryFromProg +20001ea0 g O .bss 00000004 uip_appdata +20001ea4 g O .bss 00000004 uip_conn +08001b2c g F .text 00000010 ETH_GetSoftwareResetStatus 08000f5c g F .text 0000002c SD_SelectDeselect -08004c14 g F .text 000000a8 CanTransmitPacket -08001aa4 g F .text 00000030 SDIO_SendCommand +08006c9c g F .text 000000a8 CanTransmitPacket +0800230c g F .text 00000030 SDIO_SendCommand +08001730 g F .text 0000006e ETH_ReadPHYRegister +20001ea8 g O .bss 00000068 uip_conns 08001670 g F .text 00000008 get_fattime -08003e58 g F .text 0000001c XcpInit -08004394 g F .text 0000002c FileInit -08001b30 g F .text 0000000e SDIO_ReadData -08004fa8 g F .text 0000008a FlashErase +08005edc g F .text 0000001c XcpInit +0800641c g F .text 0000002c FileInit +08002398 g F .text 0000000e SDIO_ReadData +08005924 g F .text 000001d0 uip_arp_out +08007034 g F .text 0000008a FlashErase +08007548 g F .text 0000009e memset 080002c4 g F .text 00000020 FileFirmwareUpdateErrorHook 08000344 g F .text 000000bc main -08001750 g F .text 0000006e FLASH_EraseSector -08003850 g F .text 000000ac f_sync +08001f94 g F .text 0000006e FLASH_EraseSector +080040c4 g F .text 000000ac f_sync 08001440 g F .text 0000004c SD_SendStatus -0800440c g F .text 0000004c FileSrecGetLineType -08005310 g F .text 00000012 NvmDone -08003338 g F .text 0000002a f_mount -080051f0 g F .text 00000066 UartTransmitPacket -08005308 g F .text 00000008 NvmVerifyChecksum -08004d70 g F .text 0000001e CpuMemCopy -08001ae4 g F .text 0000001a SDIO_GetResponse -08001c88 g F .text 00000120 SystemInit -08002690 g F .text 0000010e put_fat -08003910 g F .text 00000198 f_lseek -08003e04 g F .text 00000024 ComGetActiveInterfaceMaxTxLen -08005258 g F .text 00000098 UartReceivePacket +08006494 g F .text 0000004c FileSrecGetLineType +080073a8 g F .text 00000012 NvmDone +08003bac g F .text 0000002a f_mount +08007288 g F .text 00000066 UartTransmitPacket +080073a0 g F .text 00000008 NvmVerifyChecksum +08006dfc g F .text 0000001e CpuMemCopy +0800234c g F .text 0000001a SDIO_GetResponse +080024fc g F .text 00000120 SystemInit +08002f04 g F .text 0000010e put_fat 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-2000183c g .bss 00000000 _estack -08001c6c g F .text 00000008 USART_SendData -0800508c g F .text 00000068 FlashVerifyChecksum +08006b34 g F .text 00000168 CanInit +08007390 g F .text 00000008 NvmWrite +08006dcc g F .text 00000030 CpuStartUserProgram +08002d68 g F .text 00000016 clust2sect +20002d64 g .bss 00000000 _estack +080024e0 g F .text 00000008 USART_SendData +08007118 g F .text 00000068 FlashVerifyChecksum +08005d04 g F .text 00000044 NetTransmitPacket 20000020 g .data 00000000 _edata -080043c0 g F .text 00000014 FileIsIdle -08003678 g F .text 000001d8 f_write +08006448 g F .text 00000014 FileIsIdle +08005648 g F .text 0000000a htons +08003eec g F .text 000001d8 f_write 08000000 g O .text 00000188 _vectab -08003364 g F .text 0000016a f_open +08003bd8 g F .text 0000016a f_open 080015a0 g F .text 0000006c disk_write +08001af0 g F .text 00000026 ETH_MACReceptionCmd 080002e4 g F .text 00000060 FileFirmwareUpdateLogHook +200017d0 g O .bss 00000640 TxBuff 2000001c g O .data 00000004 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g F .text 00000018 SDIO_DeInit diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/bin/openbtl_olimex_stm32e407.srec b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/bin/openbtl_olimex_stm32e407.srec index 9174b342..c4ee2b5c 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/bin/openbtl_olimex_stm32e407.srec +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/bin/openbtl_olimex_stm32e407.srec @@ -1,79 +1,79 @@ S024000062696E2F6F70656E62746C5F6F6C696D65785F73746D3332653430372E737265639F -S315080000003C180020A953000895530008955300088A -S315080000109553000895530008955300089553000812 -S315080000209553000895530008955300089553000802 -S3150800003095530008955300089553000895530008F2 -S3150800004095530008955300089553000895530008E2 -S3150800005095530008955300089553000895530008D2 -S3150800006095530008955300089553000895530008C2 -S3150800007095530008955300089553000895530008B2 -S3150800008095530008955300089553000895530008A2 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+S31508007F600000000000000000000000000000000003 +S31508007F7000000000000000000000000000000000F3 +S31508007F8000000000000000000000000000000000E3 +S30D08007F900000000000000000DB +S31508007F9801000000010000000000000001020304BF +S31508007FA8010203040607080904000000947E000875 S70508000000F2 diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/blt_conf.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/blt_conf.h index 7c66ef5f..1bc54a2b 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/blt_conf.h +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/blt_conf.h @@ -108,6 +108,82 @@ #define BOOT_COM_UART_CHANNEL_INDEX (5) +/* The NET communication interface for firmware updates via TCP/IP is selected by setting + * the BOOT_COM_NET_ENABLE configurable to 1. The maximum amount of data bytes in a + * message for data transmission and reception is set through BOOT_COM_NET_TX_MAX_DATA + * and BOOT_COM_NET_RX_MAX_DATA, respectively. The default IP address is configured + * with the macros BOOT_COM_NET_IPADDRx. The default netmask is configued with the macros + * BOOT_COM_NET_NETMASKx. The default gateway is configured with the macros + * BOOT_COM_NET_GATEWAYx. The bootloader acts and a TCP/IP server. The port the server + * listen on for connections is configured with BOOT_COM_NET_PORT. + */ +/** \brief Enable/disable the NET transport layer. */ +#define BOOT_COM_NET_ENABLE (1) +/** \brief Configure number of bytes in the target->host data packet. */ +#define BOOT_COM_NET_TX_MAX_DATA (64) +/** \brief Configure number of bytes in the host->target data packet. */ +#define BOOT_COM_NET_RX_MAX_DATA (64) +/** \brief Configure the port that the TCP/IP server listens on */ +#define BOOT_COM_NET_PORT (1000) +/** \brief Configure the 1st byte of the IP address */ +#define BOOT_COM_NET_IPADDR0 (169) +/** \brief Configure the 2nd byte of the IP address */ +#define BOOT_COM_NET_IPADDR1 (254) +/** \brief Configure the 3rd byte of the IP address */ +#define BOOT_COM_NET_IPADDR2 (19) +/** \brief Configure the 4th byte of the IP address */ +#define BOOT_COM_NET_IPADDR3 (63) +/** \brief Configure the 1st byte of the network mask */ +#define BOOT_COM_NET_NETMASK0 (255) +/** \brief Configure the 2nd byte of the network mask */ +#define BOOT_COM_NET_NETMASK1 (255) +/** \brief Configure the 3rd byte of the network mask */ +#define BOOT_COM_NET_NETMASK2 (0) +/** \brief Configure the 4th byte of the network mask */ +#define BOOT_COM_NET_NETMASK3 (0) +/** \brief Configure the 1st byte of the gateway address */ +#define BOOT_COM_NET_GATEWAY0 (169) +/** \brief Configure the 2nd byte of the gateway address */ +#define BOOT_COM_NET_GATEWAY1 (254) +/** \brief Configure the 3rd byte of the gateway address */ +#define BOOT_COM_NET_GATEWAY2 (19) +/** \brief Configure the 4th byte of the gateway address */ +#define BOOT_COM_NET_GATEWAY3 (1) +/** \brief Enable/disable a hook function that is called when the IP address is about + * to be set. This allows a dynamic override of the BOOT_COM_NET_IPADDRx values. + */ +#define BOOT_COM_NET_IPADDR_HOOK_ENABLE (0) +/** \brief Enable/disable a hook function that is called when the netmask is about + * to be set. This allows a dynamic override of the BOOT_COM_NET_NETMASKx values. + */ +#define BOOT_COM_NET_NETMASK_HOOK_ENABLE (0) +/** \brief Enable/disable a hook function that is called when the gateway address is + * about to be set. This allows a dynamic override of the BOOT_COM_NET_GATEWAYx + * values. + */ +#define BOOT_COM_NET_GATEWAY_HOOK_ENABLE (0) + + +/**************************************************************************************** +* B A C K D O O R C O N F I G U R A T I O N +****************************************************************************************/ +#if (BOOT_COM_NET_ENABLE > 0) +/* Override the default time that the backdoor is open if firmware updates via TCP/IP + * are supported. in this case a reactivation of the bootloader results in a re- + * initialization of the ethernet MAC. when directly connected to the ethernet port of + * a PC this will go relatively fast (depending on what MS Windows is being used), but + * when connected to the network via a router this can take several seconds. feel free to + * shorten/lengthen this time for finetuning. the only downside of a long backdoor open + * time is that the starting of the user program will also be delayed for this time. + * + * Also note that when the target is directly connected to the ethernet port of a PC, + * the checkbox "Automatically retry socket connection" should be checked in the + * Microboot settings. if connecting via a router the uncheck this checkbox. + */ +#define BACKDOOR_ENTRY_TIMEOUT_MS (10000) +#endif + + /**************************************************************************************** * F I L E S Y S T E M I N T E R F A C E C O N F I G U R A T I O N ****************************************************************************************/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/ethernetlib/inc/stm32_eth.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/ethernetlib/inc/stm32_eth.h new file mode 100644 index 00000000..578d8baa --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/ethernetlib/inc/stm32_eth.h @@ -0,0 +1,1610 @@ +/** + ****************************************************************************** + * @file stm32_eth.h + * @author MCD Application Team + * @version V1.0.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the Ethernet + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ETH_H +#define __STM32_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" /* STM32 registers */ + +/** @addtogroup STM32_ETH_Driver + * @{ + */ + +/** @defgroup ETH_Exported_Types + * @{ + */ + +/** + * @brief ETH MAC Init structure definition + */ +typedef struct { +/** + * @brief / * MAC + */ + uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation with the external PHY */ + uint32_t ETH_Watchdog; /*!< Enable/disable Watchdog timer */ + uint32_t ETH_Jabber; /*!< Enable/disable Jabber timer */ + uint32_t ETH_InterFrameGap; /*!< Selects minimum IFG between frames during transmission */ + uint32_t ETH_CarrierSense; /*!< Enable/disable Carrier Sense */ + uint32_t ETH_Speed; /*!< Indicates the Ethernet speed: 10/100 Mbps */ + uint32_t ETH_ReceiveOwn; /*!< Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */ + uint32_t ETH_LoopbackMode; /*!< Enable/disable internal MAC MII Loopback mode */ + uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */ + uint32_t ETH_ChecksumOffload; /*!< Enable/disable the calculation of complement sum of all received Ethernet frame payloads */ + uint32_t ETH_RetryTransmission; /*!< Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */ + uint32_t ETH_AutomaticPadCRCStrip; /*!< Enable/disable Automatic MAC Pad/CRC Stripping */ + uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value */ + uint32_t ETH_DeferralCheck; /*!< Enable/disable deferral check function (Half-Duplex mode) */ + uint32_t ETH_ReceiveAll; /*!< Enable/disable all frames reception by the MAC (No fitering)*/ + uint32_t ETH_SourceAddrFilter; /*!< Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */ + uint32_t ETH_PassControlFrames; /*!< Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */ + uint32_t ETH_BroadcastFramesReception; /*!< Enable/disable reception of Broadcast Frames */ + uint32_t ETH_DestinationAddrFilter; /*!< Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */ + uint32_t ETH_PromiscuousMode; /*!< Enable/disable Promiscuous Mode */ + uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */ + uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter */ + uint32_t ETH_HashTableHigh; /*!< This field contains the higher 32 bits of Hash table. */ + uint32_t ETH_HashTableLow; /*!< This field contains the lower 32 bits of Hash table. */ + uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame */ + uint32_t ETH_ZeroQuantaPause; /*!< Enable/disable the automatic generation of Zero-Quanta Pause Control frames */ + uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */ + uint32_t ETH_UnicastPauseFrameDetect; /*!< Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */ + uint32_t ETH_ReceiveFlowControl; /*!< Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */ + uint32_t ETH_TransmitFlowControl; /*!< Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */ + uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */ + uint32_t ETH_VLANTagIdentifier; /*!< VLAN tag identifier for receive frames */ + +/** + * @brief / * DMA + */ + uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Enable/disable Dropping of TCP/IP Checksum Error Frames */ + uint32_t ETH_ReceiveStoreForward; /*!< Enable/disable Receive store and forward */ + uint32_t ETH_FlushReceivedFrame; /*!< Enable/disable flushing of received frames */ + uint32_t ETH_TransmitStoreForward; /*!< Enable/disable Transmit store and forward */ + uint32_t ETH_TransmitThresholdControl; /*!< Selects the Transmit Threshold Control */ + uint32_t ETH_ForwardErrorFrames; /*!< Enable/disable forward to DMA of all frames except runt error frames */ + uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */ + uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO */ + uint32_t ETH_SecondFrameOperate; /*!< Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */ + uint32_t ETH_AddressAlignedBeats; /*!< Enable/disable Address Aligned Beats */ + uint32_t ETH_FixedBurst; /*!< Enable/disable the AHB Master interface fixed burst transfers */ + uint32_t ETH_RxDMABurstLength; /*!< Indicate the maximum number of beats to be transferred in one Rx DMA transaction */ + uint32_t ETH_TxDMABurstLength; /*!< Indicate the maximum number of beats to be transferred in one Tx DMA transaction */ + uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + uint32_t ETH_DMAArbitration; /*!< Selects DMA Tx/Rx arbitration */ +}ETH_InitTypeDef; + +/**--------------------------------------------------------------------------**/ +/** + * @brief DMA descriptors types + */ +/**--------------------------------------------------------------------------**/ + +/** + * @brief ETH DMA Desciptors data structure definition + */ +typedef struct { + uint32_t Status; /*!< Status */ + uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ +} ETH_DMADESCTypeDef; + +/** + * @} + */ + +/** @defgroup ETH_Exported_Constants + * @{ + */ +/**--------------------------------------------------------------------------**/ +/** + * @brief ETH Frames defines + */ +/**--------------------------------------------------------------------------**/ + +/** @defgroup ENET_Buffers_setting + * @{ + */ +#define ETH_MAX_PACKET_SIZE 1520 /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /*!< Ethernet CRC */ +#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ +#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA descriptors registers bits definition + */ +/**--------------------------------------------------------------------------**/ + +/* DMA Tx Desciptor -----------------------------------------------------------*/ +/**---------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ---------------------------------------------------------------------------------------------**/ + +/** + * @brief Bit definition of TDES0 register: DMA Tx descriptor status register + */ +#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */ +#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */ +#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */ +#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ +#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ +#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ +#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */ +#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ +#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ + +/** + * @brief Bit definition of TDES1 register + */ +#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ + +/** + * @brief Bit definition of TDES2 register + */ +#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of TDES3 register + */ +#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/** + * @} + */ + + +/** @defgroup DMA_Rx_descriptor + * @{ + */ + +/**-------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + -------------------------------------------------------------------------------------------------------------------**/ + +/** + * @brief Bit definition of RDES0 register: DMA Rx descriptor status register + */ +#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */ +#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/** + * @brief Bit definition of RDES1 register + */ +#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ + +/** + * @brief Bit definition of RDES2 register + */ +#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of RDES3 register + */ +#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/**--------------------------------------------------------------------------**/ +/** + * @brief Desciption of common PHY registers + */ +/**--------------------------------------------------------------------------**/ + +/** + * @} + */ + +/** @defgroup PHY_Read_write_Timeouts + * @{ + */ +#define PHY_READ_TO ((uint32_t)0x0004FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) + +/** + * @} + */ + +/** @defgroup PHY_Reset_Delay + * @{ + */ +#define PHY_ResetDelay ((uint32_t)0x04000000) + +/** + * @} + */ + +/** @defgroup PHY_Config_Delay + * @{ + */ +#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) + +/** + * @} + */ + +/** @defgroup PHY_Register_address + * @{ + */ +#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */ +#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */ + +/** + * @} + */ + +/** @defgroup PHY_basic_Control_register + * @{ + */ +#define PHY_Reset ((u16)0x8000) /*!< PHY Reset */ +#define PHY_Loopback ((u16)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((u16)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((u16)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_Powerdown ((u16)0x0800) /*!< Select the power down mode */ +#define PHY_Isolate ((u16)0x0400) /*!< Isolate PHY from MII */ + +/** + * @} + */ + +/** @defgroup PHY_basic_status_register + * @{ + */ +#define PHY_AutoNego_Complete ((u16)0x0020) /*!< Auto-Negotioation process completed */ +#define PHY_Linked_Status ((u16)0x0004) /*!< Valid link established */ +#define PHY_Jabber_detection ((u16)0x0002) /*!< Jabber condition detected */ + +/** + * @} + */ + +/** @defgroup PHY_status_register + * @{ + */ +/* The PHY status register value change from a PHY to another so the user have + to update this value depending on the used external PHY */ +/** + * @brief For LAN8700 + */ +//#define PHY_SR 31 /*!< Tranceiver Status Register */ +/** + * @brief For DP83848 + */ +#define PHY_SR 16 /*!< Tranceiver Status Register */ + +/* The Speed and Duplex mask values change from a PHY to another so the user have to update + this value depending on the used external PHY */ +/** + * @brief For LAN8700 + */ +//#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */ +//#define PHY_Duplex_Status ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */ + +/** + * @brief For DP83848 + */ +#define PHY_Speed_Status ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */ +#define PHY_Duplex_Status ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */ +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) +#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \ + ((REG) == PHY_BSR) || \ + ((REG) == PHY_SR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief MAC defines + */ +/**--------------------------------------------------------------------------**/ + +/** + * @} + */ + +/** @defgroup ETH_AutoNegotiation + * @{ + */ +#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) +#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) +#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \ + ((CMD) == ETH_AutoNegotiation_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_watchdog + * @{ + */ +#define ETH_Watchdog_Enable ((uint32_t)0x00000000) +#define ETH_Watchdog_Disable ((uint32_t)0x00800000) +#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \ + ((CMD) == ETH_Watchdog_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Jabber + * @{ + */ +#define ETH_Jabber_Enable ((uint32_t)0x00000000) +#define ETH_Jabber_Disable ((uint32_t)0x00400000) +#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \ + ((CMD) == ETH_Jabber_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Inter_Frame_Gap + * @{ + */ +#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ +#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \ + ((GAP) == ETH_InterFrameGap_88Bit) || \ + ((GAP) == ETH_InterFrameGap_80Bit) || \ + ((GAP) == ETH_InterFrameGap_72Bit) || \ + ((GAP) == ETH_InterFrameGap_64Bit) || \ + ((GAP) == ETH_InterFrameGap_56Bit) || \ + ((GAP) == ETH_InterFrameGap_48Bit) || \ + ((GAP) == ETH_InterFrameGap_40Bit)) + +/** + * @} + */ + +/** @defgroup ETH_Carrier_Sense + * @{ + */ +#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) +#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) +#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \ + ((CMD) == ETH_CarrierSense_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Speed + * @{ + */ +#define ETH_Speed_10M ((uint32_t)0x00000000) +#define ETH_Speed_100M ((uint32_t)0x00004000) +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \ + ((SPEED) == ETH_Speed_100M)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Own + * @{ + */ +#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) +#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) +#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \ + ((CMD) == ETH_ReceiveOwn_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Loop_back_Mode + * @{ + */ +#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) +#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) +#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \ + ((CMD) == ETH_LoopbackMode_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Duplex_mode + * @{ + */ +#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) +#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) +#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \ + ((MODE) == ETH_Mode_HalfDuplex)) + +/** + * @} + */ + +/** @defgroup ETH_Checksum_Offload + * @{ + */ +#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) +#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) +#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \ + ((CMD) == ETH_ChecksumOffload_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Retry_Transmission + * @{ + */ +#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) +#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) +#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \ + ((CMD) == ETH_RetryTransmission_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Automatic_Pad_CRC_Strip + * @{ + */ +#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) +#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \ + ((CMD) == ETH_AutomaticPadCRCStrip_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Back-Off_limit + * @{ + */ +#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) +#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) +#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) +#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) +#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \ + ((LIMIT) == ETH_BackOffLimit_8) || \ + ((LIMIT) == ETH_BackOffLimit_4) || \ + ((LIMIT) == ETH_BackOffLimit_1)) + +/** + * @} + */ + +/** @defgroup ETH_Deferral_Check + * @{ + */ +#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) +#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) +#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \ + ((CMD) == ETH_DeferralCheck_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_All + * @{ + */ +#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) +#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \ + ((CMD) == ETH_ReceiveAll_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Source_Addr_Filter + * @{ + */ +#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) +#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) +#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Pass_Control_Frames + * @{ + */ +#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ +#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter)) + +/** + * @} + */ + +/** @defgroup ETH_Broadcast_Frames_Reception + * @{ + */ +#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) +#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \ + ((CMD) == ETH_BroadcastFramesReception_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Destination_Addr_Filter + * @{ + */ +#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) +#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \ + ((FILTER) == ETH_DestinationAddrFilter_Inverse)) + +/** + * @} + */ + +/** @defgroup ETH_Promiscuous_Mode + * @{ + */ +#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) +#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) +#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \ + ((CMD) == ETH_PromiscuousMode_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_multicast_frames_filter + * @{ + */ +#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) +#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) +#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \ + ((FILTER) == ETH_MulticastFramesFilter_None)) + + +/** + * @} + */ + +/** @defgroup ETH_unicast_frames_filter + * @{ + */ +#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) +#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_Perfect)) + +/** + * @} + */ + +/** @defgroup ETH_Pause_Time + * @{ + */ +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) + +/** + * @} + */ + +/** @defgroup ETH_Zero_Quanta_Pause + * @{ + */ +#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) +#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \ + ((CMD) == ETH_ZeroQuantaPause_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Pause_Low_Threshold + * @{ + */ +#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ +#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus256)) + +/** + * @} + */ + +/** @defgroup ETH_Unicast_Pause_Frame_Detect + * @{ + */ +#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) +#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \ + ((CMD) == ETH_UnicastPauseFrameDetect_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Flow_Control + * @{ + */ +#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \ + ((CMD) == ETH_ReceiveFlowControl_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Transmit_Flow_Control + * @{ + */ +#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) +#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) +#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \ + ((CMD) == ETH_TransmitFlowControl_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_VLAN_Tag_Comparison + * @{ + */ +#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) +#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) +#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \ + ((COMPARISON) == ETH_VLANTagComparison_16Bit)) +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) + +/** + * @} + */ + +/** @defgroup ETH_MAC_Flags + * @{ + */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ +#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ + ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ + ((FLAG) == ETH_MAC_FLAG_PMT)) +/** + * @} + */ + +/** @defgroup ETH_MAC_Interrupts + * @{ + */ +#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ +#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ + ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ + ((IT) == ETH_MAC_IT_PMT)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses + * @{ + */ +#define ETH_MAC_Address0 ((uint32_t)0x00000000) +#define ETH_MAC_Address1 ((uint32_t)0x00000008) +#define ETH_MAC_Address2 ((uint32_t)0x00000010) +#define ETH_MAC_Address3 ((uint32_t)0x00000018) +#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \ + ((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) +#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter:_SA_DA_filed_of_received_frames + * @{ + */ +#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) +#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) +#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \ + ((FILTER) == ETH_MAC_AddressFilter_DA)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter:_Mask_bytes + * @{ + */ +#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ +#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \ + ((MASK) == ETH_MAC_AddressMask_Byte5) || \ + ((MASK) == ETH_MAC_AddressMask_Byte4) || \ + ((MASK) == ETH_MAC_AddressMask_Byte3) || \ + ((MASK) == ETH_MAC_AddressMask_Byte2) || \ + ((MASK) == ETH_MAC_AddressMask_Byte1)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA Desciptors defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_flags + * @{ + */ +#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \ + ((FLAG) == ETH_DMATxDesc_IC) || \ + ((FLAG) == ETH_DMATxDesc_LS) || \ + ((FLAG) == ETH_DMATxDesc_FS) || \ + ((FLAG) == ETH_DMATxDesc_DC) || \ + ((FLAG) == ETH_DMATxDesc_DP) || \ + ((FLAG) == ETH_DMATxDesc_TTSE) || \ + ((FLAG) == ETH_DMATxDesc_TER) || \ + ((FLAG) == ETH_DMATxDesc_TCH) || \ + ((FLAG) == ETH_DMATxDesc_TTSS) || \ + ((FLAG) == ETH_DMATxDesc_IHE) || \ + ((FLAG) == ETH_DMATxDesc_ES) || \ + ((FLAG) == ETH_DMATxDesc_JT) || \ + ((FLAG) == ETH_DMATxDesc_FF) || \ + ((FLAG) == ETH_DMATxDesc_PCE) || \ + ((FLAG) == ETH_DMATxDesc_LCA) || \ + ((FLAG) == ETH_DMATxDesc_NC) || \ + ((FLAG) == ETH_DMATxDesc_LCO) || \ + ((FLAG) == ETH_DMATxDesc_EC) || \ + ((FLAG) == ETH_DMATxDesc_VF) || \ + ((FLAG) == ETH_DMATxDesc_CC) || \ + ((FLAG) == ETH_DMATxDesc_ED) || \ + ((FLAG) == ETH_DMATxDesc_UF) || \ + ((FLAG) == ETH_DMATxDesc_DB)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_segment + * @{ + */ +#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */ +#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \ + ((SEGMENT) == ETH_DMATxDesc_FirstSegment)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control + * @{ + */ +#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ +#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull)) +/** + * @brief ETH DMA Tx Desciptor buffer size + */ +#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_flags + * @{ + */ +#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \ + ((FLAG) == ETH_DMARxDesc_AFM) || \ + ((FLAG) == ETH_DMARxDesc_ES) || \ + ((FLAG) == ETH_DMARxDesc_DE) || \ + ((FLAG) == ETH_DMARxDesc_SAF) || \ + ((FLAG) == ETH_DMARxDesc_LE) || \ + ((FLAG) == ETH_DMARxDesc_OE) || \ + ((FLAG) == ETH_DMARxDesc_VLAN) || \ + ((FLAG) == ETH_DMARxDesc_FS) || \ + ((FLAG) == ETH_DMARxDesc_LS) || \ + ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \ + ((FLAG) == ETH_DMARxDesc_LC) || \ + ((FLAG) == ETH_DMARxDesc_FT) || \ + ((FLAG) == ETH_DMARxDesc_RWT) || \ + ((FLAG) == ETH_DMARxDesc_RE) || \ + ((FLAG) == ETH_DMARxDesc_DBE) || \ + ((FLAG) == ETH_DMARxDesc_CE) || \ + ((FLAG) == ETH_DMARxDesc_MAMPCE)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_buffers_ + * @{ + */ +#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ +#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \ + ((BUFFER) == ETH_DMARxDesc_Buffer2)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame + * @{ + */ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) +#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \ + ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Receive_Store_Forward + * @{ + */ +#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \ + ((CMD) == ETH_ReceiveStoreForward_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Flush_Received_Frame + * @{ + */ +#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) +#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \ + ((CMD) == ETH_FlushReceivedFrame_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Store_Forward + * @{ + */ +#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) +#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) +#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \ + ((CMD) == ETH_TransmitStoreForward_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Threshold_Control + * @{ + */ +#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes)) +/** + * @} + */ + +/** @defgroup ETH_Forward_Error_Frames + * @{ + */ +#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) +#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \ + ((CMD) == ETH_ForwardErrorFrames_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Forward_Undersized_Good_Frames + * @{ + */ +#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) +#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \ + ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Threshold_Control + * @{ + */ +#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ +#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes)) +/** + * @} + */ + +/** @defgroup ETH_Second_Frame_Operate + * @{ + */ +#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) +#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) +#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \ + ((CMD) == ETH_SecondFrameOperate_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Address_Aligned_Beats + * @{ + */ +#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) +#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \ + ((CMD) == ETH_AddressAlignedBeats_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Fixed_Burst + * @{ + */ +#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) +#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) +#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \ + ((CMD) == ETH_FixedBurst_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Rx_DMA_Burst_Length + * @{ + */ +#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat)) + +/** + * @} + */ + +/** @defgroup ETH_Tx_DMA_Burst_Length + * @{ + */ +#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat)) +/** + * @brief ETH DMA Desciptor SkipLength + */ +#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Arbitration + * @{ + */ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) +#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \ + ((RATIO) == ETH_DMAArbitration_RxPriorTx)) +/** + * @} + */ + +/** @defgroup ETH_DMA_Flags + * @{ + */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ +#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */ +#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */ +#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ + +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) +#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ + ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \ + ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \ + ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ + ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ + ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ + ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ + ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ + ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ + ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ + ((FLAG) == ETH_DMA_FLAG_T)) +/** + * @} + */ + +/** @defgroup ETH_DMA_Interrupts + * @{ + */ +#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ +#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ +#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */ +#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */ +#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ + +#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ + ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ + ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ + ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ + ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ + ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ + ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ + ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ + ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_transmit_process_state_ + * @{ + */ +#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ + +/** + * @} + */ + + +/** @defgroup ETH_DMA_receive_process_state_ + * @{ + */ +#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the recieve frame into host memory */ + +/** + * @} + */ + +/** @defgroup ETH_DMA_overflow_ + * @{ + */ +#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ +#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \ + ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet PMT defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_PMT_Flags + * @{ + */ +#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ + ((FLAG) == ETH_PMT_FLAG_MPR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet MMC defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_MMC_Tx_Interrupts + * @{ + */ +#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ + +/** + * @} + */ + +/** @defgroup ETH_MMC_Rx_Interrupts + * @{ + */ +#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ +#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ + ((IT) != 0x00)) +#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ + ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ + ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) +/** + * @} + */ + +/** @defgroup ETH_MMC_Registers + * @{ + */ +#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */ +#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */ +#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */ +#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */ +#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */ +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */ +#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */ +#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */ +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */ + +/** + * @brief ETH MMC registers + */ +#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \ + ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \ + ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \ + ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \ + ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \ + ((REG) == ETH_MMCRGUFCR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet PTP defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_PTP_time_update_method + * @{ + */ +#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */ +#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */ +#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \ + ((UPDATE) == ETH_PTP_CoarseUpdate)) + +/** + * @} + */ + + +/** @defgroup ETH_PTP_Flags + * @{ + */ +#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */ +#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \ + ((FLAG) == ETH_PTP_FLAG_TSITE) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTU) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTI)) +/** + * @brief ETH PTP subsecond increment + */ +#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) + +/** + * @} + */ + + +/** @defgroup ETH_PTP_time_sign + * @{ + */ +#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */ +#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */ +#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \ + ((SIGN) == ETH_PTP_NegativeTime)) + +/** + * @brief ETH PTP time stamp low update + */ +#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) + +/** + * @brief ETH PTP registers + */ +#define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */ +#define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */ +#define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */ +#define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */ +#define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */ +#define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */ +#define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */ +#define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */ +#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ +#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \ + ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \ + ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \ + ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \ + ((REG) == ETH_PTPTTLR)) + +/** + * @} + */ + + +/** + * @} + */ + +/** @defgroup ETH_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions + * @{ + */ +void ETH_DeInit(void); +uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress); +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +void ETH_Start(void); +uint32_t ETH_HandleTxPkt(u8 *ppkt, u16 FrameLength); +uint32_t ETH_HandleRxPkt(u8 *ppkt); +uint32_t ETH_GetRxPktSize(void); +void ETH_DropRxPkt(void); + +/** + * @brief PHY + */ +u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg); +uint32_t ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue); +uint32_t ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState); + +/** + * @brief MAC + */ +void ETH_MACTransmissionCmd(FunctionalState NewState); +void ETH_MACReceptionCmd(FunctionalState NewState); +FlagStatus ETH_GetFlowControlBusyStatus(void); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState NewState); +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); +void ETH_MACAddressConfig(uint32_t MacAddr, u8 *Addr); +void ETH_GetMACAddress(uint32_t MacAddr, u8 *Addr); +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); + +/** + * @brief DMA Tx/Rx descriptors + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, uint32_t TxBuffCount); +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, uint32_t TxBuffCount); +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, uint32_t RxBuffCount); +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, uint32_t RxBuffCount); +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); + +/** + * @brief DMA + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); +uint32_t ETH_GetTransmitProcessState(void); +uint32_t ETH_GetReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); +void ETH_DMATransmissionCmd(FunctionalState NewState); +void ETH_DMAReceptionCmd(FunctionalState NewState); +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); +uint32_t ETH_GetRxOverflowMissedFrameCounter(void); +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); +uint32_t ETH_GetCurrentTxDescStartAddress(void); +uint32_t ETH_GetCurrentRxDescStartAddress(void); +uint32_t ETH_GetCurrentTxBufferAddress(void); +uint32_t ETH_GetCurrentRxBufferAddress(void); +void ETH_ResumeDMATransmission(void); +void ETH_ResumeDMAReception(void); + +/** + * @brief PMT + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); +void ETH_MagicPacketDetectionCmd(FunctionalState NewState); +void ETH_PowerDownCmd(FunctionalState NewState); + +/** + * @brief MMC + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState); +void ETH_MMCResetOnReadCmd(FunctionalState NewState); +void ETH_MMCCounterRolloverCmd(FunctionalState NewState); +void ETH_MMCCountersReset(void); +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); + +/** + * @brief PTP + */ +uint32_t ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, uint32_t *PTPTxTab); +uint32_t ETH_HandlePTPRxPkt(u8 *ppkt, uint32_t *PTPRxTab); +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, uint32_t TxBuffCount); +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, uint32_t RxBuffCount); +void ETH_EnablePTPTimeStampAddend(void); +void ETH_EnablePTPTimeStampInterruptTrigger(void); +void ETH_EnablePTPTimeStampUpdate(void); +void ETH_InitializePTPTimeStamp(void); +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod); +void ETH_PTPTimeStampCmd(FunctionalState NewState); +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG); +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue); +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); +void ETH_SetPTPTimeStampAddend(uint32_t Value); +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue); +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ETH_H */ +/** + * @} + */ + + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/ethernetlib/src/stm32_eth.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/ethernetlib/src/stm32_eth.c new file mode 100644 index 00000000..119b4dbf --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/ethernetlib/src/stm32_eth.c @@ -0,0 +1,3056 @@ +/** + ****************************************************************************** + * @file stm32_eth.c + * @author MCD Application Team + * @version V1.0.0 + * @date 06/19/2009 + * @brief This file provides all the ETH firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_eth.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32_ETH_Driver + * @brief ETH driver modules + * @{ + */ + +/** @defgroup ETH_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup ETH_Private_Defines + * @{ + */ +/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */ +ETH_DMADESCTypeDef *DMATxDescToSet; +ETH_DMADESCTypeDef *DMARxDescToGet; +ETH_DMADESCTypeDef *DMAPTPTxDescToSet; +ETH_DMADESCTypeDef *DMAPTPRxDescToGet; + +/* ETHERNET MAC address offsets */ +#define ETH_MAC_AddrHighBase (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_AddrLowBase (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_Mask ((uint32_t)0xFFFFFFE3) +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_Mask ((uint32_t)0xFF20810F) +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_Mask ((uint32_t)0x0000FF41) +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_Mask ((uint32_t)0xF8DE3F23) +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WakeupRegisterLength 8 +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RxOverflowMissedFramesCounterShift 17 +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATxDesc_CollisionCountShift 3 +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATxDesc_BufferSize2Shift 16 +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARxDesc_FrameLengthShift 16 +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARxDesc_Buffer2SizeShift 16 +/* ETHERNET errors */ +#define ETH_ERROR ((uint32_t)0) +#define ETH_SUCCESS ((uint32_t)1) +/** + * @} + */ + +/** @defgroup ETH_Private_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ETHERNET peripheral registers to their + * default reset values. + * @param None + * @retval : None + */ +void ETH_DeInit(void) +{ + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE); +} + +/** + * @brief Initializes the ETHERNET peripheral according to the specified + * parameters in the ETH_InitStruct . + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure + * that contains the configuration information for the + * specified ETHERNET peripheral. + * @param PHYAddress: external PHY address + * @retval : ETH_ERROR: Ethernet initialization failed + * ETH_SUCCESS: Ethernet successfully initialized + */ +uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) +{ + uint32_t RegValue = 0, tmpreg = 0; + __IO uint32_t i = 0; + RCC_ClocksTypeDef rcc_clocks; + uint32_t hclk = 120000000; + __IO uint32_t timeout = 0; + /* Check the parameters */ + /* MAC --------------------------*/ + assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation)); + assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog)); + assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber)); + assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap)); + assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense)); + assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed)); + assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn)); + assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode)); + assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode)); + assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload)); + assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission)); + assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip)); + assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit)); + assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck)); + assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll)); + assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter)); + assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames)); + assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception)); + assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter)); + assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode)); + assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); + assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter)); + assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime)); + assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause)); + assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold)); + assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect)); + assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl)); + assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl)); + assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison)); + assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier)); + /* DMA --------------------------*/ + assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame)); + assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward)); + assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame)); + assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward)); + assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl)); + assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames)); + assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames)); + assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl)); + assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate)); + assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats)); + assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst)); + assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength)); + assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); + assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); + assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); + /*-------------------------------- MAC Config ------------------------------*/ + /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/ + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg &= MACMIIAR_CR_Mask; + /* Get hclk frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + hclk = rcc_clocks.HCLK_Frequency; + /* Set CR bits depending on hclk value */ + if((hclk >= 20000000)&&(hclk < 35000000)) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; + } + else if((hclk >= 35000000)&&(hclk < 60000000)) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; + } + else if((hclk >= 60000000)&&(hclk <= 100000000)) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else /*if((hclk >= 100000000)&&(hclk <= 120000000)) */ + { + /* CSR Clock Range between 100-120 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; + } + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + ETH->MACMIIAR = (uint32_t)tmpreg; + /*-------------------- PHY initialization and configuration ----------------*/ + /* Put the PHY in reset mode */ + if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + + /* Delay to assure PHY reset */ + for(i = PHY_ResetDelay; i != 0; i--) + { + } + + if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) + { + /* We wait for linked satus... */ + do + { + timeout++; + } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Reset Timeout counter */ + timeout = 0; + + /* Enable Auto-Negotiation */ + if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + + /* Wait until the autonegotiation will be completed */ + do + { + timeout++; + } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Reset Timeout counter */ + timeout = 0; + + /* Read the result of the autonegotiation */ + RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR); + + /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */ + if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET) + { + /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */ + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + + } + else + { + /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */ + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + } + /* Configure the MAC with the speed fixed by the autonegotiation process */ + if(RegValue & PHY_Speed_Status) + { + /* Set Ethernet speed to 10M following the autonegotiation */ + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + } + else + { + /* Set Ethernet speed to 100M following the autonegotiation */ + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + } + } + else + { + if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) | + (uint16_t)(ETH_InitStruct->ETH_Speed >> 1)))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + /* Delay to assure PHY configuration */ + for(i = PHY_ConfigDelay; i != 0; i--) + { + } + } + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = ETH->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg &= MACCR_CLEAR_Mask; + /* Set the WD bit according to ETH_Watchdog value */ + /* Set the JD: bit according to ETH_Jabber value */ + /* Set the IFG bit according to ETH_InterFrameGap value */ + /* Set the DCRS bit according to ETH_CarrierSense value */ + /* Set the FES bit according to ETH_Speed value */ + /* Set the DO bit according to ETH_ReceiveOwn value */ + /* Set the LM bit according to ETH_LoopbackMode value */ + /* Set the DM bit according to ETH_Mode value */ + /* Set the IPC bit according to ETH_ChecksumOffload value */ + /* Set the DR bit according to ETH_RetryTransmission value */ + /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ + /* Set the BL bit according to ETH_BackOffLimit value */ + /* Set the DC bit according to ETH_DeferralCheck value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | + ETH_InitStruct->ETH_Jabber | + ETH_InitStruct->ETH_InterFrameGap | + ETH_InitStruct->ETH_CarrierSense | + ETH_InitStruct->ETH_Speed | + ETH_InitStruct->ETH_ReceiveOwn | + ETH_InitStruct->ETH_LoopbackMode | + ETH_InitStruct->ETH_Mode | + ETH_InitStruct->ETH_ChecksumOffload | + ETH_InitStruct->ETH_RetryTransmission | + ETH_InitStruct->ETH_AutomaticPadCRCStrip | + ETH_InitStruct->ETH_BackOffLimit | + ETH_InitStruct->ETH_DeferralCheck); + /* Write to ETHERNET MACCR */ + ETH->MACCR = (uint32_t)tmpreg; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Set the RA bit according to ETH_ReceiveAll value */ + /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */ + /* Set the PCF bit according to ETH_PassControlFrames value */ + /* Set the DBF bit according to ETH_BroadcastFramesReception value */ + /* Set the DAIF bit according to ETH_DestinationAddrFilter value */ + /* Set the PR bit according to ETH_PromiscuousMode value */ + /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */ + /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */ + /* Write to ETHERNET MACFFR */ + ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | + ETH_InitStruct->ETH_SourceAddrFilter | + ETH_InitStruct->ETH_PassControlFrames | + ETH_InitStruct->ETH_BroadcastFramesReception | + ETH_InitStruct->ETH_DestinationAddrFilter | + ETH_InitStruct->ETH_PromiscuousMode | + ETH_InitStruct->ETH_MulticastFramesFilter | + ETH_InitStruct->ETH_UnicastFramesFilter); + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ + /* Write to ETHERNET MACHTHR */ + ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh; + /* Write to ETHERNET MACHTLR */ + ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + /* Get the ETHERNET MACFCR value */ + tmpreg = ETH->MACFCR; + /* Clear xx bits */ + tmpreg &= MACFCR_CLEAR_Mask; + + /* Set the PT bit according to ETH_PauseTime value */ + /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */ + /* Set the PLT bit according to ETH_PauseLowThreshold value */ + /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */ + /* Set the RFE bit according to ETH_ReceiveFlowControl value */ + /* Set the TFE bit according to ETH_TransmitFlowControl value */ + tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | + ETH_InitStruct->ETH_ZeroQuantaPause | + ETH_InitStruct->ETH_PauseLowThreshold | + ETH_InitStruct->ETH_UnicastPauseFrameDetect | + ETH_InitStruct->ETH_ReceiveFlowControl | + ETH_InitStruct->ETH_TransmitFlowControl); + /* Write to ETHERNET MACFCR */ + ETH->MACFCR = (uint32_t)tmpreg; + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ + /* Set the ETV bit according to ETH_VLANTagComparison value */ + /* Set the VL bit according to ETH_VLANTagIdentifier value */ + ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | + ETH_InitStruct->ETH_VLANTagIdentifier); + + /*-------------------------------- DMA Config ------------------------------*/ + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg = ETH->DMAOMR; + /* Clear xx bits */ + tmpreg &= DMAOMR_CLEAR_Mask; + + /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */ + /* Set the RSF bit according to ETH_ReceiveStoreForward value */ + /* Set the DFF bit according to ETH_FlushReceivedFrame value */ + /* Set the TSF bit according to ETH_TransmitStoreForward value */ + /* Set the TTC bit according to ETH_TransmitThresholdControl value */ + /* Set the FEF bit according to ETH_ForwardErrorFrames value */ + /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */ + /* Set the RTC bit according to ETH_ReceiveThresholdControl value */ + /* Set the OSF bit according to ETH_SecondFrameOperate value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | + ETH_InitStruct->ETH_ReceiveStoreForward | + ETH_InitStruct->ETH_FlushReceivedFrame | + ETH_InitStruct->ETH_TransmitStoreForward | + ETH_InitStruct->ETH_TransmitThresholdControl | + ETH_InitStruct->ETH_ForwardErrorFrames | + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | + ETH_InitStruct->ETH_ReceiveThresholdControl | + ETH_InitStruct->ETH_SecondFrameOperate); + /* Write to ETHERNET DMAOMR */ + ETH->DMAOMR = (uint32_t)tmpreg; + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + /* Set the AAL bit according to ETH_AddressAlignedBeats value */ + /* Set the FB bit according to ETH_FixedBurst value */ + /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */ + /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */ + /* Set the DSL bit according to ETH_DesciptorSkipLength value */ + /* Set the PR and DA bits according to ETH_DMAArbitration value */ + ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | + ETH_InitStruct->ETH_FixedBurst | + ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + ETH_InitStruct->ETH_TxDMABurstLength | + (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | + ETH_InitStruct->ETH_DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + /* Return Ethernet configuration success */ + return ETH_SUCCESS; +} + +/** + * @brief Fills each ETH_InitStruct member with its default value. + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure + * which will be initialized. + * @retval : None + */ +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct) +{ + /* ETH_InitStruct members default value */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + /*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable; + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; + ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; +} + +/** + * @brief Enables ENET MAC and DMA reception/transmission + * @param None + * @retval : None + */ +void ETH_Start(void) +{ + /* Enable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionCmd(ENABLE); + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(); + /* Enable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionCmd(ENABLE); + + /* Start DMA transmission */ + ETH_DMATransmissionCmd(ENABLE); + /* Start DMA reception */ + ETH_DMAReceptionCmd(ENABLE); +} + +/** + * @brief Transmits a packet, from application buffer, pointed by ppkt. + * @param ppkt: pointer to application packet buffer to transmit. + * @param FrameLength: Tx Packet size. + * @retval : ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission + */ +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) +{ + uint32_t offset = 0; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); + } + + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + /* Chained Mode */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Receives a packet and copies it to memory pointed by ppkt. + * @param ppkt: pointer to application packet receive buffer. + * @retval : ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct + */ +uint32_t ETH_HandleRxPkt(uint8_t *ppkt) +{ + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + } + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + /* Return Frame Length/ERROR */ + return (framelength); +} + +/** + * @brief Get the size of received the received packet. + * @param None + * @retval : framelength: received packet size + */ +uint32_t ETH_GetRxPktSize(void) +{ + uint32_t frameLength = 0; + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the size of the packet: including 4 bytes of the CRC */ + frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); + } + + /* Return Frame Length */ + return frameLength; +} + +/** + * @brief Drop a Received packet (too small packet, etc...) + * @param None + * @retval : None + */ +void ETH_DropRxPkt(void) +{ + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read: this will + be the first Rx descriptor in this case */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } +} + +/*--------------------------------- PHY ------------------------------------*/ +/** + * @brief Read a PHY register + * @param PHYAddress: PHY device address, is the index of one of supported + * 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg: PHY register address, is the index of one of the 32 + * PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR : Tranceiver Basic Control Register + * @arg PHY_BSR : Tranceiver Basic Status Register + * @arg PHY_SR : Tranceiver Status Register + * @arg More PHY register could be read depending on the used PHY + * @retval : ETH_ERROR: in case of timeout + * MAC MIIDR register value: Data read from the selected PHY register (correct read ) + */ +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) +{ + uint32_t tmpreg = 0; +__IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_Mask; + /* Prepare the MII address register value */ + tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } + + /* Return data register value */ + return (uint16_t)(ETH->MACMIIDR); +} + +/** + * @brief Write to a PHY register + * @param PHYAddress: PHY device address, is the index of one of supported + * 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg: PHY register address, is the index of one of the 32 + * PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR : Tranceiver Control Register + * @arg More PHY register could be written depending on the used PHY + * @param PHYValue: the value to write + * @retval : ETH_ERROR: in case of timeout + * ETH_SUCCESS: for correct write + */ +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_Mask; + /* Prepare the MII register address value */ + tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Give the value to the MII data register */ + ETH->MACMIIDR = PHYValue; + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_WRITE_TO) + { + return ETH_ERROR; + } + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Enables or disables the PHY loopBack mode. + * @param PHYAddress: PHY device address, is the index of one of supported + * 32 PHY devices. + * This parameter can be one of the following values: + * @param NewState: new state of the PHY loopBack mode. + * This parameter can be: ENABLE or DISABLE. + * Note: Don't be confused with ETH_MACLoopBackCmd function + * which enables internal loopback at MII level + * @retval : ETH_ERROR: in case of bad PHY configuration + * ETH_SUCCESS: for correct PHY configuration + */ +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the PHY configuration to update it */ + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + + if (NewState != DISABLE) + { + /* Enable the PHY loopback mode */ + tmpreg |= PHY_Loopback; + } + else + { + /* Disable the PHY loopback mode: normal mode */ + tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); + } + /* Update the PHY control register with the new configuration */ + if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) + { + return ETH_SUCCESS; + } + else + { + /* Return SUCCESS */ + return ETH_ERROR; + } +} + +/*--------------------------------- MAC ------------------------------------*/ +/** + * @brief Enables or disables the MAC transmission. + * @param NewState: new state of the MAC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACTransmissionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC transmission */ + ETH->MACCR |= ETH_MACCR_TE; + } + else + { + /* Disable the MAC transmission */ + ETH->MACCR &= ~ETH_MACCR_TE; + } +} + +/** + * @brief Enables or disables the MAC reception. + * @param NewState: new state of the MAC reception. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACReceptionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC reception */ + ETH->MACCR |= ETH_MACCR_RE; + } + else + { + /* Disable the MAC reception */ + ETH->MACCR &= ~ETH_MACCR_RE; + } +} + +/** + * @brief Checks whether the ETHERNET flow control busy bit is set or not. + * @param None + * @retval : The new state of flow control busy status bit (SET or RESET). + */ +FlagStatus ETH_GetFlowControlBusyStatus(void) +{ + FlagStatus bitstatus = RESET; + /* The Flow Control register should not be written to until this bit is cleared */ + if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Initiate a Pause Control Frame (Full-duplex only). + * @param None + * @retval : None + */ +void ETH_InitiatePauseControlFrame(void) +{ + /* When Set In full duplex MAC initiates pause control frame */ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; +} + +/** + * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). + * @param NewState: new state of the MAC BackPressure operation activation. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_BackPressureActivationCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Activate the MAC BackPressure operation */ + /* In Half duplex: during backpressure, when the MAC receives a new frame, + the transmitter starts sending a JAM pattern resulting in a collision */ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; + } + else + { + /* Desactivate the MAC BackPressure operation */ + ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; + } +} + +/** + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param ETH_MAC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag + * @retval : The new state of ETHERNET MAC flag (SET or RESET). + */ +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); + if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. + * @param ETH_MAC_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt + * @arg ETH_MAC_IT_MMCR : MMC receive interrupt + * @arg ETH_MAC_IT_MMC : MMC interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval : The new state of ETHERNET MAC interrupt (SET or RESET). + */ +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); + if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the specified ETHERNET MAC interrupts. + * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @param NewState: new state of the specified ETHERNET MAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_IT(ETH_MAC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC interrupts */ + ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); + } + else + { + /* Disable the selected ETHERNET MAC interrupts */ + ETH->MACIMR |= ETH_MAC_IT; + } +} + +/** + * @brief Configures the selected MAC address. + * @param MacAddr: The MAC addres to configure. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Addr: Pointer on MAC address buffer data (6 bytes). + * @retval : None + */ +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Calculate the selectecd MAC address high register */ + tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + /* Load the selectecd MAC address high register */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg; + /* Calculate the selectecd MAC address low register */ + tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + + /* Load the selectecd MAC address low register */ + (*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg; +} + +/** + * @brief Get the selected MAC address. + * @param MacAddr: The MAC addres to return. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Addr: Pointer on MAC address buffer data (6 bytes). + * @retval : None + */ +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Get the selectecd MAC address high register */ + tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)); + + /* Calculate the selectecd MAC address buffer */ + Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[4] = (tmpreg & (uint8_t)0xFF); + /* Load the selectecd MAC address low register */ + tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)); + /* Calculate the selectecd MAC address buffer */ + Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); + Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); + Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF); + Addr[0] = (tmpreg & (uint8_t)0xFF); +} + +/** + * @brief Enables or disables the Address filter module uses the specified + * ETHERNET MAC address for perfect filtering + * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param NewState: new state of the specified ETHERNET MAC address use. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE; + } + else + { + /* Disable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE); + } +} + +/** + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Filter: specifies the used frame received field for comparaison + * This parameter can be one of the following values: + * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare + * with the SA fields of the received frame. + * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare + * with the DA fields of the received frame. + * @retval : None + */ +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter)); + + if (Filter != ETH_MAC_AddressFilter_DA) + { + /* The selected ETHERNET MAC address is used to compare with the SA fields of the + received frame. */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA; + } + else + { + /* The selected ETHERNET MAC address is used to compare with the DA fields of the + received frame. */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA); + } +} + +/** + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param MaskByte: specifies the used address bytes for comparaison + * This parameter can be any combination of the following values: + * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8]. + * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0]. + * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24]. + * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16]. + * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8]. + * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0]. + * @retval : None + */ +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte)); + + /* Clear MBC bits in the selected MAC address high register */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC); + /* Set the selected Filetr mask bytes */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte; +} +/*------------------------ DMA Tx/Rx Desciptors -----------------------------*/ + +/** + * @brief Initializes the DMA Tx descriptors in chain mode. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff: Pointer on the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval : None + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Second Address Chained bit */ + DMATxDesc->Status = ETH_DMATxDesc_TCH; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Initializes the DMA Tx descriptors in ring mode. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff1: Pointer on the first TxBuffer1 list + * @param TxBuff2: Pointer on the first TxBuffer2 list + * @param TxBuffCount: Number of the used Tx desc in the list + * Note: see decriptor skip length defined in ETH_DMA_InitStruct + * for the number of Words to skip between two unchained descriptors. + * @retval : None + */ +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (TxBuffCount-1)) + { + /* Set Transmit End of Ring bit */ + DMATxDesc->Status = ETH_DMATxDesc_TER; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param ETH_DMATxDescFlag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMATxDesc_IC : Interrupt on completetion + * @arg ETH_DMATxDesc_LS : Last Segment + * @arg ETH_DMATxDesc_FS : First Segment + * @arg ETH_DMATxDesc_DC : Disable CRC + * @arg ETH_DMATxDesc_DP : Disable Pad + * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable + * @arg ETH_DMATxDesc_TER : Transmit End of Ring + * @arg ETH_DMATxDesc_TCH : Second Address Chained + * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status + * @arg ETH_DMATxDesc_IHE : IP Header Error + * @arg ETH_DMATxDesc_ES : Error summary + * @arg ETH_DMATxDesc_JT : Jabber Timeout + * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush + * @arg ETH_DMATxDesc_PCE : Payload Checksum Error + * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission + * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver + * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision + * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions + * @arg ETH_DMATxDesc_VF : VLAN Frame + * @arg ETH_DMATxDesc_CC : Collision Count + * @arg ETH_DMATxDesc_ED : Excessive Deferral + * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory + * @arg ETH_DMATxDesc_DB : Deferred Bit + * @retval : The new state of ETH_DMATxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag)); + + if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @retval : The Transmit descriptor collision counter value. + */ +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift); +} + +/** + * @brief Set the specified DMA Tx Desc Own bit. + * @param DMATxDesc: Pointer on a Tx desc + * @retval : None + */ +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) +{ + /* Set the DMA Tx Desc Own bit */ + DMATxDesc->Status |= ETH_DMATxDesc_OWN; +} + +/** + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * @param DMATxDesc: Pointer on a Tx desc + * @param NewState: new state of the DMA Tx Desc transmit interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status |= ETH_DMATxDesc_IC; + } + else + { + /* Disable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC); + } +} + +/** + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * @param DMATxDesc: Pointer on a Tx desc + * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment + * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment + * @retval : None + */ +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment)); + + /* Selects the DMA Tx Desc Frame segment */ + DMATxDesc->Status |= DMATxDesc_FrameSegment; +} + +/** + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass + * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * @retval : None + */ +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum)); + + /* Set the selected DMA Tx desc checksum insertion control */ + DMATxDesc->Status |= DMATxDesc_Checksum; +} + +/** + * @brief Enables or disables the DMA Tx Desc CRC. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc CRC. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc CRC */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); + } + else + { + /* Disable the selected DMA Tx Desc CRC */ + DMATxDesc->Status |= ETH_DMATxDesc_DC; + } +} + +/** + * @brief Enables or disables the DMA Tx Desc end of ring. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc end of ring. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status |= ETH_DMATxDesc_TER; + } + else + { + /* Disable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); + } +} + +/** + * @brief Enables or disables the DMA Tx Desc second address chained. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc second address chained. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status |= ETH_DMATxDesc_TCH; + } + else + { + /* Disable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); + } +} + +/** + * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc padding for + * frame shorter than 64 bytes. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); + } + else + { + /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/ + DMATxDesc->Status |= ETH_DMATxDesc_DP; + } +} + +/** + * @brief Enables or disables the DMA Tx Desc time stamp. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc time stamp. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + } + else + { + /* Disable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); + } +} + +/** + * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. + * @param DMATxDesc: Pointer on a Tx desc + * @param BufferSize1: specifies the Tx desc buffer1 size. + * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used). + * @retval : None + */ +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1)); + assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2)); + + /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */ + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift)); +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff: Pointer on the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval : None + */ +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Initializes the DMA Rx descriptors in ring mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff1: Pointer on the first RxBuffer1 list + * @param RxBuff2: Pointer on the first RxBuffer2 list + * @param RxBuffCount: Number of the used Rx desc in the list + * Note: see decriptor skip length defined in ETH_DMA_InitStruct + * for the number of Words to skip between two unchained descriptors. + * @retval : None + */ +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + /* Set Buffer1 size */ + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (RxBuffCount-1)) + { + /* Set Receive End of Ring bit */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param ETH_DMARxDescFlag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame + * @arg ETH_DMARxDesc_ES: Error summary + * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame + * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame + * @arg ETH_DMARxDesc_LE: Frame size not matching with length field + * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow + * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame + * @arg ETH_DMARxDesc_FS: First descriptor of the frame + * @arg ETH_DMARxDesc_LS: Last descriptor of the frame + * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * @arg ETH_DMARxDesc_LC: Late collision occurred during reception + * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3 + * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception + * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface + * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits + * @arg ETH_DMARxDesc_CE: CRC error + * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * @retval : The new state of ETH_DMARxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag)); + if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Set the specified DMA Rx Desc Own bit. + * @param DMARxDesc: Pointer on a Rx desc + * @retval : None + */ +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) +{ + /* Set the DMA Rx Desc Own bit */ + DMARxDesc->Status |= ETH_DMARxDesc_OWN; +} + +/** + * @brief Returns the specified DMA Rx Desc frame length. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @retval : The Rx descriptor received frame length. + */ +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift); +} + +/** + * @brief Enables or disables the specified DMA Rx Desc receive interrupt. + * @param DMARxDesc: Pointer on a Rx desc + * @param NewState: new state of the specified DMA Rx Desc interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC); + } + else + { + /* Disable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; + } +} + +/** + * @brief Enables or disables the DMA Rx Desc end of ring. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param NewState: new state of the specified DMA Rx Desc end of ring. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + else + { + /* Disable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); + } +} + +/** + * @brief Enables or disables the DMA Rx Desc second address chained. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param NewState: new state of the specified DMA Rx Desc second address chained. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + } + else + { + /* Disable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); + } +} + +/** + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer. + * This parameter can be any one of the following values: + * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1 + * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 + * @retval : The Receive descriptor frame length. + */ +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer)); + + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) + { + /* Return the DMA Rx Desc buffer2 size */ + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift); + } + else + { + /* Return the DMA Rx Desc buffer1 size */ + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + } +} + +/*--------------------------------- DMA ------------------------------------*/ +/** + * @brief Resets all MAC subsystem internal registers and logic. + * @param None + * @retval : None + */ +void ETH_SoftwareReset(void) +{ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + ETH->DMABMR |= ETH_DMABMR_SR; +} + +/** + * @brief Checks whether the ETHERNET software reset bit is set or not. + * @param None + * @retval : The new state of DMA Bus Mode register SR bit (SET or RESET). + */ +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param ETH_DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag + * @arg ETH_DMA_FLAG_PMT : PMT flag + * @arg ETH_DMA_FLAG_MMC : MMC flag + * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access + * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr + * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ET : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Underflow flag + * @arg ETH_DMA_FLAG_RO : Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag + * @retval : The new state of ETH_DMA_FLAG (SET or RESET). + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG)); + if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the ETHERNET’s DMA pending flag. + * @param ETH_DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ETI : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag + * @arg ETH_DMA_FLAG_RO : Receive Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag + * @retval : None + */ +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG)); + + /* Clear the selected ETHERNET DMA FLAG */ + ETH->DMASR = (uint32_t) ETH_DMA_FLAG; +} + +/** + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * @param ETH_DMA_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt + * @arg ETH_DMA_IT_PMT : PMT interrupt + * @arg ETH_DMA_IT_MMC : MMC interrupt + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @retval : The new state of ETH_DMA_IT (SET or RESET). + */ +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT)); + if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the ETHERNET’s DMA IT pending bit. + * @param ETH_DMA_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ETI : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt + * @arg ETH_DMA_IT_RO : Receive Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @retval : None + */ +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + + /* Clear the selected ETHERNET DMA IT */ + ETH->DMASR = (uint32_t) ETH_DMA_IT; +} + +/** + * @brief Returns the ETHERNET DMA Transmit Process State. + * @param None + * @retval : The new ETHERNET DMA Transmit Process State: + * This can be one of the following values: + * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued + * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor + * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status + * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory + * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe + * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor + */ +uint32_t ETH_GetTransmitProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); +} + +/** + * @brief Returns the ETHERNET DMA Receive Process State. + * @param None + * @retval : The new ETHERNET DMA Receive Process State: + * This can be one of the following values: + * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued + * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor + * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet + * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable + * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor + * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory + */ +uint32_t ETH_GetReceiveProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); +} + +/** + * @brief Clears the ETHERNET transmit FIFO. + * @param None + * @retval : None + */ +void ETH_FlushTransmitFIFO(void) +{ + /* Set the Flush Transmit FIFO bit */ + ETH->DMAOMR |= ETH_DMAOMR_FTF; +} + +/** + * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. + * @param None + * @retval : The new state of ETHERNET flush transmit FIFO bit (SET or RESET). + */ +FlagStatus ETH_GetFlushTransmitFIFOStatus(void) +{ + FlagStatus bitstatus = RESET; + if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the DMA transmission. + * @param NewState: new state of the DMA transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATransmissionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transmission */ + ETH->DMAOMR |= ETH_DMAOMR_ST; + } + else + { + /* Disable the DMA transmission */ + ETH->DMAOMR &= ~ETH_DMAOMR_ST; + } +} + +/** + * @brief Enables or disables the DMA reception. + * @param NewState: new state of the DMA reception. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMAReceptionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA reception */ + ETH->DMAOMR |= ETH_DMAOMR_SR; + } + else + { + /* Disable the DMA reception */ + ETH->DMAOMR &= ~ETH_DMAOMR_SR; + } +} + +/** + * @brief Enables or disables the specified ETHERNET DMA interrupts. + * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @param NewState: new state of the specified ETHERNET DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET DMA interrupts */ + ETH->DMAIER |= ETH_DMA_IT; + } + else + { + /* Disable the selected ETHERNET DMA interrupts */ + ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT); + } +} + +/** + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter + * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter + * @retval : The new state of ETHERNET DMA overflow Flag (SET or RESET). + */ +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow)); + + if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. + * @param None + * @retval : The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_GetRxOverflowMissedFrameCounter(void) +{ + return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift)); +} + +/** + * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. + * @param None + * @retval : The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) +{ + return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); +} + +/** + * @brief Get the ETHERNET DMA DMACHTDR register value. + * @param None + * @retval : The value of the current Tx desc start address. + */ +uint32_t ETH_GetCurrentTxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHTDR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHRDR register value. + * @param None + * @retval : The value of the current Rx desc start address. + */ +uint32_t ETH_GetCurrentRxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHRDR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHTBAR register value. + * @param None + * @retval : The value of the current Tx desc buffer address. + */ +uint32_t ETH_GetCurrentTxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHTBAR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHRBAR register value. + * @param None + * @retval : The value of the current Rx desc buffer address. + */ +uint32_t ETH_GetCurrentRxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHRBAR)); +} + +/** + * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand + * register: (the data written could be anything). This forces + * the DMA to resume transmission. + * @param None + * @retval : None. + */ +void ETH_ResumeDMATransmission(void) +{ + ETH->DMATPDR = 0; +} + +/** + * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand + * register: (the data written could be anything). This forces + * the DMA to resume reception. + * @param None + * @retval : None. + */ +void ETH_ResumeDMAReception(void) +{ + ETH->DMARPDR = 0; +} + +/*--------------------------------- PMT ------------------------------------*/ +/** + * @brief Reset Wakeup frame filter register pointer. + * @param None + * @retval : None + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; +} + +/** + * @brief Populates the remote wakeup frame registers. + * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer + * data (8 words). + * @retval : None + */ +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) +{ + uint32_t i = 0; + + /* Fill Remote Wake-up Frame Filter register with Buffer data */ + for(i =0; iMACRWUFFR = Buffer[i]; + } +} + +/** + * @brief Enables or disables any unicast packet filtered by the MAC + * (DAF) address recognition to be a wake-up frame. + * @param NewState: new state of the MAC Global Unicast Wake-Up. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; + } + else + { + /* Disable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; + } +} + +/** + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * @param ETH_PMT_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset + * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPR : Magic Packet Received + * @retval : The new state of ETHERNET PMT Flag (SET or RESET). + */ +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG)); + + if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the MAC Wake-Up Frame Detection. + * @param NewState: new state of the MAC Wake-Up Frame Detection. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; + } + else + { + /* Disable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + } +} + +/** + * @brief Enables or disables the MAC Magic Packet Detection. + * @param NewState: new state of the MAC Magic Packet Detection. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MagicPacketDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Magic Packet Detection */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; + } + else + { + /* Disable the MAC Magic Packet Detection */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + } +} + +/** + * @brief Enables or disables the MAC Power Down. + * @param NewState: new state of the MAC Power Down. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_PowerDownCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Power Down */ + /* This puts the MAC in power down mode */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; + } + else + { + /* Disable the MAC Power Down */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; + } +} + +/*--------------------------------- MMC ------------------------------------*/ +/** + * @brief Enables or disables the MMC Counter Freeze. + * @param NewState: new state of the MMC Counter Freeze. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MMC Counter Freeze */ + ETH->MMCCR |= ETH_MMCCR_MCF; + } + else + { + /* Disable the MMC Counter Freeze */ + ETH->MMCCR &= ~ETH_MMCCR_MCF; + } +} + +/** + * @brief Enables or disables the MMC Reset On Read. + * @param NewState: new state of the MMC Reset On Read. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCResetOnReadCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MMC Counter reset on read */ + ETH->MMCCR |= ETH_MMCCR_ROR; + } + else + { + /* Disable the MMC Counter reset on read */ + ETH->MMCCR &= ~ETH_MMCCR_ROR; + } +} + +/** + * @brief Enables or disables the MMC Counter Stop Rollover. + * @param NewState: new state of the MMC Counter Stop Rollover. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCCounterRolloverCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Disable the MMC Counter Stop Rollover */ + ETH->MMCCR &= ~ETH_MMCCR_CSR; + } + else + { + /* Enable the MMC Counter Stop Rollover */ + ETH->MMCCR |= ETH_MMCCR_CSR; + } +} + +/** + * @brief Resets the MMC Counters. + * @param None + * @retval : None + */ +void ETH_MMCCountersReset(void) +{ + /* Resets the MMC Counters */ + ETH->MMCCR |= ETH_MMCCR_CR; +} + +/** + * @brief Enables or disables the specified ETHERNET MMC interrupts. + * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt + * sources to be enabled or disabled. + * This parameter can be any combination of Tx interrupt or + * any combination of Rx interrupt (but not both)of the following values: + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value + * @param NewState: new state of the specified ETHERNET MMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + /* Remove egister mak from IT */ + ETH_MMC_IT &= 0xEFFFFFFF; + + /* ETHERNET MMC Rx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCRIMR |= ETH_MMC_IT; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCTIMR |= ETH_MMC_IT; + } + } +} + +/** + * @brief Checks whether the specified ETHERNET MMC IT is set or not. + * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value + * @retval : The value of ETHERNET MMC IT (SET or RESET). + */ +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); + + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + /* ETHERNET MMC Rx interrupts selected */ + /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ + if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ + if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/** + * @brief Get the specified ETHERNET MMC register value. + * @param ETH_MMCReg: specifies the ETHERNET MMC register. + * This parameter can be one of the following values: + * @arg ETH_MMCCR : MMC CR register + * @arg ETH_MMCRIR : MMC RIR register + * @arg ETH_MMCTIR : MMC TIR register + * @arg ETH_MMCRIMR : MMC RIMR register + * @arg ETH_MMCTIMR : MMC TIMR register + * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register + * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register + * @arg ETH_MMCTGFCR : MMC TGFCR register + * @arg ETH_MMCRFCECR : MMC RFCECR register + * @arg ETH_MMCRFAECR : MMC RFAECR register + * @arg ETH_MMCRGUFCR : MMC RGUFCRregister + * @retval : The value of ETHERNET MMC Register value. + */ +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) +{ + /* Check the parameters */ + assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg)); + + /* Return the selected register value */ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); +} +/*--------------------------------- PTP ------------------------------------*/ + +/** + * @brief Updated the PTP block for fine correction with the Time Stamp + * Addend register value. + * @param None + * @retval : None + */ +void ETH_EnablePTPTimeStampAddend(void) +{ + /* Enable the PTP block update with the Time Stamp Addend register value */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; +} + +/** + * @brief Enable the PTP Time Stamp interrupt trigger + * @param None + * @retval : None + */ +void ETH_EnablePTPTimeStampInterruptTrigger(void) +{ + /* Enable the PTP target time interrupt */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; +} + +/** + * @brief Updated the PTP system time with the Time Stamp Update register + * value. + * @param None + * @retval : None + */ +void ETH_EnablePTPTimeStampUpdate(void) +{ + /* Enable the PTP system time update with the Time Stamp Update register value */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; +} + +/** + * @brief Initialize the PTP Time Stamp + * @param None + * @retval : None + */ +void ETH_InitializePTPTimeStamp(void) +{ + /* Initialize the PTP Time Stamp */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; +} + +/** + * @brief Selects the PTP Update method + * @param UpdateMethod: the PTP Update method + * This parameter can be one of the following values: + * @arg ETH_PTP_FineUpdate : Fine Update method + * @arg ETH_PTP_CoarseUpdate : Coarse Update method + * @retval : None + */ +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_UPDATE(UpdateMethod)); + + if (UpdateMethod != ETH_PTP_CoarseUpdate) + { + /* Enable the PTP Fine Update method */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; + } + else + { + /* Disable the PTP Coarse Update method */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); + } +} + +/** + * @brief Enables or disables the PTP time stamp for transmit and receive frames. + * @param NewState: new state of the PTP time stamp for transmit and receive frames + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_PTPTimeStampCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSE; + } + else + { + /* Disable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); + } +} + +/** + * @brief Checks whether the specified ETHERNET PTP flag is set or not. + * @param ETH_PTP_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PTP_FLAG_TSARU : Addend Register Update + * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable + * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update + * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize + * @retval : The new state of ETHERNET PTP Flag (SET or RESET). + */ +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG)); + + if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Sets the system time Sub-Second Increment value. + * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value. + * @retval : None + */ +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue)); + /* Set the PTP Sub-Second Increment Register */ + ETH->PTPSSIR = SubSecondValue; +} + +/** + * @brief Sets the Time Stamp update sign and values. + * @param Sign: specifies the PTP Time update value sign. + * This parameter can be one of the following values: + * @arg ETH_PTP_PositiveTime : positive time value. + * @arg ETH_PTP_NegativeTime : negative time value. + * @param SecondValue: specifies the PTP Time update second value. + * @param SubSecondValue: specifies the PTP Time update sub-second value. + * this is a 31 bit value. bit32 correspond to the sign. + * @retval : None + */ +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); + assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); + /* Set the PTP Time Update High Register */ + ETH->PTPTSHUR = SecondValue; + + /* Set the PTP Time Update Low Register with sign */ + ETH->PTPTSLUR = Sign | SubSecondValue; +} + +/** + * @brief Sets the Time Stamp Addend value. + * @param Value: specifies the PTP Time Stamp Addend Register value. + * @retval : None + */ +void ETH_SetPTPTimeStampAddend(uint32_t Value) +{ + /* Set the PTP Time Stamp Addend Register */ + ETH->PTPTSAR = Value; +} + +/** + * @brief Sets the Target Time registers values. + * @param HighValue: specifies the PTP Target Time High Register value. + * @param LowValue: specifies the PTP Target Time Low Register value. + * @retval : None + */ +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) +{ + /* Set the PTP Target Time High Register */ + ETH->PTPTTHR = HighValue; + /* Set the PTP Target Time Low Register */ + ETH->PTPTTLR = LowValue; +} + +/** + * @brief Get the specified ETHERNET PTP register value. + * @param ETH_PTPReg: specifies the ETHERNET PTP register. + * This parameter can be one of the following values: + * @arg ETH_PTPTSCR : Sub-Second Increment Register + * @arg ETH_PTPSSIR : Sub-Second Increment Register + * @arg ETH_PTPTSHR : Time Stamp High Register + * @arg ETH_PTPTSLR : Time Stamp Low Register + * @arg ETH_PTPTSHUR : Time Stamp High Update Register + * @arg ETH_PTPTSLUR : Time Stamp Low Update Register + * @arg ETH_PTPTSAR : Time Stamp Addend Register + * @arg ETH_PTPTTHR : Target Time High Register + * @arg ETH_PTPTTLR : Target Time Low Register + * @retval : The value of ETHERNET PTP Register value. + */ +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg)); + + /* Return the selected register value */ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); +} + +/** + * @brief Initializes the DMA Tx descriptors in chain mode with PTP. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list + * @param TxBuff: Pointer on the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval : None + */ +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + DMAPTPTxDescToSet = DMAPTPTxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab+i; + /* Set Second Address Chained bit and enable PTP */ + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } + /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */ + (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; + (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; + } + /* Store on the last DMAPTPTxDescTab desc status record the first list address */ + (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab; + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list + * @param RxBuff: Pointer on the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval : None + */ +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */ + (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; + (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; + } + /* Store on the last DMAPTPRxDescTab desc status record the first list address */ + (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab; + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Transmits a packet, from application buffer, pointed by ppkt with + * Time Stamp values. + * @param ppkt: pointer to application packet buffer to transmit. + * @param FrameLength: Tx Packet size. + * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values. + * @retval : ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission + */ +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) +{ + uint32_t offset = 0, timeout = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); + } + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + /* Wait for ETH_DMATxDesc_TTSS flag to be set */ + do + { + timeout++; + } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Clear the DMATxDescToSet status register TTSS flag */ + DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; + *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; + *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; + /* Update the ENET DMA current descriptor */ + /* Chained Mode */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr); + if(DMAPTPTxDescToSet->Status != 0) + { + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status); + } + else + { + DMAPTPTxDescToSet++; + } + } + else /* Ring Mode */ + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read: this will + be the first Tx descriptor in this case */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Receives a packet and copies it to memory pointed by ppkt with + * Time Stamp values. + * @param ppkt: pointer to application packet receive buffer. + * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values. + * @retval : ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct + */ +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) +{ + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ENET or CPU */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + } + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; + *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr); + if(DMAPTPRxDescToGet->Status != 0) + { + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status); + } + else + { + DMAPTPRxDescToGet++; + } + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return Frame Length/ERROR */ + return (framelength); +} +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/clock-arch.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/clock-arch.c new file mode 100644 index 00000000..1e213136 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/clock-arch.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.c,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * Implementation of architecture-specific clock functionality + * \author + * Adam Dunkels + */ + +#include "clock-arch.h" +#include "boot.h" + +/*---------------------------------------------------------------------------*/ +clock_time_t +clock_time(void) +{ + return (clock_time_t)TimerGet(); +} +/*---------------------------------------------------------------------------*/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/clock-arch.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/clock-arch.h new file mode 100644 index 00000000..aa97f0e7 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/clock-arch.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +typedef int clock_time_t; +#define CLOCK_CONF_SECOND 1000 + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/netdev.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/netdev.c new file mode 100644 index 00000000..09d0d2a7 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/netdev.c @@ -0,0 +1,451 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Author: Adam Dunkels + * + * $Id: netdev.c,v 1.8 2006/06/07 08:39:58 adam Exp $ + */ + + +/*---------------------------------------------------------------------------*/ +#include "uip.h" +#include "uip_arp.h" +#include "boot.h" +#include "stm32f4xx.h" /* STM32 registers */ +#include "stm32f4xx_conf.h" /* STM32 peripheral drivers */ +#include "stm32_eth.h" /* STM32 ethernet library */ +#include /* for memcpy */ + + +/*---------------------------------------------------------------------------*/ +#define NETDEV_DEFAULT_MACADDR0 (0x08) +#define NETDEV_DEFAULT_MACADDR1 (0x00) +#define NETDEV_DEFAULT_MACADDR2 (0x27) +#define NETDEV_DEFAULT_MACADDR3 (0x69) +#define NETDEV_DEFAULT_MACADDR4 (0x5B) +#define NETDEV_DEFAULT_MACADDR5 (0x45) + + +/*---------------------------------------------------------------------------*/ +static void netdev_TxDscrInit(void); +static void netdev_RxDscrInit(void); + +/*---------------------------------------------------------------------------*/ +typedef union _TranDesc0_t +{ + uint32_t Data; + struct { + uint32_t DB : 1; + uint32_t UF : 1; + uint32_t ED : 1; + uint32_t CC : 4; + uint32_t VF : 1; + uint32_t EC : 1; + uint32_t LC : 1; + uint32_t NC : 1; + uint32_t LSC : 1; + uint32_t IPE : 1; + uint32_t FF : 1; + uint32_t JT : 1; + uint32_t ES : 1; + uint32_t IHE : 1; + uint32_t : 3; + uint32_t TCH : 1; + uint32_t TER : 1; + uint32_t CIC : 2; + uint32_t : 2; + uint32_t DP : 1; + uint32_t DC : 1; + uint32_t FS : 1; + uint32_t LSEG : 1; + uint32_t IC : 1; + uint32_t OWN : 1; + }; +} TranDesc0_t, * pTranDesc0_t; + +typedef union _TranDesc1_t +{ + uint32_t Data; + struct { + uint32_t TBS1 :13; + uint32_t : 3; + uint32_t TBS2 :12; + uint32_t : 3; + }; +} TranDesc1_t, * pTranDesc1_t; + +typedef union _RecDesc0_t +{ + uint32_t Data; + struct { + uint32_t RMAM_PCE : 1; + uint32_t CE : 1; + uint32_t DE : 1; + uint32_t RE : 1; + uint32_t RWT : 1; + uint32_t FT : 1; + uint32_t LC : 1; + uint32_t IPHCE : 1; + uint32_t LS : 1; + uint32_t FS : 1; + uint32_t VLAN : 1; + uint32_t OE : 1; + uint32_t LE : 1; + uint32_t SAF : 1; + uint32_t DERR : 1; + uint32_t ES : 1; + uint32_t FL :14; + uint32_t AFM : 1; + uint32_t OWN : 1; + }; +} RecDesc0_t, * pRecDesc0_t; + +typedef union _recDesc1_t +{ + uint32_t Data; + struct { + uint32_t RBS1 :13; + uint32_t : 1; + uint32_t RCH : 1; + uint32_t RER : 1; + uint32_t RBS2 :14; + uint32_t DIC : 1; + }; +} RecDesc1_t, * pRecDesc1_t; + +typedef union _EnetDmaDesc_t +{ + uint32_t Data[4]; + // Rx DMA descriptor + struct + { + RecDesc0_t RxDesc0; + RecDesc1_t RxDesc1; + uint32_t * pBuffer; + union + { + uint32_t * pBuffer2; + union _EnetDmaDesc_t * pEnetDmaNextDesc; + }; + } Rx; + // Tx DMA descriptor + struct + { + TranDesc0_t TxDesc0; + TranDesc1_t TxDesc1; + uint32_t * pBuffer1; + union + { + uint32_t * pBuffer2; + union _EnetDmaDesc_t * pEnetDmaNextDesc; + }; + } Tx; +} EnetDmaDesc_t, * pEnetDmaDesc_t; + + +/*---------------------------------------------------------------------------*/ +uint8_t RxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4))); +uint8_t TxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4))); + +EnetDmaDesc_t EnetDmaRx __attribute__((aligned (128))); +EnetDmaDesc_t EnetDmaTx __attribute__ ((aligned (128))); + + +/*---------------------------------------------------------------------------*/ +void netdev_init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + ETH_InitTypeDef ETH_InitStructure; + + /* Enable ETHERNET clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx | + RCC_AHB1Periph_ETH_MAC_Rx | RCC_AHB1Periph_ETH_MAC_PTP, ENABLE); + + + /* Enable GPIOs clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | + RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG, ENABLE); + + /* Enable SYSCFG clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + /*Select RMII Interface*/ + SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII); + + /* ETHERNET pins configuration */ + /* PA + ETH_RMII_REF_CLK: PA1 + ETH_RMII_MDIO: PA2 + ETH_RMII_MDINT: PA3 + ETH_RMII_CRS_DV: PA7 + */ + + /* Configure PA1, PA2, PA3 and PA7*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_7; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Connect PA1, PA2, PA3 and PA7 to ethernet module*/ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH); + + /* PB + ETH_RMII_TX_EN: PG11 + */ + + /* Configure PG11*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* Connect PG11 to ethernet module*/ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH); + + /* PC + ETH_RMII_MDC: PC1 + ETH_RMII_RXD0: PC4 + ETH_RMII_RXD1: PC5 + */ + + /* Configure PC1, PC4 and PC5*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Connect PC1, PC4 and PC5 to ethernet module*/ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH); + + /* PG + ETH_RMII_TXD0: PG13 + ETH_RMII_TXD1: PG14 + */ + + /* Configure PG13 and PG14*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* Connect PG13 and PG14 to ethernet module*/ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH); + + /* Reset ETHERNET on AHB Bus */ + ETH_DeInit(); + + /* Software reset */ + ETH_SoftwareReset(); + + /* Wait for software reset */ + while(ETH_GetSoftwareResetStatus()==SET); + + /* ETHERNET Configuration ------------------------------------------------------*/ + /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */ + ETH_StructInit(Ð_InitStructure); + + /* Fill ETH_InitStructure parametrs */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable ; + ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; + ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable; + ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; + ETH_InitStructure.ETH_Speed = ETH_Speed_100M; + + unsigned int PhyAddr; + union { + uint32_t HI_LO; + struct + { + uint16_t LO; + uint16_t HI; + }; + } PHYID; + for(PhyAddr = 0; 32 > PhyAddr; PhyAddr++) + { + // datasheet for the ks8721bl ethernet controller (http://www.micrel.com/_PDF/Ethernet/datasheets/ks8721bl-sl.pdf) + // page 20 --> PHY Identifier 1 and 2 + PHYID.HI = ETH_ReadPHYRegister(PhyAddr,2); // 0x0022 + PHYID.LO = ETH_ReadPHYRegister(PhyAddr,3); // 0x1619 + if ((0x00221619 == PHYID.HI_LO) || (0x0007C0F1 == PHYID.HI_LO)) + break; + } + if (32 < PhyAddr) + { + ASSERT_RT(BLT_FALSE); + } + /* Configure Ethernet */ + if(0 == ETH_Init(Ð_InitStructure, PhyAddr)) + { + ASSERT_RT(BLT_FALSE); + } + + netdev_TxDscrInit(); + netdev_RxDscrInit(); + ETH_Start(); +} + + +/*---------------------------------------------------------------------------*/ +void netdev_init_mac(void) +{ + struct uip_eth_addr macAddress; + + /* set the default MAC address */ + macAddress.addr[0] = NETDEV_DEFAULT_MACADDR0; + macAddress.addr[1] = NETDEV_DEFAULT_MACADDR1; + macAddress.addr[2] = NETDEV_DEFAULT_MACADDR2; + macAddress.addr[3] = NETDEV_DEFAULT_MACADDR3; + macAddress.addr[4] = NETDEV_DEFAULT_MACADDR4; + macAddress.addr[5] = NETDEV_DEFAULT_MACADDR5; + uip_setethaddr(macAddress); +} + + +/*---------------------------------------------------------------------------*/ +unsigned int netdev_read(void) +{ + uint32_t size; + /*check for validity*/ + if(0 == EnetDmaRx.Rx.RxDesc0.OWN) + { + /*Get the size of the packet*/ + size = EnetDmaRx.Rx.RxDesc0.FL; // CRC + memcpy(uip_buf, RxBuff, size); //string.h library*/ + } + else + { + return 0; + } + /* Give the buffer back to ENET */ + EnetDmaRx.Rx.RxDesc0.OWN = 1; + /* Start the receive operation */ + ETH->DMARPDR = 1; + /* Return no error */ + return size; +} + + +/*---------------------------------------------------------------------------*/ +void netdev_send(void) +{ + while(EnetDmaTx.Tx.TxDesc0.OWN); + + /* Copy the application buffer to the driver buffer + Using this MEMCOPY_L2L_BY4 makes the copy routine faster + than memcpy */ + memcpy(TxBuff, uip_buf, uip_len); + + /* Assign ENET address to Temp Tx Array */ + EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff; + + /* Setting the Frame Length*/ + EnetDmaTx.Tx.TxDesc0.Data = 0; + EnetDmaTx.Tx.TxDesc0.TCH = 1; + EnetDmaTx.Tx.TxDesc0.LSEG = 1; + EnetDmaTx.Tx.TxDesc0.FS = 1; + EnetDmaTx.Tx.TxDesc0.DC = 0; + EnetDmaTx.Tx.TxDesc0.DP = 0; + + EnetDmaTx.Tx.TxDesc1.Data = 0; + EnetDmaTx.Tx.TxDesc1.TBS1 = (uip_len&0xFFF); + + /* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/ + EnetDmaTx.Tx.TxDesc0.OWN = 1; + + /* Start the transmit operation */ + ETH->DMATPDR = 1; +} + + +/*---------------------------------------------------------------------------*/ +static void netdev_RxDscrInit(void) +{ + /* Initialization */ + /* Assign temp Rx array to the ENET buffer */ + EnetDmaRx.Rx.pBuffer = (uint32_t *)RxBuff; + + /* Initialize RX ENET Status and control */ + EnetDmaRx.Rx.RxDesc0.Data = 0; + + /* Initialize the next descriptor- In our case its single descriptor */ + EnetDmaRx.Rx.pEnetDmaNextDesc = &EnetDmaRx; + + EnetDmaRx.Rx.RxDesc1.Data = 0; + EnetDmaRx.Rx.RxDesc1.RER = 0; // end of ring + EnetDmaRx.Rx.RxDesc1.RCH = 1; // end of ring + + /* Set the max packet size */ + EnetDmaRx.Rx.RxDesc1.RBS1 = UIP_CONF_BUFFER_SIZE; + + /* Setting the VALID bit */ + EnetDmaRx.Rx.RxDesc0.OWN = 1; + /* Setting the RX NEXT Descriptor Register inside the ENET */ + ETH->DMARDLAR = (uint32_t)&EnetDmaRx; +} + + +/*---------------------------------------------------------------------------*/ +static void netdev_TxDscrInit(void) +{ + /* ENET Start Address */ + EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff; + + /* Next Descriptor Address */ + EnetDmaTx.Tx.pEnetDmaNextDesc = &EnetDmaTx; + + /* Initialize ENET status and control */ + EnetDmaTx.Tx.TxDesc0.TCH = 1; + EnetDmaTx.Tx.TxDesc0.Data = 0; + EnetDmaTx.Tx.TxDesc1.Data = 0; + /* Tx next set to Tx descriptor base */ + ETH->DMATDLAR = (uint32_t)&EnetDmaTx; + +} diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/netdev.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/netdev.h new file mode 100644 index 00000000..4ea59ce5 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/netdev.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Adam Dunkels. + * 4. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: netdev.h,v 1.1 2002/01/10 06:22:56 adam Exp $ + * + */ + +#ifndef __NETDEV_H__ +#define __NETDEV_H__ + +void netdev_init(void); +void netdev_init_mac(void); +unsigned int netdev_read(void); +void netdev_send(void); + +#endif /* __NETDEV_H__ */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/uip-conf.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/uip-conf.h new file mode 100644 index 00000000..fd9ba0dd --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/lib/uip/uip-conf.h @@ -0,0 +1,151 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef unsigned char u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef unsigned short u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 1 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 1 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1600 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 0 + +/* Here we include the header file for the application(s) we use in + our project. */ +#include "boot.h" +#include "net.h" + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/makefile b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/makefile index 98c6698f..c489cc5a 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/makefile +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Boot/makefile @@ -40,6 +40,13 @@ hooks.c \ main.c \ ./lib/fatfs/ffconf.h \ ./lib/fatfs/mmc.c \ +./lib/ethernetlib/inc/stm32_eth.h \ +./lib/ethernetlib/src/stm32_eth.c \ +./lib/uip/clock-arch.c \ +./lib/uip/clock-arch.h \ +./lib/uip/netdev.c \ +./lib/uip/netdev.h \ +./lib/uip/uip-conf.h \ ./lib/stdperiphlib/stm32f4xx_conf.h \ ./lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/misc.h \ ./lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h \ @@ -110,10 +117,30 @@ main.c \ ../../../Source/third_party/fatfs/src/ff.h \ ../../../Source/third_party/fatfs/src/integer.h \ ../../../Source/third_party/fatfs/src/option/unicode.c \ +../../../Source/third_party/uip/uip/clock.h \ +../../../Source/third_party/uip/uip/lc-addrlabels.h \ +../../../Source/third_party/uip/uip/lc-switch.h \ +../../../Source/third_party/uip/uip/lc.h \ +../../../Source/third_party/uip/uip/pt.h \ +../../../Source/third_party/uip/uip/uip-fw.h \ +../../../Source/third_party/uip/uip/uip-neighbor.h \ +../../../Source/third_party/uip/uip/uip-split.h \ +../../../Source/third_party/uip/uip/uip.c \ +../../../Source/third_party/uip/uip/uip.h \ +../../../Source/third_party/uip/uip/uip_arch.h \ +../../../Source/third_party/uip/uip/uip_arp.c \ +../../../Source/third_party/uip/uip/uip_arp.h \ +../../../Source/third_party/uip/uip/uip_timer.c \ +../../../Source/third_party/uip/uip/uip_timer.h \ +../../../Source/third_party/uip/uip/uiplib.c \ +../../../Source/third_party/uip/uip/uiplib.h \ +../../../Source/third_party/uip/uip/uipopt.h \ ../../../Source/boot.c \ ../../../Source/boot.h \ ../../../Source/com.c \ ../../../Source/com.h \ +../../../Source/net.c \ +../../../Source/net.h \ ../../../Source/xcp.c \ ../../../Source/xcp.h \ ../../../Source/backdoor.c \ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/bin/demoprog_olimex_stm32e407.elf b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/bin/demoprog_olimex_stm32e407.elf index ad51dacc..ba11bbf0 100644 Binary files a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/bin/demoprog_olimex_stm32e407.elf and b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/bin/demoprog_olimex_stm32e407.elf differ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/bin/demoprog_olimex_stm32e407.map b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/bin/demoprog_olimex_stm32e407.map index fa8b24c2..7351c25c 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/bin/demoprog_olimex_stm32e407.map +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/bin/demoprog_olimex_stm32e407.map @@ -3,47 +3,49 @@ bin/demoprog_olimex_stm32e407.elf: file format elf32-littlearm bin/demoprog_olimex_stm32e407.elf architecture: arm, flags 0x00000112: EXEC_P, HAS_SYMS, D_PAGED -start address 0x08008000 +start address 0x0800c000 Program Header: - LOAD off 0x00008000 vaddr 0x08008000 paddr 0x08008000 align 2**15 - filesz 0x00000e70 memsz 0x00000e70 flags r-x - LOAD off 0x00010000 vaddr 0x20000000 paddr 0x08008e70 align 2**15 - filesz 0x00000014 memsz 0x00000868 flags rw- + LOAD off 0x00000000 vaddr 0x08008000 paddr 0x08008000 align 2**15 + filesz 0x00007128 memsz 0x00007128 flags r-x + LOAD off 0x00008000 vaddr 0x20000000 paddr 0x0800f128 align 2**15 + filesz 0x00000014 memsz 0x00000014 flags rw- + LOAD off 0x00008080 vaddr 0x20000080 paddr 0x0800f200 align 2**15 + filesz 0x00000000 memsz 0x00001c9c flags rw- private flags = 5000202: [Version5 EABI] [soft-float ABI] [has entry point] Sections: Idx Name Size VMA LMA File off Algn - 0 .text 00000e70 08008000 08008000 00008000 2**2 + 0 .text 00003128 0800c000 0800c000 00004000 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE - 1 .data 00000014 20000000 08008e70 00010000 2**2 + 1 .data 00000014 20000000 0800f128 00008000 2**2 CONTENTS, ALLOC, LOAD, DATA - 2 .bss 00000854 20000014 08008e84 00010014 2**2 + 2 .bss 00001c9c 20000080 0800f200 00008080 2**7 ALLOC - 3 .debug_info 00004f05 00000000 00000000 00010014 2**0 + 3 .debug_info 00009528 00000000 00000000 00008014 2**0 CONTENTS, READONLY, DEBUGGING - 4 .debug_abbrev 00001212 00000000 00000000 00014f19 2**0 + 4 .debug_abbrev 00001e7d 00000000 00000000 0001153c 2**0 CONTENTS, READONLY, DEBUGGING - 5 .debug_loc 000023a4 00000000 00000000 0001612b 2**0 + 5 .debug_loc 00003ba9 00000000 00000000 000133b9 2**0 CONTENTS, READONLY, DEBUGGING - 6 .debug_aranges 00000538 00000000 00000000 000184cf 2**0 + 6 .debug_aranges 000009f8 00000000 00000000 00016f62 2**0 CONTENTS, READONLY, DEBUGGING - 7 .debug_ranges 00000478 00000000 00000000 00018a07 2**0 + 7 .debug_ranges 000008d8 00000000 00000000 0001795a 2**0 CONTENTS, READONLY, DEBUGGING - 8 .debug_line 00001b4c 00000000 00000000 00018e7f 2**0 + 8 .debug_line 0000321a 00000000 00000000 00018232 2**0 CONTENTS, READONLY, DEBUGGING - 9 .debug_str 00001e2c 00000000 00000000 0001a9cb 2**0 + 9 .debug_str 000038bb 00000000 00000000 0001b44c 2**0 CONTENTS, READONLY, DEBUGGING - 10 .comment 00000030 00000000 00000000 0001c7f7 2**0 + 10 .comment 00000030 00000000 00000000 0001ed07 2**0 CONTENTS, READONLY - 11 .ARM.attributes 00000033 00000000 00000000 0001c827 2**0 + 11 .ARM.attributes 00000033 00000000 00000000 0001ed37 2**0 CONTENTS, READONLY - 12 .debug_frame 000009d0 00000000 00000000 0001c85c 2**2 + 12 .debug_frame 000014a4 00000000 00000000 0001ed6c 2**2 CONTENTS, READONLY, DEBUGGING SYMBOL TABLE: -08008000 l d .text 00000000 .text +0800c000 l d .text 00000000 .text 20000000 l d .data 00000000 .data -20000014 l d .bss 00000000 .bss +20000080 l d .bss 00000000 .bss 00000000 l d .debug_info 00000000 .debug_info 00000000 l d .debug_abbrev 00000000 .debug_abbrev 00000000 l d .debug_loc 00000000 .debug_loc @@ -56,68 +58,148 @@ SYMBOL TABLE: 00000000 l d .debug_frame 00000000 .debug_frame 00000000 l df *ABS* 00000000 vectors.c 00000000 l df *ABS* 00000000 boot.c -0800818c l F .text 00000022 NVIC_SystemReset -080081b0 l F .text 00000038 UartReceiveByte -20000014 l O .bss 00000041 xcpCtoReqPacket.7486 -20000058 l O .bss 00000001 xcpCtoRxLength.7487 -20000059 l O .bss 00000001 xcpCtoRxInProgress.7488 -08008e4c l O .text 00000024 canTiming +0800c18c l F .text 00000022 NVIC_SystemReset +0800c1b0 l F .text 00000038 UartReceiveByte +20000080 l O .bss 00000041 xcpCtoReqPacket.7497 +200000c4 l O .bss 00000001 xcpCtoRxLength.7498 +200000c5 l O .bss 00000001 xcpCtoRxInProgress.7499 +0800f0fc l O .text 00000024 canTiming 00000000 l df *ABS* 00000000 cstart.c -08008518 l F .text 00000000 zero_loop +0800c524 l F .text 00000000 zero_loop 00000000 l df *ABS* 00000000 irq.c 00000000 l df *ABS* 00000000 led.c -2000005c l O .bss 00000004 timer_counter_last.7467 -20000060 l O .bss 00000001 led_toggle_state.7466 +200000c8 l O .bss 00000004 timer_counter_last.7478 +200000cc l O .bss 00000001 led_toggle_state.7477 +00000000 l df *ABS* 00000000 net.c +200000d0 l O .bss 00000004 ARPTimerTimeOut +200000d4 l O .bss 00000004 periodicTimerTimeOut 00000000 l df *ABS* 00000000 main.c 00000000 l df *ABS* 00000000 timer.c -20000064 l O .bss 00000004 millisecond_counter +200000d8 l O .bss 00000004 millisecond_counter +00000000 l df *ABS* 00000000 stm32_eth.c +00000000 l df *ABS* 00000000 netdev.c 00000000 l df *ABS* 00000000 stm32f4xx_can.c 00000000 l df *ABS* 00000000 stm32f4xx_gpio.c 00000000 l df *ABS* 00000000 stm32f4xx_rcc.c 20000000 l O .data 00000010 APBAHBPrescTable +00000000 l df *ABS* 00000000 stm32f4xx_syscfg.c 00000000 l df *ABS* 00000000 stm32f4xx_usart.c 00000000 l df *ABS* 00000000 system_stm32f4xx.c +00000000 l df *ABS* 00000000 uip.c +0800d96c l F .text 0000004c chksum +0800d9b8 l F .text 00000046 upper_layer_chksum +0800da80 l F .text 00000036 uip_add_rcv_nxt +200000dc l O .bss 00000002 tmp16 +200000de l O .bss 00000002 ipid +200000e0 l O .bss 00000004 iss +200000e4 l O .bss 00000002 lastport +200000f0 l O .bss 00000001 c +200000f1 l O .bss 00000001 opt +00000000 l df *ABS* 00000000 uip_arp.c +0800eb2c l F .text 00000116 uip_arp_update +200000f2 l O .bss 00000001 i +200000f3 l O .bss 00000001 tmpage +200000f4 l O .bss 00000060 arp_table +0800f120 l O .text 00000006 broadcast_ethaddr +20000154 l O .bss 00000001 c +20000155 l O .bss 00000001 arptime +20000158 l O .bss 00000004 ipaddr +00000000 l df *ABS* 00000000 memcpy-stub.c +00000000 l df *ABS* 00000000 memset.c 00000000 l df *ABS* 00000000 00000800 l *ABS* 00000000 __STACKSIZE__ -080084d4 g F .text 00000060 reset_handler -08008a90 g F .text 00000028 GPIO_PinAFConfig -08008800 g F .text 00000126 CAN_FilterInit -08008540 g F .text 00000004 IrqInterruptEnable -08008d2c g F .text 0000000c USART_GetFlagStatus -08008e70 g .text 00000000 _etext -080086bc g F .text 00000010 TimerISRHandler +0800ce0c g F .text 00000012 ETH_FlushTransmitFIFO +0800c4e0 g F .text 00000060 reset_handler +0800d580 g F .text 00000028 GPIO_PinAFConfig +0800c930 g F .text 0000009e ETH_StructInit +0800d2f0 g F .text 00000126 CAN_FilterInit +0800c54c g F .text 00000004 IrqInterruptEnable +0800caa8 g F .text 000002f0 ETH_Init +20000e90 g O .bss 00000002 uip_len +200000e8 g O .bss 00000006 uip_ethaddr +0800da00 g F .text 0000007e uip_add32 +0800d6f0 g F .text 00000024 RCC_AHB1PeriphResetCmd +0800d84c g F .text 0000000c USART_GetFlagStatus +0800f128 g .text 00000000 _etext +0800d100 g F .text 00000056 netdev_read +0800db5c g F .text 00000fc4 uip_process +0800c900 g F .text 00000010 TimerISRHandler +0800c914 g F .text 0000001c ETH_DeInit +0800efb4 g F .text 000000a6 memcpy +20000e94 g O .bss 00000004 uip_sappdata +0800ceb0 g F .text 0000022a netdev_init +20000e98 g O .bss 00000004 uip_acc32 +0800dab8 g F .text 0000002c uip_ipchksum 20000010 g O .data 00000004 SystemCoreClock -08008d24 g F .text 00000008 USART_ReceiveData -08008bdc g F .text 00000024 RCC_APB2PeriphClockCmd -080089f8 g F .text 00000090 GPIO_Init -08008d08 g F .text 0000001c USART_Cmd -08008bb8 g F .text 00000024 RCC_APB1PeriphClockCmd -080086d0 g F .text 00000042 CAN_DeInit -20000068 g .bss 00000000 _ebss -080086cc g F .text 00000002 UnusedISR -08008544 g F .text 00000056 LedInit -08008a88 g F .text 00000004 GPIO_SetBits -08008ab8 g F .text 000000da RCC_GetClocksFreq -08008c24 g F .text 000000e4 USART_Init -08008948 g F .text 00000096 CAN_Receive -08008714 g F .text 000000ea CAN_Init -20000014 g .bss 00000000 _bss -08008928 g F .text 00000020 CAN_StructInit -08008a8c g F .text 00000004 GPIO_ResetBits -0800861c g F .text 0000004a main -080089e0 g F .text 00000018 CAN_MessagePending -080081e8 g F .text 000001e8 BootComInit -08008d38 g F .text 00000112 SystemInit -08008c00 g F .text 00000024 RCC_APB1PeriphResetCmd +0800d844 g F .text 00000008 USART_ReceiveData +0800d6cc g F .text 00000024 RCC_APB2PeriphClockCmd +0800d4e8 g F .text 00000090 GPIO_Init +0800db28 g F .text 00000032 uip_listen +0800d828 g F .text 0000001c USART_Cmd +0800d158 g F .text 00000066 netdev_send +0800d6a8 g F .text 00000024 RCC_APB1PeriphClockCmd +20000e9c g O .bss 00000001 uip_flags +20000180 g O .bss 00000010 EnetDmaRx +0800d1c0 g F .text 00000042 CAN_DeInit +0800cd98 g F .text 00000026 ETH_MACTransmissionCmd +0800c4d4 g F .text 0000000c BootActivate +2000151c g .bss 00000000 _ebss +0800c910 g F .text 00000002 UnusedISR +0800c550 g F .text 00000056 LedInit +0800d578 g F .text 00000004 GPIO_SetBits +0800c6f0 g F .text 0000015c NetTask +0800cde8 g F .text 00000012 ETH_SoftwareReset +0800ca40 g F .text 00000068 ETH_WritePHYRegister +0800d5a8 g F .text 000000da RCC_GetClocksFreq +0800d0dc g F .text 00000022 netdev_init_mac +0800d744 g F .text 000000e4 USART_Init +0800d438 g F .text 00000096 CAN_Receive +0800d204 g F .text 000000ea CAN_Init +20000080 g .bss 00000000 _bss +0800d418 g F .text 00000020 CAN_StructInit +0800dae4 g F .text 00000010 uip_tcpchksum +0800ce48 g F .text 00000026 ETH_DMAReceptionCmd +20000ea0 g O .bss 00000004 uip_appdata +0800d57c g F .text 00000004 GPIO_ResetBits +20000ea4 g O .bss 00000004 uip_conn +0800cdfc g F .text 00000010 ETH_GetSoftwareResetStatus +0800c9d0 g F .text 0000006e ETH_ReadPHYRegister +20000ea8 g O .bss 0000001e uip_conns +0800eddc g F .text 000001d6 uip_arp_out +0800f05c g F .text 0000009e memset +0800c84c g F .text 0000005e main +0800d4d0 g F .text 00000018 CAN_MessagePending +0800c1e8 g F .text 000001e8 BootComInit +0800d858 g F .text 00000112 SystemInit +0800d738 g F .text 0000000a SYSCFG_ETH_MediaInterfaceConfig +0800ec9c g F .text 00000140 uip_arp_arpin +0800ec44 g F .text 00000058 uip_arp_timer +20000ec8 g O .bss 00000002 uip_listenports +20000ecc g O .bss 00000004 uip_draddr +0800d714 g F .text 00000024 RCC_APB1PeriphResetCmd 20000000 g .data 00000000 _data -0800859c g F .text 0000007e LedToggle -20000868 g .bss 00000000 _estack +0800c5a8 g F .text 0000007e LedToggle +0800ce70 g F .text 0000003e ETH_Start +20000190 g O .bss 00000640 RxBuff +20001d1c g .bss 00000000 _estack 20000014 g .data 00000000 _edata -08008000 g O .text 0000018c _vectab -080083d0 g F .text 00000104 BootComCheckActivationRequest -08008b94 g F .text 00000024 RCC_AHB1PeriphClockCmd -20000068 g .bss 00000000 _stack -080086b0 g F .text 0000000c TimerGet -08008668 g F .text 00000046 TimerInit +0800eb20 g F .text 0000000a htons +0800c000 g O .text 0000018c _vectab +0800cdc0 g F .text 00000026 ETH_MACReceptionCmd +200007d0 g O .bss 00000640 TxBuff +0800c3d0 g F .text 00000104 BootComCheckActivationRequest +0800ce20 g F .text 00000026 ETH_DMATransmissionCmd +0800daf4 g F .text 00000032 uip_init +0800d684 g F .text 00000024 RCC_AHB1PeriphClockCmd +2000151c g .bss 00000000 _stack +20000ed0 g O .bss 00000004 uip_netmask +20000ed4 g O .bss 00000004 uip_hostaddr +0800c8f4 g F .text 0000000c TimerGet +20000e80 g O .bss 00000010 EnetDmaTx +0800c6b8 g F .text 00000038 NetApp +0800c628 g F .text 00000090 NetInit +0800c8ac g F .text 00000046 TimerInit +20000ed8 g O .bss 00000642 uip_buf +2000151a g O .bss 00000002 uip_slen diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/bin/demoprog_olimex_stm32e407.srec b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/bin/demoprog_olimex_stm32e407.srec index 462f1bbd..e6b4a9e6 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/bin/demoprog_olimex_stm32e407.srec +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/bin/demoprog_olimex_stm32e407.srec @@ -1,235 +1,791 @@ S025000062696E2F64656D6F70726F675F6F6C696D65785F73746D3332653430372E7372656335 -S3150800800068080020D5840008CD860008CD860008BB -S31508008010CD860008CD860008CD860008CD860008E6 -S31508008020CD860008CD860008CD860008CD860008D6 -S31508008030CD860008CD860008CD860008BD860008D6 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a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/boot.c +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/boot.c @@ -87,7 +87,7 @@ void BootComCheckActivationRequest(void) ** \return none. ** ****************************************************************************************/ -static void BootActivate(void) +void BootActivate(void) { /* perform software reset to activate the bootoader again */ NVIC_SystemReset(); diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/boot.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/boot.h index 1e5edab7..ac8c16be 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/boot.h +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/boot.h @@ -38,6 +38,7 @@ ****************************************************************************************/ void BootComInit(void); void BootComCheckActivationRequest(void); +void BootActivate(void); #endif /* BOOT_H */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/header.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/header.h index 343341ce..0fb08098 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/header.h +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/header.h @@ -43,6 +43,7 @@ #include "irq.h" /* IRQ driver */ #include "led.h" /* LED driver */ #include "timer.h" /* Timer driver */ +#include "net.h" /* TCP/IP server application */ #endif /* HEADER_H */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/ethernetlib/inc/stm32_eth.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/ethernetlib/inc/stm32_eth.h new file mode 100644 index 00000000..578d8baa --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/ethernetlib/inc/stm32_eth.h @@ -0,0 +1,1610 @@ +/** + ****************************************************************************** + * @file stm32_eth.h + * @author MCD Application Team + * @version V1.0.0 + * @date 06/19/2009 + * @brief This file contains all the functions prototypes for the Ethernet + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ETH_H +#define __STM32_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" /* STM32 registers */ + +/** @addtogroup STM32_ETH_Driver + * @{ + */ + +/** @defgroup ETH_Exported_Types + * @{ + */ + +/** + * @brief ETH MAC Init structure definition + */ +typedef struct { +/** + * @brief / * MAC + */ + uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation with the external PHY */ + uint32_t ETH_Watchdog; /*!< Enable/disable Watchdog timer */ + uint32_t ETH_Jabber; /*!< Enable/disable Jabber timer */ + uint32_t ETH_InterFrameGap; /*!< Selects minimum IFG between frames during transmission */ + uint32_t ETH_CarrierSense; /*!< Enable/disable Carrier Sense */ + uint32_t ETH_Speed; /*!< Indicates the Ethernet speed: 10/100 Mbps */ + uint32_t ETH_ReceiveOwn; /*!< Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */ + uint32_t ETH_LoopbackMode; /*!< Enable/disable internal MAC MII Loopback mode */ + uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */ + uint32_t ETH_ChecksumOffload; /*!< Enable/disable the calculation of complement sum of all received Ethernet frame payloads */ + uint32_t ETH_RetryTransmission; /*!< Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */ + uint32_t ETH_AutomaticPadCRCStrip; /*!< Enable/disable Automatic MAC Pad/CRC Stripping */ + uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value */ + uint32_t ETH_DeferralCheck; /*!< Enable/disable deferral check function (Half-Duplex mode) */ + uint32_t ETH_ReceiveAll; /*!< Enable/disable all frames reception by the MAC (No fitering)*/ + uint32_t ETH_SourceAddrFilter; /*!< Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */ + uint32_t ETH_PassControlFrames; /*!< Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */ + uint32_t ETH_BroadcastFramesReception; /*!< Enable/disable reception of Broadcast Frames */ + uint32_t ETH_DestinationAddrFilter; /*!< Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */ + uint32_t ETH_PromiscuousMode; /*!< Enable/disable Promiscuous Mode */ + uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */ + uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter */ + uint32_t ETH_HashTableHigh; /*!< This field contains the higher 32 bits of Hash table. */ + uint32_t ETH_HashTableLow; /*!< This field contains the lower 32 bits of Hash table. */ + uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame */ + uint32_t ETH_ZeroQuantaPause; /*!< Enable/disable the automatic generation of Zero-Quanta Pause Control frames */ + uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */ + uint32_t ETH_UnicastPauseFrameDetect; /*!< Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */ + uint32_t ETH_ReceiveFlowControl; /*!< Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */ + uint32_t ETH_TransmitFlowControl; /*!< Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */ + uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */ + uint32_t ETH_VLANTagIdentifier; /*!< VLAN tag identifier for receive frames */ + +/** + * @brief / * DMA + */ + uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Enable/disable Dropping of TCP/IP Checksum Error Frames */ + uint32_t ETH_ReceiveStoreForward; /*!< Enable/disable Receive store and forward */ + uint32_t ETH_FlushReceivedFrame; /*!< Enable/disable flushing of received frames */ + uint32_t ETH_TransmitStoreForward; /*!< Enable/disable Transmit store and forward */ + uint32_t ETH_TransmitThresholdControl; /*!< Selects the Transmit Threshold Control */ + uint32_t ETH_ForwardErrorFrames; /*!< Enable/disable forward to DMA of all frames except runt error frames */ + uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */ + uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO */ + uint32_t ETH_SecondFrameOperate; /*!< Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */ + uint32_t ETH_AddressAlignedBeats; /*!< Enable/disable Address Aligned Beats */ + uint32_t ETH_FixedBurst; /*!< Enable/disable the AHB Master interface fixed burst transfers */ + uint32_t ETH_RxDMABurstLength; /*!< Indicate the maximum number of beats to be transferred in one Rx DMA transaction */ + uint32_t ETH_TxDMABurstLength; /*!< Indicate the maximum number of beats to be transferred in one Tx DMA transaction */ + uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + uint32_t ETH_DMAArbitration; /*!< Selects DMA Tx/Rx arbitration */ +}ETH_InitTypeDef; + +/**--------------------------------------------------------------------------**/ +/** + * @brief DMA descriptors types + */ +/**--------------------------------------------------------------------------**/ + +/** + * @brief ETH DMA Desciptors data structure definition + */ +typedef struct { + uint32_t Status; /*!< Status */ + uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ +} ETH_DMADESCTypeDef; + +/** + * @} + */ + +/** @defgroup ETH_Exported_Constants + * @{ + */ +/**--------------------------------------------------------------------------**/ +/** + * @brief ETH Frames defines + */ +/**--------------------------------------------------------------------------**/ + +/** @defgroup ENET_Buffers_setting + * @{ + */ +#define ETH_MAX_PACKET_SIZE 1520 /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /*!< Ethernet CRC */ +#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ +#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA descriptors registers bits definition + */ +/**--------------------------------------------------------------------------**/ + +/* DMA Tx Desciptor -----------------------------------------------------------*/ +/**---------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ---------------------------------------------------------------------------------------------**/ + +/** + * @brief Bit definition of TDES0 register: DMA Tx descriptor status register + */ +#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */ +#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */ +#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */ +#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ +#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ +#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ +#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */ +#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ +#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ + +/** + * @brief Bit definition of TDES1 register + */ +#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ + +/** + * @brief Bit definition of TDES2 register + */ +#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of TDES3 register + */ +#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/** + * @} + */ + + +/** @defgroup DMA_Rx_descriptor + * @{ + */ + +/**-------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + -------------------------------------------------------------------------------------------------------------------**/ + +/** + * @brief Bit definition of RDES0 register: DMA Rx descriptor status register + */ +#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */ +#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/** + * @brief Bit definition of RDES1 register + */ +#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ + +/** + * @brief Bit definition of RDES2 register + */ +#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of RDES3 register + */ +#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/**--------------------------------------------------------------------------**/ +/** + * @brief Desciption of common PHY registers + */ +/**--------------------------------------------------------------------------**/ + +/** + * @} + */ + +/** @defgroup PHY_Read_write_Timeouts + * @{ + */ +#define PHY_READ_TO ((uint32_t)0x0004FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) + +/** + * @} + */ + +/** @defgroup PHY_Reset_Delay + * @{ + */ +#define PHY_ResetDelay ((uint32_t)0x04000000) + +/** + * @} + */ + +/** @defgroup PHY_Config_Delay + * @{ + */ +#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) + +/** + * @} + */ + +/** @defgroup PHY_Register_address + * @{ + */ +#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */ +#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */ + +/** + * @} + */ + +/** @defgroup PHY_basic_Control_register + * @{ + */ +#define PHY_Reset ((u16)0x8000) /*!< PHY Reset */ +#define PHY_Loopback ((u16)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((u16)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((u16)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_Powerdown ((u16)0x0800) /*!< Select the power down mode */ +#define PHY_Isolate ((u16)0x0400) /*!< Isolate PHY from MII */ + +/** + * @} + */ + +/** @defgroup PHY_basic_status_register + * @{ + */ +#define PHY_AutoNego_Complete ((u16)0x0020) /*!< Auto-Negotioation process completed */ +#define PHY_Linked_Status ((u16)0x0004) /*!< Valid link established */ +#define PHY_Jabber_detection ((u16)0x0002) /*!< Jabber condition detected */ + +/** + * @} + */ + +/** @defgroup PHY_status_register + * @{ + */ +/* The PHY status register value change from a PHY to another so the user have + to update this value depending on the used external PHY */ +/** + * @brief For LAN8700 + */ +//#define PHY_SR 31 /*!< Tranceiver Status Register */ +/** + * @brief For DP83848 + */ +#define PHY_SR 16 /*!< Tranceiver Status Register */ + +/* The Speed and Duplex mask values change from a PHY to another so the user have to update + this value depending on the used external PHY */ +/** + * @brief For LAN8700 + */ +//#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */ +//#define PHY_Duplex_Status ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */ + +/** + * @brief For DP83848 + */ +#define PHY_Speed_Status ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */ +#define PHY_Duplex_Status ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */ +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) +#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \ + ((REG) == PHY_BSR) || \ + ((REG) == PHY_SR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief MAC defines + */ +/**--------------------------------------------------------------------------**/ + +/** + * @} + */ + +/** @defgroup ETH_AutoNegotiation + * @{ + */ +#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) +#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) +#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \ + ((CMD) == ETH_AutoNegotiation_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_watchdog + * @{ + */ +#define ETH_Watchdog_Enable ((uint32_t)0x00000000) +#define ETH_Watchdog_Disable ((uint32_t)0x00800000) +#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \ + ((CMD) == ETH_Watchdog_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Jabber + * @{ + */ +#define ETH_Jabber_Enable ((uint32_t)0x00000000) +#define ETH_Jabber_Disable ((uint32_t)0x00400000) +#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \ + ((CMD) == ETH_Jabber_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Inter_Frame_Gap + * @{ + */ +#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ +#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \ + ((GAP) == ETH_InterFrameGap_88Bit) || \ + ((GAP) == ETH_InterFrameGap_80Bit) || \ + ((GAP) == ETH_InterFrameGap_72Bit) || \ + ((GAP) == ETH_InterFrameGap_64Bit) || \ + ((GAP) == ETH_InterFrameGap_56Bit) || \ + ((GAP) == ETH_InterFrameGap_48Bit) || \ + ((GAP) == ETH_InterFrameGap_40Bit)) + +/** + * @} + */ + +/** @defgroup ETH_Carrier_Sense + * @{ + */ +#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) +#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) +#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \ + ((CMD) == ETH_CarrierSense_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Speed + * @{ + */ +#define ETH_Speed_10M ((uint32_t)0x00000000) +#define ETH_Speed_100M ((uint32_t)0x00004000) +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \ + ((SPEED) == ETH_Speed_100M)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Own + * @{ + */ +#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) +#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) +#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \ + ((CMD) == ETH_ReceiveOwn_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Loop_back_Mode + * @{ + */ +#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) +#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) +#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \ + ((CMD) == ETH_LoopbackMode_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Duplex_mode + * @{ + */ +#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) +#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) +#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \ + ((MODE) == ETH_Mode_HalfDuplex)) + +/** + * @} + */ + +/** @defgroup ETH_Checksum_Offload + * @{ + */ +#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) +#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) +#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \ + ((CMD) == ETH_ChecksumOffload_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Retry_Transmission + * @{ + */ +#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) +#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) +#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \ + ((CMD) == ETH_RetryTransmission_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Automatic_Pad_CRC_Strip + * @{ + */ +#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) +#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \ + ((CMD) == ETH_AutomaticPadCRCStrip_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Back-Off_limit + * @{ + */ +#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) +#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) +#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) +#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) +#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \ + ((LIMIT) == ETH_BackOffLimit_8) || \ + ((LIMIT) == ETH_BackOffLimit_4) || \ + ((LIMIT) == ETH_BackOffLimit_1)) + +/** + * @} + */ + +/** @defgroup ETH_Deferral_Check + * @{ + */ +#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) +#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) +#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \ + ((CMD) == ETH_DeferralCheck_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_All + * @{ + */ +#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) +#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \ + ((CMD) == ETH_ReceiveAll_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Source_Addr_Filter + * @{ + */ +#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) +#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) +#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Pass_Control_Frames + * @{ + */ +#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ +#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter)) + +/** + * @} + */ + +/** @defgroup ETH_Broadcast_Frames_Reception + * @{ + */ +#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) +#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \ + ((CMD) == ETH_BroadcastFramesReception_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Destination_Addr_Filter + * @{ + */ +#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) +#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \ + ((FILTER) == ETH_DestinationAddrFilter_Inverse)) + +/** + * @} + */ + +/** @defgroup ETH_Promiscuous_Mode + * @{ + */ +#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) +#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) +#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \ + ((CMD) == ETH_PromiscuousMode_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_multicast_frames_filter + * @{ + */ +#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) +#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) +#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \ + ((FILTER) == ETH_MulticastFramesFilter_None)) + + +/** + * @} + */ + +/** @defgroup ETH_unicast_frames_filter + * @{ + */ +#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) +#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_Perfect)) + +/** + * @} + */ + +/** @defgroup ETH_Pause_Time + * @{ + */ +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) + +/** + * @} + */ + +/** @defgroup ETH_Zero_Quanta_Pause + * @{ + */ +#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) +#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \ + ((CMD) == ETH_ZeroQuantaPause_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Pause_Low_Threshold + * @{ + */ +#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ +#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus256)) + +/** + * @} + */ + +/** @defgroup ETH_Unicast_Pause_Frame_Detect + * @{ + */ +#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) +#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \ + ((CMD) == ETH_UnicastPauseFrameDetect_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Flow_Control + * @{ + */ +#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \ + ((CMD) == ETH_ReceiveFlowControl_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Transmit_Flow_Control + * @{ + */ +#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) +#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) +#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \ + ((CMD) == ETH_TransmitFlowControl_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_VLAN_Tag_Comparison + * @{ + */ +#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) +#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) +#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \ + ((COMPARISON) == ETH_VLANTagComparison_16Bit)) +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) + +/** + * @} + */ + +/** @defgroup ETH_MAC_Flags + * @{ + */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ +#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ + ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ + ((FLAG) == ETH_MAC_FLAG_PMT)) +/** + * @} + */ + +/** @defgroup ETH_MAC_Interrupts + * @{ + */ +#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ +#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ + ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ + ((IT) == ETH_MAC_IT_PMT)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses + * @{ + */ +#define ETH_MAC_Address0 ((uint32_t)0x00000000) +#define ETH_MAC_Address1 ((uint32_t)0x00000008) +#define ETH_MAC_Address2 ((uint32_t)0x00000010) +#define ETH_MAC_Address3 ((uint32_t)0x00000018) +#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \ + ((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) +#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter:_SA_DA_filed_of_received_frames + * @{ + */ +#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) +#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) +#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \ + ((FILTER) == ETH_MAC_AddressFilter_DA)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter:_Mask_bytes + * @{ + */ +#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ +#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \ + ((MASK) == ETH_MAC_AddressMask_Byte5) || \ + ((MASK) == ETH_MAC_AddressMask_Byte4) || \ + ((MASK) == ETH_MAC_AddressMask_Byte3) || \ + ((MASK) == ETH_MAC_AddressMask_Byte2) || \ + ((MASK) == ETH_MAC_AddressMask_Byte1)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA Desciptors defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_flags + * @{ + */ +#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \ + ((FLAG) == ETH_DMATxDesc_IC) || \ + ((FLAG) == ETH_DMATxDesc_LS) || \ + ((FLAG) == ETH_DMATxDesc_FS) || \ + ((FLAG) == ETH_DMATxDesc_DC) || \ + ((FLAG) == ETH_DMATxDesc_DP) || \ + ((FLAG) == ETH_DMATxDesc_TTSE) || \ + ((FLAG) == ETH_DMATxDesc_TER) || \ + ((FLAG) == ETH_DMATxDesc_TCH) || \ + ((FLAG) == ETH_DMATxDesc_TTSS) || \ + ((FLAG) == ETH_DMATxDesc_IHE) || \ + ((FLAG) == ETH_DMATxDesc_ES) || \ + ((FLAG) == ETH_DMATxDesc_JT) || \ + ((FLAG) == ETH_DMATxDesc_FF) || \ + ((FLAG) == ETH_DMATxDesc_PCE) || \ + ((FLAG) == ETH_DMATxDesc_LCA) || \ + ((FLAG) == ETH_DMATxDesc_NC) || \ + ((FLAG) == ETH_DMATxDesc_LCO) || \ + ((FLAG) == ETH_DMATxDesc_EC) || \ + ((FLAG) == ETH_DMATxDesc_VF) || \ + ((FLAG) == ETH_DMATxDesc_CC) || \ + ((FLAG) == ETH_DMATxDesc_ED) || \ + ((FLAG) == ETH_DMATxDesc_UF) || \ + ((FLAG) == ETH_DMATxDesc_DB)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_segment + * @{ + */ +#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */ +#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \ + ((SEGMENT) == ETH_DMATxDesc_FirstSegment)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control + * @{ + */ +#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ +#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull)) +/** + * @brief ETH DMA Tx Desciptor buffer size + */ +#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_flags + * @{ + */ +#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \ + ((FLAG) == ETH_DMARxDesc_AFM) || \ + ((FLAG) == ETH_DMARxDesc_ES) || \ + ((FLAG) == ETH_DMARxDesc_DE) || \ + ((FLAG) == ETH_DMARxDesc_SAF) || \ + ((FLAG) == ETH_DMARxDesc_LE) || \ + ((FLAG) == ETH_DMARxDesc_OE) || \ + ((FLAG) == ETH_DMARxDesc_VLAN) || \ + ((FLAG) == ETH_DMARxDesc_FS) || \ + ((FLAG) == ETH_DMARxDesc_LS) || \ + ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \ + ((FLAG) == ETH_DMARxDesc_LC) || \ + ((FLAG) == ETH_DMARxDesc_FT) || \ + ((FLAG) == ETH_DMARxDesc_RWT) || \ + ((FLAG) == ETH_DMARxDesc_RE) || \ + ((FLAG) == ETH_DMARxDesc_DBE) || \ + ((FLAG) == ETH_DMARxDesc_CE) || \ + ((FLAG) == ETH_DMARxDesc_MAMPCE)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_buffers_ + * @{ + */ +#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ +#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \ + ((BUFFER) == ETH_DMARxDesc_Buffer2)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame + * @{ + */ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) +#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \ + ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Receive_Store_Forward + * @{ + */ +#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \ + ((CMD) == ETH_ReceiveStoreForward_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Flush_Received_Frame + * @{ + */ +#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) +#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \ + ((CMD) == ETH_FlushReceivedFrame_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Store_Forward + * @{ + */ +#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) +#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) +#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \ + ((CMD) == ETH_TransmitStoreForward_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Threshold_Control + * @{ + */ +#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes)) +/** + * @} + */ + +/** @defgroup ETH_Forward_Error_Frames + * @{ + */ +#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) +#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \ + ((CMD) == ETH_ForwardErrorFrames_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Forward_Undersized_Good_Frames + * @{ + */ +#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) +#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \ + ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Threshold_Control + * @{ + */ +#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ +#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes)) +/** + * @} + */ + +/** @defgroup ETH_Second_Frame_Operate + * @{ + */ +#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) +#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) +#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \ + ((CMD) == ETH_SecondFrameOperate_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Address_Aligned_Beats + * @{ + */ +#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) +#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \ + ((CMD) == ETH_AddressAlignedBeats_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Fixed_Burst + * @{ + */ +#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) +#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) +#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \ + ((CMD) == ETH_FixedBurst_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Rx_DMA_Burst_Length + * @{ + */ +#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat)) + +/** + * @} + */ + +/** @defgroup ETH_Tx_DMA_Burst_Length + * @{ + */ +#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat)) +/** + * @brief ETH DMA Desciptor SkipLength + */ +#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Arbitration + * @{ + */ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) +#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \ + ((RATIO) == ETH_DMAArbitration_RxPriorTx)) +/** + * @} + */ + +/** @defgroup ETH_DMA_Flags + * @{ + */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ +#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */ +#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */ +#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ + +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) +#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ + ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \ + ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \ + ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ + ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ + ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ + ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ + ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ + ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ + ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ + ((FLAG) == ETH_DMA_FLAG_T)) +/** + * @} + */ + +/** @defgroup ETH_DMA_Interrupts + * @{ + */ +#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ +#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ +#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */ +#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */ +#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ + +#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ + ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ + ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ + ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ + ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ + ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ + ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ + ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ + ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_transmit_process_state_ + * @{ + */ +#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ + +/** + * @} + */ + + +/** @defgroup ETH_DMA_receive_process_state_ + * @{ + */ +#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the recieve frame into host memory */ + +/** + * @} + */ + +/** @defgroup ETH_DMA_overflow_ + * @{ + */ +#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ +#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \ + ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet PMT defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_PMT_Flags + * @{ + */ +#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ + ((FLAG) == ETH_PMT_FLAG_MPR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet MMC defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_MMC_Tx_Interrupts + * @{ + */ +#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ + +/** + * @} + */ + +/** @defgroup ETH_MMC_Rx_Interrupts + * @{ + */ +#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ +#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ + ((IT) != 0x00)) +#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ + ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ + ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) +/** + * @} + */ + +/** @defgroup ETH_MMC_Registers + * @{ + */ +#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */ +#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */ +#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */ +#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */ +#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */ +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */ +#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */ +#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */ +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */ + +/** + * @brief ETH MMC registers + */ +#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \ + ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \ + ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \ + ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \ + ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \ + ((REG) == ETH_MMCRGUFCR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet PTP defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_PTP_time_update_method + * @{ + */ +#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */ +#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */ +#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \ + ((UPDATE) == ETH_PTP_CoarseUpdate)) + +/** + * @} + */ + + +/** @defgroup ETH_PTP_Flags + * @{ + */ +#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */ +#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \ + ((FLAG) == ETH_PTP_FLAG_TSITE) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTU) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTI)) +/** + * @brief ETH PTP subsecond increment + */ +#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) + +/** + * @} + */ + + +/** @defgroup ETH_PTP_time_sign + * @{ + */ +#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */ +#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */ +#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \ + ((SIGN) == ETH_PTP_NegativeTime)) + +/** + * @brief ETH PTP time stamp low update + */ +#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) + +/** + * @brief ETH PTP registers + */ +#define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */ +#define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */ +#define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */ +#define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */ +#define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */ +#define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */ +#define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */ +#define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */ +#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ +#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \ + ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \ + ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \ + ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \ + ((REG) == ETH_PTPTTLR)) + +/** + * @} + */ + + +/** + * @} + */ + +/** @defgroup ETH_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions + * @{ + */ +void ETH_DeInit(void); +uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress); +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +void ETH_Start(void); +uint32_t ETH_HandleTxPkt(u8 *ppkt, u16 FrameLength); +uint32_t ETH_HandleRxPkt(u8 *ppkt); +uint32_t ETH_GetRxPktSize(void); +void ETH_DropRxPkt(void); + +/** + * @brief PHY + */ +u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg); +uint32_t ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue); +uint32_t ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState); + +/** + * @brief MAC + */ +void ETH_MACTransmissionCmd(FunctionalState NewState); +void ETH_MACReceptionCmd(FunctionalState NewState); +FlagStatus ETH_GetFlowControlBusyStatus(void); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState NewState); +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); +void ETH_MACAddressConfig(uint32_t MacAddr, u8 *Addr); +void ETH_GetMACAddress(uint32_t MacAddr, u8 *Addr); +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); + +/** + * @brief DMA Tx/Rx descriptors + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, uint32_t TxBuffCount); +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, uint32_t TxBuffCount); +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, uint32_t RxBuffCount); +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, uint32_t RxBuffCount); +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); + +/** + * @brief DMA + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); +uint32_t ETH_GetTransmitProcessState(void); +uint32_t ETH_GetReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); +void ETH_DMATransmissionCmd(FunctionalState NewState); +void ETH_DMAReceptionCmd(FunctionalState NewState); +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); +uint32_t ETH_GetRxOverflowMissedFrameCounter(void); +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); +uint32_t ETH_GetCurrentTxDescStartAddress(void); +uint32_t ETH_GetCurrentRxDescStartAddress(void); +uint32_t ETH_GetCurrentTxBufferAddress(void); +uint32_t ETH_GetCurrentRxBufferAddress(void); +void ETH_ResumeDMATransmission(void); +void ETH_ResumeDMAReception(void); + +/** + * @brief PMT + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); +void ETH_MagicPacketDetectionCmd(FunctionalState NewState); +void ETH_PowerDownCmd(FunctionalState NewState); + +/** + * @brief MMC + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState); +void ETH_MMCResetOnReadCmd(FunctionalState NewState); +void ETH_MMCCounterRolloverCmd(FunctionalState NewState); +void ETH_MMCCountersReset(void); +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); + +/** + * @brief PTP + */ +uint32_t ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, uint32_t *PTPTxTab); +uint32_t ETH_HandlePTPRxPkt(u8 *ppkt, uint32_t *PTPRxTab); +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, uint32_t TxBuffCount); +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, uint32_t RxBuffCount); +void ETH_EnablePTPTimeStampAddend(void); +void ETH_EnablePTPTimeStampInterruptTrigger(void); +void ETH_EnablePTPTimeStampUpdate(void); +void ETH_InitializePTPTimeStamp(void); +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod); +void ETH_PTPTimeStampCmd(FunctionalState NewState); +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG); +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue); +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); +void ETH_SetPTPTimeStampAddend(uint32_t Value); +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue); +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ETH_H */ +/** + * @} + */ + + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/ethernetlib/src/stm32_eth.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/ethernetlib/src/stm32_eth.c new file mode 100644 index 00000000..119b4dbf --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/ethernetlib/src/stm32_eth.c @@ -0,0 +1,3056 @@ +/** + ****************************************************************************** + * @file stm32_eth.c + * @author MCD Application Team + * @version V1.0.0 + * @date 06/19/2009 + * @brief This file provides all the ETH firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_eth.h" +#include "stm32f4xx_rcc.h" + +/** @addtogroup STM32_ETH_Driver + * @brief ETH driver modules + * @{ + */ + +/** @defgroup ETH_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup ETH_Private_Defines + * @{ + */ +/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */ +ETH_DMADESCTypeDef *DMATxDescToSet; +ETH_DMADESCTypeDef *DMARxDescToGet; +ETH_DMADESCTypeDef *DMAPTPTxDescToSet; +ETH_DMADESCTypeDef *DMAPTPRxDescToGet; + +/* ETHERNET MAC address offsets */ +#define ETH_MAC_AddrHighBase (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_AddrLowBase (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_Mask ((uint32_t)0xFFFFFFE3) +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_Mask ((uint32_t)0xFF20810F) +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_Mask ((uint32_t)0x0000FF41) +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_Mask ((uint32_t)0xF8DE3F23) +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WakeupRegisterLength 8 +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RxOverflowMissedFramesCounterShift 17 +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATxDesc_CollisionCountShift 3 +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATxDesc_BufferSize2Shift 16 +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARxDesc_FrameLengthShift 16 +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARxDesc_Buffer2SizeShift 16 +/* ETHERNET errors */ +#define ETH_ERROR ((uint32_t)0) +#define ETH_SUCCESS ((uint32_t)1) +/** + * @} + */ + +/** @defgroup ETH_Private_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_FunctionPrototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ETHERNET peripheral registers to their + * default reset values. + * @param None + * @retval : None + */ +void ETH_DeInit(void) +{ + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE); +} + +/** + * @brief Initializes the ETHERNET peripheral according to the specified + * parameters in the ETH_InitStruct . + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure + * that contains the configuration information for the + * specified ETHERNET peripheral. + * @param PHYAddress: external PHY address + * @retval : ETH_ERROR: Ethernet initialization failed + * ETH_SUCCESS: Ethernet successfully initialized + */ +uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) +{ + uint32_t RegValue = 0, tmpreg = 0; + __IO uint32_t i = 0; + RCC_ClocksTypeDef rcc_clocks; + uint32_t hclk = 120000000; + __IO uint32_t timeout = 0; + /* Check the parameters */ + /* MAC --------------------------*/ + assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation)); + assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog)); + assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber)); + assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap)); + assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense)); + assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed)); + assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn)); + assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode)); + assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode)); + assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload)); + assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission)); + assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip)); + assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit)); + assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck)); + assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll)); + assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter)); + assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames)); + assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception)); + assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter)); + assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode)); + assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); + assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter)); + assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime)); + assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause)); + assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold)); + assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect)); + assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl)); + assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl)); + assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison)); + assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier)); + /* DMA --------------------------*/ + assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame)); + assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward)); + assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame)); + assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward)); + assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl)); + assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames)); + assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames)); + assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl)); + assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate)); + assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats)); + assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst)); + assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength)); + assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); + assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); + assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); + /*-------------------------------- MAC Config ------------------------------*/ + /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/ + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg &= MACMIIAR_CR_Mask; + /* Get hclk frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + hclk = rcc_clocks.HCLK_Frequency; + /* Set CR bits depending on hclk value */ + if((hclk >= 20000000)&&(hclk < 35000000)) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; + } + else if((hclk >= 35000000)&&(hclk < 60000000)) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; + } + else if((hclk >= 60000000)&&(hclk <= 100000000)) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else /*if((hclk >= 100000000)&&(hclk <= 120000000)) */ + { + /* CSR Clock Range between 100-120 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; + } + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + ETH->MACMIIAR = (uint32_t)tmpreg; + /*-------------------- PHY initialization and configuration ----------------*/ + /* Put the PHY in reset mode */ + if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + + /* Delay to assure PHY reset */ + for(i = PHY_ResetDelay; i != 0; i--) + { + } + + if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) + { + /* We wait for linked satus... */ + do + { + timeout++; + } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Reset Timeout counter */ + timeout = 0; + + /* Enable Auto-Negotiation */ + if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + + /* Wait until the autonegotiation will be completed */ + do + { + timeout++; + } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Reset Timeout counter */ + timeout = 0; + + /* Read the result of the autonegotiation */ + RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR); + + /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */ + if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET) + { + /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */ + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + + } + else + { + /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */ + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + } + /* Configure the MAC with the speed fixed by the autonegotiation process */ + if(RegValue & PHY_Speed_Status) + { + /* Set Ethernet speed to 10M following the autonegotiation */ + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + } + else + { + /* Set Ethernet speed to 100M following the autonegotiation */ + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + } + } + else + { + if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) | + (uint16_t)(ETH_InitStruct->ETH_Speed >> 1)))) + { + /* Return ERROR in case of write timeout */ + return ETH_ERROR; + } + /* Delay to assure PHY configuration */ + for(i = PHY_ConfigDelay; i != 0; i--) + { + } + } + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = ETH->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg &= MACCR_CLEAR_Mask; + /* Set the WD bit according to ETH_Watchdog value */ + /* Set the JD: bit according to ETH_Jabber value */ + /* Set the IFG bit according to ETH_InterFrameGap value */ + /* Set the DCRS bit according to ETH_CarrierSense value */ + /* Set the FES bit according to ETH_Speed value */ + /* Set the DO bit according to ETH_ReceiveOwn value */ + /* Set the LM bit according to ETH_LoopbackMode value */ + /* Set the DM bit according to ETH_Mode value */ + /* Set the IPC bit according to ETH_ChecksumOffload value */ + /* Set the DR bit according to ETH_RetryTransmission value */ + /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ + /* Set the BL bit according to ETH_BackOffLimit value */ + /* Set the DC bit according to ETH_DeferralCheck value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | + ETH_InitStruct->ETH_Jabber | + ETH_InitStruct->ETH_InterFrameGap | + ETH_InitStruct->ETH_CarrierSense | + ETH_InitStruct->ETH_Speed | + ETH_InitStruct->ETH_ReceiveOwn | + ETH_InitStruct->ETH_LoopbackMode | + ETH_InitStruct->ETH_Mode | + ETH_InitStruct->ETH_ChecksumOffload | + ETH_InitStruct->ETH_RetryTransmission | + ETH_InitStruct->ETH_AutomaticPadCRCStrip | + ETH_InitStruct->ETH_BackOffLimit | + ETH_InitStruct->ETH_DeferralCheck); + /* Write to ETHERNET MACCR */ + ETH->MACCR = (uint32_t)tmpreg; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Set the RA bit according to ETH_ReceiveAll value */ + /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */ + /* Set the PCF bit according to ETH_PassControlFrames value */ + /* Set the DBF bit according to ETH_BroadcastFramesReception value */ + /* Set the DAIF bit according to ETH_DestinationAddrFilter value */ + /* Set the PR bit according to ETH_PromiscuousMode value */ + /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */ + /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */ + /* Write to ETHERNET MACFFR */ + ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | + ETH_InitStruct->ETH_SourceAddrFilter | + ETH_InitStruct->ETH_PassControlFrames | + ETH_InitStruct->ETH_BroadcastFramesReception | + ETH_InitStruct->ETH_DestinationAddrFilter | + ETH_InitStruct->ETH_PromiscuousMode | + ETH_InitStruct->ETH_MulticastFramesFilter | + ETH_InitStruct->ETH_UnicastFramesFilter); + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ + /* Write to ETHERNET MACHTHR */ + ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh; + /* Write to ETHERNET MACHTLR */ + ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + /* Get the ETHERNET MACFCR value */ + tmpreg = ETH->MACFCR; + /* Clear xx bits */ + tmpreg &= MACFCR_CLEAR_Mask; + + /* Set the PT bit according to ETH_PauseTime value */ + /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */ + /* Set the PLT bit according to ETH_PauseLowThreshold value */ + /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */ + /* Set the RFE bit according to ETH_ReceiveFlowControl value */ + /* Set the TFE bit according to ETH_TransmitFlowControl value */ + tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | + ETH_InitStruct->ETH_ZeroQuantaPause | + ETH_InitStruct->ETH_PauseLowThreshold | + ETH_InitStruct->ETH_UnicastPauseFrameDetect | + ETH_InitStruct->ETH_ReceiveFlowControl | + ETH_InitStruct->ETH_TransmitFlowControl); + /* Write to ETHERNET MACFCR */ + ETH->MACFCR = (uint32_t)tmpreg; + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ + /* Set the ETV bit according to ETH_VLANTagComparison value */ + /* Set the VL bit according to ETH_VLANTagIdentifier value */ + ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | + ETH_InitStruct->ETH_VLANTagIdentifier); + + /*-------------------------------- DMA Config ------------------------------*/ + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg = ETH->DMAOMR; + /* Clear xx bits */ + tmpreg &= DMAOMR_CLEAR_Mask; + + /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */ + /* Set the RSF bit according to ETH_ReceiveStoreForward value */ + /* Set the DFF bit according to ETH_FlushReceivedFrame value */ + /* Set the TSF bit according to ETH_TransmitStoreForward value */ + /* Set the TTC bit according to ETH_TransmitThresholdControl value */ + /* Set the FEF bit according to ETH_ForwardErrorFrames value */ + /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */ + /* Set the RTC bit according to ETH_ReceiveThresholdControl value */ + /* Set the OSF bit according to ETH_SecondFrameOperate value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | + ETH_InitStruct->ETH_ReceiveStoreForward | + ETH_InitStruct->ETH_FlushReceivedFrame | + ETH_InitStruct->ETH_TransmitStoreForward | + ETH_InitStruct->ETH_TransmitThresholdControl | + ETH_InitStruct->ETH_ForwardErrorFrames | + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | + ETH_InitStruct->ETH_ReceiveThresholdControl | + ETH_InitStruct->ETH_SecondFrameOperate); + /* Write to ETHERNET DMAOMR */ + ETH->DMAOMR = (uint32_t)tmpreg; + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + /* Set the AAL bit according to ETH_AddressAlignedBeats value */ + /* Set the FB bit according to ETH_FixedBurst value */ + /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */ + /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */ + /* Set the DSL bit according to ETH_DesciptorSkipLength value */ + /* Set the PR and DA bits according to ETH_DMAArbitration value */ + ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | + ETH_InitStruct->ETH_FixedBurst | + ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + ETH_InitStruct->ETH_TxDMABurstLength | + (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | + ETH_InitStruct->ETH_DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + /* Return Ethernet configuration success */ + return ETH_SUCCESS; +} + +/** + * @brief Fills each ETH_InitStruct member with its default value. + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure + * which will be initialized. + * @retval : None + */ +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct) +{ + /* ETH_InitStruct members default value */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + /*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable; + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; + ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; +} + +/** + * @brief Enables ENET MAC and DMA reception/transmission + * @param None + * @retval : None + */ +void ETH_Start(void) +{ + /* Enable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionCmd(ENABLE); + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(); + /* Enable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionCmd(ENABLE); + + /* Start DMA transmission */ + ETH_DMATransmissionCmd(ENABLE); + /* Start DMA reception */ + ETH_DMAReceptionCmd(ENABLE); +} + +/** + * @brief Transmits a packet, from application buffer, pointed by ppkt. + * @param ppkt: pointer to application packet buffer to transmit. + * @param FrameLength: Tx Packet size. + * @retval : ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission + */ +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) +{ + uint32_t offset = 0; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); + } + + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + /* Chained Mode */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Receives a packet and copies it to memory pointed by ppkt. + * @param ppkt: pointer to application packet receive buffer. + * @retval : ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct + */ +uint32_t ETH_HandleRxPkt(uint8_t *ppkt) +{ + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + } + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + /* Return Frame Length/ERROR */ + return (framelength); +} + +/** + * @brief Get the size of received the received packet. + * @param None + * @retval : framelength: received packet size + */ +uint32_t ETH_GetRxPktSize(void) +{ + uint32_t frameLength = 0; + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the size of the packet: including 4 bytes of the CRC */ + frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); + } + + /* Return Frame Length */ + return frameLength; +} + +/** + * @brief Drop a Received packet (too small packet, etc...) + * @param None + * @retval : None + */ +void ETH_DropRxPkt(void) +{ + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read: this will + be the first Rx descriptor in this case */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } +} + +/*--------------------------------- PHY ------------------------------------*/ +/** + * @brief Read a PHY register + * @param PHYAddress: PHY device address, is the index of one of supported + * 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg: PHY register address, is the index of one of the 32 + * PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR : Tranceiver Basic Control Register + * @arg PHY_BSR : Tranceiver Basic Status Register + * @arg PHY_SR : Tranceiver Status Register + * @arg More PHY register could be read depending on the used PHY + * @retval : ETH_ERROR: in case of timeout + * MAC MIIDR register value: Data read from the selected PHY register (correct read ) + */ +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) +{ + uint32_t tmpreg = 0; +__IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_Mask; + /* Prepare the MII address register value */ + tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } + + /* Return data register value */ + return (uint16_t)(ETH->MACMIIDR); +} + +/** + * @brief Write to a PHY register + * @param PHYAddress: PHY device address, is the index of one of supported + * 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg: PHY register address, is the index of one of the 32 + * PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR : Tranceiver Control Register + * @arg More PHY register could be written depending on the used PHY + * @param PHYValue: the value to write + * @retval : ETH_ERROR: in case of timeout + * ETH_SUCCESS: for correct write + */ +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_Mask; + /* Prepare the MII register address value */ + tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Give the value to the MII data register */ + ETH->MACMIIDR = PHYValue; + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_WRITE_TO) + { + return ETH_ERROR; + } + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Enables or disables the PHY loopBack mode. + * @param PHYAddress: PHY device address, is the index of one of supported + * 32 PHY devices. + * This parameter can be one of the following values: + * @param NewState: new state of the PHY loopBack mode. + * This parameter can be: ENABLE or DISABLE. + * Note: Don't be confused with ETH_MACLoopBackCmd function + * which enables internal loopback at MII level + * @retval : ETH_ERROR: in case of bad PHY configuration + * ETH_SUCCESS: for correct PHY configuration + */ +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the PHY configuration to update it */ + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + + if (NewState != DISABLE) + { + /* Enable the PHY loopback mode */ + tmpreg |= PHY_Loopback; + } + else + { + /* Disable the PHY loopback mode: normal mode */ + tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); + } + /* Update the PHY control register with the new configuration */ + if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) + { + return ETH_SUCCESS; + } + else + { + /* Return SUCCESS */ + return ETH_ERROR; + } +} + +/*--------------------------------- MAC ------------------------------------*/ +/** + * @brief Enables or disables the MAC transmission. + * @param NewState: new state of the MAC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACTransmissionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC transmission */ + ETH->MACCR |= ETH_MACCR_TE; + } + else + { + /* Disable the MAC transmission */ + ETH->MACCR &= ~ETH_MACCR_TE; + } +} + +/** + * @brief Enables or disables the MAC reception. + * @param NewState: new state of the MAC reception. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACReceptionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC reception */ + ETH->MACCR |= ETH_MACCR_RE; + } + else + { + /* Disable the MAC reception */ + ETH->MACCR &= ~ETH_MACCR_RE; + } +} + +/** + * @brief Checks whether the ETHERNET flow control busy bit is set or not. + * @param None + * @retval : The new state of flow control busy status bit (SET or RESET). + */ +FlagStatus ETH_GetFlowControlBusyStatus(void) +{ + FlagStatus bitstatus = RESET; + /* The Flow Control register should not be written to until this bit is cleared */ + if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Initiate a Pause Control Frame (Full-duplex only). + * @param None + * @retval : None + */ +void ETH_InitiatePauseControlFrame(void) +{ + /* When Set In full duplex MAC initiates pause control frame */ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; +} + +/** + * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). + * @param NewState: new state of the MAC BackPressure operation activation. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_BackPressureActivationCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Activate the MAC BackPressure operation */ + /* In Half duplex: during backpressure, when the MAC receives a new frame, + the transmitter starts sending a JAM pattern resulting in a collision */ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; + } + else + { + /* Desactivate the MAC BackPressure operation */ + ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; + } +} + +/** + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param ETH_MAC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag + * @retval : The new state of ETHERNET MAC flag (SET or RESET). + */ +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); + if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. + * @param ETH_MAC_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt + * @arg ETH_MAC_IT_MMCR : MMC receive interrupt + * @arg ETH_MAC_IT_MMC : MMC interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval : The new state of ETHERNET MAC interrupt (SET or RESET). + */ +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); + if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the specified ETHERNET MAC interrupts. + * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @param NewState: new state of the specified ETHERNET MAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_IT(ETH_MAC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC interrupts */ + ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); + } + else + { + /* Disable the selected ETHERNET MAC interrupts */ + ETH->MACIMR |= ETH_MAC_IT; + } +} + +/** + * @brief Configures the selected MAC address. + * @param MacAddr: The MAC addres to configure. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Addr: Pointer on MAC address buffer data (6 bytes). + * @retval : None + */ +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Calculate the selectecd MAC address high register */ + tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + /* Load the selectecd MAC address high register */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg; + /* Calculate the selectecd MAC address low register */ + tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + + /* Load the selectecd MAC address low register */ + (*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg; +} + +/** + * @brief Get the selected MAC address. + * @param MacAddr: The MAC addres to return. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Addr: Pointer on MAC address buffer data (6 bytes). + * @retval : None + */ +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Get the selectecd MAC address high register */ + tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)); + + /* Calculate the selectecd MAC address buffer */ + Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[4] = (tmpreg & (uint8_t)0xFF); + /* Load the selectecd MAC address low register */ + tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)); + /* Calculate the selectecd MAC address buffer */ + Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); + Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); + Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF); + Addr[0] = (tmpreg & (uint8_t)0xFF); +} + +/** + * @brief Enables or disables the Address filter module uses the specified + * ETHERNET MAC address for perfect filtering + * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param NewState: new state of the specified ETHERNET MAC address use. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE; + } + else + { + /* Disable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE); + } +} + +/** + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Filter: specifies the used frame received field for comparaison + * This parameter can be one of the following values: + * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare + * with the SA fields of the received frame. + * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare + * with the DA fields of the received frame. + * @retval : None + */ +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter)); + + if (Filter != ETH_MAC_AddressFilter_DA) + { + /* The selected ETHERNET MAC address is used to compare with the SA fields of the + received frame. */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA; + } + else + { + /* The selected ETHERNET MAC address is used to compare with the DA fields of the + received frame. */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA); + } +} + +/** + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param MaskByte: specifies the used address bytes for comparaison + * This parameter can be any combination of the following values: + * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8]. + * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0]. + * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24]. + * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16]. + * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8]. + * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0]. + * @retval : None + */ +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte)); + + /* Clear MBC bits in the selected MAC address high register */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC); + /* Set the selected Filetr mask bytes */ + (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte; +} +/*------------------------ DMA Tx/Rx Desciptors -----------------------------*/ + +/** + * @brief Initializes the DMA Tx descriptors in chain mode. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff: Pointer on the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval : None + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Second Address Chained bit */ + DMATxDesc->Status = ETH_DMATxDesc_TCH; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Initializes the DMA Tx descriptors in ring mode. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff1: Pointer on the first TxBuffer1 list + * @param TxBuff2: Pointer on the first TxBuffer2 list + * @param TxBuffCount: Number of the used Tx desc in the list + * Note: see decriptor skip length defined in ETH_DMA_InitStruct + * for the number of Words to skip between two unchained descriptors. + * @retval : None + */ +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (TxBuffCount-1)) + { + /* Set Transmit End of Ring bit */ + DMATxDesc->Status = ETH_DMATxDesc_TER; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param ETH_DMATxDescFlag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMATxDesc_IC : Interrupt on completetion + * @arg ETH_DMATxDesc_LS : Last Segment + * @arg ETH_DMATxDesc_FS : First Segment + * @arg ETH_DMATxDesc_DC : Disable CRC + * @arg ETH_DMATxDesc_DP : Disable Pad + * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable + * @arg ETH_DMATxDesc_TER : Transmit End of Ring + * @arg ETH_DMATxDesc_TCH : Second Address Chained + * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status + * @arg ETH_DMATxDesc_IHE : IP Header Error + * @arg ETH_DMATxDesc_ES : Error summary + * @arg ETH_DMATxDesc_JT : Jabber Timeout + * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush + * @arg ETH_DMATxDesc_PCE : Payload Checksum Error + * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission + * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver + * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision + * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions + * @arg ETH_DMATxDesc_VF : VLAN Frame + * @arg ETH_DMATxDesc_CC : Collision Count + * @arg ETH_DMATxDesc_ED : Excessive Deferral + * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory + * @arg ETH_DMATxDesc_DB : Deferred Bit + * @retval : The new state of ETH_DMATxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag)); + + if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @retval : The Transmit descriptor collision counter value. + */ +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift); +} + +/** + * @brief Set the specified DMA Tx Desc Own bit. + * @param DMATxDesc: Pointer on a Tx desc + * @retval : None + */ +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) +{ + /* Set the DMA Tx Desc Own bit */ + DMATxDesc->Status |= ETH_DMATxDesc_OWN; +} + +/** + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * @param DMATxDesc: Pointer on a Tx desc + * @param NewState: new state of the DMA Tx Desc transmit interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status |= ETH_DMATxDesc_IC; + } + else + { + /* Disable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC); + } +} + +/** + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * @param DMATxDesc: Pointer on a Tx desc + * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment + * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment + * @retval : None + */ +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment)); + + /* Selects the DMA Tx Desc Frame segment */ + DMATxDesc->Status |= DMATxDesc_FrameSegment; +} + +/** + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass + * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * @retval : None + */ +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum)); + + /* Set the selected DMA Tx desc checksum insertion control */ + DMATxDesc->Status |= DMATxDesc_Checksum; +} + +/** + * @brief Enables or disables the DMA Tx Desc CRC. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc CRC. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc CRC */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); + } + else + { + /* Disable the selected DMA Tx Desc CRC */ + DMATxDesc->Status |= ETH_DMATxDesc_DC; + } +} + +/** + * @brief Enables or disables the DMA Tx Desc end of ring. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc end of ring. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status |= ETH_DMATxDesc_TER; + } + else + { + /* Disable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); + } +} + +/** + * @brief Enables or disables the DMA Tx Desc second address chained. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc second address chained. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status |= ETH_DMATxDesc_TCH; + } + else + { + /* Disable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); + } +} + +/** + * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc padding for + * frame shorter than 64 bytes. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); + } + else + { + /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/ + DMATxDesc->Status |= ETH_DMATxDesc_DP; + } +} + +/** + * @brief Enables or disables the DMA Tx Desc time stamp. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc time stamp. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + } + else + { + /* Disable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); + } +} + +/** + * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. + * @param DMATxDesc: Pointer on a Tx desc + * @param BufferSize1: specifies the Tx desc buffer1 size. + * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used). + * @retval : None + */ +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1)); + assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2)); + + /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */ + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift)); +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff: Pointer on the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval : None + */ +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Initializes the DMA Rx descriptors in ring mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff1: Pointer on the first RxBuffer1 list + * @param RxBuff2: Pointer on the first RxBuffer2 list + * @param RxBuffCount: Number of the used Rx desc in the list + * Note: see decriptor skip length defined in ETH_DMA_InitStruct + * for the number of Words to skip between two unchained descriptors. + * @retval : None + */ +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + /* Set Buffer1 size */ + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (RxBuffCount-1)) + { + /* Set Receive End of Ring bit */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param ETH_DMARxDescFlag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame + * @arg ETH_DMARxDesc_ES: Error summary + * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame + * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame + * @arg ETH_DMARxDesc_LE: Frame size not matching with length field + * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow + * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame + * @arg ETH_DMARxDesc_FS: First descriptor of the frame + * @arg ETH_DMARxDesc_LS: Last descriptor of the frame + * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * @arg ETH_DMARxDesc_LC: Late collision occurred during reception + * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3 + * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception + * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface + * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits + * @arg ETH_DMARxDesc_CE: CRC error + * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * @retval : The new state of ETH_DMARxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag)); + if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Set the specified DMA Rx Desc Own bit. + * @param DMARxDesc: Pointer on a Rx desc + * @retval : None + */ +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) +{ + /* Set the DMA Rx Desc Own bit */ + DMARxDesc->Status |= ETH_DMARxDesc_OWN; +} + +/** + * @brief Returns the specified DMA Rx Desc frame length. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @retval : The Rx descriptor received frame length. + */ +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift); +} + +/** + * @brief Enables or disables the specified DMA Rx Desc receive interrupt. + * @param DMARxDesc: Pointer on a Rx desc + * @param NewState: new state of the specified DMA Rx Desc interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC); + } + else + { + /* Disable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; + } +} + +/** + * @brief Enables or disables the DMA Rx Desc end of ring. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param NewState: new state of the specified DMA Rx Desc end of ring. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + else + { + /* Disable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); + } +} + +/** + * @brief Enables or disables the DMA Rx Desc second address chained. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param NewState: new state of the specified DMA Rx Desc second address chained. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + } + else + { + /* Disable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); + } +} + +/** + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer. + * This parameter can be any one of the following values: + * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1 + * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 + * @retval : The Receive descriptor frame length. + */ +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer)); + + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) + { + /* Return the DMA Rx Desc buffer2 size */ + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift); + } + else + { + /* Return the DMA Rx Desc buffer1 size */ + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + } +} + +/*--------------------------------- DMA ------------------------------------*/ +/** + * @brief Resets all MAC subsystem internal registers and logic. + * @param None + * @retval : None + */ +void ETH_SoftwareReset(void) +{ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + ETH->DMABMR |= ETH_DMABMR_SR; +} + +/** + * @brief Checks whether the ETHERNET software reset bit is set or not. + * @param None + * @retval : The new state of DMA Bus Mode register SR bit (SET or RESET). + */ +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param ETH_DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag + * @arg ETH_DMA_FLAG_PMT : PMT flag + * @arg ETH_DMA_FLAG_MMC : MMC flag + * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access + * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr + * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ET : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Underflow flag + * @arg ETH_DMA_FLAG_RO : Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag + * @retval : The new state of ETH_DMA_FLAG (SET or RESET). + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG)); + if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the ETHERNET’s DMA pending flag. + * @param ETH_DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ETI : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag + * @arg ETH_DMA_FLAG_RO : Receive Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag + * @retval : None + */ +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG)); + + /* Clear the selected ETHERNET DMA FLAG */ + ETH->DMASR = (uint32_t) ETH_DMA_FLAG; +} + +/** + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * @param ETH_DMA_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt + * @arg ETH_DMA_IT_PMT : PMT interrupt + * @arg ETH_DMA_IT_MMC : MMC interrupt + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @retval : The new state of ETH_DMA_IT (SET or RESET). + */ +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT)); + if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the ETHERNET’s DMA IT pending bit. + * @param ETH_DMA_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ETI : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt + * @arg ETH_DMA_IT_RO : Receive Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @retval : None + */ +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + + /* Clear the selected ETHERNET DMA IT */ + ETH->DMASR = (uint32_t) ETH_DMA_IT; +} + +/** + * @brief Returns the ETHERNET DMA Transmit Process State. + * @param None + * @retval : The new ETHERNET DMA Transmit Process State: + * This can be one of the following values: + * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued + * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor + * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status + * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory + * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe + * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor + */ +uint32_t ETH_GetTransmitProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); +} + +/** + * @brief Returns the ETHERNET DMA Receive Process State. + * @param None + * @retval : The new ETHERNET DMA Receive Process State: + * This can be one of the following values: + * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued + * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor + * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet + * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable + * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor + * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory + */ +uint32_t ETH_GetReceiveProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); +} + +/** + * @brief Clears the ETHERNET transmit FIFO. + * @param None + * @retval : None + */ +void ETH_FlushTransmitFIFO(void) +{ + /* Set the Flush Transmit FIFO bit */ + ETH->DMAOMR |= ETH_DMAOMR_FTF; +} + +/** + * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. + * @param None + * @retval : The new state of ETHERNET flush transmit FIFO bit (SET or RESET). + */ +FlagStatus ETH_GetFlushTransmitFIFOStatus(void) +{ + FlagStatus bitstatus = RESET; + if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the DMA transmission. + * @param NewState: new state of the DMA transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMATransmissionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transmission */ + ETH->DMAOMR |= ETH_DMAOMR_ST; + } + else + { + /* Disable the DMA transmission */ + ETH->DMAOMR &= ~ETH_DMAOMR_ST; + } +} + +/** + * @brief Enables or disables the DMA reception. + * @param NewState: new state of the DMA reception. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMAReceptionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA reception */ + ETH->DMAOMR |= ETH_DMAOMR_SR; + } + else + { + /* Disable the DMA reception */ + ETH->DMAOMR &= ~ETH_DMAOMR_SR; + } +} + +/** + * @brief Enables or disables the specified ETHERNET DMA interrupts. + * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @param NewState: new state of the specified ETHERNET DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET DMA interrupts */ + ETH->DMAIER |= ETH_DMA_IT; + } + else + { + /* Disable the selected ETHERNET DMA interrupts */ + ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT); + } +} + +/** + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter + * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter + * @retval : The new state of ETHERNET DMA overflow Flag (SET or RESET). + */ +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow)); + + if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. + * @param None + * @retval : The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_GetRxOverflowMissedFrameCounter(void) +{ + return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift)); +} + +/** + * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. + * @param None + * @retval : The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) +{ + return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); +} + +/** + * @brief Get the ETHERNET DMA DMACHTDR register value. + * @param None + * @retval : The value of the current Tx desc start address. + */ +uint32_t ETH_GetCurrentTxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHTDR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHRDR register value. + * @param None + * @retval : The value of the current Rx desc start address. + */ +uint32_t ETH_GetCurrentRxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHRDR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHTBAR register value. + * @param None + * @retval : The value of the current Tx desc buffer address. + */ +uint32_t ETH_GetCurrentTxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHTBAR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHRBAR register value. + * @param None + * @retval : The value of the current Rx desc buffer address. + */ +uint32_t ETH_GetCurrentRxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHRBAR)); +} + +/** + * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand + * register: (the data written could be anything). This forces + * the DMA to resume transmission. + * @param None + * @retval : None. + */ +void ETH_ResumeDMATransmission(void) +{ + ETH->DMATPDR = 0; +} + +/** + * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand + * register: (the data written could be anything). This forces + * the DMA to resume reception. + * @param None + * @retval : None. + */ +void ETH_ResumeDMAReception(void) +{ + ETH->DMARPDR = 0; +} + +/*--------------------------------- PMT ------------------------------------*/ +/** + * @brief Reset Wakeup frame filter register pointer. + * @param None + * @retval : None + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; +} + +/** + * @brief Populates the remote wakeup frame registers. + * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer + * data (8 words). + * @retval : None + */ +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) +{ + uint32_t i = 0; + + /* Fill Remote Wake-up Frame Filter register with Buffer data */ + for(i =0; iMACRWUFFR = Buffer[i]; + } +} + +/** + * @brief Enables or disables any unicast packet filtered by the MAC + * (DAF) address recognition to be a wake-up frame. + * @param NewState: new state of the MAC Global Unicast Wake-Up. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; + } + else + { + /* Disable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; + } +} + +/** + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * @param ETH_PMT_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset + * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPR : Magic Packet Received + * @retval : The new state of ETHERNET PMT Flag (SET or RESET). + */ +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG)); + + if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the MAC Wake-Up Frame Detection. + * @param NewState: new state of the MAC Wake-Up Frame Detection. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; + } + else + { + /* Disable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + } +} + +/** + * @brief Enables or disables the MAC Magic Packet Detection. + * @param NewState: new state of the MAC Magic Packet Detection. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MagicPacketDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Magic Packet Detection */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; + } + else + { + /* Disable the MAC Magic Packet Detection */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + } +} + +/** + * @brief Enables or disables the MAC Power Down. + * @param NewState: new state of the MAC Power Down. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_PowerDownCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Power Down */ + /* This puts the MAC in power down mode */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; + } + else + { + /* Disable the MAC Power Down */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; + } +} + +/*--------------------------------- MMC ------------------------------------*/ +/** + * @brief Enables or disables the MMC Counter Freeze. + * @param NewState: new state of the MMC Counter Freeze. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MMC Counter Freeze */ + ETH->MMCCR |= ETH_MMCCR_MCF; + } + else + { + /* Disable the MMC Counter Freeze */ + ETH->MMCCR &= ~ETH_MMCCR_MCF; + } +} + +/** + * @brief Enables or disables the MMC Reset On Read. + * @param NewState: new state of the MMC Reset On Read. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCResetOnReadCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MMC Counter reset on read */ + ETH->MMCCR |= ETH_MMCCR_ROR; + } + else + { + /* Disable the MMC Counter reset on read */ + ETH->MMCCR &= ~ETH_MMCCR_ROR; + } +} + +/** + * @brief Enables or disables the MMC Counter Stop Rollover. + * @param NewState: new state of the MMC Counter Stop Rollover. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCCounterRolloverCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Disable the MMC Counter Stop Rollover */ + ETH->MMCCR &= ~ETH_MMCCR_CSR; + } + else + { + /* Enable the MMC Counter Stop Rollover */ + ETH->MMCCR |= ETH_MMCCR_CSR; + } +} + +/** + * @brief Resets the MMC Counters. + * @param None + * @retval : None + */ +void ETH_MMCCountersReset(void) +{ + /* Resets the MMC Counters */ + ETH->MMCCR |= ETH_MMCCR_CR; +} + +/** + * @brief Enables or disables the specified ETHERNET MMC interrupts. + * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt + * sources to be enabled or disabled. + * This parameter can be any combination of Tx interrupt or + * any combination of Rx interrupt (but not both)of the following values: + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value + * @param NewState: new state of the specified ETHERNET MMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + /* Remove egister mak from IT */ + ETH_MMC_IT &= 0xEFFFFFFF; + + /* ETHERNET MMC Rx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCRIMR |= ETH_MMC_IT; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCTIMR |= ETH_MMC_IT; + } + } +} + +/** + * @brief Checks whether the specified ETHERNET MMC IT is set or not. + * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value + * @retval : The value of ETHERNET MMC IT (SET or RESET). + */ +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); + + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + /* ETHERNET MMC Rx interrupts selected */ + /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ + if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ + if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/** + * @brief Get the specified ETHERNET MMC register value. + * @param ETH_MMCReg: specifies the ETHERNET MMC register. + * This parameter can be one of the following values: + * @arg ETH_MMCCR : MMC CR register + * @arg ETH_MMCRIR : MMC RIR register + * @arg ETH_MMCTIR : MMC TIR register + * @arg ETH_MMCRIMR : MMC RIMR register + * @arg ETH_MMCTIMR : MMC TIMR register + * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register + * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register + * @arg ETH_MMCTGFCR : MMC TGFCR register + * @arg ETH_MMCRFCECR : MMC RFCECR register + * @arg ETH_MMCRFAECR : MMC RFAECR register + * @arg ETH_MMCRGUFCR : MMC RGUFCRregister + * @retval : The value of ETHERNET MMC Register value. + */ +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) +{ + /* Check the parameters */ + assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg)); + + /* Return the selected register value */ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); +} +/*--------------------------------- PTP ------------------------------------*/ + +/** + * @brief Updated the PTP block for fine correction with the Time Stamp + * Addend register value. + * @param None + * @retval : None + */ +void ETH_EnablePTPTimeStampAddend(void) +{ + /* Enable the PTP block update with the Time Stamp Addend register value */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; +} + +/** + * @brief Enable the PTP Time Stamp interrupt trigger + * @param None + * @retval : None + */ +void ETH_EnablePTPTimeStampInterruptTrigger(void) +{ + /* Enable the PTP target time interrupt */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; +} + +/** + * @brief Updated the PTP system time with the Time Stamp Update register + * value. + * @param None + * @retval : None + */ +void ETH_EnablePTPTimeStampUpdate(void) +{ + /* Enable the PTP system time update with the Time Stamp Update register value */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; +} + +/** + * @brief Initialize the PTP Time Stamp + * @param None + * @retval : None + */ +void ETH_InitializePTPTimeStamp(void) +{ + /* Initialize the PTP Time Stamp */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; +} + +/** + * @brief Selects the PTP Update method + * @param UpdateMethod: the PTP Update method + * This parameter can be one of the following values: + * @arg ETH_PTP_FineUpdate : Fine Update method + * @arg ETH_PTP_CoarseUpdate : Coarse Update method + * @retval : None + */ +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_UPDATE(UpdateMethod)); + + if (UpdateMethod != ETH_PTP_CoarseUpdate) + { + /* Enable the PTP Fine Update method */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; + } + else + { + /* Disable the PTP Coarse Update method */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); + } +} + +/** + * @brief Enables or disables the PTP time stamp for transmit and receive frames. + * @param NewState: new state of the PTP time stamp for transmit and receive frames + * This parameter can be: ENABLE or DISABLE. + * @retval : None + */ +void ETH_PTPTimeStampCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSE; + } + else + { + /* Disable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); + } +} + +/** + * @brief Checks whether the specified ETHERNET PTP flag is set or not. + * @param ETH_PTP_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PTP_FLAG_TSARU : Addend Register Update + * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable + * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update + * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize + * @retval : The new state of ETHERNET PTP Flag (SET or RESET). + */ +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG)); + + if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Sets the system time Sub-Second Increment value. + * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value. + * @retval : None + */ +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue)); + /* Set the PTP Sub-Second Increment Register */ + ETH->PTPSSIR = SubSecondValue; +} + +/** + * @brief Sets the Time Stamp update sign and values. + * @param Sign: specifies the PTP Time update value sign. + * This parameter can be one of the following values: + * @arg ETH_PTP_PositiveTime : positive time value. + * @arg ETH_PTP_NegativeTime : negative time value. + * @param SecondValue: specifies the PTP Time update second value. + * @param SubSecondValue: specifies the PTP Time update sub-second value. + * this is a 31 bit value. bit32 correspond to the sign. + * @retval : None + */ +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); + assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); + /* Set the PTP Time Update High Register */ + ETH->PTPTSHUR = SecondValue; + + /* Set the PTP Time Update Low Register with sign */ + ETH->PTPTSLUR = Sign | SubSecondValue; +} + +/** + * @brief Sets the Time Stamp Addend value. + * @param Value: specifies the PTP Time Stamp Addend Register value. + * @retval : None + */ +void ETH_SetPTPTimeStampAddend(uint32_t Value) +{ + /* Set the PTP Time Stamp Addend Register */ + ETH->PTPTSAR = Value; +} + +/** + * @brief Sets the Target Time registers values. + * @param HighValue: specifies the PTP Target Time High Register value. + * @param LowValue: specifies the PTP Target Time Low Register value. + * @retval : None + */ +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) +{ + /* Set the PTP Target Time High Register */ + ETH->PTPTTHR = HighValue; + /* Set the PTP Target Time Low Register */ + ETH->PTPTTLR = LowValue; +} + +/** + * @brief Get the specified ETHERNET PTP register value. + * @param ETH_PTPReg: specifies the ETHERNET PTP register. + * This parameter can be one of the following values: + * @arg ETH_PTPTSCR : Sub-Second Increment Register + * @arg ETH_PTPSSIR : Sub-Second Increment Register + * @arg ETH_PTPTSHR : Time Stamp High Register + * @arg ETH_PTPTSLR : Time Stamp Low Register + * @arg ETH_PTPTSHUR : Time Stamp High Update Register + * @arg ETH_PTPTSLUR : Time Stamp Low Update Register + * @arg ETH_PTPTSAR : Time Stamp Addend Register + * @arg ETH_PTPTTHR : Target Time High Register + * @arg ETH_PTPTTLR : Target Time Low Register + * @retval : The value of ETHERNET PTP Register value. + */ +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg)); + + /* Return the selected register value */ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); +} + +/** + * @brief Initializes the DMA Tx descriptors in chain mode with PTP. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list + * @param TxBuff: Pointer on the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval : None + */ +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + DMAPTPTxDescToSet = DMAPTPTxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab+i; + /* Set Second Address Chained bit and enable PTP */ + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } + /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */ + (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; + (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; + } + /* Store on the last DMAPTPTxDescTab desc status record the first list address */ + (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab; + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list + * @param RxBuff: Pointer on the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval : None + */ +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */ + (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; + (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; + } + /* Store on the last DMAPTPRxDescTab desc status record the first list address */ + (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab; + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Transmits a packet, from application buffer, pointed by ppkt with + * Time Stamp values. + * @param ppkt: pointer to application packet buffer to transmit. + * @param FrameLength: Tx Packet size. + * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values. + * @retval : ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission + */ +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) +{ + uint32_t offset = 0, timeout = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); + } + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + /* Wait for ETH_DMATxDesc_TTSS flag to be set */ + do + { + timeout++; + } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + /* Clear the DMATxDescToSet status register TTSS flag */ + DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; + *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; + *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; + /* Update the ENET DMA current descriptor */ + /* Chained Mode */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr); + if(DMAPTPTxDescToSet->Status != 0) + { + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status); + } + else + { + DMAPTPTxDescToSet++; + } + } + else /* Ring Mode */ + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer read: this will + be the first Tx descriptor in this case */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer read */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Receives a packet and copies it to memory pointed by ppkt with + * Time Stamp values. + * @param ppkt: pointer to application packet receive buffer. + * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values. + * @retval : ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct + */ +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) +{ + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ENET or CPU */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + } + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; + *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr); + if(DMAPTPRxDescToGet->Status != 0) + { + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status); + } + else + { + DMAPTPRxDescToGet++; + } + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return Frame Length/ERROR */ + return (framelength); +} +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/clock-arch.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/clock-arch.c new file mode 100644 index 00000000..d8225115 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/clock-arch.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.c,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * Implementation of architecture-specific clock functionality + * \author + * Adam Dunkels + */ + +#include "clock-arch.h" +#include "header.h" + +/*---------------------------------------------------------------------------*/ +clock_time_t +clock_time(void) +{ + return (clock_time_t)TimerGet(); +} +/*---------------------------------------------------------------------------*/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/clock-arch.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/clock-arch.h new file mode 100644 index 00000000..aa97f0e7 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/clock-arch.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: clock-arch.h,v 1.2 2006/06/12 08:00:31 adam Exp $ + */ + +#ifndef __CLOCK_ARCH_H__ +#define __CLOCK_ARCH_H__ + +typedef int clock_time_t; +#define CLOCK_CONF_SECOND 1000 + +#endif /* __CLOCK_ARCH_H__ */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/netdev.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/netdev.c new file mode 100644 index 00000000..3ce42bdf --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/netdev.c @@ -0,0 +1,442 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Author: Adam Dunkels + * + * $Id: netdev.c,v 1.8 2006/06/07 08:39:58 adam Exp $ + */ + + +/*---------------------------------------------------------------------------*/ +#include "uip.h" +#include "uip_arp.h" +#include "header.h" +#include "stm32_eth.h" /* STM32 ethernet library */ +#include /* for memcpy */ + + +/*---------------------------------------------------------------------------*/ +#define NETDEV_DEFAULT_MACADDR0 (0x08) +#define NETDEV_DEFAULT_MACADDR1 (0x00) +#define NETDEV_DEFAULT_MACADDR2 (0x27) +#define NETDEV_DEFAULT_MACADDR3 (0x69) +#define NETDEV_DEFAULT_MACADDR4 (0x5B) +#define NETDEV_DEFAULT_MACADDR5 (0x45) + + +/*---------------------------------------------------------------------------*/ +static void netdev_TxDscrInit(void); +static void netdev_RxDscrInit(void); + +/*---------------------------------------------------------------------------*/ +typedef union _TranDesc0_t +{ + uint32_t Data; + struct { + uint32_t DB : 1; + uint32_t UF : 1; + uint32_t ED : 1; + uint32_t CC : 4; + uint32_t VF : 1; + uint32_t EC : 1; + uint32_t LC : 1; + uint32_t NC : 1; + uint32_t LSC : 1; + uint32_t IPE : 1; + uint32_t FF : 1; + uint32_t JT : 1; + uint32_t ES : 1; + uint32_t IHE : 1; + uint32_t : 3; + uint32_t TCH : 1; + uint32_t TER : 1; + uint32_t CIC : 2; + uint32_t : 2; + uint32_t DP : 1; + uint32_t DC : 1; + uint32_t FS : 1; + uint32_t LSEG : 1; + uint32_t IC : 1; + uint32_t OWN : 1; + }; +} TranDesc0_t, * pTranDesc0_t; + +typedef union _TranDesc1_t +{ + uint32_t Data; + struct { + uint32_t TBS1 :13; + uint32_t : 3; + uint32_t TBS2 :12; + uint32_t : 3; + }; +} TranDesc1_t, * pTranDesc1_t; + +typedef union _RecDesc0_t +{ + uint32_t Data; + struct { + uint32_t RMAM_PCE : 1; + uint32_t CE : 1; + uint32_t DE : 1; + uint32_t RE : 1; + uint32_t RWT : 1; + uint32_t FT : 1; + uint32_t LC : 1; + uint32_t IPHCE : 1; + uint32_t LS : 1; + uint32_t FS : 1; + uint32_t VLAN : 1; + uint32_t OE : 1; + uint32_t LE : 1; + uint32_t SAF : 1; + uint32_t DERR : 1; + uint32_t ES : 1; + uint32_t FL :14; + uint32_t AFM : 1; + uint32_t OWN : 1; + }; +} RecDesc0_t, * pRecDesc0_t; + +typedef union _recDesc1_t +{ + uint32_t Data; + struct { + uint32_t RBS1 :13; + uint32_t : 1; + uint32_t RCH : 1; + uint32_t RER : 1; + uint32_t RBS2 :14; + uint32_t DIC : 1; + }; +} RecDesc1_t, * pRecDesc1_t; + +typedef union _EnetDmaDesc_t +{ + uint32_t Data[4]; + // Rx DMA descriptor + struct + { + RecDesc0_t RxDesc0; + RecDesc1_t RxDesc1; + uint32_t * pBuffer; + union + { + uint32_t * pBuffer2; + union _EnetDmaDesc_t * pEnetDmaNextDesc; + }; + } Rx; + // Tx DMA descriptor + struct + { + TranDesc0_t TxDesc0; + TranDesc1_t TxDesc1; + uint32_t * pBuffer1; + union + { + uint32_t * pBuffer2; + union _EnetDmaDesc_t * pEnetDmaNextDesc; + }; + } Tx; +} EnetDmaDesc_t, * pEnetDmaDesc_t; + + +/*---------------------------------------------------------------------------*/ +uint8_t RxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4))); +uint8_t TxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4))); + +EnetDmaDesc_t EnetDmaRx __attribute__((aligned (128))); +EnetDmaDesc_t EnetDmaTx __attribute__ ((aligned (128))); + + +/*---------------------------------------------------------------------------*/ +void netdev_init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + ETH_InitTypeDef ETH_InitStructure; + + /* Enable ETHERNET clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx | + RCC_AHB1Periph_ETH_MAC_Rx | RCC_AHB1Periph_ETH_MAC_PTP, ENABLE); + + + /* Enable GPIOs clocks */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | + RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG, ENABLE); + + /* Enable SYSCFG clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + /*Select RMII Interface*/ + SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII); + + /* ETHERNET pins configuration */ + /* PA + ETH_RMII_REF_CLK: PA1 + ETH_RMII_MDIO: PA2 + ETH_RMII_MDINT: PA3 + ETH_RMII_CRS_DV: PA7 + */ + + /* Configure PA1, PA2, PA3 and PA7*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_7; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Connect PA1, PA2, PA3 and PA7 to ethernet module*/ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH); + + /* PB + ETH_RMII_TX_EN: PG11 + */ + + /* Configure PG11*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* Connect PG11 to ethernet module*/ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH); + + /* PC + ETH_RMII_MDC: PC1 + ETH_RMII_RXD0: PC4 + ETH_RMII_RXD1: PC5 + */ + + /* Configure PC1, PC4 and PC5*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Connect PC1, PC4 and PC5 to ethernet module*/ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH); + + /* PG + ETH_RMII_TXD0: PG13 + ETH_RMII_TXD1: PG14 + */ + + /* Configure PG13 and PG14*/ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOG, &GPIO_InitStructure); + + /* Connect PG13 and PG14 to ethernet module*/ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH); + GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH); + + /* Reset ETHERNET on AHB Bus */ + ETH_DeInit(); + + /* Software reset */ + ETH_SoftwareReset(); + + /* Wait for software reset */ + while(ETH_GetSoftwareResetStatus()==SET); + + /* ETHERNET Configuration ------------------------------------------------------*/ + /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */ + ETH_StructInit(Ð_InitStructure); + + /* Fill ETH_InitStructure parametrs */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable ; + ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; + ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable; + ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; + ETH_InitStructure.ETH_Speed = ETH_Speed_100M; + + unsigned int PhyAddr; + union { + uint32_t HI_LO; + struct + { + uint16_t LO; + uint16_t HI; + }; + } PHYID; + for(PhyAddr = 0; 32 > PhyAddr; PhyAddr++) + { + // datasheet for the ks8721bl ethernet controller (http://www.micrel.com/_PDF/Ethernet/datasheets/ks8721bl-sl.pdf) + // page 20 --> PHY Identifier 1 and 2 + PHYID.HI = ETH_ReadPHYRegister(PhyAddr,2); // 0x0022 + PHYID.LO = ETH_ReadPHYRegister(PhyAddr,3); // 0x1619 + if ((0x00221619 == PHYID.HI_LO) || (0x0007C0F1 == PHYID.HI_LO)) + break; + } + /* Configure Ethernet */ + ETH_Init(Ð_InitStructure, PhyAddr); + + netdev_TxDscrInit(); + netdev_RxDscrInit(); + ETH_Start(); +} + + +/*---------------------------------------------------------------------------*/ +void netdev_init_mac(void) +{ + struct uip_eth_addr macAddress; + + /* set the default MAC address */ + macAddress.addr[0] = NETDEV_DEFAULT_MACADDR0; + macAddress.addr[1] = NETDEV_DEFAULT_MACADDR1; + macAddress.addr[2] = NETDEV_DEFAULT_MACADDR2; + macAddress.addr[3] = NETDEV_DEFAULT_MACADDR3; + macAddress.addr[4] = NETDEV_DEFAULT_MACADDR4; + macAddress.addr[5] = NETDEV_DEFAULT_MACADDR5; + uip_setethaddr(macAddress); +} + + +/*---------------------------------------------------------------------------*/ +unsigned int netdev_read(void) +{ + uint32_t size; + /*check for validity*/ + if(0 == EnetDmaRx.Rx.RxDesc0.OWN) + { + /*Get the size of the packet*/ + size = EnetDmaRx.Rx.RxDesc0.FL; // CRC + memcpy(uip_buf, RxBuff, size); //string.h library*/ + } + else + { + return 0; + } + /* Give the buffer back to ENET */ + EnetDmaRx.Rx.RxDesc0.OWN = 1; + /* Start the receive operation */ + ETH->DMARPDR = 1; + /* Return no error */ + return size; +} + + +/*---------------------------------------------------------------------------*/ +void netdev_send(void) +{ + while(EnetDmaTx.Tx.TxDesc0.OWN); + + /* Copy the application buffer to the driver buffer + Using this MEMCOPY_L2L_BY4 makes the copy routine faster + than memcpy */ + memcpy(TxBuff, uip_buf, uip_len); + + /* Assign ENET address to Temp Tx Array */ + EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff; + + /* Setting the Frame Length*/ + EnetDmaTx.Tx.TxDesc0.Data = 0; + EnetDmaTx.Tx.TxDesc0.TCH = 1; + EnetDmaTx.Tx.TxDesc0.LSEG = 1; + EnetDmaTx.Tx.TxDesc0.FS = 1; + EnetDmaTx.Tx.TxDesc0.DC = 0; + EnetDmaTx.Tx.TxDesc0.DP = 0; + + EnetDmaTx.Tx.TxDesc1.Data = 0; + EnetDmaTx.Tx.TxDesc1.TBS1 = (uip_len&0xFFF); + + /* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/ + EnetDmaTx.Tx.TxDesc0.OWN = 1; + + /* Start the transmit operation */ + ETH->DMATPDR = 1; +} + + +/*---------------------------------------------------------------------------*/ +static void netdev_RxDscrInit(void) +{ + /* Initialization */ + /* Assign temp Rx array to the ENET buffer */ + EnetDmaRx.Rx.pBuffer = (uint32_t *)RxBuff; + + /* Initialize RX ENET Status and control */ + EnetDmaRx.Rx.RxDesc0.Data = 0; + + /* Initialize the next descriptor- In our case its single descriptor */ + EnetDmaRx.Rx.pEnetDmaNextDesc = &EnetDmaRx; + + EnetDmaRx.Rx.RxDesc1.Data = 0; + EnetDmaRx.Rx.RxDesc1.RER = 0; // end of ring + EnetDmaRx.Rx.RxDesc1.RCH = 1; // end of ring + + /* Set the max packet size */ + EnetDmaRx.Rx.RxDesc1.RBS1 = UIP_CONF_BUFFER_SIZE; + + /* Setting the VALID bit */ + EnetDmaRx.Rx.RxDesc0.OWN = 1; + /* Setting the RX NEXT Descriptor Register inside the ENET */ + ETH->DMARDLAR = (uint32_t)&EnetDmaRx; +} + + +/*---------------------------------------------------------------------------*/ +static void netdev_TxDscrInit(void) +{ + /* ENET Start Address */ + EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff; + + /* Next Descriptor Address */ + EnetDmaTx.Tx.pEnetDmaNextDesc = &EnetDmaTx; + + /* Initialize ENET status and control */ + EnetDmaTx.Tx.TxDesc0.TCH = 1; + EnetDmaTx.Tx.TxDesc0.Data = 0; + EnetDmaTx.Tx.TxDesc1.Data = 0; + /* Tx next set to Tx descriptor base */ + ETH->DMATDLAR = (uint32_t)&EnetDmaTx; + +} diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/netdev.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/netdev.h new file mode 100644 index 00000000..4ea59ce5 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/netdev.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2001, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Adam Dunkels. + * 4. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack. + * + * $Id: netdev.h,v 1.1 2002/01/10 06:22:56 adam Exp $ + * + */ + +#ifndef __NETDEV_H__ +#define __NETDEV_H__ + +void netdev_init(void); +void netdev_init_mac(void); +unsigned int netdev_read(void); +void netdev_send(void); + +#endif /* __NETDEV_H__ */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/uip-conf.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/uip-conf.h new file mode 100644 index 00000000..fd9ba0dd --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/lib/uip/uip-conf.h @@ -0,0 +1,151 @@ +/** + * \addtogroup uipopt + * @{ + */ + +/** + * \name Project-specific configuration options + * @{ + * + * uIP has a number of configuration options that can be overridden + * for each project. These are kept in a project-specific uip-conf.h + * file and all configuration names have the prefix UIP_CONF. + */ + +/* + * Copyright (c) 2006, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the uIP TCP/IP stack + * + * $Id: uip-conf.h,v 1.6 2006/06/12 08:00:31 adam Exp $ + */ + +/** + * \file + * An example uIP configuration file + * \author + * Adam Dunkels + */ + +#ifndef __UIP_CONF_H__ +#define __UIP_CONF_H__ + + +/** + * 8 bit datatype + * + * This typedef defines the 8-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef unsigned char u8_t; + +/** + * 16 bit datatype + * + * This typedef defines the 16-bit type used throughout uIP. + * + * \hideinitializer + */ +typedef unsigned short u16_t; + +/** + * Statistics datatype + * + * This typedef defines the dataype used for keeping statistics in + * uIP. + * + * \hideinitializer + */ +typedef unsigned short uip_stats_t; + +/** + * Maximum number of TCP connections. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_CONNECTIONS 1 + +/** + * Maximum number of listening TCP ports. + * + * \hideinitializer + */ +#define UIP_CONF_MAX_LISTENPORTS 1 + +/** + * uIP buffer size. + * + * \hideinitializer + */ +#define UIP_CONF_BUFFER_SIZE 1600 + +/** + * CPU byte order. + * + * \hideinitializer + */ +#define UIP_CONF_BYTE_ORDER LITTLE_ENDIAN + +/** + * Logging on or off + * + * \hideinitializer + */ +#define UIP_CONF_LOGGING 0 + +/** + * UDP support on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP 0 + +/** + * UDP checksums on or off + * + * \hideinitializer + */ +#define UIP_CONF_UDP_CHECKSUMS 1 + +/** + * uIP statistics on or off + * + * \hideinitializer + */ +#define UIP_CONF_STATISTICS 0 + +/* Here we include the header file for the application(s) we use in + our project. */ +#include "boot.h" +#include "net.h" + +#endif /* __UIP_CONF_H__ */ + +/** @} */ +/** @} */ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/main.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/main.c index 6c16174f..79fc8509 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/main.c +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/main.c @@ -53,6 +53,8 @@ void main(void) { /* initialize the microcontroller */ Init(); + /* initialize the network application */ + NetInit(); /* initialize the bootloader interface */ BootComInit(); @@ -61,6 +63,8 @@ void main(void) { /* toggle LED with a fixed frequency */ LedToggle(); + /* run the network task */ + NetTask(); /* check for bootloader activation request */ BootComCheckActivationRequest(); } diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/makefile b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/makefile index 6b7f50e6..dcb69988 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/makefile +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/makefile @@ -43,10 +43,19 @@ irq.c \ irq.h \ led.c \ led.h \ +net.c \ +net.h \ main.c \ timer.c \ timer.h \ vectors.c \ +./lib/ethernetlib/inc/stm32_eth.h \ +./lib/ethernetlib/src/stm32_eth.c \ +./lib/uip/clock-arch.c \ +./lib/uip/clock-arch.h \ +./lib/uip/netdev.c \ +./lib/uip/netdev.h \ +./lib/uip/uip-conf.h \ ./lib/stdperiphlib/stm32f4xx_conf.h \ ./lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/misc.h \ ./lib/stdperiphlib/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h \ @@ -111,7 +120,27 @@ vectors.c \ ./lib/stdperiphlib/CMSIS/Include/core_cmInstr.h \ ./lib/stdperiphlib/CMSIS/Device/ST/STM32F4xx/Source/system_stm32f4xx.c \ ./lib/stdperiphlib/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ -./lib/stdperiphlib/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h +./lib/stdperiphlib/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ +../../../Source/third_party/uip/uip/clock.h \ +../../../Source/third_party/uip/uip/lc-addrlabels.h \ +../../../Source/third_party/uip/uip/lc-switch.h \ +../../../Source/third_party/uip/uip/lc.h \ +../../../Source/third_party/uip/uip/pt.h \ +../../../Source/third_party/uip/uip/uip-fw.c \ +../../../Source/third_party/uip/uip/uip-fw.h \ +../../../Source/third_party/uip/uip/uip-neighbor.h \ +../../../Source/third_party/uip/uip/uip-split.h \ +../../../Source/third_party/uip/uip/uip.c \ +../../../Source/third_party/uip/uip/uip.h \ +../../../Source/third_party/uip/uip/uiplib.c \ +../../../Source/third_party/uip/uip/uiplib.h \ +../../../Source/third_party/uip/uip/uipopt.h \ +../../../Source/third_party/uip/uip/uip_arch.h \ +../../../Source/third_party/uip/uip/uip_arp.c \ +../../../Source/third_party/uip/uip/uip_arp.h \ +../../../Source/third_party/uip/uip/uip_timer.c \ +../../../Source/third_party/uip/uip/uip_timer.h + #|---------------------------------------------------------------------------------------| diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/memory.x b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/memory.x index 4dd1f56a..69f68128 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/memory.x +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/memory.x @@ -1,6 +1,6 @@ MEMORY { - FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 1024K-32K + FLASH (rx) : ORIGIN = 0x0800C000, LENGTH = 1024K-48K SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K } diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/net.c b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/net.c new file mode 100644 index 00000000..39728207 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/net.c @@ -0,0 +1,211 @@ +/************************************************************************************//** +* \file Demo\ARMCM3_LM3S_EK_LM3S6965_IAR\Prog\net.c +* \brief Network application for the uIP TCP/IP stack. +* \ingroup Prog_ARMCM3_LM3S_EK_LM3S6965_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2014 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ +#include "netdev.h" +#include "uip.h" +#include "uip_arp.h" + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Delta time for the uIP periodic timer. */ +#define NET_UIP_PERIODIC_TIMER_MS (500) +/** \brief Delta time for the uIP ARP timer. */ +#define NET_UIP_ARP_TIMER_MS (10000) +/** \brief Macro for accessing the Ethernet header information in the buffer */ +#define NET_UIP_HEADER_BUF ((struct uip_eth_hdr *)&uip_buf[0]) + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Holds the time out value of the uIP periodic timer. */ +static unsigned long periodicTimerTimeOut; +/** \brief Holds the time out value of the uIP ARP timer. */ +static unsigned long ARPTimerTimeOut; + + +/************************************************************************************//** +** \brief Initializes the TCP/IP network communication interface. +** \return none. +** +****************************************************************************************/ +void NetInit(void) +{ + uip_ipaddr_t ipaddr; + + /* initialize the network device */ + netdev_init(); + /* initialize the timer variables */ + periodicTimerTimeOut = TimerGet() + NET_UIP_PERIODIC_TIMER_MS; + ARPTimerTimeOut = TimerGet() + NET_UIP_ARP_TIMER_MS; + /* initialize the uIP TCP/IP stack. */ + uip_init(); + /* set the IP address */ + uip_ipaddr(ipaddr, BOOT_COM_NET_IPADDR0, BOOT_COM_NET_IPADDR1, BOOT_COM_NET_IPADDR2, + BOOT_COM_NET_IPADDR3); + uip_sethostaddr(ipaddr); + /* set the network mask */ + uip_ipaddr(ipaddr, BOOT_COM_NET_NETMASK0, BOOT_COM_NET_NETMASK1, BOOT_COM_NET_NETMASK2, + BOOT_COM_NET_NETMASK3); + uip_setnetmask(ipaddr); + /* set the gateway address */ + uip_ipaddr(ipaddr, BOOT_COM_NET_GATEWAY0, BOOT_COM_NET_GATEWAY1, BOOT_COM_NET_GATEWAY2, + BOOT_COM_NET_GATEWAY3); + uip_setdraddr(ipaddr); + /* start listening on the configured port for XCP transfers on TCP/IP */ + uip_listen(HTONS(BOOT_COM_NET_PORT)); + /* initialize the MAC and set the MAC address */ + netdev_init_mac(); +} /*** end of NetInit ***/ + + +/************************************************************************************//** +** \brief The uIP network application that detects the XCP connect command on the +** port used by the bootloader. This indicates that the bootloader should +** be activated. +** \return none. +** +****************************************************************************************/ +void NetApp(void) +{ + unsigned char *newDataPtr; + + if (uip_connected()) + { + return; + } + + if (uip_newdata()) + { + /* a new XCP command was received. check if this is the connect command and in this + * case activate the bootloader. with XCP on TCP/IP the first 4 bytes contain a + * counter value in which we are not really interested. + */ + newDataPtr = uip_appdata; + newDataPtr += 4; + /* check if this was an XCP CONNECT command */ + if ((newDataPtr[0] == 0xff) && (newDataPtr[1] == 0x00)) + { + /* connection request received so start the bootloader */ + BootActivate(); + } + } +} /*** end of NetApp ***/ + + +/************************************************************************************//** +** \brief Runs the TCP/IP server task. +** \return none. +** +****************************************************************************************/ +void NetTask(void) +{ + unsigned long connection; + unsigned long packetLen; + + /* check for an RX packet and read it. */ + packetLen = netdev_read(); + if(packetLen > 0) + { + /* set uip_len for uIP stack usage */ + uip_len = (unsigned short)packetLen; + + /* process incoming IP packets here. */ + if(NET_UIP_HEADER_BUF->type == htons(UIP_ETHTYPE_IP)) + { + uip_arp_ipin(); + uip_input(); + /* if the above function invocation resulted in data that + * should be sent out on the network, the global variable + * uip_len is set to a value > 0. + */ + if(uip_len > 0) + { + uip_arp_out(); + netdev_send(); + uip_len = 0; + } + } + /* process incoming ARP packets here. */ + else if(NET_UIP_HEADER_BUF->type == htons(UIP_ETHTYPE_ARP)) + { + uip_arp_arpin(); + + /* if the above function invocation resulted in data that + * should be sent out on the network, the global variable + * uip_len is set to a value > 0. + */ + if(uip_len > 0) + { + netdev_send(); + uip_len = 0; + } + } + } + + /* process TCP/IP Periodic Timer here. */ + if (TimerGet() >= periodicTimerTimeOut) + { + periodicTimerTimeOut += NET_UIP_PERIODIC_TIMER_MS; + for (connection = 0; connection < UIP_CONNS; connection++) + { + uip_periodic(connection); + /* If the above function invocation resulted in data that + * should be sent out on the network, the global variable + * uip_len is set to a value > 0. + */ + if(uip_len > 0) + { + uip_arp_out(); + netdev_send(); + uip_len = 0; + } + } + } + + /* process ARP Timer here. */ + if (TimerGet() >= ARPTimerTimeOut) + { + ARPTimerTimeOut += NET_UIP_ARP_TIMER_MS; + uip_arp_timer(); + } +} /*** end of NetServerTask ***/ + + +/*********************************** end of net.c **************************************/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/net.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/net.h new file mode 100644 index 00000000..538e6664 --- /dev/null +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_GCC/Prog/net.h @@ -0,0 +1,66 @@ +/************************************************************************************//** +* \file Demo\ARMCM3_LM3S_EK_LM3S6965_IAR\Prog\net.h +* \brief Network application for the uIP TCP/IP stack. +* \ingroup Prog_ARMCM3_LM3S_EK_LM3S6965_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2014 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef NET_H +#define NET_H + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +#ifndef UIP_APPCALL +#define UIP_APPCALL NetApp +#endif /* UIP_APPCALL */ + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Define the uip_tcp_appstate_t datatype. This is the state of our tcp/ip + * application, and the memory required for this state is allocated together + * with each TCP connection. One application state for each TCP connection. + */ +typedef struct net_state +{ + unsigned char unused; +} uip_tcp_appstate_t; + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void NetInit(void); +void NetApp(void); +void NetTask(void); + + +#endif /* NET_H */ +/*********************************** end of net.h **************************************/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/bin/openbtl_olimex_stm32e407.out b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/bin/openbtl_olimex_stm32e407.out index cc21cfd4..3caf1703 100644 Binary files a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/bin/openbtl_olimex_stm32e407.out and b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/bin/openbtl_olimex_stm32e407.out differ diff --git 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a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/blt_conf.h b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/blt_conf.h index 208fffd3..2be19eea 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/blt_conf.h +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/blt_conf.h @@ -110,6 +110,82 @@ #define BOOT_COM_UART_CHANNEL_INDEX (5) +/* The NET communication interface for firmware updates via TCP/IP is selected by setting + * the BOOT_COM_NET_ENABLE configurable to 1. The maximum amount of data bytes in a + * message for data transmission and reception is set through BOOT_COM_NET_TX_MAX_DATA + * and BOOT_COM_NET_RX_MAX_DATA, respectively. The default IP address is configured + * with the macros BOOT_COM_NET_IPADDRx. The default netmask is configued with the macros + * BOOT_COM_NET_NETMASKx. The default gateway is configured with the macros + * BOOT_COM_NET_GATEWAYx. The bootloader acts and a TCP/IP server. The port the server + * listen on for connections is configured with BOOT_COM_NET_PORT. + */ +/** \brief Enable/disable the NET transport layer. */ +#define BOOT_COM_NET_ENABLE (1) +/** \brief Configure number of bytes in the target->host data packet. */ +#define BOOT_COM_NET_TX_MAX_DATA (64) +/** \brief Configure number of bytes in the host->target data packet. */ +#define BOOT_COM_NET_RX_MAX_DATA (64) +/** \brief Configure the port that the TCP/IP server listens on */ +#define BOOT_COM_NET_PORT (1000) +/** \brief Configure the 1st byte of the IP address */ +#define BOOT_COM_NET_IPADDR0 (169) +/** \brief Configure the 2nd byte of the IP address */ +#define BOOT_COM_NET_IPADDR1 (254) +/** \brief Configure the 3rd byte of the IP address */ +#define BOOT_COM_NET_IPADDR2 (19) +/** \brief Configure the 4th byte of the IP address */ +#define BOOT_COM_NET_IPADDR3 (63) +/** \brief Configure the 1st byte of the network mask */ +#define BOOT_COM_NET_NETMASK0 (255) +/** \brief Configure the 2nd byte of the network mask */ +#define BOOT_COM_NET_NETMASK1 (255) +/** \brief Configure the 3rd byte of the network mask */ +#define BOOT_COM_NET_NETMASK2 (0) +/** \brief Configure the 4th byte of the network mask */ +#define BOOT_COM_NET_NETMASK3 (0) +/** \brief Configure the 1st byte of the gateway address */ +#define BOOT_COM_NET_GATEWAY0 (169) +/** \brief Configure the 2nd byte of the gateway address */ +#define BOOT_COM_NET_GATEWAY1 (254) +/** \brief Configure the 3rd byte of the gateway address */ +#define BOOT_COM_NET_GATEWAY2 (19) +/** \brief Configure the 4th byte of the gateway address */ +#define BOOT_COM_NET_GATEWAY3 (1) +/** \brief Enable/disable a hook function that is called when the IP address is about + * to be set. This allows a dynamic override of the BOOT_COM_NET_IPADDRx values. + */ +#define BOOT_COM_NET_IPADDR_HOOK_ENABLE (0) +/** \brief Enable/disable a hook function that is called when the netmask is about + * to be set. This allows a dynamic override of the BOOT_COM_NET_NETMASKx values. + */ +#define BOOT_COM_NET_NETMASK_HOOK_ENABLE (0) +/** \brief Enable/disable a hook function that is called when the gateway address is + * about to be set. This allows a dynamic override of the BOOT_COM_NET_GATEWAYx + * values. + */ +#define BOOT_COM_NET_GATEWAY_HOOK_ENABLE (0) + + +/**************************************************************************************** +* B A C K D O O R C O N F I G U R A T I O N +****************************************************************************************/ +#if (BOOT_COM_NET_ENABLE > 0) +/* Override the default time that the backdoor is open if firmware updates via TCP/IP + * are supported. in this case a reactivation of the bootloader results in a re- + * initialization of the ethernet MAC. when directly connected to the ethernet port of + * a PC this will go relatively fast (depending on what MS Windows is being used), but + * when connected to the network via a router this can take several seconds. feel free to + * shorten/lengthen this time for finetuning. the only downside of a long backdoor open + * time is that the starting of the user program will also be delayed for this time. + * + * Also note that when the target is directly connected to the ethernet port of a PC, + * the checkbox "Automatically retry socket connection" should be checked in the + * Microboot settings. if connecting via a router the uncheck this checkbox. + */ +#define BACKDOOR_ENTRY_TIMEOUT_MS (10000) +#endif + + /**************************************************************************************** * F I L E S Y S T E M I N T E R F A C E C O N F I G U R A T I O N ****************************************************************************************/ diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.dbgdt b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.dbgdt index 824f59ea..e53c94ff 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.dbgdt +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.dbgdt @@ -19,7 +19,7 @@ - 124272727 + 125272727 @@ -39,7 +39,7 @@ - + TabID-30829-10739 @@ -55,7 +55,7 @@ - 0 + 0 TabID-8810-10743 @@ -67,7 +67,7 @@ - 0 + 0 TabID-19558-10746 @@ -77,20 +77,20 @@ - 0 + 0 - TextEditor$WS_DIR$\..\main.c0000033296329630TextEditor$WS_DIR$\..\blt_conf.h0000057470847080100000010000001 + TextEditor$WS_DIR$\..\main.c0000042296329630TextEditor$WS_DIR$\..\blt_conf.h00000132873587350100000010000001 - iaridepm.enu1debuggergui.enu1-2-2741198-2-2200200104167198413104167737103-2-2741461-2-2200200104167198413241146737103-2-21981922-2-219242001002083198413104167198413 + iaridepm.enu1debuggergui.enu1-2-2741199-2-2201200104688198413104688737103-2-2741460-2-2201200104688198413240625737103-2-21981922-2-219242001002083198413104688198413 diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.dni b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.dni index 89ad5e39..071dba60 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.dni +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.dni @@ -9,7 +9,7 @@ TriggerName=main LimitSize=0 ByteLimit=50 [DebugChecksum] -Checksum=-2067015847 +Checksum=-1915269868 [Exceptions] StopOnUncaught=_ 0 StopOnThrow=_ 0 diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.wsdt b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.wsdt index e3cba71c..aba1407b 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.wsdt +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/settings/stm32f407.wsdt @@ -12,7 +12,7 @@ - 338272727 + 322272727 @@ -26,7 +26,7 @@ 19027326200Build - FileFunctionLine200700100300 + FileFunctionLine20070010030017367 @@ -38,24 +38,24 @@ Workspace - stm32f407stm32f407/Bootstm32f407/Outputstm32f407/libstm32f407/src + stm32f407stm32f407/Bootstm32f407/Boot/libstm32f407/Boot/lib/uipstm32f407/Outputstm32f407/Sourcestm32f407/Source/ARMCM4_STM32stm32f407/Source/ARMCM4_STM32/IARstm32f407/Source/third_partystm32f407/libstm32f407/src - 0TabID-19870-1384BuildBuild0 + 0TabID-19870-1384BuildBuildTabID-11216-22197Debug LogDebug-Log0 - TextEditor$WS_DIR$\..\main.c0000033296329630TextEditor$WS_DIR$\..\blt_conf.h0000057470847080100000010000001 + TextEditor$WS_DIR$\..\main.c0000042296329630TextEditor$WS_DIR$\..\blt_conf.h00000132873587350100000010000001 - iaridepm.enu1-2-2963412-2-2200200104167198413215625957341-2-2963420-2-2200200104167198413219792957341 + iaridepm.enu1-2-2963413-2-2200200104167198413216146957341-2-2963413-2-2200200104167198413216146957341 diff --git a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/stm32f407.dep b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/stm32f407.dep index 58aa4fe2..468f918a 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/stm32f407.dep +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/stm32f407.dep @@ -2,261 +2,17 @@ 2 - 66273092 + 1032076476 Debug - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_rtc.h - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rtc.c - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_sdio.c - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_sdio.h - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_spi.c - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_spi.h - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_syscfg.c - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_syscfg.h - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_tim.c - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc\stm32f4xx_tim.h - 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$PROJ_DIR$\..\obj\stm32f4xx_cryp_des.lst + $PROJ_DIR$\..\obj\stm32f4xx_gpio.pbi + $PROJ_DIR$\..\obj\stm32_eth.o + $PROJ_DIR$\..\obj\stm32_eth.pbi + $PROJ_DIR$\..\obj\stm32_eth.lst + $PROJ_DIR$\..\obj\stm32f4xx_flash.pbi + $PROJ_DIR$\..\obj\stm32f4xx_rng.o + $PROJ_DIR$\..\obj\stm32f4xx_rtc.o + $PROJ_DIR$\..\obj\stm32f4xx_sdio.o + $PROJ_DIR$\..\obj\stm32f4xx_cryp_tdes.pbi + $PROJ_DIR$\..\obj\stm32f4xx_spi.o + $PROJ_DIR$\..\obj\can.pbi + $PROJ_DIR$\..\obj\can.o + $PROJ_DIR$\..\obj\can.lst + $PROJ_DIR$\..\obj\stm32f4xx_cryp_tdes.o + $PROJ_DIR$\..\obj\stm32f4xx_adc.o + $PROJ_DIR$\..\obj\stm32f4xx_dbgmcu.o + $PROJ_DIR$\..\obj\stm32f4xx_can.o + $PROJ_DIR$\..\obj\stm32f4xx_cryp.o + $PROJ_DIR$\..\obj\stm32f4xx_hash_md5.o + $PROJ_DIR$\..\obj\stm32f4xx_hash_sha1.o + $PROJ_DIR$\..\obj\stm32f4xx_crc.o + $PROJ_DIR$\..\..\..\..\Source\fatfs\src\option\ccsbcs.c + $PROJ_DIR$\..\obj\stm32f4xx_dcmi.pbi + $TOOLKIT_DIR$\inc\c\yvals.h + $TOOLKIT_DIR$\inc\c\xencoding_limits.h + $PROJ_DIR$\..\obj\stm32f4xx_dac.o + $PROJ_DIR$\..\obj\stm32f4xx_dcmi.o + $PROJ_DIR$\..\obj\stm32f4xx_dma.o + $PROJ_DIR$\..\obj\stm32f4xx_flash.o + $PROJ_DIR$\..\obj\stm32f4xx_exti.o + $PROJ_DIR$\..\obj\stm32f4xx_fsmc.o + $PROJ_DIR$\..\obj\file.o + $PROJ_DIR$\..\obj\boot.pbi + $PROJ_DIR$\..\obj\timer.o + $PROJ_DIR$\..\obj\cop.o + $PROJ_DIR$\..\obj\xcp.o + $PROJ_DIR$\..\obj\stm32f4xx_hash.o + $PROJ_DIR$\..\obj\stm32f4xx_gpio.o + $PROJ_DIR$\..\obj\backdoor.pbi + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $PROJ_DIR$\..\obj\stm32f4xx_can.pbi + $PROJ_DIR$\..\obj\stm32f4xx_pwr.o + $PROJ_DIR$\..\obj\stm32f4xx_rcc.pbi + $PROJ_DIR$\..\obj\stm32f4xx_adc.pbi + $TOOLKIT_DIR$\inc\c\string.h + $TOOLKIT_DIR$\inc\c\ycheck.h + $PROJ_DIR$\..\obj\stm32f4xx_wwdg.pbi + $PROJ_DIR$\..\obj\stm32f4xx_crc.pbi + $PROJ_DIR$\..\obj\stm32f4xx_wwdg.o + $PROJ_DIR$\..\obj\cop.pbi + $PROJ_DIR$\..\obj\file.pbi + $PROJ_DIR$\..\obj\vectors.o + $TOOLKIT_DIR$\inc\c\xlocale_c.h + $TOOLKIT_DIR$\inc\c\xlocaleuse.h + $PROJ_DIR$\..\..\..\..\Source\third_party\fatfs\src\option\ccsbcs.c + $TOOLKIT_DIR$\inc\c\stdint.h + $PROJ_DIR$\..\obj\misc.pbi + $PROJ_DIR$\..\obj\stm32f4xx_dac.pbi + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $PROJ_DIR$\..\obj\stm32f4xx_exti.pbi + $PROJ_DIR$\..\obj\stm32f4xx_iwdg.pbi + $PROJ_DIR$\..\obj\stm32f4xx_fsmc.pbi + $PROJ_DIR$\..\obj\stm32f4xx_fsmc.lst + $TOOLKIT_DIR$\lib\rt7M_tl.a + $PROJ_DIR$\..\obj\stm32f4xx_syscfg.lst + $PROJ_DIR$\..\obj\uart.o + $PROJ_DIR$\..\obj\stm32f4xx_sdio.lst + $PROJ_DIR$\..\obj\stm32f4xx_hash.lst + $PROJ_DIR$\..\obj\stm32f4xx_dac.lst + $PROJ_DIR$\..\obj\stm32f4xx_dma.lst + $PROJ_DIR$\..\obj\stm32f4xx_dcmi.lst + $TOOLKIT_DIR$\lib\dl7M_tln.a + $PROJ_DIR$\..\obj\stm32f4xx_rng.lst + $PROJ_DIR$\..\obj\stm32f4xx_hash_sha1.lst + $PROJ_DIR$\..\obj\system_stm32f4xx.lst + $PROJ_DIR$\..\obj\stm32f4xx_rtc.lst + $PROJ_DIR$\..\obj\stm32f4xx_iwdg.lst + $PROJ_DIR$\..\obj\stm32f4xx_rcc.lst + $PROJ_DIR$\..\obj\stm32f4xx_pwr.lst + $PROJ_DIR$\..\obj\stm32f4xx_gpio.lst + $PROJ_DIR$\..\obj\stm32f4xx_wwdg.lst + $PROJ_DIR$\..\obj\stm32f4xx_flash.lst + $PROJ_DIR$\..\obj\stm32f4xx_usart.lst + $PROJ_DIR$\..\obj\stm32f4xx_i2c.lst + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_STM32\IAR\memory.x + $PROJ_DIR$\..\obj\clock-arch.o + $PROJ_DIR$\..\obj\nvm.lst + $PROJ_DIR$\..\obj\clock-arch.pbi + $PROJ_DIR$\..\obj\net.o + $PROJ_DIR$\..\obj\net.pbi + $PROJ_DIR$\..\obj\nvm.pbi + $PROJ_DIR$\..\obj\stm32f4xx_cryp_des.o + $PROJ_DIR$\..\obj\stm32f4x7_eth.pbi + $PROJ_DIR$\..\obj\system_stm32f4xx.pbi + $TOOLKIT_DIR$\inc\c\wchar.h + $TOOLKIT_DIR$\inc\c\xlocale.h + $PROJ_DIR$\..\obj\stm32f4x7_eth.o + $PROJ_DIR$\..\obj\vectors.lst + $TOOLKIT_DIR$\inc\c\ctype.h + $TOOLKIT_DIR$\inc\c\xtls.h + $PROJ_DIR$\..\obj\system_stm32f4xx.o + $PROJ_DIR$\..\obj\clock-arch.lst + $PROJ_DIR$\..\obj\nvm.o + $PROJ_DIR$\..\obj\stm32f4x7_eth.lst + $PROJ_DIR$\..\obj\uip.lst + $PROJ_DIR$\..\obj\netdev.o + $PROJ_DIR$\..\obj\net.lst + $PROJ_DIR$\..\obj\netdev.pbi + $PROJ_DIR$\..\obj\stm32f4xx_cryp_aes.o + $PROJ_DIR$\..\obj\uip_arp.o + $PROJ_DIR$\..\obj\uip_timer.lst + $PROJ_DIR$\..\obj\uiplib.o + $PROJ_DIR$\..\obj\netdev.lst + $PROJ_DIR$\..\obj\uiplib.lst + $PROJ_DIR$\..\obj\uip.o + $PROJ_DIR$\..\obj\uip-fw.lst + $PROJ_DIR$\..\obj\stm32f4xx_cryp_tdes.lst + $PROJ_DIR$\..\obj\uip-fw.pbi + $PROJ_DIR$\..\obj\uip.pbi + $PROJ_DIR$\..\obj\stm32f4xx_syscfg.pbi + $PROJ_DIR$\..\obj\uip_arp.pbi + $PROJ_DIR$\..\obj\stm32f4xx_adc.lst + $PROJ_DIR$\..\obj\uiplib.pbi + $PROJ_DIR$\..\obj\uip_arp.lst + $PROJ_DIR$\..\obj\uip_timer.pbi + $PROJ_DIR$\..\obj\stm32f4xx_exti.lst - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rtc.c + $PROJ_DIR$\..\lib\ethernetlib\src\stm32_eth.c ICCARM - 137 183 + 229 227 BICOMP - 173 + 228 ICCARM - 0 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 3 5 7 9 11 13 253 + 0 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 0 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 3 5 7 9 11 13 253 + 0 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_sdio.c + $PROJ_DIR$\..\lib\fatfs\mmc.c ICCARM - 133 184 + 207 202 BICOMP - 160 + 218 ICCARM - 3 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 5 7 9 11 13 253 + 270 271 249 265 181 284 250 141 175 205 92 94 10 5 281 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 3 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 5 7 9 11 13 253 + 270 271 249 265 181 284 250 141 175 205 92 94 10 5 281 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 - [ROOT_NODE] - - - ILINK - 84 143 - - - - - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_spi.c + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\misc.c ICCARM - 139 187 + 195 180 BICOMP - 172 + 282 ICCARM - 5 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 7 9 11 13 253 + 9 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 BICOMP - 5 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 7 9 11 13 253 + 9 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_syscfg.c + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_adc.c ICCARM - 132 175 + 347 240 BICOMP - 108 + 269 ICCARM - 7 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 9 11 13 253 + 12 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 14 17 19 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 7 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 9 11 13 253 + 12 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 14 17 19 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_tim.c + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_can.c ICCARM - 141 157 + 222 242 BICOMP - 170 + 266 ICCARM - 9 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 11 13 253 + 14 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 17 19 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 9 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 11 13 253 + 14 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 17 19 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_usart.c + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_crc.c ICCARM - 130 163 + 190 246 BICOMP - 149 + 273 ICCARM - 11 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 9 13 253 + 17 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 19 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 11 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 9 13 253 + 17 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 19 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 - $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_wwdg.c + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp.c ICCARM - 127 57 + 193 243 BICOMP - 63 + 142 ICCARM - 13 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 9 11 253 + 19 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 13 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 9 11 253 + 19 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 - $PROJ_DIR$\..\lib\stdperiphlib\CMSIS\Device\ST\STM32F4xx\Source\system_stm32f4xx.c + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_aes.c ICCARM - 129 87 + 223 334 BICOMP - 88 + 174 ICCARM - 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 9 11 13 253 + 19 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 9 11 13 253 + 19 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 - $PROJ_DIR$\..\hooks.c + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_des.c ICCARM - 222 216 + 225 317 + + + BICOMP + 217 + + + + + ICCARM + 19 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 + + + BICOMP + 19 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 + + + + + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_tdes.c + + + ICCARM + 342 239 BICOMP @@ -512,52 +581,140 @@ ICCARM - 46 33 42 16 53 25 50 30 28 32 44 52 39 36 249 48 55 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 9 11 13 253 + 19 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 46 33 42 16 53 25 50 30 28 32 44 52 39 36 249 48 55 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 9 11 13 253 + 19 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 24 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 - $PROJ_DIR$\..\main.c + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dac.c ICCARM - 225 215 + 294 251 BICOMP - 235 + 283 ICCARM - 46 33 42 16 53 25 50 30 28 32 44 52 39 36 249 48 55 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 9 11 13 253 + 24 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 46 33 42 16 53 25 50 30 28 32 44 52 39 36 249 48 55 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 9 11 13 253 + 24 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 26 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 - $PROJ_DIR$\..\..\..\..\Source\ARMCM4_STM32\IAR\cstart.s + [ROOT_NODE] - AARM - 236 + ILINK + 182 194 - $PROJ_DIR$\..\..\..\..\Source\ARMCM4_STM32\IAR\vectors.c + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dbgmcu.c ICCARM - 95 66 + 189 241 + + + BICOMP + 132 + + + + + ICCARM + 26 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 + + + BICOMP + 26 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 28 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 + + + + + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dcmi.c + + + ICCARM + 296 252 + + + BICOMP + 248 + + + + + ICCARM + 28 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 + + + BICOMP + 28 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 30 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 + + + + + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dma.c + + + ICCARM + 295 253 + + + BICOMP + 146 + + + + + ICCARM + 30 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 32 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 + + + + + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_exti.c + + + ICCARM + 351 255 + + + BICOMP + 285 + + + + + ICCARM + 32 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 + + + BICOMP + 32 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 34 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 + + + + + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_flash.c + + + ICCARM + 307 254 BICOMP @@ -567,181 +724,476 @@ ICCARM - 46 33 42 16 53 25 50 30 28 32 44 52 39 36 249 48 55 + 34 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 32 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 46 33 42 16 53 25 50 30 28 32 44 52 39 36 249 48 55 + 34 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 32 36 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 - $PROJ_DIR$\..\..\..\..\Source\ARMCM4_STM32\can.c + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_fsmc.c ICCARM - 190 189 + 288 256 BICOMP - 188 + 287 ICCARM - 46 33 42 16 53 25 50 30 28 32 44 52 39 36 249 48 55 + 36 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 32 34 40 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 46 33 42 16 53 25 50 30 28 32 44 52 39 36 249 48 55 + 36 10 5 281 271 249 265 181 284 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272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 9 11 13 253 + 40 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 32 34 36 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 46 33 42 16 53 25 50 30 28 32 44 52 39 36 249 48 55 254 250 70 59 200 56 83 73 201 162 247 159 81 251 246 15 259 256 258 261 263 268 270 272 274 276 278 280 284 282 288 290 292 294 296 0 3 5 7 9 11 13 253 + 40 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 32 34 36 38 44 46 48 50 52 54 56 58 60 62 64 66 9 - $PROJ_DIR$\..\..\..\..\Source\ARMCM4_STM32\nvm.c + $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash_md5.c ICCARM - 96 93 + 186 244 BICOMP - 90 + 221 ICCARM - 46 33 42 16 53 25 50 30 28 32 44 52 39 36 249 48 55 + 40 10 5 281 271 249 265 181 284 250 141 6 135 179 7 1 68 15 12 14 17 19 24 26 28 30 32 34 36 38 44 46 48 50 52 54 56 58 60 62 64 66 9 BICOMP - 46 33 42 16 53 25 50 30 28 32 44 52 39 36 249 48 55 + 40 10 5 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a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/stm32f407.ewp b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/stm32f407.ewp index 970906df..80b1491d 100644 --- a/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/stm32f407.ewp +++ b/Target/Demo/ARMCM4_STM32_Olimex_STM32E407_IAR/Boot/ide/stm32f407.ewp @@ -299,11 +299,15 @@ $PROJ_DIR$\..\lib\stdperiphlib $PROJ_DIR$\..\lib\stdperiphlib\CMSIS\Device\ST\STM32F4xx\Include $PROJ_DIR$\..\lib\stdperiphlib\CMSIS\Include + $PROJ_DIR$\..\lib\ethernetlib\inc + $PROJ_DIR$\..\lib\ethernetlib\src $PROJ_DIR$\..\lib\fatfs + $PROJ_DIR$\..\lib\uip $PROJ_DIR$\..\lib\stdperiphlib\STM32F4xx_StdPeriph_Driver\inc $PROJ_DIR$\..\..\..\..\Source $PROJ_DIR$\..\..\..\..\Source\ARMCM4_STM32 $PROJ_DIR$\..\..\..\..\Source\third_party\fatfs\src + $PROJ_DIR$\..\..\..\..\Source\third_party\uip\uip