+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_ssi.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/ssi.h"
+
+//*****************************************************************************
+//
+// A mapping of timer base address to interrupt number.
+//
+//*****************************************************************************
+static const uint32_t g_ppui32SSIIntMap[][2] =
+{
+ { SSI0_BASE, INT_SSI0_BLIZZARD },
+ { SSI1_BASE, INT_SSI1_BLIZZARD },
+ { SSI2_BASE, INT_SSI2_BLIZZARD },
+ { SSI3_BASE, INT_SSI3_BLIZZARD },
+};
+static const uint_fast8_t g_ui8SSIIntMapRows =
+ sizeof(g_ppui32SSIIntMap) / sizeof(g_ppui32SSIIntMap[0]);
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks an SSI base address.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! This function determines if a SSI module base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_SSIBaseValid(uint32_t ui32Base)
+{
+ return((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE) ||
+ (ui32Base == SSI2_BASE) || (ui32Base == SSI3_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Returns the interrupt number of SSI module .
+//!
+//! \param ui32Base is the base address of the SSI module.
+//!
+//! This function returns the interrupt number for the SSI module with the base
+//! address passed in the \e ui32Base parameter.
+//!
+//! \return Returns an SSI interrupt number, or 0 if the interrupt does not
+//! exist.
+//
+//*****************************************************************************
+static uint32_t
+_SSIIntNumberGet(uint32_t ui32Base)
+{
+ uint_fast8_t ui8Idx, ui8Rows;
+ const uint32_t (*ppui32SSIIntMap)[2];
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ ppui32SSIIntMap = g_ppui32SSIIntMap;
+ ui8Rows = g_ui8SSIIntMapRows;
+
+ //
+ // Loop through the table that maps SSI base addresses to interrupt
+ // numbers.
+ //
+ for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++)
+ {
+ //
+ // See if this base address matches.
+ //
+ if(ppui32SSIIntMap[ui8Idx][0] == ui32Base)
+ {
+ //
+ // Return the corresponding interrupt number.
+ //
+ return(ppui32SSIIntMap[ui8Idx][1]);
+ }
+ }
+
+ //
+ // The base address could not be found, so return an error.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Configures the synchronous serial interface.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32SSIClk is the rate of the clock supplied to the SSI module.
+//! \param ui32Protocol specifies the data transfer protocol.
+//! \param ui32Mode specifies the mode of operation.
+//! \param ui32BitRate specifies the clock rate.
+//! \param ui32DataWidth specifies number of bits transferred per frame.
+//!
+//! This function configures the synchronous serial interface. It sets
+//! the SSI protocol, mode of operation, bit rate, and data width.
+//!
+//! The \e ui32Protocol parameter defines the data frame format. The
+//! \e ui32Protocol parameter can be one of the following values:
+//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
+//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola
+//! frame formats encode the following polarity and phase configurations:
+//!
+//!
+//! Polarity Phase Mode
+//! 0 0 SSI_FRF_MOTO_MODE_0
+//! 0 1 SSI_FRF_MOTO_MODE_1
+//! 1 0 SSI_FRF_MOTO_MODE_2
+//! 1 1 SSI_FRF_MOTO_MODE_3
+//!
+//!
+//! The \e ui32Mode parameter defines the operating mode of the SSI module.
+//! The SSI module can operate as a master or slave; if it is a slave, the SSI
+//! can be configured to disable output on its serial output line. The
+//! \e ui32Mode parameter can be one of the following values:
+//! \b SSI_MODE_MASTER, \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
+//!
+//! The \e ui32BitRate parameter defines the bit rate for the SSI. This bit
+//! rate must satisfy the following clock ratio criteria:
+//!
+//! - FSSI >= 2 * bit rate (master mode); this speed cannot exceed 25 MHz.
+//! - FSSI >= 12 * bit rate or 6 * bit rate (slave modes), depending on the
+//! capability of the specific microcontroller
+//!
+//! where FSSI is the frequency of the clock supplied to the SSI module.
+//!
+//! The \e ui32DataWidth parameter defines the width of the data transfers and
+//! can be a value between 4 and 16, inclusive.
+//!
+//! The peripheral clock is the same as the processor clock. This value is
+//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
+//! constant and known (to save the code/execution overhead of a call to
+//! SysCtlClockGet()).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
+ uint32_t ui32Protocol, uint32_t ui32Mode,
+ uint32_t ui32BitRate, uint32_t ui32DataWidth)
+{
+ uint32_t ui32MaxBitRate;
+ uint32_t ui32RegVal;
+ uint32_t ui32PreDiv;
+ uint32_t ui32SCR;
+ uint32_t ui32SPH_SPO;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+ ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) ||
+ (ui32Protocol == SSI_FRF_MOTO_MODE_1) ||
+ (ui32Protocol == SSI_FRF_MOTO_MODE_2) ||
+ (ui32Protocol == SSI_FRF_MOTO_MODE_3) ||
+ (ui32Protocol == SSI_FRF_TI) ||
+ (ui32Protocol == SSI_FRF_NMW));
+ ASSERT((ui32Mode == SSI_MODE_MASTER) ||
+ (ui32Mode == SSI_MODE_SLAVE) ||
+ (ui32Mode == SSI_MODE_SLAVE_OD));
+ ASSERT(((ui32Mode == SSI_MODE_MASTER) &&
+ (ui32BitRate <= (ui32SSIClk / 2))) ||
+ ((ui32Mode != SSI_MODE_MASTER) &&
+ (ui32BitRate <= (ui32SSIClk / 12))));
+ ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256));
+ ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16));
+
+ //
+ // Set the mode.
+ //
+ ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
+ ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
+ HWREG(ui32Base + SSI_O_CR1) = ui32RegVal;
+
+ //
+ // Set the clock predivider.
+ //
+ ui32MaxBitRate = ui32SSIClk / ui32BitRate;
+ ui32PreDiv = 0;
+ do
+ {
+ ui32PreDiv += 2;
+ ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1;
+ }
+ while(ui32SCR > 255);
+ HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv;
+
+ //
+ // Set protocol and clock rate.
+ //
+ ui32SPH_SPO = (ui32Protocol & 3) << 6;
+ ui32Protocol &= SSI_CR0_FRF_M;
+ ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol |
+ (ui32DataWidth - 1);
+ HWREG(ui32Base + SSI_O_CR0) = ui32RegVal;
+}
+
+//*****************************************************************************
+//
+//! Enables the synchronous serial interface.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! This function enables operation of the synchronous serial interface. The
+//! synchronous serial interface must be configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE;
+}
+
+//*****************************************************************************
+//
+//! Disables the synchronous serial interface.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! This function disables operation of the synchronous serial interface.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the synchronous serial interface.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! synchronous serial interface interrupt occurs.
+//!
+//! This function registers the handler to be called when an SSI interrupt
+//! occurs. This function enables the global interrupt in the interrupt
+//! controller; specific SSI interrupts must be enabled via SSIIntEnable(). If
+//! necessary, it is the interrupt handler's responsibility to clear the
+//! interrupt source via SSIIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+ uint32_t ui32Int;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Determine the interrupt number based on the SSI port.
+ //
+ ui32Int = _SSIIntNumberGet(ui32Base);
+
+ ASSERT(ui32Int != 0);
+
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(ui32Int, pfnHandler);
+
+ //
+ // Enable the synchronous serial interface interrupt.
+ //
+ IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the synchronous serial interface.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//!
+//! This function clears the handler to be called when an SSI interrupt
+//! occurs. This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntUnregister(uint32_t ui32Base)
+{
+ uint32_t ui32Int;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Determine the interrupt number based on the SSI port.
+ //
+ ui32Int = _SSIIntNumberGet(ui32Base);
+
+ ASSERT(ui32Int != 0);
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ui32Int);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Enables individual SSI interrupt sources.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated SSI interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor. The \e ui32IntFlags
+//! parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or
+//! \b SSI_RXOR values.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ui32Base + SSI_O_IM) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual SSI interrupt sources.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the indicated SSI interrupt sources. The
+//! \e ui32IntFlags parameter can be any of the \b SSI_TXFF, \b SSI_RXFF,
+//! \b SSI_RXTO, or \b SSI_RXOR values.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ui32Base + SSI_O_IM) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param bMasked is \b false if the raw interrupt status is required or
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the SSI module. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
+//
+//*****************************************************************************
+uint32_t
+SSIIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ui32Base + SSI_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ui32Base + SSI_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears SSI interrupt sources.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! This function clears the specified SSI interrupt sources so that they no
+//! longer assert. This function must be called in the interrupt handler to
+//! keep the interrupts from being triggered again immediately upon exit. The
+//! \e ui32IntFlags parameter can consist of either or both the \b SSI_RXTO and
+//! \b SSI_RXOR values.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Puts a data element into the SSI transmit FIFO.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32Data is the data to be transmitted over the SSI interface.
+//!
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module. If there is no space available in the transmit FIFO,
+//! this function waits until there is space available before returning.
+//!
+//! \note The upper 32 - N bits of \e ui32Data are discarded by the hardware,
+//! where N is the data width as configured by SSIConfigSetExpClk(). For
+//! example, if the interface is configured for 8-bit data width, the upper 24
+//! bits of \e ui32Data are discarded.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDataPut(uint32_t ui32Base, uint32_t ui32Data)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+ ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) &
+ SSI_CR0_DSS_M))) == 0);
+
+ //
+ // Wait until there is space.
+ //
+ while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF))
+ {
+ }
+
+ //
+ // Write the data to the SSI.
+ //
+ HWREG(ui32Base + SSI_O_DR) = ui32Data;
+}
+
+//*****************************************************************************
+//
+//! Puts a data element into the SSI transmit FIFO.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param ui32Data is the data to be transmitted over the SSI interface.
+//!
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module. If there is no space in the FIFO, then this function
+//! returns a zero.
+//!
+//! \note The upper 32 - N bits of \e ui32Data are discarded by the hardware,
+//! where N is the data width as configured by SSIConfigSetExpClk(). For
+//! example, if the interface is configured for 8-bit data width, the upper 24
+//! bits of \e ui32Data are discarded.
+//!
+//! \return Returns the number of elements written to the SSI transmit FIFO.
+//
+//*****************************************************************************
+int32_t
+SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+ ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) &
+ SSI_CR0_DSS_M))) == 0);
+
+ //
+ // Check for space to write.
+ //
+ if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)
+ {
+ HWREG(ui32Base + SSI_O_DR) = ui32Data;
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets a data element from the SSI receive FIFO.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param pui32Data is a pointer to a storage location for data that was
+//! received over the SSI interface.
+//!
+//! This function gets received data from the receive FIFO of the specified
+//! SSI module and places that data into the location specified by the
+//! \e pui32Data parameter. If there is no data available, this function waits
+//! until data is received before returning.
+//!
+//! \note Only the lower N bits of the value written to \e pui32Data contain
+//! valid data, where N is the data width as configured by
+//! SSIConfigSetExpClk(). For example, if the interface is configured for
+//! 8-bit data width, only the lower 8 bits of the value written to
+//! \e pui32Data contain valid data.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Wait until there is data to be read.
+ //
+ while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE))
+ {
+ }
+
+ //
+ // Read data from SSI.
+ //
+ *pui32Data = HWREG(ui32Base + SSI_O_DR);
+}
+
+//*****************************************************************************
+//
+//! Gets a data element from the SSI receive FIFO.
+//!
+//! \param ui32Base specifies the SSI module base address.
+//! \param pui32Data is a pointer to a storage location for data that was
+//! received over the SSI interface.
+//!
+//! This function gets received data from the receive FIFO of the specified SSI
+//! module and places that data into the location specified by the \e ui32Data
+//! parameter. If there is no data in the FIFO, then this function returns a
+//! zero.
+//!
+//! \note Only the lower N bits of the value written to \e pui32Data contain
+//! valid data, where N is the data width as configured by
+//! SSIConfigSetExpClk(). For example, if the interface is configured for
+//! 8-bit data width, only the lower 8 bits of the value written to
+//! \e pui32Data contain valid data.
+//!
+//! \return Returns the number of elements read from the SSI receive FIFO.
+//
+//*****************************************************************************
+int32_t
+SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Check for data to read.
+ //
+ if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)
+ {
+ *pui32Data = HWREG(ui32Base + SSI_O_DR);
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables SSI DMA operation.
+//!
+//! \param ui32Base is the base address of the SSI port.
+//! \param ui32DMAFlags is a bit mask of the DMA features to enable.
+//!
+//! This function enables the specified SSI DMA features. The SSI can be
+//! configured to use DMA for transmit and/or receive data transfers.
+//! The \e ui32DMAFlags parameter is the logical OR of any of the following
+//! values:
+//!
+//! - SSI_DMA_RX - enable DMA for receive
+//! - SSI_DMA_TX - enable DMA for transmit
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the SSI.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Set the requested bits in the SSI DMA control register.
+ //
+ HWREG(ui32Base + SSI_O_DMACTL) |= ui32DMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables SSI DMA operation.
+//!
+//! \param ui32Base is the base address of the SSI port.
+//! \param ui32DMAFlags is a bit mask of the DMA features to disable.
+//!
+//! This function is used to disable SSI DMA features that were enabled
+//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The
+//! \e ui32DMAFlags parameter is the logical OR of any of the following values:
+//!
+//! - SSI_DMA_RX - disable DMA for receive
+//! - SSI_DMA_TX - disable DMA for transmit
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Clear the requested bits in the SSI DMA control register.
+ //
+ HWREG(ui32Base + SSI_O_DMACTL) &= ~ui32DMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Determines whether the SSI transmitter is busy or not.
+//!
+//! \param ui32Base is the base address of the SSI port.
+//!
+//! This function allows the caller to determine whether all transmitted bytes
+//! have cleared the transmitter hardware. If \b false is returned, then the
+//! transmit FIFO is empty and all bits of the last transmitted word have left
+//! the hardware shift register.
+//!
+//! \return Returns \b true if the SSI is transmitting or \b false if all
+//! transmissions are complete.
+//
+//*****************************************************************************
+bool
+SSIBusy(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Determine if the SSI is busy.
+ //
+ return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Sets the data clock source for the specified SSI peripheral.
+//!
+//! \param ui32Base is the base address of the SSI port.
+//! \param ui32Source is the baud clock source for the SSI.
+//!
+//! This function allows the baud clock source for the SSI to be selected.
+//! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or
+//! the precision internal oscillator (\b SSI_CLOCK_PIOSC).
+//!
+//! Changing the baud clock source changes the data rate generated by the
+//! SSI. Therefore, the data rate should be reconfigured after any change to
+//! the SSI clock source.
+//!
+//! \note The ability to specify the SSI baud clock source varies with the
+//! Tiva part and SSI in use. Please consult the data sheet for the part
+//! in use to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+ ASSERT((ui32Source == SSI_CLOCK_SYSTEM) ||
+ (ui32Source == SSI_CLOCK_PIOSC));
+
+ //
+ // Set the SSI clock source.
+ //
+ HWREG(ui32Base + SSI_O_CC) = ui32Source;
+}
+
+//*****************************************************************************
+//
+//! Gets the data clock source for the specified SSI peripheral.
+//!
+//! \param ui32Base is the base address of the SSI port.
+//!
+//! This function returns the data clock source for the specified SSI.
+//!
+//! \note The ability to specify the SSI data clock source varies with the
+//! Tiva part and SSI in use. Please consult the data sheet for the part
+//! in use to determine whether this support is available.
+//!
+//! \return Returns the current clock source, which will be either
+//! \b SSI_CLOCK_SYSTEM or \b SSI_CLOCK_PIOSC.
+//
+//*****************************************************************************
+uint32_t
+SSIClockSourceGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SSIBaseValid(ui32Base));
+
+ //
+ // Return the SSI clock source.
+ //
+ return(HWREG(ui32Base + SSI_O_CC));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/ssi.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/ssi.h
new file mode 100644
index 00000000..7d75f9fe
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/ssi.h
@@ -0,0 +1,135 @@
+//*****************************************************************************
+//
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SSI_H__
+#define __DRIVERLIB_SSI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
+// as the ui32IntFlags parameter, and returned by SSIIntStatus.
+//
+//*****************************************************************************
+#define SSI_TXFF 0x00000008 // TX FIFO half full or less
+#define SSI_RXFF 0x00000004 // RX FIFO half full or more
+#define SSI_RXTO 0x00000002 // RX timeout
+#define SSI_RXOR 0x00000001 // RX overrun
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIConfigSetExpClk.
+//
+//*****************************************************************************
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
+#define SSI_FRF_TI 0x00000010 // TI frame format
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
+
+#define SSI_MODE_MASTER 0x00000000 // SSI master
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
+//
+//*****************************************************************************
+#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
+#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIClockSourceSet() or returned from
+// SSIClockSourceGet().
+//
+//*****************************************************************************
+#define SSI_CLOCK_SYSTEM 0x00000000
+#define SSI_CLOCK_PIOSC 0x00000005
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk,
+ uint32_t ui32Protocol, uint32_t ui32Mode,
+ uint32_t ui32BitRate,
+ uint32_t ui32DataWidth);
+extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data);
+extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base,
+ uint32_t *pui32Data);
+extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data);
+extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data);
+extern void SSIDisable(uint32_t ui32Base);
+extern void SSIEnable(uint32_t ui32Base);
+extern void SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern uint32_t SSIIntStatus(uint32_t ui32Base, bool bMasked);
+extern void SSIIntUnregister(uint32_t ui32Base);
+extern void SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags);
+extern void SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags);
+extern bool SSIBusy(uint32_t ui32Base);
+extern void SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source);
+extern uint32_t SSIClockSourceGet(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SSI_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sw_crc.c b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sw_crc.c
new file mode 100644
index 00000000..7b2b390b
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sw_crc.c
@@ -0,0 +1,770 @@
+//*****************************************************************************
+//
+// sw_crc.c - Software CRC functions.
+//
+// Copyright (c) 2010-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup sw_crc_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include "driverlib/sw_crc.h"
+
+//*****************************************************************************
+//
+// The CRC table for the polynomial C(x) = x^8 + x^2 + x + 1 (CRC-8-CCITT).
+//
+//*****************************************************************************
+static const uint8_t g_pui8Crc8CCITT[256] =
+{
+ 0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15,
+ 0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D,
+ 0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65,
+ 0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D,
+ 0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5,
+ 0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD,
+ 0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85,
+ 0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD,
+ 0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2,
+ 0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA,
+ 0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2,
+ 0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A,
+ 0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32,
+ 0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A,
+ 0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42,
+ 0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A,
+ 0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C,
+ 0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4,
+ 0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC,
+ 0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4,
+ 0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C,
+ 0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44,
+ 0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C,
+ 0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34,
+ 0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B,
+ 0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63,
+ 0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B,
+ 0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13,
+ 0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB,
+ 0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83,
+ 0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB,
+ 0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3
+};
+
+//*****************************************************************************
+//
+// The CRC-16 table for the polynomial C(x) = x^16 + x^15 + x^2 + 1 (standard
+// CRC-16, also known as CRC-16-IBM and CRC-16-ANSI).
+//
+//*****************************************************************************
+static const uint16_t g_pui16Crc16[256] =
+{
+ 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
+ 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
+ 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
+ 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
+ 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
+ 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
+ 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
+ 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
+ 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
+ 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
+ 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
+ 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
+ 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
+ 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
+ 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
+ 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
+ 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
+ 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
+ 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
+ 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
+ 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
+ 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
+ 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
+ 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
+ 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
+ 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
+ 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
+ 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
+ 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
+ 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
+ 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
+ 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
+};
+
+//*****************************************************************************
+//
+// The CRC-32 table for the polynomial C(x) = x^32 + x^26 + x^23 + x^22 +
+// x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1 (standard
+// CRC32 as used in Ethernet, MPEG-2, PNG, etc.).
+//
+//*****************************************************************************
+static const uint32_t g_pui32Crc32[] =
+{
+ 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
+ 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
+ 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+ 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
+ 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
+ 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+ 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
+ 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
+ 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+ 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
+ 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
+ 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+ 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
+ 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
+ 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+ 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
+ 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
+ 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+ 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
+ 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
+ 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+ 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
+ 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
+ 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+ 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
+ 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
+ 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+ 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
+ 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
+ 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+ 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
+ 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
+ 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+ 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
+ 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
+ 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+ 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
+ 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
+ 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+ 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
+ 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
+ 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+ 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
+ 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
+ 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+ 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
+ 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
+ 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+ 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
+ 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
+ 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+ 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
+ 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
+ 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+ 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
+ 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
+ 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+ 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
+ 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
+ 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+ 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
+ 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
+ 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+ 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
+};
+
+//*****************************************************************************
+//
+// This macro executes one iteration of the CRC-8-CCITT.
+//
+//*****************************************************************************
+#define CRC8_ITER(crc, data) g_pui8Crc8CCITT[(uint8_t)((crc) ^ (data))]
+
+//*****************************************************************************
+//
+// This macro executes one iteration of the CRC-16.
+//
+//*****************************************************************************
+#define CRC16_ITER(crc, data) (((crc) >> 8) ^ \
+ g_pui16Crc16[(uint8_t)((crc) ^ (data))])
+
+//*****************************************************************************
+//
+// This macro executes one iteration of the CRC-32.
+//
+//*****************************************************************************
+#define CRC32_ITER(crc, data) (((crc) >> 8) ^ \
+ g_pui32Crc32[(uint8_t)((crc & 0xFF) ^ \
+ (data))])
+
+//*****************************************************************************
+//
+//! Calculates the CRC-8-CCITT of an array of bytes.
+//!
+//! \param ui8Crc is the starting CRC-8-CCITT value.
+//! \param pui8Data is a pointer to the data buffer.
+//! \param ui32Count is the number of bytes in the data buffer.
+//!
+//! This function is used to calculate the CRC-8-CCITT of the input buffer.
+//! The CRC-8-CCITT is computed in a running fashion, meaning that the entire
+//! data block that is to have its CRC-8-CCITT computed does not need to be
+//! supplied all at once. If the input buffer contains the entire block of
+//! data, then \b ui8Crc should be set to 0. If, however, the entire block of
+//! data is not available, then \b ui8Crc should be set to 0 for the first
+//! portion of the data, and then the returned value should be passed back in
+//! as \b ui8Crc for the next portion of the data.
+//!
+//! For example, to compute the CRC-8-CCITT of a block that has been split into
+//! three pieces, use the following:
+//!
+//! \verbatim
+//! ui8Crc = Crc8CCITT(0, pui8Data1, ui32Len1);
+//! ui8Crc = Crc8CCITT(ui8Crc, pui8Data2, ui32Len2);
+//! ui8Crc = Crc8CCITT(ui8Crc, pui8Data3, ui32Len3);
+//! \endverbatim
+//!
+//! Computing a CRC-8-CCITT in a running fashion is useful in cases where the
+//! data is arriving via a serial link (for example) and is therefore not all
+//! available at one time.
+//!
+//! \return The CRC-8-CCITT of the input data.
+//
+//*****************************************************************************
+uint8_t
+Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data, uint32_t ui32Count)
+{
+ uint32_t ui32Temp;
+
+ //
+ // If the data buffer is not 16 bit-aligned, then perform a single step of
+ // the CRC to make it 16 bit-aligned.
+ //
+ if((uint32_t)pui8Data & 1)
+ {
+ //
+ // Perform the CRC on this input byte.
+ //
+ ui8Crc = CRC8_ITER(ui8Crc, *pui8Data);
+
+ //
+ // Skip this input byte.
+ //
+ pui8Data++;
+ ui32Count--;
+ }
+
+ //
+ // If the data buffer is not word-aligned and there are at least two bytes
+ // of data left, then perform two steps of the CRC to make it word-aligned.
+ //
+ if(((uint32_t)pui8Data & 2) && (ui32Count > 1))
+ {
+ //
+ // Read the next 16 bits.
+ //
+ ui32Temp = *(uint16_t *)pui8Data;
+
+ //
+ // Perform the CRC on these two bytes.
+ //
+ ui8Crc = CRC8_ITER(ui8Crc, ui32Temp);
+ ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8);
+
+ //
+ // Skip these input bytes.
+ //
+ pui8Data += 2;
+ ui32Count -= 2;
+ }
+
+ //
+ // While there is at least a word remaining in the data buffer, perform
+ // four steps of the CRC to consume a word.
+ //
+ while(ui32Count > 3)
+ {
+ //
+ // Read the next word.
+ //
+ ui32Temp = *(uint32_t *)pui8Data;
+
+ //
+ // Perform the CRC on these four bytes.
+ //
+ ui8Crc = CRC8_ITER(ui8Crc, ui32Temp);
+ ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8);
+ ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 16);
+ ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 24);
+
+ //
+ // Skip these input bytes.
+ //
+ pui8Data += 4;
+ ui32Count -= 4;
+ }
+
+ //
+ // If there are 16 bits left in the input buffer, then perform two steps of
+ // the CRC.
+ //
+ if(ui32Count > 1)
+ {
+ //
+ // Read the 16 bits.
+ //
+ ui32Temp = *(uint16_t *)pui8Data;
+
+ //
+ // Perform the CRC on these two bytes.
+ //
+ ui8Crc = CRC8_ITER(ui8Crc, ui32Temp);
+ ui8Crc = CRC8_ITER(ui8Crc, ui32Temp >> 8);
+
+ //
+ // Skip these input bytes.
+ //
+ pui8Data += 2;
+ ui32Count -= 2;
+ }
+
+ //
+ // If there is a final byte remaining in the input buffer, then perform a
+ // single step of the CRC.
+ //
+ if(ui32Count != 0)
+ {
+ ui8Crc = CRC8_ITER(ui8Crc, *pui8Data);
+ }
+
+ //
+ // Return the resulting CRC-8-CCITT value.
+ //
+ return(ui8Crc);
+}
+
+//*****************************************************************************
+//
+//! Calculates the CRC-16 of an array of bytes.
+//!
+//! \param ui16Crc is the starting CRC-16 value.
+//! \param pui8Data is a pointer to the data buffer.
+//! \param ui32Count is the number of bytes in the data buffer.
+//!
+//! This function is used to calculate the CRC-16 of the input buffer. The
+//! CRC-16 is computed in a running fashion, meaning that the entire data block
+//! that is to have its CRC-16 computed does not need to be supplied all at
+//! once. If the input buffer contains the entire block of data, then
+//! \b ui16Crc should be set to 0. If, however, the entire block of data is
+//! not available, then \b ui16Crc should be set to 0 for the first portion of
+//! the data, and then the returned value should be passed back in as
+//! \b ui16Crc for the next portion of the data.
+//!
+//! For example, to compute the CRC-16 of a block that has been split into
+//! three pieces, use the following:
+//!
+//! \verbatim
+//! ui16Crc = Crc16(0, pui8Data1, ui32Len1);
+//! ui16Crc = Crc16(ui16Crc, pui8Data2, ui32Len2);
+//! ui16Crc = Crc16(ui16Crc, pui8Data3, ui32Len3);
+//! \endverbatim
+//!
+//! Computing a CRC-16 in a running fashion is useful in cases where the data
+//! is arriving via a serial link (for example) and is therefore not all
+//! available at one time.
+//!
+//! \return The CRC-16 of the input data.
+//
+//*****************************************************************************
+uint16_t
+Crc16(uint16_t ui16Crc, const uint8_t *pui8Data, uint32_t ui32Count)
+{
+ uint32_t ui32Temp;
+
+ //
+ // If the data buffer is not 16 bit-aligned, then perform a single step of
+ // the CRC to make it 16 bit-aligned.
+ //
+ if((uint32_t)pui8Data & 1)
+ {
+ //
+ // Perform the CRC on this input byte.
+ //
+ ui16Crc = CRC16_ITER(ui16Crc, *pui8Data);
+
+ //
+ // Skip this input byte.
+ //
+ pui8Data++;
+ ui32Count--;
+ }
+
+ //
+ // If the data buffer is not word-aligned and there are at least two bytes
+ // of data left, then perform two steps of the CRC to make it word-aligned.
+ //
+ if(((uint32_t)pui8Data & 2) && (ui32Count > 1))
+ {
+ //
+ // Read the next 16 bits.
+ //
+ ui32Temp = *(uint16_t *)pui8Data;
+
+ //
+ // Perform the CRC on these two bytes.
+ //
+ ui16Crc = CRC16_ITER(ui16Crc, ui32Temp);
+ ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8);
+
+ //
+ // Skip these input bytes.
+ //
+ pui8Data += 2;
+ ui32Count -= 2;
+ }
+
+ //
+ // While there is at least a word remaining in the data buffer, perform
+ // four steps of the CRC to consume a word.
+ //
+ while(ui32Count > 3)
+ {
+ //
+ // Read the next word.
+ //
+ ui32Temp = *(uint32_t *)pui8Data;
+
+ //
+ // Perform the CRC on these four bytes.
+ //
+ ui16Crc = CRC16_ITER(ui16Crc, ui32Temp);
+ ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8);
+ ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 16);
+ ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 24);
+
+ //
+ // Skip these input bytes.
+ //
+ pui8Data += 4;
+ ui32Count -= 4;
+ }
+
+ //
+ // If there are two bytes left in the input buffer, then perform two steps
+ // of the CRC.
+ //
+ if(ui32Count > 1)
+ {
+ //
+ // Read the two bytes.
+ //
+ ui32Temp = *(uint16_t *)pui8Data;
+
+ //
+ // Perform the CRC on these two bytes.
+ //
+ ui16Crc = CRC16_ITER(ui16Crc, ui32Temp);
+ ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8);
+
+ //
+ // Skip these input bytes.
+ //
+ pui8Data += 2;
+ ui32Count -= 2;
+ }
+
+ //
+ // If there is a final byte remaining in the input buffer, then perform a
+ // single step of the CRC.
+ //
+ if(ui32Count != 0)
+ {
+ ui16Crc = CRC16_ITER(ui16Crc, *pui8Data);
+ }
+
+ //
+ // Return the resulting CRC-16 value.
+ //
+ return(ui16Crc);
+}
+
+//*****************************************************************************
+//
+//! Calculates the CRC-16 of an array of words.
+//!
+//! \param ui32WordLen is the length of the array in words (the number of bytes
+//! divided by 4).
+//! \param pui32Data is a pointer to the data buffer.
+//!
+//! This function is a wrapper around the running CRC-16 function, providing
+//! the CRC-16 for a single block of data.
+//!
+//! \return The CRC-16 of the input data.
+//
+//*****************************************************************************
+uint16_t
+Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data)
+{
+ //
+ // Calculate and return the CRC-16 of this array of words.
+ //
+ return(Crc16(0, (const uint8_t *)pui32Data, ui32WordLen * 4));
+}
+
+//*****************************************************************************
+//
+//! Calculates three CRC-16s of an array of words.
+//!
+//! \param ui32WordLen is the length of the array in words (the number of bytes
+//! divided by 4).
+//! \param pui32Data is a pointer to the data buffer.
+//! \param pui16Crc3 is a pointer to an array in which to place the three
+//! CRC-16 values.
+//!
+//! This function is used to calculate three CRC-16s of the input buffer; the
+//! first uses every byte from the array, the second uses only the even-index
+//! bytes from the array (in other words, bytes 0, 2, 4, etc.), and the third
+//! uses only the odd-index bytes from the array (in other words, bytes 1, 3,
+//! 5, etc.).
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data,
+ uint16_t *pui16Crc3)
+{
+ uint16_t ui16Crc, ui16Cri8Odd, ui16Cri8Even;
+ uint32_t ui32Temp;
+
+ //
+ // Initialize the CRC values to zero.
+ //
+ ui16Crc = 0;
+ ui16Cri8Odd = 0;
+ ui16Cri8Even = 0;
+
+ //
+ // Loop while there are more words in the data buffer.
+ //
+ while(ui32WordLen--)
+ {
+ //
+ // Read the next word.
+ //
+ ui32Temp = *pui32Data++;
+
+ //
+ // Perform the first CRC on all four data bytes.
+ //
+ ui16Crc = CRC16_ITER(ui16Crc, ui32Temp);
+ ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 8);
+ ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 16);
+ ui16Crc = CRC16_ITER(ui16Crc, ui32Temp >> 24);
+
+ //
+ // Perform the second CRC on only the even-index data bytes.
+ //
+ ui16Cri8Even = CRC16_ITER(ui16Cri8Even, ui32Temp);
+ ui16Cri8Even = CRC16_ITER(ui16Cri8Even, ui32Temp >> 16);
+
+ //
+ // Perform the third CRC on only the odd-index data bytes.
+ //
+ ui16Cri8Odd = CRC16_ITER(ui16Cri8Odd, ui32Temp >> 8);
+ ui16Cri8Odd = CRC16_ITER(ui16Cri8Odd, ui32Temp >> 24);
+ }
+
+ //
+ // Return the resulting CRC-16 values.
+ //
+ pui16Crc3[0] = ui16Crc;
+ pui16Crc3[1] = ui16Cri8Even;
+ pui16Crc3[2] = ui16Cri8Odd;
+}
+
+//*****************************************************************************
+//
+//! Calculates the CRC-32 of an array of bytes.
+//!
+//! \param ui32Crc is the starting CRC-32 value.
+//! \param pui8Data is a pointer to the data buffer.
+//! \param ui32Count is the number of bytes in the data buffer.
+//!
+//! This function is used to calculate the CRC-32 of the input buffer. The
+//! CRC-32 is computed in a running fashion, meaning that the entire data block
+//! that is to have its CRC-32 computed does not need to be supplied all at
+//! once. If the input buffer contains the entire block of data, then
+//! \b ui32Crc should be set to 0xFFFFFFFF. If, however, the entire block of
+//! data is not available, then \b ui32Crc should be set to 0xFFFFFFFF for the
+//! first portion of the data, and then the returned value should be passed
+//! back in as \b ui32Crc for the next portion of the data. Once all data has
+//! been passed to the function, the final CRC-32 can be obtained by inverting
+//! the last returned value.
+//!
+//! For example, to compute the CRC-32 of a block that has been split into
+//! three pieces, use the following:
+//!
+//! \verbatim
+//! ui32Crc = Crc32(0xFFFFFFFF, pui8Data1, ui32Len1);
+//! ui32Crc = Crc32(ui32Crc, pui8Data2, ui32Len2);
+//! ui32Crc = Crc32(ui32Crc, pui8Data3, ui32Len3);
+//! ui32Crc ^= 0xFFFFFFFF;
+//! \endverbatim
+//!
+//! Computing a CRC-32 in a running fashion is useful in cases where the data
+//! is arriving via a serial link (for example) and is therefore not all
+//! available at one time.
+//!
+//! \return The accumulated CRC-32 of the input data.
+//
+//*****************************************************************************
+uint32_t
+Crc32(uint32_t ui32Crc, const uint8_t *pui8Data, uint32_t ui32Count)
+{
+ uint32_t ui32Temp;
+
+ //
+ // If the data buffer is not 16 bit-aligned, then perform a single step
+ // of the CRC to make it 16 bit-aligned.
+ //
+ if((uint32_t)pui8Data & 1)
+ {
+ //
+ // Perform the CRC on this input byte.
+ //
+ ui32Crc = CRC32_ITER(ui32Crc, *pui8Data);
+
+ //
+ // Skip this input byte.
+ //
+ pui8Data++;
+ ui32Count--;
+ }
+
+ //
+ // If the data buffer is not word-aligned and there are at least two bytes
+ // of data left, then perform two steps of the CRC to make it word-aligned.
+ //
+ if(((uint32_t)pui8Data & 2) && (ui32Count > 1))
+ {
+ //
+ // Read the next int16_t.
+ //
+ ui32Temp = *(uint16_t *)pui8Data;
+
+ //
+ // Perform the CRC on these two bytes.
+ //
+ ui32Crc = CRC32_ITER(ui32Crc, ui32Temp);
+ ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8);
+
+ //
+ // Skip these input bytes.
+ //
+ pui8Data += 2;
+ ui32Count -= 2;
+ }
+
+ //
+ // While there is at least a word remaining in the data buffer, perform
+ // four steps of the CRC to consume a word.
+ //
+ while(ui32Count > 3)
+ {
+ //
+ // Read the next word.
+ //
+ ui32Temp = *(uint32_t *)pui8Data;
+
+ //
+ // Perform the CRC on these four bytes.
+ //
+ ui32Crc = CRC32_ITER(ui32Crc, ui32Temp);
+ ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8);
+ ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 16);
+ ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 24);
+
+ //
+ // Skip these input bytes.
+ //
+ pui8Data += 4;
+ ui32Count -= 4;
+ }
+
+ //
+ // If there are 16 bits left in the input buffer, then perform two steps of
+ // the CRC.
+ //
+ if(ui32Count > 1)
+ {
+ //
+ // Read the two bytes.
+ //
+ ui32Temp = *(uint16_t *)pui8Data;
+
+ //
+ // Perform the CRC on these two bytes.
+ //
+ ui32Crc = CRC32_ITER(ui32Crc, ui32Temp);
+ ui32Crc = CRC32_ITER(ui32Crc, ui32Temp >> 8);
+
+ //
+ // Skip these input bytes.
+ //
+ pui8Data += 2;
+ ui32Count -= 2;
+ }
+
+ //
+ // If there is a final byte remaining in the input buffer, then perform a
+ // single step of the CRC.
+ //
+ if(ui32Count != 0)
+ {
+ ui32Crc = CRC32_ITER(ui32Crc, *pui8Data);
+ }
+
+ //
+ // Return the resulting CRC-32 value.
+ //
+ return(ui32Crc);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sw_crc.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sw_crc.h
new file mode 100644
index 00000000..6761f5ca
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sw_crc.h
@@ -0,0 +1,78 @@
+//*****************************************************************************
+//
+// sw_crc.h - Prototypes for the software CRC functions.
+//
+// Copyright (c) 2010-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SW_CRC_H__
+#define __DRIVERLIB_SW_CRC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the functions.
+//
+//*****************************************************************************
+extern uint8_t Crc8CCITT(uint8_t ui8Crc, const uint8_t *pui8Data,
+ uint32_t ui32Count);
+extern uint16_t Crc16(uint16_t ui16Crc, const uint8_t *pui8Data,
+ uint32_t ui32Count);
+extern uint16_t Crc16Array(uint32_t ui32WordLen, const uint32_t *pui32Data);
+extern void Crc16Array3(uint32_t ui32WordLen, const uint32_t *pui32Data,
+ uint16_t *pui16Crc3);
+extern uint32_t Crc32(uint32_t ui32Crc, const uint8_t *pui8Data,
+ uint32_t ui32Count);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SW_CRC_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sysctl.c b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sysctl.c
new file mode 100644
index 00000000..2e278260
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sysctl.c
@@ -0,0 +1,2171 @@
+//*****************************************************************************
+//
+// sysctl.c - Driver for the system controller.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup sysctl_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "inc/hw_flash.h"
+#include "driverlib/cpu.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+
+//*****************************************************************************
+//
+// An array that maps the crystal number in RCC to a frequency.
+//
+//*****************************************************************************
+static const uint32_t g_pui32Xtals[] =
+{
+ 1000000,
+ 1843200,
+ 2000000,
+ 2457600,
+ 3579545,
+ 3686400,
+ 4000000,
+ 4096000,
+ 4915200,
+ 5000000,
+ 5120000,
+ 6000000,
+ 6144000,
+ 7372800,
+ 8000000,
+ 8192000,
+ 10000000,
+ 12000000,
+ 12288000,
+ 13560000,
+ 14318180,
+ 16000000,
+ 16384000,
+ 18000000,
+ 20000000,
+ 24000000,
+ 25000000
+};
+//*****************************************************************************
+//
+// The base addresses of the various peripheral control registers.
+//
+//*****************************************************************************
+#define SYSCTL_PPBASE 0x400fe300
+#define SYSCTL_SRBASE 0x400fe500
+#define SYSCTL_RCGCBASE 0x400fe600
+#define SYSCTL_SCGCBASE 0x400fe700
+#define SYSCTL_DCGCBASE 0x400fe800
+#define SYSCTL_PCBASE 0x400fe900
+#define SYSCTL_PRBASE 0x400fea00
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a peripheral identifier.
+//!
+//! \param ui32Peripheral is the peripheral identifier.
+//!
+//! This function determines if a peripheral identifier is valid.
+//!
+//! \return Returns \b true if the peripheral identifier is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_SysCtlPeripheralValid(uint32_t ui32Peripheral)
+{
+ return((ui32Peripheral == SYSCTL_PERIPH_ADC0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_ADC1) ||
+ (ui32Peripheral == SYSCTL_PERIPH_CAN0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_CAN1) ||
+ (ui32Peripheral == SYSCTL_PERIPH_CAN2) ||
+ (ui32Peripheral == SYSCTL_PERIPH_COMP0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_COMP1) ||
+ (ui32Peripheral == SYSCTL_PERIPH_COMP2) ||
+ (ui32Peripheral == SYSCTL_PERIPH_EEPROM0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_FAN0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOA) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOB) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOC) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOD) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOE) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOF) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOG) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOH) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOJ) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOK) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOL) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOM) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPION) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOP) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOQ) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOR) ||
+ (ui32Peripheral == SYSCTL_PERIPH_GPIOS) ||
+ (ui32Peripheral == SYSCTL_PERIPH_HIBERNATE) ||
+ (ui32Peripheral == SYSCTL_PERIPH_I2C0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_I2C1) ||
+ (ui32Peripheral == SYSCTL_PERIPH_I2C2) ||
+ (ui32Peripheral == SYSCTL_PERIPH_I2C3) ||
+ (ui32Peripheral == SYSCTL_PERIPH_I2C4) ||
+ (ui32Peripheral == SYSCTL_PERIPH_I2C5) ||
+ (ui32Peripheral == SYSCTL_PERIPH_LPC0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_PECI0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_PWM0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_PWM1) ||
+ (ui32Peripheral == SYSCTL_PERIPH_QEI0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_QEI1) ||
+ (ui32Peripheral == SYSCTL_PERIPH_SSI0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_SSI1) ||
+ (ui32Peripheral == SYSCTL_PERIPH_SSI2) ||
+ (ui32Peripheral == SYSCTL_PERIPH_SSI3) ||
+ (ui32Peripheral == SYSCTL_PERIPH_TIMER0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_TIMER1) ||
+ (ui32Peripheral == SYSCTL_PERIPH_TIMER2) ||
+ (ui32Peripheral == SYSCTL_PERIPH_TIMER3) ||
+ (ui32Peripheral == SYSCTL_PERIPH_TIMER4) ||
+ (ui32Peripheral == SYSCTL_PERIPH_TIMER5) ||
+ (ui32Peripheral == SYSCTL_PERIPH_UART0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_UART1) ||
+ (ui32Peripheral == SYSCTL_PERIPH_UART2) ||
+ (ui32Peripheral == SYSCTL_PERIPH_UART3) ||
+ (ui32Peripheral == SYSCTL_PERIPH_UART4) ||
+ (ui32Peripheral == SYSCTL_PERIPH_UART5) ||
+ (ui32Peripheral == SYSCTL_PERIPH_UART6) ||
+ (ui32Peripheral == SYSCTL_PERIPH_UART7) ||
+ (ui32Peripheral == SYSCTL_PERIPH_UDMA) ||
+ (ui32Peripheral == SYSCTL_PERIPH_USB0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_WDOG0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_WDOG1) ||
+ (ui32Peripheral == SYSCTL_PERIPH_WTIMER0) ||
+ (ui32Peripheral == SYSCTL_PERIPH_WTIMER1) ||
+ (ui32Peripheral == SYSCTL_PERIPH_WTIMER2) ||
+ (ui32Peripheral == SYSCTL_PERIPH_WTIMER3) ||
+ (ui32Peripheral == SYSCTL_PERIPH_WTIMER4) ||
+ (ui32Peripheral == SYSCTL_PERIPH_WTIMER5));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Gets the size of the SRAM.
+//!
+//! This function determines the size of the SRAM on the Tiva device.
+//!
+//! \return The total number of bytes of SRAM.
+//
+//*****************************************************************************
+uint32_t
+SysCtlSRAMSizeGet(void)
+{
+ return((HWREG(FLASH_SSIZE) + 1) * 256);
+}
+
+//*****************************************************************************
+//
+//! Gets the size of the flash.
+//!
+//! This function determines the size of the flash on the Tiva device.
+//!
+//! \return The total number of bytes of flash.
+//
+//*****************************************************************************
+uint32_t
+SysCtlFlashSizeGet(void)
+{
+ //
+ // Compute the size of the flash.
+ //
+ return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_M) << 11) + 0x800);
+}
+
+//*****************************************************************************
+//
+//! Determines if a peripheral is present.
+//!
+//! \param ui32Peripheral is the peripheral in question.
+//!
+//! This function determines if a particular peripheral is present in the
+//! device. Each member of the Tiva family has a different peripheral
+//! set; this function determines which peripherals are present on this device.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2,
+//! \b SYSCTL_PERIPH_FAN0, \b SYSCTL_PERIPH_GPIOA,
+//! \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD,
+//! \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG,
+//! \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_GPIOK,
+//! \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM, \b SYSCTL_PERIPH_GPION,
+//! \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ, \b SYSCTL_PERIPH_HIBERNATE,
+//! \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2C2,
+//! \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4, \b SYSCTL_PERIPH_I2C5,
+//! \b SYSCTL_PERIPH_LPC0,
+//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5,
+//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1,
+//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5,
+//!
+//! \return Returns \b true if the specified peripheral is present and \b false
+//! if it is not.
+//
+//*****************************************************************************
+bool
+SysCtlPeripheralPresent(uint32_t ui32Peripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+ //
+ // See if this peripheral is present.
+ //
+ return(HWREGBITW(SYSCTL_PPBASE + ((ui32Peripheral & 0xff00) >> 8),
+ ui32Peripheral & 0xff));
+}
+
+//*****************************************************************************
+//
+//! Determines if a peripheral is ready.
+//!
+//! \param ui32Peripheral is the peripheral in question.
+//!
+//! This function determines if a particular peripheral is ready to be
+//! accessed. The peripheral may be in a non-ready state if it is not enabled,
+//! is being held in reset, or is in the process of becoming ready after being
+//! enabled or taken out of reset.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0,
+//! \b SYSCTL_PERIPH_FAN0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1,
+//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4,
+//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_LPC0,
+//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5,
+//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1,
+//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5.
+//!
+//! \note The ability to check for a peripheral being ready varies based on the
+//! Tiva part in use. Please consult the data sheet for the part you are
+//! using to determine if this feature is available.
+//!
+//! \return Returns \b true if the specified peripheral is ready and \b false
+//! if it is not.
+//
+//*****************************************************************************
+bool
+SysCtlPeripheralReady(uint32_t ui32Peripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+ //
+ // See if this peripheral is ready.
+ //
+ return(HWREGBITW(SYSCTL_PRBASE + ((ui32Peripheral & 0xff00) >> 8),
+ ui32Peripheral & 0xff));
+}
+
+//*****************************************************************************
+//
+//! Powers on a peripheral.
+//!
+//! \param ui32Peripheral is the peripheral to be powered on.
+//!
+//! This function turns on the power to a peripheral. The peripheral continues
+//! to receive power even when its clock is not enabled.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0,
+//! \b SYSCTL_PERIPH_FAN0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1,
+//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4,
+//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_LPC0,
+//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5,
+//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1,
+//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5.
+//!
+//! \note The ability to power off a peripheral varies based on the Tiva
+//! part in use. Please consult the data sheet for the part you are using to
+//! determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralPowerOn(uint32_t ui32Peripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+ //
+ // Power on this peripheral.
+ //
+ HWREGBITW(SYSCTL_PCBASE + ((ui32Peripheral & 0xff00) >> 8),
+ ui32Peripheral & 0xff) = 1;
+}
+
+//*****************************************************************************
+//
+//! Powers off a peripheral.
+//!
+//! \param ui32Peripheral is the peripheral to be powered off.
+//!
+//! This function allows the power to a peripheral to be turned off. The
+//! peripheral continues to receive power when its clock is enabled, but
+//! the power is removed when its clock is disabled.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0,
+//! \b SYSCTL_PERIPH_FAN0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1,
+//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4,
+//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_LPC0,
+//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5,
+//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1,
+//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5.
+//!
+//! \note The ability to power off a peripheral varies based on the Tiva
+//! part in use. Please consult the data sheet for the part you are using to
+//! determine if this feature is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralPowerOff(uint32_t ui32Peripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+ //
+ // Power off this peripheral.
+ //
+ HWREGBITW(SYSCTL_PCBASE + ((ui32Peripheral & 0xff00) >> 8),
+ ui32Peripheral & 0xff) = 0;
+}
+
+//*****************************************************************************
+//
+//! Performs a software reset of a peripheral.
+//!
+//! \param ui32Peripheral is the peripheral to reset.
+//!
+//! This function performs a software reset of the specified peripheral. An
+//! individual peripheral reset signal is asserted for a brief period and then
+//! de-asserted, returning the internal state of the peripheral to its reset
+//! condition.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0,
+//! \b SYSCTL_PERIPH_FAN0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1,
+//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4,
+//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_LPC0,
+//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5,
+//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1,
+//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralReset(uint32_t ui32Peripheral)
+{
+ volatile uint_fast8_t ui8Delay;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+ //
+ // Put the peripheral into the reset state.
+ //
+ HWREGBITW(SYSCTL_SRBASE + ((ui32Peripheral & 0xff00) >> 8),
+ ui32Peripheral & 0xff) = 1;
+
+ //
+ // Delay for a little bit.
+ //
+ for(ui8Delay = 0; ui8Delay < 16; ui8Delay++)
+ {
+ }
+
+ //
+ // Take the peripheral out of the reset state.
+ //
+ HWREGBITW(SYSCTL_SRBASE + ((ui32Peripheral & 0xff00) >> 8),
+ ui32Peripheral & 0xff) = 0;
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral.
+//!
+//! \param ui32Peripheral is the peripheral to enable.
+//!
+//! This function enables a peripheral. At power-up, all peripherals are
+//! disabled; they must be enabled in order to operate or respond to register
+//! reads/writes.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0,
+//! \b SYSCTL_PERIPH_FAN0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1,
+//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4,
+//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_LPC0,
+//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5,
+//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1,
+//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5.
+//!
+//! \note It takes five clock cycles after the write to enable a peripheral
+//! before the the peripheral is actually enabled. During this time, attempts
+//! to access the peripheral result in a bus fault. Care should be taken
+//! to ensure that the peripheral is not accessed during this brief time
+//! period.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralEnable(uint32_t ui32Peripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+ //
+ // Enable this peripheral.
+ //
+ HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
+ ui32Peripheral & 0xff) = 1;
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral.
+//!
+//! \param ui32Peripheral is the peripheral to disable.
+//!
+//! This function disables a peripheral. Once disabled, they do not operate or
+//! respond to register reads/writes.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0,
+//! \b SYSCTL_PERIPH_FAN0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1,
+//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4,
+//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_LPC0,
+//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5,
+//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1,
+//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDisable(uint32_t ui32Peripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+ //
+ // Disable this peripheral.
+ //
+ HWREGBITW(SYSCTL_RCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
+ ui32Peripheral & 0xff) = 0;
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral in sleep mode.
+//!
+//! \param ui32Peripheral is the peripheral to enable in sleep mode.
+//!
+//! This function allows a peripheral to continue operating when the processor
+//! goes into sleep mode. Because the clocking configuration of the device
+//! does not change, any peripheral can safely continue operating while the
+//! processor is in sleep mode and can therefore wake the processor from sleep
+//! mode.
+//!
+//! Sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
+//! configuration is maintained but has no effect when sleep mode is entered.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0,
+//! \b SYSCTL_PERIPH_FAN0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1,
+//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4,
+//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_LPC0,
+//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5,
+//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1,
+//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+ //
+ // Enable this peripheral in sleep mode.
+ //
+ HWREGBITW(SYSCTL_SCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
+ ui32Peripheral & 0xff) = 1;
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral in sleep mode.
+//!
+//! \param ui32Peripheral is the peripheral to disable in sleep mode.
+//!
+//! This function causes a peripheral to stop operating when the processor goes
+//! into sleep mode. Disabling peripherals while in sleep mode helps to lower
+//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()),
+//! the peripheral automatically resumes operation when the processor
+//! leaves sleep mode, maintaining its entire state from before sleep mode was
+//! entered.
+//!
+//! Sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
+//! configuration is maintained but has no effect when sleep mode is entered.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0,
+//! \b SYSCTL_PERIPH_FAN0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1,
+//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4,
+//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_LPC0,
+//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5,
+//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1,
+//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+ //
+ // Disable this peripheral in sleep mode.
+ //
+ HWREGBITW(SYSCTL_SCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
+ ui32Peripheral & 0xff) = 0;
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral in deep-sleep mode.
+//!
+//! \param ui32Peripheral is the peripheral to enable in deep-sleep mode.
+//!
+//! This function allows a peripheral to continue operating when the processor
+//! goes into deep-sleep mode. Because the clocking configuration of the
+//! device may change, not all peripherals can safely continue operating while
+//! the processor is in deep-sleep mode. Those that must run at a particular
+//! frequency (such as a UART) do not work as expected if the clock changes.
+//! It is the responsibility of the caller to make sensible choices.
+//!
+//! Deep-sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
+//! configuration is maintained but has no effect when deep-sleep mode is
+//! entered.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0,
+//! \b SYSCTL_PERIPH_FAN0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1,
+//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4,
+//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_LPC0,
+//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5,
+//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1,
+//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+ //
+ // Enable this peripheral in deep-sleep mode.
+ //
+ HWREGBITW(SYSCTL_DCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
+ ui32Peripheral & 0xff) = 1;
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral in deep-sleep mode.
+//!
+//! \param ui32Peripheral is the peripheral to disable in deep-sleep mode.
+//!
+//! This function causes a peripheral to stop operating when the processor goes
+//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps
+//! to lower the current draw of the device, and can keep peripherals that
+//! require a particular clock frequency from operating when the clock changes
+//! as a result of entering deep-sleep mode. If enabled (via
+//! SysCtlPeripheralEnable()), the peripheral automatically resumes
+//! operation when the processor leaves deep-sleep mode, maintaining its entire
+//! state from before deep-sleep mode was entered.
+//!
+//! Deep-sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
+//! configuration is maintained but has no effect when deep-sleep mode is
+//! entered.
+//!
+//! The \e ui32Peripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EEPROM0,
+//! \b SYSCTL_PERIPH_FAN0,
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, \b SYSCTL_PERIPH_GPIOJ,
+//! \b SYSCTL_PERIPH_GPIOK, \b SYSCTL_PERIPH_GPIOL, \b SYSCTL_PERIPH_GPIOM,
+//! \b SYSCTL_PERIPH_GPION, \b SYSCTL_PERIPH_GPIOP, \b SYSCTL_PERIPH_GPIOQ,
+//! \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0, \b SYSCTL_PERIPH_I2C1,
+//! \b SYSCTL_PERIPH_I2C2, \b SYSCTL_PERIPH_I2C3, \b SYSCTL_PERIPH_I2C4,
+//! \b SYSCTL_PERIPH_I2C5, \b SYSCTL_PERIPH_LPC0,
+//! \b SYSCTL_PERIPH_PECI0, \b SYSCTL_PERIPH_PWM0, \b SYSCTL_PERIPH_PWM1,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_SSI2, \b SYSCTL_PERIPH_SSI3,
+//! \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1, \b SYSCTL_PERIPH_TIMER2,
+//! \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TIMER4, \b SYSCTL_PERIPH_TIMER5,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UART3, \b SYSCTL_PERIPH_UART4, \b SYSCTL_PERIPH_UART5,
+//! \b SYSCTL_PERIPH_UART6, \b SYSCTL_PERIPH_UART7, \b SYSCTL_PERIPH_UDMA,
+//! \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, \b SYSCTL_PERIPH_WDOG1,
+//! \b SYSCTL_PERIPH_WTIMER0, \b SYSCTL_PERIPH_WTIMER1,
+//! \b SYSCTL_PERIPH_WTIMER2, \b SYSCTL_PERIPH_WTIMER3,
+//! \b SYSCTL_PERIPH_WTIMER4, or \b SYSCTL_PERIPH_WTIMER5.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_SysCtlPeripheralValid(ui32Peripheral));
+
+ //
+ // Disable this peripheral in deep-sleep mode.
+ //
+ HWREGBITW(SYSCTL_DCGCBASE + ((ui32Peripheral & 0xff00) >> 8),
+ ui32Peripheral & 0xff) = 0;
+}
+
+//*****************************************************************************
+//
+//! Controls peripheral clock gating in sleep and deep-sleep mode.
+//!
+//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep
+//! peripheral configuration should be used and \b false if not.
+//!
+//! This function controls how peripherals are clocked when the processor goes
+//! into sleep or deep-sleep mode. By default, the peripherals are clocked the
+//! same as in run mode; if peripheral clock gating is enabled, they are
+//! clocked according to the configuration set by
+//! SysCtlPeripheralSleepEnable(), SysCtlPeripheralSleepDisable(),
+//! SysCtlPeripheralDeepSleepEnable(), and SysCtlPeripheralDeepSleepDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralClockGating(bool bEnable)
+{
+ //
+ // Enable peripheral clock gating as requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG);
+ }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the system control interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the system
+//! control interrupt occurs.
+//!
+//! This function registers the handler to be called when a system control
+//! interrupt occurs. This function enables the global interrupt in the
+//! interrupt controller; specific system control interrupts must be enabled
+//! via SysCtlIntEnable(). It is the interrupt handler's responsibility to
+//! clear the interrupt source via SysCtlIntClear().
+//!
+//! System control can generate interrupts when the PLL achieves lock, if the
+//! internal LDO current limit is exceeded, if the internal oscillator fails,
+//! if the main oscillator fails, if the internal LDO output voltage droops too
+//! much, if the external voltage droops too much, or if the PLL fails.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note The events that cause system control interrupts vary based on the
+//! Tiva part in use. Please consult the data sheet for the part you are
+//! using to determine which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(INT_SYSCTL_BLIZZARD, pfnHandler);
+
+ //
+ // Enable the system control interrupt.
+ //
+ IntEnable(INT_SYSCTL_BLIZZARD);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the system control interrupt.
+//!
+//! This function unregisters the handler to be called when a system control
+//! interrupt occurs. This function also masks off the interrupt in the
+//! interrupt controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntUnregister(void)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_SYSCTL_BLIZZARD);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_SYSCTL_BLIZZARD);
+}
+
+//*****************************************************************************
+//
+//! Enables individual system control interrupt sources.
+//!
+//! \param ui32Ints is a bit mask of the interrupt sources to be enabled. Must
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
+//!
+//! This function enables the indicated system control interrupt sources. Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the Tiva part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntEnable(uint32_t ui32Ints)
+{
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(SYSCTL_IMC) |= ui32Ints;
+}
+
+//*****************************************************************************
+//
+//! Disables individual system control interrupt sources.
+//!
+//! \param ui32Ints is a bit mask of the interrupt sources to be disabled.
+//! Must be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
+//!
+//! This function disables the indicated system control interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//! \note The interrupt sources vary based on the Tiva part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntDisable(uint32_t ui32Ints)
+{
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(SYSCTL_IMC) &= ~(ui32Ints);
+}
+
+//*****************************************************************************
+//
+//! Clears system control interrupt sources.
+//!
+//! \param ui32Ints is a bit mask of the interrupt sources to be cleared. Must
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
+//!
+//! The specified system control interrupt sources are cleared, so that they no
+//! longer assert. This function must be called in the interrupt handler to
+//! keep it from being called again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \note The interrupt sources vary based on the Tiva part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntClear(uint32_t ui32Ints)
+{
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(SYSCTL_MISC) = ui32Ints;
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the system controller.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \note The interrupt sources vary based on the Tiva part in use.
+//! Please consult the data sheet for the part you are using to determine
+//! which interrupt sources are available.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL,
+//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and
+//! \b SYSCTL_INT_PLL_FAIL.
+//
+//*****************************************************************************
+uint32_t
+SysCtlIntStatus(bool bMasked)
+{
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(SYSCTL_MISC));
+ }
+ else
+ {
+ return(HWREG(SYSCTL_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Resets the device.
+//!
+//! This function performs a software reset of the entire device. The
+//! processor and all peripherals are reset and all device registers are
+//! returned to their default values (with the exception of the reset cause
+//! register, which maintains its current value but has the software reset
+//! bit set as well).
+//!
+//! \return This function does not return.
+//
+//*****************************************************************************
+void
+SysCtlReset(void)
+{
+ //
+ // Perform a software reset request. This request causes the device to
+ // reset, no further code is executed.
+ //
+ HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ;
+
+ //
+ // The device should have reset, so this should never be reached. Just in
+ // case, loop forever.
+ //
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! Puts the processor into sleep mode.
+//!
+//! This function places the processor into sleep mode; it does not return
+//! until the processor returns to run mode. The peripherals that are enabled
+//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the
+//! processor (if automatic clock gating is enabled with
+//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
+//! operate).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlSleep(void)
+{
+ //
+ // Wait for an interrupt.
+ //
+ CPUwfi();
+}
+
+//*****************************************************************************
+//
+//! Puts the processor into deep-sleep mode.
+//!
+//! This function places the processor into deep-sleep mode; it does not return
+//! until the processor returns to run mode. The peripherals that are enabled
+//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up
+//! the processor (if automatic clock gating is enabled with
+//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
+//! operate).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlDeepSleep(void)
+{
+ //
+ // Enable deep-sleep.
+ //
+ HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
+
+ //
+ // Wait for an interrupt.
+ //
+ CPUwfi();
+
+ //
+ // Disable deep-sleep so that a future sleep works correctly.
+ //
+ HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
+}
+
+//*****************************************************************************
+//
+//! Gets the reason for a reset.
+//!
+//! This function returns the reason(s) for a reset. Because the reset
+//! reasons are sticky until either cleared by software or a power-on reset,
+//! multiple reset reasons may be returned if multiple resets have occurred.
+//! The reset reason is a logical OR of \b SYSCTL_CAUSE_LDO,
+//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR,
+//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
+//!
+//! \return Returns the reason(s) for a reset.
+//
+//*****************************************************************************
+uint32_t
+SysCtlResetCauseGet(void)
+{
+ //
+ // Return the reset reasons.
+ //
+ return(HWREG(SYSCTL_RESC));
+}
+
+//*****************************************************************************
+//
+//! Clears reset reasons.
+//!
+//! \param ui32Causes are the reset causes to be cleared; must be a logical OR
+//! of \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG,
+//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
+//!
+//! This function clears the specified sticky reset reasons. Once cleared,
+//! another reset for the same reason can be detected, and a reset for a
+//! different reason can be distinguished (instead of having two reset causes
+//! set). If the reset reason is used by an application, all reset causes
+//! should be cleared after they are retrieved with SysCtlResetCauseGet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlResetCauseClear(uint32_t ui32Causes)
+{
+ //
+ // Clear the given reset reasons.
+ //
+ HWREG(SYSCTL_RESC) &= ~(ui32Causes);
+}
+
+//*****************************************************************************
+//
+//! Provides a small delay.
+//!
+//! \param ui32Count is the number of delay loop iterations to perform.
+//!
+//! This function provides a means of generating a constant length delay. It
+//! is written in assembly to keep the delay consistent across tool chains,
+//! avoiding the need to tune the delay based on the tool chain in use.
+//!
+//! The loop takes 3 cycles/loop.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#if defined(ewarm) || defined(DOXYGEN)
+void
+SysCtlDelay(uint32_t ui32Count)
+{
+ __asm(" subs r0, #1\n"
+ " bne.n SysCtlDelay\n"
+ " bx lr");
+}
+#endif
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+SysCtlDelay(uint32_t ui32Count)
+{
+ __asm(" subs r0, #1\n"
+ " bne SysCtlDelay\n"
+ " bx lr");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+SysCtlDelay(uint32_t ui32Count)
+{
+ subs r0, #1;
+ bne SysCtlDelay;
+ bx lr;
+}
+#endif
+//
+// For CCS implement this function in pure assembly. This prevents the TI
+// compiler from doing funny things with the optimizer.
+//
+#if defined(ccs)
+__asm(" .sect \".text:SysCtlDelay\"\n"
+ " .clink\n"
+ " .thumbfunc SysCtlDelay\n"
+ " .thumb\n"
+ " .global SysCtlDelay\n"
+ "SysCtlDelay:\n"
+ " subs r0, #1\n"
+ " bne.n SysCtlDelay\n"
+ " bx lr\n");
+#endif
+
+//*****************************************************************************
+//
+//! Sets the configuration of the main oscillator (MOSC) control.
+//!
+//! \param ui32Config is the required configuration of the MOSC control.
+//!
+//! This function configures the control of the main oscillator. The
+//! \e ui32Config is specified as the logical OR of the following values:
+//!
+//! - \b SYSCTL_MOSC_VALIDATE enables the MOSC verification circuit that
+//! detects a failure of the main oscillator (such as a loss of the clock).
+//! - \b SYSCTL_MOSC_INTERRUPT indicates that a MOSC failure should generate an
+//! interrupt instead of resetting the processor.
+//! - \b SYSCTL_MOSC_NO_XTAL indicates that there is no crystal connected to
+//! the OSC0/OSC1 pins, allowing power consumption to be reduced.
+//!
+//! \note The availability of MOSC control varies based on the Tiva part
+//! in use. Please consult the data sheet for the part you are using to
+//! determine whether this support is available. In addition, the capability
+//! of MOSC control varies based on the Tiva part in use.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlMOSCConfigSet(uint32_t ui32Config)
+{
+ //
+ // Configure the MOSC control.
+ //
+ HWREG(SYSCTL_MOSCCTL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Calibrates the precision internal oscillator.
+//!
+//! \param ui32Type is the type of calibration to perform.
+//!
+//! This function performs a calibration of the PIOSC. There are three types
+//! of calibration available; the desired calibration type as specified in
+//! \e ui32Type is one of:
+//!
+//! - \b SYSCTL_PIOSC_CAL_AUTO to perform automatic calibration using the
+//! 32-kHz clock from the hibernate module as a reference. This type is
+//! only possible on parts that have a hibernate module, and then only if
+//! it is enabled and the hibernate module's RTC is also enabled.
+//!
+//! - \b SYSCTL_PIOSC_CAL_FACT to reset the PIOSC calibration to the factory
+//! provided calibration.
+//!
+//! - \b SYSCTL_PIOSC_CAL_USER to set the PIOSC calibration to a user-supplied
+//! value. The value to be used is ORed into the lower 7-bits of this value,
+//! with 0x40 being the ``nominal'' value (in other words, if everything were
+//! perfect, 0x40 provides exactly 16 MHz). Values larger than 0x40
+//! slow down PIOSC, and values smaller than 0x40 speed up PIOSC.
+//!
+//! \return Returns 1 if the calibration was successful and 0 if it failed.
+//
+//*****************************************************************************
+uint32_t
+SysCtlPIOSCCalibrate(uint32_t ui32Type)
+{
+ //
+ // Perform the requested calibration. If performing user calibration, the
+ // UTEN bit must be set with one write, then the UT field in a second
+ // write, and the UPDATE bit in a final write. For other calibration
+ // types, a single write to set UPDATE or CAL is all that is required.
+ //
+ if(ui32Type & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UPDATE))
+ {
+ HWREG(SYSCTL_PIOSCCAL) = ui32Type & SYSCTL_PIOSCCAL_UTEN;
+ HWREG(SYSCTL_PIOSCCAL) =
+ ui32Type & (SYSCTL_PIOSCCAL_UTEN | SYSCTL_PIOSCCAL_UT_M);
+ }
+ HWREG(SYSCTL_PIOSCCAL) = ui32Type;
+
+ //
+ // See if an automatic calibration was requested.
+ //
+ if(ui32Type & SYSCTL_PIOSCCAL_CAL)
+ {
+ //
+ // Wait for the automatic calibration to complete.
+ //
+ while((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) == 0)
+ {
+ }
+
+ //
+ // If the automatic calibration failed, return an error.
+ //
+ if((HWREG(SYSCTL_PIOSCSTAT) & SYSCTL_PIOSCSTAT_CR_M) !=
+ SYSCTL_PIOSCSTAT_CRPASS)
+ {
+ return(0);
+ }
+ }
+
+ //
+ // The calibration was successful.
+ //
+ return(1);
+}
+ uint32_t ui32SysDiv, ui32Osc, ui32OscSelect, ui32RSClkConfig;
+ bool bNewPLL;
+
+
+//*****************************************************************************
+//
+//! Sets the clocking of the device.
+//!
+//! \param ui32Config is the required configuration of the device clocking.
+//!
+//! This function configures the clocking of the device. The input crystal
+//! frequency, oscillator to be used, use of the PLL, and the system clock
+//! divider are all configured with this function.
+//!
+//! The \e ui32Config parameter is the logical OR of several different values,
+//! many of which are grouped into sets where only one can be chosen.
+//!
+//! The system clock divider is chosen with one of the following values:
+//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ...
+//! \b SYSCTL_SYSDIV_64.
+//!
+//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or
+//! \b SYSCTL_USE_OSC.
+//!
+//! The external crystal frequency is chosen with one of the following values:
+//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ,
+//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ,
+//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ,
+//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ,
+//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ,
+//! \b SYSCTL_XTAL_16MHZ, \b SYSCTL_XTAL_16_3MHZ, \b SYSCTL_XTAL_18MHZ,
+//! \b SYSCTL_XTAL_20MHZ, \b SYSCTL_XTAL_24MHZ, or \b SYSCTL_XTAL_25MHz.
+//! Values below \b SYSCTL_XTAL_5MHZ are not valid when the PLL is in
+//! operation.
+//!
+//! The oscillator source is chosen with one of the following values:
+//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4,
+//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only
+//! available on devices with the hibernate module, and then only when the
+//! hibernate module has been enabled.
+//!
+//! The internal and main oscillators are disabled with the
+//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively.
+//! The external oscillator must be enabled in order to use an external clock
+//! source. Note that attempts to disable the oscillator used to clock the
+//! device is prevented by the hardware.
+//!
+//! To clock the system from an external source (such as an external crystal
+//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the
+//! system from the main oscillator, use \b SYSCTL_USE_OSC \b |
+//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use
+//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate
+//! crystal with one of the \b SYSCTL_XTAL_xxx values.
+//!
+//! \note If selecting the PLL as the system clock source (that is, via
+//! \b SYSCTL_USE_PLL), this function polls the PLL lock interrupt to
+//! determine when the PLL has locked. If an interrupt handler for the
+//! system control interrupt is in place, and it responds to and clears the
+//! PLL lock interrupt, this function delays until its timeout has occurred
+//! instead of completing as soon as PLL lock is achieved.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlClockSet(uint32_t ui32Config)
+{
+ uint32_t ui32Delay, ui32RCC, ui32RCC2;
+
+ //
+ // Get the current value of the RCC and RCC2 registers.
+ //
+ ui32RCC = HWREG(SYSCTL_RCC);
+ ui32RCC2 = HWREG(SYSCTL_RCC2);
+
+ //
+ // Bypass the PLL and system clock dividers for now.
+ //
+ ui32RCC |= SYSCTL_RCC_BYPASS;
+ ui32RCC &= ~(SYSCTL_RCC_USESYSDIV);
+ ui32RCC2 |= SYSCTL_RCC2_BYPASS2;
+
+ //
+ // Write the new RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ui32RCC;
+ HWREG(SYSCTL_RCC2) = ui32RCC2;
+
+ //
+ // See if the oscillator needs to be enabled.
+ //
+ if((ui32RCC & SYSCTL_RCC_MOSCDIS) && !(ui32Config & SYSCTL_RCC_MOSCDIS))
+ {
+ //
+ // Make sure that the required oscillators are enabled. For now, the
+ // previously enabled oscillators must be enabled along with the newly
+ // requested oscillators.
+ //
+ ui32RCC &= (~SYSCTL_RCC_MOSCDIS | (ui32Config & SYSCTL_RCC_MOSCDIS));
+
+ //
+ // Write the new RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ui32RCC;
+
+ //
+ // Wait for a bit, giving the oscillator time to stabilize. The number
+ // of iterations is adjusted based on the current clock source; a
+ // smaller number of iterations is required for slower clock rates.
+ //
+ if(((ui32RCC2 & SYSCTL_RCC2_USERCC2) &&
+ (((ui32RCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_30) ||
+ ((ui32RCC2 & SYSCTL_RCC2_OSCSRC2_M) ==
+ SYSCTL_RCC2_OSCSRC2_32))) ||
+ (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) &&
+ ((ui32RCC & SYSCTL_RCC_OSCSRC_M) == SYSCTL_RCC_OSCSRC_30)))
+ {
+ //
+ // Delay for 4096 iterations.
+ //
+ SysCtlDelay(4096);
+ }
+ else
+ {
+ //
+ // Delay for 524,288 iterations.
+ //
+ SysCtlDelay(524288);
+ }
+ }
+
+ //
+ // Set the new crystal value and oscillator source. Because the OSCSRC2
+ // field in RCC2 overlaps the XTAL field in RCC, the OSCSRC field has a
+ // special encoding within ui32Config to avoid the overlap.
+ //
+ ui32RCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M);
+ ui32RCC |= ui32Config & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M);
+ ui32RCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M);
+ ui32RCC2 |= ui32Config & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M);
+ ui32RCC2 |= (ui32Config & 0x00000008) << 3;
+
+ //
+ // Write the new RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ui32RCC;
+ HWREG(SYSCTL_RCC2) = ui32RCC2;
+
+ //
+ // Wait for a bit so that new crystal value and oscillator source can take
+ // effect.
+ //
+ SysCtlDelay(16);
+
+ //
+ // Set the PLL configuration.
+ //
+ ui32RCC &= ~SYSCTL_RCC_PWRDN;
+ ui32RCC |= ui32Config & SYSCTL_RCC_PWRDN;
+ ui32RCC2 &= ~SYSCTL_RCC2_PWRDN2;
+ ui32RCC2 |= ui32Config & SYSCTL_RCC2_PWRDN2;
+
+ //
+ // Clear the PLL lock interrupt.
+ //
+ HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK;
+
+ //
+ // Write the new RCC value.
+ //
+ if(ui32RCC2 & SYSCTL_RCC2_USERCC2)
+ {
+ HWREG(SYSCTL_RCC2) = ui32RCC2;
+ HWREG(SYSCTL_RCC) = ui32RCC;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) = ui32RCC;
+ HWREG(SYSCTL_RCC2) = ui32RCC2;
+ }
+
+ //
+ // Set the requested system divider and disable the appropriate
+ // oscillators. This value is not written immediately.
+ //
+ ui32RCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
+ SYSCTL_RCC_MOSCDIS);
+ ui32RCC |= ui32Config & (SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
+ SYSCTL_RCC_MOSCDIS);
+ ui32RCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M);
+ ui32RCC2 |= ui32Config & SYSCTL_RCC2_SYSDIV2_M;
+ if(ui32Config & SYSCTL_RCC2_DIV400)
+ {
+ ui32RCC |= SYSCTL_RCC_USESYSDIV;
+ ui32RCC2 &= ~(SYSCTL_RCC_USESYSDIV);
+ ui32RCC2 |= ui32Config & (SYSCTL_RCC2_DIV400 | SYSCTL_RCC2_SYSDIV2LSB);
+ }
+ else
+ {
+ ui32RCC2 &= ~(SYSCTL_RCC2_DIV400);
+ }
+
+ //
+ // See if the PLL output is being used to clock the system.
+ //
+ if(!(ui32Config & SYSCTL_RCC_BYPASS))
+ {
+ //
+ // Wait until the PLL has locked.
+ //
+ for(ui32Delay = 32768; ui32Delay > 0; ui32Delay--)
+ {
+ if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK)
+ {
+ break;
+ }
+ }
+
+ //
+ // Enable use of the PLL.
+ //
+ ui32RCC &= ~(SYSCTL_RCC_BYPASS);
+ ui32RCC2 &= ~(SYSCTL_RCC2_BYPASS2);
+ }
+
+ //
+ // Write the final RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ui32RCC;
+ HWREG(SYSCTL_RCC2) = ui32RCC2;
+
+ //
+ // Delay for a little bit so that the system divider takes effect.
+ //
+ SysCtlDelay(16);
+}
+
+//*****************************************************************************
+//
+//! Gets the processor clock rate.
+//!
+//! This function determines the clock rate of the processor clock, which is
+//! also the clock rate of the peripheral modules (with the exception of
+//! PWM, which has its own clock divider; other peripherals may have different
+//! clocking, see the device data sheet for details).
+//!
+//! \note This cannot return accurate results if SysCtlClockSet() has not
+//! been called to configure the clocking of the device, or if the device is
+//! directly clocked from a crystal (or a clock source) that is not one of the
+//! supported crystal frequencies. In the latter case, this function should be
+//! modified to directly return the correct system clock rate.
+//!
+//! \return The processor clock rate.
+//
+//*****************************************************************************
+uint32_t
+SysCtlClockGet(void)
+{
+ uint32_t ui32RCC, ui32RCC2, ui32PLL, ui32Clk;
+ uint32_t ui32PLL1;
+
+ //
+ // This function is only valid on Blizzard-class devices.
+ //
+ ASSERT(CLASS_IS_BLIZZARD);
+
+ //
+ // Read RCC and RCC2.
+ //
+ ui32RCC = HWREG(SYSCTL_RCC);
+ ui32RCC2 = HWREG(SYSCTL_RCC2);
+
+ //
+ // Get the base clock rate.
+ //
+ switch((ui32RCC2 & SYSCTL_RCC2_USERCC2) ?
+ (ui32RCC2 & SYSCTL_RCC2_OSCSRC2_M) :
+ (ui32RCC & SYSCTL_RCC_OSCSRC_M))
+ {
+ //
+ // The main oscillator is the clock source. Determine its rate from
+ // the crystal setting field.
+ //
+ case SYSCTL_RCC_OSCSRC_MAIN:
+ {
+ ui32Clk = g_pui32Xtals[(ui32RCC & SYSCTL_RCC_XTAL_M) >>
+ SYSCTL_RCC_XTAL_S];
+ break;
+ }
+
+ //
+ // The internal oscillator is the source clock.
+ //
+ case SYSCTL_RCC_OSCSRC_INT:
+ {
+ //
+ // The internal oscillator on all devices is 16 MHz.
+ //
+ ui32Clk = 16000000;
+ break;
+ }
+
+ //
+ // The internal oscillator divided by four is the source clock.
+ //
+ case SYSCTL_RCC_OSCSRC_INT4:
+ {
+ //
+ // The internal oscillator on all devices is 16 MHz.
+ //
+ ui32Clk = 16000000 / 4;
+ break;
+ }
+
+ //
+ // The internal 30-KHz oscillator is the source clock.
+ //
+ case SYSCTL_RCC_OSCSRC_30:
+ {
+ //
+ // The internal 30-KHz oscillator has an accuracy of +/- 30%.
+ //
+ ui32Clk = 30000;
+ break;
+ }
+
+ //
+ // The 32.768-KHz clock from the hibernate module is the source clock.
+ //
+ case SYSCTL_RCC2_OSCSRC2_32:
+ {
+ ui32Clk = 32768;
+ break;
+ }
+
+ //
+ // An unknown setting, so return a zero clock (that is, an unknown
+ // clock rate).
+ //
+ default:
+ {
+ return(0);
+ }
+ }
+
+ //
+ // See if the PLL is being used.
+ //
+ if(((ui32RCC2 & SYSCTL_RCC2_USERCC2) &&
+ !(ui32RCC2 & SYSCTL_RCC2_BYPASS2)) ||
+ (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) && !(ui32RCC & SYSCTL_RCC_BYPASS)))
+ {
+ //
+ // Read the two PLL frequency registers. The formula for a
+ // Blizzard-class device is "(xtal * m) / ((q + 1) * (n + 1))".
+ //
+ ui32PLL = HWREG(SYSCTL_PLLFREQ0);
+ ui32PLL1 = HWREG(SYSCTL_PLLFREQ1);
+
+ //
+ // Divide the input clock by the dividers.
+ //
+ ui32Clk /= ((((ui32PLL1 & SYSCTL_PLLFREQ1_Q_M) >>
+ SYSCTL_PLLFREQ1_Q_S) + 1) *
+ (((ui32PLL1 & SYSCTL_PLLFREQ1_N_M) >>
+ SYSCTL_PLLFREQ1_N_S) + 1) * 2);
+
+ //
+ // Multiply the clock by the multiplier, which is split into an
+ // integer part and a fractional part.
+ //
+ ui32Clk = ((ui32Clk * ((ui32PLL & SYSCTL_PLLFREQ0_MINT_M) >>
+ SYSCTL_PLLFREQ0_MINT_S)) +
+ ((ui32Clk * ((ui32PLL & SYSCTL_PLLFREQ0_MFRAC_M) >>
+ SYSCTL_PLLFREQ0_MFRAC_S)) >> 10));
+
+ //
+ // Force the system divider to be enabled. It is always used when
+ // using the PLL, but in some cases it does not read as being enabled.
+ //
+ ui32RCC |= SYSCTL_RCC_USESYSDIV;
+ }
+
+ //
+ // See if the system divider is being used.
+ //
+ if(ui32RCC & SYSCTL_RCC_USESYSDIV)
+ {
+ //
+ // Adjust the clock rate by the system clock divider.
+ //
+ if(ui32RCC2 & SYSCTL_RCC2_USERCC2)
+ {
+ if((ui32RCC2 & SYSCTL_RCC2_DIV400) &&
+ (((ui32RCC2 & SYSCTL_RCC2_USERCC2) &&
+ !(ui32RCC2 & SYSCTL_RCC2_BYPASS2)) ||
+ (!(ui32RCC2 & SYSCTL_RCC2_USERCC2) &&
+ !(ui32RCC & SYSCTL_RCC_BYPASS))))
+
+ {
+ ui32Clk = ((ui32Clk * 2) / (((ui32RCC2 &
+ (SYSCTL_RCC2_SYSDIV2_M |
+ SYSCTL_RCC2_SYSDIV2LSB)) >>
+ (SYSCTL_RCC2_SYSDIV2_S - 1)) +
+ 1));
+ }
+ else
+ {
+ ui32Clk /= (((ui32RCC2 & SYSCTL_RCC2_SYSDIV2_M) >>
+ SYSCTL_RCC2_SYSDIV2_S) + 1);
+ }
+ }
+ else
+ {
+ ui32Clk /= (((ui32RCC & SYSCTL_RCC_SYSDIV_M) >>
+ SYSCTL_RCC_SYSDIV_S) + 1);
+ }
+ }
+
+ //
+ // Return the computed clock rate.
+ //
+ return(ui32Clk);
+}
+
+//*****************************************************************************
+//
+//! Sets the clocking of the device while in deep-sleep mode.
+//!
+//! \param ui32Config is the required configuration of the device clocking
+//! while in deep-sleep mode.
+//!
+//! This function configures the clocking of the device while in deep-sleep
+//! mode. The oscillator to be used and the system clock divider are
+//! configured with this function.
+//!
+//! The \e ui32Config parameter is the logical OR of the following values:
+//!
+//! The system clock divider is chosen from one of the following values:
+//! \b SYSCTL_DSLP_DIV_1, \b SYSCTL_DSLP_DIV_2, \b SYSCTL_DSLP_DIV_3, ...
+//! \b SYSCTL_DSLP_DIV_64.
+//!
+//! The oscillator source is chosen from one of the following values:
+//! \b SYSCTL_DSLP_OSC_MAIN, \b SYSCTL_DSLP_OSC_INT, \b SYSCTL_DSLP_OSC_INT30,
+//! or \b SYSCTL_DSLP_OSC_EXT32. \b SYSCTL_OSC_EXT32 is only available on
+//! devices with the hibernation module, and then only when the hibernation
+//! module has been enabled.
+//!
+//! The precision internal oscillator can be powered down in deep-sleep mode by
+//! specifying \b SYSCTL_DSLP_PIOSC_PD. The precision internal oscillator is
+//! not powered down if it is required for operation while in deep-sleep
+//! (based on other configuration settings.)
+//! \note The availability of deep-sleep clocking configuration varies with the
+//! Tiva part in use. Please consult the data sheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlDeepSleepClockSet(uint32_t ui32Config)
+{
+ //
+ // Set the deep-sleep clock configuration.
+ //
+ HWREG(SYSCTL_DSLPCLKCFG) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Sets the PWM clock configuration.
+//!
+//! \param ui32Config is the configuration for the PWM clock; it must be one of
+//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
+//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
+//! \b SYSCTL_PWMDIV_64.
+//!
+//! This function configures the rate of the clock provided to the PWM module
+//! as a ratio of the processor clock. This clock is used by the PWM module to
+//! generate PWM signals; its rate forms the basis for all PWM signals.
+//!
+//! \note The clocking of the PWM is dependent upon the system clock rate as
+//! configured by SysCtlClockSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPWMClockSet(uint32_t ui32Config)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Config == SYSCTL_PWMDIV_1) ||
+ (ui32Config == SYSCTL_PWMDIV_2) ||
+ (ui32Config == SYSCTL_PWMDIV_4) ||
+ (ui32Config == SYSCTL_PWMDIV_8) ||
+ (ui32Config == SYSCTL_PWMDIV_16) ||
+ (ui32Config == SYSCTL_PWMDIV_32) ||
+ (ui32Config == SYSCTL_PWMDIV_64));
+
+ //
+ // Check that there is a PWM block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & (SYSCTL_DC1_PWM0 | SYSCTL_DC1_PWM1));
+
+ //
+ // Set the PWM clock configuration into the run-mode clock configuration
+ // register.
+ //
+ HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) &
+ ~(SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)) |
+ ui32Config);
+}
+
+//*****************************************************************************
+//
+//! Gets the current PWM clock configuration.
+//!
+//! This function returns the current PWM clock configuration.
+//!
+//! \return Returns the current PWM clock configuration; is one of
+//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
+//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
+//! \b SYSCTL_PWMDIV_64.
+//
+//*****************************************************************************
+uint32_t
+SysCtlPWMClockGet(void)
+{
+ //
+ // Check that there is a PWM block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & (SYSCTL_DC1_PWM0 | SYSCTL_DC1_PWM1));
+
+ //
+ // Return the current PWM clock configuration. Make sure that
+ // SYSCTL_PWMDIV_1 is returned in all cases where the divider is disabled.
+ //
+ if(!(HWREG(SYSCTL_RCC) & SYSCTL_RCC_USEPWMDIV))
+ {
+ //
+ // The divider is not active so reflect this in the value we return.
+ //
+ return(SYSCTL_PWMDIV_1);
+ }
+ else
+ {
+ //
+ // The divider is active so directly return the masked register value.
+ //
+ return(HWREG(SYSCTL_RCC) &
+ (SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the sample rate of the ADC.
+//!
+//! \param ui32Speed is the desired sample rate of the ADC; must be one of
+//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,
+//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.
+//!
+//! This function configures the rate at which the ADC samples are captured by
+//! the ADC block. The sampling speed may be limited by the hardware, so the
+//! sample rate may end up being slower than requested. SysCtlADCSpeedGet()
+//! returns the actual speed in use.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlADCSpeedSet(uint32_t ui32Speed)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Speed == SYSCTL_ADCSPEED_1MSPS) ||
+ (ui32Speed == SYSCTL_ADCSPEED_500KSPS) ||
+ (ui32Speed == SYSCTL_ADCSPEED_250KSPS) ||
+ (ui32Speed == SYSCTL_ADCSPEED_125KSPS));
+
+ //
+ // Set the ADC speed in run and sleep mode.
+ //
+ HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_RCGC0_ADC1SPD_M |
+ SYSCTL_RCGC0_ADC0SPD_M)) |
+ ui32Speed);
+ HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SCGC0_ADCSPD_M)) |
+ ui32Speed);
+}
+
+//*****************************************************************************
+//
+//! Gets the sample rate of the ADC.
+//!
+//! This function gets the current sample rate of the ADC.
+//!
+//! \return Returns the current ADC sample rate; is one of
+//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,
+//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.
+//
+//*****************************************************************************
+uint32_t
+SysCtlADCSpeedGet(void)
+{
+ //
+ // Return the current ADC speed.
+ //
+ return(HWREG(SYSCTL_RCGC0) & (SYSCTL_RCGC0_ADC1SPD_M |
+ SYSCTL_RCGC0_ADC0SPD_M));
+}
+
+//*****************************************************************************
+//
+//! Enables access to a GPIO peripheral via the AHB.
+//!
+//! \param ui32GPIOPeripheral is the GPIO peripheral to enable.
+//!
+//! This function is used to enable the specified GPIO peripheral to be
+//! accessed from the Advanced Host Bus (AHB) instead of the legacy Advanced
+//! Peripheral Bus (APB). When a GPIO peripheral is enabled for AHB access,
+//! the \b _AHB_BASE form of the base address should be used for GPIO
+//! functions. For example, instead of using \b GPIO_PORTA_BASE as the base
+//! address for GPIO functions, use \b GPIO_PORTA_AHB_BASE instead.
+//!
+//! The \e ui32GPIOPeripheral argument must be only one of the following
+//! values:
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
+
+ //
+ // Enable this GPIO for AHB access.
+ //
+ HWREG(SYSCTL_GPIOHBCTL) |= (1 << (ui32GPIOPeripheral & 0xF));
+}
+
+//*****************************************************************************
+//
+//! Disables access to a GPIO peripheral via the AHB.
+//!
+//! \param ui32GPIOPeripheral is the GPIO peripheral to disable.
+//!
+//! This function disables the specified GPIO peripheral for access from the
+//! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed
+//! from the legacy Advanced Peripheral Bus (APB).
+//!
+//! The \b ui32GPIOPeripheral argument must be only one of the following
+//! values:
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH, or \b SYSCTL_PERIPH_GPIOJ.
+//!
+//! \note Some devices allow disabling AHB access to GPIO ports that are only
+//! present on the AHB. Disabling AHB access to these ports will disable
+//! access to these GPIO ports.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
+ (ui32GPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
+
+ //
+ // Disable this GPIO for AHB access.
+ //
+ HWREG(SYSCTL_GPIOHBCTL) &= ~(1 << (ui32GPIOPeripheral & 0xF));
+}
+
+//*****************************************************************************
+//
+//! Powers up the USB PLL.
+//!
+//! This function enables the USB controller's PLL, which is used by its
+//! physical layer. This call is necessary before connecting to any external
+//! devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlUSBPLLEnable(void)
+{
+ //
+ // Turn on the USB PLL.
+ //
+ HWREG(SYSCTL_RCC2) &= ~SYSCTL_RCC2_USBPWRDN;
+}
+
+//*****************************************************************************
+//
+//! Powers down the USB PLL.
+//!
+//! This function disables the USB controller's PLL, which is used by its
+//! physical layer. The USB registers are still accessible, but the physical
+//! layer no longer functions.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlUSBPLLDisable(void)
+{
+ //
+ // Turn off the USB PLL.
+ //
+ HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sysctl.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sysctl.h
new file mode 100644
index 00000000..25e8679c
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sysctl.h
@@ -0,0 +1,527 @@
+//*****************************************************************************
+//
+// sysctl.h - Prototypes for the system control driver.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SYSCTL_H__
+#define __DRIVERLIB_SYSCTL_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
+// ui32Peripheral parameter. The peripherals in the fourth group (upper nibble
+// is 3) can only be used with the SysCtlPeripheralPresent() API.
+//
+//*****************************************************************************
+#define SYSCTL_PERIPH_ADC0 0xf0003800 // ADC 0
+#define SYSCTL_PERIPH_ADC1 0xf0003801 // ADC 1
+#define SYSCTL_PERIPH_CAN0 0xf0003400 // CAN 0
+#define SYSCTL_PERIPH_CAN1 0xf0003401 // CAN 1
+#define SYSCTL_PERIPH_CAN2 0xf0003402 // CAN 2
+#define SYSCTL_PERIPH_COMP0 0xf0003c00 // Analog comparator 0
+#define SYSCTL_PERIPH_COMP1 0xf0003c01 // Analog comparator 1
+#define SYSCTL_PERIPH_COMP2 0xf0003c02 // Analog comparator 2
+#define SYSCTL_PERIPH_GPIOA 0xf0000800 // GPIO A
+#define SYSCTL_PERIPH_GPIOB 0xf0000801 // GPIO B
+#define SYSCTL_PERIPH_GPIOC 0xf0000802 // GPIO C
+#define SYSCTL_PERIPH_GPIOD 0xf0000803 // GPIO D
+#define SYSCTL_PERIPH_GPIOE 0xf0000804 // GPIO E
+#define SYSCTL_PERIPH_GPIOF 0xf0000805 // GPIO F
+#define SYSCTL_PERIPH_GPIOG 0xf0000806 // GPIO G
+#define SYSCTL_PERIPH_GPIOH 0xf0000807 // GPIO H
+#define SYSCTL_PERIPH_GPIOJ 0xf0000808 // GPIO J
+#define SYSCTL_PERIPH_HIBERNATE 0xf0001400 // Hibernation module
+#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0
+#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0
+#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K
+#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L
+#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M
+#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N
+#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P
+#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q
+#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R
+#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S
+#define SYSCTL_PERIPH_I2C0 0xf0002000 // I2C 0
+#define SYSCTL_PERIPH_I2C1 0xf0002001 // I2C 1
+#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2
+#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3
+#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4
+#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5
+#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0
+#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0
+#define SYSCTL_PERIPH_PWM0 0xf0004000 // PWM 0
+#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1
+#define SYSCTL_PERIPH_QEI0 0xf0004400 // QEI 0
+#define SYSCTL_PERIPH_QEI1 0xf0004401 // QEI 1
+#define SYSCTL_PERIPH_SSI0 0xf0001c00 // SSI 0
+#define SYSCTL_PERIPH_SSI1 0xf0001c01 // SSI 1
+#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2
+#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3
+#define SYSCTL_PERIPH_TIMER0 0xf0000400 // Timer 0
+#define SYSCTL_PERIPH_TIMER1 0xf0000401 // Timer 1
+#define SYSCTL_PERIPH_TIMER2 0xf0000402 // Timer 2
+#define SYSCTL_PERIPH_TIMER3 0xf0000403 // Timer 3
+#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4
+#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5
+#define SYSCTL_PERIPH_UART0 0xf0001800 // UART 0
+#define SYSCTL_PERIPH_UART1 0xf0001801 // UART 1
+#define SYSCTL_PERIPH_UART2 0xf0001802 // UART 2
+#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3
+#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4
+#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5
+#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6
+#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7
+#define SYSCTL_PERIPH_UDMA 0xf0000c00 // uDMA
+#define SYSCTL_PERIPH_USB0 0xf0002800 // USB 0
+#define SYSCTL_PERIPH_WDOG0 0xf0000000 // Watchdog 0
+#define SYSCTL_PERIPH_WDOG1 0xf0000001 // Watchdog 1
+#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0
+#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1
+#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2
+#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3
+#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4
+#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlIntEnable(),
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
+// by the SysCtlIntStatus() API.
+//
+//*****************************************************************************
+#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
+#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlResetCauseClear()
+// API or returned by the SysCtlResetCauseGet() API.
+//
+//*****************************************************************************
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
+#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
+#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()
+// API as the ui32Config parameter.
+//
+//*****************************************************************************
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPWMClockSet() API
+// as the ui32Config parameter, and can be returned by the SysCtlPWMClockGet()
+// API.
+//
+//*****************************************************************************
+#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
+#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
+#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
+#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
+#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
+#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
+#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlADCSpeedSet() API
+// as the ui32Speed parameter, and can be returned by the SysCtlADCSpeedGet()
+// API.
+//
+//*****************************************************************************
+#define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second
+#define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second
+#define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlClockSet() API as
+// the ui32Config parameter.
+//
+//*****************************************************************************
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
+#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
+#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
+#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
+#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
+#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
+#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
+#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
+#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
+#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
+#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
+#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
+#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
+#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
+#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
+#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
+#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
+#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
+#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
+#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
+#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
+#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
+#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
+#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
+#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
+#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
+#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
+#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
+#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
+#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
+#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
+#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
+#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
+#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
+#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
+#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
+#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
+#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
+#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
+#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
+#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
+#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
+#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
+#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
+#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
+#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
+#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
+#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
+#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
+#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
+#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
+#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
+#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
+#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
+#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
+#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
+#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
+#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
+#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
+#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
+#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
+#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
+#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
+#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
+#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
+#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
+#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
+#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
+#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
+#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
+#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
+#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
+#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
+#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
+#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
+#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
+#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
+#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
+#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
+#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
+#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
+#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
+#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
+#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
+#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
+#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
+#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
+#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
+#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
+#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
+#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
+#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
+#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
+#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
+#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
+#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
+#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
+#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
+#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
+#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
+#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
+#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
+#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
+#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
+#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
+#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
+#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
+#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
+#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
+#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
+#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
+#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
+#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
+#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
+#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
+#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
+#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
+#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
+#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
+#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
+#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
+#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
+#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz
+#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz
+#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz
+#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz
+#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
+#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
+#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
+#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
+#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
+#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
+#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlDeepSleepClockSet()
+// API as the ui32Config parameter.
+//
+//*****************************************************************************
+#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1
+#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2
+#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3
+#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4
+#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5
+#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6
+#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7
+#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8
+#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9
+#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10
+#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11
+#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12
+#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13
+#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14
+#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15
+#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16
+#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17
+#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18
+#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19
+#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20
+#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21
+#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22
+#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23
+#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24
+#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25
+#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26
+#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27
+#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28
+#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29
+#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30
+#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31
+#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32
+#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33
+#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34
+#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35
+#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36
+#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37
+#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38
+#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39
+#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40
+#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41
+#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42
+#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43
+#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44
+#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45
+#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46
+#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47
+#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48
+#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49
+#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50
+#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51
+#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52
+#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53
+#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54
+#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55
+#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56
+#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57
+#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58
+#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59
+#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60
+#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61
+#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62
+#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63
+#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64
+#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc
+#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc
+#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
+#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz
+#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPIOSCCalibrate()
+// API as the ui32Type parameter.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration
+#define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration
+#define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlMOSCConfigSet() API
+// as the ui32Config parameter.
+//
+//*****************************************************************************
+#define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation
+#define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail
+#define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern uint32_t SysCtlSRAMSizeGet(void);
+extern uint32_t SysCtlFlashSizeGet(void);
+extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral);
+extern bool SysCtlPeripheralReady(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralPowerOn(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralPowerOff(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralReset(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralClockGating(bool bEnable);
+extern void SysCtlIntRegister(void (*pfnHandler)(void));
+extern void SysCtlIntUnregister(void);
+extern void SysCtlIntEnable(uint32_t ui32Ints);
+extern void SysCtlIntDisable(uint32_t ui32Ints);
+extern void SysCtlIntClear(uint32_t ui32Ints);
+extern uint32_t SysCtlIntStatus(bool bMasked);
+extern void SysCtlLDOConfigSet(uint32_t ui32Config);
+extern void SysCtlReset(void);
+extern void SysCtlSleep(void);
+extern void SysCtlDeepSleep(void);
+extern uint32_t SysCtlResetCauseGet(void);
+extern void SysCtlResetCauseClear(uint32_t ui32Causes);
+extern void SysCtlBrownOutConfigSet(uint32_t ui32Config,
+ uint32_t ui32Delay);
+extern void SysCtlDelay(uint32_t ui32Count);
+extern void SysCtlMOSCConfigSet(uint32_t ui32Config);
+extern uint32_t SysCtlPIOSCCalibrate(uint32_t ui32Type);
+extern void SysCtlClockSet(uint32_t ui32Config);
+extern uint32_t SysCtlClockGet(void);
+extern void SysCtlDeepSleepClockSet(uint32_t ui32Config);
+extern void SysCtlPWMClockSet(uint32_t ui32Config);
+extern uint32_t SysCtlPWMClockGet(void);
+extern void SysCtlADCSpeedSet(uint32_t ui32Speed);
+extern uint32_t SysCtlADCSpeedGet(void);
+extern void SysCtlIOSCVerificationSet(bool bEnable);
+extern void SysCtlMOSCVerificationSet(bool bEnable);
+extern void SysCtlPLLVerificationSet(bool bEnable);
+extern void SysCtlClkVerificationClear(void);
+extern void SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral);
+extern void SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral);
+extern void SysCtlUSBPLLEnable(void);
+extern void SysCtlUSBPLLDisable(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SYSCTL_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sysexc.c b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sysexc.c
new file mode 100644
index 00000000..c4996dac
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sysexc.c
@@ -0,0 +1,307 @@
+//*****************************************************************************
+//
+// sysexc.c - Routines for the System Exception Module.
+//
+// Copyright (c) 2011-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup sysexc_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_ints.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_sysexc.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Returns the interrupt number for a system exception.
+//!
+//! This function returns the interrupt number for a system exception.
+//!
+//! \return Returns the system exception interrupt number.
+//
+//*****************************************************************************
+static uint32_t
+_SysExcIntNumberGet(void)
+{
+ uint32_t ui32Int;
+
+ //
+ // Get the interrupt number based on the class.
+ //
+ if(CLASS_IS_BLIZZARD)
+ {
+ ui32Int = INT_SYSEXC_BLIZZARD;
+ }
+ else
+ {
+ ui32Int = 0;
+ }
+ return(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the system exception interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the system
+//! exception interrupt occurs.
+//!
+//! This function places the address of the system exception interrupt handler
+//! into the interrupt vector table in SRAM. This function also enables the
+//! global interrupt in the interrupt controller; specific system exception
+//! interrupts must be enabled via SysExcIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysExcIntRegister(void (*pfnHandler)(void))
+{
+ uint32_t ui32Int;
+
+ //
+ // Get the system exception interrupt number.
+ //
+ ui32Int = _SysExcIntNumberGet();
+
+ ASSERT(ui32Int != 0);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ui32Int, pfnHandler);
+
+ //
+ // Enable the system exception interrupt.
+ //
+ IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the system exception interrupt handler.
+//!
+//! This function removes the system exception interrupt handler from the
+//! vector table in SRAM. This function also masks off the system exception
+//! interrupt in the interrupt controller so that the interrupt handler is no
+//! longer called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysExcIntUnregister(void)
+{
+ uint32_t ui32Int;
+
+ //
+ // Get the system exception interrupt number.
+ //
+ ui32Int = _SysExcIntNumberGet();
+
+ ASSERT(ui32Int != 0);
+
+ //
+ // Disable the system exception interrupt.
+ //
+ IntDisable(ui32Int);
+
+ //
+ // Unregister the system exception interrupt handler.
+ //
+ IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Enables individual system exception interrupt sources.
+//!
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated system exception interrupt sources.
+//! Only the sources that are enabled can be reflected to the processor
+//! interrupt; disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
+//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
+//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
+//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
+//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
+//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysExcIntEnable(uint32_t ui32IntFlags)
+{
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(SYSEXC_IM) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual system exception interrupt sources.
+//!
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! This function disables the indicated system exception interrupt sources.
+//! Only sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
+//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
+//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
+//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
+//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
+//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysExcIntDisable(uint32_t ui32IntFlags)
+{
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(SYSEXC_IM) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current system exception interrupt status.
+//!
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the system exception interrupt status. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return Returns the current system exception interrupt status, enumerated
+//! as the logical OR of \b SYSEXC_INT_FP_IXC, \b SYSEXC_INT_FP_OFC,
+//! \b SYSEXC_INT_FP_UFC, \b SYSEXC_INT_FP_IOC, \b SYSEXC_INT_FP_DZC, and
+//! \b SYSEXC_INT_FP_IDC.
+//
+//*****************************************************************************
+uint32_t
+SysExcIntStatus(bool bMasked)
+{
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(SYSEXC_MIS));
+ }
+ else
+ {
+ return(HWREG(SYSEXC_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears system exception interrupt sources.
+//!
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! This function clears the specified system exception interrupt sources, so
+//! that they no longer assert. This function must be called in the interrupt
+//! handler to keep the interrupt from being recognized again immediately upon
+//! exit.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b SYSEXC_INT_FP_IXC - Floating-point inexact exception interrupt
+//! - \b SYSEXC_INT_FP_OFC - Floating-point overflow exception interrupt
+//! - \b SYSEXC_INT_FP_UFC - Floating-point underflow exception interrupt
+//! - \b SYSEXC_INT_FP_IOC - Floating-point invalid operation interrupt
+//! - \b SYSEXC_INT_FP_DZC - Floating-point divide by zero exception interrupt
+//! - \b SYSEXC_INT_FP_IDC - Floating-point input denormal exception interrupt
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysExcIntClear(uint32_t ui32IntFlags)
+{
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(SYSEXC_IC) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sysexc.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sysexc.h
new file mode 100644
index 00000000..9fdf97ab
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/sysexc.h
@@ -0,0 +1,89 @@
+//*****************************************************************************
+//
+// sysexc.h - Prototypes for the System Exception Module routines.
+//
+// Copyright (c) 2011-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SYSEXC_H__
+#define __DRIVERLIB_SYSEXC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and
+// SysExcIntClear as the ui32IntFlags parameter, and returned from
+// SysExcIntStatus.
+//
+//*****************************************************************************
+#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt
+#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt
+#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt
+#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt
+#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int
+#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern void SysExcIntRegister(void (*pfnHandler)(void));
+extern void SysExcIntUnregister(void);
+extern void SysExcIntEnable(uint32_t ui32IntFlags);
+extern void SysExcIntDisable(uint32_t ui32IntFlags);
+extern uint32_t SysExcIntStatus(bool bMasked);
+extern void SysExcIntClear(uint32_t ui32IntFlags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SYSEXC_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/systick.c b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/systick.c
new file mode 100644
index 00000000..22e3aeff
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/systick.c
@@ -0,0 +1,277 @@
+//*****************************************************************************
+//
+// systick.c - Driver for the SysTick timer in NVIC.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup systick_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/systick.h"
+
+//*****************************************************************************
+//
+//! Enables the SysTick counter.
+//!
+//! This function starts the SysTick counter. If an interrupt handler has been
+//! registered, it is called when the SysTick counter rolls over.
+//!
+//! \note Calling this function causes the SysTick counter to (re)commence
+//! counting from its current value. The counter is not automatically reloaded
+//! with the period as specified in a previous call to SysTickPeriodSet(). If
+//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
+//! written to force the reload. Any write to this register clears the SysTick
+//! counter to 0 and causes a reload with the supplied period on the next
+//! clock.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickEnable(void)
+{
+ //
+ // Enable SysTick.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick counter.
+//!
+//! This function stops the SysTick counter. If an interrupt handler has been
+//! registered, it is not called until SysTick is restarted.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickDisable(void)
+{
+ //
+ // Disable SysTick.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the SysTick interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! SysTick interrupt occurs.
+//!
+//! This function registers the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(FAULT_SYSTICK, pfnHandler);
+
+ //
+ // Enable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the SysTick interrupt.
+//!
+//! This function unregisters the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntUnregister(void)
+{
+ //
+ // Disable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(FAULT_SYSTICK);
+}
+
+//*****************************************************************************
+//
+//! Enables the SysTick interrupt.
+//!
+//! This function enables the SysTick interrupt, allowing it to be
+//! reflected to the processor.
+//!
+//! \note The SysTick interrupt handler is not required to clear the SysTick
+//! interrupt source because it is cleared automatically by the NVIC when the
+//! interrupt handler is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntEnable(void)
+{
+ //
+ // Enable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick interrupt.
+//!
+//! This function disables the SysTick interrupt, preventing it from being
+//! reflected to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntDisable(void)
+{
+ //
+ // Disable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+}
+
+//*****************************************************************************
+//
+//! Sets the period of the SysTick counter.
+//!
+//! \param ui32Period is the number of clock ticks in each period of the
+//! SysTick counter and must be between 1 and 16,777,216, inclusive.
+//!
+//! This function sets the rate at which the SysTick counter wraps, which
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \note Calling this function does not cause the SysTick counter to reload
+//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
+//! register must be written. Any write to this register clears the SysTick
+//! counter to 0 and causes a reload with the \e ui32Period supplied here on
+//! the next clock after SysTick is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickPeriodSet(uint32_t ui32Period)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Period > 0) && (ui32Period <= 16777216));
+
+ //
+ // Set the period of the SysTick counter.
+ //
+ HWREG(NVIC_ST_RELOAD) = ui32Period - 1;
+}
+
+//*****************************************************************************
+//
+//! Gets the period of the SysTick counter.
+//!
+//! This function returns the rate at which the SysTick counter wraps, which
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \return Returns the period of the SysTick counter.
+//
+//*****************************************************************************
+uint32_t
+SysTickPeriodGet(void)
+{
+ //
+ // Return the period of the SysTick counter.
+ //
+ return(HWREG(NVIC_ST_RELOAD) + 1);
+}
+
+//*****************************************************************************
+//
+//! Gets the current value of the SysTick counter.
+//!
+//! This function returns the current value of the SysTick counter, which is
+//! a value between the period - 1 and zero, inclusive.
+//!
+//! \return Returns the current value of the SysTick counter.
+//
+//*****************************************************************************
+uint32_t
+SysTickValueGet(void)
+{
+ //
+ // Return the current value of the SysTick counter.
+ //
+ return(HWREG(NVIC_ST_CURRENT));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/systick.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/systick.h
new file mode 100644
index 00000000..4f1acd24
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/systick.h
@@ -0,0 +1,78 @@
+//*****************************************************************************
+//
+// systick.h - Prototypes for the SysTick driver.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_SYSTICK_H__
+#define __DRIVERLIB_SYSTICK_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SysTickEnable(void);
+extern void SysTickDisable(void);
+extern void SysTickIntRegister(void (*pfnHandler)(void));
+extern void SysTickIntUnregister(void);
+extern void SysTickIntEnable(void);
+extern void SysTickIntDisable(void);
+extern void SysTickPeriodSet(uint32_t ui32Period);
+extern uint32_t SysTickPeriodGet(void);
+extern uint32_t SysTickValueGet(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_SYSTICK_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/timer.c b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/timer.c
new file mode 100644
index 00000000..5817c695
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/timer.c
@@ -0,0 +1,1474 @@
+//*****************************************************************************
+//
+// timer.c - Driver for the timer module.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup timer_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_timer.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/timer.h"
+
+//*****************************************************************************
+//
+// A mapping of timer base address to interrupt number.
+//
+//*****************************************************************************
+static const uint32_t g_ppui32TimerIntMap[][2] =
+{
+ { TIMER0_BASE, INT_TIMER0A_BLIZZARD },
+ { TIMER1_BASE, INT_TIMER1A_BLIZZARD },
+ { TIMER2_BASE, INT_TIMER2A_BLIZZARD },
+ { TIMER3_BASE, INT_TIMER3A_BLIZZARD },
+ { TIMER4_BASE, INT_TIMER4A_BLIZZARD },
+ { TIMER5_BASE, INT_TIMER5A_BLIZZARD },
+ { WTIMER0_BASE, INT_WTIMER0A_BLIZZARD },
+ { WTIMER1_BASE, INT_WTIMER1A_BLIZZARD },
+ { WTIMER2_BASE, INT_WTIMER2A_BLIZZARD },
+ { WTIMER3_BASE, INT_WTIMER3A_BLIZZARD },
+ { WTIMER4_BASE, INT_WTIMER4A_BLIZZARD },
+ { WTIMER5_BASE, INT_WTIMER5A_BLIZZARD },
+};
+static const uint_fast8_t g_ui8TimerIntMapRows =
+ sizeof(g_ppui32TimerIntMap) / sizeof(g_ppui32TimerIntMap[0]);
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a timer base address.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function determines if a timer module base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_TimerBaseValid(uint32_t ui32Base)
+{
+ return((ui32Base == TIMER0_BASE) || (ui32Base == TIMER1_BASE) ||
+ (ui32Base == TIMER2_BASE) || (ui32Base == TIMER3_BASE) ||
+ (ui32Base == TIMER4_BASE) || (ui32Base == TIMER5_BASE) ||
+ (ui32Base == WTIMER0_BASE) || (ui32Base == WTIMER1_BASE) ||
+ (ui32Base == WTIMER2_BASE) || (ui32Base == WTIMER3_BASE) ||
+ (ui32Base == WTIMER4_BASE) || (ui32Base == WTIMER5_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Returns a timer modules interrupt number.
+//!
+//! \param ui32Base is the base address of the selected timer.
+//! \param ui32Timer specifies the timer(s) to enable; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function returns the interrupt number for a given timer module
+//! specified by the \e ui32Base and \e ui32Timer parameter.
+//!
+//! \return Returns a timer module's interrupt number or 0 if the interrupt
+//! does not exist.
+//
+//*****************************************************************************
+static uint32_t
+_TimerIntNumberGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ uint32_t ui32Int;
+ uint_fast8_t ui8Idx, ui8Rows;
+ const uint32_t (*ppui32SSIIntMap)[2];
+
+ //
+ // Default interrupt map.
+ //
+ ppui32SSIIntMap = g_ppui32TimerIntMap;
+ ui8Rows = g_ui8TimerIntMapRows;
+
+
+ //
+ // Loop through the table that maps timer base addresses to interrupt
+ // numbers.
+ //
+ for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++)
+ {
+ //
+ // See if this base address matches.
+ //
+ if(ppui32SSIIntMap[ui8Idx][0] == ui32Base)
+ {
+ ui32Int = ppui32SSIIntMap[ui8Idx][1];
+
+ if(ui32Timer == TIMER_B)
+ {
+ ui32Int += 1;
+ }
+
+ //
+ // Return the corresponding interrupt number.
+ //
+ return(ui32Int);
+ }
+ }
+
+ //
+ // The base address could not be found, so return an error.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Enables the timer(s).
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to enable; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function enables operation of the timer module. The timer must be
+//! configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerEnable(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Enable the timer(s) module.
+ //
+ HWREG(ui32Base + TIMER_O_CTL) |= ui32Timer & (TIMER_CTL_TAEN |
+ TIMER_CTL_TBEN);
+}
+
+//*****************************************************************************
+//
+//! Disables the timer(s).
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to disable; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function disables operation of the timer module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerDisable(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Disable the timer module.
+ //
+ HWREG(ui32Base + TIMER_O_CTL) &= ~(ui32Timer &
+ (TIMER_CTL_TAEN | TIMER_CTL_TBEN));
+}
+
+//*****************************************************************************
+//
+//! Configures the timer(s).
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Config is the configuration for the timer.
+//!
+//! This function configures the operating mode of the timer(s). The timer
+//! module is disabled before being configured and is left in the disabled
+//! state. The timer can be configured to be a single full-width timer
+//! by using the \b TIMER_CFG_* values or a pair of half-width timers using the
+//! \b TIMER_CFG_A_* and \b TIMER_CFG_B_* values passed in the \e ui32Config
+//! parameter.
+//!
+//! The configuration is specified in \e ui32Config as one of the following
+//! values:
+//!
+//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer
+//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up
+//! instead of down (not available on all parts)
+//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer
+//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up
+//! instead of down (not available on all parts)
+//! - \b TIMER_CFG_RTC - Full-width real time clock timer
+//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers
+//!
+//! When configured for a pair of half-width timers, each timer is separately
+//! configured. The first timer is configured by setting \e ui32Config to
+//! the result of a logical OR operation between one of the following values
+//! and \e ui32Config:
+//!
+//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer
+//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up
+//! instead of down (not available on all parts)
+//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer
+//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up
+//! instead of down (not available on all parts)
+//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture
+//! - \b TIMER_CFG_A_CAP_COUNT_UP - Half-width edge count capture that counts
+//! up instead of down (not available on all parts)
+//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture
+//! - \b TIMER_CFG_A_CAP_TIME_UP - Half-width edge time capture that counts up
+//! instead of down (not available on all parts)
+//! - \b TIMER_CFG_A_PWM - Half-width PWM output
+//!
+//! Similarly, the second timer is configured by setting \e ui32Config to
+//! the result of a logical OR operation between one of the corresponding
+//! \b TIMER_CFG_B_* values and \e ui32Config.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerConfigure(uint32_t ui32Base, uint32_t ui32Config)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) ||
+ (ui32Config == TIMER_CFG_ONE_SHOT_UP) ||
+ (ui32Config == TIMER_CFG_PERIODIC) ||
+ (ui32Config == TIMER_CFG_PERIODIC_UP) ||
+ (ui32Config == TIMER_CFG_RTC) ||
+ ((ui32Config & 0xff000000) == TIMER_CFG_SPLIT_PAIR));
+ ASSERT(((ui32Config & 0xff000000) != TIMER_CFG_SPLIT_PAIR) ||
+ ((((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
+ ((ui32Config & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) ||
+ ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
+ ((ui32Config & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) ||
+ ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
+ ((ui32Config & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
+ ((ui32Config & 0x000000ff) == TIMER_CFG_A_PWM)) &&
+ (((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
+ ((ui32Config & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) ||
+ ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
+ ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) ||
+ ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
+ ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT_UP) ||
+ ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
+ ((ui32Config & 0x0000ff00) == TIMER_CFG_B_CAP_TIME_UP) ||
+ ((ui32Config & 0x0000ff00) == TIMER_CFG_B_PWM))));
+
+ //
+ // Disable the timers.
+ //
+ HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN);
+
+ //
+ // Set the global timer configuration.
+ //
+ HWREG(ui32Base + TIMER_O_CFG) = ui32Config >> 24;
+
+ //
+ // Set the configuration of the A and B timers and set the TxPWMIE bit.
+ // Note that the B timer configuration is ignored by the hardware in 32-bit
+ // modes.
+ //
+ HWREG(ui32Base + TIMER_O_TAMR) = (ui32Config & 255) | TIMER_TAMR_TAPWMIE;
+ HWREG(ui32Base + TIMER_O_TBMR) = (((ui32Config >> 8) & 255) |
+ TIMER_TBMR_TBPWMIE);
+}
+
+//*****************************************************************************
+//
+//! Controls the output level.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bInvert specifies the output level.
+//!
+//! This function configures the PWM output level for the specified timer. If
+//! the \e bInvert parameter is \b true, then the timer's output is made active
+//! low; otherwise, it is made active high.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Set the output levels as requested.
+ //
+ ui32Timer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML;
+ HWREG(ui32Base + TIMER_O_CTL) = (bInvert ?
+ (HWREG(ui32Base + TIMER_O_CTL) |
+ ui32Timer) :
+ (HWREG(ui32Base + TIMER_O_CTL) &
+ ~(ui32Timer)));
+}
+
+//*****************************************************************************
+//
+//! Enables or disables the ADC trigger output.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param bEnable specifies the desired ADC trigger state.
+//!
+//! This function controls the ADC trigger output for the specified timer. If
+//! the \e bEnable parameter is \b true, then the timer's ADC output trigger is
+//! enabled; otherwise it is disabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer,
+ bool bEnable)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Set the trigger output as requested.
+ // Set the ADC trigger output as requested.
+ //
+ ui32Timer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE;
+ HWREG(ui32Base + TIMER_O_CTL) = (bEnable ?
+ (HWREG(ui32Base + TIMER_O_CTL) |
+ ui32Timer) :
+ (HWREG(ui32Base + TIMER_O_CTL) &
+ ~(ui32Timer)));
+}
+
+//*****************************************************************************
+//
+//! Controls the event type.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param ui32Event specifies the type of event; must be one of
+//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or
+//! \b TIMER_EVENT_BOTH_EDGES.
+//!
+//! This function configures the signal edge(s) that triggers the timer when
+//! in capture mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer,
+ uint32_t ui32Event)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Set the event type.
+ //
+ ui32Timer &= TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M;
+ HWREG(ui32Base + TIMER_O_CTL) = ((HWREG(ui32Base + TIMER_O_CTL) &
+ ~ui32Timer) | (ui32Event & ui32Timer));
+}
+
+//*****************************************************************************
+//
+//! Controls the stall handling.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bStall specifies the response to a stall signal.
+//!
+//! This function controls the stall response for the specified timer. If the
+//! \e bStall parameter is \b true, then the timer stops counting if the
+//! processor enters debug mode; otherwise the timer keeps running while in
+//! debug mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer,
+ bool bStall)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Set the stall mode.
+ //
+ ui32Timer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL;
+ HWREG(ui32Base + TIMER_O_CTL) = (bStall ?
+ (HWREG(ui32Base + TIMER_O_CTL) |
+ ui32Timer) :
+ (HWREG(ui32Base + TIMER_O_CTL) &
+ ~(ui32Timer)));
+}
+
+//*****************************************************************************
+//
+//! Controls the wait on trigger handling.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bWait specifies if the timer should wait for a trigger input.
+//!
+//! This function controls whether or not a timer waits for a trigger input to
+//! start counting. When enabled, the previous timer in the trigger chain must
+//! count to its timeout in order for this timer to start counting. Refer to
+//! the part's data sheet for a description of the trigger chain.
+//!
+//! \note This functionality is not available on all parts. This function
+//! should not be used for Timer 0A or Wide Timer 0A.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer,
+ bool bWait)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Set the wait on trigger mode for timer A.
+ //
+ if((ui32Timer & TIMER_A) != 0)
+ {
+ if(bWait)
+ {
+ HWREG(ui32Base + TIMER_O_TAMR) |= TIMER_TAMR_TAWOT;
+ }
+ else
+ {
+ HWREG(ui32Base + TIMER_O_TAMR) &= ~(TIMER_TAMR_TAWOT);
+ }
+ }
+
+ //
+ // Set the wait on trigger mode for timer B.
+ //
+ if((ui32Timer & TIMER_B) != 0)
+ {
+ if(bWait)
+ {
+ HWREG(ui32Base + TIMER_O_TBMR) |= TIMER_TBMR_TBWOT;
+ }
+ else
+ {
+ HWREG(ui32Base + TIMER_O_TBMR) &= ~(TIMER_TBMR_TBWOT);
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Enable RTC counting.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function causes the timer to start counting when in RTC mode. If not
+//! configured for RTC mode, this function does nothing.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerRTCEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+
+ //
+ // Enable RTC counting.
+ //
+ HWREG(ui32Base + TIMER_O_CTL) |= TIMER_CTL_RTCEN;
+}
+
+//*****************************************************************************
+//
+//! Disable RTC counting.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function causes the timer to stop counting when in RTC mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerRTCDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+
+ //
+ // Disable RTC counting.
+ //
+ HWREG(ui32Base + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN);
+}
+
+//*****************************************************************************
+//
+//! Set the timer prescale value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param ui32Value is the timer prescale value which must be between 0 and
+//! 255 (inclusive) for 16/32-bit timers and between 0 and 65535 (inclusive)
+//! for 32/64-bit timers.
+//!
+//! This function configures the value of the input clock prescaler. The
+//! prescaler is only operational when in half-width mode and is used to extend
+//! the range of the half-width timer modes. The prescaler provides the least
+//! significant bits when counting down in periodic and one-shot modes; in all
+//! other modes, the prescaler provides the most significant bits.
+//!
+//! \note The availability of the prescaler varies with the Tiva part and
+//! timer mode in use. Please consult the datasheet for the part you are using
+//! to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+ ASSERT(ui32Value < 256);
+
+ //
+ // Set the timer A prescaler if requested.
+ //
+ if(ui32Timer & TIMER_A)
+ {
+ HWREG(ui32Base + TIMER_O_TAPR) = ui32Value;
+ }
+
+ //
+ // Set the timer B prescaler if requested.
+ //
+ if(ui32Timer & TIMER_B)
+ {
+ HWREG(ui32Base + TIMER_O_TBPR) = ui32Value;
+ }
+}
+
+//*****************************************************************************
+//
+//! Get the timer prescale value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.
+//!
+//! This function gets the value of the input clock prescaler. The prescaler
+//! is only operational when in half-width mode and is used to extend the range
+//! of the half-width timer modes. The prescaler provides the least
+//! significant bits when counting down in periodic and one-shot modes; in all
+//! other modes, the prescaler provides the most significant bits.
+//!
+//! \note The availability of the prescaler varies with the Tiva part and
+//! timer mode in use. Please consult the datasheet for the part you are using
+//! to determine whether this support is available.
+//!
+//! \return The value of the timer prescaler.
+//
+//*****************************************************************************
+uint32_t
+TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Return the appropriate prescale value.
+ //
+ return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPR) :
+ HWREG(ui32Base + TIMER_O_TBPR));
+}
+
+//*****************************************************************************
+//
+//! Set the timer prescale match value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param ui32Value is the timer prescale match value which must be between 0
+//! and 255 (inclusive) for 16/32-bit timers and between 0 and 65535
+//! (inclusive) for 32/64-bit timers.
+//!
+//! This function configures the value of the input clock prescaler match
+//! value. When in a half-width mode that uses the counter match and the
+//! prescaler, the prescale match effectively extends the range of the match.
+//! The prescaler provides the least significant bits when counting down in
+//! periodic and one-shot modes; in all other modes, the prescaler provides the
+//! most significant bits.
+//!
+//! \note The availability of the prescaler match varies with the Tiva
+//! part and timer mode in use. Please consult the datasheet for the part you
+//! are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer,
+ uint32_t ui32Value)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+ ASSERT(ui32Value < 256);
+
+ //
+ // Set the timer A prescale match if requested.
+ //
+ if(ui32Timer & TIMER_A)
+ {
+ HWREG(ui32Base + TIMER_O_TAPMR) = ui32Value;
+ }
+
+ //
+ // Set the timer B prescale match if requested.
+ //
+ if(ui32Timer & TIMER_B)
+ {
+ HWREG(ui32Base + TIMER_O_TBPMR) = ui32Value;
+ }
+}
+
+//*****************************************************************************
+//
+//! Get the timer prescale match value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.
+//!
+//! This function gets the value of the input clock prescaler match value.
+//! When in a half-width mode that uses the counter match and prescaler, the
+//! prescale match effectively extends the range of the match. The prescaler
+//! provides the least significant bits when counting down in periodic and
+//! one-shot modes; in all other modes, the prescaler provides the most
+//! significant bits.
+//!
+//! \note The availability of the prescaler match varies with the Tiva
+//! part and timer mode in use. Please consult the datasheet for the part you
+//! are using to determine whether this support is available.
+//!
+//! \return The value of the timer prescale match.
+//
+//*****************************************************************************
+uint32_t
+TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Return the appropriate prescale match value.
+ //
+ return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAPMR) :
+ HWREG(ui32Base + TIMER_O_TBPMR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer load value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used
+//! when the timer is configured for full-width operation.
+//! \param ui32Value is the load value.
+//!
+//! This function configures the timer load value; if the timer is running then
+//! the value is immediately loaded into the timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use
+//! TimerLoadSet64() for full-width modes of 32/64-bit timers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Set the timer A load value if requested.
+ //
+ if(ui32Timer & TIMER_A)
+ {
+ HWREG(ui32Base + TIMER_O_TAILR) = ui32Value;
+ }
+
+ //
+ // Set the timer B load value if requested.
+ //
+ if(ui32Timer & TIMER_B)
+ {
+ HWREG(ui32Base + TIMER_O_TBILR) = ui32Value;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer load value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for full-width operation.
+//!
+//! This function gets the currently programmed interval load value for the
+//! specified timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use
+//! TimerLoadGet64() for full-width modes of 32/64-bit timers.
+//!
+//! \return Returns the load value for the timer.
+//
+//*****************************************************************************
+uint32_t
+TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
+
+ //
+ // Return the appropriate load value.
+ //
+ return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAILR) :
+ HWREG(ui32Base + TIMER_O_TBILR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer load value for a 64-bit timer.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui64Value is the load value.
+//!
+//! This function configures the timer load value for a 64-bit timer; if the
+//! timer is running, then the value is immediately loaded into the timer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+
+ //
+ // Set the timer load value. The upper 32-bits must be written before the
+ // lower 32-bits in order to adhere to the hardware interlocks on the
+ // 64-bit value.
+ //
+ HWREG(ui32Base + TIMER_O_TBILR) = ui64Value >> 32;
+ HWREG(ui32Base + TIMER_O_TAILR) = ui64Value & 0xffffffff;
+}
+
+//*****************************************************************************
+//
+//! Gets the timer load value for a 64-bit timer.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function gets the currently programmed interval load value for the
+//! specified 64-bit timer.
+//!
+//! \return Returns the load value for the timer.
+//
+//*****************************************************************************
+uint64_t
+TimerLoadGet64(uint32_t ui32Base)
+{
+ uint32_t ui32High1, ui32High2, ui32Low;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+
+ //
+ // Read the 64-bit load value. A read of the low 32-bits is performed
+ // between two reads of the upper 32-bits; if the upper 32-bit values match
+ // then the 64-bit value is consistent. If they do not match, then the
+ // read is performed again until they do match (it should never execute the
+ // loop body more than twice).
+ //
+ do
+ {
+ ui32High1 = HWREG(ui32Base + TIMER_O_TBILR);
+ ui32Low = HWREG(ui32Base + TIMER_O_TAILR);
+ ui32High2 = HWREG(ui32Base + TIMER_O_TBILR);
+ }
+ while(ui32High1 != ui32High2);
+
+ //
+ // Return the load value.
+ //
+ return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low);
+}
+
+//*****************************************************************************
+//
+//! Gets the current timer value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for full-width operation.
+//!
+//! This function reads the current value of the specified timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use
+//! TimerValueGet64() for full-width modes of 32/64-bit timers.
+//!
+//! \return Returns the current value of the timer.
+//
+//*****************************************************************************
+uint32_t
+TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
+
+ //
+ // Return the appropriate timer value.
+ //
+ return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAR) :
+ HWREG(ui32Base + TIMER_O_TBR));
+}
+
+//*****************************************************************************
+//
+//! Gets the current 64-bit timer value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function reads the current value of the specified timer.
+//!
+//! \return Returns the current value of the timer.
+//
+//*****************************************************************************
+uint64_t
+TimerValueGet64(uint32_t ui32Base)
+{
+ uint32_t ui32High1, ui32High2, ui32Low;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+
+ //
+ // Read the 64-bit timer value. A read of the low 32-bits is performed
+ // between two reads of the upper 32-bits; if the upper 32-bit values match
+ // then the 64-bit value is consistent. If they do not match, then the
+ // read is performed again until they do match (it should never execute the
+ // loop body more than twice).
+ //
+ do
+ {
+ ui32High1 = HWREG(ui32Base + TIMER_O_TBR);
+ ui32Low = HWREG(ui32Base + TIMER_O_TAR);
+ ui32High2 = HWREG(ui32Base + TIMER_O_TBR);
+ }
+ while(ui32High1 != ui32High2);
+
+ //
+ // Return the timer value.
+ //
+ return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low);
+}
+
+//*****************************************************************************
+//
+//! Sets the timer match value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s) to adjust; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used
+//! when the timer is configured for full-width operation.
+//! \param ui32Value is the match value.
+//!
+//! This function configures the match value for a timer. This value is used
+//! in capture count mode to determine when to interrupt the processor and in
+//! PWM mode to determine the duty cycle of the output signal. On some
+//! Tiva devices, match interrupts can also be generated in periodic and
+//! one-shot modes.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use
+//! TimerMatchSet64() for full-width modes of 32/64-bit timers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer,
+ uint32_t ui32Value)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Set the timer A match value if requested.
+ //
+ if(ui32Timer & TIMER_A)
+ {
+ HWREG(ui32Base + TIMER_O_TAMATCHR) = ui32Value;
+ }
+
+ //
+ // Set the timer B match value if requested.
+ //
+ if(ui32Timer & TIMER_B)
+ {
+ HWREG(ui32Base + TIMER_O_TBMATCHR) = ui32Value;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer match value.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for full-width operation.
+//!
+//! This function gets the match value for the specified timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers and for half-width modes of 32/64-bit timers. Use
+//! TimerMatchGet64() for full-width modes of 32/64-bit timers.
+//!
+//! \return Returns the match value for the timer.
+//
+//*****************************************************************************
+uint32_t
+TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B));
+
+ //
+ // Return the appropriate match value.
+ //
+ return((ui32Timer == TIMER_A) ? HWREG(ui32Base + TIMER_O_TAMATCHR) :
+ HWREG(ui32Base + TIMER_O_TBMATCHR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer match value for a 64-bit timer.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui64Value is the match value.
+//!
+//! This function configures the match value for a timer. This value is used
+//! in capture count mode to determine when to interrupt the processor and in
+//! PWM mode to determine the duty cycle of the output signal.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+
+ //
+ // Set the timer match value. The upper 32-bits must be written before the
+ // lower 32-bits in order to adhere to the hardware interlocks on the
+ // 64-bit value.
+ //
+ HWREG(ui32Base + TIMER_O_TBMATCHR) = ui64Value >> 32;
+ HWREG(ui32Base + TIMER_O_TAMATCHR) = ui64Value & 0xffffffff;
+}
+
+//*****************************************************************************
+//
+//! Gets the timer match value for a 64-bit timer.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function gets the match value for the specified timer.
+//!
+//! \return Returns the match value for the timer.
+//
+//*****************************************************************************
+uint64_t
+TimerMatchGet64(uint32_t ui32Base)
+{
+ uint32_t ui32High1, ui32High2, ui32Low;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+
+ //
+ // Read the 64-bit match value. A read of the low 32-bits is performed
+ // between two reads of the upper 32-bits; if the upper 32-bit values match
+ // then the 64-bit value is consistent. If they do not match, then the
+ // read is performed again until they do match (it should never execute the
+ // loop body more than twice).
+ //
+ do
+ {
+ ui32High1 = HWREG(ui32Base + TIMER_O_TBMATCHR);
+ ui32Low = HWREG(ui32Base + TIMER_O_TAMATCHR);
+ ui32High2 = HWREG(ui32Base + TIMER_O_TBMATCHR);
+ }
+ while(ui32High1 != ui32High2);
+
+ //
+ // Return the match value.
+ //
+ return(((uint64_t)ui32High1 << 32) | (uint64_t)ui32Low);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the timer interrupt.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param pfnHandler is a pointer to the function to be called when the timer
+//! interrupt occurs.
+//!
+//! This function registers the handler to be called when a timer interrupt
+//! occurs. In addition, this function enables the global interrupt in the
+//! interrupt controller; specific timer interrupts must be enabled via
+//! TimerIntEnable(). It is the interrupt handler's responsibility to clear
+//! the interrupt source via TimerIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer,
+ void (*pfnHandler)(void))
+{
+ uint32_t ui32Int;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Get the interrupt number for this timer module.
+ //
+ ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer);
+
+ ASSERT(ui32Int != 0);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ui32Int, pfnHandler);
+
+ //
+ // Enable the interrupt.
+ //
+ IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the timer interrupt.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32Timer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function unregisters the handler to be called when a timer interrupt
+//! occurs. This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler is no longer called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer)
+{
+ uint32_t ui32Int;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+ ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) ||
+ (ui32Timer == TIMER_BOTH));
+
+ //
+ // Get the interrupt number for this timer module.
+ //
+ ui32Int = _TimerIntNumberGet(ui32Base, ui32Timer);
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ui32Int);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Enables individual timer interrupt sources.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated timer interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter must be the logical OR of any combination of
+//! the following:
+//!
+//! - \b TIMER_CAPB_EVENT - Capture B event interrupt
+//! - \b TIMER_CAPB_MATCH - Capture B match interrupt
+//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt
+//! - \b TIMER_RTC_MATCH - RTC interrupt mask
+//! - \b TIMER_CAPA_EVENT - Capture A event interrupt
+//! - \b TIMER_CAPA_MATCH - Capture A match interrupt
+//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ui32Base + TIMER_O_IMR) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual timer interrupt sources.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! This function disables the indicated timer interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to TimerIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ui32Base + TIMER_O_IMR) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the timer module. Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! values described in TimerIntEnable().
+//
+//*****************************************************************************
+uint32_t
+TimerIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ return(bMasked ? HWREG(ui32Base + TIMER_O_MIS) :
+ HWREG(ui32Base + TIMER_O_RIS));
+}
+
+//*****************************************************************************
+//
+//! Clears timer interrupt sources.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified timer interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being triggered again immediately upon exit.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to TimerIntEnable().
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_TimerBaseValid(ui32Base));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ui32Base + TIMER_O_ICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Synchronizes the counters in a set of timers.
+//!
+//! \param ui32Base is the base address of the timer module. This parameter
+//! must be the base address of Timer0 (in other words, \b TIMER0_BASE).
+//! \param ui32Timers is the set of timers to synchronize.
+//!
+//! This function synchronizes the counters in a specified set of timers.
+//! When a timer is running in half-width mode, each half can be included or
+//! excluded in the synchronization event. When a timer is running in
+//! full-width mode, only the A timer can be synchronized (specifying the B
+//! timer has no effect).
+//!
+//! The \e ui32Timers parameter is the logical OR of any of the following
+//! defines:
+//!
+//! - \b TIMER_0A_SYNC
+//! - \b TIMER_0B_SYNC
+//! - \b TIMER_1A_SYNC
+//! - \b TIMER_1B_SYNC
+//! - \b TIMER_2A_SYNC
+//! - \b TIMER_2B_SYNC
+//! - \b TIMER_3A_SYNC
+//! - \b TIMER_3B_SYNC
+//! - \b TIMER_4A_SYNC
+//! - \b TIMER_4B_SYNC
+//! - \b TIMER_5A_SYNC
+//! - \b TIMER_5B_SYNC
+//! - \b WTIMER_0A_SYNC
+//! - \b WTIMER_0B_SYNC
+//! - \b WTIMER_1A_SYNC
+//! - \b WTIMER_1B_SYNC
+//! - \b WTIMER_2A_SYNC
+//! - \b WTIMER_2B_SYNC
+//! - \b WTIMER_3A_SYNC
+//! - \b WTIMER_3B_SYNC
+//! - \b WTIMER_4A_SYNC
+//! - \b WTIMER_4B_SYNC
+//! - \b WTIMER_5A_SYNC
+//! - \b WTIMER_5B_SYNC
+//!
+//! \note This functionality is not available on all parts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == TIMER0_BASE);
+
+ //
+ // Synchronize the specified timers.
+ //
+ HWREG(ui32Base + TIMER_O_SYNC) = ui32Timers;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/timer.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/timer.h
new file mode 100644
index 00000000..52904eab
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/timer.h
@@ -0,0 +1,208 @@
+//*****************************************************************************
+//
+// timer.h - Prototypes for the timer module
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_TIMER_H__
+#define __DRIVERLIB_TIMER_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerConfigure as the ui32Config parameter.
+//
+//*****************************************************************************
+#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
+#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count
+ // timer
+#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
+#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count
+ // timer
+#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer
+#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
+#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
+#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
+#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
+#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
+#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
+#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
+#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
+#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
+#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
+#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
+#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
+#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and
+// TimerIntClear as the ui32IntFlags parameter, and returned from
+// TimerIntStatus.
+//
+//*****************************************************************************
+#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
+#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerControlEvent as the ui32Event parameter.
+//
+//*****************************************************************************
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
+
+//*****************************************************************************
+//
+// Values that can be passed to most of the timer APIs as the ui32Timer
+// parameter.
+//
+//*****************************************************************************
+#define TIMER_A 0x000000ff // Timer A
+#define TIMER_B 0x0000ff00 // Timer B
+#define TIMER_BOTH 0x0000ffff // Timer Both
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerSynchronize as the ui32Timers parameter.
+//
+//*****************************************************************************
+#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A
+#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B
+#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A
+#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B
+#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A
+#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B
+#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A
+#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B
+#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A
+#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B
+#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A
+#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B
+#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A
+#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B
+#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A
+#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B
+#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A
+#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B
+#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A
+#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B
+#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A
+#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B
+#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A
+#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void TimerEnable(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerDisable(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config);
+extern void TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer,
+ bool bInvert);
+extern void TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer,
+ bool bEnable);
+extern void TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer,
+ uint32_t ui32Event);
+extern void TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer,
+ bool bStall);
+extern void TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer,
+ bool bWait);
+extern void TimerRTCEnable(uint32_t ui32Base);
+extern void TimerRTCDisable(uint32_t ui32Base);
+extern void TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer,
+ uint32_t ui32Value);
+extern uint32_t TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer,
+ uint32_t ui32Value);
+extern uint32_t TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer,
+ uint32_t ui32Value);
+extern uint32_t TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value);
+extern uint64_t TimerLoadGet64(uint32_t ui32Base);
+extern uint32_t TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer);
+extern uint64_t TimerValueGet64(uint32_t ui32Base);
+extern void TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer,
+ uint32_t ui32Value);
+extern uint32_t TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value);
+extern uint64_t TimerMatchGet64(uint32_t ui32Base);
+extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer,
+ void (*pfnHandler)(void));
+extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer);
+extern void TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t TimerIntStatus(uint32_t ui32Base, bool bMasked);
+extern void TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_TIMER_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/uart.c b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/uart.c
new file mode 100644
index 00000000..0f2d80b1
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/uart.c
@@ -0,0 +1,1938 @@
+//*****************************************************************************
+//
+// uart.c - Driver for the UART.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup uart_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "inc/hw_uart.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/uart.h"
+
+//*****************************************************************************
+//
+// The system clock divider defining the maximum baud rate supported by the
+// UART.
+//
+//*****************************************************************************
+#define UART_CLK_DIVIDER 8
+
+//*****************************************************************************
+//
+// A mapping of UART base address to interrupt number.
+//
+//*****************************************************************************
+static const uint32_t g_ppui32UARTIntMap[][2] =
+{
+ { UART0_BASE, INT_UART0_BLIZZARD },
+ { UART1_BASE, INT_UART1_BLIZZARD },
+ { UART2_BASE, INT_UART2_BLIZZARD },
+ { UART3_BASE, INT_UART3_BLIZZARD },
+ { UART4_BASE, INT_UART4_BLIZZARD },
+ { UART5_BASE, INT_UART5_BLIZZARD },
+ { UART6_BASE, INT_UART6_BLIZZARD },
+ { UART7_BASE, INT_UART7_BLIZZARD },
+};
+static const uint_fast8_t g_ui8UARTIntMapRows =
+ sizeof(g_ppui32UARTIntMap) / sizeof(g_ppui32UARTIntMap[0]);
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a UART base address.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function determines if a UART port base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_UARTBaseValid(uint32_t ui32Base)
+{
+ return((ui32Base == UART0_BASE) || (ui32Base == UART1_BASE) ||
+ (ui32Base == UART2_BASE) || (ui32Base == UART3_BASE) ||
+ (ui32Base == UART4_BASE) || (ui32Base == UART5_BASE) ||
+ (ui32Base == UART6_BASE) || (ui32Base == UART7_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Gets the UART interrupt number.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! Given a UART base address, this function returns the corresponding
+//! interrupt number.
+//!
+//! \return Returns a UART interrupt number, or 0 if \e ui32Base is invalid.
+//
+//*****************************************************************************
+static uint32_t
+_UARTIntNumberGet(uint32_t ui32Base)
+{
+ uint_fast8_t ui8Idx, ui8Rows;
+ const uint32_t (*ppui32UARTIntMap)[2];
+
+ //
+ // Default interrupt map.
+ //
+ ppui32UARTIntMap = g_ppui32UARTIntMap;
+ ui8Rows = g_ui8UARTIntMapRows;
+
+ //
+ // Loop through the table that maps UART base addresses to interrupt
+ // numbers.
+ //
+ for(ui8Idx = 0; ui8Idx < ui8Rows; ui8Idx++)
+ {
+ //
+ // See if this base address matches.
+ //
+ if(ppui32UARTIntMap[ui8Idx][0] == ui32Base)
+ {
+ //
+ // Return the corresponding interrupt number.
+ //
+ return(ppui32UARTIntMap[ui8Idx][1]);
+ }
+ }
+
+ //
+ // The base address could not be found, so return an error.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Sets the type of parity.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Parity specifies the type of parity to use.
+//!
+//! This function configures the type of parity to use for transmitting and
+//! expect when receiving. The \e ui32Parity parameter must be one of
+//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
+//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two
+//! parameters allow direct control of the parity bit; it is always either one
+//! or zero based on the mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+ ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) ||
+ (ui32Parity == UART_CONFIG_PAR_EVEN) ||
+ (ui32Parity == UART_CONFIG_PAR_ODD) ||
+ (ui32Parity == UART_CONFIG_PAR_ONE) ||
+ (ui32Parity == UART_CONFIG_PAR_ZERO));
+
+ //
+ // Set the parity mode.
+ //
+ HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) &
+ ~(UART_LCRH_SPS | UART_LCRH_EPS |
+ UART_LCRH_PEN)) | ui32Parity);
+}
+
+//*****************************************************************************
+//
+//! Gets the type of parity currently being used.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function gets the type of parity used for transmitting data and
+//! expected when receiving data.
+//!
+//! \return Returns the current parity settings, specified as one of
+//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
+//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
+//
+//*****************************************************************************
+uint32_t
+UARTParityModeGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Return the current parity setting.
+ //
+ return(HWREG(ui32Base + UART_O_LCRH) &
+ (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO level at which interrupts are generated.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one
+//! of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8,
+//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
+//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of
+//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
+//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
+//!
+//! This function configures the FIFO level at which transmit and receive
+//! interrupts are generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel,
+ uint32_t ui32RxLevel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+ ASSERT((ui32TxLevel == UART_FIFO_TX1_8) ||
+ (ui32TxLevel == UART_FIFO_TX2_8) ||
+ (ui32TxLevel == UART_FIFO_TX4_8) ||
+ (ui32TxLevel == UART_FIFO_TX6_8) ||
+ (ui32TxLevel == UART_FIFO_TX7_8));
+ ASSERT((ui32RxLevel == UART_FIFO_RX1_8) ||
+ (ui32RxLevel == UART_FIFO_RX2_8) ||
+ (ui32RxLevel == UART_FIFO_RX4_8) ||
+ (ui32RxLevel == UART_FIFO_RX6_8) ||
+ (ui32RxLevel == UART_FIFO_RX7_8));
+
+ //
+ // Set the FIFO interrupt levels.
+ //
+ HWREG(ui32Base + UART_O_IFLS) = ui32TxLevel | ui32RxLevel;
+}
+
+//*****************************************************************************
+//
+//! Gets the FIFO level at which interrupts are generated.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level,
+//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
+//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
+//! \param pui32RxLevel is a pointer to storage for the receive FIFO level,
+//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
+//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
+//!
+//! This function gets the FIFO level at which transmit and receive interrupts
+//! are generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel,
+ uint32_t *pui32RxLevel)
+{
+ uint32_t ui32Temp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Read the FIFO level register.
+ //
+ ui32Temp = HWREG(ui32Base + UART_O_IFLS);
+
+ //
+ // Extract the transmit and receive FIFO levels.
+ //
+ *pui32TxLevel = ui32Temp & UART_IFLS_TX_M;
+ *pui32RxLevel = ui32Temp & UART_IFLS_RX_M;
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration of a UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32UARTClk is the rate of the clock supplied to the UART module.
+//! \param ui32Baud is the desired baud rate.
+//! \param ui32Config is the data format for the port (number of data bits,
+//! number of stop bits, and parity).
+//!
+//! This function configures the UART for operation in the specified data
+//! format. The baud rate is provided in the \e ui32Baud parameter and the
+//! data format in the \e ui32Config parameter.
+//!
+//! The \e ui32Config parameter is the logical OR of three values: the number
+//! of data bits, the number of stop bits, and the parity.
+//! \b UART_CONFIG_WLEN_8, \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and
+//! \b UART_CONFIG_WLEN_5 select from eight to five data bits per byte
+//! (respectively). \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select
+//! one or two stop bits (respectively). \b UART_CONFIG_PAR_NONE,
+//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
+//! and \b UART_CONFIG_PAR_ZERO select the parity mode (no parity bit, even
+//! parity bit, odd parity bit, parity bit always one, and parity bit always
+//! zero, respectively).
+//!
+//! The peripheral clock is the same as the processor clock. The frequency of
+//! the system clock is the value returned by SysCtlClockGet(), or it can be
+//! explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet()).
+//!
+//! For Tiva parts that have the ability to specify the UART baud clock
+//! source (via UARTClockSourceSet()), the peripheral clock can be changed to
+//! PIOSC. In this case, the peripheral clock should be specified as
+//! 16,000,000 (the nominal rate of PIOSC).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
+ uint32_t ui32Baud, uint32_t ui32Config)
+{
+ uint32_t ui32Div;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+ ASSERT(ui32Baud != 0);
+ ASSERT(ui32UARTClk >= (ui32Baud * UART_CLK_DIVIDER));
+
+ //
+ // Stop the UART.
+ //
+ UARTDisable(ui32Base);
+
+ //
+ // Is the required baud rate greater than the maximum rate supported
+ // without the use of high speed mode?
+ //
+ if((ui32Baud * 16) > ui32UARTClk)
+ {
+ //
+ // Enable high speed mode.
+ //
+ HWREG(ui32Base + UART_O_CTL) |= UART_CTL_HSE;
+
+ //
+ // Half the supplied baud rate to compensate for enabling high speed
+ // mode. This allows the following code to be common to both cases.
+ //
+ ui32Baud /= 2;
+ }
+ else
+ {
+ //
+ // Disable high speed mode.
+ //
+ HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_HSE);
+ }
+
+ //
+ // Compute the fractional baud rate divider.
+ //
+ ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2;
+
+ //
+ // Set the baud rate.
+ //
+ HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64;
+ HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64;
+
+ //
+ // Set parity, data length, and number of stop bits.
+ //
+ HWREG(ui32Base + UART_O_LCRH) = ui32Config;
+
+ //
+ // Clear the flags register.
+ //
+ HWREG(ui32Base + UART_O_FR) = 0;
+
+ //
+ // Start the UART.
+ //
+ UARTEnable(ui32Base);
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration of a UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32UARTClk is the rate of the clock supplied to the UART module.
+//! \param pui32Baud is a pointer to storage for the baud rate.
+//! \param pui32Config is a pointer to storage for the data format.
+//!
+//! This function determines the baud rate and data format for the UART, given
+//! an explicitly provided peripheral clock (hence the ExpClk suffix). The
+//! returned baud rate is the actual baud rate; it may not be the exact baud
+//! rate requested or an ``official'' baud rate. The data format returned in
+//! \e pui32Config is enumerated the same as the \e ui32Config parameter of
+//! UARTConfigSetExpClk().
+//!
+//! The peripheral clock is the same as the processor clock. The frequency of
+//! the system clock is the value returned by SysCtlClockGet(), or it can be
+//! explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet()).
+//!
+//! For Tiva parts that have the ability to specify the UART baud clock
+//! source (via UARTClockSourceSet()), the peripheral clock can be changed to
+//! PIOSC. In this case, the peripheral clock should be specified as
+//! 16,000,000 (the nominal rate of PIOSC).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
+ uint32_t *pui32Baud, uint32_t *pui32Config)
+{
+ uint32_t ui32Int, ui32Frac;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Compute the baud rate.
+ //
+ ui32Int = HWREG(ui32Base + UART_O_IBRD);
+ ui32Frac = HWREG(ui32Base + UART_O_FBRD);
+ *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac);
+
+ //
+ // See if high speed mode enabled.
+ //
+ if(HWREG(ui32Base + UART_O_CTL) & UART_CTL_HSE)
+ {
+ //
+ // High speed mode is enabled so the actual baud rate is actually
+ // double what was just calculated.
+ //
+ *pui32Baud *= 2;
+ }
+
+ //
+ // Get the parity, data length, and number of stop bits.
+ //
+ *pui32Config = (HWREG(ui32Base + UART_O_LCRH) &
+ (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 |
+ UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! Enables transmitting and receiving.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function enables the UART and its transmit and receive FIFOs.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Enable the FIFO.
+ //
+ HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN;
+
+ //
+ // Enable RX, TX, and the UART.
+ //
+ HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
+ UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! Disables transmitting and receiving.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function disables the UART, waits for the end of transmission of the
+//! current character, and flushes the transmit FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Wait for end of TX.
+ //
+ while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY)
+ {
+ }
+
+ //
+ // Disable the FIFO.
+ //
+ HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+
+ //
+ // Disable the UART.
+ //
+ HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
+ UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! Enables the transmit and receive FIFOs.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This functions enables the transmit and receive FIFOs in the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Enable the FIFO.
+ //
+ HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the transmit and receive FIFOs.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function disables the transmit and receive FIFOs in the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFODisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Disable the FIFO.
+ //
+ HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+}
+
+//*****************************************************************************
+//
+//! Enables SIR (IrDA) mode on the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param bLowPower indicates if SIR Low Power Mode is to be used.
+//!
+//! This function enables SIR (IrDA) mode on the UART. If the \e bLowPower
+//! flag is set, then SIR low power mode will be selected as well. This
+//! function only has an effect if the UART has not been enabled by a call to
+//! UARTEnable(). The call UARTEnableSIR() must be made before a call to
+//! UARTConfigSetExpClk() because the UARTConfigSetExpClk() function calls the
+//! UARTEnable() function. Another option is to call UARTDisable() followed by
+//! UARTEnableSIR() and then enable the UART by calling UARTEnable().
+//!
+//! \note The availability of SIR (IrDA) operation varies with the Tiva
+//! part in use. Please consult the datasheet for the part you are using to
+//! determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTEnableSIR(uint32_t ui32Base, bool bLowPower)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Enable SIR and SIRLP (if appropriate).
+ //
+ if(bLowPower)
+ {
+ HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP);
+ }
+ else
+ {
+ HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_SIREN);
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables SIR (IrDA) mode on the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function disables SIR(IrDA) mode on the UART. This function only has
+//! an effect if the UART has not been enabled by a call to UARTEnable(). The
+//! call UARTEnableSIR() must be made before a call to UARTConfigSetExpClk()
+//! because the UARTConfigSetExpClk() function calls the UARTEnable() function.
+//! Another option is to call UARTDisable() followed by UARTEnableSIR() and
+//! then enable the UART by calling UARTEnable().
+//!
+//! \note The availability of SIR (IrDA) operation varies with the Tiva
+//! part in use. Please consult the datasheet for the part you are using to
+//! determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDisableSIR(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Disable SIR and SIRLP (if appropriate).
+ //
+ HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP);
+}
+
+//*****************************************************************************
+//
+//! Enables ISO7816 smart card mode on the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function enables the SMART control bit for the ISO7816 smart card mode
+//! on the UART. This call also sets 8-bit word length and even parity as
+//! required by ISO7816.
+//!
+//! \note The availability of ISO7816 smart card mode varies with the Tiva
+//! part and UART in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTSmartCardEnable(uint32_t ui32Base)
+{
+ uint32_t ui32Val;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Set 8-bit word length, even parity, 2 stop bits (note that although the
+ // STP2 bit is ignored when in smartcard mode, this code lets the caller
+ // read back the actual setting in use).
+ //
+ ui32Val = HWREG(ui32Base + UART_O_LCRH);
+ ui32Val &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN |
+ UART_LCRH_WLEN_M);
+ ui32Val |= UART_LCRH_WLEN_8 | UART_LCRH_PEN | UART_LCRH_EPS |
+ UART_LCRH_STP2;
+ HWREG(ui32Base + UART_O_LCRH) = ui32Val;
+
+ //
+ // Enable SMART mode.
+ //
+ HWREG(ui32Base + UART_O_CTL) |= UART_CTL_SMART;
+}
+
+//*****************************************************************************
+//
+//! Disables ISO7816 smart card mode on the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function clears the SMART (ISO7816 smart card) bit in the UART
+//! control register.
+//!
+//! \note The availability of ISO7816 smart card mode varies with the Tiva
+//! part and UART in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTSmartCardDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Disable the SMART bit.
+ //
+ HWREG(ui32Base + UART_O_CTL) &= ~UART_CTL_SMART;
+}
+
+//*****************************************************************************
+//
+//! Sets the states of the DTR and/or RTS modem control signals.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Control is a bit-mapped flag indicating which modem control bits
+//! should be set.
+//!
+//! This function configures the states of the DTR or RTS modem handshake
+//! outputs from the UART.
+//!
+//! The \e ui32Control parameter is the logical OR of any of the following:
+//!
+//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
+//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Tiva part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control)
+{
+ uint32_t ui32Temp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == UART1_BASE);
+ ASSERT((ui32Control & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
+
+ //
+ // Set the appropriate modem control output bits.
+ //
+ ui32Temp = HWREG(ui32Base + UART_O_CTL);
+ ui32Temp |= (ui32Control & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+ HWREG(ui32Base + UART_O_CTL) = ui32Temp;
+}
+
+//*****************************************************************************
+//
+//! Clears the states of the DTR and/or RTS modem control signals.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Control is a bit-mapped flag indicating which modem control bits
+//! should be set.
+//!
+//! This function clears the states of the DTR or RTS modem handshake outputs
+//! from the UART.
+//!
+//! The \e ui32Control parameter is the logical OR of any of the following:
+//!
+//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
+//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Tiva part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control)
+{
+ uint32_t ui32Temp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == UART1_BASE);
+ ASSERT((ui32Control & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
+
+ //
+ // Set the appropriate modem control output bits.
+ //
+ ui32Temp = HWREG(ui32Base + UART_O_CTL);
+ ui32Temp &= ~(ui32Control & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+ HWREG(ui32Base + UART_O_CTL) = ui32Temp;
+}
+
+//*****************************************************************************
+//
+//! Gets the states of the DTR and RTS modem control signals.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns the current states of each of the two UART modem
+//! control signals, DTR and RTS.
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Tiva part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return Returns the states of the handshake output signals. This value is
+//! a logical OR combination of values \b UART_OUTPUT_RTS and
+//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the
+//! associated signal is asserted.
+//
+//*****************************************************************************
+uint32_t
+UARTModemControlGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == UART1_BASE);
+
+ return(HWREG(ui32Base + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+}
+
+//*****************************************************************************
+//
+//! Gets the states of the RI, DCD, DSR and CTS modem status signals.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns the current states of each of the four UART modem
+//! status signals, RI, DCD, DSR and CTS.
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Tiva part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return Returns the states of the handshake output signals. This value
+//! is a logical OR combination of values \b UART_INPUT_RI,
+//! \b UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
+//! presence of each flag indicates that the associated signal is asserted.
+//
+//*****************************************************************************
+uint32_t
+UARTModemStatusGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == UART1_BASE);
+
+ return(HWREG(ui32Base + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD |
+ UART_INPUT_CTS | UART_INPUT_DSR));
+}
+
+//*****************************************************************************
+//
+//! Sets the UART hardware flow control mode to be used.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Mode indicates the flow control modes to be used. This
+//! parameter is a logical OR combination of values \b UART_FLOWCONTROL_TX and
+//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
+//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control.
+//!
+//! This function configures the required hardware flow control modes. If
+//! \e ui32Mode contains flag \b UART_FLOWCONTROL_TX, data is only transmitted
+//! if the incoming CTS signal is asserted. If \e ui32Mode contains flag
+//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is
+//! asserted only when there is space available in the receive FIFO. If no
+//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be
+//! passed.
+//!
+//! \note The availability of hardware flow control varies with the Tiva
+//! part and UART in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+ ASSERT((ui32Mode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0);
+
+ //
+ // Set the flow control mode as requested.
+ //
+ HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) &
+ ~(UART_FLOWCONTROL_TX |
+ UART_FLOWCONTROL_RX)) | ui32Mode);
+}
+
+//*****************************************************************************
+//
+//! Returns the UART hardware flow control mode currently in use.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns the current hardware flow control mode.
+//!
+//! \note The availability of hardware flow control varies with the Tiva
+//! part and UART in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns the current flow control mode in use. This value is a
+//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit
+//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS)
+//! flow control is in use. If hardware flow control is disabled,
+//! \b UART_FLOWCONTROL_NONE is returned.
+//
+//*****************************************************************************
+uint32_t
+UARTFlowControlGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ return(HWREG(ui32Base + UART_O_CTL) & (UART_FLOWCONTROL_TX |
+ UART_FLOWCONTROL_RX));
+}
+
+//*****************************************************************************
+//
+//! Sets the operating mode for the UART transmit interrupt.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Mode is the operating mode for the transmit interrupt. It may
+//! be \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is
+//! idle or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit
+//! FIFO level.
+//!
+//! This function allows the mode of the UART transmit interrupt to be set. By
+//! default, the transmit interrupt is asserted when the FIFO level falls past
+//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this
+//! function is called with \e ui32Mode set to \b UART_TXINT_MODE_EOT, the
+//! transmit interrupt is asserted once the transmitter is completely idle -
+//! the transmit FIFO is empty and all bits, including any stop bits, have
+//! cleared the transmitter.
+//!
+//! \note The availability of end-of-transmission mode varies with the
+//! Tiva part in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+ ASSERT((ui32Mode == UART_TXINT_MODE_EOT) ||
+ (ui32Mode == UART_TXINT_MODE_FIFO));
+
+ //
+ // Set or clear the EOT bit of the UART control register as appropriate.
+ //
+ HWREG(ui32Base + UART_O_CTL) = ((HWREG(ui32Base + UART_O_CTL) &
+ ~(UART_TXINT_MODE_EOT |
+ UART_TXINT_MODE_FIFO)) | ui32Mode);
+}
+
+//*****************************************************************************
+//
+//! Returns the current operating mode for the UART transmit interrupt.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns the current operating mode for the UART transmit
+//! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit
+//! interrupt is currently configured to be asserted once the transmitter is
+//! completely idle - the transmit FIFO is empty and all bits, including any
+//! stop bits, have cleared the transmitter. The return value is
+//! \b UART_TXINT_MODE_FIFO if the interrupt is configured to be asserted based
+//! on the level of the transmit FIFO.
+//!
+//! \note The availability of end-of-transmission mode varies with the
+//! Tiva part in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT.
+//
+//*****************************************************************************
+uint32_t
+UARTTxIntModeGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Return the current transmit interrupt mode.
+ //
+ return(HWREG(ui32Base + UART_O_CTL) & (UART_TXINT_MODE_EOT |
+ UART_TXINT_MODE_FIFO));
+}
+
+//*****************************************************************************
+//
+//! Determines if there are any characters in the receive FIFO.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns a flag indicating whether or not there is data
+//! available in the receive FIFO.
+//!
+//! \return Returns \b true if there is data in the receive FIFO or \b false
+//! if there is no data in the receive FIFO.
+//
+//*****************************************************************************
+bool
+UARTCharsAvail(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Return the availability of characters.
+ //
+ return((HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! Determines if there is any space in the transmit FIFO.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns a flag indicating whether or not there is space
+//! available in the transmit FIFO.
+//!
+//! \return Returns \b true if there is space available in the transmit FIFO
+//! or \b false if there is no space available in the transmit FIFO.
+//
+//*****************************************************************************
+bool
+UARTSpaceAvail(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Return the availability of space.
+ //
+ return((HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! Receives a character from the specified port.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function gets a character from the receive FIFO for the specified
+//! port.
+//!
+//! \return Returns the character read from the specified port, cast as a
+//! \e int32_t. A \b -1 is returned if there are no characters present in the
+//! receive FIFO. The UARTCharsAvail() function should be called before
+//! attempting to call this function.
+//
+//*****************************************************************************
+int32_t
+UARTCharGetNonBlocking(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // See if there are any characters in the receive FIFO.
+ //
+ if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE))
+ {
+ //
+ // Read and return the next character.
+ //
+ return(HWREG(ui32Base + UART_O_DR));
+ }
+ else
+ {
+ //
+ // There are no characters, so return a failure.
+ //
+ return(-1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Waits for a character from the specified port.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function gets a character from the receive FIFO for the specified
+//! port. If there are no characters available, this function waits until a
+//! character is received before returning.
+//!
+//! \return Returns the character read from the specified port, cast as a
+//! \e int32_t.
+//
+//*****************************************************************************
+int32_t
+UARTCharGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Wait until a char is available.
+ //
+ while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)
+ {
+ }
+
+ //
+ // Now get the char.
+ //
+ return(HWREG(ui32Base + UART_O_DR));
+}
+
+//*****************************************************************************
+//
+//! Sends a character to the specified port.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ucData is the character to be transmitted.
+//!
+//! This function writes the character \e ucData to the transmit FIFO for the
+//! specified port. This function does not block, so if there is no space
+//! available, then a \b false is returned and the application must retry the
+//! function later.
+//!
+//! \return Returns \b true if the character was successfully placed in the
+//! transmit FIFO or \b false if there was no space available in the transmit
+//! FIFO.
+//
+//*****************************************************************************
+bool
+UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // See if there is space in the transmit FIFO.
+ //
+ if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF))
+ {
+ //
+ // Write this character to the transmit FIFO.
+ //
+ HWREG(ui32Base + UART_O_DR) = ucData;
+
+ //
+ // Success.
+ //
+ return(true);
+ }
+ else
+ {
+ //
+ // There is no space in the transmit FIFO, so return a failure.
+ //
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Waits to send a character from the specified port.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ucData is the character to be transmitted.
+//!
+//! This function sends the character \e ucData to the transmit FIFO for the
+//! specified port. If there is no space available in the transmit FIFO, this
+//! function waits until there is space available before returning.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTCharPut(uint32_t ui32Base, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Wait until space is available.
+ //
+ while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)
+ {
+ }
+
+ //
+ // Send the char.
+ //
+ HWREG(ui32Base + UART_O_DR) = ucData;
+}
+
+//*****************************************************************************
+//
+//! Causes a BREAK to be sent.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param bBreakState controls the output level.
+//!
+//! Calling this function with \e bBreakState set to \b true asserts a break
+//! condition on the UART. Calling this function with \e bBreakState set to
+//! \b false removes the break condition. For proper transmission of a break
+//! command, the break must be asserted for at least two complete frames.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTBreakCtl(uint32_t ui32Base, bool bBreakState)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Set the break condition as requested.
+ //
+ HWREG(ui32Base + UART_O_LCRH) =
+ (bBreakState ?
+ (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) :
+ (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK)));
+}
+
+//*****************************************************************************
+//
+//! Determines whether the UART transmitter is busy or not.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function allows the caller to determine whether all transmitted bytes
+//! have cleared the transmitter hardware. If \b false is returned, the
+//! transmit FIFO is empty and all bits of the last transmitted character,
+//! including all stop bits, have left the hardware shift register.
+//!
+//! \return Returns \b true if the UART is transmitting or \b false if all
+//! transmissions are complete.
+//
+//*****************************************************************************
+bool
+UARTBusy(uint32_t ui32Base)
+{
+ //
+ // Check the argument.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Determine if the UART is busy.
+ //
+ return((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a UART interrupt.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! UART interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! function enables the global interrupt in the interrupt controller; specific
+//! UART interrupts must be enabled via UARTIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+ uint32_t ui32Int;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Determine the interrupt number based on the UART port.
+ //
+ ui32Int = _UARTIntNumberGet(ui32Base);
+
+ ASSERT(ui32Int != 0);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ui32Int, pfnHandler);
+
+ //
+ // Enable the UART interrupt.
+ //
+ IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for a UART interrupt.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when a UART interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntUnregister(uint32_t ui32Base)
+{
+ uint32_t ui32Int;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Determine the interrupt number based on the UART port.
+ //
+ ui32Int = _UARTIntNumberGet(ui32Base);
+
+ ASSERT(ui32Int != 0);
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ui32Int);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Enables individual UART interrupt sources.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated UART interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b UART_INT_9BIT - 9-bit Address Match interrupt
+//! - \b UART_INT_OE - Overrun Error interrupt
+//! - \b UART_INT_BE - Break Error interrupt
+//! - \b UART_INT_PE - Parity Error interrupt
+//! - \b UART_INT_FE - Framing Error interrupt
+//! - \b UART_INT_RT - Receive Timeout interrupt
+//! - \b UART_INT_TX - Transmit interrupt
+//! - \b UART_INT_RX - Receive interrupt
+//! - \b UART_INT_DSR - DSR interrupt
+//! - \b UART_INT_DCD - DCD interrupt
+//! - \b UART_INT_CTS - CTS interrupt
+//! - \b UART_INT_RI - RI interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ui32Base + UART_O_IM) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual UART interrupt sources.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! This function disables the indicated UART interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to UARTIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ui32Base + UART_O_IM) &= ~(ui32IntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the specified UART. Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in UARTIntEnable().
+//
+//*****************************************************************************
+uint32_t
+UARTIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ui32Base + UART_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ui32Base + UART_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears UART interrupt sources.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified UART interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being triggered again immediately upon exit.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to UARTIntEnable().
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ui32Base + UART_O_ICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Enable UART DMA operation.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32DMAFlags is a bit mask of the DMA features to enable.
+//!
+//! The specified UART DMA features are enabled. The UART can be
+//! configured to use DMA for transmit or receive and to disable
+//! receive if an error occurs. The \e ui32DMAFlags parameter is the
+//! logical OR of any of the following values:
+//!
+//! - UART_DMA_RX - enable DMA for receive
+//! - UART_DMA_TX - enable DMA for transmit
+//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Set the requested bits in the UART DMA control register.
+ //
+ HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Disable UART DMA operation.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32DMAFlags is a bit mask of the DMA features to disable.
+//!
+//! This function is used to disable UART DMA features that were enabled
+//! by UARTDMAEnable(). The specified UART DMA features are disabled. The
+//! \e ui32DMAFlags parameter is the logical OR of any of the following values:
+//!
+//! - UART_DMA_RX - disable DMA for receive
+//! - UART_DMA_TX - disable DMA for transmit
+//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Clear the requested bits in the UART DMA control register.
+ //
+ HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets current receiver errors.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns the current state of each of the 4 receiver error
+//! sources. The returned errors are equivalent to the four error bits
+//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
+//! with the exception that the overrun error is set immediately when the
+//! overrun occurs rather than when a character is next read.
+//!
+//! \return Returns a logical OR combination of the receiver error flags,
+//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
+//! and \b UART_RXERROR_OVERRUN.
+//
+//*****************************************************************************
+uint32_t
+UARTRxErrorGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Return the current value of the receive status register.
+ //
+ return(HWREG(ui32Base + UART_O_RSR) & 0x0000000F);
+}
+
+//*****************************************************************************
+//
+//! Clears all reported receiver errors.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function is used to clear all receiver error conditions reported via
+//! UARTRxErrorGet(). If using the overrun, framing error, parity error or
+//! break interrupts, this function must be called after clearing the interrupt
+//! to ensure that later errors of the same type trigger another interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTRxErrorClear(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Any write to the Error Clear Register clears all bits which are
+ // currently set.
+ //
+ HWREG(ui32Base + UART_O_ECR) = 0;
+}
+
+//*****************************************************************************
+//
+//! Sets the baud clock source for the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui32Source is the baud clock source for the UART.
+//!
+//! This function allows the baud clock source for the UART to be selected.
+//! The possible clock source are the system clock (\b UART_CLOCK_SYSTEM) or
+//! the precision internal oscillator (\b UART_CLOCK_PIOSC).
+//!
+//! Changing the baud clock source changes the baud rate generated by the
+//! UART. Therefore, the baud rate should be reconfigured after any change to
+//! the baud clock source.
+//!
+//! \note The ability to specify the UART baud clock source varies with the
+//! Tiva part in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+ ASSERT((ui32Source == UART_CLOCK_SYSTEM) ||
+ (ui32Source == UART_CLOCK_PIOSC));
+
+ //
+ // Set the UART clock source.
+ //
+ HWREG(ui32Base + UART_O_CC) = ui32Source;
+}
+
+//*****************************************************************************
+//
+//! Gets the baud clock source for the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function returns the baud clock source for the specified UART. The
+//! possible baud clock source are the system clock (\b UART_CLOCK_SYSTEM) or
+//! the precision internal oscillator (\b UART_CLOCK_PIOSC).
+//!
+//! \note The ability to specify the UART baud clock source varies with the
+//! Tiva part in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+uint32_t
+UARTClockSourceGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Return the UART clock source.
+ //
+ return(HWREG(ui32Base + UART_O_CC));
+}
+
+//*****************************************************************************
+//
+//! Enables 9-bit mode on the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function enables the 9-bit operational mode of the UART.
+//!
+//! \note The availability of 9-bit mode varies with the Tiva part in use.
+//! Please consult the datasheet for the part you are using to determine
+//! whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UART9BitEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Enable 9-bit mode.
+ //
+ HWREG(ui32Base + UART_O_9BITADDR) |= UART_9BITADDR_9BITEN;
+}
+
+//*****************************************************************************
+//
+//! Disables 9-bit mode on the specified UART.
+//!
+//! \param ui32Base is the base address of the UART port.
+//!
+//! This function disables the 9-bit operational mode of the UART.
+//!
+//! \note The availability of 9-bit mode varies with the Tiva part in use.
+//! Please consult the datasheet for the part you are using to determine
+//! whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UART9BitDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Disable 9-bit mode.
+ //
+ HWREG(ui32Base + UART_O_9BITADDR) &= ~UART_9BITADDR_9BITEN;
+}
+
+//*****************************************************************************
+//
+//! Sets the device address(es) for 9-bit mode.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui8Addr is the device address.
+//! \param ui8Mask is the device address mask.
+//!
+//! This function configures the device address or range of device addresses
+//! that respond to requests on the 9-bit UART port. The received address is
+//! masked with the mask and then compared against the given address, allowing
+//! either a single address (if \b ui8Mask is 0xff) or a set of addresses to be
+//! matched.
+//!
+//! \note The availability of 9-bit mode varies with the Tiva part in use.
+//! Please consult the datasheet for the part you are using to determine
+//! whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr,
+ uint8_t ui8Mask)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Set the address and mask.
+ //
+ HWREG(ui32Base + UART_O_9BITADDR) = ui8Addr << UART_9BITADDR_ADDR_S;
+ HWREG(ui32Base + UART_O_9BITAMASK) = ui8Mask << UART_9BITAMASK_MASK_S;
+}
+
+//*****************************************************************************
+//
+//! Sends an address character from the specified port when operating in 9-bit
+//! mode.
+//!
+//! \param ui32Base is the base address of the UART port.
+//! \param ui8Addr is the address to be transmitted.
+//!
+//! This function waits until all data has been sent from the specified port
+//! and then sends the given address as an address byte. It then waits until
+//! the address byte has been transmitted before returning.
+//!
+//! The normal data functions (UARTCharPut(), UARTCharPutNonBlocking(),
+//! UARTCharGet(), and UARTCharGetNonBlocking()) are used to send and receive
+//! data characters in 9-bit mode.
+//!
+//! \note The availability of 9-bit mode varies with the Tiva part in use.
+//! Please consult the datasheet for the part you are using to determine
+//! whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr)
+{
+ uint32_t ui32LCRH;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_UARTBaseValid(ui32Base));
+
+ //
+ // Wait until the FIFO is empty and the UART is not busy.
+ //
+ while((HWREG(ui32Base + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) !=
+ UART_FR_TXFE)
+ {
+ }
+
+ //
+ // Force the address/data bit to 1 to indicate this is an address byte.
+ //
+ ui32LCRH = HWREG(ui32Base + UART_O_LCRH);
+ HWREG(ui32Base + UART_O_LCRH) = ((ui32LCRH & ~UART_LCRH_EPS) |
+ UART_LCRH_SPS | UART_LCRH_PEN);
+
+ //
+ // Send the address.
+ //
+ HWREG(ui32Base + UART_O_DR) = ui8Addr;
+
+ //
+ // Wait until the address has been sent.
+ //
+ while((HWREG(ui32Base + UART_O_FR) & (UART_FR_TXFE | UART_FR_BUSY)) !=
+ UART_FR_TXFE)
+ {
+ }
+
+ //
+ // Restore the address/data setting.
+ //
+ HWREG(ui32Base + UART_O_LCRH) = ui32LCRH;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/uart.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/uart.h
new file mode 100644
index 00000000..323774b1
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/uart.h
@@ -0,0 +1,253 @@
+//*****************************************************************************
+//
+// uart.h - Defines and Macros for the UART.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_UART_H__
+#define __DRIVERLIB_UART_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
+// as the ui32IntFlags parameter, and returned from UARTIntStatus.
+//
+//*****************************************************************************
+#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask
+#define UART_INT_RX 0x010 // Receive Interrupt Mask
+#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask
+#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask
+#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
+#define UART_INT_RI 0x001 // RI Modem Interrupt Mask
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter
+// and returned by UARTConfigGetExpClk in the pui32Config parameter.
+// Additionally, the UART_CONFIG_PAR_* subset can be passed to
+// UARTParityModeSet as the ui32Parity parameter, and are returned by
+// UARTParityModeGet.
+//
+//*****************************************************************************
+#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
+#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
+#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
+#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
+#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter
+// and returned by UARTFIFOLevelGet in the pui32TxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
+#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
+#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
+#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
+#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter
+// and returned by UARTFIFOLevelGet in the pui32RxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
+#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
+#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
+#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
+#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
+//
+//*****************************************************************************
+#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
+#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
+#define UART_DMA_RX 0x00000001 // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Values returned from UARTRxErrorGet().
+//
+//*****************************************************************************
+#define UART_RXERROR_OVERRUN 0x00000008
+#define UART_RXERROR_BREAK 0x00000004
+#define UART_RXERROR_PARITY 0x00000002
+#define UART_RXERROR_FRAMING 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTHandshakeOutputsSet() or returned from
+// UARTHandshakeOutputGet().
+//
+//*****************************************************************************
+#define UART_OUTPUT_RTS 0x00000800
+#define UART_OUTPUT_DTR 0x00000400
+
+//*****************************************************************************
+//
+// Values that can be returned from UARTHandshakeInputsGet().
+//
+//*****************************************************************************
+#define UART_INPUT_RI 0x00000100
+#define UART_INPUT_DCD 0x00000004
+#define UART_INPUT_DSR 0x00000002
+#define UART_INPUT_CTS 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFlowControl() or returned from
+// UARTFlowControlGet().
+//
+//*****************************************************************************
+#define UART_FLOWCONTROL_TX 0x00008000
+#define UART_FLOWCONTROL_RX 0x00004000
+#define UART_FLOWCONTROL_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTTxIntModeSet() or returned from
+// UARTTxIntModeGet().
+//
+//*****************************************************************************
+#define UART_TXINT_MODE_FIFO 0x00000000
+#define UART_TXINT_MODE_EOT 0x00000010
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTClockSourceSet() or returned from
+// UARTClockSourceGet().
+//
+//*****************************************************************************
+#define UART_CLOCK_SYSTEM 0x00000000
+#define UART_CLOCK_PIOSC 0x00000005
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity);
+extern uint32_t UARTParityModeGet(uint32_t ui32Base);
+extern void UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel,
+ uint32_t ui32RxLevel);
+extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel,
+ uint32_t *pui32RxLevel);
+extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
+ uint32_t ui32Baud, uint32_t ui32Config);
+extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk,
+ uint32_t *pui32Baud, uint32_t *pui32Config);
+extern void UARTEnable(uint32_t ui32Base);
+extern void UARTDisable(uint32_t ui32Base);
+extern void UARTFIFOEnable(uint32_t ui32Base);
+extern void UARTFIFODisable(uint32_t ui32Base);
+extern void UARTEnableSIR(uint32_t ui32Base, bool bLowPower);
+extern void UARTDisableSIR(uint32_t ui32Base);
+extern bool UARTCharsAvail(uint32_t ui32Base);
+extern bool UARTSpaceAvail(uint32_t ui32Base);
+extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base);
+extern int32_t UARTCharGet(uint32_t ui32Base);
+extern bool UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData);
+extern void UARTCharPut(uint32_t ui32Base, unsigned char ucData);
+extern void UARTBreakCtl(uint32_t ui32Base, bool bBreakState);
+extern bool UARTBusy(uint32_t ui32Base);
+extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern void UARTIntUnregister(uint32_t ui32Base);
+extern void UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t UARTIntStatus(uint32_t ui32Base, bool bMasked);
+extern void UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags);
+extern void UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags);
+extern uint32_t UARTRxErrorGet(uint32_t ui32Base);
+extern void UARTRxErrorClear(uint32_t ui32Base);
+extern void UARTSmartCardEnable(uint32_t ui32Base);
+extern void UARTSmartCardDisable(uint32_t ui32Base);
+extern void UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control);
+extern void UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control);
+extern uint32_t UARTModemControlGet(uint32_t ui32Base);
+extern uint32_t UARTModemStatusGet(uint32_t ui32Base);
+extern void UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode);
+extern uint32_t UARTFlowControlGet(uint32_t ui32Base);
+extern void UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode);
+extern uint32_t UARTTxIntModeGet(uint32_t ui32Base);
+extern void UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source);
+extern uint32_t UARTClockSourceGet(uint32_t ui32Base);
+extern void UART9BitEnable(uint32_t ui32Base);
+extern void UART9BitDisable(uint32_t ui32Base);
+extern void UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr,
+ uint8_t ui8Mask);
+extern void UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_UART_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/udma.c b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/udma.c
new file mode 100644
index 00000000..9bd2e021
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/udma.c
@@ -0,0 +1,1375 @@
+//*****************************************************************************
+//
+// udma.c - Driver for the micro-DMA controller.
+//
+// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup udma_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "inc/hw_udma.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/udma.h"
+
+//*****************************************************************************
+//
+//! Enables the uDMA controller for use.
+//!
+//! This function enables the uDMA controller. The uDMA controller must be
+//! enabled before it can be configured and used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAEnable(void)
+{
+ //
+ // Set the master enable bit in the config register.
+ //
+ HWREG(UDMA_CFG) = UDMA_CFG_MASTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the uDMA controller for use.
+//!
+//! This function disables the uDMA controller. Once disabled, the uDMA
+//! controller cannot operate until re-enabled with uDMAEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMADisable(void)
+{
+ //
+ // Clear the master enable bit in the config register.
+ //
+ HWREG(UDMA_CFG) = 0;
+}
+
+//*****************************************************************************
+//
+//! Gets the uDMA error status.
+//!
+//! This function returns the uDMA error status. It should be called from
+//! within the uDMA error interrupt handler to determine if a uDMA error
+//! occurred.
+//!
+//! \return Returns non-zero if a uDMA error is pending.
+//
+//*****************************************************************************
+uint32_t
+uDMAErrorStatusGet(void)
+{
+ //
+ // Return the uDMA error status.
+ //
+ return(HWREG(UDMA_ERRCLR));
+}
+
+//*****************************************************************************
+//
+//! Clears the uDMA error interrupt.
+//!
+//! This function clears a pending uDMA error interrupt. This function should
+//! be called from within the uDMA error interrupt handler to clear the
+//! interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAErrorStatusClear(void)
+{
+ //
+ // Clear the uDMA error interrupt.
+ //
+ HWREG(UDMA_ERRCLR) = 1;
+}
+
+//*****************************************************************************
+//
+//! Enables a uDMA channel for operation.
+//!
+//! \param ui32ChannelNum is the channel number to enable.
+//!
+//! This function enables a specific uDMA channel for use. This function must
+//! be used to enable a channel before it can be used to perform a uDMA
+//! transfer.
+//!
+//! When a uDMA transfer is completed, the channel is automatically disabled by
+//! the uDMA controller. Therefore, this function should be called prior to
+//! starting up any new transfer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelEnable(uint32_t ui32ChannelNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32ChannelNum & 0xffff) < 32);
+
+ //
+ // Set the bit for this channel in the enable set register.
+ //
+ HWREG(UDMA_ENASET) = 1 << (ui32ChannelNum & 0x1f);
+}
+
+//*****************************************************************************
+//
+//! Disables a uDMA channel for operation.
+//!
+//! \param ui32ChannelNum is the channel number to disable.
+//!
+//! This function disables a specific uDMA channel. Once disabled, a channel
+//! cannot respond to uDMA transfer requests until re-enabled via
+//! uDMAChannelEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelDisable(uint32_t ui32ChannelNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32ChannelNum & 0xffff) < 32);
+
+ //
+ // Set the bit for this channel in the enable clear register.
+ //
+ HWREG(UDMA_ENACLR) = 1 << (ui32ChannelNum & 0x1f);
+}
+
+//*****************************************************************************
+//
+//! Checks if a uDMA channel is enabled for operation.
+//!
+//! \param ui32ChannelNum is the channel number to check.
+//!
+//! This function checks to see if a specific uDMA channel is enabled. This
+//! function can be used to check the status of a transfer, as the channel is
+//! automatically disabled at the end of a transfer.
+//!
+//! \return Returns \b true if the channel is enabled, \b false if disabled.
+//
+//*****************************************************************************
+bool
+uDMAChannelIsEnabled(uint32_t ui32ChannelNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32ChannelNum & 0xffff) < 32);
+
+ //
+ // AND the specified channel bit with the enable register and return the
+ // result.
+ //
+ return((HWREG(UDMA_ENASET) & (1 << (ui32ChannelNum & 0x1f))) ? true :
+ false);
+}
+
+//*****************************************************************************
+//
+//! Sets the base address for the channel control table.
+//!
+//! \param psControlTable is a pointer to the 1024-byte-aligned base address
+//! of the uDMA channel control table.
+//!
+//! This function configures the base address of the channel control table.
+//! This table resides in system memory and holds control information for each
+//! uDMA channel. The table must be aligned on a 1024-byte boundary. The base
+//! address must be configured before any of the channel functions can be used.
+//!
+//! The size of the channel control table depends on the number of uDMA
+//! channels and the transfer modes that are used. Refer to the introductory
+//! text and the microcontroller datasheet for more information about the
+//! channel control table.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAControlBaseSet(void *psControlTable)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(((uint32_t)psControlTable & ~0x3FF) ==
+ (uint32_t)psControlTable);
+ ASSERT((uint32_t)psControlTable >= 0x20000000);
+
+ //
+ // Program the base address into the register.
+ //
+ HWREG(UDMA_CTLBASE) = (uint32_t)psControlTable;
+}
+
+//*****************************************************************************
+//
+//! Gets the base address for the channel control table.
+//!
+//! This function gets the base address of the channel control table. This
+//! table resides in system memory and holds control information for each uDMA
+//! channel.
+//!
+//! \return Returns a pointer to the base address of the channel control table.
+//
+//*****************************************************************************
+void *
+uDMAControlBaseGet(void)
+{
+ //
+ // Read the current value of the control base register and return it to
+ // the caller.
+ //
+ return((void *)HWREG(UDMA_CTLBASE));
+}
+
+//*****************************************************************************
+//
+//! Gets the base address for the channel control table alternate structures.
+//!
+//! This function gets the base address of the second half of the channel
+//! control table that holds the alternate control structures for each channel.
+//!
+//! \return Returns a pointer to the base address of the second half of the
+//! channel control table.
+//
+//*****************************************************************************
+void *
+uDMAControlAlternateBaseGet(void)
+{
+ //
+ // Read the current value of the control base register and return it to
+ // the caller.
+ //
+ return((void *)HWREG(UDMA_ALTBASE));
+}
+
+//*****************************************************************************
+//
+//! Requests a uDMA channel to start a transfer.
+//!
+//! \param ui32ChannelNum is the channel number on which to request a uDMA
+//! transfer.
+//!
+//! This function allows software to request a uDMA channel to begin a
+//! transfer. This function could be used for performing a memory-to-memory
+//! transfer, or if for some reason a transfer needs to be initiated by
+//! software instead of the peripheral associated with that channel.
+//!
+//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then
+//! the completion is signaled on the uDMA dedicated interrupt. If a
+//! peripheral channel is used, then the completion is signaled on the
+//! peripheral's interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelRequest(uint32_t ui32ChannelNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32ChannelNum & 0xffff) < 32);
+
+ //
+ // Set the bit for this channel in the software uDMA request register.
+ //
+ HWREG(UDMA_SWREQ) = 1 << (ui32ChannelNum & 0x1f);
+}
+
+//*****************************************************************************
+//
+//! Enables attributes of a uDMA channel.
+//!
+//! \param ui32ChannelNum is the channel to configure.
+//! \param ui32Attr is a combination of attributes for the channel.
+//!
+//! This function is used to enable attributes of a uDMA channel.
+//!
+//! The \e ui32Attr parameter is the logical OR of any of the following:
+//!
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst
+//! mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//! for this channel (it is very unlikely that this flag should be used).
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//! peripheral for this channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelAttributeEnable(uint32_t ui32ChannelNum, uint32_t ui32Attr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32ChannelNum & 0xffff) < 32);
+ ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
+ UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0);
+
+ //
+ // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+ // passed as the ui32ChannelNum parameter, extract just the channel number
+ // from this parameter.
+ //
+ ui32ChannelNum &= 0x1f;
+
+ //
+ // Set the useburst bit for this channel if set in ui32Config.
+ //
+ if(ui32Attr & UDMA_ATTR_USEBURST)
+ {
+ HWREG(UDMA_USEBURSTSET) = 1 << ui32ChannelNum;
+ }
+
+ //
+ // Set the alternate control select bit for this channel,
+ // if set in ui32Config.
+ //
+ if(ui32Attr & UDMA_ATTR_ALTSELECT)
+ {
+ HWREG(UDMA_ALTSET) = 1 << ui32ChannelNum;
+ }
+
+ //
+ // Set the high priority bit for this channel, if set in ui32Config.
+ //
+ if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY)
+ {
+ HWREG(UDMA_PRIOSET) = 1 << ui32ChannelNum;
+ }
+
+ //
+ // Set the request mask bit for this channel, if set in ui32Config.
+ //
+ if(ui32Attr & UDMA_ATTR_REQMASK)
+ {
+ HWREG(UDMA_REQMASKSET) = 1 << ui32ChannelNum;
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables attributes of a uDMA channel.
+//!
+//! \param ui32ChannelNum is the channel to configure.
+//! \param ui32Attr is a combination of attributes for the channel.
+//!
+//! This function is used to disable attributes of a uDMA channel.
+//!
+//! The \e ui32Attr parameter is the logical OR of any of the following:
+//!
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst
+//! mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//! for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//! peripheral for this channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelAttributeDisable(uint32_t ui32ChannelNum, uint32_t ui32Attr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32ChannelNum & 0xffff) < 32);
+ ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
+ UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0);
+
+ //
+ // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+ // passed as the ui32ChannelNum parameter, extract just the channel number
+ // from this parameter.
+ //
+ ui32ChannelNum &= 0x1f;
+
+ //
+ // Clear the useburst bit for this channel if set in ui32Config.
+ //
+ if(ui32Attr & UDMA_ATTR_USEBURST)
+ {
+ HWREG(UDMA_USEBURSTCLR) = 1 << ui32ChannelNum;
+ }
+
+ //
+ // Clear the alternate control select bit for this channel, if set in
+ // ui32Config.
+ //
+ if(ui32Attr & UDMA_ATTR_ALTSELECT)
+ {
+ HWREG(UDMA_ALTCLR) = 1 << ui32ChannelNum;
+ }
+
+ //
+ // Clear the high priority bit for this channel, if set in ui32Config.
+ //
+ if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY)
+ {
+ HWREG(UDMA_PRIOCLR) = 1 << ui32ChannelNum;
+ }
+
+ //
+ // Clear the request mask bit for this channel, if set in ui32Config.
+ //
+ if(ui32Attr & UDMA_ATTR_REQMASK)
+ {
+ HWREG(UDMA_REQMASKCLR) = 1 << ui32ChannelNum;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the enabled attributes of a uDMA channel.
+//!
+//! \param ui32ChannelNum is the channel to configure.
+//!
+//! This function returns a combination of flags representing the attributes of
+//! the uDMA channel.
+//!
+//! \return Returns the logical OR of the attributes of the uDMA channel, which
+//! can be any of the following:
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst
+//! mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//! for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//! peripheral for this channel.
+//
+//*****************************************************************************
+uint32_t
+uDMAChannelAttributeGet(uint32_t ui32ChannelNum)
+{
+ uint32_t ui32Attr = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32ChannelNum & 0xffff) < 32);
+
+ //
+ // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+ // passed as the ui32ChannelNum parameter, extract just the channel number
+ // from this parameter.
+ //
+ ui32ChannelNum &= 0x1f;
+
+ //
+ // Check to see if useburst bit is set for this channel.
+ //
+ if(HWREG(UDMA_USEBURSTSET) & (1 << ui32ChannelNum))
+ {
+ ui32Attr |= UDMA_ATTR_USEBURST;
+ }
+
+ //
+ // Check to see if the alternate control bit is set for this channel.
+ //
+ if(HWREG(UDMA_ALTSET) & (1 << ui32ChannelNum))
+ {
+ ui32Attr |= UDMA_ATTR_ALTSELECT;
+ }
+
+ //
+ // Check to see if the high priority bit is set for this channel.
+ //
+ if(HWREG(UDMA_PRIOSET) & (1 << ui32ChannelNum))
+ {
+ ui32Attr |= UDMA_ATTR_HIGH_PRIORITY;
+ }
+
+ //
+ // Check to see if the request mask bit is set for this channel.
+ //
+ if(HWREG(UDMA_REQMASKSET) & (1 << ui32ChannelNum))
+ {
+ ui32Attr |= UDMA_ATTR_REQMASK;
+ }
+
+ //
+ // Return the configuration flags.
+ //
+ return(ui32Attr);
+}
+
+//*****************************************************************************
+//
+//! Sets the control parameters for a uDMA channel control structure.
+//!
+//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number
+//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//! \param ui32Control is logical OR of several control values to set the
+//! control parameters for the channel.
+//!
+//! This function is used to set control parameters for a uDMA transfer. These
+//! parameters are typically not changed often.
+//!
+//! The \e ui32ChannelStructIndex parameter should be the logical OR of the
+//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to
+//! choose whether the primary or alternate data structure is used.
+//!
+//! The \e ui32Control parameter is the logical OR of five values: the data
+//! size, the source address increment, the destination address increment, the
+//! arbitration size, and the use burst flag. The choices available for each
+//! of these values is described below.
+//!
+//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or
+//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits.
+//!
+//! Choose the source address increment from one of \b UDMA_SRC_INC_8,
+//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select
+//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or
+//! to select non-incrementing.
+//!
+//! Choose the destination address increment from one of \b UDMA_DST_INC_8,
+//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select
+//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or
+//! to select non-incrementing.
+//!
+//! The arbitration size determines how many items are transferred before
+//! the uDMA controller re-arbitrates for the bus. Choose the arbitration size
+//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8,
+//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024
+//! items, in powers of 2.
+//!
+//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only
+//! respond to burst requests at the tail end of a scatter-gather transfer.
+//!
+//! \note The address increment cannot be smaller than the data size.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelControlSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Control)
+{
+ tDMAControlTable *psCtl;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32ChannelStructIndex & 0xffff) < 64);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+ //
+ // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+ // passed as the ui32ChannelStructIndex parameter, extract just the channel
+ // index from this parameter.
+ //
+ ui32ChannelStructIndex &= 0x3f;
+
+ //
+ // Get the base address of the control table.
+ //
+ psCtl = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get the current control word value and mask off the fields to be
+ // changed, then OR in the new settings.
+ //
+ psCtl[ui32ChannelStructIndex].ui32Control =
+ ((psCtl[ui32ChannelStructIndex].ui32Control &
+ ~(UDMA_CHCTL_DSTINC_M |
+ UDMA_CHCTL_DSTSIZE_M |
+ UDMA_CHCTL_SRCINC_M |
+ UDMA_CHCTL_SRCSIZE_M |
+ UDMA_CHCTL_ARBSIZE_M |
+ UDMA_CHCTL_NXTUSEBURST)) |
+ ui32Control);
+}
+
+//*****************************************************************************
+//
+//! Sets the transfer parameters for a uDMA channel control structure.
+//!
+//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//! \param ui32Mode is the type of uDMA transfer.
+//! \param pvSrcAddr is the source address for the transfer.
+//! \param pvDstAddr is the destination address for the transfer.
+//! \param ui32TransferSize is the number of data items to transfer.
+//!
+//! This function is used to configure the parameters for a uDMA transfer.
+//! These parameters are typically changed often. The function
+//! uDMAChannelControlSet() MUST be called at least once for this channel prior
+//! to calling this function.
+//!
+//! The \e ui32ChannelStructIndex parameter should be the logical OR of the
+//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to
+//! choose whether the primary or alternate data structure is used.
+//!
+//! The \e ui32Mode parameter should be one of the following values:
+//!
+//! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode
+//! to this value at the end of a transfer.
+//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request.
+//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once
+//! started even if the request is removed.
+//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the
+//! primary and alternate control structures for the channel. This mode
+//! allows use of ping-pong buffering for uDMA transfers.
+//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather
+//! transfer.
+//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather
+//! transfer.
+//!
+//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first
+//! location of the data to be transferred. These addresses should be aligned
+//! according to the item size. The compiler takes care of this alignment if
+//! the pointers are pointing to storage of the appropriate data type.
+//!
+//! The \e ui32TransferSize parameter is the number of data items, not the
+//! number of bytes.
+//!
+//! The two scatter-gather modes, memory and peripheral, are actually different
+//! depending on whether the primary or alternate control structure is
+//! selected. This function looks for the \b UDMA_PRI_SELECT and
+//! \b UDMA_ALT_SELECT flag along with the channel number and sets the
+//! scatter-gather mode as appropriate for the primary or alternate control
+//! structure.
+//!
+//! The channel must also be enabled using uDMAChannelEnable() after calling
+//! this function. The transfer does not begin until the channel has been
+//! configured and enabled. Note that the channel is automatically disabled
+//! after the transfer is completed, meaning that uDMAChannelEnable() must be
+//! called again after setting up the next transfer.
+//!
+//! \note Great care must be taken to not modify a channel control structure
+//! that is in use or else the results are unpredictable, including the
+//! possibility of undesired data transfers to or from memory or peripherals.
+//! For BASIC and AUTO modes, it is safe to make changes when the channel is
+//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For
+//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the
+//! primary or alternate control structure only when the other is being used.
+//! The uDMAChannelModeGet() function returns \b UDMA_MODE_STOP when a
+//! channel control structure is inactive and safe to modify.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex, uint32_t ui32Mode,
+ void *pvSrcAddr, void *pvDstAddr,
+ uint32_t ui32TransferSize)
+{
+ tDMAControlTable *psControlTable;
+ uint32_t ui32Control;
+ uint32_t ui32Inc;
+ uint32_t ui32BufferBytes;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32ChannelStructIndex & 0xffff) < 64);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+ ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER);
+ ASSERT((uint32_t)pvSrcAddr >= 0x20000000);
+ ASSERT((uint32_t)pvDstAddr >= 0x20000000);
+ ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= 1024));
+
+ //
+ // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+ // passed as the ui32ChannelStructIndex parameter, extract just the channel
+ // index from this parameter.
+ //
+ ui32ChannelStructIndex &= 0x3f;
+
+ //
+ // Get the base address of the control table.
+ //
+ psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get the current control word value and mask off the mode and size
+ // fields.
+ //
+ ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control &
+ ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+ //
+ // Adjust the mode if the alt control structure is selected.
+ //
+ if(ui32ChannelStructIndex & UDMA_ALT_SELECT)
+ {
+ if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) ||
+ (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER))
+ {
+ ui32Mode |= UDMA_MODE_ALT_SELECT;
+ }
+ }
+
+ //
+ // Set the transfer size and mode in the control word (but don't write the
+ // control word yet as it could kick off a transfer).
+ //
+ ui32Control |= ui32Mode | ((ui32TransferSize - 1) << 4);
+
+ //
+ // Get the address increment value for the source, from the control word.
+ //
+ ui32Inc = (ui32Control & UDMA_CHCTL_SRCINC_M);
+
+ //
+ // Compute the ending source address of the transfer. If the source
+ // increment is set to none, then the ending address is the same as the
+ // beginning.
+ //
+ if(ui32Inc != UDMA_SRC_INC_NONE)
+ {
+ ui32Inc = ui32Inc >> 26;
+ ui32BufferBytes = ui32TransferSize << ui32Inc;
+ pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - 1);
+ }
+
+ //
+ // Load the source ending address into the control block.
+ //
+ psControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr;
+
+ //
+ // Get the address increment value for the destination, from the control
+ // word.
+ //
+ ui32Inc = ui32Control & UDMA_CHCTL_DSTINC_M;
+
+ //
+ // Compute the ending destination address of the transfer. If the
+ // destination increment is set to none, then the ending address is the
+ // same as the beginning.
+ //
+ if(ui32Inc != UDMA_DST_INC_NONE)
+ {
+ //
+ // There is a special case if this is setting up a scatter-gather
+ // transfer. The destination pointer must point to the end of
+ // the alternate structure for this channel instead of calculating
+ // the end of the buffer in the normal way.
+ //
+ if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) ||
+ (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER))
+ {
+ pvDstAddr =
+ (void *)&psControlTable[ui32ChannelStructIndex |
+ UDMA_ALT_SELECT].ui32Spare;
+ }
+ //
+ // Not a scatter-gather transfer, calculate end pointer normally.
+ //
+ else
+ {
+ ui32Inc = ui32Inc >> 30;
+ ui32BufferBytes = ui32TransferSize << ui32Inc;
+ pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1);
+ }
+ }
+
+ //
+ // Load the destination ending address into the control block.
+ //
+ psControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr;
+
+ //
+ // Write the new control word value.
+ //
+ psControlTable[ui32ChannelStructIndex].ui32Control = ui32Control;
+}
+
+//*****************************************************************************
+//
+//! Configures a uDMA channel for scatter-gather mode.
+//!
+//! \param ui32ChannelNum is the uDMA channel number.
+//! \param ui32TaskCount is the number of scatter-gather tasks to execute.
+//! \param pvTaskList is a pointer to the beginning of the scatter-gather
+//! task list.
+//! \param ui32IsPeriphSG is a flag to indicate it is a peripheral
+//! scatter-gather transfer (else it is memory scatter-gather transfer)
+//!
+//! This function is used to configure a channel for scatter-gather mode.
+//! The caller must have already set up a task list and must pass a pointer to
+//! the start of the task list as the \e pvTaskList parameter. The
+//! \e ui32TaskCount parameter is the count of tasks in the task list, not the
+//! size of the task list. The flag \e bIsPeriphSG should be used to indicate
+//! if scatter-gather should be configured for peripheral or memory
+//! operation.
+//!
+//! \sa uDMATaskStructEntry
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum, uint32_t ui32TaskCount,
+ void *pvTaskList, uint32_t ui32IsPeriphSG)
+{
+ tDMAControlTable *psControlTable;
+ tDMAControlTable *psTaskTable;
+
+ //
+ // Check the parameters
+ //
+ ASSERT((ui32ChannelNum & 0xffff) < 32);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+ ASSERT(pvTaskList != 0);
+ ASSERT(ui32TaskCount <= 1024);
+ ASSERT(ui32TaskCount != 0);
+
+ //
+ // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+ // passed as the ui32ChannelNum parameter, extract just the channel number
+ // from this parameter.
+ //
+ ui32ChannelNum &= 0x1f;
+
+ //
+ // Get the base address of the control table.
+ //
+ psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get a handy pointer to the task list
+ //
+ psTaskTable = (tDMAControlTable *)pvTaskList;
+
+ //
+ // Compute the ending address for the source pointer. This address is the
+ // last element of the last task in the task table
+ //
+ psControlTable[ui32ChannelNum].pvSrcEndAddr =
+ &psTaskTable[ui32TaskCount - 1].ui32Spare;
+
+ //
+ // Compute the ending address for the destination pointer. This address
+ // is the end of the alternate structure for this channel.
+ //
+ psControlTable[ui32ChannelNum].pvDstEndAddr =
+ &psControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare;
+
+ //
+ // Compute the control word. Most configurable items are fixed for
+ // scatter-gather. Item and increment sizes are all 32-bit and arb
+ // size must be 4. The count is the number of items in the task list
+ // times 4 (4 words per task).
+ //
+ psControlTable[ui32ChannelNum].ui32Control =
+ (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 |
+ UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 |
+ UDMA_CHCTL_ARBSIZE_4 |
+ (((ui32TaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) |
+ (ui32IsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG :
+ UDMA_CHCTL_XFERMODE_MEM_SG));
+
+ //
+ // Scatter-gather operations can leave the alt bit set. So if doing
+ // back to back scatter-gather transfers, the second attempt may not
+ // work correctly because the alt bit is set. Therefore, clear the
+ // alt bit here to ensure that it is always cleared before a new SG
+ // transfer is started.
+ //
+ HWREG(UDMA_ALTCLR) = 1 << ui32ChannelNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the current transfer size for a uDMA channel control structure.
+//!
+//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//!
+//! This function is used to get the uDMA transfer size for a channel. The
+//! transfer size is the number of items to transfer, where the size of an item
+//! might be 8, 16, or 32 bits. If a partial transfer has already occurred,
+//! then the number of remaining items is returned. If the transfer is
+//! complete, then 0 is returned.
+//!
+//! \return Returns the number of items remaining to transfer.
+//
+//*****************************************************************************
+uint32_t
+uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex)
+{
+ tDMAControlTable *psControlTable;
+ uint32_t ui32Control;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32ChannelStructIndex & 0xffff) < 64);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+ //
+ // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+ // passed as the ui32ChannelStructIndex parameter, extract just the channel
+ // index from this parameter.
+ //
+ ui32ChannelStructIndex &= 0x3f;
+
+ //
+ // Get the base address of the control table.
+ //
+ psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get the current control word value and mask off all but the size field
+ // and the mode field.
+ //
+ ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control &
+ (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+ //
+ // If the size field and mode field are 0 then the transfer is finished
+ // and there are no more items to transfer
+ //
+ if(ui32Control == 0)
+ {
+ return(0);
+ }
+
+ //
+ // Otherwise, if either the size field or more field is non-zero, then
+ // not all the items have been transferred.
+ //
+ else
+ {
+ //
+ // Shift the size field and add one, then return to user.
+ //
+ return((ui32Control >> 4) + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the transfer mode for a uDMA channel control structure.
+//!
+//! \param ui32ChannelStructIndex is the logical OR of the uDMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//!
+//! This function is used to get the transfer mode for the uDMA channel and
+//! to query the status of a transfer on a channel. When the transfer is
+//! complete the mode is \b UDMA_MODE_STOP.
+//!
+//! \return Returns the transfer mode of the specified channel and control
+//! structure, which is one of the following values: \b UDMA_MODE_STOP,
+//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG,
+//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER.
+//
+//*****************************************************************************
+uint32_t
+uDMAChannelModeGet(uint32_t ui32ChannelStructIndex)
+{
+ tDMAControlTable *psControlTable;
+ uint32_t ui32Control;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32ChannelStructIndex & 0xffff) < 64);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+ //
+ // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was
+ // passed as the ui32ChannelStructIndex parameter, extract just the channel
+ // index from this parameter.
+ //
+ ui32ChannelStructIndex &= 0x3f;
+
+ //
+ // Get the base address of the control table.
+ //
+ psControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get the current control word value and mask off all but the mode field.
+ //
+ ui32Control = (psControlTable[ui32ChannelStructIndex].ui32Control &
+ UDMA_CHCTL_XFERMODE_M);
+
+ //
+ // Check if scatter/gather mode, and if so, mask off the alt bit.
+ //
+ if(((ui32Control & ~UDMA_MODE_ALT_SELECT) ==
+ UDMA_MODE_MEM_SCATTER_GATHER) ||
+ ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER))
+ {
+ ui32Control &= ~UDMA_MODE_ALT_SELECT;
+ }
+
+ //
+ // Return the mode to the caller.
+ //
+ return(ui32Control);
+}
+
+//*****************************************************************************
+//
+//! Selects the secondary peripheral for a set of uDMA channels.
+//!
+//! \param ui32SecPeriphs is the logical OR of the uDMA channels for which to
+//! use the secondary peripheral, instead of the default peripheral.
+//!
+//! This function is used to select the secondary peripheral assignment for a
+//! set of uDMA channels. By selecting the secondary peripheral assignment for
+//! a channel, the default peripheral assignment is no longer available for
+//! that channel.
+//!
+//! The parameter \e ui32SecPeriphs can be the logical OR of any of the
+//! following macros. If one of the macros below is in the list passed to this
+//! function, then the secondary peripheral (marked as \b _SEC_) is selected.
+//!
+//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX
+//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX
+//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A
+//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B
+//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A
+//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B
+//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A
+//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B
+//! - \b UDMA_DEF_UART0RX_SEC_UART1RX
+//! - \b UDMA_DEF_UART0TX_SEC_UART1TX
+//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX
+//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2RX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2TX
+//! - \b UDMA_DEF_ADC00_SEC_TMR2A
+//! - \b UDMA_DEF_ADC01_SEC_TMR2B
+//! - \b UDMA_DEF_ADC02_SEC_RESERVED
+//! - \b UDMA_DEF_ADC03_SEC_RESERVED
+//! - \b UDMA_DEF_TMR0A_SEC_TMR1A
+//! - \b UDMA_DEF_TMR0B_SEC_TMR1B
+//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX
+//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX
+//! - \b UDMA_DEF_UART1RX_SEC_RESERVED
+//! - \b UDMA_DEF_UART1TX_SEC_RESERVED
+//! - \b UDMA_DEF_SSI1RX_SEC_ADC10
+//! - \b UDMA_DEF_SSI1TX_SEC_ADC11
+//! - \b UDMA_DEF_RESERVED_SEC_ADC12
+//! - \b UDMA_DEF_RESERVED_SEC_ADC13
+//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED
+//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs)
+{
+ //
+ // Select the secondary peripheral for the specified channels.
+ //
+ HWREG(UDMA_CHASGN) |= ui32SecPeriphs;
+}
+
+//*****************************************************************************
+//
+//! Selects the default peripheral for a set of uDMA channels.
+//!
+//! \param ui32DefPeriphs is the logical OR of the uDMA channels for which to
+//! use the default peripheral, instead of the secondary peripheral.
+//!
+//! This function is used to select the default peripheral assignment for a set
+//! of uDMA channels.
+//!
+//! The parameter \e ui32DefPeriphs can be the logical OR of any of the
+//! following macros. If one of the macros below is in the list passed to this
+//! function, then the default peripheral (marked as \b _DEF_) is selected.
+//!
+//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX
+//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX
+//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A
+//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B
+//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A
+//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B
+//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A
+//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B
+//! - \b UDMA_DEF_UART0RX_SEC_UART1RX
+//! - \b UDMA_DEF_UART0TX_SEC_UART1TX
+//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX
+//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2RX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2TX
+//! - \b UDMA_DEF_ADC00_SEC_TMR2A
+//! - \b UDMA_DEF_ADC01_SEC_TMR2B
+//! - \b UDMA_DEF_ADC02_SEC_RESERVED
+//! - \b UDMA_DEF_ADC03_SEC_RESERVED
+//! - \b UDMA_DEF_TMR0A_SEC_TMR1A
+//! - \b UDMA_DEF_TMR0B_SEC_TMR1B
+//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX
+//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX
+//! - \b UDMA_DEF_UART1RX_SEC_RESERVED
+//! - \b UDMA_DEF_UART1TX_SEC_RESERVED
+//! - \b UDMA_DEF_SSI1RX_SEC_ADC10
+//! - \b UDMA_DEF_SSI1TX_SEC_ADC11
+//! - \b UDMA_DEF_RESERVED_SEC_ADC12
+//! - \b UDMA_DEF_RESERVED_SEC_ADC13
+//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED
+//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelSelectDefault(uint32_t ui32DefPeriphs)
+{
+ //
+ // Select the default peripheral for the specified channels.
+ //
+ HWREG(UDMA_CHASGN) &= ~ui32DefPeriphs;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the uDMA controller.
+//!
+//! \param ui32IntChannel identifies which uDMA interrupt is to be registered.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! This function registers and enables the handler to be called when the uDMA
+//! controller generates an interrupt. The \e ui32IntChannel parameter should
+//! be one of the following:
+//!
+//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts
+//! from the uDMA software channel (UDMA_CHANNEL_SW)
+//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error
+//! interrupts
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note The interrupt handler for the uDMA is for transfer completion when
+//! the channel UDMA_CHANNEL_SW is used and for error interrupts. The
+//! interrupts for each peripheral channel are handled through the individual
+//! peripheral interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(pfnHandler);
+ ASSERT((ui32IntChannel == UDMA_INT_SW) ||
+ (ui32IntChannel == UDMA_INT_ERR));
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ui32IntChannel, pfnHandler);
+
+ //
+ // Enable the memory management fault.
+ //
+ IntEnable(ui32IntChannel);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the uDMA controller.
+//!
+//! \param ui32IntChannel identifies which uDMA interrupt to unregister.
+//!
+//! This function disables and unregisters the handler to be called for the
+//! specified uDMA interrupt. The \e ui32IntChannel parameter should be one of
+//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function
+//! uDMAIntRegister().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntUnregister(uint32_t ui32IntChannel)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ui32IntChannel);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ui32IntChannel);
+}
+
+//*****************************************************************************
+//
+//! Gets the uDMA controller channel interrupt status.
+//!
+//! This function is used to get the interrupt status of the uDMA controller.
+//! The returned value is a 32-bit bit mask that indicates which channels are
+//! requesting an interrupt. This function can be used from within an
+//! interrupt handler to determine or confirm which uDMA channel has requested
+//! an interrupt.
+//!
+//! \note This function is only available on devices that have the DMA Channel
+//! Interrupt Status Register (DMACHIS). Please consult the data sheet for
+//! your part.
+//!
+//! \return Returns a 32-bit mask which indicates requesting uDMA channels.
+//! There is a bit for each channel and a 1 indicates that the channel
+//! is requesting an interrupt. Multiple bits can be set.
+//
+//*****************************************************************************
+uint32_t
+uDMAIntStatus(void)
+{
+ //
+ // Return the value of the uDMA interrupt status register
+ //
+ return(HWREG(UDMA_CHIS));
+}
+
+//*****************************************************************************
+//
+//! Clears uDMA interrupt status.
+//!
+//! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel.
+//!
+//! This function clears bits in the uDMA interrupt status register according
+//! to which bits are set in \e ui32ChanMask. There is one bit for each
+//! channel. If a a bit is set in \e ui32ChanMask, then that corresponding
+//! channel's interrupt status is cleared (if it was set).
+//!
+//! \note This function is only available on devices that have the DMA Channel
+//! Interrupt Status Register (DMACHIS). Please consult the data sheet for
+//! your part.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntClear(uint32_t ui32ChanMask)
+{
+ //
+ // Clear the requested bits in the uDMA interrupt status register
+ //
+ HWREG(UDMA_CHIS) = ui32ChanMask;
+}
+
+//*****************************************************************************
+//
+//! Assigns a peripheral mapping for a uDMA channel.
+//!
+//! \param ui32Mapping is a macro specifying the peripheral assignment for
+//! a channel.
+//!
+//! This function assigns a peripheral mapping to a uDMA channel. It is
+//! used to select which peripheral is used for a uDMA channel. The parameter
+//! \e ui32Mapping should be one of the macros named \b UDMA_CHn_tttt from the
+//! header file \e udma.h. For example, to assign uDMA channel 0 to the
+//! UART2 RX channel, the parameter should be the macro \b UDMA_CH0_UART2RX.
+//!
+//! Please consult the Tiva data sheet for a table showing all the
+//! possible peripheral assignments for the uDMA channels for a particular
+//! device.
+//!
+//! \note This function is only available on devices that have the DMA Channel
+//! Map Select registers (DMACHMAP0-3). Please consult the data sheet for
+//! your part.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelAssign(uint32_t ui32Mapping)
+{
+ uint32_t ui32MapReg;
+ uint_fast8_t ui8MapShift;
+ uint_fast8_t ui8ChannelNum;
+
+ //
+ // Check the parameters
+ //
+ ASSERT((ui32Mapping & 0xffffff00) < 0x00050000);
+
+ //
+ // Extract the channel number and map encoding value from the parameter.
+ //
+ ui8ChannelNum = ui32Mapping & 0xff;
+ ui32Mapping = ui32Mapping >> 16;
+
+ //
+ // Find the uDMA channel mapping register and shift value to use for this
+ // channel
+ //
+ ui32MapReg = UDMA_CHMAP0 + (uint32_t)((ui8ChannelNum / 8) * 4);
+ ui8MapShift = (ui8ChannelNum % 8) * 4;
+
+ //
+ // Set the channel map encoding for this channel
+ //
+ HWREG(ui32MapReg) = (HWREG(ui32MapReg) & ~(0xf << ui8MapShift)) |
+ ui32Mapping << ui8MapShift;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/udma.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/udma.h
new file mode 100644
index 00000000..f6cf9fe3
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/udma.h
@@ -0,0 +1,757 @@
+//*****************************************************************************
+//
+// udma.h - Prototypes and macros for the uDMA controller.
+//
+// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_UDMA_H__
+#define __DRIVERLIB_UDMA_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup udma_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// A structure that defines an entry in the channel control table. These
+// fields are used by the uDMA controller and normally it is not necessary for
+// software to directly read or write fields in the table.
+//
+//*****************************************************************************
+typedef struct
+{
+ //
+ // The ending source address of the data transfer.
+ //
+ volatile void *pvSrcEndAddr;
+
+ //
+ // The ending destination address of the data transfer.
+ //
+ volatile void *pvDstEndAddr;
+
+ //
+ // The channel control mode.
+ //
+ volatile uint32_t ui32Control;
+
+ //
+ // An unused location.
+ //
+ volatile uint32_t ui32Spare;
+}
+tDMAControlTable;
+
+//*****************************************************************************
+//
+//! A helper macro for building scatter-gather task table entries.
+//!
+//! \param ui32TransferCount is the count of items to transfer for this task.
+//! \param ui32ItemSize is the bit size of the items to transfer for this task.
+//! \param ui32SrcIncrement is the bit size increment for source data.
+//! \param pvSrcAddr is the starting address of the data to transfer.
+//! \param ui32DstIncrement is the bit size increment for destination data.
+//! \param pvDstAddr is the starting address of the destination data.
+//! \param ui32ArbSize is the arbitration size to use for the transfer task.
+//! \param ui32Mode is the transfer mode for this task.
+//!
+//! This macro is intended to be used to help populate a table of uDMA tasks
+//! for a scatter-gather transfer. This macro will calculate the values for
+//! the fields of a task structure entry based on the input parameters.
+//!
+//! There are specific requirements for the values of each parameter. No
+//! checking is done so it is up to the caller to ensure that correct values
+//! are used for the parameters.
+//!
+//! The \e ui32TransferCount parameter is the number of items that will be
+//! transferred by this task. It must be in the range 1-1024.
+//!
+//! The \e ui32ItemSize parameter is the bit size of the transfer data. It
+//! must be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
+//!
+//! The \e ui32SrcIncrement parameter is the increment size for the source
+//! data. It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
+//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
+//!
+//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source
+//! data.
+//!
+//! The \e ui32DstIncrement parameter is the increment size for the destination
+//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16,
+//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE.
+//!
+//! The \e pvDstAddr parameter is a void pointer to the beginning of the
+//! location where the data will be transferred.
+//!
+//! The \e ui32ArbSize parameter is the arbitration size for the transfer, and
+//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
+//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in
+//! powers of 2, from 1 to 1024.
+//!
+//! The \e ui32Mode parameter is the mode to use for this transfer task. It
+//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
+//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note
+//! that normally all tasks will be one of the scatter-gather modes while the
+//! last task is a task list will be AUTO or BASIC.
+//!
+//! This macro is intended to be used to initialize individual entries of
+//! a structure of tDMAControlTable type, like this:
+//!
+//! \verbatim
+//! tDMAControlTable MyTaskList[] =
+//! {
+//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
+//! UDMA_SRC_INC_8, MySourceBuf,
+//! UDMA_DST_INC_8, MyDestBuf,
+//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
+//! uDMATaskStructEntry(Task2Count, ...),
+//! }
+//! \endverbatim
+//!
+//! \return Nothing; this is not a function.
+//
+//*****************************************************************************
+#define uDMATaskStructEntry(ui32TransferCount, \
+ ui32ItemSize, \
+ ui32SrcIncrement, \
+ pvSrcAddr, \
+ ui32DstIncrement, \
+ pvDstAddr, \
+ ui32ArbSize, \
+ ui32Mode) \
+ { \
+ (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \
+ ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \
+ ((ui32SrcIncrement) >> 26)) - 1]))), \
+ (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) :\
+ ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \
+ ((ui32DstIncrement) >> 30)) - 1]))), \
+ (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \
+ (ui32ArbSize) | \
+ (((ui32TransferCount) - 1) << 4) | \
+ ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
+ ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
+ (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \
+ }
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Flags that can be passed to uDMAChannelAttributeEnable(),
+// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
+//
+//*****************************************************************************
+#define UDMA_ATTR_USEBURST 0x00000001
+#define UDMA_ATTR_ALTSELECT 0x00000002
+#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
+#define UDMA_ATTR_REQMASK 0x00000008
+#define UDMA_ATTR_ALL 0x0000000F
+
+//*****************************************************************************
+//
+// DMA control modes that can be passed to uDMAModeSet() and returned
+// uDMAModeGet().
+//
+//*****************************************************************************
+#define UDMA_MODE_STOP 0x00000000
+#define UDMA_MODE_BASIC 0x00000001
+#define UDMA_MODE_AUTO 0x00000002
+#define UDMA_MODE_PINGPONG 0x00000003
+#define UDMA_MODE_MEM_SCATTER_GATHER \
+ 0x00000004
+#define UDMA_MODE_PER_SCATTER_GATHER \
+ 0x00000006
+#define UDMA_MODE_ALT_SELECT 0x00000001
+
+//*****************************************************************************
+//
+// Channel configuration values that can be passed to uDMAControlSet().
+//
+//*****************************************************************************
+#define UDMA_DST_INC_8 0x00000000
+#define UDMA_DST_INC_16 0x40000000
+#define UDMA_DST_INC_32 0x80000000
+#define UDMA_DST_INC_NONE 0xc0000000
+#define UDMA_SRC_INC_8 0x00000000
+#define UDMA_SRC_INC_16 0x04000000
+#define UDMA_SRC_INC_32 0x08000000
+#define UDMA_SRC_INC_NONE 0x0c000000
+#define UDMA_SIZE_8 0x00000000
+#define UDMA_SIZE_16 0x11000000
+#define UDMA_SIZE_32 0x22000000
+#define UDMA_DST_PROT_PRIV 0x00200000
+#define UDMA_SRC_PROT_PRIV 0x00040000
+#define UDMA_ARB_1 0x00000000
+#define UDMA_ARB_2 0x00004000
+#define UDMA_ARB_4 0x00008000
+#define UDMA_ARB_8 0x0000c000
+#define UDMA_ARB_16 0x00010000
+#define UDMA_ARB_32 0x00014000
+#define UDMA_ARB_64 0x00018000
+#define UDMA_ARB_128 0x0001c000
+#define UDMA_ARB_256 0x00020000
+#define UDMA_ARB_512 0x00024000
+#define UDMA_ARB_1024 0x00028000
+#define UDMA_NEXT_USEBURST 0x00000008
+
+//*****************************************************************************
+//
+// Channel numbers to be passed to API functions that require a channel number
+// ID.
+//
+//*****************************************************************************
+#define UDMA_CHANNEL_USBEP1RX 0
+#define UDMA_CHANNEL_USBEP1TX 1
+#define UDMA_CHANNEL_USBEP2RX 2
+#define UDMA_CHANNEL_USBEP2TX 3
+#define UDMA_CHANNEL_USBEP3RX 4
+#define UDMA_CHANNEL_USBEP3TX 5
+#define UDMA_CHANNEL_ETH0RX 6
+#define UDMA_CHANNEL_ETH0TX 7
+#define UDMA_CHANNEL_UART0RX 8
+#define UDMA_CHANNEL_UART0TX 9
+#define UDMA_CHANNEL_SSI0RX 10
+#define UDMA_CHANNEL_SSI0TX 11
+#define UDMA_CHANNEL_ADC0 14
+#define UDMA_CHANNEL_ADC1 15
+#define UDMA_CHANNEL_ADC2 16
+#define UDMA_CHANNEL_ADC3 17
+#define UDMA_CHANNEL_TMR0A 18
+#define UDMA_CHANNEL_TMR0B 19
+#define UDMA_CHANNEL_TMR1A 20
+#define UDMA_CHANNEL_TMR1B 21
+#define UDMA_CHANNEL_UART1RX 22
+#define UDMA_CHANNEL_UART1TX 23
+#define UDMA_CHANNEL_SSI1RX 24
+#define UDMA_CHANNEL_SSI1TX 25
+#define UDMA_CHANNEL_I2S0RX 28
+#define UDMA_CHANNEL_I2S0TX 29
+#define UDMA_CHANNEL_SW 30
+
+//*****************************************************************************
+//
+// Flags to be OR'd with the channel ID to indicate if the primary or alternate
+// control structure should be used.
+//
+//*****************************************************************************
+#define UDMA_PRI_SELECT 0x00000000
+#define UDMA_ALT_SELECT 0x00000020
+
+//*****************************************************************************
+//
+// uDMA interrupt sources, to be passed to uDMAIntRegister() and
+// uDMAIntUnregister().
+//
+//*****************************************************************************
+#define UDMA_INT_SW 62
+#define UDMA_INT_ERR 63
+
+//*****************************************************************************
+//
+// Channel numbers to be passed to API functions that require a channel number
+// ID. These are for secondary peripheral assignments.
+//
+//*****************************************************************************
+#define UDMA_SEC_CHANNEL_UART2RX_0 \
+ 0
+#define UDMA_SEC_CHANNEL_UART2TX_1 \
+ 1
+#define UDMA_SEC_CHANNEL_TMR3A 2
+#define UDMA_SEC_CHANNEL_TMR3B 3
+#define UDMA_SEC_CHANNEL_TMR2A_4 \
+ 4
+#define UDMA_SEC_CHANNEL_TMR2B_5 \
+ 5
+#define UDMA_SEC_CHANNEL_TMR2A_6 \
+ 6
+#define UDMA_SEC_CHANNEL_TMR2B_7 \
+ 7
+#define UDMA_SEC_CHANNEL_UART1RX \
+ 8
+#define UDMA_SEC_CHANNEL_UART1TX \
+ 9
+#define UDMA_SEC_CHANNEL_SSI1RX 10
+#define UDMA_SEC_CHANNEL_SSI1TX 11
+#define UDMA_SEC_CHANNEL_UART2RX_12 \
+ 12
+#define UDMA_SEC_CHANNEL_UART2TX_13 \
+ 13
+#define UDMA_SEC_CHANNEL_TMR2A_14 \
+ 14
+#define UDMA_SEC_CHANNEL_TMR2B_15 \
+ 15
+#define UDMA_SEC_CHANNEL_TMR1A 18
+#define UDMA_SEC_CHANNEL_TMR1B 19
+#define UDMA_SEC_CHANNEL_EPI0RX 20
+#define UDMA_SEC_CHANNEL_EPI0TX 21
+#define UDMA_SEC_CHANNEL_ADC10 24
+#define UDMA_SEC_CHANNEL_ADC11 25
+#define UDMA_SEC_CHANNEL_ADC12 26
+#define UDMA_SEC_CHANNEL_ADC13 27
+#define UDMA_SEC_CHANNEL_SW 30
+
+//*****************************************************************************
+//
+// uDMA default/secondary peripheral selections, to be passed to
+// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault().
+//
+//*****************************************************************************
+#define UDMA_DEF_USBEP1RX_SEC_UART2RX \
+ 0x00000001
+#define UDMA_DEF_USBEP1TX_SEC_UART2TX \
+ 0x00000002
+#define UDMA_DEF_USBEP2RX_SEC_TMR3A \
+ 0x00000004
+#define UDMA_DEF_USBEP2TX_SEC_TMR3B \
+ 0x00000008
+#define UDMA_DEF_USBEP3RX_SEC_TMR2A \
+ 0x00000010
+#define UDMA_DEF_USBEP3TX_SEC_TMR2B \
+ 0x00000020
+#define UDMA_DEF_ETH0RX_SEC_TMR2A \
+ 0x00000040
+#define UDMA_DEF_ETH0TX_SEC_TMR2B \
+ 0x00000080
+#define UDMA_DEF_UART0RX_SEC_UART1RX \
+ 0x00000100
+#define UDMA_DEF_UART0TX_SEC_UART1TX \
+ 0x00000200
+#define UDMA_DEF_SSI0RX_SEC_SSI1RX \
+ 0x00000400
+#define UDMA_DEF_SSI0TX_SEC_SSI1TX \
+ 0x00000800
+#define UDMA_DEF_RESERVED_SEC_UART2RX \
+ 0x00001000
+#define UDMA_DEF_RESERVED_SEC_UART2TX \
+ 0x00002000
+#define UDMA_DEF_ADC00_SEC_TMR2A \
+ 0x00004000
+#define UDMA_DEF_ADC01_SEC_TMR2B \
+ 0x00008000
+#define UDMA_DEF_ADC02_SEC_RESERVED \
+ 0x00010000
+#define UDMA_DEF_ADC03_SEC_RESERVED \
+ 0x00020000
+#define UDMA_DEF_TMR0A_SEC_TMR1A \
+ 0x00040000
+#define UDMA_DEF_TMR0B_SEC_TMR1B \
+ 0x00080000
+#define UDMA_DEF_TMR1A_SEC_EPI0RX \
+ 0x00100000
+#define UDMA_DEF_TMR1B_SEC_EPI0TX \
+ 0x00200000
+#define UDMA_DEF_UART1RX_SEC_RESERVED \
+ 0x00400000
+#define UDMA_DEF_UART1TX_SEC_RESERVED \
+ 0x00800000
+#define UDMA_DEF_SSI1RX_SEC_ADC10 \
+ 0x01000000
+#define UDMA_DEF_SSI1TX_SEC_ADC11 \
+ 0x02000000
+#define UDMA_DEF_RESERVED_SEC_ADC12 \
+ 0x04000000
+#define UDMA_DEF_RESERVED_SEC_ADC13 \
+ 0x08000000
+#define UDMA_DEF_I2S0RX_SEC_RESERVED \
+ 0x10000000
+#define UDMA_DEF_I2S0TX_SEC_RESERVED \
+ 0x20000000
+
+//*****************************************************************************
+//
+// Values that can be passed to uDMAChannelAssign() to select peripheral
+// mapping for each channel. The channels named RESERVED may be assigned
+// to a peripheral in future parts.
+//
+//*****************************************************************************
+//
+// Channel 0
+//
+#define UDMA_CH0_USB0EP1RX 0x00000000
+#define UDMA_CH0_UART2RX 0x00010000
+#define UDMA_CH0_RESERVED2 0x00020000
+#define UDMA_CH0_TIMER4A 0x00030000
+#define UDMA_CH0_RESERVED4 0x00040000
+
+//
+// Channel 1
+//
+#define UDMA_CH1_USB0EP1TX 0x00000001
+#define UDMA_CH1_UART2TX 0x00010001
+#define UDMA_CH1_RESERVED2 0x00020001
+#define UDMA_CH1_TIMER4B 0x00030001
+#define UDMA_CH1_RESERVED4 0x00040001
+
+//
+// Channel 2
+//
+#define UDMA_CH2_USB0EP2RX 0x00000002
+#define UDMA_CH2_TIMER3A 0x00010002
+#define UDMA_CH2_RESERVED2 0x00020002
+#define UDMA_CH2_RESERVED3 0x00030002
+#define UDMA_CH2_RESERVED4 0x00040002
+
+//
+// Channel 3
+//
+#define UDMA_CH3_USB0EP2TX 0x00000003
+#define UDMA_CH3_TIMER3B 0x00010003
+#define UDMA_CH3_RESERVED2 0x00020003
+#define UDMA_CH3_LPC0_3 0x00030003
+#define UDMA_CH3_RESERVED4 0x00040003
+
+//
+// Channel 4
+//
+#define UDMA_CH4_USB0EP3RX 0x00000004
+#define UDMA_CH4_TIMER2A 0x00010004
+#define UDMA_CH4_RESERVED2 0x00020004
+#define UDMA_CH4_GPIOA 0x00030004
+#define UDMA_CH4_RESERVED4 0x00040004
+
+//
+// Channel 5
+//
+#define UDMA_CH5_USB0EP3TX 0x00000005
+#define UDMA_CH5_TIMER2B 0x00010005
+#define UDMA_CH5_RESERVED2 0x00020005
+#define UDMA_CH5_GPIOB 0x00030005
+#define UDMA_CH5_RESERVED4 0x00040005
+
+//
+// Channel 6
+//
+#define UDMA_CH6_RESERVED0 0x00000006
+#define UDMA_CH6_TIMER2A 0x00010006
+#define UDMA_CH6_UART5RX 0x00020006
+#define UDMA_CH6_GPIOC 0x00030006
+#define UDMA_CH6_I2C0RX 0x00040006
+
+//
+// Channel 7
+//
+#define UDMA_CH7_RESERVED0 0x00000007
+#define UDMA_CH7_TIMER2B 0x00010007
+#define UDMA_CH7_UART5TX 0x00020007
+#define UDMA_CH7_GPIOD 0x00030007
+#define UDMA_CH7_I2C0TX 0x00040007
+
+//
+// Channel 8
+//
+#define UDMA_CH8_UART0RX 0x00000008
+#define UDMA_CH8_UART1RX 0x00010008
+#define UDMA_CH8_RESERVED2 0x00020008
+#define UDMA_CH8_TIMER5A 0x00030008
+#define UDMA_CH8_I2C1RX 0x00040008
+
+//
+// Channel 9
+//
+#define UDMA_CH9_UART0TX 0x00000009
+#define UDMA_CH9_UART1TX 0x00010009
+#define UDMA_CH9_RESERVED2 0x00020009
+#define UDMA_CH9_TIMER5B 0x00030009
+#define UDMA_CH9_I2C1TX 0x00040009
+
+//
+// Channel 10
+//
+#define UDMA_CH10_SSI0RX 0x0000000A
+#define UDMA_CH10_SSI1RX 0x0001000A
+#define UDMA_CH10_UART6RX 0x0002000A
+#define UDMA_CH10_WTIMER0A 0x0003000A
+#define UDMA_CH10_I2C2RX 0x0004000A
+
+//
+// Channel 11
+//
+#define UDMA_CH11_SSI0TX 0x0000000B
+#define UDMA_CH11_SSI1TX 0x0001000B
+#define UDMA_CH11_UART6TX 0x0002000B
+#define UDMA_CH11_WTIMER0B 0x0003000B
+#define UDMA_CH11_I2C2TX 0x0004000B
+
+//
+// Channel 12
+//
+#define UDMA_CH12_RESERVED0 0x0000000C
+#define UDMA_CH12_UART2RX 0x0001000C
+#define UDMA_CH12_SSI2RX 0x0002000C
+#define UDMA_CH12_WTIMER1A 0x0003000C
+#define UDMA_CH12_GPIOK 0x0004000C
+
+//
+// Channel 13
+//
+#define UDMA_CH13_RESERVED0 0x0000000D
+#define UDMA_CH13_UART2TX 0x0001000D
+#define UDMA_CH13_SSI2TX 0x0002000D
+#define UDMA_CH13_WTIMER1B 0x0003000D
+#define UDMA_CH13_GPIOL 0x0004000D
+
+//
+// Channel 14
+//
+#define UDMA_CH14_ADC0_0 0x0000000E
+#define UDMA_CH14_TIMER2A 0x0001000E
+#define UDMA_CH14_SSI3RX 0x0002000E
+#define UDMA_CH14_GPIOE 0x0003000E
+#define UDMA_CH14_GPIOM 0x0004000E
+
+//
+// Channel 15
+//
+#define UDMA_CH15_ADC0_1 0x0000000F
+#define UDMA_CH15_TIMER2B 0x0001000F
+#define UDMA_CH15_SSI3TX 0x0002000F
+#define UDMA_CH15_GPIOF 0x0003000F
+#define UDMA_CH15_GPION 0x0004000F
+
+//
+// Channel 16
+//
+#define UDMA_CH16_ADC0_2 0x00000010
+#define UDMA_CH16_RESERVED1 0x00010010
+#define UDMA_CH16_UART3RX 0x00020010
+#define UDMA_CH16_WTIMER2A 0x00030010
+#define UDMA_CH16_GPIOP 0x00040010
+
+//
+// Channel 17
+//
+#define UDMA_CH17_ADC0_3 0x00000011
+#define UDMA_CH17_RESERVED1 0x00010011
+#define UDMA_CH17_UART3TX 0x00020011
+#define UDMA_CH17_WTIMER2B 0x00030011
+#define UDMA_CH17_RESERVED4 0x00040011
+
+//
+// Channel 18
+//
+#define UDMA_CH18_TIMER0A 0x00000012
+#define UDMA_CH18_TIMER1A 0x00010012
+#define UDMA_CH18_UART4RX 0x00020012
+#define UDMA_CH18_GPIOB 0x00030012
+#define UDMA_CH18_I2C3RX 0x00040012
+
+//
+// Channel 19
+//
+#define UDMA_CH19_TIMER0B 0x00000013
+#define UDMA_CH19_TIMER1B 0x00010013
+#define UDMA_CH19_UART4TX 0x00020013
+#define UDMA_CH19_GPIOG 0x00030013
+#define UDMA_CH19_I2C3TX 0x00040013
+
+//
+// Channel 20
+//
+#define UDMA_CH20_TIMER1A 0x00000014
+#define UDMA_CH20_RESERVED1 0x00010014
+#define UDMA_CH20_UART7RX 0x00020014
+#define UDMA_CH20_GPIOH 0x00030014
+#define UDMA_CH20_I2C4RX 0x00040014
+
+//
+// Channel 21
+//
+#define UDMA_CH21_TIMER1B 0x00000015
+#define UDMA_CH21_RESERVED1 0x00010015
+#define UDMA_CH21_UART7TX 0x00020015
+#define UDMA_CH21_GPIOJ 0x00030015
+#define UDMA_CH21_I2C4TX 0x00040015
+
+//
+// Channel 22
+//
+#define UDMA_CH22_UART1RX 0x00000016
+#define UDMA_CH22_RESERVED1 0x00010016
+#define UDMA_CH22_RESERVED2 0x00020016
+#define UDMA_CH22_LPC0_2 0x00030016
+#define UDMA_CH22_I2C5RX 0x00040016
+
+//
+// Channel 23
+//
+#define UDMA_CH23_UART1TX 0x00000017
+#define UDMA_CH23_RESERVED1 0x00010017
+#define UDMA_CH23_RESERVED2 0x00020017
+#define UDMA_CH23_LPC0_1 0x00030017
+#define UDMA_CH23_I2C5TX 0x00040017
+
+//
+// Channel 24
+//
+#define UDMA_CH24_SSI1RX 0x00000018
+#define UDMA_CH24_ADC1_0 0x00010018
+#define UDMA_CH24_RESERVED2 0x00020018
+#define UDMA_CH24_WTIMER3A 0x00030018
+#define UDMA_CH24_GPIOQ 0x00040018
+
+//
+// Channel 25
+//
+#define UDMA_CH25_SSI1TX 0x00000019
+#define UDMA_CH25_ADC1_1 0x00010019
+#define UDMA_CH25_RESERVED2 0x00020019
+#define UDMA_CH25_WTIMER3B 0x00030019
+#define UDMA_CH25_RESERVED4 0x00040019
+
+//
+// Channel 26
+//
+#define UDMA_CH26_RESERVED0 0x0000001A
+#define UDMA_CH26_ADC1_2 0x0001001A
+#define UDMA_CH26_RESERVED2 0x0002001A
+#define UDMA_CH26_WTIMER4A 0x0003001A
+#define UDMA_CH26_RESERVED4 0x0004001A
+
+//
+// Channel 27
+//
+#define UDMA_CH27_RESERVED0 0x0000001B
+#define UDMA_CH27_ADC1_3 0x0001001B
+#define UDMA_CH27_RESERVED2 0x0002001B
+#define UDMA_CH27_WTIMER4B 0x0003001B
+#define UDMA_CH27_RESERVED4 0x0004001B
+
+//
+// Channel 28
+//
+#define UDMA_CH28_RESERVED0 0x0000001C
+#define UDMA_CH28_RESERVED1 0x0001001C
+#define UDMA_CH28_RESERVED2 0x0002001C
+#define UDMA_CH28_WTIMER5A 0x0003001C
+#define UDMA_CH28_RESERVED4 0x0004001C
+
+//
+// Channel 29
+//
+#define UDMA_CH29_RESERVED0 0x0000001D
+#define UDMA_CH29_RESERVED1 0x0001001D
+#define UDMA_CH29_RESERVED2 0x0002001D
+#define UDMA_CH29_WTIMER5B 0x0003001D
+#define UDMA_CH29_RESERVED4 0x0004001D
+
+//
+// Channel 30
+//
+#define UDMA_CH30_SW 0x0000001E
+#define UDMA_CH30_RESERVED1 0x0001001E
+#define UDMA_CH30_RESERVED2 0x0002001E
+#define UDMA_CH30_RESERVED3 0x0003001E
+#define UDMA_CH30_RESERVED4 0x0004001E
+
+//
+// Channel 31
+//
+#define UDMA_CH31_RESERVED0 0x0000001F
+#define UDMA_CH31_RESERVED1 0x0001001F
+#define UDMA_CH31_RESERVED2 0x0002001F
+#define UDMA_CH31_LPC0_0 0x0003001F
+#define UDMA_CH31_RESERVED4 0x0004001F
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void uDMAEnable(void);
+extern void uDMADisable(void);
+extern uint32_t uDMAErrorStatusGet(void);
+extern void uDMAErrorStatusClear(void);
+extern void uDMAChannelEnable(uint32_t ui32ChannelNum);
+extern void uDMAChannelDisable(uint32_t ui32ChannelNum);
+extern bool uDMAChannelIsEnabled(uint32_t ui32ChannelNum);
+extern void uDMAControlBaseSet(void *pControlTable);
+extern void *uDMAControlBaseGet(void);
+extern void *uDMAControlAlternateBaseGet(void);
+extern void uDMAChannelRequest(uint32_t ui32ChannelNum);
+extern void uDMAChannelAttributeEnable(uint32_t ui32ChannelNum,
+ uint32_t ui32Attr);
+extern void uDMAChannelAttributeDisable(uint32_t ui32ChannelNum,
+ uint32_t ui32Attr);
+extern uint32_t uDMAChannelAttributeGet(uint32_t ui32ChannelNum);
+extern void uDMAChannelControlSet(uint32_t ui32ChannelStructIndex,
+ uint32_t ui32Control);
+extern void uDMAChannelTransferSet(uint32_t ui32ChannelStructIndex,
+ uint32_t ui32Mode, void *pvSrcAddr,
+ void *pvDstAddr, uint32_t ui32TransferSize);
+extern void uDMAChannelScatterGatherSet(uint32_t ui32ChannelNum,
+ uint32_t ui32TaskCount,
+ void *pvTaskList,
+ uint32_t ui32IsPeriphSG);
+extern uint32_t uDMAChannelSizeGet(uint32_t ui32ChannelStructIndex);
+extern uint32_t uDMAChannelModeGet(uint32_t ui32ChannelStructIndex);
+extern void uDMAIntRegister(uint32_t ui32IntChannel, void (*pfnHandler)(void));
+extern void uDMAIntUnregister(uint32_t ui32IntChannel);
+extern void uDMAChannelSelectDefault(uint32_t ui32DefPeriphs);
+extern void uDMAChannelSelectSecondary(uint32_t ui32SecPeriphs);
+extern uint32_t uDMAIntStatus(void);
+extern void uDMAIntClear(uint32_t ui32ChanMask);
+extern void uDMAChannelAssign(uint32_t ui32Mapping);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_UDMA_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/usb.c b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/usb.c
new file mode 100644
index 00000000..1b27e3e9
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/usb.c
@@ -0,0 +1,3862 @@
+//*****************************************************************************
+//
+// usb.c - Driver for the USB Interface.
+//
+// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup usb_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_usb.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+#include "driverlib/udma.h"
+#include "driverlib/usb.h"
+
+//*****************************************************************************
+//
+// Amount to shift the RX interrupt sources by in the flags used in the
+// interrupt calls.
+//
+//*****************************************************************************
+#define USB_INTEP_RX_SHIFT 16
+
+//*****************************************************************************
+//
+// Amount to shift the RX endpoint status sources by in the flags used in the
+// calls.
+//
+//*****************************************************************************
+#define USB_RX_EPSTATUS_SHIFT 16
+
+//*****************************************************************************
+//
+// Converts from an endpoint specifier to the offset of the endpoint's
+// control/status registers.
+//
+//*****************************************************************************
+#define EP_OFFSET(Endpoint) (Endpoint - 0x10)
+
+//*****************************************************************************
+//
+// Sets one of the indexed registers.
+//
+// \param ui32Base specifies the USB module base address.
+// \param ui32Endpoint is the endpoint index to target for this write.
+// \param ui32IndexedReg is the indexed register to write to.
+// \param ui8Value is the value to write to the register.
+//
+// This function is used to access the indexed registers for each endpoint.
+// The only registers that are indexed are the FIFO configuration registers,
+// which are not used after configuration.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+_USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32IndexedReg, uint32_t ui32Value, uint32_t ui32Size)
+{
+ uint32_t ui32Index;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) ||
+ (ui32Endpoint == 3));
+ ASSERT((ui32Size == 1) || (ui32Size == 2));
+
+ //
+ // Save the old index in case it was in use.
+ //
+ ui32Index = HWREGB(ui32Base + USB_O_EPIDX);
+
+ //
+ // Set the index.
+ //
+ HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint;
+
+ //
+ // Determine the size of the register value.
+ //
+ if(ui32Size == 1)
+ {
+ //
+ // Set the value.
+ //
+ HWREGB(ui32Base + ui32IndexedReg) = ui32Value;
+ }
+ else
+ {
+ //
+ // Set the value.
+ //
+ HWREGH(ui32Base + ui32IndexedReg) = ui32Value;
+ }
+
+ //
+ // Restore the old index in case it was in use.
+ //
+ HWREGB(ui32Base + USB_O_EPIDX) = ui32Index;
+}
+
+//*****************************************************************************
+//
+// Reads one of the indexed registers.
+//
+// \param ui32Base specifies the USB module base address.
+// \param ui32Endpoint is the endpoint index to target for this write.
+// \param ui32IndexedReg is the indexed register to write to.
+//
+// This function is used internally to access the indexed registers for each
+// endpoint. The only registers that are indexed are the FIFO configuration
+// registers, which are not used after configuration.
+//
+// \return The value in the register requested.
+//
+//*****************************************************************************
+static uint32_t
+_USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32IndexedReg, uint32_t ui32Size)
+{
+ uint8_t ui8Index;
+ uint8_t ui8Value;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) ||
+ (ui32Endpoint == 3));
+ ASSERT((ui32Size == 1) || (ui32Size == 2));
+
+ //
+ // Save the old index in case it was in use.
+ //
+ ui8Index = HWREGB(ui32Base + USB_O_EPIDX);
+
+ //
+ // Set the index.
+ //
+ HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint;
+
+ //
+ // Determine the size of the register value.
+ //
+ if(ui32Size == 1)
+ {
+ //
+ // Get the value.
+ //
+ ui8Value = HWREGB(ui32Base + ui32IndexedReg);
+ }
+ else
+ {
+ //
+ // Get the value.
+ //
+ ui8Value = HWREGH(ui32Base + ui32IndexedReg);
+ }
+
+ //
+ // Restore the old index in case it was in use.
+ //
+ HWREGB(ui32Base + USB_O_EPIDX) = ui8Index;
+
+ //
+ // Return the register's value.
+ //
+ return(ui8Value);
+}
+
+//*****************************************************************************
+//
+//! Puts the USB bus in a suspended state.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! When used in host mode, this function puts the USB bus in the suspended
+//! state.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostSuspend(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Send the suspend signaling to the USB bus.
+ //
+ HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SUSPEND;
+}
+
+//*****************************************************************************
+//
+//! Handles the USB bus reset condition.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param bStart specifies whether to start or stop signaling reset on the USB
+//! bus.
+//!
+//! When this function is called with the \e bStart parameter set to \b true,
+//! this function causes the start of a reset condition on the USB bus.
+//! The caller must then delay at least 20ms before calling this function
+//! again with the \e bStart parameter set to \b false.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostReset(uint32_t ui32Base, bool bStart)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Send a reset signal to the bus.
+ //
+ if(bStart)
+ {
+ HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESET;
+ }
+ else
+ {
+ HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESET;
+ }
+}
+
+//*****************************************************************************
+//
+//! Handles the USB bus resume condition.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param bStart specifies if the USB controller is entering or leaving the
+//! resume signaling state.
+//!
+//! When in device mode, this function brings the USB controller out of the
+//! suspend state. This call must first be made with the \e bStart parameter
+//! set to \b true to start resume signaling. The device application must
+//! then delay at least 10ms but not more than 15ms before calling this
+//! function with the \e bStart parameter set to \b false.
+//!
+//! When in host mode, this function signals devices to leave the suspend
+//! state. This call must first be made with the \e bStart parameter set to
+//! \b true to start resume signaling. The host application must then delay
+//! at least 20ms before calling this function with the \e bStart parameter set
+//! to \b false. This action causes the controller to complete the resume
+//! signaling on the USB bus.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostResume(uint32_t ui32Base, bool bStart)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Send a resume signal to the bus.
+ //
+ if(bStart)
+ {
+ HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESUME;
+ }
+ else
+ {
+ HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESUME;
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the current speed of the USB device connected.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the current speed of the USB bus in host mode.
+//!
+//! \b Example: Get the USB connection speed.
+//!
+//! \verbatim
+//! //
+//! // Get the connection speed of the device connected to the USB controller.
+//! //
+//! USBHostSpeedGet(USB0_BASE);
+//! \endverbatim
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED,
+//! or \b USB_UNDEF_SPEED.
+//
+//*****************************************************************************
+uint32_t
+USBHostSpeedGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // If the Full Speed device bit is set, then this is a full speed device.
+ //
+ if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_FSDEV)
+ {
+ return(USB_FULL_SPEED);
+ }
+
+ //
+ // If the Low Speed device bit is set, then this is a low speed device.
+ //
+ if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_LSDEV)
+ {
+ return(USB_LOW_SPEED);
+ }
+
+ //
+ // The device speed is not known.
+ //
+ return(USB_UNDEF_SPEED);
+}
+
+//*****************************************************************************
+//
+//! Disables control interrupts on a given USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Flags specifies which control interrupts to disable.
+//!
+//! This function disables the control interrupts for the USB controller
+//! specified by the \e ui32Base parameter. The \e ui32Flags parameter
+//! specifies which control interrupts to disable. The flags passed in the
+//! \e ui32Flags parameters must be the definitions that start with
+//! \b USB_INTCTRL_* and not any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Flags & ~(USB_INTCTRL_ALL)) == 0);
+
+ //
+ // If any general interrupts were disabled then write the general interrupt
+ // settings out to the hardware.
+ //
+ if(ui32Flags & USB_INTCTRL_STATUS)
+ {
+ HWREGB(ui32Base + USB_O_IE) &= ~(ui32Flags & USB_INTCTRL_STATUS);
+ }
+
+ //
+ // Disable the power fault interrupt.
+ //
+ if(ui32Flags & USB_INTCTRL_POWER_FAULT)
+ {
+ HWREG(ui32Base + USB_O_EPCIM) = 0;
+ }
+
+ //
+ // Disable the ID pin detect interrupt.
+ //
+ if(ui32Flags & USB_INTCTRL_MODE_DETECT)
+ {
+ HWREG(USB0_BASE + USB_O_IDVIM) = 0;
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables control interrupts on a given USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Flags specifies which control interrupts to enable.
+//!
+//! This function enables the control interrupts for the USB controller
+//! specified by the \e ui32Base parameter. The \e ui32Flags parameter
+//! specifies which control interrupts to enable. The flags passed in the
+//! \e ui32Flags parameters must be the definitions that start with
+//! \b USB_INTCTRL_* and not any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Flags & (~USB_INTCTRL_ALL)) == 0);
+
+ //
+ // If any general interrupts were enabled, then write the general
+ // interrupt settings out to the hardware.
+ //
+ if(ui32Flags & USB_INTCTRL_STATUS)
+ {
+ HWREGB(ui32Base + USB_O_IE) |= ui32Flags;
+ }
+
+ //
+ // Enable the power fault interrupt.
+ //
+ if(ui32Flags & USB_INTCTRL_POWER_FAULT)
+ {
+ HWREG(ui32Base + USB_O_EPCIM) = USB_EPCIM_PF;
+ }
+
+ //
+ // Enable the ID pin detect interrupt.
+ //
+ if(ui32Flags & USB_INTCTRL_MODE_DETECT)
+ {
+ HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID;
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the control interrupt status on a given USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function reads control interrupt status for a USB controller. This
+//! call returns the current status for control interrupts only, the endpoint
+//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit
+//! values returned are compared against the \b USB_INTCTRL_* values.
+//!
+//! The following are the meanings of all \b USB_INCTRL_ flags and the modes
+//! for which they are valid. These values apply to any calls to
+//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl().
+//! Some of these flags are only valid in the following modes as indicated in
+//! the parentheses: Host, Device, and OTG.
+//!
+//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources.
+//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only).
+//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable
+//! (OTG Only).
+//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only)
+//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only)
+//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only)
+//! - \b USB_INTCTRL_SOF - Start of Frame Detected.
+//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past
+//! the end of a frame (Host Only)
+//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only)
+//! - \b USB_INTCTRL_RESUME - Resume signaling detected.
+//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device
+//! Only)
+//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed
+//! (OTG Only)
+//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only)
+//!
+//! \note This call clears the source of all of the control status interrupts.
+//!
+//! \return Returns the status of the control interrupts for a USB controller.
+//
+//*****************************************************************************
+uint32_t
+USBIntStatusControl(uint32_t ui32Base)
+{
+ uint32_t ui32Status;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Get the general interrupt status, these bits go into the upper 8 bits
+ // of the returned value.
+ //
+ ui32Status = HWREGB(ui32Base + USB_O_IS);
+
+ //
+ // Add the power fault status.
+ //
+ if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF)
+ {
+ //
+ // Indicate a power fault was detected.
+ //
+ ui32Status |= USB_INTCTRL_POWER_FAULT;
+
+ //
+ // Clear the power fault interrupt.
+ //
+ HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF;
+ }
+
+ if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID)
+ {
+ //
+ // Indicate an id detection.
+ //
+ ui32Status |= USB_INTCTRL_MODE_DETECT;
+
+ //
+ // Clear the id detection interrupt.
+ //
+ HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID;
+ }
+
+ //
+ // Return the combined interrupt status.
+ //
+ return(ui32Status);
+}
+
+//*****************************************************************************
+//
+//! Disables endpoint interrupts on a given USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Flags specifies which endpoint interrupts to disable.
+//!
+//! This function disables endpoint interrupts for the USB controller specified
+//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which
+//! endpoint interrupts to disable. The flags passed in the \e ui32Flags
+//! parameters must be the definitions that start with \b USB_INTEP_* and not
+//! any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // If any transmit interrupts were disabled, then write the transmit
+ // interrupt settings out to the hardware.
+ //
+ HWREGH(ui32Base + USB_O_TXIE) &=
+ ~(ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0));
+
+ //
+ // If any receive interrupts were disabled, then write the receive
+ // interrupt settings out to the hardware.
+ //
+ HWREGH(ui32Base + USB_O_RXIE) &=
+ ~((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >>
+ USB_INTEP_RX_SHIFT);
+}
+
+//*****************************************************************************
+//
+//! Enables endpoint interrupts on a given USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Flags specifies which endpoint interrupts to enable.
+//!
+//! This function enables endpoint interrupts for the USB controller specified
+//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which
+//! endpoint interrupts to enable. The flags passed in the \e ui32Flags
+//! parameters must be the definitions that start with \b USB_INTEP_* and not
+//! any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Enable any transmit endpoint interrupts.
+ //
+ HWREGH(ui32Base + USB_O_TXIE) |=
+ ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0);
+
+ //
+ // Enable any receive endpoint interrupts.
+ //
+ HWREGH(ui32Base + USB_O_RXIE) |=
+ ((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >>
+ USB_INTEP_RX_SHIFT);
+}
+
+//*****************************************************************************
+//
+//! Returns the endpoint interrupt status on a given USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function reads endpoint interrupt status for a USB controller. This
+//! call returns the current status for endpoint interrupts only, the control
+//! interrupt status is retrieved by calling USBIntStatusControl(). The bit
+//! values returned are compared against the \b USB_INTEP_* values.
+//! These values are grouped into classes for \b USB_INTEP_HOST_* and
+//! \b USB_INTEP_DEV_* values to handle both host and device modes with all
+//! endpoints.
+//!
+//! \note This call clears the source of all of the endpoint interrupts.
+//!
+//! \return Returns the status of the endpoint interrupts for a USB controller.
+//
+//*****************************************************************************
+uint32_t
+USBIntStatusEndpoint(uint32_t ui32Base)
+{
+ uint32_t ui32Status;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Get the transmit interrupt status.
+ //
+ ui32Status = HWREGH(ui32Base + USB_O_TXIS);
+ ui32Status |= (HWREGH(ui32Base + USB_O_RXIS) << USB_INTEP_RX_SHIFT);
+
+ //
+ // Return the combined interrupt status.
+ //
+ return(ui32Status);
+}
+
+//*****************************************************************************
+//
+//! Returns the interrupt number for a given USB module.
+//!
+//! \param ui32Base is the base address of the USB module.
+//!
+//! This function returns the interrupt number for the USB module with the base
+//! address passed in the \e ui32Base parameter.
+//!
+//! \return Returns the USB interrupt number or 0 if the interrupt does not
+//! exist.
+//
+//*****************************************************************************
+static uint32_t
+_USBIntNumberGet(uint32_t ui32Base)
+{
+ uint32_t ui32Int;
+
+ if(CLASS_IS_BLIZZARD)
+ {
+ ui32Int = INT_USB0_BLIZZARD;
+ }
+ else
+ {
+ ui32Int = 0;
+ }
+ return(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param pfnHandler is a pointer to the function to be called when a USB
+//! interrupt occurs.
+//!
+//! This function registers the handler to be called when a USB interrupt
+//! occurs and enables the global USB interrupt in the interrupt controller.
+//! The specific desired USB interrupts must be enabled via a separate call to
+//! USBIntEnable(). It is the interrupt handler's responsibility to clear the
+//! interrupt sources via calls to USBIntStatusControl() and
+//! USBIntStatusEndpoint().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+ uint32_t ui32Int;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ ui32Int = _USBIntNumberGet(ui32Base);
+
+ ASSERT(ui32Int != 0);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ui32Int, pfnHandler);
+
+ //
+ // Enable the USB interrupt.
+ //
+ IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the USB controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function unregisters the interrupt handler. This function also
+//! disables the USB interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering or
+//! unregistering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntUnregister(uint32_t ui32Base)
+{
+ uint32_t ui32Int;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ ui32Int = _USBIntNumberGet(ui32Base);
+
+ ASSERT(ui32Int != 0);
+
+ //
+ // Disable the USB interrupt.
+ //
+ IntDisable(ui32Int);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Returns the current status of an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//!
+//! This function returns the status of a given endpoint. If any of these
+//! status bits must be cleared, then the USBDevEndpointStatusClear() or the
+//! USBHostEndpointStatusClear() functions must be called.
+//!
+//! The following are the status flags for host mode:
+//!
+//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint.
+//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request.
+//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint.
+//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN
+//! endpoint in Isochronous mode.
+//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than
+//! the specified timeout period.
+//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN
+//! endpoint.
+//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full.
+//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint.
+//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than
+//! the specified timeout period.
+//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT
+//! request.
+//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint.
+//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this
+//! OUT endpoint.
+//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty.
+//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not
+//! completed.
+//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the
+//! specified timeout period.
+//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on
+//! endpoint zero.
+//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an
+//! IN transaction.
+//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN
+//! transaction.
+//!
+//! The following are the status flags for device mode:
+//!
+//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint.
+//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT
+//! endpoint.
+//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO.
+//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full.
+//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT
+//! endpoint's FIFO.
+//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come.
+//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint.
+//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no
+//! data was ready.
+//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty.
+//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not
+//! completed.
+//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End
+//! condition was sent.
+//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero.
+//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not
+//! completed.
+//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint
+//! zero's OUT FIFO.
+//!
+//! \return The current status flags for the endpoint depending on mode.
+//
+//*****************************************************************************
+uint32_t
+USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint)
+{
+ uint32_t ui32Status;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // Get the TX portion of the endpoint status.
+ //
+ ui32Status = HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1);
+
+ //
+ // Get the RX portion of the endpoint status.
+ //
+ ui32Status |=
+ ((HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) <<
+ USB_RX_EPSTATUS_SHIFT);
+
+ //
+ // Return the endpoint status.
+ //
+ return(ui32Status);
+}
+
+//*****************************************************************************
+//
+//! Clears the status bits in this endpoint in host mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags are the status bits that are cleared.
+//!
+//! This function clears the status of any bits that are passed in the
+//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value
+//! returned from the USBEndpointStatus() call.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // Clear the specified flags for the endpoint.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ HWREGB(ui32Base + USB_O_CSRL0) &= ~ui32Flags;
+ }
+ else
+ {
+ HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+ ~ui32Flags;
+ HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+ ~(ui32Flags >> USB_RX_EPSTATUS_SHIFT);
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the status bits in this endpoint in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags are the status bits that are cleared.
+//!
+//! This function clears the status of any bits that are passed in the
+//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value
+//! returned from the USBEndpointStatus() call.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // If this is endpoint 0, then the bits have different meaning and map
+ // into the TX memory location.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ //
+ // Set the Serviced RxPktRdy bit to clear the RxPktRdy.
+ //
+ if(ui32Flags & USB_DEV_EP0_OUT_PKTRDY)
+ {
+ HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_RXRDYC;
+ }
+
+ //
+ // Set the serviced Setup End bit to clear the SetupEnd status.
+ //
+ if(ui32Flags & USB_DEV_EP0_SETUP_END)
+ {
+ HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_SETENDC;
+ }
+
+ //
+ // Clear the Sent Stall status flag.
+ //
+ if(ui32Flags & USB_DEV_EP0_SENT_STALL)
+ {
+ HWREGB(ui32Base + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL);
+ }
+ }
+ else
+ {
+ //
+ // Clear out any TX flags that were passed in. Only
+ // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared.
+ //
+ HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+ ~(ui32Flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN));
+
+ //
+ // Clear out valid RX flags that were passed in. Only
+ // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN
+ // must be cleared.
+ //
+ HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+ ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR |
+ USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT);
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the value data toggle on an endpoint in host mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies the endpoint to reset the data toggle.
+//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1.
+//! \param ui32Flags specifies whether to set the IN or OUT endpoint.
+//!
+//! This function is used to force the state of the data toggle in host mode.
+//! If the value passed in the \e bDataToggle parameter is \b false, then the
+//! data toggle is set to the DATA0 state, and if it is \b true it is set to
+//! the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or
+//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The
+//! \e ui32Flags parameter is ignored for endpoint zero.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint,
+ bool bDataToggle, uint32_t ui32Flags)
+{
+ uint32_t ui32DataToggle;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // The data toggle defaults to DATA0.
+ //
+ ui32DataToggle = 0;
+
+ //
+ // See if the data toggle must be set to DATA1.
+ //
+ if(bDataToggle)
+ {
+ //
+ // Select the data toggle bit based on the endpoint.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ ui32DataToggle = USB_CSRH0_DT;
+ }
+ else if(ui32Flags == USB_EP_HOST_IN)
+ {
+ ui32DataToggle = USB_RXCSRH1_DT;
+ }
+ else
+ {
+ ui32DataToggle = USB_TXCSRH1_DT;
+ }
+ }
+
+ //
+ // Set the data toggle based on the endpoint.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ //
+ // Set the write enable and the bit value for endpoint zero.
+ //
+ HWREGB(ui32Base + USB_O_CSRH0) =
+ ((HWREGB(ui32Base + USB_O_CSRH0) &
+ ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) |
+ (ui32DataToggle | USB_CSRH0_DTWE));
+ }
+ else if(ui32Flags == USB_EP_HOST_IN)
+ {
+ //
+ // Set the Write enable and the bit value for an IN endpoint.
+ //
+ HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) =
+ ((HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) &
+ ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) |
+ (ui32DataToggle | USB_RXCSRH1_DTWE));
+ }
+ else
+ {
+ //
+ // Set the Write enable and the bit value for an OUT endpoint.
+ //
+ HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) =
+ ((HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) &
+ ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) |
+ (ui32DataToggle | USB_TXCSRH1_DTWE));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the data toggle on an endpoint to zero.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies the endpoint to reset the data toggle.
+//! \param ui32Flags specifies whether to access the IN or OUT endpoint.
+//!
+//! This function causes the USB controller to clear the data toggle for an
+//! endpoint. This call is not valid for endpoint zero and can be made with
+//! host or device controllers.
+//!
+//! The \e ui32Flags parameter must be one of \b USB_EP_HOST_OUT,
+//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
+ (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
+ (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
+ (ui32Endpoint == USB_EP_7));
+
+ //
+ // See if the transmit or receive data toggle must be cleared.
+ //
+ if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+ {
+ HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+ USB_TXCSRL1_CLRDT;
+ }
+ else
+ {
+ HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+ USB_RXCSRL1_CLRDT;
+ }
+}
+
+//*****************************************************************************
+//
+//! Stalls the specified endpoint in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies the endpoint to stall.
+//! \param ui32Flags specifies whether to stall the IN or OUT endpoint.
+//!
+//! This function causes the endpoint number passed in to go into a stall
+//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the
+//! stall is issued on the IN portion of this endpoint. If the \e ui32Flags
+//! parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion
+//! of this endpoint.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // Determine how to stall this endpoint.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ //
+ // Perform a stall on endpoint zero.
+ //
+ HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_STALL | USB_CSRL0_RXRDYC;
+ }
+ else if(ui32Flags == USB_EP_DEV_IN)
+ {
+ //
+ // Perform a stall on an IN endpoint.
+ //
+ HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+ USB_TXCSRL1_STALL;
+ }
+ else
+ {
+ //
+ // Perform a stall on an OUT endpoint.
+ //
+ HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+ USB_RXCSRL1_STALL;
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the stall condition on the specified endpoint in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies which endpoint to remove the stall condition.
+//! \param ui32Flags specifies whether to remove the stall condition from the
+//! IN or the OUT portion of this endpoint.
+//!
+//! This function causes the endpoint number passed in to exit the stall
+//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the
+//! stall is cleared on the IN portion of this endpoint. If the \e ui32Flags
+//! parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT
+//! portion of this endpoint.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+ ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0);
+
+ //
+ // Determine how to clear the stall on this endpoint.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ //
+ // Clear the stall on endpoint zero.
+ //
+ HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_STALLED;
+ }
+ else if(ui32Flags == USB_EP_DEV_IN)
+ {
+ //
+ // Clear the stall on an IN endpoint.
+ //
+ HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+ ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED);
+
+ //
+ // Reset the data toggle.
+ //
+ HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+ USB_TXCSRL1_CLRDT;
+ }
+ else
+ {
+ //
+ // Clear the stall on an OUT endpoint.
+ //
+ HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+ ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);
+
+ //
+ // Reset the data toggle.
+ //
+ HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+ USB_RXCSRL1_CLRDT;
+ }
+}
+
+//*****************************************************************************
+//
+//! Connects the USB controller to the bus in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function causes the soft connect feature of the USB controller to
+//! be enabled. Call USBDevDisconnect() to remove the USB device from the bus.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevConnect(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Enable connection to the USB bus.
+ //
+ HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SOFTCONN;
+}
+
+//*****************************************************************************
+//
+//! Removes the USB controller from the bus in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function causes the soft connect feature of the USB controller to
+//! remove the device from the USB bus. A call to USBDevConnect() is needed to
+//! reconnect to the bus.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevDisconnect(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Disable connection to the USB bus.
+ //
+ HWREGB(ui32Base + USB_O_POWER) &= (~USB_POWER_SOFTCONN);
+}
+
+//*****************************************************************************
+//
+//! Sets the address in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Address is the address to use for a device.
+//!
+//! This function configures the device address on the USB bus. This address
+//! was likely received via a SET ADDRESS command from the host controller.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Set the function address in the correct location.
+ //
+ HWREGB(ui32Base + USB_O_FADDR) = (uint8_t)ui32Address;
+}
+
+//*****************************************************************************
+//
+//! Returns the current device address in device mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the current device address. This address was set
+//! by a call to USBDevAddrSet().
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return The current device address.
+//
+//*****************************************************************************
+uint32_t
+USBDevAddrGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Return the function address.
+ //
+ return(HWREGB(ui32Base + USB_O_FADDR));
+}
+
+//*****************************************************************************
+//
+//! Sets the base configuration for a host endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32MaxPayload is the maximum payload for this endpoint.
+//! \param ui32NAKPollInterval is the either the NAK timeout limit or the
+//! polling interval, depending on the type of endpoint.
+//! \param ui32TargetEndpoint is the endpoint that the host endpoint is
+//! targeting.
+//! \param ui32Flags are used to configure other endpoint settings.
+//!
+//! This function sets the basic configuration for the transmit or receive
+//! portion of an endpoint in host mode. The \e ui32Flags parameter determines
+//! some of the configuration while the other parameters provide the rest. The
+//! \e ui32Flags parameter determines whether this is an IN endpoint
+//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint
+//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed
+//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint
+//! (\b USB_EP_SPEED_LOW).
+//!
+//! The \b USB_EP_MODE_ flags control the type of the endpoint.
+//! - \b USB_EP_MODE_CTRL is a control endpoint.
+//! - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+//! - \b USB_EP_MODE_BULK is a bulk endpoint.
+//! - \b USB_EP_MODE_INT is an interrupt endpoint.
+//!
+//! The \e ui32NAKPollInterval parameter has different meanings based on the
+//! \b USB_EP_MODE value and whether or not this call is being made for
+//! endpoint zero or another endpoint. For endpoint zero or any Bulk
+//! endpoints, this value always indicates the number of frames to allow a
+//! device to NAK before considering it a timeout. If this endpoint is an
+//! isochronous or interrupt endpoint, this value is the polling interval for
+//! this endpoint.
+//!
+//! For interrupt endpoints, the polling interval is the number of frames
+//! between interrupt IN requests to an endpoint and has a range of 1 to 255.
+//! For isochronous endpoints this value represents a polling interval of
+//! 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the
+//! \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1)
+//! frames before issuing a time out.
+//!
+//! There are two special time out values that can be specified when setting
+//! the \e ui32NAKPollInterval value. The first is \b MAX_NAK_LIMIT, which is
+//! the maximum value that can be passed in this variable. The other is
+//! \b DISABLE_NAK_LIMIT, which indicates that there is no limit on the
+//! number of NAKs.
+//!
+//! The \b USB_EP_DMA_MODE_ flags enable the type of DMA used to access the
+//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA
+//! controller is configured and how it is being used. See the ``Using USB
+//! with the uDMA Controller'' section for more information on DMA
+//! configuration.
+//!
+//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit
+//! is specified to cause the transmission of data on the USB bus to start
+//! as soon as the number of bytes specified by \e ui32MaxPayload has been
+//! written into the OUT FIFO for this endpoint.
+//!
+//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST
+//! bit can be specified to trigger the request for more data once the FIFO has
+//! been drained enough to fit \e ui32MaxPayload bytes. The
+//! \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag
+//! automatically once the data has been read from the FIFO. If this option is
+//! not used, this flag must be manually cleared via a call to
+//! USBDevEndpointStatusClear() or USBHostEndpointStatusClear().
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval,
+ uint32_t ui32TargetEndpoint, uint32_t ui32Flags)
+{
+ uint32_t ui32Register;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+ ASSERT(ui32NAKPollInterval <= MAX_NAK_LIMIT);
+
+ //
+ // Endpoint zero is configured differently than the other endpoints, so see
+ // if this is endpoint zero.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ //
+ // Set the NAK timeout.
+ //
+ HWREGB(ui32Base + USB_O_NAKLMT) = ui32NAKPollInterval;
+
+ //
+ // Set the transfer type information.
+ //
+ HWREGB(ui32Base + USB_O_TYPE0) =
+ ((ui32Flags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL :
+ USB_TYPE0_SPEED_LOW);
+ }
+ else
+ {
+ //
+ // Start with the target endpoint.
+ //
+ ui32Register = ui32TargetEndpoint;
+
+ //
+ // Set the speed for the device using this endpoint.
+ //
+ if(ui32Flags & USB_EP_SPEED_FULL)
+ {
+ ui32Register |= USB_TXTYPE1_SPEED_FULL;
+ }
+ else
+ {
+ ui32Register |= USB_TXTYPE1_SPEED_LOW;
+ }
+
+ //
+ // Set the protocol for the device using this endpoint.
+ //
+ switch(ui32Flags & USB_EP_MODE_MASK)
+ {
+ //
+ // The bulk protocol is being used.
+ //
+ case USB_EP_MODE_BULK:
+ {
+ ui32Register |= USB_TXTYPE1_PROTO_BULK;
+ break;
+ }
+
+ //
+ // The isochronous protocol is being used.
+ //
+ case USB_EP_MODE_ISOC:
+ {
+ ui32Register |= USB_TXTYPE1_PROTO_ISOC;
+ break;
+ }
+
+ //
+ // The interrupt protocol is being used.
+ //
+ case USB_EP_MODE_INT:
+ {
+ ui32Register |= USB_TXTYPE1_PROTO_INT;
+ break;
+ }
+
+ //
+ // The control protocol is being used.
+ //
+ case USB_EP_MODE_CTRL:
+ {
+ ui32Register |= USB_TXTYPE1_PROTO_CTRL;
+ break;
+ }
+ }
+
+ //
+ // See if the transmit or receive endpoint is being configured.
+ //
+ if(ui32Flags & USB_EP_HOST_OUT)
+ {
+ //
+ // Set the transfer type information.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) =
+ ui32Register;
+
+ //
+ // Set the NAK timeout or polling interval.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXINTERVAL1) =
+ ui32NAKPollInterval;
+
+ //
+ // Set the Maximum Payload per transaction.
+ //
+ HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) =
+ ui32MaxPayload;
+
+ //
+ // Set the transmit control value to zero.
+ //
+ ui32Register = 0;
+
+ //
+ // Allow auto setting of TxPktRdy when max packet size has been
+ // loaded into the FIFO.
+ //
+ if(ui32Flags & USB_EP_AUTO_SET)
+ {
+ ui32Register |= USB_TXCSRH1_AUTOSET;
+ }
+
+ //
+ // Configure the DMA Mode.
+ //
+ if(ui32Flags & USB_EP_DMA_MODE_1)
+ {
+ ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
+ }
+ else if(ui32Flags & USB_EP_DMA_MODE_0)
+ {
+ ui32Register |= USB_TXCSRH1_DMAEN;
+ }
+
+ //
+ // Write out the transmit control value.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) =
+ (uint8_t)ui32Register;
+ }
+ else
+ {
+ //
+ // Set the transfer type information.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) =
+ ui32Register;
+
+ //
+ // Set the NAK timeout or polling interval.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXINTERVAL1) =
+ ui32NAKPollInterval;
+
+ //
+ // Set the Maximum Payload per transaction.
+ //
+ HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) =
+ ui32MaxPayload;
+
+ //
+ // Set the receive control value to zero.
+ //
+ ui32Register = 0;
+
+ //
+ // Allow auto clearing of RxPktRdy when packet of size max packet
+ // has been unloaded from the FIFO.
+ //
+ if(ui32Flags & USB_EP_AUTO_CLEAR)
+ {
+ ui32Register |= USB_RXCSRH1_AUTOCL;
+ }
+
+ //
+ // Allow auto generation of DMA requests.
+ //
+ if(ui32Flags & USB_EP_AUTO_REQUEST)
+ {
+ ui32Register |= USB_RXCSRH1_AUTORQ;
+ }
+
+ //
+ // Configure the DMA Mode.
+ //
+ if(ui32Flags & USB_EP_DMA_MODE_1)
+ {
+ ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
+ }
+ else if(ui32Flags & USB_EP_DMA_MODE_0)
+ {
+ ui32Register |= USB_RXCSRH1_DMAEN;
+ }
+
+ //
+ // Write out the receive control value.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) =
+ (uint8_t)ui32Register;
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration for an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32MaxPacketSize is the maximum packet size for this endpoint.
+//! \param ui32Flags are used to configure other endpoint settings.
+//!
+//! This function sets the basic configuration for an endpoint in device mode.
+//! Endpoint zero does not have a dynamic configuration, so this function
+//! must not be called for endpoint zero. The \e ui32Flags parameter
+//! determines some of the configuration while the other parameters provide the
+//! rest.
+//!
+//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint.
+//!
+//! - \b USB_EP_MODE_CTRL is a control endpoint.
+//! - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+//! - \b USB_EP_MODE_BULK is a bulk endpoint.
+//! - \b USB_EP_MODE_INT is an interrupt endpoint.
+//!
+//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the
+//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA
+//! controller is configured and how it is being used. See the ``Using USB
+//! with the uDMA Controller'' section for more information on DMA
+//! configuration.
+//!
+//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be
+//! specified to cause the automatic transmission of data on the USB bus as
+//! soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for
+//! this endpoint. This option is commonly used with DMA as no interaction is
+//! required to start the transmission of data.
+//!
+//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is
+//! specified to trigger the request for more data once the FIFO has been
+//! drained enough to receive \e ui32MaxPacketSize more bytes of data. Also
+//! for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the
+//! data packet ready flag automatically once the data has been read from the
+//! FIFO. If this option is not used, this flag must be manually cleared via a
+//! call to USBDevEndpointStatusClear(). Both of these settings can be used to
+//! remove the need for extra calls when using the controller in DMA mode.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32MaxPacketSize, uint32_t ui32Flags)
+{
+ uint32_t ui32Register;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
+ (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
+ (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
+ (ui32Endpoint == USB_EP_7));
+
+ //
+ // Determine if a transmit or receive endpoint is being configured.
+ //
+ if(ui32Flags & USB_EP_DEV_IN)
+ {
+ //
+ // Set the maximum packet size.
+ //
+ HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) =
+ ui32MaxPacketSize;
+
+ //
+ // The transmit control value is zero unless options are enabled.
+ //
+ ui32Register = 0;
+
+ //
+ // Allow auto setting of TxPktRdy when max packet size has been loaded
+ // into the FIFO.
+ //
+ if(ui32Flags & USB_EP_AUTO_SET)
+ {
+ ui32Register |= USB_TXCSRH1_AUTOSET;
+ }
+
+ //
+ // Configure the DMA mode.
+ //
+ if(ui32Flags & USB_EP_DMA_MODE_1)
+ {
+ ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
+ }
+ else if(ui32Flags & USB_EP_DMA_MODE_0)
+ {
+ ui32Register |= USB_TXCSRH1_DMAEN;
+ }
+
+ //
+ // Enable isochronous mode if requested.
+ //
+ if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
+ {
+ ui32Register |= USB_TXCSRH1_ISO;
+ }
+
+ //
+ // Write the transmit control value.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) =
+ (uint8_t)ui32Register;
+
+ //
+ // Reset the Data toggle to zero.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1) =
+ USB_TXCSRL1_CLRDT;
+ }
+ else
+ {
+ //
+ // Set the MaxPacketSize.
+ //
+ HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) =
+ ui32MaxPacketSize;
+
+ //
+ // The receive control value is zero unless options are enabled.
+ //
+ ui32Register = 0;
+
+ //
+ // Allow auto clearing of RxPktRdy when packet of size max packet
+ // has been unloaded from the FIFO.
+ //
+ if(ui32Flags & USB_EP_AUTO_CLEAR)
+ {
+ ui32Register = USB_RXCSRH1_AUTOCL;
+ }
+
+ //
+ // Configure the DMA mode.
+ //
+ if(ui32Flags & USB_EP_DMA_MODE_1)
+ {
+ ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
+ }
+ else if(ui32Flags & USB_EP_DMA_MODE_0)
+ {
+ ui32Register |= USB_RXCSRH1_DMAEN;
+ }
+
+ //
+ // Enable isochronous mode if requested.
+ //
+ if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
+ {
+ ui32Register |= USB_RXCSRH1_ISO;
+ }
+
+ //
+ // Write the receive control value.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) =
+ (uint8_t)ui32Register;
+
+ //
+ // Reset the Data toggle to zero.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1) =
+ USB_RXCSRL1_CLRDT;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration for an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param pui32MaxPacketSize is a pointer which is written with the maximum
+//! packet size for this endpoint.
+//! \param pui32Flags is a pointer which is written with the current endpoint
+//! settings. On entry to the function, this pointer must contain either
+//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT
+//! endpoint is to be queried.
+//!
+//! This function returns the basic configuration for an endpoint in device
+//! mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are
+//! equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed
+//! to USBDevEndpointConfigSet() for this endpoint.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags)
+{
+ uint32_t ui32Register;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT(pui32MaxPacketSize && pui32Flags);
+ ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
+ (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
+ (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
+ (ui32Endpoint == USB_EP_7));
+
+ //
+ // Determine if a transmit or receive endpoint is being queried.
+ //
+ if(*pui32Flags & USB_EP_DEV_IN)
+ {
+ //
+ // Clear the flags other than the direction bit.
+ //
+ *pui32Flags = USB_EP_DEV_IN;
+
+ //
+ // Get the maximum packet size.
+ //
+ *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base +
+ EP_OFFSET(ui32Endpoint) +
+ USB_O_TXMAXP1);
+
+ //
+ // Get the current transmit control register value.
+ //
+ ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) +
+ USB_O_TXCSRH1);
+
+ //
+ // Are we allowing auto setting of TxPktRdy when max packet size has
+ // been loaded into the FIFO?
+ //
+ if(ui32Register & USB_TXCSRH1_AUTOSET)
+ {
+ *pui32Flags |= USB_EP_AUTO_SET;
+ }
+
+ //
+ // Get the DMA mode.
+ //
+ if(ui32Register & USB_TXCSRH1_DMAEN)
+ {
+ if(ui32Register & USB_TXCSRH1_DMAMOD)
+ {
+ *pui32Flags |= USB_EP_DMA_MODE_1;
+ }
+ else
+ {
+ *pui32Flags |= USB_EP_DMA_MODE_0;
+ }
+ }
+
+ //
+ // Are we in isochronous mode?
+ //
+ if(ui32Register & USB_TXCSRH1_ISO)
+ {
+ *pui32Flags |= USB_EP_MODE_ISOC;
+ }
+ else
+ {
+ //
+ // The hardware doesn't differentiate between bulk, interrupt
+ // and control mode for the endpoint so we just set something
+ // that isn't isochronous. This protocol ensures that anyone
+ // modifying the returned flags in preparation for a call to
+ // USBDevEndpointConfigSet do not see an unexpected mode change.
+ // If they decode the returned mode, however, they may be in for
+ // a surprise.
+ //
+ *pui32Flags |= USB_EP_MODE_BULK;
+ }
+ }
+ else
+ {
+ //
+ // Clear the flags other than the direction bit.
+ //
+ *pui32Flags = USB_EP_DEV_OUT;
+
+ //
+ // Get the MaxPacketSize.
+ //
+ *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base +
+ EP_OFFSET(ui32Endpoint) +
+ USB_O_RXMAXP1);
+
+ //
+ // Get the current receive control register value.
+ //
+ ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) +
+ USB_O_RXCSRH1);
+
+ //
+ // Are we allowing auto clearing of RxPktRdy when packet of size max
+ // packet has been unloaded from the FIFO?
+ //
+ if(ui32Register & USB_RXCSRH1_AUTOCL)
+ {
+ *pui32Flags |= USB_EP_AUTO_CLEAR;
+ }
+
+ //
+ // Get the DMA mode.
+ //
+ if(ui32Register & USB_RXCSRH1_DMAEN)
+ {
+ if(ui32Register & USB_RXCSRH1_DMAMOD)
+ {
+ *pui32Flags |= USB_EP_DMA_MODE_1;
+ }
+ else
+ {
+ *pui32Flags |= USB_EP_DMA_MODE_0;
+ }
+ }
+
+ //
+ // Are we in isochronous mode?
+ //
+ if(ui32Register & USB_RXCSRH1_ISO)
+ {
+ *pui32Flags |= USB_EP_MODE_ISOC;
+ }
+ else
+ {
+ //
+ // The hardware doesn't differentiate between bulk, interrupt
+ // and control mode for the endpoint so we just set something
+ // that isn't isochronous. This protocol ensures that anyone
+ // modifying the returned flags in preparation for a call to
+ // USBDevEndpointConfigSet do not see an unexpected mode change.
+ // If they decode the returned mode, however, they may be in for
+ // a surprise.
+ //
+ *pui32Flags |= USB_EP_MODE_BULK;
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO configuration for an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32FIFOAddress is the starting address for the FIFO.
+//! \param ui32FIFOSize is the size of the FIFO specified by one of the
+//! USB_FIFO_SZ_ values.
+//! \param ui32Flags specifies what information to set in the FIFO
+//! configuration.
+//!
+//! This function configures the starting FIFO RAM address and size of the FIFO
+//! for a given endpoint. Endpoint zero does not have a dynamically
+//! configurable FIFO, so this function must not be called for endpoint zero.
+//! The \e ui32FIFOSize parameter must be one of the values in the
+//! \b USB_FIFO_SZ_ values.
+//!
+//! The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly
+//! indicates the starting address in the USB controller's FIFO RAM. For
+//! example, a value of 64 indicates that the FIFO starts 64 bytes into
+//! the USB controller's FIFO memory. The \e ui32Flags value specifies whether
+//! the endpoint's OUT or IN FIFO must be configured. If in host mode, use
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use
+//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize,
+ uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
+ (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
+ (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
+ (ui32Endpoint == USB_EP_7));
+
+ //
+ // See if the transmit or receive FIFO is being configured.
+ //
+ if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+ {
+ //
+ // Set the transmit FIFO location and size for this endpoint.
+ //
+ _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOSZ,
+ ui32FIFOSize, 1);
+ _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOADD,
+ ui32FIFOAddress >> 3, 2);
+ }
+ else
+ {
+ //
+ // Set the receive FIFO location and size for this endpoint.
+ //
+ _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOSZ,
+ ui32FIFOSize, 1);
+ _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOADD,
+ ui32FIFOAddress >> 3, 2);
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the FIFO configuration for an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param pui32FIFOAddress is the starting address for the FIFO.
+//! \param pui32FIFOSize is the size of the FIFO as specified by one of the
+//! USB_FIFO_SZ_ values.
+//! \param ui32Flags specifies what information to retrieve from the FIFO
+//! configuration.
+//!
+//! This function returns the starting address and size of the FIFO for a
+//! given endpoint. Endpoint zero does not have a dynamically configurable
+//! FIFO, so this function must not be called for endpoint zero. The
+//! \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must
+//! be read. If in host mode, the \e ui32Flags parameter must be
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the
+//! \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or
+//! \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize,
+ uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
+ (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
+ (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
+ (ui32Endpoint == USB_EP_7));
+
+ //
+ // See if the transmit or receive FIFO is being configured.
+ //
+ if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+ {
+ //
+ // Get the transmit FIFO location and size for this endpoint.
+ //
+ *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4,
+ (uint32_t)USB_O_TXFIFOADD,
+ 2)) << 3;
+ *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4,
+ (uint32_t)USB_O_TXFIFOSZ, 1);
+ }
+ else
+ {
+ //
+ // Get the receive FIFO location and size for this endpoint.
+ //
+ *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4,
+ (uint32_t)USB_O_RXFIFOADD,
+ 2)) << 3;
+ *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4,
+ (uint32_t)USB_O_RXFIFOSZ, 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configure the DMA settings for an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Config specifies the configuration options for an endpoint.
+//!
+//! This function configures the DMA settings for a given endpoint without
+//! changing other options that may already be configured. In order for the
+//! DMA transfer to be enabled, the USBEndpointDMAEnable() function must be
+//! called before starting the DMA transfer. The configuration
+//! options are passed in the \e ui32Config parameter and can have the values
+//! described below.
+//!
+//! One of the following values to specify direction:
+//! - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with
+//! DMA transfers from memory to the USB controller.
+//! - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with
+//! DMA transfers from the USB controller to memory.
+//!
+//! One of the following values:
+//! - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for
+//! transfers that do not span multiple packets or when interrupts are
+//! required for each packet.
+//! - \b USB_EP_DMA_MODE_1 - This setting is typically used for
+//! transfers that span multiple packets and do not require interrupts
+//! between packets.
+//!
+//! Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN:
+//! - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers
+//! to automatically be sent when a full packet is loaded into a FIFO.
+//! This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go
+//! out when the FIFO becomes full and the DMA has more data to send.
+//!
+//! Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT:
+//! - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA
+//! transfers to automatically be acknowledged as they are received. This is
+//! needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to
+//! be received and acknowledged when the FIFO is emptied by the DMA
+//! transfer.
+//!
+//! Values only used with \b USB_EP_HOST_IN:
+//! - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA
+//! transfers to automatically request a new IN transaction when the
+//! previous transfer has emptied the FIFO. This is typically used in
+//! conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers
+//! can continue without interrupting the main processor.
+//!
+//! \b Example: Set endpoint 1 receive endpoint to automatically acknowledge
+//! request and automatically generate a new IN request in host mode.
+//!
+//! \verbatim
+//! //
+//! // Configure endpoint 1 for receiving multiple packets using DMA.
+//! //
+//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_1, USB_EP_HOST_IN |
+//! USB_EP_DMA_MODE_1 |
+//! USB_EP_AUTO_CLEAR |
+//! USB_EP_AUTO_REQUEST);
+//! \endverbatim
+//!
+//! \b Example: Set endpoint 2 transmit endpoint to automatically send each
+//! packet in host mode when spanning multiple packets.
+//!
+//! \verbatim
+//! //
+//! // Configure endpoint 1 for transmitting multiple packets using DMA.
+//! //
+//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_2, USB_EP_HOST_OUT |
+//! USB_EP_DMA_MODE_1 |
+//! USB_EP_AUTO_SET);
+//! \endverbatim
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Config)
+{
+ uint32_t ui32NewConfig;
+
+ if(ui32Config & USB_EP_HOST_OUT)
+ {
+ //
+ // Clear mode and DMA enable.
+ //
+ ui32NewConfig =
+ (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &
+ ~(USB_TXCSRH1_DMAMOD | USB_TXCSRH1_AUTOSET));
+
+ if(ui32Config & USB_EP_DMA_MODE_1)
+ {
+ ui32NewConfig |= USB_TXCSRH1_DMAMOD;
+ }
+
+ if(ui32Config & USB_EP_AUTO_SET)
+ {
+ ui32NewConfig |= USB_TXCSRH1_AUTOSET;
+ }
+
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) =
+ ui32NewConfig;
+ }
+ else
+ {
+ ui32NewConfig =
+ (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &
+ ~(USB_RXCSRH1_AUTORQ | USB_RXCSRH1_AUTOCL | USB_RXCSRH1_DMAMOD));
+
+ if(ui32Config & USB_EP_DMA_MODE_1)
+ {
+ ui32NewConfig |= USB_RXCSRH1_DMAMOD;
+ }
+
+ if(ui32Config & USB_EP_AUTO_CLEAR)
+ {
+ ui32NewConfig |= USB_RXCSRH1_AUTOCL;
+ }
+ if(ui32Config & USB_EP_AUTO_REQUEST)
+ {
+ ui32NewConfig |= USB_RXCSRH1_AUTORQ;
+ }
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) =
+ ui32NewConfig;
+ }
+}
+
+//*****************************************************************************
+//
+//! Enable DMA on a given endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags specifies which direction and what mode to use when
+//! enabling DMA.
+//!
+//! This function enables DMA on a given endpoint and configures the mode
+//! according to the values in the \e ui32Flags parameter. The \e ui32Flags
+//! parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this
+//! function is called the only DMA or error interrupts are generated by the
+//! USB controller.
+//!
+//! \note If this function is called when an endpoint is configured in DMA
+//! mode 0 the USB controller does not generate an interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags)
+{
+ //
+ // See if the transmit DMA is being enabled.
+ //
+ if(ui32Flags & USB_EP_DEV_IN)
+ {
+ //
+ // Enable DMA on the transmit endpoint.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) |=
+ USB_TXCSRH1_DMAEN;
+ }
+ else
+ {
+ //
+ // Enable DMA on the receive endpoint.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) |=
+ USB_RXCSRH1_DMAEN;
+ }
+}
+
+//*****************************************************************************
+//
+//! Disable DMA on a given endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags specifies which direction to disable.
+//!
+//! This function disables DMA on a given endpoint to allow non-DMA USB
+//! transactions to generate interrupts normally. The \e ui32Flags parameter
+//! must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags)
+{
+ //
+ // If this was a request to disable DMA on the IN portion of the endpoint
+ // then handle it.
+ //
+ if(ui32Flags & USB_EP_DEV_IN)
+ {
+ //
+ // Just disable DMA leave the mode setting.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &=
+ ~USB_TXCSRH1_DMAEN;
+ }
+ else
+ {
+ //
+ // Just disable DMA leave the mode setting.
+ //
+ HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &=
+ ~USB_RXCSRH1_DMAEN;
+ }
+}
+
+//*****************************************************************************
+//
+//! Determine the number of bytes of data available in a given endpoint's FIFO.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//!
+//! This function returns the number of bytes of data currently available in
+//! the FIFO for the given receive (OUT) endpoint. It may be used prior to
+//! calling USBEndpointDataGet() to determine the size of buffer required to
+//! hold the newly-received packet.
+//!
+//! \return This call returns the number of bytes available in a given endpoint
+//! FIFO.
+//
+//*****************************************************************************
+uint32_t
+USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint)
+{
+ uint32_t ui32Register;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // Get the address of the receive status register to use, based on the
+ // endpoint.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ ui32Register = USB_O_CSRL0;
+ }
+ else
+ {
+ ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint);
+ }
+
+ //
+ // Is there a packet ready in the FIFO?
+ //
+ if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0)
+ {
+ return(0);
+ }
+
+ //
+ // Return the byte count in the FIFO.
+ //
+ return(HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint));
+}
+
+//*****************************************************************************
+//
+//! Retrieves data from the given endpoint's FIFO.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param pui8Data is a pointer to the data area used to return the data from
+//! the FIFO.
+//! \param pui32Size is initially the size of the buffer passed into this call
+//! via the \e pui8Data parameter. It is set to the amount of data returned in
+//! the buffer.
+//!
+//! This function returns the data from the FIFO for the given endpoint.
+//! The \e pui32Size parameter indicates the size of the buffer passed in
+//! the \e pui32Data parameter. The data in the \e pui32Size parameter is
+//! changed to match the amount of data returned in the \e pui8Data parameter.
+//! If a zero-byte packet is received, this call does not return an error but
+//! instead just returns a zero in the \e pui32Size parameter. The only error
+//! case occurs when there is no data packet available.
+//!
+//! \return This call returns 0, or -1 if no packet was received.
+//
+//*****************************************************************************
+int32_t
+USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint8_t *pui8Data, uint32_t *pui32Size)
+{
+ uint32_t ui32Register, ui32ByteCount, ui32FIFO;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // Get the address of the receive status register to use, based on the
+ // endpoint.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ ui32Register = USB_O_CSRL0;
+ }
+ else
+ {
+ ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint);
+ }
+
+ //
+ // Don't allow reading of data if the RxPktRdy bit is not set.
+ //
+ if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0)
+ {
+ //
+ // Can't read the data because none is available.
+ //
+ *pui32Size = 0;
+
+ //
+ // Return a failure since there is no data to read.
+ //
+ return(-1);
+ }
+
+ //
+ // Get the byte count in the FIFO.
+ //
+ ui32ByteCount = HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint);
+
+ //
+ // Determine how many bytes are copied.
+ //
+ ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size;
+
+ //
+ // Return the number of bytes we are going to read.
+ //
+ *pui32Size = ui32ByteCount;
+
+ //
+ // Calculate the FIFO address.
+ //
+ ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2);
+
+ //
+ // Read the data out of the FIFO.
+ //
+ for(; ui32ByteCount > 0; ui32ByteCount--)
+ {
+ //
+ // Read a byte at a time from the FIFO.
+ //
+ *pui8Data++ = HWREGB(ui32FIFO);
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Acknowledge that data was read from the given endpoint's FIFO in device
+//! mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param bIsLastPacket indicates if this packet is the last one.
+//!
+//! This function acknowledges that the data was read from the endpoint's FIFO.
+//! The \e bIsLastPacket parameter is set to a \b true value if this is the
+//! last in a series of data packets on endpoint zero. The \e bIsLastPacket
+//! parameter is not used for endpoints other than endpoint zero. This call
+//! can be used if processing is required between reading the data and
+//! acknowledging that the data has been read.
+//!
+//! \note This function must only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint,
+ bool bIsLastPacket)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // Determine which endpoint is being acked.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ //
+ // Clear RxPktRdy, and optionally DataEnd, on endpoint zero.
+ //
+ HWREGB(ui32Base + USB_O_CSRL0) =
+ USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0);
+ }
+ else
+ {
+ //
+ // Clear RxPktRdy on all other endpoints.
+ //
+ HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+ ~(USB_RXCSRL1_RXRDY);
+ }
+}
+
+//*****************************************************************************
+//
+//! Acknowledge that data was read from the given endpoint's FIFO in host
+//! mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//!
+//! This function acknowledges that the data was read from the endpoint's FIFO.
+//! This call is used if processing is required between reading the data and
+//! acknowledging that the data has been read.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // Clear RxPktRdy.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY;
+ }
+ else
+ {
+ HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &=
+ ~(USB_RXCSRL1_RXRDY);
+ }
+}
+
+//*****************************************************************************
+//
+//! Puts data into the given endpoint's FIFO.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param pui8Data is a pointer to the data area used as the source for the
+//! data to put into the FIFO.
+//! \param ui32Size is the amount of data to put into the FIFO.
+//!
+//! This function puts the data from the \e pui8Data parameter into the FIFO
+//! for this endpoint. If a packet is already pending for transmission, then
+//! this call does not put any of the data into the FIFO and returns -1. Care
+//! must be taken to not write more data than can fit into the FIFO
+//! allocated by the call to USBFIFOConfigSet().
+//!
+//! \return This call returns 0 on success, or -1 to indicate that the FIFO
+//! is in use and cannot be written.
+//
+//*****************************************************************************
+int32_t
+USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint8_t *pui8Data, uint32_t ui32Size)
+{
+ uint32_t ui32FIFO;
+ uint8_t ui8TxPktRdy;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // Get the bit position of TxPktRdy based on the endpoint.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ ui8TxPktRdy = USB_CSRL0_TXRDY;
+ }
+ else
+ {
+ ui8TxPktRdy = USB_TXCSRL1_TXRDY;
+ }
+
+ //
+ // Don't allow transmit of data if the TxPktRdy bit is already set.
+ //
+ if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & ui8TxPktRdy)
+ {
+ return(-1);
+ }
+
+ //
+ // Calculate the FIFO address.
+ //
+ ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2);
+
+ //
+ // Write the data to the FIFO.
+ //
+ for(; ui32Size > 0; ui32Size--)
+ {
+ HWREGB(ui32FIFO) = *pui8Data++;
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Starts the transfer of data from an endpoint's FIFO.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32TransType is set to indicate what type of data is being sent.
+//!
+//! This function starts the transfer of data from the FIFO for a given
+//! endpoint. This function is called if the \b USB_EP_AUTO_SET bit was
+//! not enabled for the endpoint. Setting the \e ui32TransType parameter
+//! allows the appropriate signaling on the USB bus for the type of transaction
+//! being requested. The \e ui32TransType parameter must be one of the
+//! following:
+//!
+//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode.
+//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode.
+//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a
+//! sequence of IN transactions.
+//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero.
+//! - \b USB_TRANS_STATUS for status results on endpoint zero.
+//!
+//! \return This call returns 0 on success, or -1 if a transmission is already
+//! in progress.
+//
+//*****************************************************************************
+int32_t
+USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32TransType)
+{
+ uint32_t ui32TxPktRdy;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // Get the bit position of TxPktRdy based on the endpoint.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ //
+ // Don't allow transmit of data if the TxPktRdy bit is already set.
+ //
+ if(HWREGB(ui32Base + USB_O_CSRL0) & USB_CSRL0_TXRDY)
+ {
+ return(-1);
+ }
+
+ ui32TxPktRdy = ui32TransType & 0xff;
+ }
+ else
+ {
+ //
+ // Don't allow transmit of data if the TxPktRdy bit is already set.
+ //
+ if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & USB_TXCSRL1_TXRDY)
+ {
+ return(-1);
+ }
+
+ ui32TxPktRdy = (ui32TransType >> 8) & 0xff;
+ }
+
+ //
+ // Set TxPktRdy in order to send the data.
+ //
+ HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) = ui32TxPktRdy;
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Forces a flush of an endpoint's FIFO.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags specifies if the IN or OUT endpoint is accessed.
+//!
+//! This function forces the USB controller to flush out the data in the FIFO.
+//! The function can be called with either host or device controllers and
+//! requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT,
+//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // Endpoint zero has a different register set for FIFO flushing.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ //
+ // Nothing in the FIFO if neither of these bits are set.
+ //
+ if((HWREGB(ui32Base + USB_O_CSRL0) &
+ (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0)
+ {
+ //
+ // Hit the Flush FIFO bit.
+ //
+ HWREGB(ui32Base + USB_O_CSRH0) = USB_CSRH0_FLUSH;
+ }
+ }
+ else
+ {
+ //
+ // Only reset the IN or OUT FIFO.
+ //
+ if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+ {
+ //
+ // Make sure the FIFO is not empty.
+ //
+ if(HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &
+ USB_TXCSRL1_TXRDY)
+ {
+ //
+ // Hit the Flush FIFO bit.
+ //
+ HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+ USB_TXCSRL1_FLUSH;
+ }
+ }
+ else
+ {
+ //
+ // Make sure that the FIFO is not empty.
+ //
+ if(HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &
+ USB_RXCSRL1_RXRDY)
+ {
+ //
+ // Hit the Flush FIFO bit.
+ //
+ HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |=
+ USB_RXCSRL1_FLUSH;
+ }
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Schedules a request for an IN transaction on an endpoint in host mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//!
+//! This function schedules a request for an IN transaction. When the USB
+//! device being communicated with responds with the data, the data can be
+//! retrieved by calling USBEndpointDataGet() or via a DMA transfer.
+//!
+//! \note This function must only be called in host mode and only for IN
+//! endpoints.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint)
+{
+ uint32_t ui32Register;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // Endpoint zero uses a different offset than the other endpoints.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ ui32Register = USB_O_CSRL0;
+ }
+ else
+ {
+ ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint);
+ }
+
+ //
+ // Set the request for an IN transaction.
+ //
+ HWREGB(ui32Base + ui32Register) = USB_RXCSRL1_REQPKT;
+}
+
+//*****************************************************************************
+//
+//! Clears a scheduled IN transaction for an endpoint in host mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//!
+//! This function clears a previously scheduled IN transaction if it is still
+//! pending. This function is used to safely disable any scheduled IN
+//! transactions if the endpoint specified by \e ui32Endpoint is reconfigured
+//! for communications with other devices.
+//!
+//! \note This function must only be called in host mode and only for IN
+//! endpoints.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint)
+{
+ uint32_t ui32Register;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // Endpoint zero uses a different offset than the other endpoints.
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ ui32Register = USB_O_CSRL0;
+ }
+ else
+ {
+ ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint);
+ }
+
+ //
+ // Clear the request for an IN transaction.
+ //
+ HWREGB(ui32Base + ui32Register) &= ~USB_RXCSRL1_REQPKT;
+}
+
+//*****************************************************************************
+//
+//! Issues a request for a status IN transaction on endpoint zero.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function is used to cause a request for a status IN transaction from
+//! a device on endpoint zero. This function can only be used with endpoint
+//! zero as that is the only control endpoint that supports this ability. This
+//! function is used to complete the last phase of a control transaction to a
+//! device and an interrupt is signaled when the status packet has been
+//! received.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostRequestStatus(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Set the request for a status IN transaction.
+ //
+ HWREGB(ui32Base + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS;
+}
+
+//*****************************************************************************
+//
+//! Sets the functional address for the device that is connected to an
+//! endpoint in host mode.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Addr is the functional address for the controller to use for
+//! this endpoint.
+//! \param ui32Flags determines if this is an IN or an OUT endpoint.
+//!
+//! This function configures the functional address for a device that is using
+//! this endpoint for communication. This \e ui32Addr parameter is the address
+//! of the target device that this endpoint is communicating with. The
+//! \e ui32Flags parameter indicates if the IN or OUT endpoint is set.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr,
+ uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // See if the transmit or receive address is set.
+ //
+ if(ui32Flags & USB_EP_HOST_OUT)
+ {
+ //
+ // Set the transmit address.
+ //
+ HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1)) = ui32Addr;
+ }
+ else
+ {
+ //
+ // Set the receive address.
+ //
+ HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1)) =
+ ui32Addr;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current functional device address for an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags determines if this is an IN or an OUT endpoint.
+//!
+//! This function returns the current functional address that an endpoint is
+//! using to communicate with a device. The \e ui32Flags parameter determines
+//! if the IN or OUT endpoint's device address is returned.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return Returns the current function address being used by an endpoint.
+//
+//*****************************************************************************
+uint32_t
+USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // See if the transmit or receive address is returned.
+ //
+ if(ui32Flags & USB_EP_HOST_OUT)
+ {
+ //
+ // Return this endpoint's transmit address.
+ //
+ return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1)));
+ }
+ else
+ {
+ //
+ // Return this endpoint's receive address.
+ //
+ return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1)));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the hub address for the device that is connected to an endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Addr is the hub address and port for the device using this
+//! endpoint. The hub address must be defined in bits 0 through 6 with the
+//! port number in bits 8 through 14.
+//! \param ui32Flags determines if this is an IN or an OUT endpoint.
+//!
+//! This function configures the hub address for a device that is using this
+//! endpoint for communication. The \e ui32Flags parameter determines if the
+//! device address for the IN or the OUT endpoint is configured by this call
+//! and sets the speed of the downstream device. Valid values are one of
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with
+//! \b USB_EP_SPEED_LOW.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr,
+ uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // See if the hub transmit or receive address is being set.
+ //
+ if(ui32Flags & USB_EP_HOST_OUT)
+ {
+ //
+ // Set the hub transmit address and port number for this endpoint.
+ //
+ HWREGH(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1)) = ui32Addr;
+ }
+ else
+ {
+ //
+ // Set the hub receive address and port number for this endpoint.
+ //
+ HWREGH(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1)) =
+ ui32Addr;
+ }
+
+ //
+ // Set the speed of communication for endpoint 0. This configuration is
+ // done here because it changes on a transaction-by-transaction basis for
+ // EP0. For other endpoints, this is set in USBHostEndpointConfig().
+ //
+ if(ui32Endpoint == USB_EP_0)
+ {
+ if(ui32Flags & USB_EP_SPEED_FULL)
+ {
+ HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL;
+ }
+ else
+ {
+ HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW;
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current device hub address for this endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint to access.
+//! \param ui32Flags determines if this is an IN or an OUT endpoint.
+//!
+//! This function returns the current hub address that an endpoint is using
+//! to communicate with a device. The \e ui32Flags parameter determines if the
+//! device address for the IN or OUT endpoint is returned.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return This function returns the current hub address being used by an
+//! endpoint.
+//
+//*****************************************************************************
+uint32_t
+USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) ||
+ (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) ||
+ (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) ||
+ (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7));
+
+ //
+ // See if the hub transmit or receive address is returned.
+ //
+ if(ui32Flags & USB_EP_HOST_OUT)
+ {
+ //
+ // Return the hub transmit address for this endpoint.
+ //
+ return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1)));
+ }
+ else
+ {
+ //
+ // Return the hub receive address for this endpoint.
+ //
+ return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1)));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration for USB power fault.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Flags specifies the configuration of the power fault.
+//!
+//! This function controls how the USB controller uses its external power
+//! control pins (USBnPFLT and USBnEPEN). The flags specify the power
+//! fault level sensitivity, the power fault action, and the power enable level
+//! and source.
+//!
+//! One of the following can be selected as the power fault level sensitivity:
+//!
+//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin
+//! being driven low.
+//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin
+//! being driven high.
+//!
+//! One of the following can be selected as the power fault action:
+//!
+//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault
+//! detected.
+//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a
+//! power fault.
+//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a
+//! power fault.
+//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a
+//! power fault.
+//!
+//! One of the following can be selected as the power enable level and source:
+//!
+//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller
+//! when USBHostPwrEnable() is called.
+//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB
+//! controller when USBHostPwrEnable() is
+//! called.
+//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller
+//! automatically if USBOTGSessionRequest() has
+//! enabled a session.
+//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB
+//! controller automatically if
+//! USBOTGSessionRequest() has enabled a
+//! session.
+//!
+//! On devices that support the VBUS glitch filter, the
+//! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS
+//! level caused by high power consumption. This feature is mainly used to
+//! avoid causing VBUS errors caused by devices with high in-rush current.
+//!
+//! \note This function must only be called on microcontrollers that support
+//! host mode or OTG operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Flags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M |
+ USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH |
+ USB_EPC_EPEN_M)) == 0);
+
+ //
+ // If requested, enable VBUS droop detection on parts that support this
+ // feature.
+ //
+ HWREG(ui32Base + USB_O_VDC) = ui32Flags >> 16;
+
+ //
+ // Set the power fault configuration as specified. This configuration
+ // does not change whether fault detection is enabled or not.
+ //
+ HWREGH(ui32Base + USB_O_EPC) =
+ (ui32Flags | (HWREGH(ui32Base + USB_O_EPC) &
+ ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN |
+ USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M)));
+}
+
+//*****************************************************************************
+//
+//! Enables power fault detection.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function enables power fault detection in the USB controller. If the
+//! USBnPFLT pin is not in use, this function must not be used.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrFaultEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Enable power fault input.
+ //
+ HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_PFLTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables power fault detection.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function disables power fault detection in the USB controller.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrFaultDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Enable power fault input.
+ //
+ HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_PFLTEN;
+}
+
+//*****************************************************************************
+//
+//! Enables the external power pin.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function enables the USBnEPEN signal, which enables an external power
+//! supply in host mode operation.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Enable the external power supply enable signal.
+ //
+ HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_EPENDE;
+}
+
+//*****************************************************************************
+//
+//! Disables the external power pin.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function disables the USBnEPEN signal, which disables an external
+//! power supply in host mode operation.
+//!
+//! \note This function must only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Disable the external power supply enable signal.
+ //
+ HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_EPENDE;
+}
+
+//*****************************************************************************
+//
+//! Get the current frame number.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the last frame number received.
+//!
+//! \return The last frame number received.
+//
+//*****************************************************************************
+uint32_t
+USBFrameNumberGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Return the most recent frame number.
+ //
+ return(HWREGH(ui32Base + USB_O_FRAME));
+}
+
+//*****************************************************************************
+//
+//! Starts or ends a session.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param bStart specifies if this call starts or ends a session.
+//!
+//! This function is used in OTG mode to start a session request or end a
+//! session. If the \e bStart parameter is set to \b true, then this function
+//! starts a session and if it is \b false it ends a session.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBOTGSessionRequest(uint32_t ui32Base, bool bStart)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Start or end the session as directed.
+ //
+ if(bStart)
+ {
+ HWREGB(ui32Base + USB_O_DEVCTL) |= USB_DEVCTL_SESSION;
+ }
+ else
+ {
+ HWREGB(ui32Base + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION;
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the absolute FIFO address for a given endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies which endpoint's FIFO address to return.
+//!
+//! This function returns the actual physical address of the FIFO. This
+//! address is needed when the USB is going to be used with the uDMA
+//! controller and the source or destination address must be set to the
+//! physical FIFO address for a given endpoint.
+//!
+//! \return None.
+//
+//*****************************************************************************
+uint32_t
+USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint)
+{
+ //
+ // Return the FIFO address for this endpoint.
+ //
+ return(ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2));
+}
+
+//*****************************************************************************
+//
+//! Returns the current operating mode of the controller.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the current operating mode on USB controllers with
+//! OTG or Dual mode functionality.
+//!
+//! For OTG controllers:
+//!
+//! The function returns one of the following values on OTG controllers:
+//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV,
+//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV,
+//! \b USB_OTG_MODE_NONE.
+//!
+//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode
+//! on the A-side of the cable.
+//!
+//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode
+//! on the A-side of the cable.
+//!
+//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode
+//! on the B-side of the cable.
+//!
+//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode
+//! on the B-side of the cable. If an OTG session request is started with no
+//! cable in place, this mode is the default.
+//!
+//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to
+//! determine its role in the system.
+//!
+//! For Dual Mode controllers:
+//!
+//! The function returns one of the following values:
+//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or
+//! \b USB_DUAL_MODE_NONE.
+//!
+//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host.
+//!
+//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device.
+//!
+//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as
+//! either a host or device.
+//!
+//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV,
+//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV,
+//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or
+//! \b USB_DUAL_MODE_NONE.
+//
+//*****************************************************************************
+uint32_t
+USBModeGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Checks the current mode in the USB_O_DEVCTL and returns the current
+ // mode.
+ //
+ // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION
+ // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION
+ // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION |
+ // USB_DEVCTL_HOST
+ // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION
+ // USB_OTG_MODE_NONE: USB_DEVCTL_DEV
+ //
+ return(HWREGB(ui32Base + USB_O_DEVCTL) &
+ (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION |
+ USB_DEVCTL_VBUS_M));
+}
+
+//*****************************************************************************
+//
+//! Sets the DMA channel to use for a given endpoint.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint specifies which endpoint's FIFO address to return.
+//! \param ui32Channel specifies which DMA channel to use for which endpoint.
+//!
+//! This function is used to configure which DMA channel to use with a given
+//! endpoint. Receive DMA channels can only be used with receive endpoints
+//! and transmit DMA channels can only be used with transmit endpoints. As a
+//! result, the 3 receive and 3 transmit DMA channels can be mapped to any
+//! endpoint other than 0. The values that are passed into the
+//! \e ui32Channel value are the UDMA_CHANNEL_USBEP* values defined in udma.h.
+//!
+//! \note This function only has an effect on microcontrollers that have the
+//! ability to change the DMA channel for an endpoint. Calling this function
+//! on other devices has no effect.
+//!
+//! \return None.
+//!
+//*****************************************************************************
+void
+USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Channel)
+{
+ uint32_t ui32Mask;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+ ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) ||
+ (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) ||
+ (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) ||
+ (ui32Endpoint == USB_EP_7));
+ ASSERT(ui32Channel <= UDMA_CHANNEL_USBEP3TX);
+
+ //
+ // The input select mask must be shifted into the correct position
+ // based on the channel.
+ //
+ ui32Mask = 0xf << (ui32Channel * 4);
+
+ //
+ // Clear out the current selection for the channel.
+ //
+ ui32Mask = HWREG(ui32Base + USB_O_DMASEL) & (~ui32Mask);
+
+ //
+ // The input select is now shifted into the correct position based on the
+ // channel.
+ //
+ ui32Mask |= (USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4);
+
+ //
+ // Write the value out to the register.
+ //
+ HWREG(ui32Base + USB_O_DMASEL) = ui32Mask;
+}
+
+//*****************************************************************************
+//
+//! Change the mode of the USB controller to host.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to host mode.
+//!
+//! \note This function must only be called on microcontrollers that support
+//! OTG operation and have the DEVMODOTG bit in the USBGPCS register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostMode(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Force mode in OTG parts that support forcing USB controller mode.
+ // This bit is not writable in USB controllers that do not support
+ // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a
+ // force of host mode.
+ //
+ HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG;
+}
+
+//*****************************************************************************
+//
+//! Change the mode of the USB controller to device.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to device mode.
+//!
+//! \note This function must only be called on microcontrollers that support
+//! OTG operation and have the DEVMODOTG bit in the USBGPCS register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevMode(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Set the USB controller mode to device.
+ //
+ HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD;
+}
+
+//*****************************************************************************
+//
+//! Change the mode of the USB controller to OTG.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to OTG mode. This
+//! function is only valid on microcontrollers that have the OTG capabilities.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBOTGMode(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == USB0_BASE);
+
+ //
+ // Disable the override of the USB controller mode when running on an OTG
+ // device.
+ //
+ HWREGB(ui32Base + USB_O_GPCS) = 0;
+}
+
+//*****************************************************************************
+//
+//! Powers off the USB PHY.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function powers off the USB PHY, reducing the current consuption
+//! of the device. While in the powered-off state, the USB controller is
+//! unable to operate.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBPHYPowerOff(uint32_t ui32Base)
+{
+ //
+ // Set the PWRDNPHY bit in the PHY, putting it into its low power mode.
+ //
+ HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_PWRDNPHY;
+}
+
+//*****************************************************************************
+//
+//! Powers on the USB PHY.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function powers on the USB PHY, enabling it return to normal
+//! operation. By default, the PHY is powered on, so this function must
+//! only be called if USBPHYPowerOff() has previously been called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBPHYPowerOn(uint32_t ui32Base)
+{
+ //
+ // Clear the PWRDNPHY bit in the PHY, putting it into normal operating
+ // mode.
+ //
+ HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_PWRDNPHY;
+}
+
+//*****************************************************************************
+//
+//! Sets the number of packets to request when transferring multiple bulk
+//! packets.
+//!
+//! \param ui32Base specifies the USB module base address.
+//! \param ui32Endpoint is the endpoint index to target for this write.
+//! \param ui32Count is the number of packets to request.
+//!
+//! This function sets the number of consecutive bulk packets to request
+//! when transferring multiple bulk packets with DMA.
+//!
+//! \note This feature is not available on all Tiva devices. Please
+//! check the data sheet to determine if the USB controller has a DMA
+//! controller or if it must use the uDMA controller for DMA transfers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Count)
+{
+ HWREG(ui32Base + USB_O_RQPKTCOUNT1 +
+ (0x4 * (USBEPToIndex(ui32Endpoint) - 1))) = ui32Count;
+}
+
+//*****************************************************************************
+//
+//! Returns the number of USB endpoint pairs on the device.
+//!
+//! \param ui32Base specifies the USB module base address.
+//!
+//! This function returns the number of endpoint pairs supported by the USB
+//! controller corresponding to the passed base address. The value returned is
+//! the number of IN or OUT endpoints available and does not include endpoint 0
+//! (the control endpoint). For example, if 15 is returned, there are 15 IN
+//! and 15 OUT endpoints available in addition to endpoint 0.
+//!
+//! \return Returns the number of IN or OUT endpoints available.
+//
+//*****************************************************************************
+uint32_t
+USBNumEndpointsGet(uint32_t ui32Base)
+{
+ //
+ // Read the number of endpoints from the hardware. The number of TX and
+ // RX endpoints are always the same.
+ //
+ return(HWREGB(ui32Base + USB_O_EPINFO) & USB_EPINFO_TXEP_M);
+}
+
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/usb.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/usb.h
new file mode 100644
index 00000000..b2b13ba2
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/usb.h
@@ -0,0 +1,481 @@
+//*****************************************************************************
+//
+// usb.h - Prototypes for the USB Interface Driver.
+//
+// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_USB_H__
+#define __DRIVERLIB_USB_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBIntEnableControl() and
+// USBIntDisableControl() as the ui32Flags parameter, and are returned from
+// USBIntStatusControl().
+//
+//*****************************************************************************
+#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources
+#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts
+#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error
+#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected
+#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected
+#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected
+#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected
+#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected
+#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled
+#define USB_INTCTRL_RESET 0x00000004 // Reset signaled
+#define USB_INTCTRL_RESUME 0x00000002 // Resume detected
+#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected
+#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid
+#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBIntEnableEndpoint() and
+// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from
+// USBIntStatusEndpoint().
+//
+//*****************************************************************************
+#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts
+#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts
+#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt
+#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt
+#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt
+#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt
+#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt
+#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt
+#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt
+#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt
+#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt
+#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt
+#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt
+#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt
+#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt
+#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt
+#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt
+
+#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts
+#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt
+
+#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts
+#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt
+
+#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts
+#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt
+#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt
+#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt
+#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt
+#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt
+#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt
+#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt
+#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt
+#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt
+#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt
+#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt
+#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt
+#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt
+#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt
+#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt
+
+#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are values that are returned from USBSpeedGet().
+//
+//*****************************************************************************
+#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined
+#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed
+#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed
+
+//*****************************************************************************
+//
+// The following are values that are returned from USBEndpointStatus(). The
+// USB_HOST_* values are used when the USB controller is in host mode and the
+// USB_DEV_* values are used when the USB controller is in device mode.
+//
+//*****************************************************************************
+#define USB_HOST_IN_STATUS 0xFFFF0000 // Mask of all host IN interrupts
+#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received
+#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond
+#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received
+#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error
+ // (ISOC Mode)
+#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the
+ // specified timeout period
+#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a
+ // device
+#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full
+#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready
+#define USB_HOST_OUT_STATUS 0x0000FFFF // Mask of all host OUT interrupts
+#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the
+ // specified timeout period
+#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device
+ // (ISOC mode)
+#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received
+#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a
+ // device
+#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty
+#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted
+#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the
+ // specified timeout period
+#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet
+#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a
+ // device
+#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received
+#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready
+#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous
+ // transfer
+#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint
+#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data
+#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to
+ // a full FIFO
+#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full
+#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready
+#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data
+ // to come
+#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint
+#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready
+#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty
+#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted
+#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before
+ // Data End seen
+#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint
+#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending
+#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBHostEndpointConfig() and
+// USBDevEndpointConfigSet() as the ui32Flags parameter.
+//
+//*****************************************************************************
+#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled
+#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled
+#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled
+#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0
+#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1
+#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint
+#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint
+#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint
+#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint
+#define USB_EP_MODE_MASK 0x00000300 // Mode Mask
+#define USB_EP_SPEED_LOW 0x00000000 // Low Speed
+#define USB_EP_SPEED_FULL 0x00001000 // Full Speed
+#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint
+#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint
+#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint
+#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBHostPwrConfig() as the
+// ui32Flags parameter.
+//
+//*****************************************************************************
+#define USB_HOST_PWRFLT_LOW 0x00000010
+#define USB_HOST_PWRFLT_HIGH 0x00000030
+#define USB_HOST_PWRFLT_EP_NONE 0x00000000
+#define USB_HOST_PWRFLT_EP_TRI 0x00000140
+#define USB_HOST_PWRFLT_EP_LOW 0x00000240
+#define USB_HOST_PWRFLT_EP_HIGH 0x00000340
+#define USB_HOST_PWREN_MAN_LOW 0x00000000
+#define USB_HOST_PWREN_MAN_HIGH 0x00000001
+#define USB_HOST_PWREN_AUTOLOW 0x00000002
+#define USB_HOST_PWREN_AUTOHIGH 0x00000003
+#define USB_HOST_PWREN_FILTER 0x00010000
+
+//*****************************************************************************
+//
+// The following are special values that can be passed to
+// USBHostEndpointConfig() as the ui32NAKPollInterval parameter.
+//
+//*****************************************************************************
+#define MAX_NAK_LIMIT 31 // Maximum NAK interval
+#define DISABLE_NAK_LIMIT 0 // No NAK timeouts
+
+//*****************************************************************************
+//
+// This value specifies the maximum size of transfers on endpoint 0 as 64
+// bytes. This value is fixed in hardware as the FIFO size for endpoint 0.
+//
+//*****************************************************************************
+#define MAX_PACKET_SIZE_EP0 64
+
+//*****************************************************************************
+//
+// These values are used to indicate which endpoint to access.
+//
+//*****************************************************************************
+#define USB_EP_0 0x00000000 // Endpoint 0
+#define USB_EP_1 0x00000010 // Endpoint 1
+#define USB_EP_2 0x00000020 // Endpoint 2
+#define USB_EP_3 0x00000030 // Endpoint 3
+#define USB_EP_4 0x00000040 // Endpoint 4
+#define USB_EP_5 0x00000050 // Endpoint 5
+#define USB_EP_6 0x00000060 // Endpoint 6
+#define USB_EP_7 0x00000070 // Endpoint 7
+#define NUM_USB_EP 8 // Number of supported endpoints
+
+//*****************************************************************************
+//
+// These macros allow conversion between 0-based endpoint indices and the
+// USB_EP_x values required when calling various USB APIs.
+//
+//*****************************************************************************
+#define IndexToUSBEP(x) ((x) << 4)
+#define USBEPToIndex(x) ((x) >> 4)
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBFIFOConfigSet() as the
+// ui32FIFOSize parameter.
+//
+//*****************************************************************************
+#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO
+#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO
+#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO
+#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO
+#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO
+#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO
+#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO
+#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO
+#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO
+
+//*****************************************************************************
+//
+// This macro allow conversion from a FIFO size label as defined above to
+// a number of bytes
+//
+//*****************************************************************************
+#define USBFIFOSizeToBytes(x) (8 << (x))
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBEndpointDataSend() as the
+// ui32TransType parameter.
+//
+//*****************************************************************************
+#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction
+#define USB_TRANS_IN 0x00000102 // Normal IN transaction
+#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for
+ // endpoint 0 in device mode)
+#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint
+ // 0)
+#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint
+ // 0)
+
+//*****************************************************************************
+//
+// The following are values are returned by the USBModeGet function.
+//
+//*****************************************************************************
+#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host
+ // mode.
+#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in
+ // Device mode.
+#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not
+ // set.
+#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of
+ // the cable.
+#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of
+ // the cable.
+#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of
+ // the cable Session Valid.
+#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of
+ // the cable A valid.
+#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of
+ // the cable.
+#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of
+ // the cable.
+#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of
+ // the cable.
+#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of
+ // the cable.
+#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set.
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern uint32_t USBDevAddrGet(uint32_t ui32Base);
+extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address);
+extern void USBDevConnect(uint32_t ui32Base);
+extern void USBDevDisconnect(uint32_t ui32Base);
+extern void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32MaxPacketSize,
+ uint32_t ui32Flags);
+extern void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t *pui32MaxPacketSize,
+ uint32_t *pui32Flags);
+extern void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint,
+ bool bIsLastPacket);
+extern void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags);
+extern void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags);
+extern void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags);
+extern uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint);
+extern void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags);
+extern void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags);
+extern void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Config);
+extern int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint8_t *pui8Data, uint32_t *pui32Size);
+extern int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint8_t *pui8Data, uint32_t ui32Size);
+extern int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32TransType);
+extern void USBEndpointDataToggleClear(uint32_t ui32Base,
+ uint32_t ui32Endpoint,
+ uint32_t ui32Flags);
+extern void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Count);
+extern uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint);
+extern uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint);
+extern void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t *pui32FIFOAddress,
+ uint32_t *pui32FIFOSize, uint32_t ui32Flags);
+extern void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize,
+ uint32_t ui32Flags);
+extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags);
+extern uint32_t USBFrameNumberGet(uint32_t ui32Base);
+extern uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags);
+extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Addr, uint32_t ui32Flags);
+extern void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32MaxPacketSize,
+ uint32_t ui32NAKPollInterval,
+ uint32_t ui32TargetEndpoint,
+ uint32_t ui32Flags);
+extern void USBHostEndpointDataAck(uint32_t ui32Base,
+ uint32_t ui32Endpoint);
+extern void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint,
+ bool bDataToggle, uint32_t ui32Flags);
+extern void USBHostEndpointStatusClear(uint32_t ui32Base,
+ uint32_t ui32Endpoint,
+ uint32_t ui32Flags);
+extern uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Flags);
+extern void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Addr, uint32_t ui32Flags);
+extern void USBHostPwrDisable(uint32_t ui32Base);
+extern void USBHostPwrEnable(uint32_t ui32Base);
+extern void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags);
+extern void USBHostPwrFaultDisable(uint32_t ui32Base);
+extern void USBHostPwrFaultEnable(uint32_t ui32Base);
+extern void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint);
+extern void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint);
+extern void USBHostRequestStatus(uint32_t ui32Base);
+extern void USBHostReset(uint32_t ui32Base, bool bStart);
+extern void USBHostResume(uint32_t ui32Base, bool bStart);
+extern uint32_t USBHostSpeedGet(uint32_t ui32Base);
+extern void USBHostSuspend(uint32_t ui32Base);
+extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t USBIntStatusControl(uint32_t ui32Base);
+extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern uint32_t USBIntStatusEndpoint(uint32_t ui32Base);
+extern void USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern void USBIntUnregister(uint32_t ui32Base);
+extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart);
+extern uint32_t USBModeGet(uint32_t ui32Base);
+extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint,
+ uint32_t ui32Channel);
+extern void USBHostMode(uint32_t ui32Base);
+extern void USBDevMode(uint32_t ui32Base);
+extern void USBOTGMode(uint32_t ui32Base);
+extern void USBPHYPowerOff(uint32_t ui32Base);
+extern void USBPHYPowerOn(uint32_t ui32Base);
+extern uint32_t USBNumEndpointsGet(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_USB_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/watchdog.c b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/watchdog.c
new file mode 100644
index 00000000..3e576166
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/watchdog.c
@@ -0,0 +1,618 @@
+//*****************************************************************************
+//
+// watchdog.c - Driver for the Watchdog Timer Module.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup watchdog_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_watchdog.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/watchdog.h"
+
+//*****************************************************************************
+//
+//! Determines if the watchdog timer is enabled.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function checks to see if the watchdog timer is enabled.
+//!
+//! \return Returns \b true if the watchdog timer is enabled and \b false
+//! if it is not.
+//
+//*****************************************************************************
+bool
+WatchdogRunning(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // See if the watchdog timer module is enabled, and return.
+ //
+ return(HWREG(ui32Base + WDT_O_CTL) & WDT_CTL_INTEN);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function enables the watchdog timer counter and interrupt.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Enable the watchdog timer module.
+ //
+ HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer reset.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function enables the capability of the watchdog timer to issue a reset
+//! to the processor after a second timeout condition.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogResetEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Enable the watchdog reset.
+ //
+ HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_RESEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the watchdog timer reset.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function disables the capability of the watchdog timer to issue a
+//! reset to the processor after a second timeout condition.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogResetDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Disable the watchdog reset.
+ //
+ HWREG(ui32Base + WDT_O_CTL) &= ~(WDT_CTL_RESEN);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer lock mechanism.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function locks out write access to the watchdog timer configuration
+//! registers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogLock(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
+ // register causes the lock to go into effect.
+ //
+ HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_LOCKED;
+}
+
+//*****************************************************************************
+//
+//! Disables the watchdog timer lock mechanism.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function enables write access to the watchdog timer configuration
+//! registers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogUnlock(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Unlock watchdog register writes.
+ //
+ HWREG(ui32Base + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
+}
+
+//*****************************************************************************
+//
+//! Gets the state of the watchdog timer lock mechanism.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function returns the lock state of the watchdog timer registers.
+//!
+//! \return Returns \b true if the watchdog timer registers are locked, and
+//! \b false if they are not locked.
+//
+//*****************************************************************************
+bool
+WatchdogLockState(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Get the lock state.
+ //
+ return((HWREG(ui32Base + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Sets the watchdog timer reload value.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//! \param ui32LoadVal is the load value for the watchdog timer.
+//!
+//! This function configures the value to load into the watchdog timer when the
+//! count reaches zero for the first time; if the watchdog timer is running
+//! when this function is called, then the value is immediately loaded into the
+//! watchdog timer counter. If the \e ui32LoadVal parameter is 0, then an
+//! interrupt is immediately generated.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Set the load register.
+ //
+ HWREG(ui32Base + WDT_O_LOAD) = ui32LoadVal;
+}
+
+//*****************************************************************************
+//
+//! Gets the watchdog timer reload value.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function gets the value that is loaded into the watchdog timer when
+//! the count reaches zero for the first time.
+//!
+//! \return None.
+//
+//*****************************************************************************
+uint32_t
+WatchdogReloadGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Get the load register.
+ //
+ return(HWREG(ui32Base + WDT_O_LOAD));
+}
+
+//*****************************************************************************
+//
+//! Gets the current watchdog timer value.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function reads the current value of the watchdog timer.
+//!
+//! \return Returns the current value of the watchdog timer.
+//
+//*****************************************************************************
+uint32_t
+WatchdogValueGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Get the current watchdog timer register value.
+ //
+ return(HWREG(ui32Base + WDT_O_VALUE));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the watchdog timer interrupt.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! watchdog timer interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! function also enables the global interrupt in the interrupt controller; the
+//! watchdog timer interrupt must be enabled via WatchdogEnable(). It is the
+//! interrupt handler's responsibility to clear the interrupt source via
+//! WatchdogIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note For parts with a watchdog timer module that has the ability to
+//! generate an NMI instead of a standard interrupt, this function registers
+//! the standard watchdog interrupt handler. To register the NMI watchdog
+//! handler, use IntRegister() to register the handler for the
+//! \b FAULT_NMI interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_WATCHDOG_BLIZZARD, pfnHandler);
+
+ //
+ // Enable the watchdog timer interrupt.
+ //
+ IntEnable(INT_WATCHDOG_BLIZZARD);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the watchdog timer interrupt.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function does the actual unregistering of the interrupt handler. This
+//! function clears the handler to be called when a watchdog timer interrupt
+//! occurs. This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note For parts with a watchdog timer module that has the ability to
+//! generate an NMI instead of a standard interrupt, this function unregisters
+//! the standard watchdog interrupt handler. To unregister the NMI watchdog
+//! handler, use IntUnregister() to unregister the handler for the
+//! \b FAULT_NMI interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntUnregister(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_WATCHDOG_BLIZZARD);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_WATCHDOG_BLIZZARD);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer interrupt.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function enables the watchdog timer interrupt.
+//!
+//! \note This function has no effect if the watchdog timer has been locked.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Enable the watchdog interrupt.
+ //
+ HWREG(ui32Base + WDT_O_CTL) |= WDT_CTL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Gets the current watchdog timer interrupt status.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the watchdog timer module.
+//! Either the raw interrupt status or the status of interrupt that is allowed
+//! to reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, where a 1 indicates that the
+//! watchdog interrupt is active, and a 0 indicates that it is not active.
+//
+//*****************************************************************************
+uint32_t
+WatchdogIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ui32Base + WDT_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ui32Base + WDT_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the watchdog timer interrupt.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! The watchdog timer interrupt source is cleared, so that it no longer
+//! asserts.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntClear(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Clear the interrupt source.
+ //
+ HWREG(ui32Base + WDT_O_ICR) = WDT_RIS_WDTRIS;
+}
+
+//*****************************************************************************
+//
+//! Sets the type of interrupt generated by the watchdog.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//! \param ui32Type is the type of interrupt to generate.
+//!
+//! This function sets the type of interrupt that is generated if the watchdog
+//! timer expires. \e ui32Type can be either \b WATCHDOG_INT_TYPE_INT to
+//! generate a standard interrupt (the default) or \b WATCHDOG_INT_TYPE_NMI to
+//! generate a non-maskable interrupt (NMI).
+//!
+//! When configured to generate an NMI, the watchdog interrupt must still be
+//! enabled with WatchdogIntEnable(), and it must still be cleared inside the
+//! NMI handler with WatchdogIntClear().
+//!
+//! \note The ability to select an NMI interrupt varies with the Tiva part
+//! in use. Please consult the datasheet for the part you are using to
+//! determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+ ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) ||
+ (ui32Type == WATCHDOG_INT_TYPE_NMI));
+
+ //
+ // Set the interrupt type.
+ //
+ HWREG(ui32Base + WDT_O_CTL) = (HWREG(ui32Base + WDT_O_CTL) &
+ ~WDT_CTL_INTTYPE) | ui32Type;
+}
+
+//*****************************************************************************
+//
+//! Enables stalling of the watchdog timer during debug events.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function allows the watchdog timer to stop counting when the processor
+//! is stopped by the debugger. By doing so, the watchdog is prevented from
+//! expiring (typically almost immediately from a human time perspective) and
+//! resetting the system (if reset is enabled). The watchdog instead expires
+//! after the appropriate number of processor cycles have been executed while
+//! debugging (or at the appropriate time after the processor has been
+//! restarted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogStallEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Enable timer stalling.
+ //
+ HWREG(ui32Base + WDT_O_TEST) |= WDT_TEST_STALL;
+}
+
+//*****************************************************************************
+//
+//! Disables stalling of the watchdog timer during debug events.
+//!
+//! \param ui32Base is the base address of the watchdog timer module.
+//!
+//! This function disables the debug mode stall of the watchdog timer. By
+//! doing so, the watchdog timer continues to count regardless of the processor
+//! debug state.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogStallDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ui32Base == WATCHDOG0_BASE) || (ui32Base == WATCHDOG1_BASE));
+
+ //
+ // Disable timer stalling.
+ //
+ HWREG(ui32Base + WDT_O_TEST) &= ~(WDT_TEST_STALL);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/watchdog.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/watchdog.h
new file mode 100644
index 00000000..f1a2aca5
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/driverlib/watchdog.h
@@ -0,0 +1,95 @@
+//*****************************************************************************
+//
+// watchdog.h - Prototypes for the Watchdog Timer API
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_WATCHDOG_H__
+#define __DRIVERLIB_WATCHDOG_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The type of interrupt that can be generated by the watchdog.
+//
+//*****************************************************************************
+#define WATCHDOG_INT_TYPE_INT 0x00000000
+#define WATCHDOG_INT_TYPE_NMI 0x00000004
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern bool WatchdogRunning(uint32_t ui32Base);
+extern void WatchdogEnable(uint32_t ui32Base);
+extern void WatchdogResetEnable(uint32_t ui32Base);
+extern void WatchdogResetDisable(uint32_t ui32Base);
+extern void WatchdogLock(uint32_t ui32Base);
+extern void WatchdogUnlock(uint32_t ui32Base);
+extern bool WatchdogLockState(uint32_t ui32Base);
+extern void WatchdogReloadSet(uint32_t ui32Base, uint32_t ui32LoadVal);
+extern uint32_t WatchdogReloadGet(uint32_t ui32Base);
+extern uint32_t WatchdogValueGet(uint32_t ui32Base);
+extern void WatchdogIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
+extern void WatchdogIntUnregister(uint32_t ui32Base);
+extern void WatchdogIntEnable(uint32_t ui32Base);
+extern uint32_t WatchdogIntStatus(uint32_t ui32Base, bool bMasked);
+extern void WatchdogIntClear(uint32_t ui32Base);
+extern void WatchdogIntTypeSet(uint32_t ui32Base, uint32_t ui32Type);
+extern void WatchdogStallEnable(uint32_t ui32Base);
+extern void WatchdogStallDisable(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_WATCHDOG_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/asmdefs.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/asmdefs.h
new file mode 100644
index 00000000..5379a3cc
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/asmdefs.h
@@ -0,0 +1,227 @@
+//*****************************************************************************
+//
+// asmdefs.h - Macros to allow assembly code be portable among toolchains.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __ASMDEFS_H__
+#define __ASMDEFS_H__
+
+//*****************************************************************************
+//
+// The defines required for code_red.
+//
+//*****************************************************************************
+#ifdef codered
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // codered
+
+//*****************************************************************************
+//
+// The defines required for EW-ARM.
+//
+//*****************************************************************************
+#ifdef ewarm
+
+//
+// Section headers.
+//
+#define __LIBRARY__ module
+#define __TEXT__ rseg CODE:CODE(2)
+#define __DATA__ rseg DATA:DATA(2)
+#define __BSS__ rseg DATA:DATA(2)
+#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ alignrom 2
+#define __END__ end
+#define __EXPORT__ export
+#define __IMPORT__ import
+#define __LABEL__
+#define __STR__ dcb
+#define __THUMB_LABEL__ thumb
+#define __WORD__ dcd
+#define __INLINE_DATA__ data
+
+#endif // ewarm
+
+//*****************************************************************************
+//
+// The defines required for GCC.
+//
+//*****************************************************************************
+#if defined(gcc)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // gcc
+
+//*****************************************************************************
+//
+// The defines required for RV-MDK.
+//
+//*****************************************************************************
+#ifdef rvmdk
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ thumb
+ require8
+ preserve8
+
+//
+// Section headers.
+//
+#define __LIBRARY__ ;
+#define __TEXT__ area ||.text||, code, readonly, align=2
+#define __DATA__ area ||.data||, data, align=2
+#define __BSS__ area ||.bss||, noinit, align=2
+#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ align 4
+#define __END__ end
+#define __EXPORT__ export
+#define __IMPORT__ import
+#define __LABEL__
+#define __STR__ dcb
+#define __THUMB_LABEL__
+#define __WORD__ dcd
+#define __INLINE_DATA__
+
+#endif // rvmdk
+
+//*****************************************************************************
+//
+// The defines required for Sourcery G++.
+//
+//*****************************************************************************
+#if defined(sourcerygxx)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // sourcerygxx
+
+#endif // __ASMDEF_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_adc.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_adc.h
new file mode 100644
index 00000000..c5c7e71c
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_adc.h
@@ -0,0 +1,1148 @@
+//*****************************************************************************
+//
+// hw_adc.h - Macros used when accessing the ADC hardware.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ADC_H__
+#define __HW_ADC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_O_ACTSS 0x00000000 // ADC Active Sample Sequencer
+#define ADC_O_RIS 0x00000004 // ADC Raw Interrupt Status
+#define ADC_O_IM 0x00000008 // ADC Interrupt Mask
+#define ADC_O_ISC 0x0000000C // ADC Interrupt Status and Clear
+#define ADC_O_OSTAT 0x00000010 // ADC Overflow Status
+#define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select
+#define ADC_O_USTAT 0x00000018 // ADC Underflow Status
+#define ADC_O_TSSEL 0x0000001C // ADC Trigger Source Select
+#define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority
+#define ADC_O_SPC 0x00000024 // ADC Sample Phase Control
+#define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence
+ // Initiate
+#define ADC_O_SAC 0x00000030 // ADC Sample Averaging Control
+#define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt
+ // Status and Clear
+#define ADC_O_CTL 0x00000038 // ADC Control
+#define ADC_O_SSMUX0 0x00000040 // ADC Sample Sequence Input
+ // Multiplexer Select 0
+#define ADC_O_SSCTL0 0x00000044 // ADC Sample Sequence Control 0
+#define ADC_O_SSFIFO0 0x00000048 // ADC Sample Sequence Result FIFO
+ // 0
+#define ADC_O_SSFSTAT0 0x0000004C // ADC Sample Sequence FIFO 0
+ // Status
+#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation
+#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital
+ // Comparator Select
+#define ADC_O_SSEMUX0 0x00000058 // ADC Sample Sequence Extended
+ // Input Multiplexer Select 0
+#define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input
+ // Multiplexer Select 1
+#define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1
+#define ADC_O_SSFIFO1 0x00000068 // ADC Sample Sequence Result FIFO
+ // 1
+#define ADC_O_SSFSTAT1 0x0000006C // ADC Sample Sequence FIFO 1
+ // Status
+#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation
+#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital
+ // Comparator Select
+#define ADC_O_SSEMUX1 0x00000078 // ADC Sample Sequence Extended
+ // Input Multiplexer Select 1
+#define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input
+ // Multiplexer Select 2
+#define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2
+#define ADC_O_SSFIFO2 0x00000088 // ADC Sample Sequence Result FIFO
+ // 2
+#define ADC_O_SSFSTAT2 0x0000008C // ADC Sample Sequence FIFO 2
+ // Status
+#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation
+#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital
+ // Comparator Select
+#define ADC_O_SSEMUX2 0x00000098 // ADC Sample Sequence Extended
+ // Input Multiplexer Select 2
+#define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input
+ // Multiplexer Select 3
+#define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3
+#define ADC_O_SSFIFO3 0x000000A8 // ADC Sample Sequence Result FIFO
+ // 3
+#define ADC_O_SSFSTAT3 0x000000AC // ADC Sample Sequence FIFO 3
+ // Status
+#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation
+#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital
+ // Comparator Select
+#define ADC_O_SSEMUX3 0x000000B8 // ADC Sample Sequence Extended
+ // Input Multiplexer Select 3
+#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset
+ // Initial Conditions
+#define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0
+#define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1
+#define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2
+#define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3
+#define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4
+#define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5
+#define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6
+#define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7
+#define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0
+#define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1
+#define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2
+#define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3
+#define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4
+#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5
+#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6
+#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7
+#define ADC_O_PP 0x00000FC0 // ADC Peripheral Properties
+#define ADC_O_PC 0x00000FC4 // ADC Peripheral Configuration
+#define ADC_O_CC 0x00000FC8 // ADC Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt
+ // Status
+#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on
+ // SS3
+#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on
+ // SS2
+#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on
+ // SS1
+#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on
+ // SS0
+#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask
+#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask
+#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask
+#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt
+ // Status on SS3
+#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt
+ // Status on SS2
+#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt
+ // Status on SS1
+#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt
+ // Status on SS0
+#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2
+#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM3
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
+#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2
+#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM3
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
+#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2
+#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM3
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
+#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2
+#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM3
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow
+#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow
+#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow
+#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TSSEL register.
+//
+//*****************************************************************************
+#define ADC_TSSEL_PS3_M 0x30000000 // PWM Unit Select
+#define ADC_TSSEL_PS3_0 0x00000000 // PWM Unit 0
+#define ADC_TSSEL_PS3_1 0x10000000 // PWM Unit 1
+#define ADC_TSSEL_PS2_M 0x00300000 // PWM Unit Select
+#define ADC_TSSEL_PS2_0 0x00000000 // PWM Unit 0
+#define ADC_TSSEL_PS2_1 0x00100000 // PWM Unit 1
+#define ADC_TSSEL_PS1_M 0x00003000 // PWM Unit Select
+#define ADC_TSSEL_PS1_0 0x00000000 // PWM Unit 0
+#define ADC_TSSEL_PS1_1 0x00001000 // PWM Unit 1
+#define ADC_TSSEL_PS0_M 0x00000030 // PWM Unit Select
+#define ADC_TSSEL_PS0_0 0x00000000 // PWM Unit 0
+#define ADC_TSSEL_PS0_1 0x00000010 // PWM Unit 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority
+#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority
+#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority
+#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SPC register.
+//
+//*****************************************************************************
+#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference
+#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize
+#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait
+#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate
+#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate
+#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate
+#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt
+ // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CTL register.
+//
+//*****************************************************************************
+#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select
+#define ADC_CTL_VREF_INTERNAL 0x00000000 // The internal reference as the
+ // voltage reference
+#define ADC_CTL_VREF_EXT_3V 0x00000001 // A 3.0 V external VREFA input is
+ // the voltage reference. The ADC
+ // conversion range is 0.0 V to the
+ // external reference value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S 28
+#define ADC_SSMUX0_MUX6_S 24
+#define ADC_SSMUX0_MUX5_S 20
+#define ADC_SSMUX0_MUX4_S 16
+#define ADC_SSMUX0_MUX3_S 12
+#define ADC_SSMUX0_MUX2_S 8
+#define ADC_SSMUX0_MUX1_S 4
+#define ADC_SSMUX0_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S 4
+#define ADC_SSFSTAT0_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator
+ // Select
+#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator
+ // Select
+#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator
+ // Select
+#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator
+ // Select
+#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC0_S6DCSEL_S 24
+#define ADC_SSDC0_S5DCSEL_S 20
+#define ADC_SSDC0_S4DCSEL_S 16
+#define ADC_SSDC0_S3DCSEL_S 12
+#define ADC_SSDC0_S2DCSEL_S 8
+#define ADC_SSDC0_S1DCSEL_S 4
+#define ADC_SSDC0_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S 12
+#define ADC_SSMUX1_MUX2_S 8
+#define ADC_SSMUX1_MUX1_S 4
+#define ADC_SSMUX1_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S 4
+#define ADC_SSFSTAT1_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC1_S2DCSEL_S 8
+#define ADC_SSDC1_S1DCSEL_S 4
+#define ADC_SSDC1_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S 12
+#define ADC_SSMUX2_MUX2_S 8
+#define ADC_SSMUX2_MUX1_S 4
+#define ADC_SSMUX2_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S 4
+#define ADC_SSFSTAT2_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC2_S2DCSEL_S 8
+#define ADC_SSDC2_S1DCSEL_S 4
+#define ADC_SSDC2_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S 4
+#define ADC_SSFSTAT3_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP0_COMP1_S 16
+#define ADC_DCCMP0_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP1_COMP1_S 16
+#define ADC_DCCMP1_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP2_COMP1_S 16
+#define ADC_DCCMP2_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP3_COMP1_S 16
+#define ADC_DCCMP3_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP4_COMP1_S 16
+#define ADC_DCCMP4_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP5_COMP1_S 16
+#define ADC_DCCMP5_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP6_COMP1_S 16
+#define ADC_DCCMP6_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP7_COMP1_S 16
+#define ADC_DCCMP7_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PP register.
+//
+//*****************************************************************************
+#define ADC_PP_TS 0x00800000 // Temperature Sensor
+#define ADC_PP_RSL_M 0x007C0000 // Resolution
+#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture
+#define ADC_PP_TYPE_SAR 0x00000000 // SAR
+#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count
+#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count
+#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate
+#define ADC_PP_MSR_125K 0x00000001 // 125 ksps
+#define ADC_PP_MSR_250K 0x00000003 // 250 ksps
+#define ADC_PP_MSR_500K 0x00000005 // 500 ksps
+#define ADC_PP_MSR_1M 0x00000007 // 1 Msps
+#define ADC_PP_RSL_S 18
+#define ADC_PP_DC_S 10
+#define ADC_PP_CH_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PC register.
+//
+//*****************************************************************************
+#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate
+#define ADC_PC_SR_125K 0x00000001 // 125 ksps
+#define ADC_PC_SR_250K 0x00000003 // 250 ksps
+#define ADC_PC_SR_500K 0x00000005 // 500 ksps
+#define ADC_PC_SR_1M 0x00000007 // 1 Msps
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CC register.
+//
+//*****************************************************************************
+#define ADC_CC_CS_M 0x0000000F // ADC Clock Source
+#define ADC_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
+ // PLL bypass is in effect) or the
+ // 16 MHz clock derived from PLL /
+ // 25 (default)
+#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC
+
+#endif // __HW_ADC_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_can.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_can.h
new file mode 100644
index 00000000..6d05c1f6
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_can.h
@@ -0,0 +1,462 @@
+//*****************************************************************************
+//
+// hw_can.h - Defines and macros used when accessing the CAN controllers.
+//
+// Copyright (c) 2006-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_CAN_H__
+#define __HW_CAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the CAN register offsets.
+//
+//*****************************************************************************
+#define CAN_O_CTL 0x00000000 // CAN Control
+#define CAN_O_STS 0x00000004 // CAN Status
+#define CAN_O_ERR 0x00000008 // CAN Error Counter
+#define CAN_O_BIT 0x0000000C // CAN Bit Timing
+#define CAN_O_INT 0x00000010 // CAN Interrupt
+#define CAN_O_TST 0x00000014 // CAN Test
+#define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler
+ // Extension
+#define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request
+#define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask
+#define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1
+#define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2
+#define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1
+#define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2
+#define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control
+#define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1
+#define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2
+#define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1
+#define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2
+#define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request
+#define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask
+#define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1
+#define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2
+#define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1
+#define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2
+#define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control
+#define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1
+#define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2
+#define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1
+#define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2
+#define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1
+#define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2
+#define CAN_O_NWDA1 0x00000120 // CAN New Data 1
+#define CAN_O_NWDA2 0x00000124 // CAN New Data 2
+#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
+#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
+#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
+#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
+#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
+#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
+#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
+#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
+#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable
+#define CAN_CTL_INIT 0x00000001 // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF 0x00000080 // Bus-Off Status
+#define CAN_STS_EWARN 0x00000040 // Warning Status
+#define CAN_STS_EPASS 0x00000020 // Error Passive
+#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully
+#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
+ // Successfully
+#define CAN_STS_LEC_M 0x00000007 // Last Error Code
+#define CAN_STS_LEC_NONE 0x00000000 // No Error
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
+#define CAN_STS_LEC_FORM 0x00000002 // Format Error
+#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
+#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
+#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP 0x00008000 // Received Error Passive
+#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter
+#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter
+#define CAN_ERR_REC_S 8
+#define CAN_ERR_TEC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler
+#define CAN_BIT_TSEG2_S 12
+#define CAN_BIT_TSEG1_S 8
+#define CAN_BIT_SJW_S 6
+#define CAN_BIT_BRP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier
+#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX 0x00000080 // Receive Observation
+#define CAN_TST_TX_M 0x00000060 // Transmit Control
+#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control
+#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point
+#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low
+#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High
+#define CAN_TST_LBACK 0x00000010 // Loopback Mode
+#define CAN_TST_SILENT 0x00000008 // Silent Mode
+#define CAN_TST_BASIC 0x00000004 // Basic Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension
+#define CAN_BRPE_BRPE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag
+#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number
+#define CAN_IF1CRQ_MNUM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read
+#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits
+#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data
+#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request
+#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
+#define CAN_IF1MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask
+#define CAN_IF1MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier
+#define CAN_IF1ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid
+#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier
+#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction
+#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier
+#define CAN_IF1ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data
+#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost
+#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending
+#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable
+#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request
+#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer
+#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code
+#define CAN_IF1MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag
+#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number
+#define CAN_IF2CRQ_MNUM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read
+#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits
+#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data
+#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request
+#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
+#define CAN_IF2MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask
+#define CAN_IF2MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier
+#define CAN_IF2ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid
+#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier
+#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction
+#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier
+#define CAN_IF2ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data
+#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost
+#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending
+#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable
+#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request
+#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer
+#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code
+#define CAN_IF2MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits
+#define CAN_NWDA1_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits
+#define CAN_NWDA2_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
+#define CAN_MSG1INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
+#define CAN_MSG2INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
+#define CAN_MSG1VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
+#define CAN_MSG2VAL_MSGVAL_S 0
+
+#endif // __HW_CAN_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_comp.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_comp.h
new file mode 100644
index 00000000..6853d616
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_comp.h
@@ -0,0 +1,213 @@
+//*****************************************************************************
+//
+// hw_comp.h - Macros used when accessing the comparator hardware.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_COMP_H__
+#define __HW_COMP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Comparator register offsets.
+//
+//*****************************************************************************
+#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked
+ // Interrupt Status
+#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt
+ // Status
+#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt
+ // Enable
+#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference
+ // Voltage Control
+#define COMP_O_ACSTAT0 0x00000020 // Analog Comparator Status 0
+#define COMP_O_ACCTL0 0x00000024 // Analog Comparator Control 0
+#define COMP_O_ACSTAT1 0x00000040 // Analog Comparator Status 1
+#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1
+#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2
+#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2
+#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral
+ // Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
+ // Status
+#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
+ // Status
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status
+#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable
+#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_PP register.
+//
+//*****************************************************************************
+#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present
+#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present
+#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present
+#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present
+#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present
+#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present
+
+#endif // __HW_COMP_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_eeprom.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_eeprom.h
new file mode 100644
index 00000000..9b6ea73d
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_eeprom.h
@@ -0,0 +1,220 @@
+//*****************************************************************************
+//
+// hw_eeprom.h - Macros used when accessing the EEPROM controller.
+//
+// Copyright (c) 2011-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EEPROM_H__
+#define __HW_EEPROM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the EEPROM register offsets.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information
+#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block
+#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset
+#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write
+#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment
+#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status
+#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and
+ // Status
+#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock
+#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection
+#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password
+#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password
+#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password
+#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt
+#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide
+#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase
+#define EEPROM_PP 0x400AFFC0 // EEPROM Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESIZE register.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words
+#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks
+#define EEPROM_EESIZE_WORDCNT_S 0
+#define EEPROM_EESIZE_BLKCNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
+//
+//*****************************************************************************
+#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block
+#define EEPROM_EEBLOCK_BLOCK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEOFFSET
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEOFFSET_OFFSET_M \
+ 0x0000000F // Current Address Offset
+#define EEPROM_EEOFFSET_OFFSET_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWR register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data
+#define EEPROM_EERDWR_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWRINC
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWRINC_VALUE_M \
+ 0xFFFFFFFF // EEPROM Read or Write Data with
+ // Increment
+#define EEPROM_EERDWRINC_VALUE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDONE register.
+//
+//*****************************************************************************
+#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working
+#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase
+#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy
+#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission
+#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy
+#define EEPROM_EEDONE_INVPL 0x00000100 // Invalid Program Voltage Level
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESUPP register.
+//
+//*****************************************************************************
+#define EEPROM_EESUPP_START 0x00000001 // Start Erase
+#define EEPROM_EESUPP_EREQ 0x00000002 // Erase Required
+#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried
+#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEUNLOCK
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEUNLOCK_UNLOCK_M \
+ 0xFFFFFFFF // EEPROM Unlock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPROT register.
+//
+//*****************************************************************************
+#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control
+#define EEPROM_EEPROT_PROT_RWNPW \
+ 0x00000000 // This setting is the default. If
+ // there is no password, the block
+ // is not protected and is readable
+ // and writable
+#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the
+ // block is readable or writable
+ // only when unlocked
+#define EEPROM_EEPROT_PROT_RONPW \
+ 0x00000002 // If there is no password, the
+ // block is readable, not writable
+#define EEPROM_EEPROT_ACC 0x00000008 // Access Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS0_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS1_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS2_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEINT register.
+//
+//*****************************************************************************
+#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDBGME register.
+//
+//*****************************************************************************
+#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase
+#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key
+#define EEPROM_EEDBGME_KEY_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_PP register.
+//
+//*****************************************************************************
+#define EEPROM_PP_SIZE_M 0x0000001F // EEPROM Size
+#define EEPROM_PP_SIZE_S 0
+
+#endif // __HW_EEPROM_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_fan.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_fan.h
new file mode 100644
index 00000000..115bf116
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_fan.h
@@ -0,0 +1,49 @@
+//*****************************************************************************
+//
+// hw_fan.h - Macros used when accessing the fan control hardware.
+//
+// Copyright (c) 2010-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FAN_H__
+#define __HW_FAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Fan Control register offsets.
+//
+//*****************************************************************************
+
+#endif // __HW_FAN_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_flash.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_flash.h
new file mode 100644
index 00000000..e17c9b46
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_flash.h
@@ -0,0 +1,298 @@
+//*****************************************************************************
+//
+// hw_flash.h - Macros used when accessing the flash controller.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FLASH_H__
+#define __HW_FLASH_H__
+
+//*****************************************************************************
+//
+// The following are defines for the FLASH register offsets.
+//
+//*****************************************************************************
+#define FLASH_FMA 0x400FD000 // Flash Memory Address
+#define FLASH_FMD 0x400FD004 // Flash Memory Data
+#define FLASH_FMC 0x400FD008 // Flash Memory Control
+#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt
+ // Status
+#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask
+#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked
+ // Interrupt Status and Clear
+#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2
+#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
+#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n
+#define FLASH_FSIZE 0x400FDFC0 // Flash Size
+#define FLASH_SSIZE 0x400FDFC4 // SRAM Size
+#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map
+#define FLASH_RMCTL 0x400FE0F0 // ROM Control
+#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration
+#define FLASH_USERREG0 0x400FE1E0 // User Register 0
+#define FLASH_USERREG1 0x400FE1E4 // User Register 1
+#define FLASH_USERREG2 0x400FE1E8 // User Register 2
+#define FLASH_USERREG3 0x400FE1EC // User Register 3
+#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read
+ // Enable 0
+#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read
+ // Enable 1
+#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read
+ // Enable 2
+#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
+ // Enable 3
+#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
+ // Enable 0
+#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
+ // Enable 1
+#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program
+ // Enable 2
+#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
+ // Enable 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset
+#define FLASH_FMA_OFFSET_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
+#define FLASH_FMD_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
+#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status
+#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status
+#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
+ // Status
+#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status
+#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
+#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
+#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
+#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
+#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
+ // Status and Clear
+#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
+ // Clear
+#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FSIZE register.
+//
+//*****************************************************************************
+#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
+#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash
+#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash
+#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
+#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
+#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash
+#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
+#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash
+#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_SSIZE register.
+//
+//*****************************************************************************
+#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
+#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM
+#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM
+#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM
+#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM
+#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
+#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM
+#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM
+#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
+#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
+//
+//*****************************************************************************
+#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
+#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
+#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
+#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
+#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
+#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
+#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
+#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
+#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
+#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
+#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1
+#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2
+#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
+#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4
+#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5
+#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6
+#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
+#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
+#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select
+#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
+#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE 0x00000800
+#define FLASH_ERASE_SIZE 0x00000400
+
+#endif // __HW_FLASH_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_gpio.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_gpio.h
new file mode 100644
index 00000000..7d1da195
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_gpio.h
@@ -0,0 +1,125 @@
+//*****************************************************************************
+//
+// hw_gpio.h - Defines and Macros for GPIO hardware.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_GPIO_H__
+#define __HW_GPIO_H__
+
+//*****************************************************************************
+//
+// The following are defines for the GPIO register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_DATA 0x00000000 // GPIO Data
+#define GPIO_O_DIR 0x00000400 // GPIO Direction
+#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
+#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
+#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
+#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
+#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
+#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
+#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
+#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
+#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
+#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
+#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
+#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
+#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
+#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
+#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
+#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
+#define GPIO_O_LOCK 0x00000520 // GPIO Lock
+#define GPIO_O_CR 0x00000524 // GPIO Commit
+#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
+#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
+#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
+#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
+#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_IM register.
+//
+//*****************************************************************************
+#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
+#define GPIO_IM_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_RIS register.
+//
+//*****************************************************************************
+#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
+#define GPIO_RIS_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_MIS register.
+//
+//*****************************************************************************
+#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
+#define GPIO_MIS_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_ICR register.
+//
+//*****************************************************************************
+#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
+#define GPIO_ICR_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
+#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
+ // and may be modified
+#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
+ // and may not be modified
+#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_SI register.
+//
+//*****************************************************************************
+#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
+
+#endif // __HW_GPIO_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_hibernate.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_hibernate.h
new file mode 100644
index 00000000..8b4f3421
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_hibernate.h
@@ -0,0 +1,188 @@
+//*****************************************************************************
+//
+// hw_hibernate.h - Defines and Macros for the Hibernation module.
+//
+// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_HIBERNATE_H__
+#define __HW_HIBERNATE_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Hibernation module register addresses.
+//
+//*****************************************************************************
+#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
+#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
+#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
+#define HIB_CTL 0x400FC010 // Hibernation Control
+#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
+#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
+#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
+ // Status
+#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
+#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
+#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
+#define HIB_DATA 0x400FC030 // Hibernation Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
+#define HIB_RTCC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
+#define HIB_RTCM0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
+#define HIB_RTCLD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
+#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
+#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
+#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
+ // Comparator
+#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
+#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
+#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
+#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
+#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
+#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
+#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
+#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
+#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
+#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
+#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
+#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
+ // Interrupt Mask
+#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
+ // Mask
+#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
+ // Interrupt Status
+#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
+ // Status
+#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
+ // Interrupt Status
+#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
+ // Interrupt Status
+#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Status
+#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Status
+#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
+ // Interrupt Clear
+#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Clear
+#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Clear
+#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
+#define HIB_RTCT_TRIM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCSS register.
+//
+//*****************************************************************************
+#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
+#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
+#define HIB_RTCSS_RTCSSM_S 16
+#define HIB_RTCSS_RTCSSC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
+#define HIB_DATA_RTD_S 0
+
+#endif // __HW_HIBERNATE_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_i2c.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_i2c.h
new file mode 100644
index 00000000..77864716
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_i2c.h
@@ -0,0 +1,293 @@
+//*****************************************************************************
+//
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_I2C_H__
+#define __HW_I2C_H__
+
+//*****************************************************************************
+//
+// The following are defines for the I2C register offsets.
+//
+//*****************************************************************************
+#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
+#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
+#define I2C_O_MDR 0x00000008 // I2C Master Data
+#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
+#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
+#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
+#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
+ // Status
+#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
+#define I2C_O_MCR 0x00000020 // I2C Master Configuration
+#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
+ // Count
+#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
+#define I2C_O_MCR2 0x00000038 // I2C Master Configuration 2
+#define I2C_O_SOAR 0x00000800 // I2C Slave Own Address
+#define I2C_O_SCSR 0x00000804 // I2C Slave Control/Status
+#define I2C_O_SDR 0x00000808 // I2C Slave Data
+#define I2C_O_SIMR 0x0000080C // I2C Slave Interrupt Mask
+#define I2C_O_SRIS 0x00000810 // I2C Slave Raw Interrupt Status
+#define I2C_O_SMIS 0x00000814 // I2C Slave Masked Interrupt
+ // Status
+#define I2C_O_SICR 0x00000818 // I2C Slave Interrupt Clear
+#define I2C_O_SOAR2 0x0000081C // I2C Slave Own Address 2
+#define I2C_O_SACKCTL 0x00000820 // I2C Slave ACK Control
+#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
+#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
+#define I2C_MSA_RS 0x00000001 // Receive not send
+#define I2C_MSA_SA_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
+#define I2C_MCS_HS 0x00000010 // High-Speed Enable
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
+#define I2C_MCS_STOP 0x00000004 // Generate STOP
+#define I2C_MCS_ERROR 0x00000002 // Error
+#define I2C_MCS_START 0x00000002 // Generate START
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
+#define I2C_MTPR_TPR_M 0x0000007F // Timer Period
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
+#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
+ // Status
+#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
+ // Status
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
+#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
+//
+//*****************************************************************************
+#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
+#define I2C_MCLKOCNT_CNTL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBMON register.
+//
+//*****************************************************************************
+#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
+#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR2 register.
+//
+//*****************************************************************************
+#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width
+#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass
+#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock
+#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks
+#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks
+#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks
+#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks
+#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks
+#define I2C_MCR2_GFPW_32 0x00000070 // 32 clocks
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
+#define I2C_SCSR_DA 0x00000001 // Device Active
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR2 register.
+//
+//*****************************************************************************
+#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
+#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
+#define I2C_SOAR2_OAR2_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SACKCTL register.
+//
+//*****************************************************************************
+#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
+#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PP register.
+//
+//*****************************************************************************
+#define I2C_PP_HS 0x00000001 // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PC register.
+//
+//*****************************************************************************
+#define I2C_PC_HS 0x00000001 // High-Speed Capable
+
+#endif // __HW_I2C_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_ints.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_ints.h
new file mode 100644
index 00000000..a949e4f2
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_ints.h
@@ -0,0 +1,344 @@
+//*****************************************************************************
+//
+// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series
+// MCUs.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_INTS_H__
+#define __HW_INTS_H__
+
+//*****************************************************************************
+//
+// The following are defines for the fault assignments.
+//
+//*****************************************************************************
+#define FAULT_NMI 2 // NMI fault
+#define FAULT_HARD 3 // Hard fault
+#define FAULT_MPU 4 // MPU fault
+#define FAULT_BUS 5 // Bus fault
+#define FAULT_USAGE 6 // Usage fault
+#define FAULT_SVCALL 11 // SVCall
+#define FAULT_DEBUG 12 // Debug monitor
+#define FAULT_PENDSV 14 // PendSV
+#define FAULT_SYSTICK 15 // System Tick
+
+//*****************************************************************************
+//
+// Blizzard Class Interrupts
+//
+//*****************************************************************************
+#define INT_GPIOA_BLIZZARD 16 // GPIO Port A
+#define INT_GPIOB_BLIZZARD 17 // GPIO Port B
+#define INT_GPIOC_BLIZZARD 18 // GPIO Port C
+#define INT_GPIOD_BLIZZARD 19 // GPIO Port D
+#define INT_GPIOE_BLIZZARD 20 // GPIO Port E
+#define INT_UART0_BLIZZARD 21 // UART0
+#define INT_UART1_BLIZZARD 22 // UART1
+#define INT_SSI0_BLIZZARD 23 // SSI0
+#define INT_I2C0_BLIZZARD 24 // I2C0
+#define INT_PWM0_FAULT_BLIZZARD 25 // PWM0 Fault
+#define INT_PWM0_0_BLIZZARD 26 // PWM0 Generator 0
+#define INT_PWM0_1_BLIZZARD 27 // PWM0 Generator 1
+#define INT_PWM0_2_BLIZZARD 28 // PWM0 Generator 2
+#define INT_QEI0_BLIZZARD 29 // QEI0
+#define INT_ADC0SS0_BLIZZARD 30 // ADC0 Sequence 0
+#define INT_ADC0SS1_BLIZZARD 31 // ADC0 Sequence 1
+#define INT_ADC0SS2_BLIZZARD 32 // ADC0 Sequence 2
+#define INT_ADC0SS3_BLIZZARD 33 // ADC0 Sequence 3
+#define INT_WATCHDOG_BLIZZARD 34 // Watchdog Timers 0 and 1
+#define INT_TIMER0A_BLIZZARD 35 // 16/32-Bit Timer 0A
+#define INT_TIMER0B_BLIZZARD 36 // 16/32-Bit Timer 0B
+#define INT_TIMER1A_BLIZZARD 37 // 16/32-Bit Timer 1A
+#define INT_TIMER1B_BLIZZARD 38 // 16/32-Bit Timer 1B
+#define INT_TIMER2A_BLIZZARD 39 // 16/32-Bit Timer 2A
+#define INT_TIMER2B_BLIZZARD 40 // 16/32-Bit Timer 2B
+#define INT_COMP0_BLIZZARD 41 // Analog Comparator 0
+#define INT_COMP1_BLIZZARD 42 // Analog Comparator 1
+#define INT_COMP2_BLIZZARD 43 // Analog Comparator 2
+#define INT_SYSCTL_BLIZZARD 44 // System Control
+#define INT_FLASH_BLIZZARD 45 // Flash Memory Control and EEPROM
+ // Control
+#define INT_GPIOF_BLIZZARD 46 // GPIO Port F
+#define INT_GPIOG_BLIZZARD 47 // GPIO Port G
+#define INT_GPIOH_BLIZZARD 48 // GPIO Port H
+#define INT_UART2_BLIZZARD 49 // UART2
+#define INT_SSI1_BLIZZARD 50 // SSI1
+#define INT_TIMER3A_BLIZZARD 51 // Timer 3A
+#define INT_TIMER3B_BLIZZARD 52 // Timer 3B
+#define INT_I2C1_BLIZZARD 53 // I2C1
+#define INT_QEI1_BLIZZARD 54 // QEI1
+#define INT_CAN0_BLIZZARD 55 // CAN0
+#define INT_CAN1_BLIZZARD 56 // CAN1
+#define INT_HIBERNATE_BLIZZARD 59 // Hibernation Module
+#define INT_USB0_BLIZZARD 60 // USB
+#define INT_PWM0_3_BLIZZARD 61 // PWM Generator 3
+#define INT_UDMA_BLIZZARD 62 // uDMA Software
+#define INT_UDMAERR_BLIZZARD 63 // uDMA Error
+#define INT_ADC1SS0_BLIZZARD 64 // ADC1 Sequence 0
+#define INT_ADC1SS1_BLIZZARD 65 // ADC1 Sequence 1
+#define INT_ADC1SS2_BLIZZARD 66 // ADC1 Sequence 2
+#define INT_ADC1SS3_BLIZZARD 67 // ADC1 Sequence 3
+#define INT_GPIOJ_BLIZZARD 70 // GPIO Port J
+#define INT_GPIOK_BLIZZARD 71 // GPIO Port K
+#define INT_GPIOL_BLIZZARD 72 // GPIO Port L
+#define INT_SSI2_BLIZZARD 73 // SSI2
+#define INT_SSI3_BLIZZARD 74 // SSI3
+#define INT_UART3_BLIZZARD 75 // UART3
+#define INT_UART4_BLIZZARD 76 // UART4
+#define INT_UART5_BLIZZARD 77 // UART5
+#define INT_UART6_BLIZZARD 78 // UART6
+#define INT_UART7_BLIZZARD 79 // UART7
+#define INT_I2C2_BLIZZARD 84 // I2C2
+#define INT_I2C3_BLIZZARD 85 // I2C3
+#define INT_TIMER4A_BLIZZARD 86 // 16/32-Bit Timer 4A
+#define INT_TIMER4B_BLIZZARD 87 // 16/32-Bit Timer 4B
+#define INT_TIMER5A_BLIZZARD 108 // 16/32-Bit Timer 5A
+#define INT_TIMER5B_BLIZZARD 109 // 16/32-Bit Timer 5B
+#define INT_WTIMER0A_BLIZZARD 110 // 32/64-Bit Timer 0A
+#define INT_WTIMER0B_BLIZZARD 111 // 32/64-Bit Timer 0B
+#define INT_WTIMER1A_BLIZZARD 112 // 32/64-Bit Timer 1A
+#define INT_WTIMER1B_BLIZZARD 113 // 32/64-Bit Timer 1B
+#define INT_WTIMER2A_BLIZZARD 114 // 32/64-Bit Timer 2A
+#define INT_WTIMER2B_BLIZZARD 115 // 32/64-Bit Timer 2B
+#define INT_WTIMER3A_BLIZZARD 116 // 32/64-Bit Timer 3A
+#define INT_WTIMER3B_BLIZZARD 117 // 32/64-Bit Timer 3B
+#define INT_WTIMER4A_BLIZZARD 118 // 32/64-Bit Timer 4A
+#define INT_WTIMER4B_BLIZZARD 119 // 32/64-Bit Timer 4B
+#define INT_WTIMER5A_BLIZZARD 120 // 32/64-Bit Timer 5A
+#define INT_WTIMER5B_BLIZZARD 121 // 32/64-Bit Timer 5B
+#define INT_SYSEXC_BLIZZARD 122 // System Exception (imprecise)
+#define INT_PECI0_BLIZZARD 123 // PECI 0
+#define INT_LPC0_BLIZZARD 124 // LPC 0
+#define INT_I2C4_BLIZZARD 125 // I2C4
+#define INT_I2C5_BLIZZARD 126 // I2C5
+#define INT_GPIOM_BLIZZARD 127 // GPIO Port M
+#define INT_GPION_BLIZZARD 128 // GPIO Port N
+#define INT_FAN0_BLIZZARD 130 // FAN 0
+#define INT_GPIOP0_BLIZZARD 132 // GPIO Port P (Summary or P0)
+#define INT_GPIOP1_BLIZZARD 133 // GPIO Port P1
+#define INT_GPIOP2_BLIZZARD 134 // GPIO Port P2
+#define INT_GPIOP3_BLIZZARD 135 // GPIO Port P3
+#define INT_GPIOP4_BLIZZARD 136 // GPIO Port P4
+#define INT_GPIOP5_BLIZZARD 137 // GPIO Port P5
+#define INT_GPIOP6_BLIZZARD 138 // GPIO Port P6
+#define INT_GPIOP7_BLIZZARD 139 // GPIO Port P7
+#define INT_GPIOQ0_BLIZZARD 140 // GPIO Port Q (Summary or Q0)
+#define INT_GPIOQ1_BLIZZARD 141 // GPIO Port Q1
+#define INT_GPIOQ2_BLIZZARD 142 // GPIO Port Q2
+#define INT_GPIOQ3_BLIZZARD 143 // GPIO Port Q3
+#define INT_GPIOQ4_BLIZZARD 144 // GPIO Port Q4
+#define INT_GPIOQ5_BLIZZARD 145 // GPIO Port Q5
+#define INT_GPIOQ6_BLIZZARD 146 // GPIO Port Q6
+#define INT_GPIOQ7_BLIZZARD 147 // GPIO Port Q7
+#define INT_PWM1_0_BLIZZARD 150 // PWM1 Generator 0
+#define INT_PWM1_1_BLIZZARD 151 // PWM1 Generator 1
+#define INT_PWM1_2_BLIZZARD 152 // PWM1 Generator 2
+#define INT_PWM1_3_BLIZZARD 153 // PWM1 Generator 3
+#define INT_PWM1_FAULT_BLIZZARD 154 // PWM1 Fault
+#define NUM_INTERRUPTS_BLIZZARD 155
+
+//*****************************************************************************
+//
+// Blizzard Interrupt Class Definition
+//
+//*****************************************************************************
+#if defined(TARGET_IS_BLIZZARD_RA1) || defined(TARGET_IS_BLIZZARD_RA2) || \
+ defined(TARGET_IS_BLIZZARD_RA3) || defined(TARGET_IS_BLIZZARD_RB0) || \
+ defined(TARGET_IS_BLIZZARD_RB1) || defined(PART_TM4C1230C3PM) || \
+ defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \
+ defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \
+ defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \
+ defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \
+ defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \
+ defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \
+ defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \
+ defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \
+ defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \
+ defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \
+ defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \
+ defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \
+ defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \
+ defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \
+ defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \
+ defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \
+ defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \
+ defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \
+ defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \
+ defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \
+ defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \
+ defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \
+ defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \
+ defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \
+ defined(PART_TM4C123GH6ZRB)
+#define INT_RESOLVE(intname, class) intname##BLIZZARD
+#else
+#define INT_DEVICE_CLASS "UNKNOWN"
+#endif
+
+//*****************************************************************************
+//
+// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name.
+//
+//*****************************************************************************
+#define INT_CONCAT(intname, class) INT_RESOLVE(intname, class)
+
+//*****************************************************************************
+//
+// The following are defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS)
+#define INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS)
+#define INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS)
+#define INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS)
+#define INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS)
+#define INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS)
+#define INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS)
+#define INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS)
+#define INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS)
+#define INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS)
+#define INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS)
+#define INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS)
+#define INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS)
+#define INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS)
+#define INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS)
+#define INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS)
+#define INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS)
+#define INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS)
+#define INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS)
+#define INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS)
+#define INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS)
+#define INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS)
+#define INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS)
+#define INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS)
+#define INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS)
+#define INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS)
+#define INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS)
+#define INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS)
+#define INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS)
+#define INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS)
+#define INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS)
+#define INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS)
+#define INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS)
+#define INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS)
+#define INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS)
+#define INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS)
+#define INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS)
+#define INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS)
+#define INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS)
+#define INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS)
+#define INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS)
+#define INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS)
+#define INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS)
+#define INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS)
+#define INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS)
+#define INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS)
+#define INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS)
+#define INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS)
+#define INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS)
+#define INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS)
+#define INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS)
+#define INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS)
+#define INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS)
+#define INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS)
+#define INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS)
+#define INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS)
+#define INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS)
+#define INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS)
+#define INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS)
+#define INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS)
+#define INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS)
+#define INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS)
+#define INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS)
+#define INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS)
+#define INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS)
+#define INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS)
+#define INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS)
+#define INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS)
+#define INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS)
+#define INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS)
+#define INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS)
+#define INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS)
+#define INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS)
+#define INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS)
+#define INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS)
+#define INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS)
+#define INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS)
+#define INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS)
+#define INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS)
+#define INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS)
+#define INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS)
+#define INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS)
+#define INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS)
+#define INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS)
+#define INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS)
+#define INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS)
+#define INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS)
+#define INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS)
+#define INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS)
+#define INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS)
+#define INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS)
+#define INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS)
+#define INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS)
+#define INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS)
+#define INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS)
+#define INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS)
+#define INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS)
+#define INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS)
+#define INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS)
+#define INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS)
+#define INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS)
+#define INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS)
+#define INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS)
+#define INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS)
+
+//*****************************************************************************
+//
+// The following are defines for the total number of interrupts.
+//
+//*****************************************************************************
+#define NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS)
+
+//*****************************************************************************
+//
+// The following are defines for the total number of priority levels.
+//
+//*****************************************************************************
+#define NUM_PRIORITY 8
+#define NUM_PRIORITY_BITS 3
+
+#endif // __HW_INTS_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_lpc.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_lpc.h
new file mode 100644
index 00000000..2f96cefb
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_lpc.h
@@ -0,0 +1,49 @@
+//*****************************************************************************
+//
+// hw_lpc.h - Macros used when accessing the LPC hardware.
+//
+// Copyright (c) 2010-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_LPC_H__
+#define __HW_LPC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the LPC register addresses.
+//
+//*****************************************************************************
+
+#endif // __HW_LPC_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_memmap.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_memmap.h
new file mode 100644
index 00000000..446c5659
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_memmap.h
@@ -0,0 +1,129 @@
+//*****************************************************************************
+//
+// hw_memmap.h - Macros defining the memory map of the device.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_MEMMAP_H__
+#define __HW_MEMMAP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the base address of the memories and
+// peripherals.
+//
+//*****************************************************************************
+#define FLASH_BASE 0x00000000 // FLASH memory
+#define SRAM_BASE 0x20000000 // SRAM memory
+#define WATCHDOG0_BASE 0x40000000 // Watchdog0
+#define WATCHDOG1_BASE 0x40001000 // Watchdog1
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
+#define SSI0_BASE 0x40008000 // SSI0
+#define SSI1_BASE 0x40009000 // SSI1
+#define SSI2_BASE 0x4000A000 // SSI2
+#define SSI3_BASE 0x4000B000 // SSI3
+#define UART0_BASE 0x4000C000 // UART0
+#define UART1_BASE 0x4000D000 // UART1
+#define UART2_BASE 0x4000E000 // UART2
+#define UART3_BASE 0x4000F000 // UART3
+#define UART4_BASE 0x40010000 // UART4
+#define UART5_BASE 0x40011000 // UART5
+#define UART6_BASE 0x40012000 // UART6
+#define UART7_BASE 0x40013000 // UART7
+#define I2C0_BASE 0x40020000 // I2C0
+#define I2C1_BASE 0x40021000 // I2C1
+#define I2C2_BASE 0x40022000 // I2C2
+#define I2C3_BASE 0x40023000 // I2C3
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
+#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
+#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
+#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
+#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
+#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
+#define QEI0_BASE 0x4002C000 // QEI0
+#define QEI1_BASE 0x4002D000 // QEI1
+#define TIMER0_BASE 0x40030000 // Timer0
+#define TIMER1_BASE 0x40031000 // Timer1
+#define TIMER2_BASE 0x40032000 // Timer2
+#define TIMER3_BASE 0x40033000 // Timer3
+#define TIMER4_BASE 0x40034000 // Timer4
+#define TIMER5_BASE 0x40035000 // Timer5
+#define WTIMER0_BASE 0x40036000 // Wide Timer0
+#define WTIMER1_BASE 0x40037000 // Wide Timer1
+#define ADC0_BASE 0x40038000 // ADC0
+#define ADC1_BASE 0x40039000 // ADC1
+#define COMP_BASE 0x4003C000 // Analog comparators
+#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
+#define CAN0_BASE 0x40040000 // CAN0
+#define CAN1_BASE 0x40041000 // CAN1
+#define WTIMER2_BASE 0x4004C000 // Wide Timer2
+#define WTIMER3_BASE 0x4004D000 // Wide Timer3
+#define WTIMER4_BASE 0x4004E000 // Wide Timer4
+#define WTIMER5_BASE 0x4004F000 // Wide Timer5
+#define USB0_BASE 0x40050000 // USB 0 Controller
+#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
+#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
+#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
+#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
+#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
+#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
+#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
+#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
+#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
+#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
+#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
+#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
+#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
+#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
+#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
+#define EEPROM_BASE 0x400AF000 // EEPROM memory
+#define I2C4_BASE 0x400C0000 // I2C4
+#define I2C5_BASE 0x400C1000 // I2C5
+#define SYSEXC_BASE 0x400F9000 // System Exception Module
+#define HIB_BASE 0x400FC000 // Hibernation Module
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
+#define SYSCTL_BASE 0x400FE000 // System Control
+#define UDMA_BASE 0x400FF000 // uDMA Controller
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
+
+#endif // __HW_MEMMAP_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_nvic.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_nvic.h
new file mode 100644
index 00000000..ffcc471c
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_nvic.h
@@ -0,0 +1,1415 @@
+//*****************************************************************************
+//
+// hw_nvic.h - Macros used when accessing the NVIC hardware.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_NVIC_H__
+#define __HW_NVIC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_ACTLR 0xE000E008 // Auxiliary Control
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status
+ // Register
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
+#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable
+#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable
+#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable
+#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable
+#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable
+#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable
+#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable
+#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable
+#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable
+#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable
+#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending
+#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending
+#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending
+#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending
+#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending
+#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending
+#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending
+#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending
+#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending
+#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending
+#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit
+#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit
+#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit
+#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit
+#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit
+#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority
+#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority
+#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority
+#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority
+#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority
+#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority
+#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority
+#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority
+#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority
+#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority
+#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority
+#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority
+#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority
+#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority
+#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority
+#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority
+#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority
+#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority
+#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority
+#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority
+#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority
+#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority
+#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority
+#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority
+#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority
+#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority
+#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority
+#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority
+#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority
+#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority
+#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority
+#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority
+#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority
+#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority
+#define NVIC_PRI34 0xE000E488 // Interrupt 136-138 Priority
+#define NVIC_CPUID 0xE000ED00 // CPU ID Base
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset
+#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset
+ // Control
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control
+#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1
+#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2
+#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
+#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address
+#define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size
+#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1
+#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size
+ // Alias 1
+#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2
+#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size
+ // Alias 2
+#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3
+#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size
+ // Alias 3
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt
+#define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control
+#define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address
+#define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating
+ // Point
+#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL
+#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple
+ // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN2 register.
+//
+//*****************************************************************************
+#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN3 register.
+//
+//*****************************************************************************
+#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN4 register.
+//
+//*****************************************************************************
+#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS2 register.
+//
+//*****************************************************************************
+#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS3 register.
+//
+//*****************************************************************************
+#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS4 register.
+//
+//*****************************************************************************
+#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND2 register.
+//
+//*****************************************************************************
+#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND3 register.
+//
+//*****************************************************************************
+#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND4 register.
+//
+//*****************************************************************************
+#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND2 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND3 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND4 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE4 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S 29
+#define NVIC_PRI0_INT2_S 21
+#define NVIC_PRI0_INT1_S 13
+#define NVIC_PRI0_INT0_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S 29
+#define NVIC_PRI1_INT6_S 21
+#define NVIC_PRI1_INT5_S 13
+#define NVIC_PRI1_INT4_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S 29
+#define NVIC_PRI2_INT10_S 21
+#define NVIC_PRI2_INT9_S 13
+#define NVIC_PRI2_INT8_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S 29
+#define NVIC_PRI3_INT14_S 21
+#define NVIC_PRI3_INT13_S 13
+#define NVIC_PRI3_INT12_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S 29
+#define NVIC_PRI4_INT18_S 21
+#define NVIC_PRI4_INT17_S 13
+#define NVIC_PRI4_INT16_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S 29
+#define NVIC_PRI5_INT22_S 21
+#define NVIC_PRI5_INT21_S 13
+#define NVIC_PRI5_INT20_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S 29
+#define NVIC_PRI6_INT26_S 21
+#define NVIC_PRI6_INT25_S 13
+#define NVIC_PRI6_INT24_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S 29
+#define NVIC_PRI7_INT30_S 21
+#define NVIC_PRI7_INT29_S 13
+#define NVIC_PRI7_INT28_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S 29
+#define NVIC_PRI8_INT34_S 21
+#define NVIC_PRI8_INT33_S 13
+#define NVIC_PRI8_INT32_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S 29
+#define NVIC_PRI9_INT38_S 21
+#define NVIC_PRI9_INT37_S 13
+#define NVIC_PRI9_INT36_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S 29
+#define NVIC_PRI10_INT42_S 21
+#define NVIC_PRI10_INT41_S 13
+#define NVIC_PRI10_INT40_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S 29
+#define NVIC_PRI11_INT46_S 21
+#define NVIC_PRI11_INT45_S 13
+#define NVIC_PRI11_INT44_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S 29
+#define NVIC_PRI12_INT50_S 21
+#define NVIC_PRI12_INT49_S 13
+#define NVIC_PRI12_INT48_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S 29
+#define NVIC_PRI13_INT54_S 21
+#define NVIC_PRI13_INT53_S 13
+#define NVIC_PRI13_INT52_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI14 register.
+//
+//*****************************************************************************
+#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask
+#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask
+#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask
+#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask
+#define NVIC_PRI14_INTD_S 29
+#define NVIC_PRI14_INTC_S 21
+#define NVIC_PRI14_INTB_S 13
+#define NVIC_PRI14_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI15 register.
+//
+//*****************************************************************************
+#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask
+#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask
+#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask
+#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask
+#define NVIC_PRI15_INTD_S 29
+#define NVIC_PRI15_INTC_S 21
+#define NVIC_PRI15_INTB_S 13
+#define NVIC_PRI15_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI16 register.
+//
+//*****************************************************************************
+#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask
+#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask
+#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask
+#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask
+#define NVIC_PRI16_INTD_S 29
+#define NVIC_PRI16_INTC_S 21
+#define NVIC_PRI16_INTB_S 13
+#define NVIC_PRI16_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI17 register.
+//
+//*****************************************************************************
+#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask
+#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask
+#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask
+#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask
+#define NVIC_PRI17_INTD_S 29
+#define NVIC_PRI17_INTC_S 21
+#define NVIC_PRI17_INTB_S 13
+#define NVIC_PRI17_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI18 register.
+//
+//*****************************************************************************
+#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask
+#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask
+#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask
+#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask
+#define NVIC_PRI18_INTD_S 29
+#define NVIC_PRI18_INTC_S 21
+#define NVIC_PRI18_INTB_S 13
+#define NVIC_PRI18_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI19 register.
+//
+//*****************************************************************************
+#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask
+#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask
+#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask
+#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask
+#define NVIC_PRI19_INTD_S 29
+#define NVIC_PRI19_INTC_S 21
+#define NVIC_PRI19_INTB_S 13
+#define NVIC_PRI19_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI20 register.
+//
+//*****************************************************************************
+#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask
+#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask
+#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask
+#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask
+#define NVIC_PRI20_INTD_S 29
+#define NVIC_PRI20_INTC_S 21
+#define NVIC_PRI20_INTB_S 13
+#define NVIC_PRI20_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI21 register.
+//
+//*****************************************************************************
+#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask
+#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask
+#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask
+#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask
+#define NVIC_PRI21_INTD_S 29
+#define NVIC_PRI21_INTC_S 21
+#define NVIC_PRI21_INTB_S 13
+#define NVIC_PRI21_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI22 register.
+//
+//*****************************************************************************
+#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask
+#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask
+#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask
+#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask
+#define NVIC_PRI22_INTD_S 29
+#define NVIC_PRI22_INTC_S 21
+#define NVIC_PRI22_INTB_S 13
+#define NVIC_PRI22_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI23 register.
+//
+//*****************************************************************************
+#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask
+#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask
+#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask
+#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask
+#define NVIC_PRI23_INTD_S 29
+#define NVIC_PRI23_INTC_S 21
+#define NVIC_PRI23_INTB_S 13
+#define NVIC_PRI23_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI24 register.
+//
+//*****************************************************************************
+#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask
+#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask
+#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask
+#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask
+#define NVIC_PRI24_INTD_S 29
+#define NVIC_PRI24_INTC_S 21
+#define NVIC_PRI24_INTB_S 13
+#define NVIC_PRI24_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI25 register.
+//
+//*****************************************************************************
+#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask
+#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask
+#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask
+#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask
+#define NVIC_PRI25_INTD_S 29
+#define NVIC_PRI25_INTC_S 21
+#define NVIC_PRI25_INTB_S 13
+#define NVIC_PRI25_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI26 register.
+//
+//*****************************************************************************
+#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask
+#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask
+#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask
+#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask
+#define NVIC_PRI26_INTD_S 29
+#define NVIC_PRI26_INTC_S 21
+#define NVIC_PRI26_INTB_S 13
+#define NVIC_PRI26_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI27 register.
+//
+//*****************************************************************************
+#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask
+#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask
+#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask
+#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask
+#define NVIC_PRI27_INTD_S 29
+#define NVIC_PRI27_INTC_S 21
+#define NVIC_PRI27_INTB_S 13
+#define NVIC_PRI27_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI28 register.
+//
+//*****************************************************************************
+#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask
+#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask
+#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask
+#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask
+#define NVIC_PRI28_INTD_S 29
+#define NVIC_PRI28_INTC_S 21
+#define NVIC_PRI28_INTB_S 13
+#define NVIC_PRI28_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI29 register.
+//
+//*****************************************************************************
+#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask
+#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask
+#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask
+#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask
+#define NVIC_PRI29_INTD_S 29
+#define NVIC_PRI29_INTC_S 21
+#define NVIC_PRI29_INTB_S 13
+#define NVIC_PRI29_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI30 register.
+//
+//*****************************************************************************
+#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask
+#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask
+#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask
+#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask
+#define NVIC_PRI30_INTD_S 29
+#define NVIC_PRI30_INTC_S 21
+#define NVIC_PRI30_INTB_S 13
+#define NVIC_PRI30_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI31 register.
+//
+//*****************************************************************************
+#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask
+#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask
+#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask
+#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask
+#define NVIC_PRI31_INTD_S 29
+#define NVIC_PRI31_INTC_S 21
+#define NVIC_PRI31_INTB_S 13
+#define NVIC_PRI31_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI32 register.
+//
+//*****************************************************************************
+#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask
+#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask
+#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask
+#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask
+#define NVIC_PRI32_INTD_S 29
+#define NVIC_PRI32_INTC_S 21
+#define NVIC_PRI32_INTB_S 13
+#define NVIC_PRI32_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI33 register.
+//
+//*****************************************************************************
+#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
+ // [4n+3]
+#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
+ // [4n+2]
+#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
+ // [4n+1]
+#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
+ // [4n]
+#define NVIC_PRI33_INTD_S 29
+#define NVIC_PRI33_INTC_S 21
+#define NVIC_PRI33_INTB_S 13
+#define NVIC_PRI33_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI34 register.
+//
+//*****************************************************************************
+#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
+ // [4n+3]
+#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
+ // [4n+2]
+#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
+ // [4n+1]
+#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
+ // [4n]
+#define NVIC_PRI34_INTD_S 29
+#define NVIC_PRI34_INTC_S 21
+#define NVIC_PRI34_INTB_S 13
+#define NVIC_PRI34_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code
+#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number
+#define NVIC_CPUID_CON_M 0x000F0000 // Constant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number
+#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor
+#define NVIC_CPUID_REV_M 0x0000000F // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+ 0x00002000 // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+ 0x00003000 // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+ 0x00004000 // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+ 0x00005000 // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+ 0x00006000 // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+ 0x0000B000 // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+ 0x0000E000 // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+ 0x0000F000 // SysTick
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception
+ // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and
+ // Fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S 21
+#define NVIC_SYS_PRI1_BUS_S 13
+#define NVIC_SYS_PRI1_MEM_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S 29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S 29
+#define NVIC_SYS_PRI3_PENDSV_S 21
+#define NVIC_SYS_PRI3_DEBUG_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+ 0x00001000 // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage
+ // Fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy
+ // State Preservation
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address
+ // Register Valid
+#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on
+ // Floating-Point Lazy State
+ // Preservation
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPAC register.
+//
+//*****************************************************************************
+#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access
+ // Privilege
+#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied
+#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only
+#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access
+#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access
+ // Privilege
+#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied
+#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only
+#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE_ADDR_S 5
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE1_ADDR_S 5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE2_ADDR_S 5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE3_ADDR_S 5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCC register.
+//
+//*****************************************************************************
+#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation
+ // Enable
+#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable
+#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready
+#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready
+#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready
+#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready
+#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode
+#define NVIC_FPCC_USER 0x00000002 // User Privilege Level
+#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCA register.
+//
+//*****************************************************************************
+#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address
+#define NVIC_FPCA_ADDRESS_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPDSC register.
+//
+//*****************************************************************************
+#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default
+#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default
+#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default
+#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default
+#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode
+#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP)
+ // mode
+#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity
+ // (RM) mode
+#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode
+
+#endif // __HW_NVIC_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_peci.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_peci.h
new file mode 100644
index 00000000..738213b6
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_peci.h
@@ -0,0 +1,49 @@
+//*****************************************************************************
+//
+// hw_peci.h - Macros used when accessing the PECI hardware.
+//
+// Copyright (c) 2010-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_PECI_H__
+#define __HW_PECI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the PECI register addresses.
+//
+//*****************************************************************************
+
+#endif // __HW_PECI_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_pwm.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_pwm.h
new file mode 100644
index 00000000..00badae9
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_pwm.h
@@ -0,0 +1,1882 @@
+//*****************************************************************************
+//
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_PWM_H__
+#define __HW_PWM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the PWM register offsets.
+//
+//*****************************************************************************
+#define PWM_O_CTL 0x00000000 // PWM Master Control
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable
+#define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear
+#define PWM_O_STATUS 0x00000020 // PWM Status
+#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value
+#define PWM_O_ENUPD 0x00000028 // PWM Enable Update
+#define PWM_O_0_CTL 0x00000040 // PWM0 Control
+#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger
+ // Enable
+#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status
+#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear
+#define PWM_O_0_LOAD 0x00000050 // PWM0 Load
+#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter
+#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A
+#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B
+#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control
+#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control
+#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control
+#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay
+#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0
+#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1
+#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period
+#define PWM_O_1_CTL 0x00000080 // PWM1 Control
+#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger
+ // Enable
+#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status
+#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear
+#define PWM_O_1_LOAD 0x00000090 // PWM1 Load
+#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter
+#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A
+#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B
+#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control
+#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control
+#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control
+#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay
+#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0
+#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1
+#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period
+#define PWM_O_2_CTL 0x000000C0 // PWM2 Control
+#define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger
+ // Enable
+#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status
+#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear
+#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load
+#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter
+#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A
+#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B
+#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control
+#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control
+#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control
+#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay
+#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0
+#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1
+#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period
+#define PWM_O_3_CTL 0x00000100 // PWM3 Control
+#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger
+ // Enable
+#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status
+#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear
+#define PWM_O_3_LOAD 0x00000110 // PWM3 Load
+#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter
+#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A
+#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B
+#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control
+#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control
+#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control
+#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay
+#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0
+#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1
+#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period
+#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense
+#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0
+#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1
+#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense
+#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0
+#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1
+#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense
+#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0
+#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1
+#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense
+#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0
+#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1
+#define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 Output Enable
+#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 Output Enable
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV 0x00000080 // Invert PWM7 Signal
+#define PWM_INVERT_PWM6INV 0x00000040 // Invert PWM6 Signal
+#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal
+#define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal
+#define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal
+#define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal
+#define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal
+#define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7 0x00000080 // PWM7 Fault
+#define PWM_FAULT_FAULT6 0x00000040 // PWM6 Fault
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault
+#define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault
+#define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault
+#define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault
+#define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault
+#define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3
+#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2
+#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3
+#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2
+#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0
+#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted
+#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted
+#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status
+#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status
+#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value
+#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value
+#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value
+#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value
+#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value
+#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value
+#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value
+#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
+//
+//*****************************************************************************
+#define PWM_ENUPD_ENUPD7_M 0x0000C000 // PWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M 0x00003000 // PWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M 0x00000C00 // PWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M 0x00000300 // PWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M 0x000000C0 // PWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M 0x00000030 // PWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M 0x0000000C // PWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M 0x00000003 // PWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CTL register.
+//
+//*****************************************************************************
+#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register
+#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_0_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_INTEN register.
+//
+//*****************************************************************************
+#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down
+#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up
+#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down
+#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up
+#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
+#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down
+#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up
+#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down
+#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up
+#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
+#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_RIS register.
+//
+//*****************************************************************************
+#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_ISC register.
+//
+//*****************************************************************************
+#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_LOAD register.
+//
+//*****************************************************************************
+#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_0_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_COUNT register.
+//
+//*****************************************************************************
+#define PWM_0_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_0_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPA register.
+//
+//*****************************************************************************
+#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_0_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPB register.
+//
+//*****************************************************************************
+#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_0_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENA register.
+//
+//*****************************************************************************
+#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_0_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_0_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_0_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_0_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_0_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_0_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_0_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_0_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENB register.
+//
+//*****************************************************************************
+#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_0_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_0_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_0_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_0_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_0_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_0_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_0_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_0_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
+#define PWM_0_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
+#define PWM_0_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
+#define PWM_0_MINFLTPER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CTL register.
+//
+//*****************************************************************************
+#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register
+#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_1_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_INTEN register.
+//
+//*****************************************************************************
+#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down
+#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up
+#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down
+#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up
+#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
+#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down
+#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up
+#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down
+#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up
+#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
+#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_RIS register.
+//
+//*****************************************************************************
+#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_ISC register.
+//
+//*****************************************************************************
+#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_LOAD register.
+//
+//*****************************************************************************
+#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_1_LOAD_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_COUNT register.
+//
+//*****************************************************************************
+#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_1_COUNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPA register.
+//
+//*****************************************************************************
+#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_1_CMPA_COMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPB register.
+//
+//*****************************************************************************
+#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_1_CMPB_COMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENA register.
+//
+//*****************************************************************************
+#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_1_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_1_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_1_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_1_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_1_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_1_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_1_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_1_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENB register.
+//
+//*****************************************************************************
+#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_1_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_1_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_1_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_1_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_1_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_1_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_1_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_1_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_1_DBRISE_RISEDELAY_M \
+ 0x00000FFF // Dead-Band Rise Delay
+#define PWM_1_DBRISE_RISEDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_1_DBFALL_FALLDELAY_M \
+ 0x00000FFF // Dead-Band Fall Delay
+#define PWM_1_DBFALL_FALLDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
+#define PWM_1_MINFLTPER_MFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CTL register.
+//
+//*****************************************************************************
+#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register
+#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_2_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_INTEN register.
+//
+//*****************************************************************************
+#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down
+#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up
+#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down
+#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up
+#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
+#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down
+#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up
+#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down
+#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up
+#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
+#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_RIS register.
+//
+//*****************************************************************************
+#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_ISC register.
+//
+//*****************************************************************************
+#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_LOAD register.
+//
+//*****************************************************************************
+#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_2_LOAD_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_COUNT register.
+//
+//*****************************************************************************
+#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_2_COUNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPA register.
+//
+//*****************************************************************************
+#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_2_CMPA_COMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPB register.
+//
+//*****************************************************************************
+#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_2_CMPB_COMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENA register.
+//
+//*****************************************************************************
+#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_2_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_2_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_2_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_2_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_2_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_2_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_2_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_2_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENB register.
+//
+//*****************************************************************************
+#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_2_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_2_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_2_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_2_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_2_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_2_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_2_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_2_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_2_DBRISE_RISEDELAY_M \
+ 0x00000FFF // Dead-Band Rise Delay
+#define PWM_2_DBRISE_RISEDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_2_DBFALL_FALLDELAY_M \
+ 0x00000FFF // Dead-Band Fall Delay
+#define PWM_2_DBFALL_FALLDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
+#define PWM_2_MINFLTPER_MFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CTL register.
+//
+//*****************************************************************************
+#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register
+#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_3_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_INTEN register.
+//
+//*****************************************************************************
+#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down
+#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up
+#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down
+#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up
+#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
+#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down
+#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up
+#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down
+#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up
+#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
+#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_RIS register.
+//
+//*****************************************************************************
+#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_ISC register.
+//
+//*****************************************************************************
+#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_LOAD register.
+//
+//*****************************************************************************
+#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_3_LOAD_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_COUNT register.
+//
+//*****************************************************************************
+#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_3_COUNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPA register.
+//
+//*****************************************************************************
+#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_3_CMPA_COMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPB register.
+//
+//*****************************************************************************
+#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_3_CMPB_COMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENA register.
+//
+//*****************************************************************************
+#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_3_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_3_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_3_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_3_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_3_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_3_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_3_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_3_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENB register.
+//
+//*****************************************************************************
+#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_3_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_3_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_3_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_3_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_3_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_3_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_3_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_3_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_3_DBRISE_RISEDELAY_M \
+ 0x00000FFF // Dead-Band Rise Delay
+#define PWM_3_DBRISE_RISEDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_3_DBFALL_FALLDELAY_M \
+ 0x00000FFF // Dead-Band Fall Delay
+#define PWM_3_DBFALL_FALLDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2
+#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1
+#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
+#define PWM_3_MINFLTPER_MFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_PP register.
+//
+//*****************************************************************************
+#define PWM_PP_GCNT_M 0x0000000F // Generators
+#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs
+#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization
+#define PWM_PP_EFAULT 0x00000200 // Extended Fault
+#define PWM_PP_ONE 0x00000400 // One-Shot Mode
+#define PWM_PP_GCNT_S 0
+#define PWM_PP_FCNT_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator standard offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
+#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition
+#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition
+#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
+#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
+#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_X_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
+ // Down
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
+ // Down
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
+ // Down
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
+ // Up
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
+ // Down
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
+ // Up
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_X_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_X_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_X_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_X_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_X_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_X_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_X_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_X_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_X_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_X_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_X_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_X_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
+#define PWM_X_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
+#define PWM_X_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
+#define PWM_X_MINFLTPER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator extended offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense
+#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status
+#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status
+#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base
+#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base
+#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base
+#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+#endif // __HW_PWM_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_qei.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_qei.h
new file mode 100644
index 00000000..a5db5f42
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_qei.h
@@ -0,0 +1,178 @@
+//*****************************************************************************
+//
+// hw_qei.h - Macros used when accessing the QEI hardware.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_QEI_H__
+#define __HW_QEI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the QEI register offsets.
+//
+//*****************************************************************************
+#define QEI_O_CTL 0x00000000 // QEI Control
+#define QEI_O_STAT 0x00000004 // QEI Status
+#define QEI_O_POS 0x00000008 // QEI Position
+#define QEI_O_MAXPOS 0x0000000C // QEI Maximum Position
+#define QEI_O_LOAD 0x00000010 // QEI Timer Load
+#define QEI_O_TIME 0x00000014 // QEI Timer
+#define QEI_O_COUNT 0x00000018 // QEI Velocity Counter
+#define QEI_O_SPEED 0x0000001C // QEI Velocity
+#define QEI_O_INTEN 0x00000020 // QEI Interrupt Enable
+#define QEI_O_RIS 0x00000024 // QEI Raw Interrupt Status
+#define QEI_O_ISC 0x00000028 // QEI Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count
+#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter
+#define QEI_CTL_STALLEN 0x00001000 // Stall QEI
+#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse
+#define QEI_CTL_INVB 0x00000400 // Invert PhB
+#define QEI_CTL_INVA 0x00000200 // Invert PhA
+#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity
+#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1
+#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2
+#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4
+#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8
+#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16
+#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32
+#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64
+#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128
+#define QEI_CTL_VELEN 0x00000020 // Capture Velocity
+#define QEI_CTL_RESMODE 0x00000010 // Reset Mode
+#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode
+#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode
+#define QEI_CTL_SWAP 0x00000002 // Swap Signals
+#define QEI_CTL_ENABLE 0x00000001 // Enable QEI
+#define QEI_CTL_FILTCNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation
+#define QEI_STAT_ERROR 0x00000001 // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
+ // Value
+#define QEI_POS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
+ // Value
+#define QEI_MAXPOS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value
+#define QEI_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value
+#define QEI_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count
+#define QEI_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M 0xFFFFFFFF // Velocity
+#define QEI_SPEED_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
+ // Enable
+#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected
+#define QEI_RIS_DIR 0x00000004 // Direction Change Detected
+#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired
+#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt
+#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt
+#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt
+
+#endif // __HW_QEI_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_ssi.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_ssi.h
new file mode 100644
index 00000000..75f3761b
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_ssi.h
@@ -0,0 +1,197 @@
+//*****************************************************************************
+//
+// hw_ssi.h - Macros used when accessing the SSI hardware.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SSI_H__
+#define __HW_SSI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the SSI register offsets.
+//
+//*****************************************************************************
+#define SSI_O_CR0 0x00000000 // SSI Control 0
+#define SSI_O_CR1 0x00000004 // SSI Control 1
+#define SSI_O_DR 0x00000008 // SSI Data
+#define SSI_O_SR 0x0000000C // SSI Status
+#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale
+#define SSI_O_IM 0x00000014 // SSI Interrupt Mask
+#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status
+#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status
+#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear
+#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
+#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
+#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
+#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
+ // Serial Frame Format
+#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
+#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
+#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
+#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
+#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
+#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
+#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
+#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
+#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
+#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
+#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
+#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
+#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
+#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
+#define SSI_CR0_SCR_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_EOT 0x00000010 // End of Transmission
+#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
+#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
+#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
+ // Enable
+#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
+#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
+#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
+ // Mask
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
+ // Interrupt Status
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
+ // Interrupt Status
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
+ // Clear
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CC register.
+//
+//*****************************************************************************
+#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
+#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
+ // PLL bypass is in effect) or the
+ // PLL output (default)
+#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC
+
+#endif // __HW_SSI_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_sysctl.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_sysctl.h
new file mode 100644
index 00000000..35694c42
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_sysctl.h
@@ -0,0 +1,2368 @@
+//*****************************************************************************
+//
+// hw_sysctl.h - Macros used when accessing the system control hardware.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSCTL_H__
+#define __HW_SYSCTL_H__
+
+//*****************************************************************************
+//
+// The following are defines for the System Control register addresses.
+//
+//*****************************************************************************
+#define SYSCTL_DID0 0x400FE000 // Device Identification 0
+#define SYSCTL_DID1 0x400FE004 // Device Identification 1
+#define SYSCTL_DC0 0x400FE008 // Device Capabilities 0
+#define SYSCTL_DC1 0x400FE010 // Device Capabilities 1
+#define SYSCTL_DC2 0x400FE014 // Device Capabilities 2
+#define SYSCTL_DC3 0x400FE018 // Device Capabilities 3
+#define SYSCTL_DC4 0x400FE01C // Device Capabilities 4
+#define SYSCTL_DC5 0x400FE020 // Device Capabilities 5
+#define SYSCTL_DC6 0x400FE024 // Device Capabilities 6
+#define SYSCTL_DC7 0x400FE028 // Device Capabilities 7
+#define SYSCTL_DC8 0x400FE02C // Device Capabilities 8 ADC
+ // Channels
+#define SYSCTL_PBORCTL 0x400FE030 // Brown-Out Reset Control
+#define SYSCTL_SRCR0 0x400FE040 // Software Reset Control 0
+#define SYSCTL_SRCR1 0x400FE044 // Software Reset Control 1
+#define SYSCTL_SRCR2 0x400FE048 // Software Reset Control 2
+#define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status
+#define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control
+#define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and
+ // Clear
+#define SYSCTL_RESC 0x400FE05C // Reset Cause
+#define SYSCTL_RCC 0x400FE060 // Run-Mode Clock Configuration
+#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO High-Performance Bus
+ // Control
+#define SYSCTL_RCC2 0x400FE070 // Run-Mode Clock Configuration 2
+#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control
+#define SYSCTL_RCGC0 0x400FE100 // Run Mode Clock Gating Control
+ // Register 0
+#define SYSCTL_RCGC1 0x400FE104 // Run Mode Clock Gating Control
+ // Register 1
+#define SYSCTL_RCGC2 0x400FE108 // Run Mode Clock Gating Control
+ // Register 2
+#define SYSCTL_SCGC0 0x400FE110 // Sleep Mode Clock Gating Control
+ // Register 0
+#define SYSCTL_SCGC1 0x400FE114 // Sleep Mode Clock Gating Control
+ // Register 1
+#define SYSCTL_SCGC2 0x400FE118 // Sleep Mode Clock Gating Control
+ // Register 2
+#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep Mode Clock Gating
+ // Control Register 0
+#define SYSCTL_DCGC1 0x400FE124 // Deep-Sleep Mode Clock Gating
+ // Control Register 1
+#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating
+ // Control Register 2
+#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration
+#define SYSCTL_SYSPROP 0x400FE14C // System Properties
+#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator
+ // Calibration
+#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator
+ // Statistics
+#define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0
+#define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1
+#define SYSCTL_PLLSTAT 0x400FE168 // PLL Status
+#define SYSCTL_DC9 0x400FE190 // Device Capabilities 9 ADC
+ // Digital Comparators
+#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information
+#define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral
+ // Present
+#define SYSCTL_PPTIMER 0x400FE304 // Timer Peripheral Present
+#define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output
+ // Peripheral Present
+#define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access
+ // Peripheral Present
+#define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present
+#define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous
+ // Receiver/Transmitter Peripheral
+ // Present
+#define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface
+ // Peripheral Present
+#define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit
+ // Peripheral Present
+#define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral
+ // Present
+#define SYSCTL_PPCAN 0x400FE334 // Controller Area Network
+ // Peripheral Present
+#define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter
+ // Peripheral Present
+#define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral
+ // Present
+#define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral
+ // Present
+#define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface
+ // Peripheral Present
+#define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present
+#define SYSCTL_PPWTIMER 0x400FE35C // Wide Timer Peripheral Present
+#define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset
+#define SYSCTL_SRTIMER 0x400FE504 // Timer Software Reset
+#define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output
+ // Software Reset
+#define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access
+ // Software Reset
+#define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset
+#define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous
+ // Receiver/Transmitter Software
+ // Reset
+#define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface
+ // Software Reset
+#define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit
+ // Software Reset
+#define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software
+ // Reset
+#define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software
+ // Reset
+#define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter
+ // Software Reset
+#define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset
+#define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software
+ // Reset
+#define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface
+ // Software Reset
+#define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset
+#define SYSCTL_SRWTIMER 0x400FE55C // Wide Timer Software Reset
+#define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCTIMER 0x400FE604 // Timer Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous
+ // Receiver/Transmitter Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCWTIMER 0x400FE65C // Wide Timer Run Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCTIMER 0x400FE704 // Timer Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous
+ // Receiver/Transmitter Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCWTIMER 0x400FE75C // Wide Timer Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCTIMER 0x400FE804 // Timer Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous
+ // Receiver/Transmitter Deep-Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCWTIMER 0x400FE85C // Wide Timer Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready
+#define SYSCTL_PRTIMER 0x400FEA04 // Timer Peripheral Ready
+#define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output
+ // Peripheral Ready
+#define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access
+ // Peripheral Ready
+#define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready
+#define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous
+ // Receiver/Transmitter Peripheral
+ // Ready
+#define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface
+ // Peripheral Ready
+#define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit
+ // Peripheral Ready
+#define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral
+ // Ready
+#define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network
+ // Peripheral Ready
+#define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter
+ // Peripheral Ready
+#define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral
+ // Ready
+#define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral
+ // Ready
+#define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface
+ // Peripheral Ready
+#define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready
+#define SYSCTL_PRWTIMER 0x400FEA5C // Wide Timer Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version
+#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
+ // register format
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
+#define SYSCTL_DID0_CLASS_BLIZZARD \
+ 0x00050000 // Tiva(TM) C Series Blizzard-class
+ // microcontrollers
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
+ // revision)
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
+ // revision)
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision
+#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
+ // revision update
+#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change
+#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version
+#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1
+ // register format
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family
+#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number
+#define SYSCTL_DID1_PRTNO_TM4C1230C3PM \
+ 0x00220000 // TM4C1230C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1230D5PM \
+ 0x00230000 // TM4C1230D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1230E6PM \
+ 0x00200000 // TM4C1230E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1230H6PM \
+ 0x00210000 // TM4C1230H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1231C3PM \
+ 0x00180000 // TM4C1231C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1231D5PM \
+ 0x00190000 // TM4C1231D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1231D5PZ \
+ 0x00360000 // TM4C1231D5PZ
+#define SYSCTL_DID1_PRTNO_TM4C1231E6PM \
+ 0x00100000 // TM4C1231E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1231E6PZ \
+ 0x00300000 // TM4C1231E6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1231H6PGE \
+ 0x00350000 // TM4C1231H6PGE
+#define SYSCTL_DID1_PRTNO_TM4C1231H6PM \
+ 0x00110000 // TM4C1231H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1231H6PZ \
+ 0x00310000 // TM4C1231H6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1232C3PM \
+ 0x00080000 // TM4C1232C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1232D5PM \
+ 0x00090000 // TM4C1232D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1232E6PM \
+ 0x000A0000 // TM4C1232E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1232H6PM \
+ 0x000B0000 // TM4C1232H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1233C3PM \
+ 0x00010000 // TM4C1233C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1233D5PM \
+ 0x00020000 // TM4C1233D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1233D5PZ \
+ 0x00D00000 // TM4C1233D5PZ
+#define SYSCTL_DID1_PRTNO_TM4C1233E6PM \
+ 0x00030000 // TM4C1233E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1233E6PZ \
+ 0x00D10000 // TM4C1233E6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1233H6PGE \
+ 0x00D60000 // TM4C1233H6PGE
+#define SYSCTL_DID1_PRTNO_TM4C1233H6PM \
+ 0x00040000 // TM4C1233H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1233H6PZ \
+ 0x00D20000 // TM4C1233H6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1236D5PM \
+ 0x00520000 // TM4C1236D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1236E6PM \
+ 0x00500000 // TM4C1236E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1236H6PM \
+ 0x00510000 // TM4C1236H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1237D5PM \
+ 0x00480000 // TM4C1237D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1237D5PZ \
+ 0x00660000 // TM4C1237D5PZ
+#define SYSCTL_DID1_PRTNO_TM4C1237E6PM \
+ 0x00400000 // TM4C1237E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1237E6PZ \
+ 0x00600000 // TM4C1237E6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1237H6PGE \
+ 0x00650000 // TM4C1237H6PGE
+#define SYSCTL_DID1_PRTNO_TM4C1237H6PM \
+ 0x00410000 // TM4C1237H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1237H6PZ \
+ 0x00610000 // TM4C1237H6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123AE6PM \
+ 0x00800000 // TM4C123AE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123AH6PM \
+ 0x00830000 // TM4C123AH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123BE6PM \
+ 0x00700000 // TM4C123BE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123BE6PZ \
+ 0x00C30000 // TM4C123BE6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123BH6PGE \
+ 0x00C60000 // TM4C123BH6PGE
+#define SYSCTL_DID1_PRTNO_TM4C123BH6PM \
+ 0x00730000 // TM4C123BH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123BH6PZ \
+ 0x00C40000 // TM4C123BH6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123BH6ZRB \
+ 0x00E90000 // TM4C123BH6ZRB
+#define SYSCTL_DID1_PRTNO_TM4C123FE6PM \
+ 0x00B00000 // TM4C123FE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123FH6PM \
+ 0x00B10000 // TM4C123FH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123GE6PM \
+ 0x00A00000 // TM4C123GE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123GE6PZ \
+ 0x00C00000 // TM4C123GE6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PGE \
+ 0x00C50000 // TM4C123GH6PGE
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PM \
+ 0x00A10000 // TM4C123GH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PZ \
+ 0x00C10000 // TM4C123GH6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123GH6ZRB \
+ 0x00E30000 // TM4C123GH6ZRB
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count
+#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28-pin package
+#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package
+#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package
+#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin package
+#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin package
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C
+ // to 70C)
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
+ // (-40C to 85C)
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
+ // to 105C)
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type
+#define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
+#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present
+#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present
+#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present
+#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present
+#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider
+#define SYSCTL_DC1_MINSYSDIV_100 \
+ 0x00001000 // Divide VCO (400MHZ) by 5 minimum
+#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Divide VCO (400MHZ) by 2*2 + 2 =
+ // 6 minimum
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
+ // with a PLL divider of 4
+#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock
+ // with a PLL divider of 5
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
+ // PLL divider of 8
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
+ // PLL divider of 10
+#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed
+#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second
+#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second
+#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second
+#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed
+#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second
+#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second
+#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second
+#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DC1_MPU 0x00000080 // MPU Present
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present
+#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present
+#define SYSCTL_DC1_PLL 0x00000010 // PLL Present
+#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present
+#define SYSCTL_DC1_SWD 0x00000002 // SWD Present
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present
+#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed
+#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present
+#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present
+#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present
+#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 Pin Present
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 Pin Present
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present
+#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present
+#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present
+#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present
+#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present
+#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable
+#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate
+#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present
+#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present
+#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present
+#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present
+#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present
+#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present
+#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present
+#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present
+#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active
+#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active
+#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present
+#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present
+#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present
+#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present
+#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host
+#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_DMACH30 0x40000000 // SW
+#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX / CAN1_TX
+#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX / CAN1_RX
+#define SYSCTL_DC7_DMACH27 0x08000000 // CAN1_TX / ADC1_SS3
+#define SYSCTL_DC7_DMACH26 0x04000000 // CAN1_RX / ADC1_SS2
+#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1
+#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0
+#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX / CAN2_TX
+#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX / CAN2_RX
+#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_WFIFO
+#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_NBRFIFO
+#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B
+#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A
+#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3
+#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2
+#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B
+#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A
+#define SYSCTL_DC7_DMACH13 0x00002000 // CAN0_TX / UART2_TX
+#define SYSCTL_DC7_DMACH12 0x00001000 // CAN0_RX / UART2_RX
+#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / SSI1_TX
+#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / SSI1_RX
+#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / UART1_TX
+#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / UART1_RX
+#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B
+#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A
+#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B
+#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A
+#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B
+#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A
+#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX
+#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present
+#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present
+#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present
+#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present
+#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present
+#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present
+#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present
+#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present
+#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present
+#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present
+#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present
+#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present
+#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present
+#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present
+#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present
+#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present
+#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present
+#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present
+#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present
+#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present
+#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present
+#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present
+#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present
+#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present
+#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BOR0 0x00000004 // VDD under BOR0 Event Action
+#define SYSCTL_PBORCTL_BOR1 0x00000002 // VDD under BOR1 Event Action
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control
+#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control
+#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control
+#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control
+#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control
+#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control
+#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control
+#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control
+#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control
+#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_VDDARIS 0x00000400 // VDDA Power OK Event Raw
+ // Interrupt Status
+#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
+ // Status
+#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt
+ // Status
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_VDDAIM 0x00000400 // VDDA Power OK Interrupt Mask
+#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_VDDAMIS 0x00000400 // VDDA Power OK Masked Interrupt
+ // Status
+#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
+ // Status
+#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt
+ // Status
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset
+#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW 0x00000010 // Software Reset
+#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset
+#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset
+#define SYSCTL_RESC_EXT 0x00000001 // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass
+#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value
+#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
+#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz
+#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
+#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz
+#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz
+#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz
+#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S 23
+#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance
+ // Bus
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
+#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200
+ // MHz
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2
+#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2
+#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz
+#define SYSCTL_RCC2_SYSDIV2_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected
+#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action
+#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed
+#define SYSCTL_RCGC0_ADC1SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_250K \
+ 0x00000400 // 250K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_500K \
+ 0x00000800 // 500K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed
+#define SYSCTL_RCGC0_ADC0SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_250K \
+ 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_500K \
+ 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed
+#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz
+#define SYSCTL_DSLPCLKCFG_D_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
+//
+//*****************************************************************************
+#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value
+#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration
+#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value
+#define SYSCTL_PIOSCCAL_UT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value
+#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result
+#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been
+ // attempted
+#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation
+ // completed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation
+ // failed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value
+#define SYSCTL_PIOSCSTAT_DT_S 16
+#define SYSCTL_PIOSCSTAT_CT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value
+#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value
+#define SYSCTL_PLLFREQ0_MFRAC_S 10
+#define SYSCTL_PLLFREQ0_MINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value
+#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value
+#define SYSCTL_PLLFREQ1_Q_S 8
+#define SYSCTL_PLLFREQ1_N_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC9 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present
+#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present
+#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present
+#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present
+#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present
+#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present
+#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present
+#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present
+#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present
+#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present
+#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present
+#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present
+#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present
+#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present
+#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present
+#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer
+ // Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present
+#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PPTIMER_P5 0x00000020 // Timer 5 Present
+#define SYSCTL_PPTIMER_P4 0x00000010 // Timer 4 Present
+#define SYSCTL_PPTIMER_P3 0x00000008 // Timer 3 Present
+#define SYSCTL_PPTIMER_P2 0x00000004 // Timer 2 Present
+#define SYSCTL_PPTIMER_P1 0x00000002 // Timer 1 Present
+#define SYSCTL_PPTIMER_P0 0x00000001 // Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present
+#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present
+#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present
+#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present
+#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present
+#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present
+#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present
+#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present
+#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present
+#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present
+#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present
+#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present
+#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present
+#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present
+#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present
+#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present
+#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present
+#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present
+#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present
+#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present
+#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present
+#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present
+#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present
+#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present
+#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present
+#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present
+#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present
+#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present
+#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present
+#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present
+#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present
+#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present
+#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present
+#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWTIMER_P5 0x00000020 // Wide Timer 5 Present
+#define SYSCTL_PPWTIMER_P4 0x00000010 // Wide Timer 4 Present
+#define SYSCTL_PPWTIMER_P3 0x00000008 // Wide Timer 3 Present
+#define SYSCTL_PPWTIMER_P2 0x00000004 // Wide Timer 2 Present
+#define SYSCTL_PPWTIMER_P1 0x00000002 // Wide Timer 1 Present
+#define SYSCTL_PPWTIMER_P0 0x00000001 // Wide Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset
+#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_SRTIMER_R5 0x00000020 // Timer 5 Software Reset
+#define SYSCTL_SRTIMER_R4 0x00000010 // Timer 4 Software Reset
+#define SYSCTL_SRTIMER_R3 0x00000008 // Timer 3 Software Reset
+#define SYSCTL_SRTIMER_R2 0x00000004 // Timer 2 Software Reset
+#define SYSCTL_SRTIMER_R1 0x00000002 // Timer 1 Software Reset
+#define SYSCTL_SRTIMER_R0 0x00000001 // Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset
+#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset
+#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset
+#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset
+#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset
+#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset
+#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset
+#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset
+#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset
+#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset
+#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset
+#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset
+#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset
+#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset
+#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software
+ // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset
+#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset
+#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset
+#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset
+#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset
+#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset
+#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset
+#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset
+#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset
+#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset
+#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset
+#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset
+#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset
+#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset
+#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset
+#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset
+#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset
+#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0
+ // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset
+#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset
+#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWTIMER_R5 0x00000020 // Wide Timer 5 Software Reset
+#define SYSCTL_SRWTIMER_R4 0x00000010 // Wide Timer 4 Software Reset
+#define SYSCTL_SRWTIMER_R3 0x00000008 // Wide Timer 3 Software Reset
+#define SYSCTL_SRWTIMER_R2 0x00000004 // Wide Timer 2 Software Reset
+#define SYSCTL_SRWTIMER_R1 0x00000002 // Wide Timer 1 Software Reset
+#define SYSCTL_SRWTIMER_R0 0x00000001 // Wide Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCTIMER_R5 0x00000020 // Timer 5 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R4 0x00000010 // Timer 4 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R3 0x00000008 // Timer 3 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R2 0x00000004 // Timer 2 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R1 0x00000002 // Timer 1 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R0 0x00000001 // Timer 0 Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWTIMER_R5 0x00000020 // Wide Timer 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R4 0x00000010 // Wide Timer 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R3 0x00000008 // Wide Timer 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R2 0x00000004 // Wide Timer 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R1 0x00000002 // Wide Timer 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R0 0x00000001 // Wide Timer 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCTIMER_S5 0x00000020 // Timer 5 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S4 0x00000010 // Timer 4 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S3 0x00000008 // Timer 3 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S2 0x00000004 // Timer 2 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S1 0x00000002 // Timer 1 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S0 0x00000001 // Timer 0 Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWTIMER_S5 0x00000020 // Wide Timer 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S4 0x00000010 // Wide Timer 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S3 0x00000008 // Wide Timer 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S2 0x00000004 // Wide Timer 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S1 0x00000002 // Wide Timer 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S0 0x00000001 // Wide Timer 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCTIMER_D5 0x00000020 // Timer 5 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D4 0x00000010 // Timer 4 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D3 0x00000008 // Timer 3 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D2 0x00000004 // Timer 2 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D1 0x00000002 // Timer 1 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D0 0x00000001 // Timer 0 Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0
+ // Deep-Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWTIMER_D5 0x00000020 // Wide Timer 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D4 0x00000010 // Wide Timer 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D3 0x00000008 // Wide Timer 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D2 0x00000004 // Wide Timer 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D1 0x00000002 // Wide Timer 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D0 0x00000001 // Wide Timer 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral
+ // Ready
+#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral
+ // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PRTIMER_R5 0x00000020 // Timer 5 Peripheral Ready
+#define SYSCTL_PRTIMER_R4 0x00000010 // Timer 4 Peripheral Ready
+#define SYSCTL_PRTIMER_R3 0x00000008 // Timer 3 Peripheral Ready
+#define SYSCTL_PRTIMER_R2 0x00000004 // Timer 2 Peripheral Ready
+#define SYSCTL_PRTIMER_R1 0x00000002 // Timer 1 Peripheral Ready
+#define SYSCTL_PRTIMER_R0 0x00000001 // Timer 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready
+#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready
+#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready
+#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready
+#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready
+#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready
+#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready
+#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready
+#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready
+#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready
+#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready
+#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready
+#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready
+#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready
+#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral
+ // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready
+#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready
+#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready
+#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready
+#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready
+#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready
+#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready
+#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready
+#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready
+#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready
+#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready
+#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready
+#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready
+#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready
+#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready
+#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready
+#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready
+#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0
+ // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready
+#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready
+#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWTIMER_R5 0x00000020 // Wide Timer 5 Peripheral Ready
+#define SYSCTL_PRWTIMER_R4 0x00000010 // Wide Timer 4 Peripheral Ready
+#define SYSCTL_PRWTIMER_R3 0x00000008 // Wide Timer 3 Peripheral Ready
+#define SYSCTL_PRWTIMER_R2 0x00000004 // Wide Timer 2 Peripheral Ready
+#define SYSCTL_PRWTIMER_R1 0x00000002 // Wide Timer 1 Peripheral Ready
+#define SYSCTL_PRWTIMER_R0 0x00000001 // Wide Timer 0 Peripheral Ready
+
+#endif // __HW_SYSCTL_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_sysexc.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_sysexc.h
new file mode 100644
index 00000000..07c895de
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_sysexc.h
@@ -0,0 +1,132 @@
+//*****************************************************************************
+//
+// hw_sysexc.h - Macros used when accessing the system exception module.
+//
+// Copyright (c) 2011-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSEXC_H__
+#define __HW_SYSEXC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the System Exception Module register
+// addresses.
+//
+//*****************************************************************************
+#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt
+ // Status
+#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask
+#define SYSEXC_MIS 0x400F9008 // System Exception Masked
+ // Interrupt Status
+#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_RIS register.
+//
+//*****************************************************************************
+#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception
+ // Raw Interrupt Status
+#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation
+ // Raw Interrupt Status
+#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal
+ // Exception Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IM register.
+//
+//*****************************************************************************
+#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception
+ // Interrupt Mask
+#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation
+ // Interrupt Mask
+#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal
+ // Exception Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_MIS register.
+//
+//*****************************************************************************
+#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception
+ // Masked Interrupt Status
+#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation
+ // Masked Interrupt Status
+#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal
+ // Exception Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IC register.
+//
+//*****************************************************************************
+#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception
+ // Interrupt Clear
+#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation
+ // Interrupt Clear
+#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal
+ // Exception Interrupt Clear
+
+#endif // __HW_SYSEXC_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_timer.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_timer.h
new file mode 100644
index 00000000..10349046
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_timer.h
@@ -0,0 +1,587 @@
+//*****************************************************************************
+//
+// hw_timer.h - Defines and macros used when accessing the timer.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TIMER_H__
+#define __HW_TIMER_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Timer register offsets.
+//
+//*****************************************************************************
+#define TIMER_O_CFG 0x00000000 // GPTM Configuration
+#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
+#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
+#define TIMER_O_CTL 0x0000000C // GPTM Control
+#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
+#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
+#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
+#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
+#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
+#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
+#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
+#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
+#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
+#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
+#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
+#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
+#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
+#define TIMER_O_TAR 0x00000048 // GPTM Timer A
+#define TIMER_O_TBR 0x0000004C // GPTM Timer B
+#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
+#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
+#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
+#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
+#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
+#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
+#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
+#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
+ // counter configuration
+#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
+ // function is controlled by bits
+ // 1:0 of GPTMTAMR and GPTMTBMR
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
+ // Operation
+#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
+ // Update
+#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
+ // Enable
+#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
+#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
+ // Enable
+#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
+ // Select
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
+ // Operation
+#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
+ // Update
+#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
+ // Enable
+#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
+#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
+ // Enable
+#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
+ // Select
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
+ // Enable
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
+#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
+ // Enable
+#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
+#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_SYNC register.
+//
+//*****************************************************************************
+#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer
+ // 5
+#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not
+ // affected
+#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 5 is triggered
+#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer
+ // 4
+#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not
+ // affected
+#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 4 is triggered
+#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer
+ // 3
+#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not
+ // affected
+#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 3 is triggered
+#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer
+ // 2
+#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not
+ // affected
+#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 2 is triggered
+#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer
+ // 1
+#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not
+ // affected
+#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 1 is triggered
+#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer
+ // 0
+#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not
+ // affected
+#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 0 is triggered
+#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer
+ // 5
+#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not
+ // affected
+#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 5 is triggered
+#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer
+ // 4
+#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not
+ // affected
+#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 4 is triggered
+#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer
+ // 3
+#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not
+ // affected
+#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 3 is triggered
+#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer
+ // 2
+#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not
+ // affected
+#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 2 is triggered
+#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer
+ // 1
+#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not
+ // affected
+#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 1 is triggered
+#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer
+ // 0
+#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not
+ // affected
+#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 0 is triggered
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_WUEIM 0x00010000 // GPTM Write Update Error
+ // Interrupt Mask
+#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt
+ // Mask
+#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event
+ // Interrupt Mask
+#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Mask
+#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt
+ // Mask
+#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event
+ // Interrupt Mask
+#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_WUERIS 0x00010000 // GPTM Write Update Error Raw
+ // Interrupt
+#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt
+#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event
+ // Raw Interrupt
+#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match
+ // Raw Interrupt
+#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
+ // Interrupt
+#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt
+#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event
+ // Raw Interrupt
+#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match
+ // Raw Interrupt
+#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_WUEMIS 0x00010000 // GPTM Write Update Error Masked
+ // Interrupt
+#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked
+ // Interrupt
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event
+ // Masked Interrupt
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match
+ // Masked Interrupt
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
+ // Interrupt
+#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked
+ // Interrupt
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event
+ // Masked Interrupt
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match
+ // Masked Interrupt
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update
+ // Error Interrupt Clear
+#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt
+ // Clear
+#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event
+ // Interrupt Clear
+#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Clear
+#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt
+ // Clear
+#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event
+ // Interrupt Clear
+#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
+ // Register
+#define TIMER_TAILR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
+ // Register
+#define TIMER_TBILR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
+#define TIMER_TAMATCHR_TAMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
+#define TIMER_TBMATCHR_TBMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSRH_S 8
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSRH_S 8
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
+ // Byte
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMRH_S 8
+#define TIMER_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
+ // Byte
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMRH_S 8
+#define TIMER_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
+#define TIMER_TAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
+#define TIMER_TBR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
+#define TIMER_TAV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
+#define TIMER_TBV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RTCPD register.
+//
+//*****************************************************************************
+#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
+#define TIMER_RTCPD_RTCPD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPS register.
+//
+//*****************************************************************************
+#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
+#define TIMER_TAPS_PSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPS register.
+//
+//*****************************************************************************
+#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
+#define TIMER_TBPS_PSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPV register.
+//
+//*****************************************************************************
+#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
+#define TIMER_TAPV_PSV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPV register.
+//
+//*****************************************************************************
+#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
+#define TIMER_TBPV_PSV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_PP register.
+//
+//*****************************************************************************
+#define TIMER_PP_SIZE_M 0x0000000F // Count Size
+#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
+ // 16 bits each with an 8-bit
+ // prescale counter
+#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
+ // 32 bits each with a 16-bit
+ // prescale counter
+
+#endif // __HW_TIMER_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_types.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_types.h
new file mode 100644
index 00000000..b4470df5
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_types.h
@@ -0,0 +1,128 @@
+//*****************************************************************************
+//
+// hw_types.h - Common types and macros.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TYPES_H__
+#define __HW_TYPES_H__
+
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x) \
+ (*((volatile uint32_t *)(x)))
+#define HWREGH(x) \
+ (*((volatile uint16_t *)(x)))
+#define HWREGB(x) \
+ (*((volatile uint8_t *)(x)))
+#define HWREGBITW(x, b) \
+ HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
+ (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITH(x, b) \
+ HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
+ (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITB(x, b) \
+ HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
+ (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+//*****************************************************************************
+//
+// Helper Macros for determining silicon revisions, etc.
+//
+// These macros will be used by Driverlib at "run-time" to create necessary
+// conditional code blocks that will allow a single version of the Driverlib
+// "binary" code to support multiple(all) Tiva silicon revisions.
+//
+// It is expected that these macros will be used inside of a standard 'C'
+// conditional block of code, e.g.
+//
+// if(CLASS_IS_BLIZZARD)
+// {
+// do some Blizzard-class specific code here.
+// }
+//
+// By default, these macros will be defined as run-time checks of the
+// appropriate register(s) to allow creation of run-time conditional code
+// blocks for a common DriverLib across the entire Tiva family.
+//
+// However, if code-space optimization is required, these macros can be "hard-
+// coded" for a specific version of Tiva silicon. Many compilers will then
+// detect the "hard-coded" conditionals, and appropriately optimize the code
+// blocks, eliminating any "unreachable" code. This would result in a smaller
+// Driverlib, thus producing a smaller final application size, but at the cost
+// of limiting the Driverlib binary to a specific Tiva silicon revision.
+//
+//*****************************************************************************
+#ifndef CLASS_IS_BLIZZARD
+#define CLASS_IS_BLIZZARD \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_BLIZZARD))
+#endif
+
+#ifndef REVISION_IS_A0
+#define REVISION_IS_A0 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A1
+#define REVISION_IS_A1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A2
+#define REVISION_IS_A2 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
+#endif
+
+#ifndef REVISION_IS_B0
+#define REVISION_IS_B0 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_B1
+#define REVISION_IS_B1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
+#endif
+
+#endif // __HW_TYPES_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_uart.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_uart.h
new file mode 100644
index 00000000..89e75559
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_uart.h
@@ -0,0 +1,345 @@
+//*****************************************************************************
+//
+// hw_uart.h - Macros and defines used when accessing the UART hardware.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UART_H__
+#define __HW_UART_H__
+
+//*****************************************************************************
+//
+// The following are defines for the UART register offsets.
+//
+//*****************************************************************************
+#define UART_O_DR 0x00000000 // UART Data
+#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear
+#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear
+#define UART_O_FR 0x00000018 // UART Flag
+#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
+#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor
+#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate
+ // Divisor
+#define UART_O_LCRH 0x0000002C // UART Line Control
+#define UART_O_CTL 0x00000030 // UART Control
+#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select
+#define UART_O_IM 0x00000038 // UART Interrupt Mask
+#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status
+#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status
+#define UART_O_ICR 0x00000044 // UART Interrupt Clear
+#define UART_O_DMACTL 0x00000048 // UART DMA Control
+#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address
+#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask
+#define UART_O_PP 0x00000FC0 // UART Peripheral Properties
+#define UART_O_CC 0x00000FC8 // UART Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE 0x00000800 // UART Overrun Error
+#define UART_DR_BE 0x00000400 // UART Break Error
+#define UART_DR_PE 0x00000200 // UART Parity Error
+#define UART_DR_FE 0x00000100 // UART Framing Error
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE 0x00000008 // UART Overrun Error
+#define UART_RSR_BE 0x00000004 // UART Break Error
+#define UART_RSR_PE 0x00000002 // UART Parity Error
+#define UART_RSR_FE 0x00000001 // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear
+#define UART_ECR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_RI 0x00000100 // Ring Indicator
+#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
+#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
+#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
+#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
+#define UART_FR_BUSY 0x00000008 // UART Busy
+#define UART_FR_DCD 0x00000004 // Data Carrier Detect
+#define UART_FR_DSR 0x00000002 // Data Set Ready
+#define UART_FR_CTS 0x00000001 // Clear To Send
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
+#define UART_LCRH_BRK 0x00000001 // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
+#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
+#define UART_CTL_RTS 0x00000800 // Request to Send
+#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
+#define UART_CTL_RXE 0x00000200 // UART Receive Enable
+#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
+#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
+#define UART_CTL_HSE 0x00000020 // High-Speed Enable
+#define UART_CTL_EOT 0x00000010 // End of Transmission
+#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
+#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
+#define UART_CTL_UARTEN 0x00000001 // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
+ // Level Select
+#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
+ // Level Select
+#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
+#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
+ // Mask
+#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
+#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
+ // Mask
+#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
+ // Mask
+#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
+#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
+#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Mask
+#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Mask
+#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
+ // Interrupt Mask
+#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
+#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
+ // Status
+#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
+ // Status
+#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
+ // Status
+#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
+ // Status
+#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
+ // Interrupt Status
+#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
+ // Status
+#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
+ // Status
+#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
+ // Interrupt Status
+#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
+ // Raw Interrupt Status
+#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
+ // Interrupt Status
+#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
+ // Status
+#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
+ // Interrupt Status
+#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
+ // Interrupt Status
+#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
+ // Interrupt Status
+#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
+ // Interrupt Status
+#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
+ // Interrupt Status
+#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
+ // Status
+#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
+ // Status
+#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
+ // Interrupt Status
+#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
+ // Masked Interrupt Status
+#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
+ // Interrupt Status
+#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
+#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
+#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Clear
+#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Clear
+#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
+ // Interrupt Clear
+#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
+#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITADDR
+// register.
+//
+//*****************************************************************************
+#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
+#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
+#define UART_9BITADDR_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITAMASK
+// register.
+//
+//*****************************************************************************
+#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
+#define UART_9BITAMASK_MASK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_PP register.
+//
+//*****************************************************************************
+#define UART_PP_NB 0x00000002 // 9-Bit Support
+#define UART_PP_SC 0x00000001 // Smart Card Support
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CC register.
+//
+//*****************************************************************************
+#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
+#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default)
+#define UART_CC_CS_PIOSC 0x00000005 // PIOSC
+
+#endif // __HW_UART_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_udma.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_udma.h
new file mode 100644
index 00000000..b7a54030
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_udma.h
@@ -0,0 +1,412 @@
+//*****************************************************************************
+//
+// hw_udma.h - Macros for use in accessing the UDMA registers.
+//
+// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UDMA_H__
+#define __HW_UDMA_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access register
+// addresses.
+//
+//*****************************************************************************
+#define UDMA_STAT 0x400FF000 // DMA Status
+#define UDMA_CFG 0x400FF004 // DMA Configuration
+#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer
+#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control
+ // Base Pointer
+#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request
+ // Status
+#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request
+#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set
+#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear
+#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set
+#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear
+#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set
+#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear
+#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate
+ // Set
+#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate
+ // Clear
+#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
+#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
+#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
+#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment
+#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status
+#define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0
+#define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1
+#define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2
+#define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP \
+ 0x00000020 // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP \
+ 0x00000030 // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT \
+ 0x00000040 // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT \
+ 0x00000050 // Writing destination data
+#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to
+ // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
+#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
+#define UDMA_STAT_STATE_DONE 0x00000090 // Done
+#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
+#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
+#define UDMA_STAT_DMACHANS_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
+ // Pointer
+#define UDMA_ALTBASE_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel
+ // assignment
+#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel
+ // assignment
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHIS register.
+//
+//*****************************************************************************
+#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP0 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
+#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
+#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
+#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
+#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
+#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
+#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
+#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
+#define UDMA_CHMAP0_CH7SEL_S 28
+#define UDMA_CHMAP0_CH6SEL_S 24
+#define UDMA_CHMAP0_CH5SEL_S 20
+#define UDMA_CHMAP0_CH4SEL_S 16
+#define UDMA_CHMAP0_CH3SEL_S 12
+#define UDMA_CHMAP0_CH2SEL_S 8
+#define UDMA_CHMAP0_CH1SEL_S 4
+#define UDMA_CHMAP0_CH0SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP1 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
+#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
+#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
+#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
+#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
+#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
+#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
+#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
+#define UDMA_CHMAP1_CH15SEL_S 28
+#define UDMA_CHMAP1_CH14SEL_S 24
+#define UDMA_CHMAP1_CH13SEL_S 20
+#define UDMA_CHMAP1_CH12SEL_S 16
+#define UDMA_CHMAP1_CH11SEL_S 12
+#define UDMA_CHMAP1_CH10SEL_S 8
+#define UDMA_CHMAP1_CH9SEL_S 4
+#define UDMA_CHMAP1_CH8SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP2 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
+#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
+#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
+#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
+#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
+#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
+#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
+#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
+#define UDMA_CHMAP2_CH23SEL_S 28
+#define UDMA_CHMAP2_CH22SEL_S 24
+#define UDMA_CHMAP2_CH21SEL_S 20
+#define UDMA_CHMAP2_CH20SEL_S 16
+#define UDMA_CHMAP2_CH19SEL_S 12
+#define UDMA_CHMAP2_CH18SEL_S 8
+#define UDMA_CHMAP2_CH17SEL_S 4
+#define UDMA_CHMAP2_CH16SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP3 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
+#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
+#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
+#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
+#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
+#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
+#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
+#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
+#define UDMA_CHMAP3_CH31SEL_S 28
+#define UDMA_CHMAP3_CH30SEL_S 24
+#define UDMA_CHMAP3_CH29SEL_S 20
+#define UDMA_CHMAP3_CH28SEL_S 16
+#define UDMA_CHMAP3_CH27SEL_S 12
+#define UDMA_CHMAP3_CH26SEL_S 8
+#define UDMA_CHMAP3_CH25SEL_S 4
+#define UDMA_CHMAP3_CH24SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
+//
+//*****************************************************************************
+#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
+ // Pointer
+#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
+ // End Pointer
+#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
+#define UDMA_SRCENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
+#define UDMA_DSTENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
+#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
+#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
+#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
+#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
+#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
+#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
+#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
+#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
+#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
+#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
+#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
+#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
+#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
+#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
+#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
+#define UDMA_CHCTL_XFERMODE_STOP \
+ 0x00000000 // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC \
+ 0x00000001 // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO \
+ 0x00000002 // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG \
+ 0x00000003 // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG \
+ 0x00000004 // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA \
+ 0x00000005 // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG \
+ 0x00000006 // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA \
+ 0x00000007 // Alternate Peripheral
+ // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S 4
+
+#endif // __HW_UDMA_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_usb.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_usb.h
new file mode 100644
index 00000000..6b0aa188
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_usb.h
@@ -0,0 +1,2443 @@
+//*****************************************************************************
+//
+// hw_usb.h - Macros for use in accessing the USB registers.
+//
+// Copyright (c) 2007-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_USB_H__
+#define __HW_USB_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Univeral Serial Bus register offsets.
+//
+//*****************************************************************************
+#define USB_O_FADDR 0x00000000 // USB Device Functional Address
+#define USB_O_POWER 0x00000001 // USB Power
+#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status
+#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status
+#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable
+#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable
+#define USB_O_IS 0x0000000A // USB General Interrupt Status
+#define USB_O_IE 0x0000000B // USB Interrupt Enable
+#define USB_O_FRAME 0x0000000C // USB Frame Value
+#define USB_O_EPIDX 0x0000000E // USB Endpoint Index
+#define USB_O_TEST 0x0000000F // USB Test Mode
+#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0
+#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1
+#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2
+#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3
+#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4
+#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5
+#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6
+#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7
+#define USB_O_DEVCTL 0x00000060 // USB Device Control
+#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing
+#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing
+#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address
+#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address
+#define USB_O_EPINFO 0x00000078 // USB Endpoint Information
+#define USB_O_CONTIM 0x0000007A // USB Connect Timing
+#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing
+#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction
+ // to End of Frame Timing
+#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction
+ // to End of Frame Timing
+#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address
+ // Endpoint 0
+#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address
+ // Endpoint 0
+#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0
+#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address
+ // Endpoint 1
+#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address
+ // Endpoint 1
+#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1
+#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address
+ // Endpoint 1
+#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint
+ // 1
+#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1
+#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address
+ // Endpoint 2
+#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address
+ // Endpoint 2
+#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2
+#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address
+ // Endpoint 2
+#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint
+ // 2
+#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2
+#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address
+ // Endpoint 3
+#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address
+ // Endpoint 3
+#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3
+#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address
+ // Endpoint 3
+#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint
+ // 3
+#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3
+#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address
+ // Endpoint 4
+#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address
+ // Endpoint 4
+#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4
+#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address
+ // Endpoint 4
+#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint
+ // 4
+#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4
+#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address
+ // Endpoint 5
+#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address
+ // Endpoint 5
+#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5
+#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address
+ // Endpoint 5
+#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint
+ // 5
+#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5
+#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address
+ // Endpoint 6
+#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address
+ // Endpoint 6
+#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6
+#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address
+ // Endpoint 6
+#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint
+ // 6
+#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6
+#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address
+ // Endpoint 7
+#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address
+ // Endpoint 7
+#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7
+#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address
+ // Endpoint 7
+#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint
+ // 7
+#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7
+#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint
+ // 0 Low
+#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint
+ // 0 High
+#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint
+ // 0
+#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0
+#define USB_O_NAKLMT 0x0000010B // USB NAK Limit
+#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data
+ // Endpoint 1
+#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status
+ // Endpoint 1 Low
+#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status
+ // Endpoint 1 High
+#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data
+ // Endpoint 1
+#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status
+ // Endpoint 1 Low
+#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status
+ // Endpoint 1 High
+#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint
+ // 1
+#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type
+ // Endpoint 1
+#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval
+ // Endpoint 1
+#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type
+ // Endpoint 1
+#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling
+ // Interval Endpoint 1
+#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data
+ // Endpoint 2
+#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status
+ // Endpoint 2 Low
+#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status
+ // Endpoint 2 High
+#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data
+ // Endpoint 2
+#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status
+ // Endpoint 2 Low
+#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status
+ // Endpoint 2 High
+#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint
+ // 2
+#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type
+ // Endpoint 2
+#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval
+ // Endpoint 2
+#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type
+ // Endpoint 2
+#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling
+ // Interval Endpoint 2
+#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data
+ // Endpoint 3
+#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status
+ // Endpoint 3 Low
+#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status
+ // Endpoint 3 High
+#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data
+ // Endpoint 3
+#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status
+ // Endpoint 3 Low
+#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status
+ // Endpoint 3 High
+#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint
+ // 3
+#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type
+ // Endpoint 3
+#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval
+ // Endpoint 3
+#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type
+ // Endpoint 3
+#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling
+ // Interval Endpoint 3
+#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data
+ // Endpoint 4
+#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status
+ // Endpoint 4 Low
+#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status
+ // Endpoint 4 High
+#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data
+ // Endpoint 4
+#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status
+ // Endpoint 4 Low
+#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status
+ // Endpoint 4 High
+#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint
+ // 4
+#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type
+ // Endpoint 4
+#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval
+ // Endpoint 4
+#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type
+ // Endpoint 4
+#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling
+ // Interval Endpoint 4
+#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data
+ // Endpoint 5
+#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status
+ // Endpoint 5 Low
+#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status
+ // Endpoint 5 High
+#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data
+ // Endpoint 5
+#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status
+ // Endpoint 5 Low
+#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status
+ // Endpoint 5 High
+#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint
+ // 5
+#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type
+ // Endpoint 5
+#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval
+ // Endpoint 5
+#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type
+ // Endpoint 5
+#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling
+ // Interval Endpoint 5
+#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data
+ // Endpoint 6
+#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status
+ // Endpoint 6 Low
+#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status
+ // Endpoint 6 High
+#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data
+ // Endpoint 6
+#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status
+ // Endpoint 6 Low
+#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status
+ // Endpoint 6 High
+#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint
+ // 6
+#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type
+ // Endpoint 6
+#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval
+ // Endpoint 6
+#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type
+ // Endpoint 6
+#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling
+ // Interval Endpoint 6
+#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data
+ // Endpoint 7
+#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status
+ // Endpoint 7 Low
+#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status
+ // Endpoint 7 High
+#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data
+ // Endpoint 7
+#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status
+ // Endpoint 7 Low
+#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status
+ // Endpoint 7 High
+#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint
+ // 7
+#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type
+ // Endpoint 7
+#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval
+ // Endpoint 7
+#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type
+ // Endpoint 7
+#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling
+ // Interval Endpoint 7
+#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in
+ // Block Transfer Endpoint 1
+#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in
+ // Block Transfer Endpoint 2
+#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in
+ // Block Transfer Endpoint 3
+#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in
+ // Block Transfer Endpoint 4
+#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in
+ // Block Transfer Endpoint 5
+#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in
+ // Block Transfer Endpoint 6
+#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in
+ // Block Transfer Endpoint 7
+#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer
+ // Disable
+#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet
+ // Buffer Disable
+#define USB_O_EPC 0x00000400 // USB External Power Control
+#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw
+ // Interrupt Status
+#define USB_O_EPCIM 0x00000408 // USB External Power Control
+ // Interrupt Mask
+#define USB_O_EPCISC 0x0000040C // USB External Power Control
+ // Interrupt Status and Clear
+#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt
+ // Status
+#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask
+#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt
+ // Status and Clear
+#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and
+ // Status
+#define USB_O_VDC 0x00000430 // USB VBUS Droop Control
+#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw
+ // Interrupt Status
+#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt
+ // Mask
+#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt
+ // Status and Clear
+#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw
+ // Interrupt Status
+#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt
+ // Mask
+#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt
+ // Status and Clear
+#define USB_O_DMASEL 0x00000450 // USB DMA Select
+#define USB_O_PP 0x00000FC0 // USB Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M 0x0000007F // Function Address
+#define USB_FADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP 0x00000080 // Isochronous Update
+#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect
+#define USB_POWER_RESET 0x00000008 // RESET Signaling
+#define USB_POWER_RESUME 0x00000004 // RESUME Signaling
+#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode
+#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable
+#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR 0x00000080 // VBUS Error
+#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST
+#define USB_IS_DISCON 0x00000020 // Session Disconnect
+#define USB_IS_CONN 0x00000010 // Session Connect
+#define USB_IS_SOF 0x00000008 // Start of Frame
+#define USB_IS_BABBLE 0x00000004 // Babble Detected
+#define USB_IS_RESET 0x00000004 // RESET Signaling Detected
+#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected
+#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt
+#define USB_IE_SESREQ 0x00000040 // Enable Session Request
+#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt
+#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt
+#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt
+#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt
+#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt
+#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M 0x000007FF // Frame Number
+#define USB_FRAME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index
+#define USB_EPIDX_EPIDX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH 0x00000080 // Force Host Mode
+#define USB_TEST_FIFOACC 0x00000040 // FIFO Access
+#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO0_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO1_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO2_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO3_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO4_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO5_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO6_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO7_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV 0x00000080 // Device Mode
+#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level
+#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid
+#define USB_DEVCTL_HOST 0x00000004 // Host Mode
+#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request
+#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
+#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
+#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPINFO register.
+//
+//*****************************************************************************
+#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints
+#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints
+#define USB_EPINFO_RXEP_S 4
+#define USB_EPINFO_TXEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait
+#define USB_CONTIM_WTID_M 0x0000000F // Wait ID
+#define USB_CONTIM_WTCON_S 4
+#define USB_CONTIM_WTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length
+#define USB_VPLEN_VPLEN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap
+#define USB_FSEOF_FSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap
+#define USB_LSEOF_LSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT0_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout
+#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear
+#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet
+#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear
+#define USB_CSRL0_REQPKT 0x00000020 // Request Packet
+#define USB_CSRL0_STALL 0x00000020 // Send Stall
+#define USB_CSRL0_SETEND 0x00000010 // Setup End
+#define USB_CSRL0_ERROR 0x00000010 // Error
+#define USB_CSRL0_DATAEND 0x00000008 // Data End
+#define USB_CSRL0_SETUP 0x00000008 // Setup Packet
+#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled
+#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready
+#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_CSRH0_DT 0x00000002 // Data Toggle
+#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count
+#define USB_COUNT0_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TYPE0_SPEED_FULL 0x00000080 // Full
+#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit
+#define USB_NAKLMT_NAKLMT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL1_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL1_ERROR 0x00000004 // Error
+#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH1_MODE 0x00000020 // Mode
+#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH1_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL1_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL1_OVER 0x00000004 // Overrun
+#define USB_RXCSRL1_ERROR 0x00000004 // Error
+#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH1_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT1_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL1_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL2_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL2_ERROR 0x00000004 // Error
+#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH2_MODE 0x00000020 // Mode
+#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH2_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL2_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL2_ERROR 0x00000004 // Error
+#define USB_RXCSRL2_OVER 0x00000004 // Overrun
+#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH2_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT2_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL2_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL2_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL2_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL2_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL3_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL3_ERROR 0x00000004 // Error
+#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH3_MODE 0x00000020 // Mode
+#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH3_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL3_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL3_ERROR 0x00000004 // Error
+#define USB_RXCSRL3_OVER 0x00000004 // Overrun
+#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH3_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT3_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL4_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL4_ERROR 0x00000004 // Error
+#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH4_MODE 0x00000020 // Mode
+#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH4_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL4_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL4_OVER 0x00000004 // Overrun
+#define USB_RXCSRL4_ERROR 0x00000004 // Error
+#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH4_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL5_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL5_ERROR 0x00000004 // Error
+#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH5_MODE 0x00000020 // Mode
+#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH5_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL5_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL5_ERROR 0x00000004 // Error
+#define USB_RXCSRL5_OVER 0x00000004 // Overrun
+#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH5_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL5_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL5_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL5_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL5_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL6_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL6_ERROR 0x00000004 // Error
+#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH6_MODE 0x00000020 // Mode
+#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH6_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL6_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL6_ERROR 0x00000004 // Error
+#define USB_RXCSRL6_OVER 0x00000004 // Overrun
+#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH6_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL6_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL6_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL6_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL6_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL7_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL7_ERROR 0x00000004 // Error
+#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH7_MODE 0x00000020 // Mode
+#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH7_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL7_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL7_ERROR 0x00000004 // Error
+#define USB_RXCSRL7_OVER 0x00000004 // Overrun
+#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH7_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT2_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT3_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
+ // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
+ // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action
+#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged
+#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate
+#define USB_EPC_PFLTACT_LOW 0x00000200 // Low
+#define USB_EPC_PFLTACT_HIGH 0x00000300 // High
+#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense
+#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable
+#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable
+#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable
+ // Configuration
+#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low
+#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode
+#define USB_GPCS_DEVMOD 0x00000001 // Device Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVRIS register.
+//
+//*****************************************************************************
+#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVIM register.
+//
+//*****************************************************************************
+#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVISC register.
+//
+//*****************************************************************************
+#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMASEL register.
+//
+//*****************************************************************************
+#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select
+#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select
+#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select
+#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select
+#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select
+#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select
+#define USB_DMASEL_DMACTX_S 20
+#define USB_DMASEL_DMACRX_S 16
+#define USB_DMASEL_DMABTX_S 12
+#define USB_DMASEL_DMABRX_S 8
+#define USB_DMASEL_DMAATX_S 4
+#define USB_DMASEL_DMAARX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PP register.
+//
+//*****************************************************************************
+#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count
+#define USB_PP_USB_M 0x000000C0 // USB Capability
+#define USB_PP_USB_DEVICE 0x00000040 // DEVICE
+#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST
+#define USB_PP_USB_OTG 0x000000C0 // OTG
+#define USB_PP_PHY 0x00000010 // PHY Present
+#define USB_PP_TYPE_M 0x0000000F // Controller Type
+#define USB_PP_TYPE_0 0x00000000 // The first-generation USB
+ // controller
+#define USB_PP_ECNT_S 8
+
+#endif // __HW_USB_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_watchdog.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_watchdog.h
new file mode 100644
index 00000000..c7191510
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/hw_watchdog.h
@@ -0,0 +1,122 @@
+//*****************************************************************************
+//
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
+//
+// Copyright (c) 2005-2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_WATCHDOG_H__
+#define __HW_WATCHDOG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Watchdog Timer register offsets.
+//
+//*****************************************************************************
+#define WDT_O_LOAD 0x00000000 // Watchdog Load
+#define WDT_O_VALUE 0x00000004 // Watchdog Value
+#define WDT_O_CTL 0x00000008 // Watchdog Control
+#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear
+#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status
+#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status
+#define WDT_O_TEST 0x00000418 // Watchdog Test
+#define WDT_O_LOCK 0x00000C00 // Watchdog Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
+#define WDT_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
+#define WDT_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC 0x80000000 // Write Complete
+#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
+#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
+#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
+#define WDT_ICR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
+#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WDT_LOCK_LOCKED 0x00000001 // Locked
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
+
+#endif // __HW_WATCHDOG_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/tm4c123gh6pge.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/tm4c123gh6pge.h
new file mode 100644
index 00000000..8e606c1f
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/lib/inc/tm4c123gh6pge.h
@@ -0,0 +1,13754 @@
+//*****************************************************************************
+//
+// tm4c123gh6pge.h - TM4C123GH6PGE Register Definitions
+//
+// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.1 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __TM4C123GH6PGE_H__
+#define __TM4C123GH6PGE_H__
+
+//*****************************************************************************
+//
+// Interrupt assignments
+//
+//*****************************************************************************
+#define INT_GPIOA 16 // GPIO Port A
+#define INT_GPIOB 17 // GPIO Port B
+#define INT_GPIOC 18 // GPIO Port C
+#define INT_GPIOD 19 // GPIO Port D
+#define INT_GPIOE 20 // GPIO Port E
+#define INT_UART0 21 // UART0
+#define INT_UART1 22 // UART1
+#define INT_SSI0 23 // SSI0
+#define INT_I2C0 24 // I2C0
+#define INT_PWM0_FAULT 25 // PWM0 Fault
+#define INT_PWM0_0 26 // PWM0 Generator 0
+#define INT_PWM0_1 27 // PWM0 Generator 1
+#define INT_PWM0_2 28 // PWM0 Generator 2
+#define INT_QEI0 29 // QEI0
+#define INT_ADC0SS0 30 // ADC0 Sequence 0
+#define INT_ADC0SS1 31 // ADC0 Sequence 1
+#define INT_ADC0SS2 32 // ADC0 Sequence 2
+#define INT_ADC0SS3 33 // ADC0 Sequence 3
+#define INT_WATCHDOG 34 // Watchdog Timers 0 and 1
+#define INT_TIMER0A 35 // 16/32-Bit Timer 0A
+#define INT_TIMER0B 36 // 16/32-Bit Timer 0B
+#define INT_TIMER1A 37 // 16/32-Bit Timer 1A
+#define INT_TIMER1B 38 // 16/32-Bit Timer 1B
+#define INT_TIMER2A 39 // 16/32-Bit Timer 2A
+#define INT_TIMER2B 40 // 16/32-Bit Timer 2B
+#define INT_COMP0 41 // Analog Comparator 0
+#define INT_COMP1 42 // Analog Comparator 1
+#define INT_COMP2 43 // Analog Comparator 2
+#define INT_SYSCTL 44 // System Control
+#define INT_FLASH 45 // Flash Memory Control and EEPROM
+ // Control
+#define INT_GPIOF 46 // GPIO Port F
+#define INT_GPIOG 47 // GPIO Port G
+#define INT_GPIOH 48 // GPIO Port H
+#define INT_UART2 49 // UART2
+#define INT_SSI1 50 // SSI1
+#define INT_TIMER3A 51 // Timer 3A
+#define INT_TIMER3B 52 // Timer 3B
+#define INT_I2C1 53 // I2C1
+#define INT_QEI1 54 // QEI1
+#define INT_CAN0 55 // CAN0
+#define INT_CAN1 56 // CAN1
+#define INT_HIBERNATE 59 // Hibernation Module
+#define INT_USB0 60 // USB
+#define INT_PWM0_3 61 // PWM Generator 3
+#define INT_UDMA 62 // uDMA Software
+#define INT_UDMAERR 63 // uDMA Error
+#define INT_ADC1SS0 64 // ADC1 Sequence 0
+#define INT_ADC1SS1 65 // ADC1 Sequence 1
+#define INT_ADC1SS2 66 // ADC1 Sequence 2
+#define INT_ADC1SS3 67 // ADC1 Sequence 3
+#define INT_GPIOJ 70 // GPIO Port J
+#define INT_GPIOK 71 // GPIO Port K
+#define INT_GPIOL 72 // GPIO Port L
+#define INT_SSI2 73 // SSI2
+#define INT_SSI3 74 // SSI3
+#define INT_UART3 75 // UART3
+#define INT_UART4 76 // UART4
+#define INT_UART5 77 // UART5
+#define INT_UART6 78 // UART6
+#define INT_UART7 79 // UART7
+#define INT_I2C2 84 // I2C2
+#define INT_I2C3 85 // I2C3
+#define INT_TIMER4A 86 // 16/32-Bit Timer 4A
+#define INT_TIMER4B 87 // 16/32-Bit Timer 4B
+#define INT_TIMER5A 108 // 16/32-Bit Timer 5A
+#define INT_TIMER5B 109 // 16/32-Bit Timer 5B
+#define INT_WTIMER0A 110 // 32/64-Bit Timer 0A
+#define INT_WTIMER0B 111 // 32/64-Bit Timer 0B
+#define INT_WTIMER1A 112 // 32/64-Bit Timer 1A
+#define INT_WTIMER1B 113 // 32/64-Bit Timer 1B
+#define INT_WTIMER2A 114 // 32/64-Bit Timer 2A
+#define INT_WTIMER2B 115 // 32/64-Bit Timer 2B
+#define INT_WTIMER3A 116 // 32/64-Bit Timer 3A
+#define INT_WTIMER3B 117 // 32/64-Bit Timer 3B
+#define INT_WTIMER4A 118 // 32/64-Bit Timer 4A
+#define INT_WTIMER4B 119 // 32/64-Bit Timer 4B
+#define INT_WTIMER5A 120 // 32/64-Bit Timer 5A
+#define INT_WTIMER5B 121 // 32/64-Bit Timer 5B
+#define INT_SYSEXC 122 // System Exception (imprecise)
+#define INT_I2C4 125 // I2C4
+#define INT_I2C5 126 // I2C5
+#define INT_GPIOM 127 // GPIO Port M
+#define INT_GPION 128 // GPIO Port N
+#define INT_GPIOP0 132 // GPIO Port P (Summary or P0)
+#define INT_GPIOP1 133 // GPIO Port P1
+#define INT_GPIOP2 134 // GPIO Port P2
+#define INT_GPIOP3 135 // GPIO Port P3
+#define INT_GPIOP4 136 // GPIO Port P4
+#define INT_GPIOP5 137 // GPIO Port P5
+#define INT_GPIOP6 138 // GPIO Port P6
+#define INT_GPIOP7 139 // GPIO Port P7
+#define INT_PWM1_0 150 // PWM1 Generator 0
+#define INT_PWM1_1 151 // PWM1 Generator 1
+#define INT_PWM1_2 152 // PWM1 Generator 2
+#define INT_PWM1_3 153 // PWM1 Generator 3
+#define INT_PWM1_FAULT 154 // PWM1 Fault
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG0)
+//
+//*****************************************************************************
+#define WATCHDOG0_LOAD_R (*((volatile uint32_t *)0x40000000))
+#define WATCHDOG0_VALUE_R (*((volatile uint32_t *)0x40000004))
+#define WATCHDOG0_CTL_R (*((volatile uint32_t *)0x40000008))
+#define WATCHDOG0_ICR_R (*((volatile uint32_t *)0x4000000C))
+#define WATCHDOG0_RIS_R (*((volatile uint32_t *)0x40000010))
+#define WATCHDOG0_MIS_R (*((volatile uint32_t *)0x40000014))
+#define WATCHDOG0_TEST_R (*((volatile uint32_t *)0x40000418))
+#define WATCHDOG0_LOCK_R (*((volatile uint32_t *)0x40000C00))
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG1)
+//
+//*****************************************************************************
+#define WATCHDOG1_LOAD_R (*((volatile uint32_t *)0x40001000))
+#define WATCHDOG1_VALUE_R (*((volatile uint32_t *)0x40001004))
+#define WATCHDOG1_CTL_R (*((volatile uint32_t *)0x40001008))
+#define WATCHDOG1_ICR_R (*((volatile uint32_t *)0x4000100C))
+#define WATCHDOG1_RIS_R (*((volatile uint32_t *)0x40001010))
+#define WATCHDOG1_MIS_R (*((volatile uint32_t *)0x40001014))
+#define WATCHDOG1_TEST_R (*((volatile uint32_t *)0x40001418))
+#define WATCHDOG1_LOCK_R (*((volatile uint32_t *)0x40001C00))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTA)
+//
+//*****************************************************************************
+#define GPIO_PORTA_DATA_BITS_R ((volatile uint32_t *)0x40004000)
+#define GPIO_PORTA_DATA_R (*((volatile uint32_t *)0x400043FC))
+#define GPIO_PORTA_DIR_R (*((volatile uint32_t *)0x40004400))
+#define GPIO_PORTA_IS_R (*((volatile uint32_t *)0x40004404))
+#define GPIO_PORTA_IBE_R (*((volatile uint32_t *)0x40004408))
+#define GPIO_PORTA_IEV_R (*((volatile uint32_t *)0x4000440C))
+#define GPIO_PORTA_IM_R (*((volatile uint32_t *)0x40004410))
+#define GPIO_PORTA_RIS_R (*((volatile uint32_t *)0x40004414))
+#define GPIO_PORTA_MIS_R (*((volatile uint32_t *)0x40004418))
+#define GPIO_PORTA_ICR_R (*((volatile uint32_t *)0x4000441C))
+#define GPIO_PORTA_AFSEL_R (*((volatile uint32_t *)0x40004420))
+#define GPIO_PORTA_DR2R_R (*((volatile uint32_t *)0x40004500))
+#define GPIO_PORTA_DR4R_R (*((volatile uint32_t *)0x40004504))
+#define GPIO_PORTA_DR8R_R (*((volatile uint32_t *)0x40004508))
+#define GPIO_PORTA_ODR_R (*((volatile uint32_t *)0x4000450C))
+#define GPIO_PORTA_PUR_R (*((volatile uint32_t *)0x40004510))
+#define GPIO_PORTA_PDR_R (*((volatile uint32_t *)0x40004514))
+#define GPIO_PORTA_SLR_R (*((volatile uint32_t *)0x40004518))
+#define GPIO_PORTA_DEN_R (*((volatile uint32_t *)0x4000451C))
+#define GPIO_PORTA_LOCK_R (*((volatile uint32_t *)0x40004520))
+#define GPIO_PORTA_CR_R (*((volatile uint32_t *)0x40004524))
+#define GPIO_PORTA_AMSEL_R (*((volatile uint32_t *)0x40004528))
+#define GPIO_PORTA_PCTL_R (*((volatile uint32_t *)0x4000452C))
+#define GPIO_PORTA_ADCCTL_R (*((volatile uint32_t *)0x40004530))
+#define GPIO_PORTA_DMACTL_R (*((volatile uint32_t *)0x40004534))
+#define GPIO_PORTA_SI_R (*((volatile uint32_t *)0x40004538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_DATA_BITS_R ((volatile uint32_t *)0x40005000)
+#define GPIO_PORTB_DATA_R (*((volatile uint32_t *)0x400053FC))
+#define GPIO_PORTB_DIR_R (*((volatile uint32_t *)0x40005400))
+#define GPIO_PORTB_IS_R (*((volatile uint32_t *)0x40005404))
+#define GPIO_PORTB_IBE_R (*((volatile uint32_t *)0x40005408))
+#define GPIO_PORTB_IEV_R (*((volatile uint32_t *)0x4000540C))
+#define GPIO_PORTB_IM_R (*((volatile uint32_t *)0x40005410))
+#define GPIO_PORTB_RIS_R (*((volatile uint32_t *)0x40005414))
+#define GPIO_PORTB_MIS_R (*((volatile uint32_t *)0x40005418))
+#define GPIO_PORTB_ICR_R (*((volatile uint32_t *)0x4000541C))
+#define GPIO_PORTB_AFSEL_R (*((volatile uint32_t *)0x40005420))
+#define GPIO_PORTB_DR2R_R (*((volatile uint32_t *)0x40005500))
+#define GPIO_PORTB_DR4R_R (*((volatile uint32_t *)0x40005504))
+#define GPIO_PORTB_DR8R_R (*((volatile uint32_t *)0x40005508))
+#define GPIO_PORTB_ODR_R (*((volatile uint32_t *)0x4000550C))
+#define GPIO_PORTB_PUR_R (*((volatile uint32_t *)0x40005510))
+#define GPIO_PORTB_PDR_R (*((volatile uint32_t *)0x40005514))
+#define GPIO_PORTB_SLR_R (*((volatile uint32_t *)0x40005518))
+#define GPIO_PORTB_DEN_R (*((volatile uint32_t *)0x4000551C))
+#define GPIO_PORTB_LOCK_R (*((volatile uint32_t *)0x40005520))
+#define GPIO_PORTB_CR_R (*((volatile uint32_t *)0x40005524))
+#define GPIO_PORTB_AMSEL_R (*((volatile uint32_t *)0x40005528))
+#define GPIO_PORTB_PCTL_R (*((volatile uint32_t *)0x4000552C))
+#define GPIO_PORTB_ADCCTL_R (*((volatile uint32_t *)0x40005530))
+#define GPIO_PORTB_DMACTL_R (*((volatile uint32_t *)0x40005534))
+#define GPIO_PORTB_SI_R (*((volatile uint32_t *)0x40005538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTC)
+//
+//*****************************************************************************
+#define GPIO_PORTC_DATA_BITS_R ((volatile uint32_t *)0x40006000)
+#define GPIO_PORTC_DATA_R (*((volatile uint32_t *)0x400063FC))
+#define GPIO_PORTC_DIR_R (*((volatile uint32_t *)0x40006400))
+#define GPIO_PORTC_IS_R (*((volatile uint32_t *)0x40006404))
+#define GPIO_PORTC_IBE_R (*((volatile uint32_t *)0x40006408))
+#define GPIO_PORTC_IEV_R (*((volatile uint32_t *)0x4000640C))
+#define GPIO_PORTC_IM_R (*((volatile uint32_t *)0x40006410))
+#define GPIO_PORTC_RIS_R (*((volatile uint32_t *)0x40006414))
+#define GPIO_PORTC_MIS_R (*((volatile uint32_t *)0x40006418))
+#define GPIO_PORTC_ICR_R (*((volatile uint32_t *)0x4000641C))
+#define GPIO_PORTC_AFSEL_R (*((volatile uint32_t *)0x40006420))
+#define GPIO_PORTC_DR2R_R (*((volatile uint32_t *)0x40006500))
+#define GPIO_PORTC_DR4R_R (*((volatile uint32_t *)0x40006504))
+#define GPIO_PORTC_DR8R_R (*((volatile uint32_t *)0x40006508))
+#define GPIO_PORTC_ODR_R (*((volatile uint32_t *)0x4000650C))
+#define GPIO_PORTC_PUR_R (*((volatile uint32_t *)0x40006510))
+#define GPIO_PORTC_PDR_R (*((volatile uint32_t *)0x40006514))
+#define GPIO_PORTC_SLR_R (*((volatile uint32_t *)0x40006518))
+#define GPIO_PORTC_DEN_R (*((volatile uint32_t *)0x4000651C))
+#define GPIO_PORTC_LOCK_R (*((volatile uint32_t *)0x40006520))
+#define GPIO_PORTC_CR_R (*((volatile uint32_t *)0x40006524))
+#define GPIO_PORTC_AMSEL_R (*((volatile uint32_t *)0x40006528))
+#define GPIO_PORTC_PCTL_R (*((volatile uint32_t *)0x4000652C))
+#define GPIO_PORTC_ADCCTL_R (*((volatile uint32_t *)0x40006530))
+#define GPIO_PORTC_DMACTL_R (*((volatile uint32_t *)0x40006534))
+#define GPIO_PORTC_SI_R (*((volatile uint32_t *)0x40006538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTD)
+//
+//*****************************************************************************
+#define GPIO_PORTD_DATA_BITS_R ((volatile uint32_t *)0x40007000)
+#define GPIO_PORTD_DATA_R (*((volatile uint32_t *)0x400073FC))
+#define GPIO_PORTD_DIR_R (*((volatile uint32_t *)0x40007400))
+#define GPIO_PORTD_IS_R (*((volatile uint32_t *)0x40007404))
+#define GPIO_PORTD_IBE_R (*((volatile uint32_t *)0x40007408))
+#define GPIO_PORTD_IEV_R (*((volatile uint32_t *)0x4000740C))
+#define GPIO_PORTD_IM_R (*((volatile uint32_t *)0x40007410))
+#define GPIO_PORTD_RIS_R (*((volatile uint32_t *)0x40007414))
+#define GPIO_PORTD_MIS_R (*((volatile uint32_t *)0x40007418))
+#define GPIO_PORTD_ICR_R (*((volatile uint32_t *)0x4000741C))
+#define GPIO_PORTD_AFSEL_R (*((volatile uint32_t *)0x40007420))
+#define GPIO_PORTD_DR2R_R (*((volatile uint32_t *)0x40007500))
+#define GPIO_PORTD_DR4R_R (*((volatile uint32_t *)0x40007504))
+#define GPIO_PORTD_DR8R_R (*((volatile uint32_t *)0x40007508))
+#define GPIO_PORTD_ODR_R (*((volatile uint32_t *)0x4000750C))
+#define GPIO_PORTD_PUR_R (*((volatile uint32_t *)0x40007510))
+#define GPIO_PORTD_PDR_R (*((volatile uint32_t *)0x40007514))
+#define GPIO_PORTD_SLR_R (*((volatile uint32_t *)0x40007518))
+#define GPIO_PORTD_DEN_R (*((volatile uint32_t *)0x4000751C))
+#define GPIO_PORTD_LOCK_R (*((volatile uint32_t *)0x40007520))
+#define GPIO_PORTD_CR_R (*((volatile uint32_t *)0x40007524))
+#define GPIO_PORTD_AMSEL_R (*((volatile uint32_t *)0x40007528))
+#define GPIO_PORTD_PCTL_R (*((volatile uint32_t *)0x4000752C))
+#define GPIO_PORTD_ADCCTL_R (*((volatile uint32_t *)0x40007530))
+#define GPIO_PORTD_DMACTL_R (*((volatile uint32_t *)0x40007534))
+#define GPIO_PORTD_SI_R (*((volatile uint32_t *)0x40007538))
+
+//*****************************************************************************
+//
+// SSI registers (SSI0)
+//
+//*****************************************************************************
+#define SSI0_CR0_R (*((volatile uint32_t *)0x40008000))
+#define SSI0_CR1_R (*((volatile uint32_t *)0x40008004))
+#define SSI0_DR_R (*((volatile uint32_t *)0x40008008))
+#define SSI0_SR_R (*((volatile uint32_t *)0x4000800C))
+#define SSI0_CPSR_R (*((volatile uint32_t *)0x40008010))
+#define SSI0_IM_R (*((volatile uint32_t *)0x40008014))
+#define SSI0_RIS_R (*((volatile uint32_t *)0x40008018))
+#define SSI0_MIS_R (*((volatile uint32_t *)0x4000801C))
+#define SSI0_ICR_R (*((volatile uint32_t *)0x40008020))
+#define SSI0_DMACTL_R (*((volatile uint32_t *)0x40008024))
+#define SSI0_CC_R (*((volatile uint32_t *)0x40008FC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI1)
+//
+//*****************************************************************************
+#define SSI1_CR0_R (*((volatile uint32_t *)0x40009000))
+#define SSI1_CR1_R (*((volatile uint32_t *)0x40009004))
+#define SSI1_DR_R (*((volatile uint32_t *)0x40009008))
+#define SSI1_SR_R (*((volatile uint32_t *)0x4000900C))
+#define SSI1_CPSR_R (*((volatile uint32_t *)0x40009010))
+#define SSI1_IM_R (*((volatile uint32_t *)0x40009014))
+#define SSI1_RIS_R (*((volatile uint32_t *)0x40009018))
+#define SSI1_MIS_R (*((volatile uint32_t *)0x4000901C))
+#define SSI1_ICR_R (*((volatile uint32_t *)0x40009020))
+#define SSI1_DMACTL_R (*((volatile uint32_t *)0x40009024))
+#define SSI1_CC_R (*((volatile uint32_t *)0x40009FC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI2)
+//
+//*****************************************************************************
+#define SSI2_CR0_R (*((volatile uint32_t *)0x4000A000))
+#define SSI2_CR1_R (*((volatile uint32_t *)0x4000A004))
+#define SSI2_DR_R (*((volatile uint32_t *)0x4000A008))
+#define SSI2_SR_R (*((volatile uint32_t *)0x4000A00C))
+#define SSI2_CPSR_R (*((volatile uint32_t *)0x4000A010))
+#define SSI2_IM_R (*((volatile uint32_t *)0x4000A014))
+#define SSI2_RIS_R (*((volatile uint32_t *)0x4000A018))
+#define SSI2_MIS_R (*((volatile uint32_t *)0x4000A01C))
+#define SSI2_ICR_R (*((volatile uint32_t *)0x4000A020))
+#define SSI2_DMACTL_R (*((volatile uint32_t *)0x4000A024))
+#define SSI2_CC_R (*((volatile uint32_t *)0x4000AFC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI3)
+//
+//*****************************************************************************
+#define SSI3_CR0_R (*((volatile uint32_t *)0x4000B000))
+#define SSI3_CR1_R (*((volatile uint32_t *)0x4000B004))
+#define SSI3_DR_R (*((volatile uint32_t *)0x4000B008))
+#define SSI3_SR_R (*((volatile uint32_t *)0x4000B00C))
+#define SSI3_CPSR_R (*((volatile uint32_t *)0x4000B010))
+#define SSI3_IM_R (*((volatile uint32_t *)0x4000B014))
+#define SSI3_RIS_R (*((volatile uint32_t *)0x4000B018))
+#define SSI3_MIS_R (*((volatile uint32_t *)0x4000B01C))
+#define SSI3_ICR_R (*((volatile uint32_t *)0x4000B020))
+#define SSI3_DMACTL_R (*((volatile uint32_t *)0x4000B024))
+#define SSI3_CC_R (*((volatile uint32_t *)0x4000BFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART0)
+//
+//*****************************************************************************
+#define UART0_DR_R (*((volatile uint32_t *)0x4000C000))
+#define UART0_RSR_R (*((volatile uint32_t *)0x4000C004))
+#define UART0_ECR_R (*((volatile uint32_t *)0x4000C004))
+#define UART0_FR_R (*((volatile uint32_t *)0x4000C018))
+#define UART0_ILPR_R (*((volatile uint32_t *)0x4000C020))
+#define UART0_IBRD_R (*((volatile uint32_t *)0x4000C024))
+#define UART0_FBRD_R (*((volatile uint32_t *)0x4000C028))
+#define UART0_LCRH_R (*((volatile uint32_t *)0x4000C02C))
+#define UART0_CTL_R (*((volatile uint32_t *)0x4000C030))
+#define UART0_IFLS_R (*((volatile uint32_t *)0x4000C034))
+#define UART0_IM_R (*((volatile uint32_t *)0x4000C038))
+#define UART0_RIS_R (*((volatile uint32_t *)0x4000C03C))
+#define UART0_MIS_R (*((volatile uint32_t *)0x4000C040))
+#define UART0_ICR_R (*((volatile uint32_t *)0x4000C044))
+#define UART0_DMACTL_R (*((volatile uint32_t *)0x4000C048))
+#define UART0_9BITADDR_R (*((volatile uint32_t *)0x4000C0A4))
+#define UART0_9BITAMASK_R (*((volatile uint32_t *)0x4000C0A8))
+#define UART0_PP_R (*((volatile uint32_t *)0x4000CFC0))
+#define UART0_CC_R (*((volatile uint32_t *)0x4000CFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART1)
+//
+//*****************************************************************************
+#define UART1_DR_R (*((volatile uint32_t *)0x4000D000))
+#define UART1_RSR_R (*((volatile uint32_t *)0x4000D004))
+#define UART1_ECR_R (*((volatile uint32_t *)0x4000D004))
+#define UART1_FR_R (*((volatile uint32_t *)0x4000D018))
+#define UART1_ILPR_R (*((volatile uint32_t *)0x4000D020))
+#define UART1_IBRD_R (*((volatile uint32_t *)0x4000D024))
+#define UART1_FBRD_R (*((volatile uint32_t *)0x4000D028))
+#define UART1_LCRH_R (*((volatile uint32_t *)0x4000D02C))
+#define UART1_CTL_R (*((volatile uint32_t *)0x4000D030))
+#define UART1_IFLS_R (*((volatile uint32_t *)0x4000D034))
+#define UART1_IM_R (*((volatile uint32_t *)0x4000D038))
+#define UART1_RIS_R (*((volatile uint32_t *)0x4000D03C))
+#define UART1_MIS_R (*((volatile uint32_t *)0x4000D040))
+#define UART1_ICR_R (*((volatile uint32_t *)0x4000D044))
+#define UART1_DMACTL_R (*((volatile uint32_t *)0x4000D048))
+#define UART1_9BITADDR_R (*((volatile uint32_t *)0x4000D0A4))
+#define UART1_9BITAMASK_R (*((volatile uint32_t *)0x4000D0A8))
+#define UART1_PP_R (*((volatile uint32_t *)0x4000DFC0))
+#define UART1_CC_R (*((volatile uint32_t *)0x4000DFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART2)
+//
+//*****************************************************************************
+#define UART2_DR_R (*((volatile uint32_t *)0x4000E000))
+#define UART2_RSR_R (*((volatile uint32_t *)0x4000E004))
+#define UART2_ECR_R (*((volatile uint32_t *)0x4000E004))
+#define UART2_FR_R (*((volatile uint32_t *)0x4000E018))
+#define UART2_ILPR_R (*((volatile uint32_t *)0x4000E020))
+#define UART2_IBRD_R (*((volatile uint32_t *)0x4000E024))
+#define UART2_FBRD_R (*((volatile uint32_t *)0x4000E028))
+#define UART2_LCRH_R (*((volatile uint32_t *)0x4000E02C))
+#define UART2_CTL_R (*((volatile uint32_t *)0x4000E030))
+#define UART2_IFLS_R (*((volatile uint32_t *)0x4000E034))
+#define UART2_IM_R (*((volatile uint32_t *)0x4000E038))
+#define UART2_RIS_R (*((volatile uint32_t *)0x4000E03C))
+#define UART2_MIS_R (*((volatile uint32_t *)0x4000E040))
+#define UART2_ICR_R (*((volatile uint32_t *)0x4000E044))
+#define UART2_DMACTL_R (*((volatile uint32_t *)0x4000E048))
+#define UART2_9BITADDR_R (*((volatile uint32_t *)0x4000E0A4))
+#define UART2_9BITAMASK_R (*((volatile uint32_t *)0x4000E0A8))
+#define UART2_PP_R (*((volatile uint32_t *)0x4000EFC0))
+#define UART2_CC_R (*((volatile uint32_t *)0x4000EFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART3)
+//
+//*****************************************************************************
+#define UART3_DR_R (*((volatile uint32_t *)0x4000F000))
+#define UART3_RSR_R (*((volatile uint32_t *)0x4000F004))
+#define UART3_ECR_R (*((volatile uint32_t *)0x4000F004))
+#define UART3_FR_R (*((volatile uint32_t *)0x4000F018))
+#define UART3_ILPR_R (*((volatile uint32_t *)0x4000F020))
+#define UART3_IBRD_R (*((volatile uint32_t *)0x4000F024))
+#define UART3_FBRD_R (*((volatile uint32_t *)0x4000F028))
+#define UART3_LCRH_R (*((volatile uint32_t *)0x4000F02C))
+#define UART3_CTL_R (*((volatile uint32_t *)0x4000F030))
+#define UART3_IFLS_R (*((volatile uint32_t *)0x4000F034))
+#define UART3_IM_R (*((volatile uint32_t *)0x4000F038))
+#define UART3_RIS_R (*((volatile uint32_t *)0x4000F03C))
+#define UART3_MIS_R (*((volatile uint32_t *)0x4000F040))
+#define UART3_ICR_R (*((volatile uint32_t *)0x4000F044))
+#define UART3_DMACTL_R (*((volatile uint32_t *)0x4000F048))
+#define UART3_9BITADDR_R (*((volatile uint32_t *)0x4000F0A4))
+#define UART3_9BITAMASK_R (*((volatile uint32_t *)0x4000F0A8))
+#define UART3_PP_R (*((volatile uint32_t *)0x4000FFC0))
+#define UART3_CC_R (*((volatile uint32_t *)0x4000FFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART4)
+//
+//*****************************************************************************
+#define UART4_DR_R (*((volatile uint32_t *)0x40010000))
+#define UART4_RSR_R (*((volatile uint32_t *)0x40010004))
+#define UART4_ECR_R (*((volatile uint32_t *)0x40010004))
+#define UART4_FR_R (*((volatile uint32_t *)0x40010018))
+#define UART4_ILPR_R (*((volatile uint32_t *)0x40010020))
+#define UART4_IBRD_R (*((volatile uint32_t *)0x40010024))
+#define UART4_FBRD_R (*((volatile uint32_t *)0x40010028))
+#define UART4_LCRH_R (*((volatile uint32_t *)0x4001002C))
+#define UART4_CTL_R (*((volatile uint32_t *)0x40010030))
+#define UART4_IFLS_R (*((volatile uint32_t *)0x40010034))
+#define UART4_IM_R (*((volatile uint32_t *)0x40010038))
+#define UART4_RIS_R (*((volatile uint32_t *)0x4001003C))
+#define UART4_MIS_R (*((volatile uint32_t *)0x40010040))
+#define UART4_ICR_R (*((volatile uint32_t *)0x40010044))
+#define UART4_DMACTL_R (*((volatile uint32_t *)0x40010048))
+#define UART4_9BITADDR_R (*((volatile uint32_t *)0x400100A4))
+#define UART4_9BITAMASK_R (*((volatile uint32_t *)0x400100A8))
+#define UART4_PP_R (*((volatile uint32_t *)0x40010FC0))
+#define UART4_CC_R (*((volatile uint32_t *)0x40010FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART5)
+//
+//*****************************************************************************
+#define UART5_DR_R (*((volatile uint32_t *)0x40011000))
+#define UART5_RSR_R (*((volatile uint32_t *)0x40011004))
+#define UART5_ECR_R (*((volatile uint32_t *)0x40011004))
+#define UART5_FR_R (*((volatile uint32_t *)0x40011018))
+#define UART5_ILPR_R (*((volatile uint32_t *)0x40011020))
+#define UART5_IBRD_R (*((volatile uint32_t *)0x40011024))
+#define UART5_FBRD_R (*((volatile uint32_t *)0x40011028))
+#define UART5_LCRH_R (*((volatile uint32_t *)0x4001102C))
+#define UART5_CTL_R (*((volatile uint32_t *)0x40011030))
+#define UART5_IFLS_R (*((volatile uint32_t *)0x40011034))
+#define UART5_IM_R (*((volatile uint32_t *)0x40011038))
+#define UART5_RIS_R (*((volatile uint32_t *)0x4001103C))
+#define UART5_MIS_R (*((volatile uint32_t *)0x40011040))
+#define UART5_ICR_R (*((volatile uint32_t *)0x40011044))
+#define UART5_DMACTL_R (*((volatile uint32_t *)0x40011048))
+#define UART5_9BITADDR_R (*((volatile uint32_t *)0x400110A4))
+#define UART5_9BITAMASK_R (*((volatile uint32_t *)0x400110A8))
+#define UART5_PP_R (*((volatile uint32_t *)0x40011FC0))
+#define UART5_CC_R (*((volatile uint32_t *)0x40011FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART6)
+//
+//*****************************************************************************
+#define UART6_DR_R (*((volatile uint32_t *)0x40012000))
+#define UART6_RSR_R (*((volatile uint32_t *)0x40012004))
+#define UART6_ECR_R (*((volatile uint32_t *)0x40012004))
+#define UART6_FR_R (*((volatile uint32_t *)0x40012018))
+#define UART6_ILPR_R (*((volatile uint32_t *)0x40012020))
+#define UART6_IBRD_R (*((volatile uint32_t *)0x40012024))
+#define UART6_FBRD_R (*((volatile uint32_t *)0x40012028))
+#define UART6_LCRH_R (*((volatile uint32_t *)0x4001202C))
+#define UART6_CTL_R (*((volatile uint32_t *)0x40012030))
+#define UART6_IFLS_R (*((volatile uint32_t *)0x40012034))
+#define UART6_IM_R (*((volatile uint32_t *)0x40012038))
+#define UART6_RIS_R (*((volatile uint32_t *)0x4001203C))
+#define UART6_MIS_R (*((volatile uint32_t *)0x40012040))
+#define UART6_ICR_R (*((volatile uint32_t *)0x40012044))
+#define UART6_DMACTL_R (*((volatile uint32_t *)0x40012048))
+#define UART6_9BITADDR_R (*((volatile uint32_t *)0x400120A4))
+#define UART6_9BITAMASK_R (*((volatile uint32_t *)0x400120A8))
+#define UART6_PP_R (*((volatile uint32_t *)0x40012FC0))
+#define UART6_CC_R (*((volatile uint32_t *)0x40012FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART7)
+//
+//*****************************************************************************
+#define UART7_DR_R (*((volatile uint32_t *)0x40013000))
+#define UART7_RSR_R (*((volatile uint32_t *)0x40013004))
+#define UART7_ECR_R (*((volatile uint32_t *)0x40013004))
+#define UART7_FR_R (*((volatile uint32_t *)0x40013018))
+#define UART7_ILPR_R (*((volatile uint32_t *)0x40013020))
+#define UART7_IBRD_R (*((volatile uint32_t *)0x40013024))
+#define UART7_FBRD_R (*((volatile uint32_t *)0x40013028))
+#define UART7_LCRH_R (*((volatile uint32_t *)0x4001302C))
+#define UART7_CTL_R (*((volatile uint32_t *)0x40013030))
+#define UART7_IFLS_R (*((volatile uint32_t *)0x40013034))
+#define UART7_IM_R (*((volatile uint32_t *)0x40013038))
+#define UART7_RIS_R (*((volatile uint32_t *)0x4001303C))
+#define UART7_MIS_R (*((volatile uint32_t *)0x40013040))
+#define UART7_ICR_R (*((volatile uint32_t *)0x40013044))
+#define UART7_DMACTL_R (*((volatile uint32_t *)0x40013048))
+#define UART7_9BITADDR_R (*((volatile uint32_t *)0x400130A4))
+#define UART7_9BITAMASK_R (*((volatile uint32_t *)0x400130A8))
+#define UART7_PP_R (*((volatile uint32_t *)0x40013FC0))
+#define UART7_CC_R (*((volatile uint32_t *)0x40013FC8))
+
+//*****************************************************************************
+//
+// I2C registers (I2C0)
+//
+//*****************************************************************************
+#define I2C0_MSA_R (*((volatile uint32_t *)0x40020000))
+#define I2C0_MCS_R (*((volatile uint32_t *)0x40020004))
+#define I2C0_MDR_R (*((volatile uint32_t *)0x40020008))
+#define I2C0_MTPR_R (*((volatile uint32_t *)0x4002000C))
+#define I2C0_MIMR_R (*((volatile uint32_t *)0x40020010))
+#define I2C0_MRIS_R (*((volatile uint32_t *)0x40020014))
+#define I2C0_MMIS_R (*((volatile uint32_t *)0x40020018))
+#define I2C0_MICR_R (*((volatile uint32_t *)0x4002001C))
+#define I2C0_MCR_R (*((volatile uint32_t *)0x40020020))
+#define I2C0_MCLKOCNT_R (*((volatile uint32_t *)0x40020024))
+#define I2C0_MBMON_R (*((volatile uint32_t *)0x4002002C))
+#define I2C0_MCR2_R (*((volatile uint32_t *)0x40020038))
+#define I2C0_SOAR_R (*((volatile uint32_t *)0x40020800))
+#define I2C0_SCSR_R (*((volatile uint32_t *)0x40020804))
+#define I2C0_SDR_R (*((volatile uint32_t *)0x40020808))
+#define I2C0_SIMR_R (*((volatile uint32_t *)0x4002080C))
+#define I2C0_SRIS_R (*((volatile uint32_t *)0x40020810))
+#define I2C0_SMIS_R (*((volatile uint32_t *)0x40020814))
+#define I2C0_SICR_R (*((volatile uint32_t *)0x40020818))
+#define I2C0_SOAR2_R (*((volatile uint32_t *)0x4002081C))
+#define I2C0_SACKCTL_R (*((volatile uint32_t *)0x40020820))
+#define I2C0_PP_R (*((volatile uint32_t *)0x40020FC0))
+#define I2C0_PC_R (*((volatile uint32_t *)0x40020FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C1)
+//
+//*****************************************************************************
+#define I2C1_MSA_R (*((volatile uint32_t *)0x40021000))
+#define I2C1_MCS_R (*((volatile uint32_t *)0x40021004))
+#define I2C1_MDR_R (*((volatile uint32_t *)0x40021008))
+#define I2C1_MTPR_R (*((volatile uint32_t *)0x4002100C))
+#define I2C1_MIMR_R (*((volatile uint32_t *)0x40021010))
+#define I2C1_MRIS_R (*((volatile uint32_t *)0x40021014))
+#define I2C1_MMIS_R (*((volatile uint32_t *)0x40021018))
+#define I2C1_MICR_R (*((volatile uint32_t *)0x4002101C))
+#define I2C1_MCR_R (*((volatile uint32_t *)0x40021020))
+#define I2C1_MCLKOCNT_R (*((volatile uint32_t *)0x40021024))
+#define I2C1_MBMON_R (*((volatile uint32_t *)0x4002102C))
+#define I2C1_MCR2_R (*((volatile uint32_t *)0x40021038))
+#define I2C1_SOAR_R (*((volatile uint32_t *)0x40021800))
+#define I2C1_SCSR_R (*((volatile uint32_t *)0x40021804))
+#define I2C1_SDR_R (*((volatile uint32_t *)0x40021808))
+#define I2C1_SIMR_R (*((volatile uint32_t *)0x4002180C))
+#define I2C1_SRIS_R (*((volatile uint32_t *)0x40021810))
+#define I2C1_SMIS_R (*((volatile uint32_t *)0x40021814))
+#define I2C1_SICR_R (*((volatile uint32_t *)0x40021818))
+#define I2C1_SOAR2_R (*((volatile uint32_t *)0x4002181C))
+#define I2C1_SACKCTL_R (*((volatile uint32_t *)0x40021820))
+#define I2C1_PP_R (*((volatile uint32_t *)0x40021FC0))
+#define I2C1_PC_R (*((volatile uint32_t *)0x40021FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C2)
+//
+//*****************************************************************************
+#define I2C2_MSA_R (*((volatile uint32_t *)0x40022000))
+#define I2C2_MCS_R (*((volatile uint32_t *)0x40022004))
+#define I2C2_MDR_R (*((volatile uint32_t *)0x40022008))
+#define I2C2_MTPR_R (*((volatile uint32_t *)0x4002200C))
+#define I2C2_MIMR_R (*((volatile uint32_t *)0x40022010))
+#define I2C2_MRIS_R (*((volatile uint32_t *)0x40022014))
+#define I2C2_MMIS_R (*((volatile uint32_t *)0x40022018))
+#define I2C2_MICR_R (*((volatile uint32_t *)0x4002201C))
+#define I2C2_MCR_R (*((volatile uint32_t *)0x40022020))
+#define I2C2_MCLKOCNT_R (*((volatile uint32_t *)0x40022024))
+#define I2C2_MBMON_R (*((volatile uint32_t *)0x4002202C))
+#define I2C2_MCR2_R (*((volatile uint32_t *)0x40022038))
+#define I2C2_SOAR_R (*((volatile uint32_t *)0x40022800))
+#define I2C2_SCSR_R (*((volatile uint32_t *)0x40022804))
+#define I2C2_SDR_R (*((volatile uint32_t *)0x40022808))
+#define I2C2_SIMR_R (*((volatile uint32_t *)0x4002280C))
+#define I2C2_SRIS_R (*((volatile uint32_t *)0x40022810))
+#define I2C2_SMIS_R (*((volatile uint32_t *)0x40022814))
+#define I2C2_SICR_R (*((volatile uint32_t *)0x40022818))
+#define I2C2_SOAR2_R (*((volatile uint32_t *)0x4002281C))
+#define I2C2_SACKCTL_R (*((volatile uint32_t *)0x40022820))
+#define I2C2_PP_R (*((volatile uint32_t *)0x40022FC0))
+#define I2C2_PC_R (*((volatile uint32_t *)0x40022FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C3)
+//
+//*****************************************************************************
+#define I2C3_MSA_R (*((volatile uint32_t *)0x40023000))
+#define I2C3_MCS_R (*((volatile uint32_t *)0x40023004))
+#define I2C3_MDR_R (*((volatile uint32_t *)0x40023008))
+#define I2C3_MTPR_R (*((volatile uint32_t *)0x4002300C))
+#define I2C3_MIMR_R (*((volatile uint32_t *)0x40023010))
+#define I2C3_MRIS_R (*((volatile uint32_t *)0x40023014))
+#define I2C3_MMIS_R (*((volatile uint32_t *)0x40023018))
+#define I2C3_MICR_R (*((volatile uint32_t *)0x4002301C))
+#define I2C3_MCR_R (*((volatile uint32_t *)0x40023020))
+#define I2C3_MCLKOCNT_R (*((volatile uint32_t *)0x40023024))
+#define I2C3_MBMON_R (*((volatile uint32_t *)0x4002302C))
+#define I2C3_MCR2_R (*((volatile uint32_t *)0x40023038))
+#define I2C3_SOAR_R (*((volatile uint32_t *)0x40023800))
+#define I2C3_SCSR_R (*((volatile uint32_t *)0x40023804))
+#define I2C3_SDR_R (*((volatile uint32_t *)0x40023808))
+#define I2C3_SIMR_R (*((volatile uint32_t *)0x4002380C))
+#define I2C3_SRIS_R (*((volatile uint32_t *)0x40023810))
+#define I2C3_SMIS_R (*((volatile uint32_t *)0x40023814))
+#define I2C3_SICR_R (*((volatile uint32_t *)0x40023818))
+#define I2C3_SOAR2_R (*((volatile uint32_t *)0x4002381C))
+#define I2C3_SACKCTL_R (*((volatile uint32_t *)0x40023820))
+#define I2C3_PP_R (*((volatile uint32_t *)0x40023FC0))
+#define I2C3_PC_R (*((volatile uint32_t *)0x40023FC4))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTE)
+//
+//*****************************************************************************
+#define GPIO_PORTE_DATA_BITS_R ((volatile uint32_t *)0x40024000)
+#define GPIO_PORTE_DATA_R (*((volatile uint32_t *)0x400243FC))
+#define GPIO_PORTE_DIR_R (*((volatile uint32_t *)0x40024400))
+#define GPIO_PORTE_IS_R (*((volatile uint32_t *)0x40024404))
+#define GPIO_PORTE_IBE_R (*((volatile uint32_t *)0x40024408))
+#define GPIO_PORTE_IEV_R (*((volatile uint32_t *)0x4002440C))
+#define GPIO_PORTE_IM_R (*((volatile uint32_t *)0x40024410))
+#define GPIO_PORTE_RIS_R (*((volatile uint32_t *)0x40024414))
+#define GPIO_PORTE_MIS_R (*((volatile uint32_t *)0x40024418))
+#define GPIO_PORTE_ICR_R (*((volatile uint32_t *)0x4002441C))
+#define GPIO_PORTE_AFSEL_R (*((volatile uint32_t *)0x40024420))
+#define GPIO_PORTE_DR2R_R (*((volatile uint32_t *)0x40024500))
+#define GPIO_PORTE_DR4R_R (*((volatile uint32_t *)0x40024504))
+#define GPIO_PORTE_DR8R_R (*((volatile uint32_t *)0x40024508))
+#define GPIO_PORTE_ODR_R (*((volatile uint32_t *)0x4002450C))
+#define GPIO_PORTE_PUR_R (*((volatile uint32_t *)0x40024510))
+#define GPIO_PORTE_PDR_R (*((volatile uint32_t *)0x40024514))
+#define GPIO_PORTE_SLR_R (*((volatile uint32_t *)0x40024518))
+#define GPIO_PORTE_DEN_R (*((volatile uint32_t *)0x4002451C))
+#define GPIO_PORTE_LOCK_R (*((volatile uint32_t *)0x40024520))
+#define GPIO_PORTE_CR_R (*((volatile uint32_t *)0x40024524))
+#define GPIO_PORTE_AMSEL_R (*((volatile uint32_t *)0x40024528))
+#define GPIO_PORTE_PCTL_R (*((volatile uint32_t *)0x4002452C))
+#define GPIO_PORTE_ADCCTL_R (*((volatile uint32_t *)0x40024530))
+#define GPIO_PORTE_DMACTL_R (*((volatile uint32_t *)0x40024534))
+#define GPIO_PORTE_SI_R (*((volatile uint32_t *)0x40024538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTF)
+//
+//*****************************************************************************
+#define GPIO_PORTF_DATA_BITS_R ((volatile uint32_t *)0x40025000)
+#define GPIO_PORTF_DATA_R (*((volatile uint32_t *)0x400253FC))
+#define GPIO_PORTF_DIR_R (*((volatile uint32_t *)0x40025400))
+#define GPIO_PORTF_IS_R (*((volatile uint32_t *)0x40025404))
+#define GPIO_PORTF_IBE_R (*((volatile uint32_t *)0x40025408))
+#define GPIO_PORTF_IEV_R (*((volatile uint32_t *)0x4002540C))
+#define GPIO_PORTF_IM_R (*((volatile uint32_t *)0x40025410))
+#define GPIO_PORTF_RIS_R (*((volatile uint32_t *)0x40025414))
+#define GPIO_PORTF_MIS_R (*((volatile uint32_t *)0x40025418))
+#define GPIO_PORTF_ICR_R (*((volatile uint32_t *)0x4002541C))
+#define GPIO_PORTF_AFSEL_R (*((volatile uint32_t *)0x40025420))
+#define GPIO_PORTF_DR2R_R (*((volatile uint32_t *)0x40025500))
+#define GPIO_PORTF_DR4R_R (*((volatile uint32_t *)0x40025504))
+#define GPIO_PORTF_DR8R_R (*((volatile uint32_t *)0x40025508))
+#define GPIO_PORTF_ODR_R (*((volatile uint32_t *)0x4002550C))
+#define GPIO_PORTF_PUR_R (*((volatile uint32_t *)0x40025510))
+#define GPIO_PORTF_PDR_R (*((volatile uint32_t *)0x40025514))
+#define GPIO_PORTF_SLR_R (*((volatile uint32_t *)0x40025518))
+#define GPIO_PORTF_DEN_R (*((volatile uint32_t *)0x4002551C))
+#define GPIO_PORTF_LOCK_R (*((volatile uint32_t *)0x40025520))
+#define GPIO_PORTF_CR_R (*((volatile uint32_t *)0x40025524))
+#define GPIO_PORTF_AMSEL_R (*((volatile uint32_t *)0x40025528))
+#define GPIO_PORTF_PCTL_R (*((volatile uint32_t *)0x4002552C))
+#define GPIO_PORTF_ADCCTL_R (*((volatile uint32_t *)0x40025530))
+#define GPIO_PORTF_DMACTL_R (*((volatile uint32_t *)0x40025534))
+#define GPIO_PORTF_SI_R (*((volatile uint32_t *)0x40025538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTG)
+//
+//*****************************************************************************
+#define GPIO_PORTG_DATA_BITS_R ((volatile uint32_t *)0x40026000)
+#define GPIO_PORTG_DATA_R (*((volatile uint32_t *)0x400263FC))
+#define GPIO_PORTG_DIR_R (*((volatile uint32_t *)0x40026400))
+#define GPIO_PORTG_IS_R (*((volatile uint32_t *)0x40026404))
+#define GPIO_PORTG_IBE_R (*((volatile uint32_t *)0x40026408))
+#define GPIO_PORTG_IEV_R (*((volatile uint32_t *)0x4002640C))
+#define GPIO_PORTG_IM_R (*((volatile uint32_t *)0x40026410))
+#define GPIO_PORTG_RIS_R (*((volatile uint32_t *)0x40026414))
+#define GPIO_PORTG_MIS_R (*((volatile uint32_t *)0x40026418))
+#define GPIO_PORTG_ICR_R (*((volatile uint32_t *)0x4002641C))
+#define GPIO_PORTG_AFSEL_R (*((volatile uint32_t *)0x40026420))
+#define GPIO_PORTG_DR2R_R (*((volatile uint32_t *)0x40026500))
+#define GPIO_PORTG_DR4R_R (*((volatile uint32_t *)0x40026504))
+#define GPIO_PORTG_DR8R_R (*((volatile uint32_t *)0x40026508))
+#define GPIO_PORTG_ODR_R (*((volatile uint32_t *)0x4002650C))
+#define GPIO_PORTG_PUR_R (*((volatile uint32_t *)0x40026510))
+#define GPIO_PORTG_PDR_R (*((volatile uint32_t *)0x40026514))
+#define GPIO_PORTG_SLR_R (*((volatile uint32_t *)0x40026518))
+#define GPIO_PORTG_DEN_R (*((volatile uint32_t *)0x4002651C))
+#define GPIO_PORTG_LOCK_R (*((volatile uint32_t *)0x40026520))
+#define GPIO_PORTG_CR_R (*((volatile uint32_t *)0x40026524))
+#define GPIO_PORTG_AMSEL_R (*((volatile uint32_t *)0x40026528))
+#define GPIO_PORTG_PCTL_R (*((volatile uint32_t *)0x4002652C))
+#define GPIO_PORTG_ADCCTL_R (*((volatile uint32_t *)0x40026530))
+#define GPIO_PORTG_DMACTL_R (*((volatile uint32_t *)0x40026534))
+#define GPIO_PORTG_SI_R (*((volatile uint32_t *)0x40026538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTH)
+//
+//*****************************************************************************
+#define GPIO_PORTH_DATA_BITS_R ((volatile uint32_t *)0x40027000)
+#define GPIO_PORTH_DATA_R (*((volatile uint32_t *)0x400273FC))
+#define GPIO_PORTH_DIR_R (*((volatile uint32_t *)0x40027400))
+#define GPIO_PORTH_IS_R (*((volatile uint32_t *)0x40027404))
+#define GPIO_PORTH_IBE_R (*((volatile uint32_t *)0x40027408))
+#define GPIO_PORTH_IEV_R (*((volatile uint32_t *)0x4002740C))
+#define GPIO_PORTH_IM_R (*((volatile uint32_t *)0x40027410))
+#define GPIO_PORTH_RIS_R (*((volatile uint32_t *)0x40027414))
+#define GPIO_PORTH_MIS_R (*((volatile uint32_t *)0x40027418))
+#define GPIO_PORTH_ICR_R (*((volatile uint32_t *)0x4002741C))
+#define GPIO_PORTH_AFSEL_R (*((volatile uint32_t *)0x40027420))
+#define GPIO_PORTH_DR2R_R (*((volatile uint32_t *)0x40027500))
+#define GPIO_PORTH_DR4R_R (*((volatile uint32_t *)0x40027504))
+#define GPIO_PORTH_DR8R_R (*((volatile uint32_t *)0x40027508))
+#define GPIO_PORTH_ODR_R (*((volatile uint32_t *)0x4002750C))
+#define GPIO_PORTH_PUR_R (*((volatile uint32_t *)0x40027510))
+#define GPIO_PORTH_PDR_R (*((volatile uint32_t *)0x40027514))
+#define GPIO_PORTH_SLR_R (*((volatile uint32_t *)0x40027518))
+#define GPIO_PORTH_DEN_R (*((volatile uint32_t *)0x4002751C))
+#define GPIO_PORTH_LOCK_R (*((volatile uint32_t *)0x40027520))
+#define GPIO_PORTH_CR_R (*((volatile uint32_t *)0x40027524))
+#define GPIO_PORTH_AMSEL_R (*((volatile uint32_t *)0x40027528))
+#define GPIO_PORTH_PCTL_R (*((volatile uint32_t *)0x4002752C))
+#define GPIO_PORTH_ADCCTL_R (*((volatile uint32_t *)0x40027530))
+#define GPIO_PORTH_DMACTL_R (*((volatile uint32_t *)0x40027534))
+#define GPIO_PORTH_SI_R (*((volatile uint32_t *)0x40027538))
+
+//*****************************************************************************
+//
+// PWM registers (PWM0)
+//
+//*****************************************************************************
+#define PWM0_CTL_R (*((volatile uint32_t *)0x40028000))
+#define PWM0_SYNC_R (*((volatile uint32_t *)0x40028004))
+#define PWM0_ENABLE_R (*((volatile uint32_t *)0x40028008))
+#define PWM0_INVERT_R (*((volatile uint32_t *)0x4002800C))
+#define PWM0_FAULT_R (*((volatile uint32_t *)0x40028010))
+#define PWM0_INTEN_R (*((volatile uint32_t *)0x40028014))
+#define PWM0_RIS_R (*((volatile uint32_t *)0x40028018))
+#define PWM0_ISC_R (*((volatile uint32_t *)0x4002801C))
+#define PWM0_STATUS_R (*((volatile uint32_t *)0x40028020))
+#define PWM0_FAULTVAL_R (*((volatile uint32_t *)0x40028024))
+#define PWM0_ENUPD_R (*((volatile uint32_t *)0x40028028))
+#define PWM0_0_CTL_R (*((volatile uint32_t *)0x40028040))
+#define PWM0_0_INTEN_R (*((volatile uint32_t *)0x40028044))
+#define PWM0_0_RIS_R (*((volatile uint32_t *)0x40028048))
+#define PWM0_0_ISC_R (*((volatile uint32_t *)0x4002804C))
+#define PWM0_0_LOAD_R (*((volatile uint32_t *)0x40028050))
+#define PWM0_0_COUNT_R (*((volatile uint32_t *)0x40028054))
+#define PWM0_0_CMPA_R (*((volatile uint32_t *)0x40028058))
+#define PWM0_0_CMPB_R (*((volatile uint32_t *)0x4002805C))
+#define PWM0_0_GENA_R (*((volatile uint32_t *)0x40028060))
+#define PWM0_0_GENB_R (*((volatile uint32_t *)0x40028064))
+#define PWM0_0_DBCTL_R (*((volatile uint32_t *)0x40028068))
+#define PWM0_0_DBRISE_R (*((volatile uint32_t *)0x4002806C))
+#define PWM0_0_DBFALL_R (*((volatile uint32_t *)0x40028070))
+#define PWM0_0_FLTSRC0_R (*((volatile uint32_t *)0x40028074))
+#define PWM0_0_FLTSRC1_R (*((volatile uint32_t *)0x40028078))
+#define PWM0_0_MINFLTPER_R (*((volatile uint32_t *)0x4002807C))
+#define PWM0_1_CTL_R (*((volatile uint32_t *)0x40028080))
+#define PWM0_1_INTEN_R (*((volatile uint32_t *)0x40028084))
+#define PWM0_1_RIS_R (*((volatile uint32_t *)0x40028088))
+#define PWM0_1_ISC_R (*((volatile uint32_t *)0x4002808C))
+#define PWM0_1_LOAD_R (*((volatile uint32_t *)0x40028090))
+#define PWM0_1_COUNT_R (*((volatile uint32_t *)0x40028094))
+#define PWM0_1_CMPA_R (*((volatile uint32_t *)0x40028098))
+#define PWM0_1_CMPB_R (*((volatile uint32_t *)0x4002809C))
+#define PWM0_1_GENA_R (*((volatile uint32_t *)0x400280A0))
+#define PWM0_1_GENB_R (*((volatile uint32_t *)0x400280A4))
+#define PWM0_1_DBCTL_R (*((volatile uint32_t *)0x400280A8))
+#define PWM0_1_DBRISE_R (*((volatile uint32_t *)0x400280AC))
+#define PWM0_1_DBFALL_R (*((volatile uint32_t *)0x400280B0))
+#define PWM0_1_FLTSRC0_R (*((volatile uint32_t *)0x400280B4))
+#define PWM0_1_FLTSRC1_R (*((volatile uint32_t *)0x400280B8))
+#define PWM0_1_MINFLTPER_R (*((volatile uint32_t *)0x400280BC))
+#define PWM0_2_CTL_R (*((volatile uint32_t *)0x400280C0))
+#define PWM0_2_INTEN_R (*((volatile uint32_t *)0x400280C4))
+#define PWM0_2_RIS_R (*((volatile uint32_t *)0x400280C8))
+#define PWM0_2_ISC_R (*((volatile uint32_t *)0x400280CC))
+#define PWM0_2_LOAD_R (*((volatile uint32_t *)0x400280D0))
+#define PWM0_2_COUNT_R (*((volatile uint32_t *)0x400280D4))
+#define PWM0_2_CMPA_R (*((volatile uint32_t *)0x400280D8))
+#define PWM0_2_CMPB_R (*((volatile uint32_t *)0x400280DC))
+#define PWM0_2_GENA_R (*((volatile uint32_t *)0x400280E0))
+#define PWM0_2_GENB_R (*((volatile uint32_t *)0x400280E4))
+#define PWM0_2_DBCTL_R (*((volatile uint32_t *)0x400280E8))
+#define PWM0_2_DBRISE_R (*((volatile uint32_t *)0x400280EC))
+#define PWM0_2_DBFALL_R (*((volatile uint32_t *)0x400280F0))
+#define PWM0_2_FLTSRC0_R (*((volatile uint32_t *)0x400280F4))
+#define PWM0_2_FLTSRC1_R (*((volatile uint32_t *)0x400280F8))
+#define PWM0_2_MINFLTPER_R (*((volatile uint32_t *)0x400280FC))
+#define PWM0_3_CTL_R (*((volatile uint32_t *)0x40028100))
+#define PWM0_3_INTEN_R (*((volatile uint32_t *)0x40028104))
+#define PWM0_3_RIS_R (*((volatile uint32_t *)0x40028108))
+#define PWM0_3_ISC_R (*((volatile uint32_t *)0x4002810C))
+#define PWM0_3_LOAD_R (*((volatile uint32_t *)0x40028110))
+#define PWM0_3_COUNT_R (*((volatile uint32_t *)0x40028114))
+#define PWM0_3_CMPA_R (*((volatile uint32_t *)0x40028118))
+#define PWM0_3_CMPB_R (*((volatile uint32_t *)0x4002811C))
+#define PWM0_3_GENA_R (*((volatile uint32_t *)0x40028120))
+#define PWM0_3_GENB_R (*((volatile uint32_t *)0x40028124))
+#define PWM0_3_DBCTL_R (*((volatile uint32_t *)0x40028128))
+#define PWM0_3_DBRISE_R (*((volatile uint32_t *)0x4002812C))
+#define PWM0_3_DBFALL_R (*((volatile uint32_t *)0x40028130))
+#define PWM0_3_FLTSRC0_R (*((volatile uint32_t *)0x40028134))
+#define PWM0_3_FLTSRC1_R (*((volatile uint32_t *)0x40028138))
+#define PWM0_3_MINFLTPER_R (*((volatile uint32_t *)0x4002813C))
+#define PWM0_0_FLTSEN_R (*((volatile uint32_t *)0x40028800))
+#define PWM0_0_FLTSTAT0_R (*((volatile uint32_t *)0x40028804))
+#define PWM0_0_FLTSTAT1_R (*((volatile uint32_t *)0x40028808))
+#define PWM0_1_FLTSEN_R (*((volatile uint32_t *)0x40028880))
+#define PWM0_1_FLTSTAT0_R (*((volatile uint32_t *)0x40028884))
+#define PWM0_1_FLTSTAT1_R (*((volatile uint32_t *)0x40028888))
+#define PWM0_2_FLTSEN_R (*((volatile uint32_t *)0x40028900))
+#define PWM0_2_FLTSTAT0_R (*((volatile uint32_t *)0x40028904))
+#define PWM0_2_FLTSTAT1_R (*((volatile uint32_t *)0x40028908))
+#define PWM0_3_FLTSEN_R (*((volatile uint32_t *)0x40028980))
+#define PWM0_3_FLTSTAT0_R (*((volatile uint32_t *)0x40028984))
+#define PWM0_3_FLTSTAT1_R (*((volatile uint32_t *)0x40028988))
+#define PWM0_PP_R (*((volatile uint32_t *)0x40028FC0))
+
+//*****************************************************************************
+//
+// PWM registers (PWM1)
+//
+//*****************************************************************************
+#define PWM1_CTL_R (*((volatile uint32_t *)0x40029000))
+#define PWM1_SYNC_R (*((volatile uint32_t *)0x40029004))
+#define PWM1_ENABLE_R (*((volatile uint32_t *)0x40029008))
+#define PWM1_INVERT_R (*((volatile uint32_t *)0x4002900C))
+#define PWM1_FAULT_R (*((volatile uint32_t *)0x40029010))
+#define PWM1_INTEN_R (*((volatile uint32_t *)0x40029014))
+#define PWM1_RIS_R (*((volatile uint32_t *)0x40029018))
+#define PWM1_ISC_R (*((volatile uint32_t *)0x4002901C))
+#define PWM1_STATUS_R (*((volatile uint32_t *)0x40029020))
+#define PWM1_FAULTVAL_R (*((volatile uint32_t *)0x40029024))
+#define PWM1_ENUPD_R (*((volatile uint32_t *)0x40029028))
+#define PWM1_0_CTL_R (*((volatile uint32_t *)0x40029040))
+#define PWM1_0_INTEN_R (*((volatile uint32_t *)0x40029044))
+#define PWM1_0_RIS_R (*((volatile uint32_t *)0x40029048))
+#define PWM1_0_ISC_R (*((volatile uint32_t *)0x4002904C))
+#define PWM1_0_LOAD_R (*((volatile uint32_t *)0x40029050))
+#define PWM1_0_COUNT_R (*((volatile uint32_t *)0x40029054))
+#define PWM1_0_CMPA_R (*((volatile uint32_t *)0x40029058))
+#define PWM1_0_CMPB_R (*((volatile uint32_t *)0x4002905C))
+#define PWM1_0_GENA_R (*((volatile uint32_t *)0x40029060))
+#define PWM1_0_GENB_R (*((volatile uint32_t *)0x40029064))
+#define PWM1_0_DBCTL_R (*((volatile uint32_t *)0x40029068))
+#define PWM1_0_DBRISE_R (*((volatile uint32_t *)0x4002906C))
+#define PWM1_0_DBFALL_R (*((volatile uint32_t *)0x40029070))
+#define PWM1_0_FLTSRC0_R (*((volatile uint32_t *)0x40029074))
+#define PWM1_0_FLTSRC1_R (*((volatile uint32_t *)0x40029078))
+#define PWM1_0_MINFLTPER_R (*((volatile uint32_t *)0x4002907C))
+#define PWM1_1_CTL_R (*((volatile uint32_t *)0x40029080))
+#define PWM1_1_INTEN_R (*((volatile uint32_t *)0x40029084))
+#define PWM1_1_RIS_R (*((volatile uint32_t *)0x40029088))
+#define PWM1_1_ISC_R (*((volatile uint32_t *)0x4002908C))
+#define PWM1_1_LOAD_R (*((volatile uint32_t *)0x40029090))
+#define PWM1_1_COUNT_R (*((volatile uint32_t *)0x40029094))
+#define PWM1_1_CMPA_R (*((volatile uint32_t *)0x40029098))
+#define PWM1_1_CMPB_R (*((volatile uint32_t *)0x4002909C))
+#define PWM1_1_GENA_R (*((volatile uint32_t *)0x400290A0))
+#define PWM1_1_GENB_R (*((volatile uint32_t *)0x400290A4))
+#define PWM1_1_DBCTL_R (*((volatile uint32_t *)0x400290A8))
+#define PWM1_1_DBRISE_R (*((volatile uint32_t *)0x400290AC))
+#define PWM1_1_DBFALL_R (*((volatile uint32_t *)0x400290B0))
+#define PWM1_1_FLTSRC0_R (*((volatile uint32_t *)0x400290B4))
+#define PWM1_1_FLTSRC1_R (*((volatile uint32_t *)0x400290B8))
+#define PWM1_1_MINFLTPER_R (*((volatile uint32_t *)0x400290BC))
+#define PWM1_2_CTL_R (*((volatile uint32_t *)0x400290C0))
+#define PWM1_2_INTEN_R (*((volatile uint32_t *)0x400290C4))
+#define PWM1_2_RIS_R (*((volatile uint32_t *)0x400290C8))
+#define PWM1_2_ISC_R (*((volatile uint32_t *)0x400290CC))
+#define PWM1_2_LOAD_R (*((volatile uint32_t *)0x400290D0))
+#define PWM1_2_COUNT_R (*((volatile uint32_t *)0x400290D4))
+#define PWM1_2_CMPA_R (*((volatile uint32_t *)0x400290D8))
+#define PWM1_2_CMPB_R (*((volatile uint32_t *)0x400290DC))
+#define PWM1_2_GENA_R (*((volatile uint32_t *)0x400290E0))
+#define PWM1_2_GENB_R (*((volatile uint32_t *)0x400290E4))
+#define PWM1_2_DBCTL_R (*((volatile uint32_t *)0x400290E8))
+#define PWM1_2_DBRISE_R (*((volatile uint32_t *)0x400290EC))
+#define PWM1_2_DBFALL_R (*((volatile uint32_t *)0x400290F0))
+#define PWM1_2_FLTSRC0_R (*((volatile uint32_t *)0x400290F4))
+#define PWM1_2_FLTSRC1_R (*((volatile uint32_t *)0x400290F8))
+#define PWM1_2_MINFLTPER_R (*((volatile uint32_t *)0x400290FC))
+#define PWM1_3_CTL_R (*((volatile uint32_t *)0x40029100))
+#define PWM1_3_INTEN_R (*((volatile uint32_t *)0x40029104))
+#define PWM1_3_RIS_R (*((volatile uint32_t *)0x40029108))
+#define PWM1_3_ISC_R (*((volatile uint32_t *)0x4002910C))
+#define PWM1_3_LOAD_R (*((volatile uint32_t *)0x40029110))
+#define PWM1_3_COUNT_R (*((volatile uint32_t *)0x40029114))
+#define PWM1_3_CMPA_R (*((volatile uint32_t *)0x40029118))
+#define PWM1_3_CMPB_R (*((volatile uint32_t *)0x4002911C))
+#define PWM1_3_GENA_R (*((volatile uint32_t *)0x40029120))
+#define PWM1_3_GENB_R (*((volatile uint32_t *)0x40029124))
+#define PWM1_3_DBCTL_R (*((volatile uint32_t *)0x40029128))
+#define PWM1_3_DBRISE_R (*((volatile uint32_t *)0x4002912C))
+#define PWM1_3_DBFALL_R (*((volatile uint32_t *)0x40029130))
+#define PWM1_3_FLTSRC0_R (*((volatile uint32_t *)0x40029134))
+#define PWM1_3_FLTSRC1_R (*((volatile uint32_t *)0x40029138))
+#define PWM1_3_MINFLTPER_R (*((volatile uint32_t *)0x4002913C))
+#define PWM1_0_FLTSEN_R (*((volatile uint32_t *)0x40029800))
+#define PWM1_0_FLTSTAT0_R (*((volatile uint32_t *)0x40029804))
+#define PWM1_0_FLTSTAT1_R (*((volatile uint32_t *)0x40029808))
+#define PWM1_1_FLTSEN_R (*((volatile uint32_t *)0x40029880))
+#define PWM1_1_FLTSTAT0_R (*((volatile uint32_t *)0x40029884))
+#define PWM1_1_FLTSTAT1_R (*((volatile uint32_t *)0x40029888))
+#define PWM1_2_FLTSEN_R (*((volatile uint32_t *)0x40029900))
+#define PWM1_2_FLTSTAT0_R (*((volatile uint32_t *)0x40029904))
+#define PWM1_2_FLTSTAT1_R (*((volatile uint32_t *)0x40029908))
+#define PWM1_3_FLTSEN_R (*((volatile uint32_t *)0x40029980))
+#define PWM1_3_FLTSTAT0_R (*((volatile uint32_t *)0x40029984))
+#define PWM1_3_FLTSTAT1_R (*((volatile uint32_t *)0x40029988))
+#define PWM1_PP_R (*((volatile uint32_t *)0x40029FC0))
+
+//*****************************************************************************
+//
+// QEI registers (QEI0)
+//
+//*****************************************************************************
+#define QEI0_CTL_R (*((volatile uint32_t *)0x4002C000))
+#define QEI0_STAT_R (*((volatile uint32_t *)0x4002C004))
+#define QEI0_POS_R (*((volatile uint32_t *)0x4002C008))
+#define QEI0_MAXPOS_R (*((volatile uint32_t *)0x4002C00C))
+#define QEI0_LOAD_R (*((volatile uint32_t *)0x4002C010))
+#define QEI0_TIME_R (*((volatile uint32_t *)0x4002C014))
+#define QEI0_COUNT_R (*((volatile uint32_t *)0x4002C018))
+#define QEI0_SPEED_R (*((volatile uint32_t *)0x4002C01C))
+#define QEI0_INTEN_R (*((volatile uint32_t *)0x4002C020))
+#define QEI0_RIS_R (*((volatile uint32_t *)0x4002C024))
+#define QEI0_ISC_R (*((volatile uint32_t *)0x4002C028))
+
+//*****************************************************************************
+//
+// QEI registers (QEI1)
+//
+//*****************************************************************************
+#define QEI1_CTL_R (*((volatile uint32_t *)0x4002D000))
+#define QEI1_STAT_R (*((volatile uint32_t *)0x4002D004))
+#define QEI1_POS_R (*((volatile uint32_t *)0x4002D008))
+#define QEI1_MAXPOS_R (*((volatile uint32_t *)0x4002D00C))
+#define QEI1_LOAD_R (*((volatile uint32_t *)0x4002D010))
+#define QEI1_TIME_R (*((volatile uint32_t *)0x4002D014))
+#define QEI1_COUNT_R (*((volatile uint32_t *)0x4002D018))
+#define QEI1_SPEED_R (*((volatile uint32_t *)0x4002D01C))
+#define QEI1_INTEN_R (*((volatile uint32_t *)0x4002D020))
+#define QEI1_RIS_R (*((volatile uint32_t *)0x4002D024))
+#define QEI1_ISC_R (*((volatile uint32_t *)0x4002D028))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER0)
+//
+//*****************************************************************************
+#define TIMER0_CFG_R (*((volatile uint32_t *)0x40030000))
+#define TIMER0_TAMR_R (*((volatile uint32_t *)0x40030004))
+#define TIMER0_TBMR_R (*((volatile uint32_t *)0x40030008))
+#define TIMER0_CTL_R (*((volatile uint32_t *)0x4003000C))
+#define TIMER0_SYNC_R (*((volatile uint32_t *)0x40030010))
+#define TIMER0_IMR_R (*((volatile uint32_t *)0x40030018))
+#define TIMER0_RIS_R (*((volatile uint32_t *)0x4003001C))
+#define TIMER0_MIS_R (*((volatile uint32_t *)0x40030020))
+#define TIMER0_ICR_R (*((volatile uint32_t *)0x40030024))
+#define TIMER0_TAILR_R (*((volatile uint32_t *)0x40030028))
+#define TIMER0_TBILR_R (*((volatile uint32_t *)0x4003002C))
+#define TIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40030030))
+#define TIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40030034))
+#define TIMER0_TAPR_R (*((volatile uint32_t *)0x40030038))
+#define TIMER0_TBPR_R (*((volatile uint32_t *)0x4003003C))
+#define TIMER0_TAPMR_R (*((volatile uint32_t *)0x40030040))
+#define TIMER0_TBPMR_R (*((volatile uint32_t *)0x40030044))
+#define TIMER0_TAR_R (*((volatile uint32_t *)0x40030048))
+#define TIMER0_TBR_R (*((volatile uint32_t *)0x4003004C))
+#define TIMER0_TAV_R (*((volatile uint32_t *)0x40030050))
+#define TIMER0_TBV_R (*((volatile uint32_t *)0x40030054))
+#define TIMER0_RTCPD_R (*((volatile uint32_t *)0x40030058))
+#define TIMER0_TAPS_R (*((volatile uint32_t *)0x4003005C))
+#define TIMER0_TBPS_R (*((volatile uint32_t *)0x40030060))
+#define TIMER0_TAPV_R (*((volatile uint32_t *)0x40030064))
+#define TIMER0_TBPV_R (*((volatile uint32_t *)0x40030068))
+#define TIMER0_PP_R (*((volatile uint32_t *)0x40030FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER1)
+//
+//*****************************************************************************
+#define TIMER1_CFG_R (*((volatile uint32_t *)0x40031000))
+#define TIMER1_TAMR_R (*((volatile uint32_t *)0x40031004))
+#define TIMER1_TBMR_R (*((volatile uint32_t *)0x40031008))
+#define TIMER1_CTL_R (*((volatile uint32_t *)0x4003100C))
+#define TIMER1_SYNC_R (*((volatile uint32_t *)0x40031010))
+#define TIMER1_IMR_R (*((volatile uint32_t *)0x40031018))
+#define TIMER1_RIS_R (*((volatile uint32_t *)0x4003101C))
+#define TIMER1_MIS_R (*((volatile uint32_t *)0x40031020))
+#define TIMER1_ICR_R (*((volatile uint32_t *)0x40031024))
+#define TIMER1_TAILR_R (*((volatile uint32_t *)0x40031028))
+#define TIMER1_TBILR_R (*((volatile uint32_t *)0x4003102C))
+#define TIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40031030))
+#define TIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40031034))
+#define TIMER1_TAPR_R (*((volatile uint32_t *)0x40031038))
+#define TIMER1_TBPR_R (*((volatile uint32_t *)0x4003103C))
+#define TIMER1_TAPMR_R (*((volatile uint32_t *)0x40031040))
+#define TIMER1_TBPMR_R (*((volatile uint32_t *)0x40031044))
+#define TIMER1_TAR_R (*((volatile uint32_t *)0x40031048))
+#define TIMER1_TBR_R (*((volatile uint32_t *)0x4003104C))
+#define TIMER1_TAV_R (*((volatile uint32_t *)0x40031050))
+#define TIMER1_TBV_R (*((volatile uint32_t *)0x40031054))
+#define TIMER1_RTCPD_R (*((volatile uint32_t *)0x40031058))
+#define TIMER1_TAPS_R (*((volatile uint32_t *)0x4003105C))
+#define TIMER1_TBPS_R (*((volatile uint32_t *)0x40031060))
+#define TIMER1_TAPV_R (*((volatile uint32_t *)0x40031064))
+#define TIMER1_TBPV_R (*((volatile uint32_t *)0x40031068))
+#define TIMER1_PP_R (*((volatile uint32_t *)0x40031FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER2)
+//
+//*****************************************************************************
+#define TIMER2_CFG_R (*((volatile uint32_t *)0x40032000))
+#define TIMER2_TAMR_R (*((volatile uint32_t *)0x40032004))
+#define TIMER2_TBMR_R (*((volatile uint32_t *)0x40032008))
+#define TIMER2_CTL_R (*((volatile uint32_t *)0x4003200C))
+#define TIMER2_SYNC_R (*((volatile uint32_t *)0x40032010))
+#define TIMER2_IMR_R (*((volatile uint32_t *)0x40032018))
+#define TIMER2_RIS_R (*((volatile uint32_t *)0x4003201C))
+#define TIMER2_MIS_R (*((volatile uint32_t *)0x40032020))
+#define TIMER2_ICR_R (*((volatile uint32_t *)0x40032024))
+#define TIMER2_TAILR_R (*((volatile uint32_t *)0x40032028))
+#define TIMER2_TBILR_R (*((volatile uint32_t *)0x4003202C))
+#define TIMER2_TAMATCHR_R (*((volatile uint32_t *)0x40032030))
+#define TIMER2_TBMATCHR_R (*((volatile uint32_t *)0x40032034))
+#define TIMER2_TAPR_R (*((volatile uint32_t *)0x40032038))
+#define TIMER2_TBPR_R (*((volatile uint32_t *)0x4003203C))
+#define TIMER2_TAPMR_R (*((volatile uint32_t *)0x40032040))
+#define TIMER2_TBPMR_R (*((volatile uint32_t *)0x40032044))
+#define TIMER2_TAR_R (*((volatile uint32_t *)0x40032048))
+#define TIMER2_TBR_R (*((volatile uint32_t *)0x4003204C))
+#define TIMER2_TAV_R (*((volatile uint32_t *)0x40032050))
+#define TIMER2_TBV_R (*((volatile uint32_t *)0x40032054))
+#define TIMER2_RTCPD_R (*((volatile uint32_t *)0x40032058))
+#define TIMER2_TAPS_R (*((volatile uint32_t *)0x4003205C))
+#define TIMER2_TBPS_R (*((volatile uint32_t *)0x40032060))
+#define TIMER2_TAPV_R (*((volatile uint32_t *)0x40032064))
+#define TIMER2_TBPV_R (*((volatile uint32_t *)0x40032068))
+#define TIMER2_PP_R (*((volatile uint32_t *)0x40032FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER3)
+//
+//*****************************************************************************
+#define TIMER3_CFG_R (*((volatile uint32_t *)0x40033000))
+#define TIMER3_TAMR_R (*((volatile uint32_t *)0x40033004))
+#define TIMER3_TBMR_R (*((volatile uint32_t *)0x40033008))
+#define TIMER3_CTL_R (*((volatile uint32_t *)0x4003300C))
+#define TIMER3_SYNC_R (*((volatile uint32_t *)0x40033010))
+#define TIMER3_IMR_R (*((volatile uint32_t *)0x40033018))
+#define TIMER3_RIS_R (*((volatile uint32_t *)0x4003301C))
+#define TIMER3_MIS_R (*((volatile uint32_t *)0x40033020))
+#define TIMER3_ICR_R (*((volatile uint32_t *)0x40033024))
+#define TIMER3_TAILR_R (*((volatile uint32_t *)0x40033028))
+#define TIMER3_TBILR_R (*((volatile uint32_t *)0x4003302C))
+#define TIMER3_TAMATCHR_R (*((volatile uint32_t *)0x40033030))
+#define TIMER3_TBMATCHR_R (*((volatile uint32_t *)0x40033034))
+#define TIMER3_TAPR_R (*((volatile uint32_t *)0x40033038))
+#define TIMER3_TBPR_R (*((volatile uint32_t *)0x4003303C))
+#define TIMER3_TAPMR_R (*((volatile uint32_t *)0x40033040))
+#define TIMER3_TBPMR_R (*((volatile uint32_t *)0x40033044))
+#define TIMER3_TAR_R (*((volatile uint32_t *)0x40033048))
+#define TIMER3_TBR_R (*((volatile uint32_t *)0x4003304C))
+#define TIMER3_TAV_R (*((volatile uint32_t *)0x40033050))
+#define TIMER3_TBV_R (*((volatile uint32_t *)0x40033054))
+#define TIMER3_RTCPD_R (*((volatile uint32_t *)0x40033058))
+#define TIMER3_TAPS_R (*((volatile uint32_t *)0x4003305C))
+#define TIMER3_TBPS_R (*((volatile uint32_t *)0x40033060))
+#define TIMER3_TAPV_R (*((volatile uint32_t *)0x40033064))
+#define TIMER3_TBPV_R (*((volatile uint32_t *)0x40033068))
+#define TIMER3_PP_R (*((volatile uint32_t *)0x40033FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER4)
+//
+//*****************************************************************************
+#define TIMER4_CFG_R (*((volatile uint32_t *)0x40034000))
+#define TIMER4_TAMR_R (*((volatile uint32_t *)0x40034004))
+#define TIMER4_TBMR_R (*((volatile uint32_t *)0x40034008))
+#define TIMER4_CTL_R (*((volatile uint32_t *)0x4003400C))
+#define TIMER4_SYNC_R (*((volatile uint32_t *)0x40034010))
+#define TIMER4_IMR_R (*((volatile uint32_t *)0x40034018))
+#define TIMER4_RIS_R (*((volatile uint32_t *)0x4003401C))
+#define TIMER4_MIS_R (*((volatile uint32_t *)0x40034020))
+#define TIMER4_ICR_R (*((volatile uint32_t *)0x40034024))
+#define TIMER4_TAILR_R (*((volatile uint32_t *)0x40034028))
+#define TIMER4_TBILR_R (*((volatile uint32_t *)0x4003402C))
+#define TIMER4_TAMATCHR_R (*((volatile uint32_t *)0x40034030))
+#define TIMER4_TBMATCHR_R (*((volatile uint32_t *)0x40034034))
+#define TIMER4_TAPR_R (*((volatile uint32_t *)0x40034038))
+#define TIMER4_TBPR_R (*((volatile uint32_t *)0x4003403C))
+#define TIMER4_TAPMR_R (*((volatile uint32_t *)0x40034040))
+#define TIMER4_TBPMR_R (*((volatile uint32_t *)0x40034044))
+#define TIMER4_TAR_R (*((volatile uint32_t *)0x40034048))
+#define TIMER4_TBR_R (*((volatile uint32_t *)0x4003404C))
+#define TIMER4_TAV_R (*((volatile uint32_t *)0x40034050))
+#define TIMER4_TBV_R (*((volatile uint32_t *)0x40034054))
+#define TIMER4_RTCPD_R (*((volatile uint32_t *)0x40034058))
+#define TIMER4_TAPS_R (*((volatile uint32_t *)0x4003405C))
+#define TIMER4_TBPS_R (*((volatile uint32_t *)0x40034060))
+#define TIMER4_TAPV_R (*((volatile uint32_t *)0x40034064))
+#define TIMER4_TBPV_R (*((volatile uint32_t *)0x40034068))
+#define TIMER4_PP_R (*((volatile uint32_t *)0x40034FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER5)
+//
+//*****************************************************************************
+#define TIMER5_CFG_R (*((volatile uint32_t *)0x40035000))
+#define TIMER5_TAMR_R (*((volatile uint32_t *)0x40035004))
+#define TIMER5_TBMR_R (*((volatile uint32_t *)0x40035008))
+#define TIMER5_CTL_R (*((volatile uint32_t *)0x4003500C))
+#define TIMER5_SYNC_R (*((volatile uint32_t *)0x40035010))
+#define TIMER5_IMR_R (*((volatile uint32_t *)0x40035018))
+#define TIMER5_RIS_R (*((volatile uint32_t *)0x4003501C))
+#define TIMER5_MIS_R (*((volatile uint32_t *)0x40035020))
+#define TIMER5_ICR_R (*((volatile uint32_t *)0x40035024))
+#define TIMER5_TAILR_R (*((volatile uint32_t *)0x40035028))
+#define TIMER5_TBILR_R (*((volatile uint32_t *)0x4003502C))
+#define TIMER5_TAMATCHR_R (*((volatile uint32_t *)0x40035030))
+#define TIMER5_TBMATCHR_R (*((volatile uint32_t *)0x40035034))
+#define TIMER5_TAPR_R (*((volatile uint32_t *)0x40035038))
+#define TIMER5_TBPR_R (*((volatile uint32_t *)0x4003503C))
+#define TIMER5_TAPMR_R (*((volatile uint32_t *)0x40035040))
+#define TIMER5_TBPMR_R (*((volatile uint32_t *)0x40035044))
+#define TIMER5_TAR_R (*((volatile uint32_t *)0x40035048))
+#define TIMER5_TBR_R (*((volatile uint32_t *)0x4003504C))
+#define TIMER5_TAV_R (*((volatile uint32_t *)0x40035050))
+#define TIMER5_TBV_R (*((volatile uint32_t *)0x40035054))
+#define TIMER5_RTCPD_R (*((volatile uint32_t *)0x40035058))
+#define TIMER5_TAPS_R (*((volatile uint32_t *)0x4003505C))
+#define TIMER5_TBPS_R (*((volatile uint32_t *)0x40035060))
+#define TIMER5_TAPV_R (*((volatile uint32_t *)0x40035064))
+#define TIMER5_TBPV_R (*((volatile uint32_t *)0x40035068))
+#define TIMER5_PP_R (*((volatile uint32_t *)0x40035FC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER0)
+//
+//*****************************************************************************
+#define WTIMER0_CFG_R (*((volatile uint32_t *)0x40036000))
+#define WTIMER0_TAMR_R (*((volatile uint32_t *)0x40036004))
+#define WTIMER0_TBMR_R (*((volatile uint32_t *)0x40036008))
+#define WTIMER0_CTL_R (*((volatile uint32_t *)0x4003600C))
+#define WTIMER0_SYNC_R (*((volatile uint32_t *)0x40036010))
+#define WTIMER0_IMR_R (*((volatile uint32_t *)0x40036018))
+#define WTIMER0_RIS_R (*((volatile uint32_t *)0x4003601C))
+#define WTIMER0_MIS_R (*((volatile uint32_t *)0x40036020))
+#define WTIMER0_ICR_R (*((volatile uint32_t *)0x40036024))
+#define WTIMER0_TAILR_R (*((volatile uint32_t *)0x40036028))
+#define WTIMER0_TBILR_R (*((volatile uint32_t *)0x4003602C))
+#define WTIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40036030))
+#define WTIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40036034))
+#define WTIMER0_TAPR_R (*((volatile uint32_t *)0x40036038))
+#define WTIMER0_TBPR_R (*((volatile uint32_t *)0x4003603C))
+#define WTIMER0_TAPMR_R (*((volatile uint32_t *)0x40036040))
+#define WTIMER0_TBPMR_R (*((volatile uint32_t *)0x40036044))
+#define WTIMER0_TAR_R (*((volatile uint32_t *)0x40036048))
+#define WTIMER0_TBR_R (*((volatile uint32_t *)0x4003604C))
+#define WTIMER0_TAV_R (*((volatile uint32_t *)0x40036050))
+#define WTIMER0_TBV_R (*((volatile uint32_t *)0x40036054))
+#define WTIMER0_RTCPD_R (*((volatile uint32_t *)0x40036058))
+#define WTIMER0_TAPS_R (*((volatile uint32_t *)0x4003605C))
+#define WTIMER0_TBPS_R (*((volatile uint32_t *)0x40036060))
+#define WTIMER0_TAPV_R (*((volatile uint32_t *)0x40036064))
+#define WTIMER0_TBPV_R (*((volatile uint32_t *)0x40036068))
+#define WTIMER0_PP_R (*((volatile uint32_t *)0x40036FC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER1)
+//
+//*****************************************************************************
+#define WTIMER1_CFG_R (*((volatile uint32_t *)0x40037000))
+#define WTIMER1_TAMR_R (*((volatile uint32_t *)0x40037004))
+#define WTIMER1_TBMR_R (*((volatile uint32_t *)0x40037008))
+#define WTIMER1_CTL_R (*((volatile uint32_t *)0x4003700C))
+#define WTIMER1_SYNC_R (*((volatile uint32_t *)0x40037010))
+#define WTIMER1_IMR_R (*((volatile uint32_t *)0x40037018))
+#define WTIMER1_RIS_R (*((volatile uint32_t *)0x4003701C))
+#define WTIMER1_MIS_R (*((volatile uint32_t *)0x40037020))
+#define WTIMER1_ICR_R (*((volatile uint32_t *)0x40037024))
+#define WTIMER1_TAILR_R (*((volatile uint32_t *)0x40037028))
+#define WTIMER1_TBILR_R (*((volatile uint32_t *)0x4003702C))
+#define WTIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40037030))
+#define WTIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40037034))
+#define WTIMER1_TAPR_R (*((volatile uint32_t *)0x40037038))
+#define WTIMER1_TBPR_R (*((volatile uint32_t *)0x4003703C))
+#define WTIMER1_TAPMR_R (*((volatile uint32_t *)0x40037040))
+#define WTIMER1_TBPMR_R (*((volatile uint32_t *)0x40037044))
+#define WTIMER1_TAR_R (*((volatile uint32_t *)0x40037048))
+#define WTIMER1_TBR_R (*((volatile uint32_t *)0x4003704C))
+#define WTIMER1_TAV_R (*((volatile uint32_t *)0x40037050))
+#define WTIMER1_TBV_R (*((volatile uint32_t *)0x40037054))
+#define WTIMER1_RTCPD_R (*((volatile uint32_t *)0x40037058))
+#define WTIMER1_TAPS_R (*((volatile uint32_t *)0x4003705C))
+#define WTIMER1_TBPS_R (*((volatile uint32_t *)0x40037060))
+#define WTIMER1_TAPV_R (*((volatile uint32_t *)0x40037064))
+#define WTIMER1_TBPV_R (*((volatile uint32_t *)0x40037068))
+#define WTIMER1_PP_R (*((volatile uint32_t *)0x40037FC0))
+
+//*****************************************************************************
+//
+// ADC registers (ADC0)
+//
+//*****************************************************************************
+#define ADC0_ACTSS_R (*((volatile uint32_t *)0x40038000))
+#define ADC0_RIS_R (*((volatile uint32_t *)0x40038004))
+#define ADC0_IM_R (*((volatile uint32_t *)0x40038008))
+#define ADC0_ISC_R (*((volatile uint32_t *)0x4003800C))
+#define ADC0_OSTAT_R (*((volatile uint32_t *)0x40038010))
+#define ADC0_EMUX_R (*((volatile uint32_t *)0x40038014))
+#define ADC0_USTAT_R (*((volatile uint32_t *)0x40038018))
+#define ADC0_TSSEL_R (*((volatile uint32_t *)0x4003801C))
+#define ADC0_SSPRI_R (*((volatile uint32_t *)0x40038020))
+#define ADC0_SPC_R (*((volatile uint32_t *)0x40038024))
+#define ADC0_PSSI_R (*((volatile uint32_t *)0x40038028))
+#define ADC0_SAC_R (*((volatile uint32_t *)0x40038030))
+#define ADC0_DCISC_R (*((volatile uint32_t *)0x40038034))
+#define ADC0_CTL_R (*((volatile uint32_t *)0x40038038))
+#define ADC0_SSMUX0_R (*((volatile uint32_t *)0x40038040))
+#define ADC0_SSCTL0_R (*((volatile uint32_t *)0x40038044))
+#define ADC0_SSFIFO0_R (*((volatile uint32_t *)0x40038048))
+#define ADC0_SSFSTAT0_R (*((volatile uint32_t *)0x4003804C))
+#define ADC0_SSOP0_R (*((volatile uint32_t *)0x40038050))
+#define ADC0_SSDC0_R (*((volatile uint32_t *)0x40038054))
+#define ADC0_SSEMUX0_R (*((volatile uint32_t *)0x40038058))
+#define ADC0_SSMUX1_R (*((volatile uint32_t *)0x40038060))
+#define ADC0_SSCTL1_R (*((volatile uint32_t *)0x40038064))
+#define ADC0_SSFIFO1_R (*((volatile uint32_t *)0x40038068))
+#define ADC0_SSFSTAT1_R (*((volatile uint32_t *)0x4003806C))
+#define ADC0_SSOP1_R (*((volatile uint32_t *)0x40038070))
+#define ADC0_SSDC1_R (*((volatile uint32_t *)0x40038074))
+#define ADC0_SSEMUX1_R (*((volatile uint32_t *)0x40038078))
+#define ADC0_SSMUX2_R (*((volatile uint32_t *)0x40038080))
+#define ADC0_SSCTL2_R (*((volatile uint32_t *)0x40038084))
+#define ADC0_SSFIFO2_R (*((volatile uint32_t *)0x40038088))
+#define ADC0_SSFSTAT2_R (*((volatile uint32_t *)0x4003808C))
+#define ADC0_SSOP2_R (*((volatile uint32_t *)0x40038090))
+#define ADC0_SSDC2_R (*((volatile uint32_t *)0x40038094))
+#define ADC0_SSEMUX2_R (*((volatile uint32_t *)0x40038098))
+#define ADC0_SSMUX3_R (*((volatile uint32_t *)0x400380A0))
+#define ADC0_SSCTL3_R (*((volatile uint32_t *)0x400380A4))
+#define ADC0_SSFIFO3_R (*((volatile uint32_t *)0x400380A8))
+#define ADC0_SSFSTAT3_R (*((volatile uint32_t *)0x400380AC))
+#define ADC0_SSOP3_R (*((volatile uint32_t *)0x400380B0))
+#define ADC0_SSDC3_R (*((volatile uint32_t *)0x400380B4))
+#define ADC0_SSEMUX3_R (*((volatile uint32_t *)0x400380B8))
+#define ADC0_DCRIC_R (*((volatile uint32_t *)0x40038D00))
+#define ADC0_DCCTL0_R (*((volatile uint32_t *)0x40038E00))
+#define ADC0_DCCTL1_R (*((volatile uint32_t *)0x40038E04))
+#define ADC0_DCCTL2_R (*((volatile uint32_t *)0x40038E08))
+#define ADC0_DCCTL3_R (*((volatile uint32_t *)0x40038E0C))
+#define ADC0_DCCTL4_R (*((volatile uint32_t *)0x40038E10))
+#define ADC0_DCCTL5_R (*((volatile uint32_t *)0x40038E14))
+#define ADC0_DCCTL6_R (*((volatile uint32_t *)0x40038E18))
+#define ADC0_DCCTL7_R (*((volatile uint32_t *)0x40038E1C))
+#define ADC0_DCCMP0_R (*((volatile uint32_t *)0x40038E40))
+#define ADC0_DCCMP1_R (*((volatile uint32_t *)0x40038E44))
+#define ADC0_DCCMP2_R (*((volatile uint32_t *)0x40038E48))
+#define ADC0_DCCMP3_R (*((volatile uint32_t *)0x40038E4C))
+#define ADC0_DCCMP4_R (*((volatile uint32_t *)0x40038E50))
+#define ADC0_DCCMP5_R (*((volatile uint32_t *)0x40038E54))
+#define ADC0_DCCMP6_R (*((volatile uint32_t *)0x40038E58))
+#define ADC0_DCCMP7_R (*((volatile uint32_t *)0x40038E5C))
+#define ADC0_PP_R (*((volatile uint32_t *)0x40038FC0))
+#define ADC0_PC_R (*((volatile uint32_t *)0x40038FC4))
+#define ADC0_CC_R (*((volatile uint32_t *)0x40038FC8))
+
+//*****************************************************************************
+//
+// ADC registers (ADC1)
+//
+//*****************************************************************************
+#define ADC1_ACTSS_R (*((volatile uint32_t *)0x40039000))
+#define ADC1_RIS_R (*((volatile uint32_t *)0x40039004))
+#define ADC1_IM_R (*((volatile uint32_t *)0x40039008))
+#define ADC1_ISC_R (*((volatile uint32_t *)0x4003900C))
+#define ADC1_OSTAT_R (*((volatile uint32_t *)0x40039010))
+#define ADC1_EMUX_R (*((volatile uint32_t *)0x40039014))
+#define ADC1_USTAT_R (*((volatile uint32_t *)0x40039018))
+#define ADC1_TSSEL_R (*((volatile uint32_t *)0x4003901C))
+#define ADC1_SSPRI_R (*((volatile uint32_t *)0x40039020))
+#define ADC1_SPC_R (*((volatile uint32_t *)0x40039024))
+#define ADC1_PSSI_R (*((volatile uint32_t *)0x40039028))
+#define ADC1_SAC_R (*((volatile uint32_t *)0x40039030))
+#define ADC1_DCISC_R (*((volatile uint32_t *)0x40039034))
+#define ADC1_CTL_R (*((volatile uint32_t *)0x40039038))
+#define ADC1_SSMUX0_R (*((volatile uint32_t *)0x40039040))
+#define ADC1_SSCTL0_R (*((volatile uint32_t *)0x40039044))
+#define ADC1_SSFIFO0_R (*((volatile uint32_t *)0x40039048))
+#define ADC1_SSFSTAT0_R (*((volatile uint32_t *)0x4003904C))
+#define ADC1_SSOP0_R (*((volatile uint32_t *)0x40039050))
+#define ADC1_SSDC0_R (*((volatile uint32_t *)0x40039054))
+#define ADC1_SSEMUX0_R (*((volatile uint32_t *)0x40039058))
+#define ADC1_SSMUX1_R (*((volatile uint32_t *)0x40039060))
+#define ADC1_SSCTL1_R (*((volatile uint32_t *)0x40039064))
+#define ADC1_SSFIFO1_R (*((volatile uint32_t *)0x40039068))
+#define ADC1_SSFSTAT1_R (*((volatile uint32_t *)0x4003906C))
+#define ADC1_SSOP1_R (*((volatile uint32_t *)0x40039070))
+#define ADC1_SSDC1_R (*((volatile uint32_t *)0x40039074))
+#define ADC1_SSEMUX1_R (*((volatile uint32_t *)0x40039078))
+#define ADC1_SSMUX2_R (*((volatile uint32_t *)0x40039080))
+#define ADC1_SSCTL2_R (*((volatile uint32_t *)0x40039084))
+#define ADC1_SSFIFO2_R (*((volatile uint32_t *)0x40039088))
+#define ADC1_SSFSTAT2_R (*((volatile uint32_t *)0x4003908C))
+#define ADC1_SSOP2_R (*((volatile uint32_t *)0x40039090))
+#define ADC1_SSDC2_R (*((volatile uint32_t *)0x40039094))
+#define ADC1_SSEMUX2_R (*((volatile uint32_t *)0x40039098))
+#define ADC1_SSMUX3_R (*((volatile uint32_t *)0x400390A0))
+#define ADC1_SSCTL3_R (*((volatile uint32_t *)0x400390A4))
+#define ADC1_SSFIFO3_R (*((volatile uint32_t *)0x400390A8))
+#define ADC1_SSFSTAT3_R (*((volatile uint32_t *)0x400390AC))
+#define ADC1_SSOP3_R (*((volatile uint32_t *)0x400390B0))
+#define ADC1_SSDC3_R (*((volatile uint32_t *)0x400390B4))
+#define ADC1_SSEMUX3_R (*((volatile uint32_t *)0x400390B8))
+#define ADC1_DCRIC_R (*((volatile uint32_t *)0x40039D00))
+#define ADC1_DCCTL0_R (*((volatile uint32_t *)0x40039E00))
+#define ADC1_DCCTL1_R (*((volatile uint32_t *)0x40039E04))
+#define ADC1_DCCTL2_R (*((volatile uint32_t *)0x40039E08))
+#define ADC1_DCCTL3_R (*((volatile uint32_t *)0x40039E0C))
+#define ADC1_DCCTL4_R (*((volatile uint32_t *)0x40039E10))
+#define ADC1_DCCTL5_R (*((volatile uint32_t *)0x40039E14))
+#define ADC1_DCCTL6_R (*((volatile uint32_t *)0x40039E18))
+#define ADC1_DCCTL7_R (*((volatile uint32_t *)0x40039E1C))
+#define ADC1_DCCMP0_R (*((volatile uint32_t *)0x40039E40))
+#define ADC1_DCCMP1_R (*((volatile uint32_t *)0x40039E44))
+#define ADC1_DCCMP2_R (*((volatile uint32_t *)0x40039E48))
+#define ADC1_DCCMP3_R (*((volatile uint32_t *)0x40039E4C))
+#define ADC1_DCCMP4_R (*((volatile uint32_t *)0x40039E50))
+#define ADC1_DCCMP5_R (*((volatile uint32_t *)0x40039E54))
+#define ADC1_DCCMP6_R (*((volatile uint32_t *)0x40039E58))
+#define ADC1_DCCMP7_R (*((volatile uint32_t *)0x40039E5C))
+#define ADC1_PP_R (*((volatile uint32_t *)0x40039FC0))
+#define ADC1_PC_R (*((volatile uint32_t *)0x40039FC4))
+#define ADC1_CC_R (*((volatile uint32_t *)0x40039FC8))
+
+//*****************************************************************************
+//
+// Comparator registers (COMP)
+//
+//*****************************************************************************
+#define COMP_ACMIS_R (*((volatile uint32_t *)0x4003C000))
+#define COMP_ACRIS_R (*((volatile uint32_t *)0x4003C004))
+#define COMP_ACINTEN_R (*((volatile uint32_t *)0x4003C008))
+#define COMP_ACREFCTL_R (*((volatile uint32_t *)0x4003C010))
+#define COMP_ACSTAT0_R (*((volatile uint32_t *)0x4003C020))
+#define COMP_ACCTL0_R (*((volatile uint32_t *)0x4003C024))
+#define COMP_ACSTAT1_R (*((volatile uint32_t *)0x4003C040))
+#define COMP_ACCTL1_R (*((volatile uint32_t *)0x4003C044))
+#define COMP_ACSTAT2_R (*((volatile uint32_t *)0x4003C060))
+#define COMP_ACCTL2_R (*((volatile uint32_t *)0x4003C064))
+#define COMP_PP_R (*((volatile uint32_t *)0x4003CFC0))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTJ)
+//
+//*****************************************************************************
+#define GPIO_PORTJ_DATA_BITS_R ((volatile uint32_t *)0x4003D000)
+#define GPIO_PORTJ_DATA_R (*((volatile uint32_t *)0x4003D3FC))
+#define GPIO_PORTJ_DIR_R (*((volatile uint32_t *)0x4003D400))
+#define GPIO_PORTJ_IS_R (*((volatile uint32_t *)0x4003D404))
+#define GPIO_PORTJ_IBE_R (*((volatile uint32_t *)0x4003D408))
+#define GPIO_PORTJ_IEV_R (*((volatile uint32_t *)0x4003D40C))
+#define GPIO_PORTJ_IM_R (*((volatile uint32_t *)0x4003D410))
+#define GPIO_PORTJ_RIS_R (*((volatile uint32_t *)0x4003D414))
+#define GPIO_PORTJ_MIS_R (*((volatile uint32_t *)0x4003D418))
+#define GPIO_PORTJ_ICR_R (*((volatile uint32_t *)0x4003D41C))
+#define GPIO_PORTJ_AFSEL_R (*((volatile uint32_t *)0x4003D420))
+#define GPIO_PORTJ_DR2R_R (*((volatile uint32_t *)0x4003D500))
+#define GPIO_PORTJ_DR4R_R (*((volatile uint32_t *)0x4003D504))
+#define GPIO_PORTJ_DR8R_R (*((volatile uint32_t *)0x4003D508))
+#define GPIO_PORTJ_ODR_R (*((volatile uint32_t *)0x4003D50C))
+#define GPIO_PORTJ_PUR_R (*((volatile uint32_t *)0x4003D510))
+#define GPIO_PORTJ_PDR_R (*((volatile uint32_t *)0x4003D514))
+#define GPIO_PORTJ_SLR_R (*((volatile uint32_t *)0x4003D518))
+#define GPIO_PORTJ_DEN_R (*((volatile uint32_t *)0x4003D51C))
+#define GPIO_PORTJ_LOCK_R (*((volatile uint32_t *)0x4003D520))
+#define GPIO_PORTJ_CR_R (*((volatile uint32_t *)0x4003D524))
+#define GPIO_PORTJ_AMSEL_R (*((volatile uint32_t *)0x4003D528))
+#define GPIO_PORTJ_PCTL_R (*((volatile uint32_t *)0x4003D52C))
+#define GPIO_PORTJ_ADCCTL_R (*((volatile uint32_t *)0x4003D530))
+#define GPIO_PORTJ_DMACTL_R (*((volatile uint32_t *)0x4003D534))
+#define GPIO_PORTJ_SI_R (*((volatile uint32_t *)0x4003D538))
+
+//*****************************************************************************
+//
+// CAN registers (CAN0)
+//
+//*****************************************************************************
+#define CAN0_CTL_R (*((volatile uint32_t *)0x40040000))
+#define CAN0_STS_R (*((volatile uint32_t *)0x40040004))
+#define CAN0_ERR_R (*((volatile uint32_t *)0x40040008))
+#define CAN0_BIT_R (*((volatile uint32_t *)0x4004000C))
+#define CAN0_INT_R (*((volatile uint32_t *)0x40040010))
+#define CAN0_TST_R (*((volatile uint32_t *)0x40040014))
+#define CAN0_BRPE_R (*((volatile uint32_t *)0x40040018))
+#define CAN0_IF1CRQ_R (*((volatile uint32_t *)0x40040020))
+#define CAN0_IF1CMSK_R (*((volatile uint32_t *)0x40040024))
+#define CAN0_IF1MSK1_R (*((volatile uint32_t *)0x40040028))
+#define CAN0_IF1MSK2_R (*((volatile uint32_t *)0x4004002C))
+#define CAN0_IF1ARB1_R (*((volatile uint32_t *)0x40040030))
+#define CAN0_IF1ARB2_R (*((volatile uint32_t *)0x40040034))
+#define CAN0_IF1MCTL_R (*((volatile uint32_t *)0x40040038))
+#define CAN0_IF1DA1_R (*((volatile uint32_t *)0x4004003C))
+#define CAN0_IF1DA2_R (*((volatile uint32_t *)0x40040040))
+#define CAN0_IF1DB1_R (*((volatile uint32_t *)0x40040044))
+#define CAN0_IF1DB2_R (*((volatile uint32_t *)0x40040048))
+#define CAN0_IF2CRQ_R (*((volatile uint32_t *)0x40040080))
+#define CAN0_IF2CMSK_R (*((volatile uint32_t *)0x40040084))
+#define CAN0_IF2MSK1_R (*((volatile uint32_t *)0x40040088))
+#define CAN0_IF2MSK2_R (*((volatile uint32_t *)0x4004008C))
+#define CAN0_IF2ARB1_R (*((volatile uint32_t *)0x40040090))
+#define CAN0_IF2ARB2_R (*((volatile uint32_t *)0x40040094))
+#define CAN0_IF2MCTL_R (*((volatile uint32_t *)0x40040098))
+#define CAN0_IF2DA1_R (*((volatile uint32_t *)0x4004009C))
+#define CAN0_IF2DA2_R (*((volatile uint32_t *)0x400400A0))
+#define CAN0_IF2DB1_R (*((volatile uint32_t *)0x400400A4))
+#define CAN0_IF2DB2_R (*((volatile uint32_t *)0x400400A8))
+#define CAN0_TXRQ1_R (*((volatile uint32_t *)0x40040100))
+#define CAN0_TXRQ2_R (*((volatile uint32_t *)0x40040104))
+#define CAN0_NWDA1_R (*((volatile uint32_t *)0x40040120))
+#define CAN0_NWDA2_R (*((volatile uint32_t *)0x40040124))
+#define CAN0_MSG1INT_R (*((volatile uint32_t *)0x40040140))
+#define CAN0_MSG2INT_R (*((volatile uint32_t *)0x40040144))
+#define CAN0_MSG1VAL_R (*((volatile uint32_t *)0x40040160))
+#define CAN0_MSG2VAL_R (*((volatile uint32_t *)0x40040164))
+
+//*****************************************************************************
+//
+// CAN registers (CAN1)
+//
+//*****************************************************************************
+#define CAN1_CTL_R (*((volatile uint32_t *)0x40041000))
+#define CAN1_STS_R (*((volatile uint32_t *)0x40041004))
+#define CAN1_ERR_R (*((volatile uint32_t *)0x40041008))
+#define CAN1_BIT_R (*((volatile uint32_t *)0x4004100C))
+#define CAN1_INT_R (*((volatile uint32_t *)0x40041010))
+#define CAN1_TST_R (*((volatile uint32_t *)0x40041014))
+#define CAN1_BRPE_R (*((volatile uint32_t *)0x40041018))
+#define CAN1_IF1CRQ_R (*((volatile uint32_t *)0x40041020))
+#define CAN1_IF1CMSK_R (*((volatile uint32_t *)0x40041024))
+#define CAN1_IF1MSK1_R (*((volatile uint32_t *)0x40041028))
+#define CAN1_IF1MSK2_R (*((volatile uint32_t *)0x4004102C))
+#define CAN1_IF1ARB1_R (*((volatile uint32_t *)0x40041030))
+#define CAN1_IF1ARB2_R (*((volatile uint32_t *)0x40041034))
+#define CAN1_IF1MCTL_R (*((volatile uint32_t *)0x40041038))
+#define CAN1_IF1DA1_R (*((volatile uint32_t *)0x4004103C))
+#define CAN1_IF1DA2_R (*((volatile uint32_t *)0x40041040))
+#define CAN1_IF1DB1_R (*((volatile uint32_t *)0x40041044))
+#define CAN1_IF1DB2_R (*((volatile uint32_t *)0x40041048))
+#define CAN1_IF2CRQ_R (*((volatile uint32_t *)0x40041080))
+#define CAN1_IF2CMSK_R (*((volatile uint32_t *)0x40041084))
+#define CAN1_IF2MSK1_R (*((volatile uint32_t *)0x40041088))
+#define CAN1_IF2MSK2_R (*((volatile uint32_t *)0x4004108C))
+#define CAN1_IF2ARB1_R (*((volatile uint32_t *)0x40041090))
+#define CAN1_IF2ARB2_R (*((volatile uint32_t *)0x40041094))
+#define CAN1_IF2MCTL_R (*((volatile uint32_t *)0x40041098))
+#define CAN1_IF2DA1_R (*((volatile uint32_t *)0x4004109C))
+#define CAN1_IF2DA2_R (*((volatile uint32_t *)0x400410A0))
+#define CAN1_IF2DB1_R (*((volatile uint32_t *)0x400410A4))
+#define CAN1_IF2DB2_R (*((volatile uint32_t *)0x400410A8))
+#define CAN1_TXRQ1_R (*((volatile uint32_t *)0x40041100))
+#define CAN1_TXRQ2_R (*((volatile uint32_t *)0x40041104))
+#define CAN1_NWDA1_R (*((volatile uint32_t *)0x40041120))
+#define CAN1_NWDA2_R (*((volatile uint32_t *)0x40041124))
+#define CAN1_MSG1INT_R (*((volatile uint32_t *)0x40041140))
+#define CAN1_MSG2INT_R (*((volatile uint32_t *)0x40041144))
+#define CAN1_MSG1VAL_R (*((volatile uint32_t *)0x40041160))
+#define CAN1_MSG2VAL_R (*((volatile uint32_t *)0x40041164))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER2)
+//
+//*****************************************************************************
+#define WTIMER2_CFG_R (*((volatile uint32_t *)0x4004C000))
+#define WTIMER2_TAMR_R (*((volatile uint32_t *)0x4004C004))
+#define WTIMER2_TBMR_R (*((volatile uint32_t *)0x4004C008))
+#define WTIMER2_CTL_R (*((volatile uint32_t *)0x4004C00C))
+#define WTIMER2_SYNC_R (*((volatile uint32_t *)0x4004C010))
+#define WTIMER2_IMR_R (*((volatile uint32_t *)0x4004C018))
+#define WTIMER2_RIS_R (*((volatile uint32_t *)0x4004C01C))
+#define WTIMER2_MIS_R (*((volatile uint32_t *)0x4004C020))
+#define WTIMER2_ICR_R (*((volatile uint32_t *)0x4004C024))
+#define WTIMER2_TAILR_R (*((volatile uint32_t *)0x4004C028))
+#define WTIMER2_TBILR_R (*((volatile uint32_t *)0x4004C02C))
+#define WTIMER2_TAMATCHR_R (*((volatile uint32_t *)0x4004C030))
+#define WTIMER2_TBMATCHR_R (*((volatile uint32_t *)0x4004C034))
+#define WTIMER2_TAPR_R (*((volatile uint32_t *)0x4004C038))
+#define WTIMER2_TBPR_R (*((volatile uint32_t *)0x4004C03C))
+#define WTIMER2_TAPMR_R (*((volatile uint32_t *)0x4004C040))
+#define WTIMER2_TBPMR_R (*((volatile uint32_t *)0x4004C044))
+#define WTIMER2_TAR_R (*((volatile uint32_t *)0x4004C048))
+#define WTIMER2_TBR_R (*((volatile uint32_t *)0x4004C04C))
+#define WTIMER2_TAV_R (*((volatile uint32_t *)0x4004C050))
+#define WTIMER2_TBV_R (*((volatile uint32_t *)0x4004C054))
+#define WTIMER2_RTCPD_R (*((volatile uint32_t *)0x4004C058))
+#define WTIMER2_TAPS_R (*((volatile uint32_t *)0x4004C05C))
+#define WTIMER2_TBPS_R (*((volatile uint32_t *)0x4004C060))
+#define WTIMER2_TAPV_R (*((volatile uint32_t *)0x4004C064))
+#define WTIMER2_TBPV_R (*((volatile uint32_t *)0x4004C068))
+#define WTIMER2_PP_R (*((volatile uint32_t *)0x4004CFC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER3)
+//
+//*****************************************************************************
+#define WTIMER3_CFG_R (*((volatile uint32_t *)0x4004D000))
+#define WTIMER3_TAMR_R (*((volatile uint32_t *)0x4004D004))
+#define WTIMER3_TBMR_R (*((volatile uint32_t *)0x4004D008))
+#define WTIMER3_CTL_R (*((volatile uint32_t *)0x4004D00C))
+#define WTIMER3_SYNC_R (*((volatile uint32_t *)0x4004D010))
+#define WTIMER3_IMR_R (*((volatile uint32_t *)0x4004D018))
+#define WTIMER3_RIS_R (*((volatile uint32_t *)0x4004D01C))
+#define WTIMER3_MIS_R (*((volatile uint32_t *)0x4004D020))
+#define WTIMER3_ICR_R (*((volatile uint32_t *)0x4004D024))
+#define WTIMER3_TAILR_R (*((volatile uint32_t *)0x4004D028))
+#define WTIMER3_TBILR_R (*((volatile uint32_t *)0x4004D02C))
+#define WTIMER3_TAMATCHR_R (*((volatile uint32_t *)0x4004D030))
+#define WTIMER3_TBMATCHR_R (*((volatile uint32_t *)0x4004D034))
+#define WTIMER3_TAPR_R (*((volatile uint32_t *)0x4004D038))
+#define WTIMER3_TBPR_R (*((volatile uint32_t *)0x4004D03C))
+#define WTIMER3_TAPMR_R (*((volatile uint32_t *)0x4004D040))
+#define WTIMER3_TBPMR_R (*((volatile uint32_t *)0x4004D044))
+#define WTIMER3_TAR_R (*((volatile uint32_t *)0x4004D048))
+#define WTIMER3_TBR_R (*((volatile uint32_t *)0x4004D04C))
+#define WTIMER3_TAV_R (*((volatile uint32_t *)0x4004D050))
+#define WTIMER3_TBV_R (*((volatile uint32_t *)0x4004D054))
+#define WTIMER3_RTCPD_R (*((volatile uint32_t *)0x4004D058))
+#define WTIMER3_TAPS_R (*((volatile uint32_t *)0x4004D05C))
+#define WTIMER3_TBPS_R (*((volatile uint32_t *)0x4004D060))
+#define WTIMER3_TAPV_R (*((volatile uint32_t *)0x4004D064))
+#define WTIMER3_TBPV_R (*((volatile uint32_t *)0x4004D068))
+#define WTIMER3_PP_R (*((volatile uint32_t *)0x4004DFC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER4)
+//
+//*****************************************************************************
+#define WTIMER4_CFG_R (*((volatile uint32_t *)0x4004E000))
+#define WTIMER4_TAMR_R (*((volatile uint32_t *)0x4004E004))
+#define WTIMER4_TBMR_R (*((volatile uint32_t *)0x4004E008))
+#define WTIMER4_CTL_R (*((volatile uint32_t *)0x4004E00C))
+#define WTIMER4_SYNC_R (*((volatile uint32_t *)0x4004E010))
+#define WTIMER4_IMR_R (*((volatile uint32_t *)0x4004E018))
+#define WTIMER4_RIS_R (*((volatile uint32_t *)0x4004E01C))
+#define WTIMER4_MIS_R (*((volatile uint32_t *)0x4004E020))
+#define WTIMER4_ICR_R (*((volatile uint32_t *)0x4004E024))
+#define WTIMER4_TAILR_R (*((volatile uint32_t *)0x4004E028))
+#define WTIMER4_TBILR_R (*((volatile uint32_t *)0x4004E02C))
+#define WTIMER4_TAMATCHR_R (*((volatile uint32_t *)0x4004E030))
+#define WTIMER4_TBMATCHR_R (*((volatile uint32_t *)0x4004E034))
+#define WTIMER4_TAPR_R (*((volatile uint32_t *)0x4004E038))
+#define WTIMER4_TBPR_R (*((volatile uint32_t *)0x4004E03C))
+#define WTIMER4_TAPMR_R (*((volatile uint32_t *)0x4004E040))
+#define WTIMER4_TBPMR_R (*((volatile uint32_t *)0x4004E044))
+#define WTIMER4_TAR_R (*((volatile uint32_t *)0x4004E048))
+#define WTIMER4_TBR_R (*((volatile uint32_t *)0x4004E04C))
+#define WTIMER4_TAV_R (*((volatile uint32_t *)0x4004E050))
+#define WTIMER4_TBV_R (*((volatile uint32_t *)0x4004E054))
+#define WTIMER4_RTCPD_R (*((volatile uint32_t *)0x4004E058))
+#define WTIMER4_TAPS_R (*((volatile uint32_t *)0x4004E05C))
+#define WTIMER4_TBPS_R (*((volatile uint32_t *)0x4004E060))
+#define WTIMER4_TAPV_R (*((volatile uint32_t *)0x4004E064))
+#define WTIMER4_TBPV_R (*((volatile uint32_t *)0x4004E068))
+#define WTIMER4_PP_R (*((volatile uint32_t *)0x4004EFC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER5)
+//
+//*****************************************************************************
+#define WTIMER5_CFG_R (*((volatile uint32_t *)0x4004F000))
+#define WTIMER5_TAMR_R (*((volatile uint32_t *)0x4004F004))
+#define WTIMER5_TBMR_R (*((volatile uint32_t *)0x4004F008))
+#define WTIMER5_CTL_R (*((volatile uint32_t *)0x4004F00C))
+#define WTIMER5_SYNC_R (*((volatile uint32_t *)0x4004F010))
+#define WTIMER5_IMR_R (*((volatile uint32_t *)0x4004F018))
+#define WTIMER5_RIS_R (*((volatile uint32_t *)0x4004F01C))
+#define WTIMER5_MIS_R (*((volatile uint32_t *)0x4004F020))
+#define WTIMER5_ICR_R (*((volatile uint32_t *)0x4004F024))
+#define WTIMER5_TAILR_R (*((volatile uint32_t *)0x4004F028))
+#define WTIMER5_TBILR_R (*((volatile uint32_t *)0x4004F02C))
+#define WTIMER5_TAMATCHR_R (*((volatile uint32_t *)0x4004F030))
+#define WTIMER5_TBMATCHR_R (*((volatile uint32_t *)0x4004F034))
+#define WTIMER5_TAPR_R (*((volatile uint32_t *)0x4004F038))
+#define WTIMER5_TBPR_R (*((volatile uint32_t *)0x4004F03C))
+#define WTIMER5_TAPMR_R (*((volatile uint32_t *)0x4004F040))
+#define WTIMER5_TBPMR_R (*((volatile uint32_t *)0x4004F044))
+#define WTIMER5_TAR_R (*((volatile uint32_t *)0x4004F048))
+#define WTIMER5_TBR_R (*((volatile uint32_t *)0x4004F04C))
+#define WTIMER5_TAV_R (*((volatile uint32_t *)0x4004F050))
+#define WTIMER5_TBV_R (*((volatile uint32_t *)0x4004F054))
+#define WTIMER5_RTCPD_R (*((volatile uint32_t *)0x4004F058))
+#define WTIMER5_TAPS_R (*((volatile uint32_t *)0x4004F05C))
+#define WTIMER5_TBPS_R (*((volatile uint32_t *)0x4004F060))
+#define WTIMER5_TAPV_R (*((volatile uint32_t *)0x4004F064))
+#define WTIMER5_TBPV_R (*((volatile uint32_t *)0x4004F068))
+#define WTIMER5_PP_R (*((volatile uint32_t *)0x4004FFC0))
+
+//*****************************************************************************
+//
+// Univeral Serial Bus registers (USB0)
+//
+//*****************************************************************************
+#define USB0_FADDR_R (*((volatile uint8_t *)0x40050000))
+#define USB0_POWER_R (*((volatile uint8_t *)0x40050001))
+#define USB0_TXIS_R (*((volatile uint16_t *)0x40050002))
+#define USB0_RXIS_R (*((volatile uint16_t *)0x40050004))
+#define USB0_TXIE_R (*((volatile uint16_t *)0x40050006))
+#define USB0_RXIE_R (*((volatile uint16_t *)0x40050008))
+#define USB0_IS_R (*((volatile uint8_t *)0x4005000A))
+#define USB0_IE_R (*((volatile uint8_t *)0x4005000B))
+#define USB0_FRAME_R (*((volatile uint16_t *)0x4005000C))
+#define USB0_EPIDX_R (*((volatile uint8_t *)0x4005000E))
+#define USB0_TEST_R (*((volatile uint8_t *)0x4005000F))
+#define USB0_FIFO0_R (*((volatile uint32_t *)0x40050020))
+#define USB0_FIFO1_R (*((volatile uint32_t *)0x40050024))
+#define USB0_FIFO2_R (*((volatile uint32_t *)0x40050028))
+#define USB0_FIFO3_R (*((volatile uint32_t *)0x4005002C))
+#define USB0_FIFO4_R (*((volatile uint32_t *)0x40050030))
+#define USB0_FIFO5_R (*((volatile uint32_t *)0x40050034))
+#define USB0_FIFO6_R (*((volatile uint32_t *)0x40050038))
+#define USB0_FIFO7_R (*((volatile uint32_t *)0x4005003C))
+#define USB0_DEVCTL_R (*((volatile uint8_t *)0x40050060))
+#define USB0_TXFIFOSZ_R (*((volatile uint8_t *)0x40050062))
+#define USB0_RXFIFOSZ_R (*((volatile uint8_t *)0x40050063))
+#define USB0_TXFIFOADD_R (*((volatile uint16_t *)0x40050064))
+#define USB0_RXFIFOADD_R (*((volatile uint16_t *)0x40050066))
+#define USB0_CONTIM_R (*((volatile uint8_t *)0x4005007A))
+#define USB0_VPLEN_R (*((volatile uint8_t *)0x4005007B))
+#define USB0_FSEOF_R (*((volatile uint8_t *)0x4005007D))
+#define USB0_LSEOF_R (*((volatile uint8_t *)0x4005007E))
+#define USB0_TXFUNCADDR0_R (*((volatile uint8_t *)0x40050080))
+#define USB0_TXHUBADDR0_R (*((volatile uint8_t *)0x40050082))
+#define USB0_TXHUBPORT0_R (*((volatile uint8_t *)0x40050083))
+#define USB0_TXFUNCADDR1_R (*((volatile uint8_t *)0x40050088))
+#define USB0_TXHUBADDR1_R (*((volatile uint8_t *)0x4005008A))
+#define USB0_TXHUBPORT1_R (*((volatile uint8_t *)0x4005008B))
+#define USB0_RXFUNCADDR1_R (*((volatile uint8_t *)0x4005008C))
+#define USB0_RXHUBADDR1_R (*((volatile uint8_t *)0x4005008E))
+#define USB0_RXHUBPORT1_R (*((volatile uint8_t *)0x4005008F))
+#define USB0_TXFUNCADDR2_R (*((volatile uint8_t *)0x40050090))
+#define USB0_TXHUBADDR2_R (*((volatile uint8_t *)0x40050092))
+#define USB0_TXHUBPORT2_R (*((volatile uint8_t *)0x40050093))
+#define USB0_RXFUNCADDR2_R (*((volatile uint8_t *)0x40050094))
+#define USB0_RXHUBADDR2_R (*((volatile uint8_t *)0x40050096))
+#define USB0_RXHUBPORT2_R (*((volatile uint8_t *)0x40050097))
+#define USB0_TXFUNCADDR3_R (*((volatile uint8_t *)0x40050098))
+#define USB0_TXHUBADDR3_R (*((volatile uint8_t *)0x4005009A))
+#define USB0_TXHUBPORT3_R (*((volatile uint8_t *)0x4005009B))
+#define USB0_RXFUNCADDR3_R (*((volatile uint8_t *)0x4005009C))
+#define USB0_RXHUBADDR3_R (*((volatile uint8_t *)0x4005009E))
+#define USB0_RXHUBPORT3_R (*((volatile uint8_t *)0x4005009F))
+#define USB0_TXFUNCADDR4_R (*((volatile uint8_t *)0x400500A0))
+#define USB0_TXHUBADDR4_R (*((volatile uint8_t *)0x400500A2))
+#define USB0_TXHUBPORT4_R (*((volatile uint8_t *)0x400500A3))
+#define USB0_RXFUNCADDR4_R (*((volatile uint8_t *)0x400500A4))
+#define USB0_RXHUBADDR4_R (*((volatile uint8_t *)0x400500A6))
+#define USB0_RXHUBPORT4_R (*((volatile uint8_t *)0x400500A7))
+#define USB0_TXFUNCADDR5_R (*((volatile uint8_t *)0x400500A8))
+#define USB0_TXHUBADDR5_R (*((volatile uint8_t *)0x400500AA))
+#define USB0_TXHUBPORT5_R (*((volatile uint8_t *)0x400500AB))
+#define USB0_RXFUNCADDR5_R (*((volatile uint8_t *)0x400500AC))
+#define USB0_RXHUBADDR5_R (*((volatile uint8_t *)0x400500AE))
+#define USB0_RXHUBPORT5_R (*((volatile uint8_t *)0x400500AF))
+#define USB0_TXFUNCADDR6_R (*((volatile uint8_t *)0x400500B0))
+#define USB0_TXHUBADDR6_R (*((volatile uint8_t *)0x400500B2))
+#define USB0_TXHUBPORT6_R (*((volatile uint8_t *)0x400500B3))
+#define USB0_RXFUNCADDR6_R (*((volatile uint8_t *)0x400500B4))
+#define USB0_RXHUBADDR6_R (*((volatile uint8_t *)0x400500B6))
+#define USB0_RXHUBPORT6_R (*((volatile uint8_t *)0x400500B7))
+#define USB0_TXFUNCADDR7_R (*((volatile uint8_t *)0x400500B8))
+#define USB0_TXHUBADDR7_R (*((volatile uint8_t *)0x400500BA))
+#define USB0_TXHUBPORT7_R (*((volatile uint8_t *)0x400500BB))
+#define USB0_RXFUNCADDR7_R (*((volatile uint8_t *)0x400500BC))
+#define USB0_RXHUBADDR7_R (*((volatile uint8_t *)0x400500BE))
+#define USB0_RXHUBPORT7_R (*((volatile uint8_t *)0x400500BF))
+#define USB0_CSRL0_R (*((volatile uint8_t *)0x40050102))
+#define USB0_CSRH0_R (*((volatile uint8_t *)0x40050103))
+#define USB0_COUNT0_R (*((volatile uint8_t *)0x40050108))
+#define USB0_TYPE0_R (*((volatile uint8_t *)0x4005010A))
+#define USB0_NAKLMT_R (*((volatile uint8_t *)0x4005010B))
+#define USB0_TXMAXP1_R (*((volatile uint16_t *)0x40050110))
+#define USB0_TXCSRL1_R (*((volatile uint8_t *)0x40050112))
+#define USB0_TXCSRH1_R (*((volatile uint8_t *)0x40050113))
+#define USB0_RXMAXP1_R (*((volatile uint16_t *)0x40050114))
+#define USB0_RXCSRL1_R (*((volatile uint8_t *)0x40050116))
+#define USB0_RXCSRH1_R (*((volatile uint8_t *)0x40050117))
+#define USB0_RXCOUNT1_R (*((volatile uint16_t *)0x40050118))
+#define USB0_TXTYPE1_R (*((volatile uint8_t *)0x4005011A))
+#define USB0_TXINTERVAL1_R (*((volatile uint8_t *)0x4005011B))
+#define USB0_RXTYPE1_R (*((volatile uint8_t *)0x4005011C))
+#define USB0_RXINTERVAL1_R (*((volatile uint8_t *)0x4005011D))
+#define USB0_TXMAXP2_R (*((volatile uint16_t *)0x40050120))
+#define USB0_TXCSRL2_R (*((volatile uint8_t *)0x40050122))
+#define USB0_TXCSRH2_R (*((volatile uint8_t *)0x40050123))
+#define USB0_RXMAXP2_R (*((volatile uint16_t *)0x40050124))
+#define USB0_RXCSRL2_R (*((volatile uint8_t *)0x40050126))
+#define USB0_RXCSRH2_R (*((volatile uint8_t *)0x40050127))
+#define USB0_RXCOUNT2_R (*((volatile uint16_t *)0x40050128))
+#define USB0_TXTYPE2_R (*((volatile uint8_t *)0x4005012A))
+#define USB0_TXINTERVAL2_R (*((volatile uint8_t *)0x4005012B))
+#define USB0_RXTYPE2_R (*((volatile uint8_t *)0x4005012C))
+#define USB0_RXINTERVAL2_R (*((volatile uint8_t *)0x4005012D))
+#define USB0_TXMAXP3_R (*((volatile uint16_t *)0x40050130))
+#define USB0_TXCSRL3_R (*((volatile uint8_t *)0x40050132))
+#define USB0_TXCSRH3_R (*((volatile uint8_t *)0x40050133))
+#define USB0_RXMAXP3_R (*((volatile uint16_t *)0x40050134))
+#define USB0_RXCSRL3_R (*((volatile uint8_t *)0x40050136))
+#define USB0_RXCSRH3_R (*((volatile uint8_t *)0x40050137))
+#define USB0_RXCOUNT3_R (*((volatile uint16_t *)0x40050138))
+#define USB0_TXTYPE3_R (*((volatile uint8_t *)0x4005013A))
+#define USB0_TXINTERVAL3_R (*((volatile uint8_t *)0x4005013B))
+#define USB0_RXTYPE3_R (*((volatile uint8_t *)0x4005013C))
+#define USB0_RXINTERVAL3_R (*((volatile uint8_t *)0x4005013D))
+#define USB0_TXMAXP4_R (*((volatile uint16_t *)0x40050140))
+#define USB0_TXCSRL4_R (*((volatile uint8_t *)0x40050142))
+#define USB0_TXCSRH4_R (*((volatile uint8_t *)0x40050143))
+#define USB0_RXMAXP4_R (*((volatile uint16_t *)0x40050144))
+#define USB0_RXCSRL4_R (*((volatile uint8_t *)0x40050146))
+#define USB0_RXCSRH4_R (*((volatile uint8_t *)0x40050147))
+#define USB0_RXCOUNT4_R (*((volatile uint16_t *)0x40050148))
+#define USB0_TXTYPE4_R (*((volatile uint8_t *)0x4005014A))
+#define USB0_TXINTERVAL4_R (*((volatile uint8_t *)0x4005014B))
+#define USB0_RXTYPE4_R (*((volatile uint8_t *)0x4005014C))
+#define USB0_RXINTERVAL4_R (*((volatile uint8_t *)0x4005014D))
+#define USB0_TXMAXP5_R (*((volatile uint16_t *)0x40050150))
+#define USB0_TXCSRL5_R (*((volatile uint8_t *)0x40050152))
+#define USB0_TXCSRH5_R (*((volatile uint8_t *)0x40050153))
+#define USB0_RXMAXP5_R (*((volatile uint16_t *)0x40050154))
+#define USB0_RXCSRL5_R (*((volatile uint8_t *)0x40050156))
+#define USB0_RXCSRH5_R (*((volatile uint8_t *)0x40050157))
+#define USB0_RXCOUNT5_R (*((volatile uint16_t *)0x40050158))
+#define USB0_TXTYPE5_R (*((volatile uint8_t *)0x4005015A))
+#define USB0_TXINTERVAL5_R (*((volatile uint8_t *)0x4005015B))
+#define USB0_RXTYPE5_R (*((volatile uint8_t *)0x4005015C))
+#define USB0_RXINTERVAL5_R (*((volatile uint8_t *)0x4005015D))
+#define USB0_TXMAXP6_R (*((volatile uint16_t *)0x40050160))
+#define USB0_TXCSRL6_R (*((volatile uint8_t *)0x40050162))
+#define USB0_TXCSRH6_R (*((volatile uint8_t *)0x40050163))
+#define USB0_RXMAXP6_R (*((volatile uint16_t *)0x40050164))
+#define USB0_RXCSRL6_R (*((volatile uint8_t *)0x40050166))
+#define USB0_RXCSRH6_R (*((volatile uint8_t *)0x40050167))
+#define USB0_RXCOUNT6_R (*((volatile uint16_t *)0x40050168))
+#define USB0_TXTYPE6_R (*((volatile uint8_t *)0x4005016A))
+#define USB0_TXINTERVAL6_R (*((volatile uint8_t *)0x4005016B))
+#define USB0_RXTYPE6_R (*((volatile uint8_t *)0x4005016C))
+#define USB0_RXINTERVAL6_R (*((volatile uint8_t *)0x4005016D))
+#define USB0_TXMAXP7_R (*((volatile uint16_t *)0x40050170))
+#define USB0_TXCSRL7_R (*((volatile uint8_t *)0x40050172))
+#define USB0_TXCSRH7_R (*((volatile uint8_t *)0x40050173))
+#define USB0_RXMAXP7_R (*((volatile uint16_t *)0x40050174))
+#define USB0_RXCSRL7_R (*((volatile uint8_t *)0x40050176))
+#define USB0_RXCSRH7_R (*((volatile uint8_t *)0x40050177))
+#define USB0_RXCOUNT7_R (*((volatile uint16_t *)0x40050178))
+#define USB0_TXTYPE7_R (*((volatile uint8_t *)0x4005017A))
+#define USB0_TXINTERVAL7_R (*((volatile uint8_t *)0x4005017B))
+#define USB0_RXTYPE7_R (*((volatile uint8_t *)0x4005017C))
+#define USB0_RXINTERVAL7_R (*((volatile uint8_t *)0x4005017D))
+#define USB0_RQPKTCOUNT1_R (*((volatile uint16_t *)0x40050304))
+#define USB0_RQPKTCOUNT2_R (*((volatile uint16_t *)0x40050308))
+#define USB0_RQPKTCOUNT3_R (*((volatile uint16_t *)0x4005030C))
+#define USB0_RQPKTCOUNT4_R (*((volatile uint16_t *)0x40050310))
+#define USB0_RQPKTCOUNT5_R (*((volatile uint16_t *)0x40050314))
+#define USB0_RQPKTCOUNT6_R (*((volatile uint16_t *)0x40050318))
+#define USB0_RQPKTCOUNT7_R (*((volatile uint16_t *)0x4005031C))
+#define USB0_RXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050340))
+#define USB0_TXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050342))
+#define USB0_EPC_R (*((volatile uint32_t *)0x40050400))
+#define USB0_EPCRIS_R (*((volatile uint32_t *)0x40050404))
+#define USB0_EPCIM_R (*((volatile uint32_t *)0x40050408))
+#define USB0_EPCISC_R (*((volatile uint32_t *)0x4005040C))
+#define USB0_DRRIS_R (*((volatile uint32_t *)0x40050410))
+#define USB0_DRIM_R (*((volatile uint32_t *)0x40050414))
+#define USB0_DRISC_R (*((volatile uint32_t *)0x40050418))
+#define USB0_GPCS_R (*((volatile uint32_t *)0x4005041C))
+#define USB0_VDC_R (*((volatile uint32_t *)0x40050430))
+#define USB0_VDCRIS_R (*((volatile uint32_t *)0x40050434))
+#define USB0_VDCIM_R (*((volatile uint32_t *)0x40050438))
+#define USB0_VDCISC_R (*((volatile uint32_t *)0x4005043C))
+#define USB0_IDVRIS_R (*((volatile uint32_t *)0x40050444))
+#define USB0_IDVIM_R (*((volatile uint32_t *)0x40050448))
+#define USB0_IDVISC_R (*((volatile uint32_t *)0x4005044C))
+#define USB0_DMASEL_R (*((volatile uint32_t *)0x40050450))
+#define USB0_PP_R (*((volatile uint32_t *)0x40050FC0))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTA AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTA_AHB_DATA_BITS_R \
+ ((volatile uint32_t *)0x40058000)
+#define GPIO_PORTA_AHB_DATA_R (*((volatile uint32_t *)0x400583FC))
+#define GPIO_PORTA_AHB_DIR_R (*((volatile uint32_t *)0x40058400))
+#define GPIO_PORTA_AHB_IS_R (*((volatile uint32_t *)0x40058404))
+#define GPIO_PORTA_AHB_IBE_R (*((volatile uint32_t *)0x40058408))
+#define GPIO_PORTA_AHB_IEV_R (*((volatile uint32_t *)0x4005840C))
+#define GPIO_PORTA_AHB_IM_R (*((volatile uint32_t *)0x40058410))
+#define GPIO_PORTA_AHB_RIS_R (*((volatile uint32_t *)0x40058414))
+#define GPIO_PORTA_AHB_MIS_R (*((volatile uint32_t *)0x40058418))
+#define GPIO_PORTA_AHB_ICR_R (*((volatile uint32_t *)0x4005841C))
+#define GPIO_PORTA_AHB_AFSEL_R (*((volatile uint32_t *)0x40058420))
+#define GPIO_PORTA_AHB_DR2R_R (*((volatile uint32_t *)0x40058500))
+#define GPIO_PORTA_AHB_DR4R_R (*((volatile uint32_t *)0x40058504))
+#define GPIO_PORTA_AHB_DR8R_R (*((volatile uint32_t *)0x40058508))
+#define GPIO_PORTA_AHB_ODR_R (*((volatile uint32_t *)0x4005850C))
+#define GPIO_PORTA_AHB_PUR_R (*((volatile uint32_t *)0x40058510))
+#define GPIO_PORTA_AHB_PDR_R (*((volatile uint32_t *)0x40058514))
+#define GPIO_PORTA_AHB_SLR_R (*((volatile uint32_t *)0x40058518))
+#define GPIO_PORTA_AHB_DEN_R (*((volatile uint32_t *)0x4005851C))
+#define GPIO_PORTA_AHB_LOCK_R (*((volatile uint32_t *)0x40058520))
+#define GPIO_PORTA_AHB_CR_R (*((volatile uint32_t *)0x40058524))
+#define GPIO_PORTA_AHB_AMSEL_R (*((volatile uint32_t *)0x40058528))
+#define GPIO_PORTA_AHB_PCTL_R (*((volatile uint32_t *)0x4005852C))
+#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile uint32_t *)0x40058530))
+#define GPIO_PORTA_AHB_DMACTL_R (*((volatile uint32_t *)0x40058534))
+#define GPIO_PORTA_AHB_SI_R (*((volatile uint32_t *)0x40058538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTB AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_AHB_DATA_BITS_R \
+ ((volatile uint32_t *)0x40059000)
+#define GPIO_PORTB_AHB_DATA_R (*((volatile uint32_t *)0x400593FC))
+#define GPIO_PORTB_AHB_DIR_R (*((volatile uint32_t *)0x40059400))
+#define GPIO_PORTB_AHB_IS_R (*((volatile uint32_t *)0x40059404))
+#define GPIO_PORTB_AHB_IBE_R (*((volatile uint32_t *)0x40059408))
+#define GPIO_PORTB_AHB_IEV_R (*((volatile uint32_t *)0x4005940C))
+#define GPIO_PORTB_AHB_IM_R (*((volatile uint32_t *)0x40059410))
+#define GPIO_PORTB_AHB_RIS_R (*((volatile uint32_t *)0x40059414))
+#define GPIO_PORTB_AHB_MIS_R (*((volatile uint32_t *)0x40059418))
+#define GPIO_PORTB_AHB_ICR_R (*((volatile uint32_t *)0x4005941C))
+#define GPIO_PORTB_AHB_AFSEL_R (*((volatile uint32_t *)0x40059420))
+#define GPIO_PORTB_AHB_DR2R_R (*((volatile uint32_t *)0x40059500))
+#define GPIO_PORTB_AHB_DR4R_R (*((volatile uint32_t *)0x40059504))
+#define GPIO_PORTB_AHB_DR8R_R (*((volatile uint32_t *)0x40059508))
+#define GPIO_PORTB_AHB_ODR_R (*((volatile uint32_t *)0x4005950C))
+#define GPIO_PORTB_AHB_PUR_R (*((volatile uint32_t *)0x40059510))
+#define GPIO_PORTB_AHB_PDR_R (*((volatile uint32_t *)0x40059514))
+#define GPIO_PORTB_AHB_SLR_R (*((volatile uint32_t *)0x40059518))
+#define GPIO_PORTB_AHB_DEN_R (*((volatile uint32_t *)0x4005951C))
+#define GPIO_PORTB_AHB_LOCK_R (*((volatile uint32_t *)0x40059520))
+#define GPIO_PORTB_AHB_CR_R (*((volatile uint32_t *)0x40059524))
+#define GPIO_PORTB_AHB_AMSEL_R (*((volatile uint32_t *)0x40059528))
+#define GPIO_PORTB_AHB_PCTL_R (*((volatile uint32_t *)0x4005952C))
+#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile uint32_t *)0x40059530))
+#define GPIO_PORTB_AHB_DMACTL_R (*((volatile uint32_t *)0x40059534))
+#define GPIO_PORTB_AHB_SI_R (*((volatile uint32_t *)0x40059538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTC AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTC_AHB_DATA_BITS_R \
+ ((volatile uint32_t *)0x4005A000)
+#define GPIO_PORTC_AHB_DATA_R (*((volatile uint32_t *)0x4005A3FC))
+#define GPIO_PORTC_AHB_DIR_R (*((volatile uint32_t *)0x4005A400))
+#define GPIO_PORTC_AHB_IS_R (*((volatile uint32_t *)0x4005A404))
+#define GPIO_PORTC_AHB_IBE_R (*((volatile uint32_t *)0x4005A408))
+#define GPIO_PORTC_AHB_IEV_R (*((volatile uint32_t *)0x4005A40C))
+#define GPIO_PORTC_AHB_IM_R (*((volatile uint32_t *)0x4005A410))
+#define GPIO_PORTC_AHB_RIS_R (*((volatile uint32_t *)0x4005A414))
+#define GPIO_PORTC_AHB_MIS_R (*((volatile uint32_t *)0x4005A418))
+#define GPIO_PORTC_AHB_ICR_R (*((volatile uint32_t *)0x4005A41C))
+#define GPIO_PORTC_AHB_AFSEL_R (*((volatile uint32_t *)0x4005A420))
+#define GPIO_PORTC_AHB_DR2R_R (*((volatile uint32_t *)0x4005A500))
+#define GPIO_PORTC_AHB_DR4R_R (*((volatile uint32_t *)0x4005A504))
+#define GPIO_PORTC_AHB_DR8R_R (*((volatile uint32_t *)0x4005A508))
+#define GPIO_PORTC_AHB_ODR_R (*((volatile uint32_t *)0x4005A50C))
+#define GPIO_PORTC_AHB_PUR_R (*((volatile uint32_t *)0x4005A510))
+#define GPIO_PORTC_AHB_PDR_R (*((volatile uint32_t *)0x4005A514))
+#define GPIO_PORTC_AHB_SLR_R (*((volatile uint32_t *)0x4005A518))
+#define GPIO_PORTC_AHB_DEN_R (*((volatile uint32_t *)0x4005A51C))
+#define GPIO_PORTC_AHB_LOCK_R (*((volatile uint32_t *)0x4005A520))
+#define GPIO_PORTC_AHB_CR_R (*((volatile uint32_t *)0x4005A524))
+#define GPIO_PORTC_AHB_AMSEL_R (*((volatile uint32_t *)0x4005A528))
+#define GPIO_PORTC_AHB_PCTL_R (*((volatile uint32_t *)0x4005A52C))
+#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005A530))
+#define GPIO_PORTC_AHB_DMACTL_R (*((volatile uint32_t *)0x4005A534))
+#define GPIO_PORTC_AHB_SI_R (*((volatile uint32_t *)0x4005A538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTD AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTD_AHB_DATA_BITS_R \
+ ((volatile uint32_t *)0x4005B000)
+#define GPIO_PORTD_AHB_DATA_R (*((volatile uint32_t *)0x4005B3FC))
+#define GPIO_PORTD_AHB_DIR_R (*((volatile uint32_t *)0x4005B400))
+#define GPIO_PORTD_AHB_IS_R (*((volatile uint32_t *)0x4005B404))
+#define GPIO_PORTD_AHB_IBE_R (*((volatile uint32_t *)0x4005B408))
+#define GPIO_PORTD_AHB_IEV_R (*((volatile uint32_t *)0x4005B40C))
+#define GPIO_PORTD_AHB_IM_R (*((volatile uint32_t *)0x4005B410))
+#define GPIO_PORTD_AHB_RIS_R (*((volatile uint32_t *)0x4005B414))
+#define GPIO_PORTD_AHB_MIS_R (*((volatile uint32_t *)0x4005B418))
+#define GPIO_PORTD_AHB_ICR_R (*((volatile uint32_t *)0x4005B41C))
+#define GPIO_PORTD_AHB_AFSEL_R (*((volatile uint32_t *)0x4005B420))
+#define GPIO_PORTD_AHB_DR2R_R (*((volatile uint32_t *)0x4005B500))
+#define GPIO_PORTD_AHB_DR4R_R (*((volatile uint32_t *)0x4005B504))
+#define GPIO_PORTD_AHB_DR8R_R (*((volatile uint32_t *)0x4005B508))
+#define GPIO_PORTD_AHB_ODR_R (*((volatile uint32_t *)0x4005B50C))
+#define GPIO_PORTD_AHB_PUR_R (*((volatile uint32_t *)0x4005B510))
+#define GPIO_PORTD_AHB_PDR_R (*((volatile uint32_t *)0x4005B514))
+#define GPIO_PORTD_AHB_SLR_R (*((volatile uint32_t *)0x4005B518))
+#define GPIO_PORTD_AHB_DEN_R (*((volatile uint32_t *)0x4005B51C))
+#define GPIO_PORTD_AHB_LOCK_R (*((volatile uint32_t *)0x4005B520))
+#define GPIO_PORTD_AHB_CR_R (*((volatile uint32_t *)0x4005B524))
+#define GPIO_PORTD_AHB_AMSEL_R (*((volatile uint32_t *)0x4005B528))
+#define GPIO_PORTD_AHB_PCTL_R (*((volatile uint32_t *)0x4005B52C))
+#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005B530))
+#define GPIO_PORTD_AHB_DMACTL_R (*((volatile uint32_t *)0x4005B534))
+#define GPIO_PORTD_AHB_SI_R (*((volatile uint32_t *)0x4005B538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTE AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTE_AHB_DATA_BITS_R \
+ ((volatile uint32_t *)0x4005C000)
+#define GPIO_PORTE_AHB_DATA_R (*((volatile uint32_t *)0x4005C3FC))
+#define GPIO_PORTE_AHB_DIR_R (*((volatile uint32_t *)0x4005C400))
+#define GPIO_PORTE_AHB_IS_R (*((volatile uint32_t *)0x4005C404))
+#define GPIO_PORTE_AHB_IBE_R (*((volatile uint32_t *)0x4005C408))
+#define GPIO_PORTE_AHB_IEV_R (*((volatile uint32_t *)0x4005C40C))
+#define GPIO_PORTE_AHB_IM_R (*((volatile uint32_t *)0x4005C410))
+#define GPIO_PORTE_AHB_RIS_R (*((volatile uint32_t *)0x4005C414))
+#define GPIO_PORTE_AHB_MIS_R (*((volatile uint32_t *)0x4005C418))
+#define GPIO_PORTE_AHB_ICR_R (*((volatile uint32_t *)0x4005C41C))
+#define GPIO_PORTE_AHB_AFSEL_R (*((volatile uint32_t *)0x4005C420))
+#define GPIO_PORTE_AHB_DR2R_R (*((volatile uint32_t *)0x4005C500))
+#define GPIO_PORTE_AHB_DR4R_R (*((volatile uint32_t *)0x4005C504))
+#define GPIO_PORTE_AHB_DR8R_R (*((volatile uint32_t *)0x4005C508))
+#define GPIO_PORTE_AHB_ODR_R (*((volatile uint32_t *)0x4005C50C))
+#define GPIO_PORTE_AHB_PUR_R (*((volatile uint32_t *)0x4005C510))
+#define GPIO_PORTE_AHB_PDR_R (*((volatile uint32_t *)0x4005C514))
+#define GPIO_PORTE_AHB_SLR_R (*((volatile uint32_t *)0x4005C518))
+#define GPIO_PORTE_AHB_DEN_R (*((volatile uint32_t *)0x4005C51C))
+#define GPIO_PORTE_AHB_LOCK_R (*((volatile uint32_t *)0x4005C520))
+#define GPIO_PORTE_AHB_CR_R (*((volatile uint32_t *)0x4005C524))
+#define GPIO_PORTE_AHB_AMSEL_R (*((volatile uint32_t *)0x4005C528))
+#define GPIO_PORTE_AHB_PCTL_R (*((volatile uint32_t *)0x4005C52C))
+#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005C530))
+#define GPIO_PORTE_AHB_DMACTL_R (*((volatile uint32_t *)0x4005C534))
+#define GPIO_PORTE_AHB_SI_R (*((volatile uint32_t *)0x4005C538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTF AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTF_AHB_DATA_BITS_R \
+ ((volatile uint32_t *)0x4005D000)
+#define GPIO_PORTF_AHB_DATA_R (*((volatile uint32_t *)0x4005D3FC))
+#define GPIO_PORTF_AHB_DIR_R (*((volatile uint32_t *)0x4005D400))
+#define GPIO_PORTF_AHB_IS_R (*((volatile uint32_t *)0x4005D404))
+#define GPIO_PORTF_AHB_IBE_R (*((volatile uint32_t *)0x4005D408))
+#define GPIO_PORTF_AHB_IEV_R (*((volatile uint32_t *)0x4005D40C))
+#define GPIO_PORTF_AHB_IM_R (*((volatile uint32_t *)0x4005D410))
+#define GPIO_PORTF_AHB_RIS_R (*((volatile uint32_t *)0x4005D414))
+#define GPIO_PORTF_AHB_MIS_R (*((volatile uint32_t *)0x4005D418))
+#define GPIO_PORTF_AHB_ICR_R (*((volatile uint32_t *)0x4005D41C))
+#define GPIO_PORTF_AHB_AFSEL_R (*((volatile uint32_t *)0x4005D420))
+#define GPIO_PORTF_AHB_DR2R_R (*((volatile uint32_t *)0x4005D500))
+#define GPIO_PORTF_AHB_DR4R_R (*((volatile uint32_t *)0x4005D504))
+#define GPIO_PORTF_AHB_DR8R_R (*((volatile uint32_t *)0x4005D508))
+#define GPIO_PORTF_AHB_ODR_R (*((volatile uint32_t *)0x4005D50C))
+#define GPIO_PORTF_AHB_PUR_R (*((volatile uint32_t *)0x4005D510))
+#define GPIO_PORTF_AHB_PDR_R (*((volatile uint32_t *)0x4005D514))
+#define GPIO_PORTF_AHB_SLR_R (*((volatile uint32_t *)0x4005D518))
+#define GPIO_PORTF_AHB_DEN_R (*((volatile uint32_t *)0x4005D51C))
+#define GPIO_PORTF_AHB_LOCK_R (*((volatile uint32_t *)0x4005D520))
+#define GPIO_PORTF_AHB_CR_R (*((volatile uint32_t *)0x4005D524))
+#define GPIO_PORTF_AHB_AMSEL_R (*((volatile uint32_t *)0x4005D528))
+#define GPIO_PORTF_AHB_PCTL_R (*((volatile uint32_t *)0x4005D52C))
+#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005D530))
+#define GPIO_PORTF_AHB_DMACTL_R (*((volatile uint32_t *)0x4005D534))
+#define GPIO_PORTF_AHB_SI_R (*((volatile uint32_t *)0x4005D538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTG AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTG_AHB_DATA_BITS_R \
+ ((volatile uint32_t *)0x4005E000)
+#define GPIO_PORTG_AHB_DATA_R (*((volatile uint32_t *)0x4005E3FC))
+#define GPIO_PORTG_AHB_DIR_R (*((volatile uint32_t *)0x4005E400))
+#define GPIO_PORTG_AHB_IS_R (*((volatile uint32_t *)0x4005E404))
+#define GPIO_PORTG_AHB_IBE_R (*((volatile uint32_t *)0x4005E408))
+#define GPIO_PORTG_AHB_IEV_R (*((volatile uint32_t *)0x4005E40C))
+#define GPIO_PORTG_AHB_IM_R (*((volatile uint32_t *)0x4005E410))
+#define GPIO_PORTG_AHB_RIS_R (*((volatile uint32_t *)0x4005E414))
+#define GPIO_PORTG_AHB_MIS_R (*((volatile uint32_t *)0x4005E418))
+#define GPIO_PORTG_AHB_ICR_R (*((volatile uint32_t *)0x4005E41C))
+#define GPIO_PORTG_AHB_AFSEL_R (*((volatile uint32_t *)0x4005E420))
+#define GPIO_PORTG_AHB_DR2R_R (*((volatile uint32_t *)0x4005E500))
+#define GPIO_PORTG_AHB_DR4R_R (*((volatile uint32_t *)0x4005E504))
+#define GPIO_PORTG_AHB_DR8R_R (*((volatile uint32_t *)0x4005E508))
+#define GPIO_PORTG_AHB_ODR_R (*((volatile uint32_t *)0x4005E50C))
+#define GPIO_PORTG_AHB_PUR_R (*((volatile uint32_t *)0x4005E510))
+#define GPIO_PORTG_AHB_PDR_R (*((volatile uint32_t *)0x4005E514))
+#define GPIO_PORTG_AHB_SLR_R (*((volatile uint32_t *)0x4005E518))
+#define GPIO_PORTG_AHB_DEN_R (*((volatile uint32_t *)0x4005E51C))
+#define GPIO_PORTG_AHB_LOCK_R (*((volatile uint32_t *)0x4005E520))
+#define GPIO_PORTG_AHB_CR_R (*((volatile uint32_t *)0x4005E524))
+#define GPIO_PORTG_AHB_AMSEL_R (*((volatile uint32_t *)0x4005E528))
+#define GPIO_PORTG_AHB_PCTL_R (*((volatile uint32_t *)0x4005E52C))
+#define GPIO_PORTG_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005E530))
+#define GPIO_PORTG_AHB_DMACTL_R (*((volatile uint32_t *)0x4005E534))
+#define GPIO_PORTG_AHB_SI_R (*((volatile uint32_t *)0x4005E538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTH AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTH_AHB_DATA_BITS_R \
+ ((volatile uint32_t *)0x4005F000)
+#define GPIO_PORTH_AHB_DATA_R (*((volatile uint32_t *)0x4005F3FC))
+#define GPIO_PORTH_AHB_DIR_R (*((volatile uint32_t *)0x4005F400))
+#define GPIO_PORTH_AHB_IS_R (*((volatile uint32_t *)0x4005F404))
+#define GPIO_PORTH_AHB_IBE_R (*((volatile uint32_t *)0x4005F408))
+#define GPIO_PORTH_AHB_IEV_R (*((volatile uint32_t *)0x4005F40C))
+#define GPIO_PORTH_AHB_IM_R (*((volatile uint32_t *)0x4005F410))
+#define GPIO_PORTH_AHB_RIS_R (*((volatile uint32_t *)0x4005F414))
+#define GPIO_PORTH_AHB_MIS_R (*((volatile uint32_t *)0x4005F418))
+#define GPIO_PORTH_AHB_ICR_R (*((volatile uint32_t *)0x4005F41C))
+#define GPIO_PORTH_AHB_AFSEL_R (*((volatile uint32_t *)0x4005F420))
+#define GPIO_PORTH_AHB_DR2R_R (*((volatile uint32_t *)0x4005F500))
+#define GPIO_PORTH_AHB_DR4R_R (*((volatile uint32_t *)0x4005F504))
+#define GPIO_PORTH_AHB_DR8R_R (*((volatile uint32_t *)0x4005F508))
+#define GPIO_PORTH_AHB_ODR_R (*((volatile uint32_t *)0x4005F50C))
+#define GPIO_PORTH_AHB_PUR_R (*((volatile uint32_t *)0x4005F510))
+#define GPIO_PORTH_AHB_PDR_R (*((volatile uint32_t *)0x4005F514))
+#define GPIO_PORTH_AHB_SLR_R (*((volatile uint32_t *)0x4005F518))
+#define GPIO_PORTH_AHB_DEN_R (*((volatile uint32_t *)0x4005F51C))
+#define GPIO_PORTH_AHB_LOCK_R (*((volatile uint32_t *)0x4005F520))
+#define GPIO_PORTH_AHB_CR_R (*((volatile uint32_t *)0x4005F524))
+#define GPIO_PORTH_AHB_AMSEL_R (*((volatile uint32_t *)0x4005F528))
+#define GPIO_PORTH_AHB_PCTL_R (*((volatile uint32_t *)0x4005F52C))
+#define GPIO_PORTH_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005F530))
+#define GPIO_PORTH_AHB_DMACTL_R (*((volatile uint32_t *)0x4005F534))
+#define GPIO_PORTH_AHB_SI_R (*((volatile uint32_t *)0x4005F538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTJ AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTJ_AHB_DATA_BITS_R \
+ ((volatile uint32_t *)0x40060000)
+#define GPIO_PORTJ_AHB_DATA_R (*((volatile uint32_t *)0x400603FC))
+#define GPIO_PORTJ_AHB_DIR_R (*((volatile uint32_t *)0x40060400))
+#define GPIO_PORTJ_AHB_IS_R (*((volatile uint32_t *)0x40060404))
+#define GPIO_PORTJ_AHB_IBE_R (*((volatile uint32_t *)0x40060408))
+#define GPIO_PORTJ_AHB_IEV_R (*((volatile uint32_t *)0x4006040C))
+#define GPIO_PORTJ_AHB_IM_R (*((volatile uint32_t *)0x40060410))
+#define GPIO_PORTJ_AHB_RIS_R (*((volatile uint32_t *)0x40060414))
+#define GPIO_PORTJ_AHB_MIS_R (*((volatile uint32_t *)0x40060418))
+#define GPIO_PORTJ_AHB_ICR_R (*((volatile uint32_t *)0x4006041C))
+#define GPIO_PORTJ_AHB_AFSEL_R (*((volatile uint32_t *)0x40060420))
+#define GPIO_PORTJ_AHB_DR2R_R (*((volatile uint32_t *)0x40060500))
+#define GPIO_PORTJ_AHB_DR4R_R (*((volatile uint32_t *)0x40060504))
+#define GPIO_PORTJ_AHB_DR8R_R (*((volatile uint32_t *)0x40060508))
+#define GPIO_PORTJ_AHB_ODR_R (*((volatile uint32_t *)0x4006050C))
+#define GPIO_PORTJ_AHB_PUR_R (*((volatile uint32_t *)0x40060510))
+#define GPIO_PORTJ_AHB_PDR_R (*((volatile uint32_t *)0x40060514))
+#define GPIO_PORTJ_AHB_SLR_R (*((volatile uint32_t *)0x40060518))
+#define GPIO_PORTJ_AHB_DEN_R (*((volatile uint32_t *)0x4006051C))
+#define GPIO_PORTJ_AHB_LOCK_R (*((volatile uint32_t *)0x40060520))
+#define GPIO_PORTJ_AHB_CR_R (*((volatile uint32_t *)0x40060524))
+#define GPIO_PORTJ_AHB_AMSEL_R (*((volatile uint32_t *)0x40060528))
+#define GPIO_PORTJ_AHB_PCTL_R (*((volatile uint32_t *)0x4006052C))
+#define GPIO_PORTJ_AHB_ADCCTL_R (*((volatile uint32_t *)0x40060530))
+#define GPIO_PORTJ_AHB_DMACTL_R (*((volatile uint32_t *)0x40060534))
+#define GPIO_PORTJ_AHB_SI_R (*((volatile uint32_t *)0x40060538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTK)
+//
+//*****************************************************************************
+#define GPIO_PORTK_DATA_BITS_R ((volatile uint32_t *)0x40061000)
+#define GPIO_PORTK_DATA_R (*((volatile uint32_t *)0x400613FC))
+#define GPIO_PORTK_DIR_R (*((volatile uint32_t *)0x40061400))
+#define GPIO_PORTK_IS_R (*((volatile uint32_t *)0x40061404))
+#define GPIO_PORTK_IBE_R (*((volatile uint32_t *)0x40061408))
+#define GPIO_PORTK_IEV_R (*((volatile uint32_t *)0x4006140C))
+#define GPIO_PORTK_IM_R (*((volatile uint32_t *)0x40061410))
+#define GPIO_PORTK_RIS_R (*((volatile uint32_t *)0x40061414))
+#define GPIO_PORTK_MIS_R (*((volatile uint32_t *)0x40061418))
+#define GPIO_PORTK_ICR_R (*((volatile uint32_t *)0x4006141C))
+#define GPIO_PORTK_AFSEL_R (*((volatile uint32_t *)0x40061420))
+#define GPIO_PORTK_DR2R_R (*((volatile uint32_t *)0x40061500))
+#define GPIO_PORTK_DR4R_R (*((volatile uint32_t *)0x40061504))
+#define GPIO_PORTK_DR8R_R (*((volatile uint32_t *)0x40061508))
+#define GPIO_PORTK_ODR_R (*((volatile uint32_t *)0x4006150C))
+#define GPIO_PORTK_PUR_R (*((volatile uint32_t *)0x40061510))
+#define GPIO_PORTK_PDR_R (*((volatile uint32_t *)0x40061514))
+#define GPIO_PORTK_SLR_R (*((volatile uint32_t *)0x40061518))
+#define GPIO_PORTK_DEN_R (*((volatile uint32_t *)0x4006151C))
+#define GPIO_PORTK_LOCK_R (*((volatile uint32_t *)0x40061520))
+#define GPIO_PORTK_CR_R (*((volatile uint32_t *)0x40061524))
+#define GPIO_PORTK_AMSEL_R (*((volatile uint32_t *)0x40061528))
+#define GPIO_PORTK_PCTL_R (*((volatile uint32_t *)0x4006152C))
+#define GPIO_PORTK_ADCCTL_R (*((volatile uint32_t *)0x40061530))
+#define GPIO_PORTK_DMACTL_R (*((volatile uint32_t *)0x40061534))
+#define GPIO_PORTK_SI_R (*((volatile uint32_t *)0x40061538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTL)
+//
+//*****************************************************************************
+#define GPIO_PORTL_DATA_BITS_R ((volatile uint32_t *)0x40062000)
+#define GPIO_PORTL_DATA_R (*((volatile uint32_t *)0x400623FC))
+#define GPIO_PORTL_DIR_R (*((volatile uint32_t *)0x40062400))
+#define GPIO_PORTL_IS_R (*((volatile uint32_t *)0x40062404))
+#define GPIO_PORTL_IBE_R (*((volatile uint32_t *)0x40062408))
+#define GPIO_PORTL_IEV_R (*((volatile uint32_t *)0x4006240C))
+#define GPIO_PORTL_IM_R (*((volatile uint32_t *)0x40062410))
+#define GPIO_PORTL_RIS_R (*((volatile uint32_t *)0x40062414))
+#define GPIO_PORTL_MIS_R (*((volatile uint32_t *)0x40062418))
+#define GPIO_PORTL_ICR_R (*((volatile uint32_t *)0x4006241C))
+#define GPIO_PORTL_AFSEL_R (*((volatile uint32_t *)0x40062420))
+#define GPIO_PORTL_DR2R_R (*((volatile uint32_t *)0x40062500))
+#define GPIO_PORTL_DR4R_R (*((volatile uint32_t *)0x40062504))
+#define GPIO_PORTL_DR8R_R (*((volatile uint32_t *)0x40062508))
+#define GPIO_PORTL_ODR_R (*((volatile uint32_t *)0x4006250C))
+#define GPIO_PORTL_PUR_R (*((volatile uint32_t *)0x40062510))
+#define GPIO_PORTL_PDR_R (*((volatile uint32_t *)0x40062514))
+#define GPIO_PORTL_SLR_R (*((volatile uint32_t *)0x40062518))
+#define GPIO_PORTL_DEN_R (*((volatile uint32_t *)0x4006251C))
+#define GPIO_PORTL_LOCK_R (*((volatile uint32_t *)0x40062520))
+#define GPIO_PORTL_CR_R (*((volatile uint32_t *)0x40062524))
+#define GPIO_PORTL_AMSEL_R (*((volatile uint32_t *)0x40062528))
+#define GPIO_PORTL_PCTL_R (*((volatile uint32_t *)0x4006252C))
+#define GPIO_PORTL_ADCCTL_R (*((volatile uint32_t *)0x40062530))
+#define GPIO_PORTL_DMACTL_R (*((volatile uint32_t *)0x40062534))
+#define GPIO_PORTL_SI_R (*((volatile uint32_t *)0x40062538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTM)
+//
+//*****************************************************************************
+#define GPIO_PORTM_DATA_BITS_R ((volatile uint32_t *)0x40063000)
+#define GPIO_PORTM_DATA_R (*((volatile uint32_t *)0x400633FC))
+#define GPIO_PORTM_DIR_R (*((volatile uint32_t *)0x40063400))
+#define GPIO_PORTM_IS_R (*((volatile uint32_t *)0x40063404))
+#define GPIO_PORTM_IBE_R (*((volatile uint32_t *)0x40063408))
+#define GPIO_PORTM_IEV_R (*((volatile uint32_t *)0x4006340C))
+#define GPIO_PORTM_IM_R (*((volatile uint32_t *)0x40063410))
+#define GPIO_PORTM_RIS_R (*((volatile uint32_t *)0x40063414))
+#define GPIO_PORTM_MIS_R (*((volatile uint32_t *)0x40063418))
+#define GPIO_PORTM_ICR_R (*((volatile uint32_t *)0x4006341C))
+#define GPIO_PORTM_AFSEL_R (*((volatile uint32_t *)0x40063420))
+#define GPIO_PORTM_DR2R_R (*((volatile uint32_t *)0x40063500))
+#define GPIO_PORTM_DR4R_R (*((volatile uint32_t *)0x40063504))
+#define GPIO_PORTM_DR8R_R (*((volatile uint32_t *)0x40063508))
+#define GPIO_PORTM_ODR_R (*((volatile uint32_t *)0x4006350C))
+#define GPIO_PORTM_PUR_R (*((volatile uint32_t *)0x40063510))
+#define GPIO_PORTM_PDR_R (*((volatile uint32_t *)0x40063514))
+#define GPIO_PORTM_SLR_R (*((volatile uint32_t *)0x40063518))
+#define GPIO_PORTM_DEN_R (*((volatile uint32_t *)0x4006351C))
+#define GPIO_PORTM_LOCK_R (*((volatile uint32_t *)0x40063520))
+#define GPIO_PORTM_CR_R (*((volatile uint32_t *)0x40063524))
+#define GPIO_PORTM_AMSEL_R (*((volatile uint32_t *)0x40063528))
+#define GPIO_PORTM_PCTL_R (*((volatile uint32_t *)0x4006352C))
+#define GPIO_PORTM_ADCCTL_R (*((volatile uint32_t *)0x40063530))
+#define GPIO_PORTM_DMACTL_R (*((volatile uint32_t *)0x40063534))
+#define GPIO_PORTM_SI_R (*((volatile uint32_t *)0x40063538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTN)
+//
+//*****************************************************************************
+#define GPIO_PORTN_DATA_BITS_R ((volatile uint32_t *)0x40064000)
+#define GPIO_PORTN_DATA_R (*((volatile uint32_t *)0x400643FC))
+#define GPIO_PORTN_DIR_R (*((volatile uint32_t *)0x40064400))
+#define GPIO_PORTN_IS_R (*((volatile uint32_t *)0x40064404))
+#define GPIO_PORTN_IBE_R (*((volatile uint32_t *)0x40064408))
+#define GPIO_PORTN_IEV_R (*((volatile uint32_t *)0x4006440C))
+#define GPIO_PORTN_IM_R (*((volatile uint32_t *)0x40064410))
+#define GPIO_PORTN_RIS_R (*((volatile uint32_t *)0x40064414))
+#define GPIO_PORTN_MIS_R (*((volatile uint32_t *)0x40064418))
+#define GPIO_PORTN_ICR_R (*((volatile uint32_t *)0x4006441C))
+#define GPIO_PORTN_AFSEL_R (*((volatile uint32_t *)0x40064420))
+#define GPIO_PORTN_DR2R_R (*((volatile uint32_t *)0x40064500))
+#define GPIO_PORTN_DR4R_R (*((volatile uint32_t *)0x40064504))
+#define GPIO_PORTN_DR8R_R (*((volatile uint32_t *)0x40064508))
+#define GPIO_PORTN_ODR_R (*((volatile uint32_t *)0x4006450C))
+#define GPIO_PORTN_PUR_R (*((volatile uint32_t *)0x40064510))
+#define GPIO_PORTN_PDR_R (*((volatile uint32_t *)0x40064514))
+#define GPIO_PORTN_SLR_R (*((volatile uint32_t *)0x40064518))
+#define GPIO_PORTN_DEN_R (*((volatile uint32_t *)0x4006451C))
+#define GPIO_PORTN_LOCK_R (*((volatile uint32_t *)0x40064520))
+#define GPIO_PORTN_CR_R (*((volatile uint32_t *)0x40064524))
+#define GPIO_PORTN_AMSEL_R (*((volatile uint32_t *)0x40064528))
+#define GPIO_PORTN_PCTL_R (*((volatile uint32_t *)0x4006452C))
+#define GPIO_PORTN_ADCCTL_R (*((volatile uint32_t *)0x40064530))
+#define GPIO_PORTN_DMACTL_R (*((volatile uint32_t *)0x40064534))
+#define GPIO_PORTN_SI_R (*((volatile uint32_t *)0x40064538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTP)
+//
+//*****************************************************************************
+#define GPIO_PORTP_DATA_BITS_R ((volatile uint32_t *)0x40065000)
+#define GPIO_PORTP_DATA_R (*((volatile uint32_t *)0x400653FC))
+#define GPIO_PORTP_DIR_R (*((volatile uint32_t *)0x40065400))
+#define GPIO_PORTP_IS_R (*((volatile uint32_t *)0x40065404))
+#define GPIO_PORTP_IBE_R (*((volatile uint32_t *)0x40065408))
+#define GPIO_PORTP_IEV_R (*((volatile uint32_t *)0x4006540C))
+#define GPIO_PORTP_IM_R (*((volatile uint32_t *)0x40065410))
+#define GPIO_PORTP_RIS_R (*((volatile uint32_t *)0x40065414))
+#define GPIO_PORTP_MIS_R (*((volatile uint32_t *)0x40065418))
+#define GPIO_PORTP_ICR_R (*((volatile uint32_t *)0x4006541C))
+#define GPIO_PORTP_AFSEL_R (*((volatile uint32_t *)0x40065420))
+#define GPIO_PORTP_DR2R_R (*((volatile uint32_t *)0x40065500))
+#define GPIO_PORTP_DR4R_R (*((volatile uint32_t *)0x40065504))
+#define GPIO_PORTP_DR8R_R (*((volatile uint32_t *)0x40065508))
+#define GPIO_PORTP_ODR_R (*((volatile uint32_t *)0x4006550C))
+#define GPIO_PORTP_PUR_R (*((volatile uint32_t *)0x40065510))
+#define GPIO_PORTP_PDR_R (*((volatile uint32_t *)0x40065514))
+#define GPIO_PORTP_SLR_R (*((volatile uint32_t *)0x40065518))
+#define GPIO_PORTP_DEN_R (*((volatile uint32_t *)0x4006551C))
+#define GPIO_PORTP_LOCK_R (*((volatile uint32_t *)0x40065520))
+#define GPIO_PORTP_CR_R (*((volatile uint32_t *)0x40065524))
+#define GPIO_PORTP_AMSEL_R (*((volatile uint32_t *)0x40065528))
+#define GPIO_PORTP_PCTL_R (*((volatile uint32_t *)0x4006552C))
+#define GPIO_PORTP_ADCCTL_R (*((volatile uint32_t *)0x40065530))
+#define GPIO_PORTP_DMACTL_R (*((volatile uint32_t *)0x40065534))
+#define GPIO_PORTP_SI_R (*((volatile uint32_t *)0x40065538))
+
+//*****************************************************************************
+//
+// EEPROM registers (EEPROM)
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_R (*((volatile uint32_t *)0x400AF000))
+#define EEPROM_EEBLOCK_R (*((volatile uint32_t *)0x400AF004))
+#define EEPROM_EEOFFSET_R (*((volatile uint32_t *)0x400AF008))
+#define EEPROM_EERDWR_R (*((volatile uint32_t *)0x400AF010))
+#define EEPROM_EERDWRINC_R (*((volatile uint32_t *)0x400AF014))
+#define EEPROM_EEDONE_R (*((volatile uint32_t *)0x400AF018))
+#define EEPROM_EESUPP_R (*((volatile uint32_t *)0x400AF01C))
+#define EEPROM_EEUNLOCK_R (*((volatile uint32_t *)0x400AF020))
+#define EEPROM_EEPROT_R (*((volatile uint32_t *)0x400AF030))
+#define EEPROM_EEPASS0_R (*((volatile uint32_t *)0x400AF034))
+#define EEPROM_EEPASS1_R (*((volatile uint32_t *)0x400AF038))
+#define EEPROM_EEPASS2_R (*((volatile uint32_t *)0x400AF03C))
+#define EEPROM_EEINT_R (*((volatile uint32_t *)0x400AF040))
+#define EEPROM_EEHIDE_R (*((volatile uint32_t *)0x400AF050))
+#define EEPROM_EEDBGME_R (*((volatile uint32_t *)0x400AF080))
+#define EEPROM_PP_R (*((volatile uint32_t *)0x400AFFC0))
+
+//*****************************************************************************
+//
+// I2C registers (I2C4)
+//
+//*****************************************************************************
+#define I2C4_MSA_R (*((volatile uint32_t *)0x400C0000))
+#define I2C4_MCS_R (*((volatile uint32_t *)0x400C0004))
+#define I2C4_MDR_R (*((volatile uint32_t *)0x400C0008))
+#define I2C4_MTPR_R (*((volatile uint32_t *)0x400C000C))
+#define I2C4_MIMR_R (*((volatile uint32_t *)0x400C0010))
+#define I2C4_MRIS_R (*((volatile uint32_t *)0x400C0014))
+#define I2C4_MMIS_R (*((volatile uint32_t *)0x400C0018))
+#define I2C4_MICR_R (*((volatile uint32_t *)0x400C001C))
+#define I2C4_MCR_R (*((volatile uint32_t *)0x400C0020))
+#define I2C4_MCLKOCNT_R (*((volatile uint32_t *)0x400C0024))
+#define I2C4_MBMON_R (*((volatile uint32_t *)0x400C002C))
+#define I2C4_MCR2_R (*((volatile uint32_t *)0x400C0038))
+#define I2C4_SOAR_R (*((volatile uint32_t *)0x400C0800))
+#define I2C4_SCSR_R (*((volatile uint32_t *)0x400C0804))
+#define I2C4_SDR_R (*((volatile uint32_t *)0x400C0808))
+#define I2C4_SIMR_R (*((volatile uint32_t *)0x400C080C))
+#define I2C4_SRIS_R (*((volatile uint32_t *)0x400C0810))
+#define I2C4_SMIS_R (*((volatile uint32_t *)0x400C0814))
+#define I2C4_SICR_R (*((volatile uint32_t *)0x400C0818))
+#define I2C4_SOAR2_R (*((volatile uint32_t *)0x400C081C))
+#define I2C4_SACKCTL_R (*((volatile uint32_t *)0x400C0820))
+#define I2C4_PP_R (*((volatile uint32_t *)0x400C0FC0))
+#define I2C4_PC_R (*((volatile uint32_t *)0x400C0FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C5)
+//
+//*****************************************************************************
+#define I2C5_MSA_R (*((volatile uint32_t *)0x400C1000))
+#define I2C5_MCS_R (*((volatile uint32_t *)0x400C1004))
+#define I2C5_MDR_R (*((volatile uint32_t *)0x400C1008))
+#define I2C5_MTPR_R (*((volatile uint32_t *)0x400C100C))
+#define I2C5_MIMR_R (*((volatile uint32_t *)0x400C1010))
+#define I2C5_MRIS_R (*((volatile uint32_t *)0x400C1014))
+#define I2C5_MMIS_R (*((volatile uint32_t *)0x400C1018))
+#define I2C5_MICR_R (*((volatile uint32_t *)0x400C101C))
+#define I2C5_MCR_R (*((volatile uint32_t *)0x400C1020))
+#define I2C5_MCLKOCNT_R (*((volatile uint32_t *)0x400C1024))
+#define I2C5_MBMON_R (*((volatile uint32_t *)0x400C102C))
+#define I2C5_MCR2_R (*((volatile uint32_t *)0x400C1038))
+#define I2C5_SOAR_R (*((volatile uint32_t *)0x400C1800))
+#define I2C5_SCSR_R (*((volatile uint32_t *)0x400C1804))
+#define I2C5_SDR_R (*((volatile uint32_t *)0x400C1808))
+#define I2C5_SIMR_R (*((volatile uint32_t *)0x400C180C))
+#define I2C5_SRIS_R (*((volatile uint32_t *)0x400C1810))
+#define I2C5_SMIS_R (*((volatile uint32_t *)0x400C1814))
+#define I2C5_SICR_R (*((volatile uint32_t *)0x400C1818))
+#define I2C5_SOAR2_R (*((volatile uint32_t *)0x400C181C))
+#define I2C5_SACKCTL_R (*((volatile uint32_t *)0x400C1820))
+#define I2C5_PP_R (*((volatile uint32_t *)0x400C1FC0))
+#define I2C5_PC_R (*((volatile uint32_t *)0x400C1FC4))
+
+//*****************************************************************************
+//
+// System Exception Module registers (SYSEXC)
+//
+//*****************************************************************************
+#define SYSEXC_RIS_R (*((volatile uint32_t *)0x400F9000))
+#define SYSEXC_IM_R (*((volatile uint32_t *)0x400F9004))
+#define SYSEXC_MIS_R (*((volatile uint32_t *)0x400F9008))
+#define SYSEXC_IC_R (*((volatile uint32_t *)0x400F900C))
+
+//*****************************************************************************
+//
+// Hibernation module registers (HIB)
+//
+//*****************************************************************************
+#define HIB_RTCC_R (*((volatile uint32_t *)0x400FC000))
+#define HIB_RTCM0_R (*((volatile uint32_t *)0x400FC004))
+#define HIB_RTCLD_R (*((volatile uint32_t *)0x400FC00C))
+#define HIB_CTL_R (*((volatile uint32_t *)0x400FC010))
+#define HIB_IM_R (*((volatile uint32_t *)0x400FC014))
+#define HIB_RIS_R (*((volatile uint32_t *)0x400FC018))
+#define HIB_MIS_R (*((volatile uint32_t *)0x400FC01C))
+#define HIB_IC_R (*((volatile uint32_t *)0x400FC020))
+#define HIB_RTCT_R (*((volatile uint32_t *)0x400FC024))
+#define HIB_RTCSS_R (*((volatile uint32_t *)0x400FC028))
+#define HIB_DATA_R (*((volatile uint32_t *)0x400FC030))
+
+//*****************************************************************************
+//
+// FLASH registers (FLASH CTRL)
+//
+//*****************************************************************************
+#define FLASH_FMA_R (*((volatile uint32_t *)0x400FD000))
+#define FLASH_FMD_R (*((volatile uint32_t *)0x400FD004))
+#define FLASH_FMC_R (*((volatile uint32_t *)0x400FD008))
+#define FLASH_FCRIS_R (*((volatile uint32_t *)0x400FD00C))
+#define FLASH_FCIM_R (*((volatile uint32_t *)0x400FD010))
+#define FLASH_FCMISC_R (*((volatile uint32_t *)0x400FD014))
+#define FLASH_FMC2_R (*((volatile uint32_t *)0x400FD020))
+#define FLASH_FWBVAL_R (*((volatile uint32_t *)0x400FD030))
+#define FLASH_FWBN_R (*((volatile uint32_t *)0x400FD100))
+#define FLASH_FSIZE_R (*((volatile uint32_t *)0x400FDFC0))
+#define FLASH_SSIZE_R (*((volatile uint32_t *)0x400FDFC4))
+#define FLASH_ROMSWMAP_R (*((volatile uint32_t *)0x400FDFCC))
+#define FLASH_RMCTL_R (*((volatile uint32_t *)0x400FE0F0))
+#define FLASH_BOOTCFG_R (*((volatile uint32_t *)0x400FE1D0))
+#define FLASH_USERREG0_R (*((volatile uint32_t *)0x400FE1E0))
+#define FLASH_USERREG1_R (*((volatile uint32_t *)0x400FE1E4))
+#define FLASH_USERREG2_R (*((volatile uint32_t *)0x400FE1E8))
+#define FLASH_USERREG3_R (*((volatile uint32_t *)0x400FE1EC))
+#define FLASH_FMPRE0_R (*((volatile uint32_t *)0x400FE200))
+#define FLASH_FMPRE1_R (*((volatile uint32_t *)0x400FE204))
+#define FLASH_FMPRE2_R (*((volatile uint32_t *)0x400FE208))
+#define FLASH_FMPRE3_R (*((volatile uint32_t *)0x400FE20C))
+#define FLASH_FMPPE0_R (*((volatile uint32_t *)0x400FE400))
+#define FLASH_FMPPE1_R (*((volatile uint32_t *)0x400FE404))
+#define FLASH_FMPPE2_R (*((volatile uint32_t *)0x400FE408))
+#define FLASH_FMPPE3_R (*((volatile uint32_t *)0x400FE40C))
+
+//*****************************************************************************
+//
+// System Control registers (SYSCTL)
+//
+//*****************************************************************************
+#define SYSCTL_DID0_R (*((volatile uint32_t *)0x400FE000))
+#define SYSCTL_DID1_R (*((volatile uint32_t *)0x400FE004))
+#define SYSCTL_DC0_R (*((volatile uint32_t *)0x400FE008))
+#define SYSCTL_DC1_R (*((volatile uint32_t *)0x400FE010))
+#define SYSCTL_DC2_R (*((volatile uint32_t *)0x400FE014))
+#define SYSCTL_DC3_R (*((volatile uint32_t *)0x400FE018))
+#define SYSCTL_DC4_R (*((volatile uint32_t *)0x400FE01C))
+#define SYSCTL_DC5_R (*((volatile uint32_t *)0x400FE020))
+#define SYSCTL_DC6_R (*((volatile uint32_t *)0x400FE024))
+#define SYSCTL_DC7_R (*((volatile uint32_t *)0x400FE028))
+#define SYSCTL_DC8_R (*((volatile uint32_t *)0x400FE02C))
+#define SYSCTL_PBORCTL_R (*((volatile uint32_t *)0x400FE030))
+#define SYSCTL_SRCR0_R (*((volatile uint32_t *)0x400FE040))
+#define SYSCTL_SRCR1_R (*((volatile uint32_t *)0x400FE044))
+#define SYSCTL_SRCR2_R (*((volatile uint32_t *)0x400FE048))
+#define SYSCTL_RIS_R (*((volatile uint32_t *)0x400FE050))
+#define SYSCTL_IMC_R (*((volatile uint32_t *)0x400FE054))
+#define SYSCTL_MISC_R (*((volatile uint32_t *)0x400FE058))
+#define SYSCTL_RESC_R (*((volatile uint32_t *)0x400FE05C))
+#define SYSCTL_RCC_R (*((volatile uint32_t *)0x400FE060))
+#define SYSCTL_GPIOHBCTL_R (*((volatile uint32_t *)0x400FE06C))
+#define SYSCTL_RCC2_R (*((volatile uint32_t *)0x400FE070))
+#define SYSCTL_MOSCCTL_R (*((volatile uint32_t *)0x400FE07C))
+#define SYSCTL_RCGC0_R (*((volatile uint32_t *)0x400FE100))
+#define SYSCTL_RCGC1_R (*((volatile uint32_t *)0x400FE104))
+#define SYSCTL_RCGC2_R (*((volatile uint32_t *)0x400FE108))
+#define SYSCTL_SCGC0_R (*((volatile uint32_t *)0x400FE110))
+#define SYSCTL_SCGC1_R (*((volatile uint32_t *)0x400FE114))
+#define SYSCTL_SCGC2_R (*((volatile uint32_t *)0x400FE118))
+#define SYSCTL_DCGC0_R (*((volatile uint32_t *)0x400FE120))
+#define SYSCTL_DCGC1_R (*((volatile uint32_t *)0x400FE124))
+#define SYSCTL_DCGC2_R (*((volatile uint32_t *)0x400FE128))
+#define SYSCTL_DSLPCLKCFG_R (*((volatile uint32_t *)0x400FE144))
+#define SYSCTL_SYSPROP_R (*((volatile uint32_t *)0x400FE14C))
+#define SYSCTL_PIOSCCAL_R (*((volatile uint32_t *)0x400FE150))
+#define SYSCTL_PIOSCSTAT_R (*((volatile uint32_t *)0x400FE154))
+#define SYSCTL_PLLFREQ0_R (*((volatile uint32_t *)0x400FE160))
+#define SYSCTL_PLLFREQ1_R (*((volatile uint32_t *)0x400FE164))
+#define SYSCTL_PLLSTAT_R (*((volatile uint32_t *)0x400FE168))
+#define SYSCTL_DC9_R (*((volatile uint32_t *)0x400FE190))
+#define SYSCTL_NVMSTAT_R (*((volatile uint32_t *)0x400FE1A0))
+#define SYSCTL_PPWD_R (*((volatile uint32_t *)0x400FE300))
+#define SYSCTL_PPTIMER_R (*((volatile uint32_t *)0x400FE304))
+#define SYSCTL_PPGPIO_R (*((volatile uint32_t *)0x400FE308))
+#define SYSCTL_PPDMA_R (*((volatile uint32_t *)0x400FE30C))
+#define SYSCTL_PPHIB_R (*((volatile uint32_t *)0x400FE314))
+#define SYSCTL_PPUART_R (*((volatile uint32_t *)0x400FE318))
+#define SYSCTL_PPSSI_R (*((volatile uint32_t *)0x400FE31C))
+#define SYSCTL_PPI2C_R (*((volatile uint32_t *)0x400FE320))
+#define SYSCTL_PPUSB_R (*((volatile uint32_t *)0x400FE328))
+#define SYSCTL_PPCAN_R (*((volatile uint32_t *)0x400FE334))
+#define SYSCTL_PPADC_R (*((volatile uint32_t *)0x400FE338))
+#define SYSCTL_PPACMP_R (*((volatile uint32_t *)0x400FE33C))
+#define SYSCTL_PPPWM_R (*((volatile uint32_t *)0x400FE340))
+#define SYSCTL_PPQEI_R (*((volatile uint32_t *)0x400FE344))
+#define SYSCTL_PPEEPROM_R (*((volatile uint32_t *)0x400FE358))
+#define SYSCTL_PPWTIMER_R (*((volatile uint32_t *)0x400FE35C))
+#define SYSCTL_SRWD_R (*((volatile uint32_t *)0x400FE500))
+#define SYSCTL_SRTIMER_R (*((volatile uint32_t *)0x400FE504))
+#define SYSCTL_SRGPIO_R (*((volatile uint32_t *)0x400FE508))
+#define SYSCTL_SRDMA_R (*((volatile uint32_t *)0x400FE50C))
+#define SYSCTL_SRHIB_R (*((volatile uint32_t *)0x400FE514))
+#define SYSCTL_SRUART_R (*((volatile uint32_t *)0x400FE518))
+#define SYSCTL_SRSSI_R (*((volatile uint32_t *)0x400FE51C))
+#define SYSCTL_SRI2C_R (*((volatile uint32_t *)0x400FE520))
+#define SYSCTL_SRUSB_R (*((volatile uint32_t *)0x400FE528))
+#define SYSCTL_SRCAN_R (*((volatile uint32_t *)0x400FE534))
+#define SYSCTL_SRADC_R (*((volatile uint32_t *)0x400FE538))
+#define SYSCTL_SRACMP_R (*((volatile uint32_t *)0x400FE53C))
+#define SYSCTL_SRPWM_R (*((volatile uint32_t *)0x400FE540))
+#define SYSCTL_SRQEI_R (*((volatile uint32_t *)0x400FE544))
+#define SYSCTL_SREEPROM_R (*((volatile uint32_t *)0x400FE558))
+#define SYSCTL_SRWTIMER_R (*((volatile uint32_t *)0x400FE55C))
+#define SYSCTL_RCGCWD_R (*((volatile uint32_t *)0x400FE600))
+#define SYSCTL_RCGCTIMER_R (*((volatile uint32_t *)0x400FE604))
+#define SYSCTL_RCGCGPIO_R (*((volatile uint32_t *)0x400FE608))
+#define SYSCTL_RCGCDMA_R (*((volatile uint32_t *)0x400FE60C))
+#define SYSCTL_RCGCHIB_R (*((volatile uint32_t *)0x400FE614))
+#define SYSCTL_RCGCUART_R (*((volatile uint32_t *)0x400FE618))
+#define SYSCTL_RCGCSSI_R (*((volatile uint32_t *)0x400FE61C))
+#define SYSCTL_RCGCI2C_R (*((volatile uint32_t *)0x400FE620))
+#define SYSCTL_RCGCUSB_R (*((volatile uint32_t *)0x400FE628))
+#define SYSCTL_RCGCCAN_R (*((volatile uint32_t *)0x400FE634))
+#define SYSCTL_RCGCADC_R (*((volatile uint32_t *)0x400FE638))
+#define SYSCTL_RCGCACMP_R (*((volatile uint32_t *)0x400FE63C))
+#define SYSCTL_RCGCPWM_R (*((volatile uint32_t *)0x400FE640))
+#define SYSCTL_RCGCQEI_R (*((volatile uint32_t *)0x400FE644))
+#define SYSCTL_RCGCEEPROM_R (*((volatile uint32_t *)0x400FE658))
+#define SYSCTL_RCGCWTIMER_R (*((volatile uint32_t *)0x400FE65C))
+#define SYSCTL_SCGCWD_R (*((volatile uint32_t *)0x400FE700))
+#define SYSCTL_SCGCTIMER_R (*((volatile uint32_t *)0x400FE704))
+#define SYSCTL_SCGCGPIO_R (*((volatile uint32_t *)0x400FE708))
+#define SYSCTL_SCGCDMA_R (*((volatile uint32_t *)0x400FE70C))
+#define SYSCTL_SCGCHIB_R (*((volatile uint32_t *)0x400FE714))
+#define SYSCTL_SCGCUART_R (*((volatile uint32_t *)0x400FE718))
+#define SYSCTL_SCGCSSI_R (*((volatile uint32_t *)0x400FE71C))
+#define SYSCTL_SCGCI2C_R (*((volatile uint32_t *)0x400FE720))
+#define SYSCTL_SCGCUSB_R (*((volatile uint32_t *)0x400FE728))
+#define SYSCTL_SCGCCAN_R (*((volatile uint32_t *)0x400FE734))
+#define SYSCTL_SCGCADC_R (*((volatile uint32_t *)0x400FE738))
+#define SYSCTL_SCGCACMP_R (*((volatile uint32_t *)0x400FE73C))
+#define SYSCTL_SCGCPWM_R (*((volatile uint32_t *)0x400FE740))
+#define SYSCTL_SCGCQEI_R (*((volatile uint32_t *)0x400FE744))
+#define SYSCTL_SCGCEEPROM_R (*((volatile uint32_t *)0x400FE758))
+#define SYSCTL_SCGCWTIMER_R (*((volatile uint32_t *)0x400FE75C))
+#define SYSCTL_DCGCWD_R (*((volatile uint32_t *)0x400FE800))
+#define SYSCTL_DCGCTIMER_R (*((volatile uint32_t *)0x400FE804))
+#define SYSCTL_DCGCGPIO_R (*((volatile uint32_t *)0x400FE808))
+#define SYSCTL_DCGCDMA_R (*((volatile uint32_t *)0x400FE80C))
+#define SYSCTL_DCGCHIB_R (*((volatile uint32_t *)0x400FE814))
+#define SYSCTL_DCGCUART_R (*((volatile uint32_t *)0x400FE818))
+#define SYSCTL_DCGCSSI_R (*((volatile uint32_t *)0x400FE81C))
+#define SYSCTL_DCGCI2C_R (*((volatile uint32_t *)0x400FE820))
+#define SYSCTL_DCGCUSB_R (*((volatile uint32_t *)0x400FE828))
+#define SYSCTL_DCGCCAN_R (*((volatile uint32_t *)0x400FE834))
+#define SYSCTL_DCGCADC_R (*((volatile uint32_t *)0x400FE838))
+#define SYSCTL_DCGCACMP_R (*((volatile uint32_t *)0x400FE83C))
+#define SYSCTL_DCGCPWM_R (*((volatile uint32_t *)0x400FE840))
+#define SYSCTL_DCGCQEI_R (*((volatile uint32_t *)0x400FE844))
+#define SYSCTL_DCGCEEPROM_R (*((volatile uint32_t *)0x400FE858))
+#define SYSCTL_DCGCWTIMER_R (*((volatile uint32_t *)0x400FE85C))
+#define SYSCTL_PRWD_R (*((volatile uint32_t *)0x400FEA00))
+#define SYSCTL_PRTIMER_R (*((volatile uint32_t *)0x400FEA04))
+#define SYSCTL_PRGPIO_R (*((volatile uint32_t *)0x400FEA08))
+#define SYSCTL_PRDMA_R (*((volatile uint32_t *)0x400FEA0C))
+#define SYSCTL_PRHIB_R (*((volatile uint32_t *)0x400FEA14))
+#define SYSCTL_PRUART_R (*((volatile uint32_t *)0x400FEA18))
+#define SYSCTL_PRSSI_R (*((volatile uint32_t *)0x400FEA1C))
+#define SYSCTL_PRI2C_R (*((volatile uint32_t *)0x400FEA20))
+#define SYSCTL_PRUSB_R (*((volatile uint32_t *)0x400FEA28))
+#define SYSCTL_PRCAN_R (*((volatile uint32_t *)0x400FEA34))
+#define SYSCTL_PRADC_R (*((volatile uint32_t *)0x400FEA38))
+#define SYSCTL_PRACMP_R (*((volatile uint32_t *)0x400FEA3C))
+#define SYSCTL_PRPWM_R (*((volatile uint32_t *)0x400FEA40))
+#define SYSCTL_PRQEI_R (*((volatile uint32_t *)0x400FEA44))
+#define SYSCTL_PREEPROM_R (*((volatile uint32_t *)0x400FEA58))
+#define SYSCTL_PRWTIMER_R (*((volatile uint32_t *)0x400FEA5C))
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access registers (UDMA)
+//
+//*****************************************************************************
+#define UDMA_STAT_R (*((volatile uint32_t *)0x400FF000))
+#define UDMA_CFG_R (*((volatile uint32_t *)0x400FF004))
+#define UDMA_CTLBASE_R (*((volatile uint32_t *)0x400FF008))
+#define UDMA_ALTBASE_R (*((volatile uint32_t *)0x400FF00C))
+#define UDMA_WAITSTAT_R (*((volatile uint32_t *)0x400FF010))
+#define UDMA_SWREQ_R (*((volatile uint32_t *)0x400FF014))
+#define UDMA_USEBURSTSET_R (*((volatile uint32_t *)0x400FF018))
+#define UDMA_USEBURSTCLR_R (*((volatile uint32_t *)0x400FF01C))
+#define UDMA_REQMASKSET_R (*((volatile uint32_t *)0x400FF020))
+#define UDMA_REQMASKCLR_R (*((volatile uint32_t *)0x400FF024))
+#define UDMA_ENASET_R (*((volatile uint32_t *)0x400FF028))
+#define UDMA_ENACLR_R (*((volatile uint32_t *)0x400FF02C))
+#define UDMA_ALTSET_R (*((volatile uint32_t *)0x400FF030))
+#define UDMA_ALTCLR_R (*((volatile uint32_t *)0x400FF034))
+#define UDMA_PRIOSET_R (*((volatile uint32_t *)0x400FF038))
+#define UDMA_PRIOCLR_R (*((volatile uint32_t *)0x400FF03C))
+#define UDMA_ERRCLR_R (*((volatile uint32_t *)0x400FF04C))
+#define UDMA_CHASGN_R (*((volatile uint32_t *)0x400FF500))
+#define UDMA_CHIS_R (*((volatile uint32_t *)0x400FF504))
+#define UDMA_CHMAP0_R (*((volatile uint32_t *)0x400FF510))
+#define UDMA_CHMAP1_R (*((volatile uint32_t *)0x400FF514))
+#define UDMA_CHMAP2_R (*((volatile uint32_t *)0x400FF518))
+#define UDMA_CHMAP3_R (*((volatile uint32_t *)0x400FF51C))
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access (uDMA) offsets (UDMA)
+//
+//*****************************************************************************
+#define UDMA_SRCENDP 0x00000000 // DMA Channel Source Address End
+ // Pointer
+#define UDMA_DSTENDP 0x00000004 // DMA Channel Destination Address
+ // End Pointer
+#define UDMA_CHCTL 0x00000008 // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// NVIC registers (NVIC)
+//
+//*****************************************************************************
+#define NVIC_ACTLR_R (*((volatile uint32_t *)0xE000E008))
+#define NVIC_ST_CTRL_R (*((volatile uint32_t *)0xE000E010))
+#define NVIC_ST_RELOAD_R (*((volatile uint32_t *)0xE000E014))
+#define NVIC_ST_CURRENT_R (*((volatile uint32_t *)0xE000E018))
+#define NVIC_EN0_R (*((volatile uint32_t *)0xE000E100))
+#define NVIC_EN1_R (*((volatile uint32_t *)0xE000E104))
+#define NVIC_EN2_R (*((volatile uint32_t *)0xE000E108))
+#define NVIC_EN3_R (*((volatile uint32_t *)0xE000E10C))
+#define NVIC_EN4_R (*((volatile uint32_t *)0xE000E110))
+#define NVIC_DIS0_R (*((volatile uint32_t *)0xE000E180))
+#define NVIC_DIS1_R (*((volatile uint32_t *)0xE000E184))
+#define NVIC_DIS2_R (*((volatile uint32_t *)0xE000E188))
+#define NVIC_DIS3_R (*((volatile uint32_t *)0xE000E18C))
+#define NVIC_DIS4_R (*((volatile uint32_t *)0xE000E190))
+#define NVIC_PEND0_R (*((volatile uint32_t *)0xE000E200))
+#define NVIC_PEND1_R (*((volatile uint32_t *)0xE000E204))
+#define NVIC_PEND2_R (*((volatile uint32_t *)0xE000E208))
+#define NVIC_PEND3_R (*((volatile uint32_t *)0xE000E20C))
+#define NVIC_PEND4_R (*((volatile uint32_t *)0xE000E210))
+#define NVIC_UNPEND0_R (*((volatile uint32_t *)0xE000E280))
+#define NVIC_UNPEND1_R (*((volatile uint32_t *)0xE000E284))
+#define NVIC_UNPEND2_R (*((volatile uint32_t *)0xE000E288))
+#define NVIC_UNPEND3_R (*((volatile uint32_t *)0xE000E28C))
+#define NVIC_UNPEND4_R (*((volatile uint32_t *)0xE000E290))
+#define NVIC_ACTIVE0_R (*((volatile uint32_t *)0xE000E300))
+#define NVIC_ACTIVE1_R (*((volatile uint32_t *)0xE000E304))
+#define NVIC_ACTIVE2_R (*((volatile uint32_t *)0xE000E308))
+#define NVIC_ACTIVE3_R (*((volatile uint32_t *)0xE000E30C))
+#define NVIC_ACTIVE4_R (*((volatile uint32_t *)0xE000E310))
+#define NVIC_PRI0_R (*((volatile uint32_t *)0xE000E400))
+#define NVIC_PRI1_R (*((volatile uint32_t *)0xE000E404))
+#define NVIC_PRI2_R (*((volatile uint32_t *)0xE000E408))
+#define NVIC_PRI3_R (*((volatile uint32_t *)0xE000E40C))
+#define NVIC_PRI4_R (*((volatile uint32_t *)0xE000E410))
+#define NVIC_PRI5_R (*((volatile uint32_t *)0xE000E414))
+#define NVIC_PRI6_R (*((volatile uint32_t *)0xE000E418))
+#define NVIC_PRI7_R (*((volatile uint32_t *)0xE000E41C))
+#define NVIC_PRI8_R (*((volatile uint32_t *)0xE000E420))
+#define NVIC_PRI9_R (*((volatile uint32_t *)0xE000E424))
+#define NVIC_PRI10_R (*((volatile uint32_t *)0xE000E428))
+#define NVIC_PRI11_R (*((volatile uint32_t *)0xE000E42C))
+#define NVIC_PRI12_R (*((volatile uint32_t *)0xE000E430))
+#define NVIC_PRI13_R (*((volatile uint32_t *)0xE000E434))
+#define NVIC_PRI14_R (*((volatile uint32_t *)0xE000E438))
+#define NVIC_PRI15_R (*((volatile uint32_t *)0xE000E43C))
+#define NVIC_PRI16_R (*((volatile uint32_t *)0xE000E440))
+#define NVIC_PRI17_R (*((volatile uint32_t *)0xE000E444))
+#define NVIC_PRI18_R (*((volatile uint32_t *)0xE000E448))
+#define NVIC_PRI19_R (*((volatile uint32_t *)0xE000E44C))
+#define NVIC_PRI20_R (*((volatile uint32_t *)0xE000E450))
+#define NVIC_PRI21_R (*((volatile uint32_t *)0xE000E454))
+#define NVIC_PRI22_R (*((volatile uint32_t *)0xE000E458))
+#define NVIC_PRI23_R (*((volatile uint32_t *)0xE000E45C))
+#define NVIC_PRI24_R (*((volatile uint32_t *)0xE000E460))
+#define NVIC_PRI25_R (*((volatile uint32_t *)0xE000E464))
+#define NVIC_PRI26_R (*((volatile uint32_t *)0xE000E468))
+#define NVIC_PRI27_R (*((volatile uint32_t *)0xE000E46C))
+#define NVIC_PRI28_R (*((volatile uint32_t *)0xE000E470))
+#define NVIC_PRI29_R (*((volatile uint32_t *)0xE000E474))
+#define NVIC_PRI30_R (*((volatile uint32_t *)0xE000E478))
+#define NVIC_PRI31_R (*((volatile uint32_t *)0xE000E47C))
+#define NVIC_PRI32_R (*((volatile uint32_t *)0xE000E480))
+#define NVIC_PRI33_R (*((volatile uint32_t *)0xE000E484))
+#define NVIC_PRI34_R (*((volatile uint32_t *)0xE000E488))
+#define NVIC_CPUID_R (*((volatile uint32_t *)0xE000ED00))
+#define NVIC_INT_CTRL_R (*((volatile uint32_t *)0xE000ED04))
+#define NVIC_VTABLE_R (*((volatile uint32_t *)0xE000ED08))
+#define NVIC_APINT_R (*((volatile uint32_t *)0xE000ED0C))
+#define NVIC_SYS_CTRL_R (*((volatile uint32_t *)0xE000ED10))
+#define NVIC_CFG_CTRL_R (*((volatile uint32_t *)0xE000ED14))
+#define NVIC_SYS_PRI1_R (*((volatile uint32_t *)0xE000ED18))
+#define NVIC_SYS_PRI2_R (*((volatile uint32_t *)0xE000ED1C))
+#define NVIC_SYS_PRI3_R (*((volatile uint32_t *)0xE000ED20))
+#define NVIC_SYS_HND_CTRL_R (*((volatile uint32_t *)0xE000ED24))
+#define NVIC_FAULT_STAT_R (*((volatile uint32_t *)0xE000ED28))
+#define NVIC_HFAULT_STAT_R (*((volatile uint32_t *)0xE000ED2C))
+#define NVIC_DEBUG_STAT_R (*((volatile uint32_t *)0xE000ED30))
+#define NVIC_MM_ADDR_R (*((volatile uint32_t *)0xE000ED34))
+#define NVIC_FAULT_ADDR_R (*((volatile uint32_t *)0xE000ED38))
+#define NVIC_CPAC_R (*((volatile uint32_t *)0xE000ED88))
+#define NVIC_MPU_TYPE_R (*((volatile uint32_t *)0xE000ED90))
+#define NVIC_MPU_CTRL_R (*((volatile uint32_t *)0xE000ED94))
+#define NVIC_MPU_NUMBER_R (*((volatile uint32_t *)0xE000ED98))
+#define NVIC_MPU_BASE_R (*((volatile uint32_t *)0xE000ED9C))
+#define NVIC_MPU_ATTR_R (*((volatile uint32_t *)0xE000EDA0))
+#define NVIC_MPU_BASE1_R (*((volatile uint32_t *)0xE000EDA4))
+#define NVIC_MPU_ATTR1_R (*((volatile uint32_t *)0xE000EDA8))
+#define NVIC_MPU_BASE2_R (*((volatile uint32_t *)0xE000EDAC))
+#define NVIC_MPU_ATTR2_R (*((volatile uint32_t *)0xE000EDB0))
+#define NVIC_MPU_BASE3_R (*((volatile uint32_t *)0xE000EDB4))
+#define NVIC_MPU_ATTR3_R (*((volatile uint32_t *)0xE000EDB8))
+#define NVIC_DBG_CTRL_R (*((volatile uint32_t *)0xE000EDF0))
+#define NVIC_DBG_XFER_R (*((volatile uint32_t *)0xE000EDF4))
+#define NVIC_DBG_DATA_R (*((volatile uint32_t *)0xE000EDF8))
+#define NVIC_DBG_INT_R (*((volatile uint32_t *)0xE000EDFC))
+#define NVIC_SW_TRIG_R (*((volatile uint32_t *)0xE000EF00))
+#define NVIC_FPCC_R (*((volatile uint32_t *)0xE000EF34))
+#define NVIC_FPCA_R (*((volatile uint32_t *)0xE000EF38))
+#define NVIC_FPDSC_R (*((volatile uint32_t *)0xE000EF3C))
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
+#define WDT_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
+#define WDT_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC 0x80000000 // Write Complete
+#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
+#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
+#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
+#define WDT_ICR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
+#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WDT_LOCK_LOCKED 0x00000001 // Locked
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_IM register.
+//
+//*****************************************************************************
+#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
+#define GPIO_IM_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_RIS register.
+//
+//*****************************************************************************
+#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
+#define GPIO_RIS_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_MIS register.
+//
+//*****************************************************************************
+#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
+#define GPIO_MIS_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_ICR register.
+//
+//*****************************************************************************
+#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
+#define GPIO_ICR_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
+#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
+ // and may be modified
+#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
+ // and may not be modified
+#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_SI register.
+//
+//*****************************************************************************
+#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port A.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask
+#define GPIO_PCTL_PA7_I2C1SDA 0x30000000 // I2C1SDA on PA7
+#define GPIO_PCTL_PA7_M1PWM3 0x50000000 // M1PWM3 on PA7
+#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask
+#define GPIO_PCTL_PA6_I2C1SCL 0x03000000 // I2C1SCL on PA6
+#define GPIO_PCTL_PA6_M1PWM2 0x05000000 // M1PWM2 on PA6
+#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 mask
+#define GPIO_PCTL_PA5_SSI0TX 0x00200000 // SSI0TX on PA5
+#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 mask
+#define GPIO_PCTL_PA4_SSI0RX 0x00020000 // SSI0RX on PA4
+#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 mask
+#define GPIO_PCTL_PA3_SSI0FSS 0x00002000 // SSI0FSS on PA3
+#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 mask
+#define GPIO_PCTL_PA2_SSI0CLK 0x00000200 // SSI0CLK on PA2
+#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 mask
+#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1
+#define GPIO_PCTL_PA1_CAN1TX 0x00000080 // CAN1TX on PA1
+#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask
+#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0
+#define GPIO_PCTL_PA0_CAN1RX 0x00000008 // CAN1RX on PA0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port B.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 mask
+#define GPIO_PCTL_PB5_SSI2FSS 0x00200000 // SSI2FSS on PB5
+#define GPIO_PCTL_PB5_M0PWM3 0x00400000 // M0PWM3 on PB5
+#define GPIO_PCTL_PB5_T1CCP1 0x00700000 // T1CCP1 on PB5
+#define GPIO_PCTL_PB5_CAN0TX 0x00800000 // CAN0TX on PB5
+#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 mask
+#define GPIO_PCTL_PB4_SSI2CLK 0x00020000 // SSI2CLK on PB4
+#define GPIO_PCTL_PB4_M0PWM2 0x00040000 // M0PWM2 on PB4
+#define GPIO_PCTL_PB4_T1CCP0 0x00070000 // T1CCP0 on PB4
+#define GPIO_PCTL_PB4_CAN0RX 0x00080000 // CAN0RX on PB4
+#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 mask
+#define GPIO_PCTL_PB3_I2C0SDA 0x00003000 // I2C0SDA on PB3
+#define GPIO_PCTL_PB3_T3CCP1 0x00007000 // T3CCP1 on PB3
+#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 mask
+#define GPIO_PCTL_PB2_I2C0SCL 0x00000300 // I2C0SCL on PB2
+#define GPIO_PCTL_PB2_T3CCP0 0x00000700 // T3CCP0 on PB2
+#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 mask
+#define GPIO_PCTL_PB1_USB0VBUS 0x00000000 // USB0VBUS on PB1
+#define GPIO_PCTL_PB1_U1TX 0x00000010 // U1TX on PB1
+#define GPIO_PCTL_PB1_T2CCP1 0x00000070 // T2CCP1 on PB1
+#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask
+#define GPIO_PCTL_PB0_USB0ID 0x00000000 // USB0ID on PB0
+#define GPIO_PCTL_PB0_U1RX 0x00000001 // U1RX on PB0
+#define GPIO_PCTL_PB0_T2CCP0 0x00000007 // T2CCP0 on PB0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port C.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask
+#define GPIO_PCTL_PC7_U3TX 0x10000000 // U3TX on PC7
+#define GPIO_PCTL_PC7_WT1CCP1 0x70000000 // WT1CCP1 on PC7
+#define GPIO_PCTL_PC7_USB0PFLT 0x80000000 // USB0PFLT on PC7
+#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask
+#define GPIO_PCTL_PC6_U3RX 0x01000000 // U3RX on PC6
+#define GPIO_PCTL_PC6_PHB1 0x06000000 // PHB1 on PC6
+#define GPIO_PCTL_PC6_WT1CCP0 0x07000000 // WT1CCP0 on PC6
+#define GPIO_PCTL_PC6_USB0EPEN 0x08000000 // USB0EPEN on PC6
+#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 mask
+#define GPIO_PCTL_PC5_U4TX 0x00100000 // U4TX on PC5
+#define GPIO_PCTL_PC5_U1TX 0x00200000 // U1TX on PC5
+#define GPIO_PCTL_PC5_M0PWM7 0x00400000 // M0PWM7 on PC5
+#define GPIO_PCTL_PC5_PHA1 0x00600000 // PHA1 on PC5
+#define GPIO_PCTL_PC5_WT0CCP1 0x00700000 // WT0CCP1 on PC5
+#define GPIO_PCTL_PC5_U1CTS 0x00800000 // U1CTS on PC5
+#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 mask
+#define GPIO_PCTL_PC4_U4RX 0x00010000 // U4RX on PC4
+#define GPIO_PCTL_PC4_U1RX 0x00020000 // U1RX on PC4
+#define GPIO_PCTL_PC4_M0PWM6 0x00040000 // M0PWM6 on PC4
+#define GPIO_PCTL_PC4_IDX1 0x00060000 // IDX1 on PC4
+#define GPIO_PCTL_PC4_WT0CCP0 0x00070000 // WT0CCP0 on PC4
+#define GPIO_PCTL_PC4_U1RTS 0x00080000 // U1RTS on PC4
+#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 mask
+#define GPIO_PCTL_PC3_TDO 0x00001000 // TDO on PC3
+#define GPIO_PCTL_PC3_T5CCP1 0x00007000 // T5CCP1 on PC3
+#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 mask
+#define GPIO_PCTL_PC2_TDI 0x00000100 // TDI on PC2
+#define GPIO_PCTL_PC2_T5CCP0 0x00000700 // T5CCP0 on PC2
+#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 mask
+#define GPIO_PCTL_PC1_TMS 0x00000010 // TMS on PC1
+#define GPIO_PCTL_PC1_T4CCP1 0x00000070 // T4CCP1 on PC1
+#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask
+#define GPIO_PCTL_PC0_TCK 0x00000001 // TCK on PC0
+#define GPIO_PCTL_PC0_T4CCP0 0x00000007 // T4CCP0 on PC0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port D.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask
+#define GPIO_PCTL_PD7_AIN4 0x00000000 // AIN4 on PD7
+#define GPIO_PCTL_PD7_U2TX 0x10000000 // U2TX on PD7
+#define GPIO_PCTL_PD7_M0FAULT1 0x40000000 // M0FAULT1 on PD7
+#define GPIO_PCTL_PD7_PHB0 0x60000000 // PHB0 on PD7
+#define GPIO_PCTL_PD7_WT5CCP1 0x70000000 // WT5CCP1 on PD7
+#define GPIO_PCTL_PD7_NMI 0x80000000 // NMI on PD7
+#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask
+#define GPIO_PCTL_PD6_AIN5 0x00000000 // AIN5 on PD6
+#define GPIO_PCTL_PD6_U2RX 0x01000000 // U2RX on PD6
+#define GPIO_PCTL_PD6_M0FAULT0 0x04000000 // M0FAULT0 on PD6
+#define GPIO_PCTL_PD6_PHA0 0x06000000 // PHA0 on PD6
+#define GPIO_PCTL_PD6_WT5CCP0 0x07000000 // WT5CCP0 on PD6
+#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 mask
+#define GPIO_PCTL_PD5_U6TX 0x00100000 // U6TX on PD5
+#define GPIO_PCTL_PD5_WT4CCP1 0x00700000 // WT4CCP1 on PD5
+#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 mask
+#define GPIO_PCTL_PD4_AIN7 0x00000000 // AIN7 on PD4
+#define GPIO_PCTL_PD4_U6RX 0x00010000 // U6RX on PD4
+#define GPIO_PCTL_PD4_WT4CCP0 0x00070000 // WT4CCP0 on PD4
+#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 mask
+#define GPIO_PCTL_PD3_AIN12 0x00000000 // AIN12 on PD3
+#define GPIO_PCTL_PD3_SSI3TX 0x00001000 // SSI3TX on PD3
+#define GPIO_PCTL_PD3_SSI1TX 0x00002000 // SSI1TX on PD3
+#define GPIO_PCTL_PD3_IDX0 0x00006000 // IDX0 on PD3
+#define GPIO_PCTL_PD3_WT3CCP1 0x00007000 // WT3CCP1 on PD3
+#define GPIO_PCTL_PD3_USB0PFLT 0x00008000 // USB0PFLT on PD3
+#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 mask
+#define GPIO_PCTL_PD2_AIN13 0x00000000 // AIN13 on PD2
+#define GPIO_PCTL_PD2_SSI3RX 0x00000100 // SSI3RX on PD2
+#define GPIO_PCTL_PD2_SSI1RX 0x00000200 // SSI1RX on PD2
+#define GPIO_PCTL_PD2_M0FAULT0 0x00000400 // M0FAULT0 on PD2
+#define GPIO_PCTL_PD2_WT3CCP0 0x00000700 // WT3CCP0 on PD2
+#define GPIO_PCTL_PD2_USB0EPEN 0x00000800 // USB0EPEN on PD2
+#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 mask
+#define GPIO_PCTL_PD1_AIN14 0x00000000 // AIN14 on PD1
+#define GPIO_PCTL_PD1_SSI3FSS 0x00000010 // SSI3FSS on PD1
+#define GPIO_PCTL_PD1_SSI1FSS 0x00000020 // SSI1FSS on PD1
+#define GPIO_PCTL_PD1_I2C3SDA 0x00000030 // I2C3SDA on PD1
+#define GPIO_PCTL_PD1_M0PWM7 0x00000040 // M0PWM7 on PD1
+#define GPIO_PCTL_PD1_M1PWM1 0x00000050 // M1PWM1 on PD1
+#define GPIO_PCTL_PD1_WT2CCP1 0x00000070 // WT2CCP1 on PD1
+#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask
+#define GPIO_PCTL_PD0_AIN15 0x00000000 // AIN15 on PD0
+#define GPIO_PCTL_PD0_SSI3CLK 0x00000001 // SSI3CLK on PD0
+#define GPIO_PCTL_PD0_SSI1CLK 0x00000002 // SSI1CLK on PD0
+#define GPIO_PCTL_PD0_I2C3SCL 0x00000003 // I2C3SCL on PD0
+#define GPIO_PCTL_PD0_M0PWM6 0x00000004 // M0PWM6 on PD0
+#define GPIO_PCTL_PD0_M1PWM0 0x00000005 // M1PWM0 on PD0
+#define GPIO_PCTL_PD0_WT2CCP0 0x00000007 // WT2CCP0 on PD0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port E.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PE7_M 0xF0000000 // PE7 mask
+#define GPIO_PCTL_PE7_AIN20 0x00000000 // AIN20 on PE7
+#define GPIO_PCTL_PE7_U1RI 0x10000000 // U1RI on PE7
+#define GPIO_PCTL_PE7_CAN1TX 0x80000000 // CAN1TX on PE7
+#define GPIO_PCTL_PE6_M 0x0F000000 // PE6 mask
+#define GPIO_PCTL_PE6_AIN21 0x00000000 // AIN21 on PE6
+#define GPIO_PCTL_PE6_CAN1RX 0x08000000 // CAN1RX on PE6
+#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 mask
+#define GPIO_PCTL_PE5_AIN8 0x00000000 // AIN8 on PE5
+#define GPIO_PCTL_PE5_U5TX 0x00100000 // U5TX on PE5
+#define GPIO_PCTL_PE5_I2C2SDA 0x00300000 // I2C2SDA on PE5
+#define GPIO_PCTL_PE5_M0PWM5 0x00400000 // M0PWM5 on PE5
+#define GPIO_PCTL_PE5_M1PWM3 0x00500000 // M1PWM3 on PE5
+#define GPIO_PCTL_PE5_CAN0TX 0x00800000 // CAN0TX on PE5
+#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 mask
+#define GPIO_PCTL_PE4_AIN9 0x00000000 // AIN9 on PE4
+#define GPIO_PCTL_PE4_U5RX 0x00010000 // U5RX on PE4
+#define GPIO_PCTL_PE4_I2C2SCL 0x00030000 // I2C2SCL on PE4
+#define GPIO_PCTL_PE4_M0PWM4 0x00040000 // M0PWM4 on PE4
+#define GPIO_PCTL_PE4_M1PWM2 0x00050000 // M1PWM2 on PE4
+#define GPIO_PCTL_PE4_CAN0RX 0x00080000 // CAN0RX on PE4
+#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 mask
+#define GPIO_PCTL_PE3_AIN0 0x00000000 // AIN0 on PE3
+#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 mask
+#define GPIO_PCTL_PE2_AIN1 0x00000000 // AIN1 on PE2
+#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 mask
+#define GPIO_PCTL_PE1_AIN2 0x00000000 // AIN2 on PE1
+#define GPIO_PCTL_PE1_U7TX 0x00000010 // U7TX on PE1
+#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask
+#define GPIO_PCTL_PE0_AIN3 0x00000000 // AIN3 on PE0
+#define GPIO_PCTL_PE0_U7RX 0x00000001 // U7RX on PE0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port F.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PF7_M 0xF0000000 // PF7 mask
+#define GPIO_PCTL_PF7_I2C2SDA 0x30000000 // I2C2SDA on PF7
+#define GPIO_PCTL_PF7_M1FAULT0 0x50000000 // M1FAULT0 on PF7
+#define GPIO_PCTL_PF7_T3CCP1 0x70000000 // T3CCP1 on PF7
+#define GPIO_PCTL_PF6_M 0x0F000000 // PF6 mask
+#define GPIO_PCTL_PF6_I2C2SCL 0x03000000 // I2C2SCL on PF6
+#define GPIO_PCTL_PF6_T3CCP0 0x07000000 // T3CCP0 on PF6
+#define GPIO_PCTL_PF5_M 0x00F00000 // PF5 mask
+#define GPIO_PCTL_PF5_M0FAULT3 0x00400000 // M0FAULT3 on PF5
+#define GPIO_PCTL_PF5_T2CCP1 0x00700000 // T2CCP1 on PF5
+#define GPIO_PCTL_PF5_USB0PFLT 0x00800000 // USB0PFLT on PF5
+#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 mask
+#define GPIO_PCTL_PF4_U1DTR 0x00010000 // U1DTR on PF4
+#define GPIO_PCTL_PF4_M0FAULT2 0x00040000 // M0FAULT2 on PF4
+#define GPIO_PCTL_PF4_M1FAULT0 0x00050000 // M1FAULT0 on PF4
+#define GPIO_PCTL_PF4_IDX0 0x00060000 // IDX0 on PF4
+#define GPIO_PCTL_PF4_T2CCP0 0x00070000 // T2CCP0 on PF4
+#define GPIO_PCTL_PF4_USB0EPEN 0x00080000 // USB0EPEN on PF4
+#define GPIO_PCTL_PF4_TRD3 0x000E0000 // TRD3 on PF4
+#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 mask
+#define GPIO_PCTL_PF3_U1DSR 0x00001000 // U1DSR on PF3
+#define GPIO_PCTL_PF3_SSI1FSS 0x00002000 // SSI1FSS on PF3
+#define GPIO_PCTL_PF3_CAN0TX 0x00003000 // CAN0TX on PF3
+#define GPIO_PCTL_PF3_M0FAULT1 0x00004000 // M0FAULT1 on PF3
+#define GPIO_PCTL_PF3_M1PWM7 0x00005000 // M1PWM7 on PF3
+#define GPIO_PCTL_PF3_T1CCP1 0x00007000 // T1CCP1 on PF3
+#define GPIO_PCTL_PF3_TRCLK 0x0000E000 // TRCLK on PF3
+#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 mask
+#define GPIO_PCTL_PF2_U1DCD 0x00000100 // U1DCD on PF2
+#define GPIO_PCTL_PF2_SSI1CLK 0x00000200 // SSI1CLK on PF2
+#define GPIO_PCTL_PF2_M0FAULT0 0x00000400 // M0FAULT0 on PF2
+#define GPIO_PCTL_PF2_M1PWM6 0x00000500 // M1PWM6 on PF2
+#define GPIO_PCTL_PF2_T1CCP0 0x00000700 // T1CCP0 on PF2
+#define GPIO_PCTL_PF2_C2O 0x00000900 // C2O on PF2
+#define GPIO_PCTL_PF2_TRD0 0x00000E00 // TRD0 on PF2
+#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 mask
+#define GPIO_PCTL_PF1_U1CTS 0x00000010 // U1CTS on PF1
+#define GPIO_PCTL_PF1_SSI1TX 0x00000020 // SSI1TX on PF1
+#define GPIO_PCTL_PF1_M1PWM5 0x00000050 // M1PWM5 on PF1
+#define GPIO_PCTL_PF1_PHB0 0x00000060 // PHB0 on PF1
+#define GPIO_PCTL_PF1_T0CCP1 0x00000070 // T0CCP1 on PF1
+#define GPIO_PCTL_PF1_C1O 0x00000090 // C1O on PF1
+#define GPIO_PCTL_PF1_TRD1 0x000000E0 // TRD1 on PF1
+#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask
+#define GPIO_PCTL_PF0_U1RTS 0x00000001 // U1RTS on PF0
+#define GPIO_PCTL_PF0_SSI1RX 0x00000002 // SSI1RX on PF0
+#define GPIO_PCTL_PF0_CAN0RX 0x00000003 // CAN0RX on PF0
+#define GPIO_PCTL_PF0_M1PWM4 0x00000005 // M1PWM4 on PF0
+#define GPIO_PCTL_PF0_PHA0 0x00000006 // PHA0 on PF0
+#define GPIO_PCTL_PF0_T0CCP0 0x00000007 // T0CCP0 on PF0
+#define GPIO_PCTL_PF0_NMI 0x00000008 // NMI on PF0
+#define GPIO_PCTL_PF0_C0O 0x00000009 // C0O on PF0
+#define GPIO_PCTL_PF0_TRD2 0x0000000E // TRD2 on PF0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port G.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PG7_M 0xF0000000 // PG7 mask
+#define GPIO_PCTL_PG7_I2C5SDA 0x30000000 // I2C5SDA on PG7
+#define GPIO_PCTL_PG7_M0PWM7 0x40000000 // M0PWM7 on PG7
+#define GPIO_PCTL_PG7_IDX1 0x50000000 // IDX1 on PG7
+#define GPIO_PCTL_PG7_WT1CCP1 0x70000000 // WT1CCP1 on PG7
+#define GPIO_PCTL_PG6_M 0x0F000000 // PG6 mask
+#define GPIO_PCTL_PG6_I2C5SCL 0x03000000 // I2C5SCL on PG6
+#define GPIO_PCTL_PG6_M0PWM6 0x04000000 // M0PWM6 on PG6
+#define GPIO_PCTL_PG6_WT1CCP0 0x07000000 // WT1CCP0 on PG6
+#define GPIO_PCTL_PG5_M 0x00F00000 // PG5 mask
+#define GPIO_PCTL_PG5_U2TX 0x00100000 // U2TX on PG5
+#define GPIO_PCTL_PG5_I2C1SDA 0x00300000 // I2C1SDA on PG5
+#define GPIO_PCTL_PG5_M0PWM5 0x00400000 // M0PWM5 on PG5
+#define GPIO_PCTL_PG5_M1PWM3 0x00500000 // M1PWM3 on PG5
+#define GPIO_PCTL_PG5_IDX1 0x00600000 // IDX1 on PG5
+#define GPIO_PCTL_PG5_WT0CCP1 0x00700000 // WT0CCP1 on PG5
+#define GPIO_PCTL_PG5_USB0PFLT 0x00800000 // USB0PFLT on PG5
+#define GPIO_PCTL_PG4_M 0x000F0000 // PG4 mask
+#define GPIO_PCTL_PG4_U2RX 0x00010000 // U2RX on PG4
+#define GPIO_PCTL_PG4_I2C1SCL 0x00030000 // I2C1SCL on PG4
+#define GPIO_PCTL_PG4_M0PWM4 0x00040000 // M0PWM4 on PG4
+#define GPIO_PCTL_PG4_M1PWM2 0x00050000 // M1PWM2 on PG4
+#define GPIO_PCTL_PG4_PHB1 0x00060000 // PHB1 on PG4
+#define GPIO_PCTL_PG4_WT0CCP0 0x00070000 // WT0CCP0 on PG4
+#define GPIO_PCTL_PG4_USB0EPEN 0x00080000 // USB0EPEN on PG4
+#define GPIO_PCTL_PG3_M 0x0000F000 // PG3 mask
+#define GPIO_PCTL_PG3_I2C4SDA 0x00003000 // I2C4SDA on PG3
+#define GPIO_PCTL_PG3_M0FAULT2 0x00004000 // M0FAULT2 on PG3
+#define GPIO_PCTL_PG3_M1PWM1 0x00005000 // M1PWM1 on PG3
+#define GPIO_PCTL_PG3_PHA1 0x00006000 // PHA1 on PG3
+#define GPIO_PCTL_PG3_T5CCP1 0x00007000 // T5CCP1 on PG3
+#define GPIO_PCTL_PG2_M 0x00000F00 // PG2 mask
+#define GPIO_PCTL_PG2_I2C4SCL 0x00000300 // I2C4SCL on PG2
+#define GPIO_PCTL_PG2_M0FAULT1 0x00000400 // M0FAULT1 on PG2
+#define GPIO_PCTL_PG2_M1PWM0 0x00000500 // M1PWM0 on PG2
+#define GPIO_PCTL_PG2_T5CCP0 0x00000700 // T5CCP0 on PG2
+#define GPIO_PCTL_PG1_M 0x000000F0 // PG1 mask
+#define GPIO_PCTL_PG1_I2C3SDA 0x00000030 // I2C3SDA on PG1
+#define GPIO_PCTL_PG1_M1FAULT2 0x00000050 // M1FAULT2 on PG1
+#define GPIO_PCTL_PG1_PHB1 0x00000060 // PHB1 on PG1
+#define GPIO_PCTL_PG1_T4CCP1 0x00000070 // T4CCP1 on PG1
+#define GPIO_PCTL_PG0_M 0x0000000F // PG0 mask
+#define GPIO_PCTL_PG0_I2C3SCL 0x00000003 // I2C3SCL on PG0
+#define GPIO_PCTL_PG0_M1FAULT1 0x00000005 // M1FAULT1 on PG0
+#define GPIO_PCTL_PG0_PHA1 0x00000006 // PHA1 on PG0
+#define GPIO_PCTL_PG0_T4CCP0 0x00000007 // T4CCP0 on PG0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port H.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PH7_M 0xF0000000 // PH7 mask
+#define GPIO_PCTL_PH7_SSI2TX 0x20000000 // SSI2TX on PH7
+#define GPIO_PCTL_PH7_M0PWM7 0x40000000 // M0PWM7 on PH7
+#define GPIO_PCTL_PH7_WT4CCP1 0x70000000 // WT4CCP1 on PH7
+#define GPIO_PCTL_PH6_M 0x0F000000 // PH6 mask
+#define GPIO_PCTL_PH6_SSI2RX 0x02000000 // SSI2RX on PH6
+#define GPIO_PCTL_PH6_M0PWM6 0x04000000 // M0PWM6 on PH6
+#define GPIO_PCTL_PH6_WT4CCP0 0x07000000 // WT4CCP0 on PH6
+#define GPIO_PCTL_PH5_M 0x00F00000 // PH5 mask
+#define GPIO_PCTL_PH5_SSI2FSS 0x00200000 // SSI2FSS on PH5
+#define GPIO_PCTL_PH5_M0PWM5 0x00400000 // M0PWM5 on PH5
+#define GPIO_PCTL_PH5_PHB0 0x00500000 // PHB0 on PH5
+#define GPIO_PCTL_PH5_WT3CCP1 0x00700000 // WT3CCP1 on PH5
+#define GPIO_PCTL_PH4_M 0x000F0000 // PH4 mask
+#define GPIO_PCTL_PH4_SSI2CLK 0x00020000 // SSI2CLK on PH4
+#define GPIO_PCTL_PH4_M0PWM4 0x00040000 // M0PWM4 on PH4
+#define GPIO_PCTL_PH4_PHA0 0x00050000 // PHA0 on PH4
+#define GPIO_PCTL_PH4_WT3CCP0 0x00070000 // WT3CCP0 on PH4
+#define GPIO_PCTL_PH3_M 0x0000F000 // PH3 mask
+#define GPIO_PCTL_PH3_SSI3TX 0x00002000 // SSI3TX on PH3
+#define GPIO_PCTL_PH3_M0PWM3 0x00004000 // M0PWM3 on PH3
+#define GPIO_PCTL_PH3_M0FAULT3 0x00006000 // M0FAULT3 on PH3
+#define GPIO_PCTL_PH3_WT5CCP1 0x00007000 // WT5CCP1 on PH3
+#define GPIO_PCTL_PH2_M 0x00000F00 // PH2 mask
+#define GPIO_PCTL_PH2_SSI3RX 0x00000200 // SSI3RX on PH2
+#define GPIO_PCTL_PH2_M0PWM2 0x00000400 // M0PWM2 on PH2
+#define GPIO_PCTL_PH2_M0FAULT2 0x00000600 // M0FAULT2 on PH2
+#define GPIO_PCTL_PH2_WT5CCP0 0x00000700 // WT5CCP0 on PH2
+#define GPIO_PCTL_PH1_M 0x000000F0 // PH1 mask
+#define GPIO_PCTL_PH1_SSI3FSS 0x00000020 // SSI3FSS on PH1
+#define GPIO_PCTL_PH1_M0PWM1 0x00000040 // M0PWM1 on PH1
+#define GPIO_PCTL_PH1_IDX0 0x00000050 // IDX0 on PH1
+#define GPIO_PCTL_PH1_M0FAULT1 0x00000060 // M0FAULT1 on PH1
+#define GPIO_PCTL_PH1_WT2CCP1 0x00000070 // WT2CCP1 on PH1
+#define GPIO_PCTL_PH0_M 0x0000000F // PH0 mask
+#define GPIO_PCTL_PH0_SSI3CLK 0x00000002 // SSI3CLK on PH0
+#define GPIO_PCTL_PH0_M0PWM0 0x00000004 // M0PWM0 on PH0
+#define GPIO_PCTL_PH0_M0FAULT0 0x00000006 // M0FAULT0 on PH0
+#define GPIO_PCTL_PH0_WT2CCP0 0x00000007 // WT2CCP0 on PH0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port J.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PJ7_M 0xF0000000 // PJ7 mask
+#define GPIO_PCTL_PJ6_M 0x0F000000 // PJ6 mask
+#define GPIO_PCTL_PJ5_M 0x00F00000 // PJ5 mask
+#define GPIO_PCTL_PJ5_C2M 0x00000000 // C2- on PJ5
+#define GPIO_PCTL_PJ5_U6TX 0x00100000 // U6TX on PJ5
+#define GPIO_PCTL_PJ5_T3CCP1 0x00700000 // T3CCP1 on PJ5
+#define GPIO_PCTL_PJ4_M 0x000F0000 // PJ4 mask
+#define GPIO_PCTL_PJ4_C2P 0x00000000 // C2+ on PJ4
+#define GPIO_PCTL_PJ4_U6RX 0x00010000 // U6RX on PJ4
+#define GPIO_PCTL_PJ4_T3CCP0 0x00070000 // T3CCP0 on PJ4
+#define GPIO_PCTL_PJ3_M 0x0000F000 // PJ3 mask
+#define GPIO_PCTL_PJ3_U5TX 0x00001000 // U5TX on PJ3
+#define GPIO_PCTL_PJ3_T2CCP1 0x00007000 // T2CCP1 on PJ3
+#define GPIO_PCTL_PJ2_M 0x00000F00 // PJ2 mask
+#define GPIO_PCTL_PJ2_U5RX 0x00000100 // U5RX on PJ2
+#define GPIO_PCTL_PJ2_IDX0 0x00000500 // IDX0 on PJ2
+#define GPIO_PCTL_PJ2_T2CCP0 0x00000700 // T2CCP0 on PJ2
+#define GPIO_PCTL_PJ1_M 0x000000F0 // PJ1 mask
+#define GPIO_PCTL_PJ1_U4TX 0x00000010 // U4TX on PJ1
+#define GPIO_PCTL_PJ1_T1CCP1 0x00000070 // T1CCP1 on PJ1
+#define GPIO_PCTL_PJ0_M 0x0000000F // PJ0 mask
+#define GPIO_PCTL_PJ0_U4RX 0x00000001 // U4RX on PJ0
+#define GPIO_PCTL_PJ0_T1CCP0 0x00000007 // T1CCP0 on PJ0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port K.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PK7_M 0xF0000000 // PK7 Mask
+#define GPIO_PCTL_PK7_M0FAULT3 0x60000000 // M0FAULT3 on PK7
+#define GPIO_PCTL_PK7_WT1CCP1 0x70000000 // WT1CCP1 on PK7
+#define GPIO_PCTL_PK6_M 0x0F000000 // PK6 Mask
+#define GPIO_PCTL_PK6_M0FAULT2 0x06000000 // M0FAULT2 on PK6
+#define GPIO_PCTL_PK6_WT1CCP0 0x07000000 // WT1CCP0 on PK6
+#define GPIO_PCTL_PK6_C2O 0x08000000 // C2O on PK6
+#define GPIO_PCTL_PK5_M 0x00F00000 // PK5 Mask
+#define GPIO_PCTL_PK5_U7TX 0x00100000 // U7TX on PK5
+#define GPIO_PCTL_PK5_M0FAULT1 0x00600000 // M0FAULT1 on PK5
+#define GPIO_PCTL_PK5_C1O 0x00800000 // C1O on PK5
+#define GPIO_PCTL_PK4_M 0x000F0000 // PK4 Mask
+#define GPIO_PCTL_PK4_U7RX 0x00010000 // U7RX on PK4
+#define GPIO_PCTL_PK4_M0FAULT0 0x00060000 // M0FAULT0 on PK4
+#define GPIO_PCTL_PK4_RTCCLK 0x00070000 // RTCCLK on PK4
+#define GPIO_PCTL_PK4_C0O 0x00080000 // C0O on PK4
+#define GPIO_PCTL_PK3_M 0x0000F000 // PK3 Mask
+#define GPIO_PCTL_PK3_AIN19 0x00000000 // AIN19 on PK3
+#define GPIO_PCTL_PK3_SSI3TX 0x00002000 // SSI3TX on PK3
+#define GPIO_PCTL_PK3_M1FAULT3 0x00006000 // M1FAULT3 on PK3
+#define GPIO_PCTL_PK2_M 0x00000F00 // PK2 Mask
+#define GPIO_PCTL_PK2_AIN18 0x00000000 // AIN18 on PK2
+#define GPIO_PCTL_PK2_SSI3RX 0x00000200 // SSI3RX on PK2
+#define GPIO_PCTL_PK2_M1FAULT2 0x00000600 // M1FAULT2 on PK2
+#define GPIO_PCTL_PK1_M 0x000000F0 // PK1 Mask
+#define GPIO_PCTL_PK1_AIN17 0x00000000 // AIN17 on PK1
+#define GPIO_PCTL_PK1_SSI3FSS 0x00000020 // SSI3FSS on PK1
+#define GPIO_PCTL_PK1_M1FAULT1 0x00000060 // M1FAULT1 on PK1
+#define GPIO_PCTL_PK0_M 0x0000000F // PK0 Mask
+#define GPIO_PCTL_PK0_AIN16 0x00000000 // AIN16 on PK0
+#define GPIO_PCTL_PK0_SSI3CLK 0x00000002 // SSI3CLK on PK0
+#define GPIO_PCTL_PK0_M1FAULT0 0x00000006 // M1FAULT0 on PK0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port L.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PL7_M 0xF0000000 // PL7 Mask
+#define GPIO_PCTL_PL7_USB0DM 0x00000000 // USB0DM on PL7
+#define GPIO_PCTL_PL7_T3CCP1 0x70000000 // T3CCP1 on PL7
+#define GPIO_PCTL_PL7_WT3CCP1 0x80000000 // WT3CCP1 on PL7
+#define GPIO_PCTL_PL6_M 0x0F000000 // PL6 Mask
+#define GPIO_PCTL_PL6_USB0DP 0x00000000 // USB0DP on PL6
+#define GPIO_PCTL_PL6_T3CCP0 0x07000000 // T3CCP0 on PL6
+#define GPIO_PCTL_PL6_WT3CCP0 0x08000000 // WT3CCP0 on PL6
+#define GPIO_PCTL_PL5_M 0x00F00000 // PL5 Mask
+#define GPIO_PCTL_PL5_T2CCP1 0x00700000 // T2CCP1 on PL5
+#define GPIO_PCTL_PL5_WT2CCP1 0x00800000 // WT2CCP1 on PL5
+#define GPIO_PCTL_PL4_M 0x000F0000 // PL4 Mask
+#define GPIO_PCTL_PL4_T2CCP0 0x00070000 // T2CCP0 on PL4
+#define GPIO_PCTL_PL4_WT2CCP0 0x00080000 // WT2CCP0 on PL4
+#define GPIO_PCTL_PL3_M 0x0000F000 // PL3 Mask
+#define GPIO_PCTL_PL3_T1CCP1 0x00007000 // T1CCP1 on PL3
+#define GPIO_PCTL_PL3_WT1CCP1 0x00008000 // WT1CCP1 on PL3
+#define GPIO_PCTL_PL2_M 0x00000F00 // PL2 Mask
+#define GPIO_PCTL_PL2_T1CCP0 0x00000700 // T1CCP0 on PL2
+#define GPIO_PCTL_PL2_WT1CCP0 0x00000800 // WT1CCP0 on PL2
+#define GPIO_PCTL_PL1_M 0x000000F0 // PL1 Mask
+#define GPIO_PCTL_PL1_T0CCP1 0x00000070 // T0CCP1 on PL1
+#define GPIO_PCTL_PL1_WT0CCP1 0x00000080 // WT0CCP1 on PL1
+#define GPIO_PCTL_PL0_M 0x0000000F // PL0 Mask
+#define GPIO_PCTL_PL0_T0CCP0 0x00000007 // T0CCP0 on PL0
+#define GPIO_PCTL_PL0_WT0CCP0 0x00000008 // WT0CCP0 on PL0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port M.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PM7_M 0xF0000000 // PM7 Mask
+#define GPIO_PCTL_PM7_M0PWM5 0x20000000 // M0PWM5 on PM7
+#define GPIO_PCTL_PM7_WT0CCP1 0x70000000 // WT0CCP1 on PM7
+#define GPIO_PCTL_PM6_M 0x0F000000 // PM6 Mask
+#define GPIO_PCTL_PM6_M0PWM4 0x02000000 // M0PWM4 on PM6
+#define GPIO_PCTL_PM6_WT0CCP0 0x07000000 // WT0CCP0 on PM6
+#define GPIO_PCTL_PM5_M 0x00F00000 // PM5 Mask
+#define GPIO_PCTL_PM4_M 0x000F0000 // PM4 Mask
+#define GPIO_PCTL_PM3_M 0x0000F000 // PM3 Mask
+#define GPIO_PCTL_PM3_T5CCP1 0x00007000 // T5CCP1 on PM3
+#define GPIO_PCTL_PM3_WT5CCP1 0x00008000 // WT5CCP1 on PM3
+#define GPIO_PCTL_PM2_M 0x00000F00 // PM2 Mask
+#define GPIO_PCTL_PM2_T5CCP0 0x00000700 // T5CCP0 on PM2
+#define GPIO_PCTL_PM2_WT5CCP0 0x00000800 // WT5CCP0 on PM2
+#define GPIO_PCTL_PM1_M 0x000000F0 // PM1 Mask
+#define GPIO_PCTL_PM1_T4CCP1 0x00000070 // T4CCP1 on PM1
+#define GPIO_PCTL_PM1_WT4CCP1 0x00000080 // WT4CCP1 on PM1
+#define GPIO_PCTL_PM0_M 0x0000000F // PM0 Mask
+#define GPIO_PCTL_PM0_T4CCP0 0x00000007 // T4CCP0 on PM0
+#define GPIO_PCTL_PM0_WT4CCP0 0x00000008 // WT4CCP0 on PM0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port N.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PN7_M 0xF0000000 // PN7 Mask
+#define GPIO_PCTL_PN7_M1PWM7 0x20000000 // M1PWM7 on PN7
+#define GPIO_PCTL_PN7_WT4CCP1 0x70000000 // WT4CCP1 on PN7
+#define GPIO_PCTL_PN6_M 0x0F000000 // PN6 Mask
+#define GPIO_PCTL_PN6_M1PWM6 0x02000000 // M1PWM6 on PN6
+#define GPIO_PCTL_PN6_WT4CCP0 0x07000000 // WT4CCP0 on PN6
+#define GPIO_PCTL_PN5_M 0x00F00000 // PN5 Mask
+#define GPIO_PCTL_PN5_M1PWM5 0x00200000 // M1PWM5 on PN5
+#define GPIO_PCTL_PN5_WT3CCP1 0x00700000 // WT3CCP1 on PN5
+#define GPIO_PCTL_PN4_M 0x000F0000 // PN4 Mask
+#define GPIO_PCTL_PN4_M1PWM4 0x00020000 // M1PWM4 on PN4
+#define GPIO_PCTL_PN4_WT3CCP0 0x00070000 // WT3CCP0 on PN4
+#define GPIO_PCTL_PN3_M 0x0000F000 // PN3 Mask
+#define GPIO_PCTL_PN3_M0PWM7 0x00002000 // M0PWM7 on PN3
+#define GPIO_PCTL_PN3_WT2CCP1 0x00007000 // WT2CCP1 on PN3
+#define GPIO_PCTL_PN2_M 0x00000F00 // PN2 Mask
+#define GPIO_PCTL_PN2_M0PWM6 0x00000200 // M0PWM6 on PN2
+#define GPIO_PCTL_PN2_WT2CCP0 0x00000700 // WT2CCP0 on PN2
+#define GPIO_PCTL_PN1_M 0x000000F0 // PN1 Mask
+#define GPIO_PCTL_PN1_CAN0TX 0x00000010 // CAN0TX on PN1
+#define GPIO_PCTL_PN0_M 0x0000000F // PN0 Mask
+#define GPIO_PCTL_PN0_CAN0RX 0x00000001 // CAN0RX on PN0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port P.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PP2_M 0x00000F00 // PP2 Mask
+#define GPIO_PCTL_PP2_M0PWM2 0x00000100 // M0PWM2 on PP2
+#define GPIO_PCTL_PP2_T5CCP0 0x00000700 // T5CCP0 on PP2
+#define GPIO_PCTL_PP1_M 0x000000F0 // PP1 Mask
+#define GPIO_PCTL_PP1_AIN22 0x00000000 // AIN22 on PP1
+#define GPIO_PCTL_PP1_M0PWM1 0x00000010 // M0PWM1 on PP1
+#define GPIO_PCTL_PP1_T4CCP1 0x00000070 // T4CCP1 on PP1
+#define GPIO_PCTL_PP0_M 0x0000000F // PP0 Mask
+#define GPIO_PCTL_PP0_AIN23 0x00000000 // AIN23 on PP0
+#define GPIO_PCTL_PP0_M0PWM0 0x00000001 // M0PWM0 on PP0
+#define GPIO_PCTL_PP0_T4CCP0 0x00000007 // T4CCP0 on PP0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
+#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
+#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
+ // Serial Frame Format
+#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
+#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
+#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
+#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
+#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
+#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
+#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
+#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
+#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
+#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
+#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
+#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
+#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
+#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
+#define SSI_CR0_SCR_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_EOT 0x00000010 // End of Transmission
+#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
+#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
+#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
+ // Enable
+#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
+#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
+#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
+ // Mask
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
+ // Interrupt Status
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
+ // Interrupt Status
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
+ // Clear
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CC register.
+//
+//*****************************************************************************
+#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
+#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
+ // PLL bypass is in effect) or the
+ // PLL output (default)
+#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE 0x00000800 // UART Overrun Error
+#define UART_DR_BE 0x00000400 // UART Break Error
+#define UART_DR_PE 0x00000200 // UART Parity Error
+#define UART_DR_FE 0x00000100 // UART Framing Error
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE 0x00000008 // UART Overrun Error
+#define UART_RSR_BE 0x00000004 // UART Break Error
+#define UART_RSR_PE 0x00000002 // UART Parity Error
+#define UART_RSR_FE 0x00000001 // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear
+#define UART_ECR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_RI 0x00000100 // Ring Indicator
+#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
+#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
+#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
+#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
+#define UART_FR_BUSY 0x00000008 // UART Busy
+#define UART_FR_DCD 0x00000004 // Data Carrier Detect
+#define UART_FR_DSR 0x00000002 // Data Set Ready
+#define UART_FR_CTS 0x00000001 // Clear To Send
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
+#define UART_LCRH_BRK 0x00000001 // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
+#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
+#define UART_CTL_RTS 0x00000800 // Request to Send
+#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
+#define UART_CTL_RXE 0x00000200 // UART Receive Enable
+#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
+#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
+#define UART_CTL_HSE 0x00000020 // High-Speed Enable
+#define UART_CTL_EOT 0x00000010 // End of Transmission
+#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
+#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
+#define UART_CTL_UARTEN 0x00000001 // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
+ // Level Select
+#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
+ // Level Select
+#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
+#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
+ // Mask
+#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
+#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
+ // Mask
+#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
+ // Mask
+#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
+#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
+#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Mask
+#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Mask
+#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
+ // Interrupt Mask
+#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
+#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
+ // Status
+#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
+ // Status
+#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
+ // Status
+#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
+ // Status
+#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
+ // Interrupt Status
+#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
+ // Status
+#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
+ // Status
+#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
+ // Interrupt Status
+#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
+ // Raw Interrupt Status
+#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
+ // Interrupt Status
+#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
+ // Status
+#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
+ // Interrupt Status
+#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
+ // Interrupt Status
+#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
+ // Interrupt Status
+#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
+ // Interrupt Status
+#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
+ // Interrupt Status
+#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
+ // Status
+#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
+ // Status
+#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
+ // Interrupt Status
+#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
+ // Masked Interrupt Status
+#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
+ // Interrupt Status
+#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
+#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
+#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Clear
+#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Clear
+#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
+ // Interrupt Clear
+#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
+#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITADDR
+// register.
+//
+//*****************************************************************************
+#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
+#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
+#define UART_9BITADDR_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITAMASK
+// register.
+//
+//*****************************************************************************
+#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
+#define UART_9BITAMASK_MASK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_PP register.
+//
+//*****************************************************************************
+#define UART_PP_NB 0x00000002 // 9-Bit Support
+#define UART_PP_SC 0x00000001 // Smart Card Support
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CC register.
+//
+//*****************************************************************************
+#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
+#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default)
+#define UART_CC_CS_PIOSC 0x00000005 // PIOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
+#define I2C_MSA_RS 0x00000001 // Receive not send
+#define I2C_MSA_SA_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
+#define I2C_MCS_HS 0x00000010 // High-Speed Enable
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
+#define I2C_MCS_STOP 0x00000004 // Generate STOP
+#define I2C_MCS_ERROR 0x00000002 // Error
+#define I2C_MCS_START 0x00000002 // Generate START
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
+#define I2C_MTPR_TPR_M 0x0000007F // Timer Period
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
+#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
+ // Status
+#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
+ // Status
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
+#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
+//
+//*****************************************************************************
+#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
+#define I2C_MCLKOCNT_CNTL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBMON register.
+//
+//*****************************************************************************
+#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
+#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR2 register.
+//
+//*****************************************************************************
+#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width
+#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass
+#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock
+#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks
+#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks
+#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks
+#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks
+#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks
+#define I2C_MCR2_GFPW_32 0x00000070 // 32 clocks
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
+#define I2C_SCSR_DA 0x00000001 // Device Active
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR2 register.
+//
+//*****************************************************************************
+#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
+#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
+#define I2C_SOAR2_OAR2_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SACKCTL register.
+//
+//*****************************************************************************
+#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
+#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PP register.
+//
+//*****************************************************************************
+#define I2C_PP_HS 0x00000001 // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PC register.
+//
+//*****************************************************************************
+#define I2C_PC_HS 0x00000001 // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 Output Enable
+#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 Output Enable
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV 0x00000080 // Invert PWM7 Signal
+#define PWM_INVERT_PWM6INV 0x00000040 // Invert PWM6 Signal
+#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal
+#define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal
+#define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal
+#define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal
+#define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal
+#define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7 0x00000080 // PWM7 Fault
+#define PWM_FAULT_FAULT6 0x00000040 // PWM6 Fault
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault
+#define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault
+#define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault
+#define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault
+#define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault
+#define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3
+#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2
+#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3
+#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2
+#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0
+#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted
+#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted
+#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status
+#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status
+#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value
+#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value
+#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value
+#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value
+#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value
+#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value
+#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value
+#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
+//
+//*****************************************************************************
+#define PWM_ENUPD_ENUPD7_M 0x0000C000 // PWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M 0x00003000 // PWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M 0x00000C00 // PWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M 0x00000300 // PWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M 0x000000C0 // PWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M 0x00000030 // PWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M 0x0000000C // PWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M 0x00000003 // PWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CTL register.
+//
+//*****************************************************************************
+#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register
+#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_0_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_INTEN register.
+//
+//*****************************************************************************
+#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down
+#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up
+#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down
+#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up
+#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
+#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down
+#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up
+#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down
+#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up
+#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
+#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_RIS register.
+//
+//*****************************************************************************
+#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_ISC register.
+//
+//*****************************************************************************
+#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_LOAD register.
+//
+//*****************************************************************************
+#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_0_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_COUNT register.
+//
+//*****************************************************************************
+#define PWM_0_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_0_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPA register.
+//
+//*****************************************************************************
+#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_0_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPB register.
+//
+//*****************************************************************************
+#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_0_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENA register.
+//
+//*****************************************************************************
+#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_0_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_0_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_0_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_0_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_0_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_0_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_0_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_0_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENB register.
+//
+//*****************************************************************************
+#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_0_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_0_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_0_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_0_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_0_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_0_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_0_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_0_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
+#define PWM_0_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
+#define PWM_0_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
+#define PWM_0_MINFLTPER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CTL register.
+//
+//*****************************************************************************
+#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register
+#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_1_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_INTEN register.
+//
+//*****************************************************************************
+#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down
+#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up
+#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down
+#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up
+#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
+#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down
+#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up
+#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down
+#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up
+#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
+#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_RIS register.
+//
+//*****************************************************************************
+#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_ISC register.
+//
+//*****************************************************************************
+#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_LOAD register.
+//
+//*****************************************************************************
+#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_1_LOAD_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_COUNT register.
+//
+//*****************************************************************************
+#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_1_COUNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPA register.
+//
+//*****************************************************************************
+#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_1_CMPA_COMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPB register.
+//
+//*****************************************************************************
+#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_1_CMPB_COMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENA register.
+//
+//*****************************************************************************
+#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_1_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_1_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_1_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_1_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_1_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_1_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_1_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_1_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENB register.
+//
+//*****************************************************************************
+#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_1_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_1_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_1_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_1_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_1_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_1_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_1_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_1_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_1_DBRISE_RISEDELAY_M \
+ 0x00000FFF // Dead-Band Rise Delay
+#define PWM_1_DBRISE_RISEDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_1_DBFALL_FALLDELAY_M \
+ 0x00000FFF // Dead-Band Fall Delay
+#define PWM_1_DBFALL_FALLDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
+#define PWM_1_MINFLTPER_MFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CTL register.
+//
+//*****************************************************************************
+#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register
+#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_2_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_INTEN register.
+//
+//*****************************************************************************
+#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down
+#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up
+#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down
+#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up
+#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
+#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down
+#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up
+#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down
+#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up
+#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
+#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_RIS register.
+//
+//*****************************************************************************
+#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_ISC register.
+//
+//*****************************************************************************
+#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_LOAD register.
+//
+//*****************************************************************************
+#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_2_LOAD_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_COUNT register.
+//
+//*****************************************************************************
+#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_2_COUNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPA register.
+//
+//*****************************************************************************
+#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_2_CMPA_COMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPB register.
+//
+//*****************************************************************************
+#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_2_CMPB_COMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENA register.
+//
+//*****************************************************************************
+#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_2_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_2_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_2_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_2_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_2_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_2_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_2_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_2_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENB register.
+//
+//*****************************************************************************
+#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_2_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_2_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_2_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_2_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_2_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_2_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_2_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_2_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_2_DBRISE_RISEDELAY_M \
+ 0x00000FFF // Dead-Band Rise Delay
+#define PWM_2_DBRISE_RISEDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_2_DBFALL_FALLDELAY_M \
+ 0x00000FFF // Dead-Band Fall Delay
+#define PWM_2_DBFALL_FALLDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
+#define PWM_2_MINFLTPER_MFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CTL register.
+//
+//*****************************************************************************
+#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register
+#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_3_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_INTEN register.
+//
+//*****************************************************************************
+#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down
+#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up
+#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down
+#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up
+#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
+#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down
+#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up
+#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down
+#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up
+#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
+#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_RIS register.
+//
+//*****************************************************************************
+#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_ISC register.
+//
+//*****************************************************************************
+#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_LOAD register.
+//
+//*****************************************************************************
+#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_3_LOAD_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_COUNT register.
+//
+//*****************************************************************************
+#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_3_COUNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPA register.
+//
+//*****************************************************************************
+#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_3_CMPA_COMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPB register.
+//
+//*****************************************************************************
+#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_3_CMPB_COMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENA register.
+//
+//*****************************************************************************
+#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_3_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_3_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_3_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_3_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_3_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_3_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_3_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_3_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENB register.
+//
+//*****************************************************************************
+#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_3_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_3_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_3_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_3_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_3_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_3_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_3_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_3_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_3_DBRISE_RISEDELAY_M \
+ 0x00000FFF // Dead-Band Rise Delay
+#define PWM_3_DBRISE_RISEDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_3_DBFALL_FALLDELAY_M \
+ 0x00000FFF // Dead-Band Fall Delay
+#define PWM_3_DBFALL_FALLDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2
+#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1
+#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
+#define PWM_3_MINFLTPER_MFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_PP register.
+//
+//*****************************************************************************
+#define PWM_PP_ONE 0x00000400 // One-Shot Mode
+#define PWM_PP_EFAULT 0x00000200 // Extended Fault
+#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization
+#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs
+#define PWM_PP_GCNT_M 0x0000000F // Generators
+#define PWM_PP_FCNT_S 4
+#define PWM_PP_GCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count
+#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter
+#define QEI_CTL_STALLEN 0x00001000 // Stall QEI
+#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse
+#define QEI_CTL_INVB 0x00000400 // Invert PhB
+#define QEI_CTL_INVA 0x00000200 // Invert PhA
+#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity
+#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1
+#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2
+#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4
+#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8
+#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16
+#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32
+#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64
+#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128
+#define QEI_CTL_VELEN 0x00000020 // Capture Velocity
+#define QEI_CTL_RESMODE 0x00000010 // Reset Mode
+#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode
+#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode
+#define QEI_CTL_SWAP 0x00000002 // Swap Signals
+#define QEI_CTL_ENABLE 0x00000001 // Enable QEI
+#define QEI_CTL_FILTCNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation
+#define QEI_STAT_ERROR 0x00000001 // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
+ // Value
+#define QEI_POS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
+ // Value
+#define QEI_MAXPOS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value
+#define QEI_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value
+#define QEI_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count
+#define QEI_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M 0xFFFFFFFF // Velocity
+#define QEI_SPEED_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
+ // Enable
+#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected
+#define QEI_RIS_DIR 0x00000004 // Direction Change Detected
+#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired
+#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt
+#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt
+#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
+ // counter configuration
+#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
+ // function is controlled by bits
+ // 1:0 of GPTMTAMR and GPTMTBMR
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
+ // Operation
+#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
+ // Update
+#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
+ // Enable
+#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
+#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
+ // Enable
+#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
+ // Select
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
+ // Operation
+#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
+ // Update
+#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
+ // Enable
+#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
+#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
+ // Enable
+#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
+ // Select
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
+ // Enable
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
+#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
+ // Enable
+#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
+#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_SYNC register.
+//
+//*****************************************************************************
+#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer
+ // 5
+#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not
+ // affected
+#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 5 is triggered
+#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer
+ // 4
+#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not
+ // affected
+#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 4 is triggered
+#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer
+ // 3
+#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not
+ // affected
+#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 3 is triggered
+#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer
+ // 2
+#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not
+ // affected
+#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 2 is triggered
+#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer
+ // 1
+#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not
+ // affected
+#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 1 is triggered
+#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer
+ // 0
+#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not
+ // affected
+#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 0 is triggered
+#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer
+ // 5
+#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not
+ // affected
+#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 5 is triggered
+#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer
+ // 4
+#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not
+ // affected
+#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 4 is triggered
+#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer
+ // 3
+#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not
+ // affected
+#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 3 is triggered
+#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer
+ // 2
+#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not
+ // affected
+#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 2 is triggered
+#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer
+ // 1
+#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not
+ // affected
+#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 1 is triggered
+#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer
+ // 0
+#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not
+ // affected
+#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 0 is triggered
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_WUEIM 0x00010000 // GPTM Write Update Error
+ // Interrupt Mask
+#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt
+ // Mask
+#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event
+ // Interrupt Mask
+#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Mask
+#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt
+ // Mask
+#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event
+ // Interrupt Mask
+#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_WUERIS 0x00010000 // GPTM Write Update Error Raw
+ // Interrupt
+#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt
+#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event
+ // Raw Interrupt
+#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match
+ // Raw Interrupt
+#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
+ // Interrupt
+#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt
+#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event
+ // Raw Interrupt
+#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match
+ // Raw Interrupt
+#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_WUEMIS 0x00010000 // GPTM Write Update Error Masked
+ // Interrupt
+#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked
+ // Interrupt
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event
+ // Masked Interrupt
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match
+ // Masked Interrupt
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
+ // Interrupt
+#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked
+ // Interrupt
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event
+ // Masked Interrupt
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match
+ // Masked Interrupt
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update
+ // Error Interrupt Clear
+#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt
+ // Clear
+#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event
+ // Interrupt Clear
+#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Clear
+#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt
+ // Clear
+#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event
+ // Interrupt Clear
+#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
+ // Register
+#define TIMER_TAILR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
+ // Register
+#define TIMER_TBILR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
+#define TIMER_TAMATCHR_TAMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
+#define TIMER_TBMATCHR_TBMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSRH_S 8
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSRH_S 8
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
+ // Byte
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMRH_S 8
+#define TIMER_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
+ // Byte
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMRH_S 8
+#define TIMER_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
+#define TIMER_TAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
+#define TIMER_TBR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
+#define TIMER_TAV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
+#define TIMER_TBV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RTCPD register.
+//
+//*****************************************************************************
+#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
+#define TIMER_RTCPD_RTCPD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPS register.
+//
+//*****************************************************************************
+#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
+#define TIMER_TAPS_PSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPS register.
+//
+//*****************************************************************************
+#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
+#define TIMER_TBPS_PSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPV register.
+//
+//*****************************************************************************
+#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
+#define TIMER_TAPV_PSV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPV register.
+//
+//*****************************************************************************
+#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
+#define TIMER_TBPV_PSV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_PP register.
+//
+//*****************************************************************************
+#define TIMER_PP_SIZE_M 0x0000000F // Count Size
+#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
+ // 16 bits each with an 8-bit
+ // prescale counter
+#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
+ // 32 bits each with a 16-bit
+ // prescale counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_BUSY 0x00010000 // ADC Busy
+#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt
+ // Status
+#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on
+ // SS3
+#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on
+ // SS2
+#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on
+ // SS1
+#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on
+ // SS0
+#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask
+#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask
+#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask
+#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt
+ // Status on SS3
+#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt
+ // Status on SS2
+#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt
+ // Status on SS1
+#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt
+ // Status on SS0
+#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2
+#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM3
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
+#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2
+#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM3
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
+#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2
+#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM3
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
+#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2
+#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM3
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow
+#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow
+#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow
+#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TSSEL register.
+//
+//*****************************************************************************
+#define ADC_TSSEL_PS3_M 0x30000000 // PWM Unit Select
+#define ADC_TSSEL_PS3_0 0x00000000 // PWM Unit 0
+#define ADC_TSSEL_PS3_1 0x10000000 // PWM Unit 1
+#define ADC_TSSEL_PS2_M 0x00300000 // PWM Unit Select
+#define ADC_TSSEL_PS2_0 0x00000000 // PWM Unit 0
+#define ADC_TSSEL_PS2_1 0x00100000 // PWM Unit 1
+#define ADC_TSSEL_PS1_M 0x00003000 // PWM Unit Select
+#define ADC_TSSEL_PS1_0 0x00000000 // PWM Unit 0
+#define ADC_TSSEL_PS1_1 0x00001000 // PWM Unit 1
+#define ADC_TSSEL_PS0_M 0x00000030 // PWM Unit Select
+#define ADC_TSSEL_PS0_0 0x00000000 // PWM Unit 0
+#define ADC_TSSEL_PS0_1 0x00000010 // PWM Unit 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority
+#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority
+#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority
+#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SPC register.
+//
+//*****************************************************************************
+#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference
+#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize
+#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait
+#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate
+#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate
+#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate
+#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt
+ // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CTL register.
+//
+//*****************************************************************************
+#define ADC_CTL_DITHER 0x00000040 // Dither Mode Enable
+#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select
+#define ADC_CTL_VREF_INTERNAL 0x00000000 // The internal reference as the
+ // voltage reference
+#define ADC_CTL_VREF_EXT_3V 0x00000001 // A 3.0 V external VREFA input is
+ // the voltage reference. The ADC
+ // conversion range is 0.0 V to the
+ // external reference value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S 28
+#define ADC_SSMUX0_MUX6_S 24
+#define ADC_SSMUX0_MUX5_S 20
+#define ADC_SSMUX0_MUX4_S 16
+#define ADC_SSMUX0_MUX3_S 12
+#define ADC_SSMUX0_MUX2_S 8
+#define ADC_SSMUX0_MUX1_S 4
+#define ADC_SSMUX0_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S 4
+#define ADC_SSFSTAT0_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator
+ // Select
+#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator
+ // Select
+#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator
+ // Select
+#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator
+ // Select
+#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC0_S6DCSEL_S 24
+#define ADC_SSDC0_S5DCSEL_S 20
+#define ADC_SSDC0_S4DCSEL_S 16
+#define ADC_SSDC0_S3DCSEL_S 12
+#define ADC_SSDC0_S2DCSEL_S 8
+#define ADC_SSDC0_S1DCSEL_S 4
+#define ADC_SSDC0_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S 12
+#define ADC_SSMUX1_MUX2_S 8
+#define ADC_SSMUX1_MUX1_S 4
+#define ADC_SSMUX1_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S 4
+#define ADC_SSFSTAT1_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC1_S2DCSEL_S 8
+#define ADC_SSDC1_S1DCSEL_S 4
+#define ADC_SSDC1_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S 12
+#define ADC_SSMUX2_MUX2_S 8
+#define ADC_SSMUX2_MUX1_S 4
+#define ADC_SSMUX2_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S 4
+#define ADC_SSFSTAT2_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC2_S2DCSEL_S 8
+#define ADC_SSDC2_S1DCSEL_S 4
+#define ADC_SSDC2_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S 4
+#define ADC_SSFSTAT3_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP0_COMP1_S 16
+#define ADC_DCCMP0_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP1_COMP1_S 16
+#define ADC_DCCMP1_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP2_COMP1_S 16
+#define ADC_DCCMP2_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP3_COMP1_S 16
+#define ADC_DCCMP3_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP4_COMP1_S 16
+#define ADC_DCCMP4_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP5_COMP1_S 16
+#define ADC_DCCMP5_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP6_COMP1_S 16
+#define ADC_DCCMP6_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP7_COMP1_S 16
+#define ADC_DCCMP7_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PP register.
+//
+//*****************************************************************************
+#define ADC_PP_TS 0x00800000 // Temperature Sensor
+#define ADC_PP_RSL_M 0x007C0000 // Resolution
+#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture
+#define ADC_PP_TYPE_SAR 0x00000000 // SAR
+#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count
+#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count
+#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate
+#define ADC_PP_MSR_125K 0x00000001 // 125 ksps
+#define ADC_PP_MSR_250K 0x00000003 // 250 ksps
+#define ADC_PP_MSR_500K 0x00000005 // 500 ksps
+#define ADC_PP_MSR_1M 0x00000007 // 1 Msps
+#define ADC_PP_RSL_S 18
+#define ADC_PP_DC_S 10
+#define ADC_PP_CH_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PC register.
+//
+//*****************************************************************************
+#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate
+#define ADC_PC_SR_125K 0x00000001 // 125 ksps
+#define ADC_PC_SR_250K 0x00000003 // 250 ksps
+#define ADC_PC_SR_500K 0x00000005 // 500 ksps
+#define ADC_PC_SR_1M 0x00000007 // 1 Msps
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CC register.
+//
+//*****************************************************************************
+#define ADC_CC_CS_M 0x0000000F // ADC Clock Source
+#define ADC_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
+ // PLL bypass is in effect) or the
+ // 16 MHz clock derived from PLL /
+ // 25 (default)
+#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
+ // Status
+#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
+ // Status
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status
+#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable
+#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_PP register.
+//
+//*****************************************************************************
+#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present
+#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present
+#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present
+#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present
+#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present
+#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
+#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
+#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
+#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
+#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
+#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable
+#define CAN_CTL_INIT 0x00000001 // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF 0x00000080 // Bus-Off Status
+#define CAN_STS_EWARN 0x00000040 // Warning Status
+#define CAN_STS_EPASS 0x00000020 // Error Passive
+#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully
+#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
+ // Successfully
+#define CAN_STS_LEC_M 0x00000007 // Last Error Code
+#define CAN_STS_LEC_NONE 0x00000000 // No Error
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
+#define CAN_STS_LEC_FORM 0x00000002 // Format Error
+#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
+#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
+#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP 0x00008000 // Received Error Passive
+#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter
+#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter
+#define CAN_ERR_REC_S 8
+#define CAN_ERR_TEC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler
+#define CAN_BIT_TSEG2_S 12
+#define CAN_BIT_TSEG1_S 8
+#define CAN_BIT_SJW_S 6
+#define CAN_BIT_BRP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier
+#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX 0x00000080 // Receive Observation
+#define CAN_TST_TX_M 0x00000060 // Transmit Control
+#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control
+#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point
+#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low
+#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High
+#define CAN_TST_LBACK 0x00000010 // Loopback Mode
+#define CAN_TST_SILENT 0x00000008 // Silent Mode
+#define CAN_TST_BASIC 0x00000004 // Basic Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension
+#define CAN_BRPE_BRPE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag
+#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number
+#define CAN_IF1CRQ_MNUM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read
+#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits
+#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data
+#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request
+#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
+#define CAN_IF1MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask
+#define CAN_IF1MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier
+#define CAN_IF1ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid
+#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier
+#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction
+#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier
+#define CAN_IF1ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data
+#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost
+#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending
+#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable
+#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request
+#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer
+#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code
+#define CAN_IF1MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag
+#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number
+#define CAN_IF2CRQ_MNUM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read
+#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits
+#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data
+#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request
+#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
+#define CAN_IF2MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask
+#define CAN_IF2MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier
+#define CAN_IF2ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid
+#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier
+#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction
+#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier
+#define CAN_IF2ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data
+#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost
+#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending
+#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable
+#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request
+#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer
+#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code
+#define CAN_IF2MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits
+#define CAN_NWDA1_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits
+#define CAN_NWDA2_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
+#define CAN_MSG1INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
+#define CAN_MSG2INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
+#define CAN_MSG1VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
+#define CAN_MSG2VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M 0x0000007F // Function Address
+#define USB_FADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP 0x00000080 // Isochronous Update
+#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect
+#define USB_POWER_RESET 0x00000008 // RESET Signaling
+#define USB_POWER_RESUME 0x00000004 // RESUME Signaling
+#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode
+#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable
+#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR 0x00000080 // VBUS Error
+#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST
+#define USB_IS_DISCON 0x00000020 // Session Disconnect
+#define USB_IS_CONN 0x00000010 // Session Connect
+#define USB_IS_SOF 0x00000008 // Start of Frame
+#define USB_IS_BABBLE 0x00000004 // Babble Detected
+#define USB_IS_RESET 0x00000004 // RESET Signaling Detected
+#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected
+#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt
+#define USB_IE_SESREQ 0x00000040 // Enable Session Request
+#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt
+#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt
+#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt
+#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt
+#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt
+#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M 0x000007FF // Frame Number
+#define USB_FRAME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index
+#define USB_EPIDX_EPIDX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH 0x00000080 // Force Host Mode
+#define USB_TEST_FIFOACC 0x00000040 // FIFO Access
+#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO0_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO1_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO2_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO3_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO4_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO5_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO6_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO7_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV 0x00000080 // Device Mode
+#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level
+#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid
+#define USB_DEVCTL_HOST 0x00000004 // Host Mode
+#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request
+#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
+#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
+#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait
+#define USB_CONTIM_WTID_M 0x0000000F // Wait ID
+#define USB_CONTIM_WTCON_S 4
+#define USB_CONTIM_WTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length
+#define USB_VPLEN_VPLEN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap
+#define USB_FSEOF_FSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap
+#define USB_LSEOF_LSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT0_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout
+#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear
+#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet
+#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear
+#define USB_CSRL0_REQPKT 0x00000020 // Request Packet
+#define USB_CSRL0_STALL 0x00000020 // Send Stall
+#define USB_CSRL0_SETEND 0x00000010 // Setup End
+#define USB_CSRL0_ERROR 0x00000010 // Error
+#define USB_CSRL0_DATAEND 0x00000008 // Data End
+#define USB_CSRL0_SETUP 0x00000008 // Setup Packet
+#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled
+#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready
+#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_CSRH0_DT 0x00000002 // Data Toggle
+#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count
+#define USB_COUNT0_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TYPE0_SPEED_FULL 0x00000080 // Full
+#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit
+#define USB_NAKLMT_NAKLMT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL1_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL1_ERROR 0x00000004 // Error
+#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH1_MODE 0x00000020 // Mode
+#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH1_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL1_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL1_OVER 0x00000004 // Overrun
+#define USB_RXCSRL1_ERROR 0x00000004 // Error
+#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH1_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT1_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL1_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL2_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL2_ERROR 0x00000004 // Error
+#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH2_MODE 0x00000020 // Mode
+#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH2_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL2_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL2_ERROR 0x00000004 // Error
+#define USB_RXCSRL2_OVER 0x00000004 // Overrun
+#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH2_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT2_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL2_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL2_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL2_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL2_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL3_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL3_ERROR 0x00000004 // Error
+#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH3_MODE 0x00000020 // Mode
+#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH3_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL3_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL3_ERROR 0x00000004 // Error
+#define USB_RXCSRL3_OVER 0x00000004 // Overrun
+#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH3_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT3_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL4_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL4_ERROR 0x00000004 // Error
+#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH4_MODE 0x00000020 // Mode
+#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH4_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL4_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL4_OVER 0x00000004 // Overrun
+#define USB_RXCSRL4_ERROR 0x00000004 // Error
+#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH4_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL5_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL5_ERROR 0x00000004 // Error
+#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH5_MODE 0x00000020 // Mode
+#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH5_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL5_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL5_ERROR 0x00000004 // Error
+#define USB_RXCSRL5_OVER 0x00000004 // Overrun
+#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH5_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL5_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL5_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL5_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL5_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL6_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL6_ERROR 0x00000004 // Error
+#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH6_MODE 0x00000020 // Mode
+#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH6_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL6_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL6_ERROR 0x00000004 // Error
+#define USB_RXCSRL6_OVER 0x00000004 // Overrun
+#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH6_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL6_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL6_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL6_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL6_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL7_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL7_ERROR 0x00000004 // Error
+#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH7_MODE 0x00000020 // Mode
+#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH7_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL7_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL7_ERROR 0x00000004 // Error
+#define USB_RXCSRL7_OVER 0x00000004 // Overrun
+#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH7_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT2_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT3_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
+ // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
+ // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action
+#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged
+#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate
+#define USB_EPC_PFLTACT_LOW 0x00000200 // Low
+#define USB_EPC_PFLTACT_HIGH 0x00000300 // High
+#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense
+#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable
+#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable
+#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable
+ // Configuration
+#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low
+#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode
+#define USB_GPCS_DEVMOD 0x00000001 // Device Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVRIS register.
+//
+//*****************************************************************************
+#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVIM register.
+//
+//*****************************************************************************
+#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVISC register.
+//
+//*****************************************************************************
+#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMASEL register.
+//
+//*****************************************************************************
+#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select
+#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select
+#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select
+#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select
+#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select
+#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select
+#define USB_DMASEL_DMACTX_S 20
+#define USB_DMASEL_DMACRX_S 16
+#define USB_DMASEL_DMABTX_S 12
+#define USB_DMASEL_DMABRX_S 8
+#define USB_DMASEL_DMAATX_S 4
+#define USB_DMASEL_DMAARX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PP register.
+//
+//*****************************************************************************
+#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count
+#define USB_PP_USB_M 0x000000C0 // USB Capability
+#define USB_PP_USB_DEVICE 0x00000040 // DEVICE
+#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST
+#define USB_PP_USB_OTG 0x000000C0 // OTG
+#define USB_PP_PHY 0x00000010 // PHY Present
+#define USB_PP_TYPE_M 0x0000000F // Controller Type
+#define USB_PP_TYPE_0 0x00000000 // The first-generation USB
+ // controller
+#define USB_PP_ECNT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESIZE register.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks
+#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words
+#define EEPROM_EESIZE_BLKCNT_S 16
+#define EEPROM_EESIZE_WORDCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
+//
+//*****************************************************************************
+#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block
+#define EEPROM_EEBLOCK_BLOCK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEOFFSET
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEOFFSET_OFFSET_M \
+ 0x0000000F // Current Address Offset
+#define EEPROM_EEOFFSET_OFFSET_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWR register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data
+#define EEPROM_EERDWR_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWRINC
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWRINC_VALUE_M \
+ 0xFFFFFFFF // EEPROM Read or Write Data with
+ // Increment
+#define EEPROM_EERDWRINC_VALUE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDONE register.
+//
+//*****************************************************************************
+#define EEPROM_EEDONE_INVPL 0x00000100 // Invalid Program Voltage Level
+#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy
+#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission
+#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy
+#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase
+#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESUPP register.
+//
+//*****************************************************************************
+#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried
+#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried
+#define EEPROM_EESUPP_EREQ 0x00000002 // Erase Required
+#define EEPROM_EESUPP_START 0x00000001 // Start Erase
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEUNLOCK
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEUNLOCK_UNLOCK_M \
+ 0xFFFFFFFF // EEPROM Unlock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPROT register.
+//
+//*****************************************************************************
+#define EEPROM_EEPROT_ACC 0x00000008 // Access Control
+#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control
+#define EEPROM_EEPROT_PROT_RWNPW \
+ 0x00000000 // This setting is the default. If
+ // there is no password, the block
+ // is not protected and is readable
+ // and writable
+#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the
+ // block is readable or writable
+ // only when unlocked
+#define EEPROM_EEPROT_PROT_RONPW \
+ 0x00000002 // If there is no password, the
+ // block is readable, not writable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS0_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS1_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS2_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEINT register.
+//
+//*****************************************************************************
+#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDBGME register.
+//
+//*****************************************************************************
+#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key
+#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase
+#define EEPROM_EEDBGME_KEY_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_PP register.
+//
+//*****************************************************************************
+#define EEPROM_PP_SIZE_M 0x0000001F // EEPROM Size
+#define EEPROM_PP_SIZE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_RIS register.
+//
+//*****************************************************************************
+#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception
+ // Raw Interrupt Status
+#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation
+ // Raw Interrupt Status
+#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal
+ // Exception Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IM register.
+//
+//*****************************************************************************
+#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception
+ // Interrupt Mask
+#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation
+ // Interrupt Mask
+#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal
+ // Exception Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_MIS register.
+//
+//*****************************************************************************
+#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception
+ // Masked Interrupt Status
+#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation
+ // Masked Interrupt Status
+#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal
+ // Exception Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IC register.
+//
+//*****************************************************************************
+#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception
+ // Interrupt Clear
+#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation
+ // Interrupt Clear
+#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal
+ // Exception Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
+#define HIB_RTCC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
+#define HIB_RTCM0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
+#define HIB_RTCLD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
+#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
+#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
+#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
+ // Comparator
+#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
+#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
+#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
+#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
+#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
+#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
+#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
+#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
+#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
+#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
+#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
+#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
+ // Interrupt Mask
+#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
+ // Mask
+#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
+ // Interrupt Status
+#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
+ // Status
+#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
+ // Interrupt Status
+#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
+ // Interrupt Status
+#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Status
+#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Status
+#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
+ // Interrupt Clear
+#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Clear
+#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Clear
+#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
+#define HIB_RTCT_TRIM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCSS register.
+//
+//*****************************************************************************
+#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
+#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
+#define HIB_RTCSS_RTCSSM_S 16
+#define HIB_RTCSS_RTCSSC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
+#define HIB_DATA_RTD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset
+#define FLASH_FMA_OFFSET_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
+#define FLASH_FMD_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
+#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status
+#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status
+#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
+ // Status
+#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status
+#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
+#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
+#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
+#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
+#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
+ // Status and Clear
+#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
+ // Clear
+#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FSIZE register.
+//
+//*****************************************************************************
+#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
+#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash
+#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash
+#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
+#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
+#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash
+#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
+#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash
+#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_SSIZE register.
+//
+//*****************************************************************************
+#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
+#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM
+#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM
+#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM
+#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM
+#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
+#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM
+#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM
+#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
+#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
+//
+//*****************************************************************************
+#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
+#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
+#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
+#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
+#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
+#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
+#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
+#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
+#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
+#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
+#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1
+#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2
+#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
+#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4
+#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5
+#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6
+#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
+#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
+#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select
+#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
+#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version
+#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
+ // register format
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
+#define SYSCTL_DID0_CLASS_BLIZZARD \
+ 0x00050000 // Tiva(TM) C Series Blizzard-class
+ // microcontrollers
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
+ // revision)
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
+ // revision)
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision
+#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
+ // revision update
+#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change
+#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version
+#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1
+ // register format
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family
+#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PGE \
+ 0x00C50000 // TM4C123GH6PGE
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count
+#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28-pin package
+#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package
+#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package
+#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin package
+#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin package
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C
+ // to 70C)
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
+ // (-40C to 85C)
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
+ // to 105C)
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type
+#define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
+#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present
+#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present
+#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present
+#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present
+#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider
+#define SYSCTL_DC1_MINSYSDIV_100 \
+ 0x00001000 // Divide VCO (400MHZ) by 5 minimum
+#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Divide VCO (400MHZ) by 2*2 + 2 =
+ // 6 minimum
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
+ // with a PLL divider of 4
+#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock
+ // with a PLL divider of 5
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
+ // PLL divider of 8
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
+ // PLL divider of 10
+#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed
+#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second
+#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second
+#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second
+#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed
+#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second
+#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second
+#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second
+#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DC1_MPU 0x00000080 // MPU Present
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present
+#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present
+#define SYSCTL_DC1_PLL 0x00000010 // PLL Present
+#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present
+#define SYSCTL_DC1_SWD 0x00000002 // SWD Present
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present
+#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed
+#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present
+#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present
+#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present
+#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 Pin Present
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 Pin Present
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present
+#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present
+#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present
+#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present
+#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present
+#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable
+#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate
+#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present
+#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present
+#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present
+#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present
+#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present
+#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present
+#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present
+#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present
+#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active
+#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active
+#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present
+#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present
+#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present
+#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present
+#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host
+#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_DMACH30 0x40000000 // SW
+#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX / CAN1_TX
+#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX / CAN1_RX
+#define SYSCTL_DC7_DMACH27 0x08000000 // CAN1_TX / ADC1_SS3
+#define SYSCTL_DC7_DMACH26 0x04000000 // CAN1_RX / ADC1_SS2
+#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1
+#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0
+#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX / CAN2_TX
+#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX / CAN2_RX
+#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_WFIFO
+#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_NBRFIFO
+#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B
+#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A
+#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3
+#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2
+#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B
+#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A
+#define SYSCTL_DC7_DMACH13 0x00002000 // CAN0_TX / UART2_TX
+#define SYSCTL_DC7_DMACH12 0x00001000 // CAN0_RX / UART2_RX
+#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / SSI1_TX
+#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / SSI1_RX
+#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / UART1_TX
+#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / UART1_RX
+#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B
+#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A
+#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B
+#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A
+#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B
+#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A
+#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX
+#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present
+#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present
+#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present
+#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present
+#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present
+#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present
+#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present
+#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present
+#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present
+#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present
+#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present
+#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present
+#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present
+#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present
+#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present
+#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present
+#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present
+#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present
+#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present
+#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present
+#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present
+#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present
+#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present
+#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present
+#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BOR0 0x00000004 // VDD under BOR0 Event Action
+#define SYSCTL_PBORCTL_BOR1 0x00000002 // VDD under BOR1 Event Action
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control
+#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control
+#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control
+#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control
+#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control
+#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control
+#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control
+#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control
+#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control
+#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_VDDARIS 0x00000400 // VDDA Power OK Event Raw
+ // Interrupt Status
+#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
+ // Status
+#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt
+ // Status
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_VDDAIM 0x00000400 // VDDA Power OK Interrupt Mask
+#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_VDDAMIS 0x00000400 // VDDA Power OK Masked Interrupt
+ // Status
+#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
+ // Status
+#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt
+ // Status
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset
+#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW 0x00000010 // Software Reset
+#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset
+#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset
+#define SYSCTL_RESC_EXT 0x00000001 // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass
+#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value
+#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
+#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz
+#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
+#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz
+#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz
+#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz
+#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance
+ // Bus
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
+#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200
+ // MHz
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2
+#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2
+#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz
+#define SYSCTL_RCC2_SYSDIV2_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected
+#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action
+#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed
+#define SYSCTL_RCGC0_ADC1SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_250K \
+ 0x00000400 // 250K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_500K \
+ 0x00000800 // 500K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed
+#define SYSCTL_RCGC0_ADC0SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_250K \
+ 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_500K \
+ 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz
+#define SYSCTL_DSLPCLKCFG_D_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
+//
+//*****************************************************************************
+#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value
+#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration
+#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value
+#define SYSCTL_PIOSCCAL_UT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value
+#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result
+#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been
+ // attempted
+#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation
+ // completed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation
+ // failed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value
+#define SYSCTL_PIOSCSTAT_DT_S 16
+#define SYSCTL_PIOSCSTAT_CT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value
+#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value
+#define SYSCTL_PLLFREQ0_MFRAC_S 10
+#define SYSCTL_PLLFREQ0_MINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value
+#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value
+#define SYSCTL_PLLFREQ1_Q_S 8
+#define SYSCTL_PLLFREQ1_N_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC9 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present
+#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present
+#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present
+#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present
+#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present
+#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present
+#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present
+#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present
+#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present
+#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present
+#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present
+#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present
+#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present
+#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present
+#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present
+#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer
+ // Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present
+#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PPTIMER_P5 0x00000020 // Timer 5 Present
+#define SYSCTL_PPTIMER_P4 0x00000010 // Timer 4 Present
+#define SYSCTL_PPTIMER_P3 0x00000008 // Timer 3 Present
+#define SYSCTL_PPTIMER_P2 0x00000004 // Timer 2 Present
+#define SYSCTL_PPTIMER_P1 0x00000002 // Timer 1 Present
+#define SYSCTL_PPTIMER_P0 0x00000001 // Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present
+#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present
+#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present
+#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present
+#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present
+#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present
+#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present
+#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present
+#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present
+#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present
+#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present
+#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present
+#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present
+#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present
+#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present
+#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present
+#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present
+#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present
+#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present
+#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present
+#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present
+#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present
+#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present
+#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present
+#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present
+#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present
+#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present
+#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present
+#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present
+#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present
+#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present
+#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present
+#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present
+#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWTIMER_P5 0x00000020 // Wide Timer 5 Present
+#define SYSCTL_PPWTIMER_P4 0x00000010 // Wide Timer 4 Present
+#define SYSCTL_PPWTIMER_P3 0x00000008 // Wide Timer 3 Present
+#define SYSCTL_PPWTIMER_P2 0x00000004 // Wide Timer 2 Present
+#define SYSCTL_PPWTIMER_P1 0x00000002 // Wide Timer 1 Present
+#define SYSCTL_PPWTIMER_P0 0x00000001 // Wide Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset
+#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_SRTIMER_R5 0x00000020 // Timer 5 Software Reset
+#define SYSCTL_SRTIMER_R4 0x00000010 // Timer 4 Software Reset
+#define SYSCTL_SRTIMER_R3 0x00000008 // Timer 3 Software Reset
+#define SYSCTL_SRTIMER_R2 0x00000004 // Timer 2 Software Reset
+#define SYSCTL_SRTIMER_R1 0x00000002 // Timer 1 Software Reset
+#define SYSCTL_SRTIMER_R0 0x00000001 // Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset
+#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset
+#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset
+#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset
+#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset
+#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset
+#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset
+#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset
+#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset
+#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset
+#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset
+#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset
+#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset
+#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software
+ // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset
+#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset
+#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset
+#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset
+#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset
+#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset
+#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset
+#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset
+#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset
+#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset
+#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset
+#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset
+#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset
+#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset
+#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset
+#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset
+#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset
+#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0
+ // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset
+#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset
+#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWTIMER_R5 0x00000020 // Wide Timer 5 Software Reset
+#define SYSCTL_SRWTIMER_R4 0x00000010 // Wide Timer 4 Software Reset
+#define SYSCTL_SRWTIMER_R3 0x00000008 // Wide Timer 3 Software Reset
+#define SYSCTL_SRWTIMER_R2 0x00000004 // Wide Timer 2 Software Reset
+#define SYSCTL_SRWTIMER_R1 0x00000002 // Wide Timer 1 Software Reset
+#define SYSCTL_SRWTIMER_R0 0x00000001 // Wide Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCTIMER_R5 0x00000020 // Timer 5 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R4 0x00000010 // Timer 4 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R3 0x00000008 // Timer 3 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R2 0x00000004 // Timer 2 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R1 0x00000002 // Timer 1 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R0 0x00000001 // Timer 0 Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWTIMER_R5 0x00000020 // Wide Timer 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R4 0x00000010 // Wide Timer 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R3 0x00000008 // Wide Timer 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R2 0x00000004 // Wide Timer 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R1 0x00000002 // Wide Timer 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R0 0x00000001 // Wide Timer 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCTIMER_S5 0x00000020 // Timer 5 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S4 0x00000010 // Timer 4 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S3 0x00000008 // Timer 3 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S2 0x00000004 // Timer 2 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S1 0x00000002 // Timer 1 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S0 0x00000001 // Timer 0 Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWTIMER_S5 0x00000020 // Wide Timer 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S4 0x00000010 // Wide Timer 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S3 0x00000008 // Wide Timer 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S2 0x00000004 // Wide Timer 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S1 0x00000002 // Wide Timer 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S0 0x00000001 // Wide Timer 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCTIMER_D5 0x00000020 // Timer 5 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D4 0x00000010 // Timer 4 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D3 0x00000008 // Timer 3 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D2 0x00000004 // Timer 2 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D1 0x00000002 // Timer 1 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D0 0x00000001 // Timer 0 Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0
+ // Deep-Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWTIMER_D5 0x00000020 // Wide Timer 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D4 0x00000010 // Wide Timer 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D3 0x00000008 // Wide Timer 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D2 0x00000004 // Wide Timer 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D1 0x00000002 // Wide Timer 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D0 0x00000001 // Wide Timer 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral
+ // Ready
+#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral
+ // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PRTIMER_R5 0x00000020 // Timer 5 Peripheral Ready
+#define SYSCTL_PRTIMER_R4 0x00000010 // Timer 4 Peripheral Ready
+#define SYSCTL_PRTIMER_R3 0x00000008 // Timer 3 Peripheral Ready
+#define SYSCTL_PRTIMER_R2 0x00000004 // Timer 2 Peripheral Ready
+#define SYSCTL_PRTIMER_R1 0x00000002 // Timer 1 Peripheral Ready
+#define SYSCTL_PRTIMER_R0 0x00000001 // Timer 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready
+#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready
+#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready
+#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready
+#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready
+#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready
+#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready
+#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready
+#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready
+#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready
+#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready
+#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready
+#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready
+#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral
+ // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready
+#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready
+#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready
+#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready
+#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready
+#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready
+#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready
+#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready
+#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready
+#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready
+#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready
+#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready
+#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready
+#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready
+#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready
+#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready
+#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready
+#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0
+ // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready
+#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready
+#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWTIMER_R5 0x00000020 // Wide Timer 5 Peripheral Ready
+#define SYSCTL_PRWTIMER_R4 0x00000010 // Wide Timer 4 Peripheral Ready
+#define SYSCTL_PRWTIMER_R3 0x00000008 // Wide Timer 3 Peripheral Ready
+#define SYSCTL_PRWTIMER_R2 0x00000004 // Wide Timer 2 Peripheral Ready
+#define SYSCTL_PRWTIMER_R1 0x00000002 // Wide Timer 1 Peripheral Ready
+#define SYSCTL_PRWTIMER_R0 0x00000001 // Wide Timer 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP \
+ 0x00000020 // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP \
+ 0x00000030 // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT \
+ 0x00000040 // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT \
+ 0x00000050 // Writing destination data
+#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to
+ // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
+#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
+#define UDMA_STAT_STATE_DONE 0x00000090 // Done
+#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
+#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
+#define UDMA_STAT_DMACHANS_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
+ // Pointer
+#define UDMA_ALTBASE_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel
+ // assignment
+#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel
+ // assignment
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHIS register.
+//
+//*****************************************************************************
+#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP0 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
+#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
+#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
+#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
+#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
+#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
+#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
+#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
+#define UDMA_CHMAP0_CH7SEL_S 28
+#define UDMA_CHMAP0_CH6SEL_S 24
+#define UDMA_CHMAP0_CH5SEL_S 20
+#define UDMA_CHMAP0_CH4SEL_S 16
+#define UDMA_CHMAP0_CH3SEL_S 12
+#define UDMA_CHMAP0_CH2SEL_S 8
+#define UDMA_CHMAP0_CH1SEL_S 4
+#define UDMA_CHMAP0_CH0SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP1 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
+#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
+#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
+#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
+#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
+#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
+#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
+#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
+#define UDMA_CHMAP1_CH15SEL_S 28
+#define UDMA_CHMAP1_CH14SEL_S 24
+#define UDMA_CHMAP1_CH13SEL_S 20
+#define UDMA_CHMAP1_CH12SEL_S 16
+#define UDMA_CHMAP1_CH11SEL_S 12
+#define UDMA_CHMAP1_CH10SEL_S 8
+#define UDMA_CHMAP1_CH9SEL_S 4
+#define UDMA_CHMAP1_CH8SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP2 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
+#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
+#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
+#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
+#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
+#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
+#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
+#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
+#define UDMA_CHMAP2_CH23SEL_S 28
+#define UDMA_CHMAP2_CH22SEL_S 24
+#define UDMA_CHMAP2_CH21SEL_S 20
+#define UDMA_CHMAP2_CH20SEL_S 16
+#define UDMA_CHMAP2_CH19SEL_S 12
+#define UDMA_CHMAP2_CH18SEL_S 8
+#define UDMA_CHMAP2_CH17SEL_S 4
+#define UDMA_CHMAP2_CH16SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP3 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
+#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
+#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
+#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
+#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
+#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
+#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
+#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
+#define UDMA_CHMAP3_CH31SEL_S 28
+#define UDMA_CHMAP3_CH30SEL_S 24
+#define UDMA_CHMAP3_CH29SEL_S 20
+#define UDMA_CHMAP3_CH28SEL_S 16
+#define UDMA_CHMAP3_CH27SEL_S 12
+#define UDMA_CHMAP3_CH26SEL_S 8
+#define UDMA_CHMAP3_CH25SEL_S 4
+#define UDMA_CHMAP3_CH24SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
+#define UDMA_SRCENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
+#define UDMA_DSTENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
+#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
+#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
+#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
+#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
+#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
+#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
+#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
+#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
+#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
+#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
+#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
+#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
+#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
+#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
+#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
+#define UDMA_CHCTL_XFERMODE_STOP \
+ 0x00000000 // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC \
+ 0x00000001 // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO \
+ 0x00000002 // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG \
+ 0x00000003 // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG \
+ 0x00000004 // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA \
+ 0x00000005 // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG \
+ 0x00000006 // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA \
+ 0x00000007 // Alternate Peripheral
+ // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating
+ // Point
+#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL
+#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple
+ // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN2 register.
+//
+//*****************************************************************************
+#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN3 register.
+//
+//*****************************************************************************
+#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN4 register.
+//
+//*****************************************************************************
+#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS2 register.
+//
+//*****************************************************************************
+#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS3 register.
+//
+//*****************************************************************************
+#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS4 register.
+//
+//*****************************************************************************
+#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND2 register.
+//
+//*****************************************************************************
+#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND3 register.
+//
+//*****************************************************************************
+#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND4 register.
+//
+//*****************************************************************************
+#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND2 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND3 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND4 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE4 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S 29
+#define NVIC_PRI0_INT2_S 21
+#define NVIC_PRI0_INT1_S 13
+#define NVIC_PRI0_INT0_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S 29
+#define NVIC_PRI1_INT6_S 21
+#define NVIC_PRI1_INT5_S 13
+#define NVIC_PRI1_INT4_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S 29
+#define NVIC_PRI2_INT10_S 21
+#define NVIC_PRI2_INT9_S 13
+#define NVIC_PRI2_INT8_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S 29
+#define NVIC_PRI3_INT14_S 21
+#define NVIC_PRI3_INT13_S 13
+#define NVIC_PRI3_INT12_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S 29
+#define NVIC_PRI4_INT18_S 21
+#define NVIC_PRI4_INT17_S 13
+#define NVIC_PRI4_INT16_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S 29
+#define NVIC_PRI5_INT22_S 21
+#define NVIC_PRI5_INT21_S 13
+#define NVIC_PRI5_INT20_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S 29
+#define NVIC_PRI6_INT26_S 21
+#define NVIC_PRI6_INT25_S 13
+#define NVIC_PRI6_INT24_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S 29
+#define NVIC_PRI7_INT30_S 21
+#define NVIC_PRI7_INT29_S 13
+#define NVIC_PRI7_INT28_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S 29
+#define NVIC_PRI8_INT34_S 21
+#define NVIC_PRI8_INT33_S 13
+#define NVIC_PRI8_INT32_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S 29
+#define NVIC_PRI9_INT38_S 21
+#define NVIC_PRI9_INT37_S 13
+#define NVIC_PRI9_INT36_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S 29
+#define NVIC_PRI10_INT42_S 21
+#define NVIC_PRI10_INT41_S 13
+#define NVIC_PRI10_INT40_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S 29
+#define NVIC_PRI11_INT46_S 21
+#define NVIC_PRI11_INT45_S 13
+#define NVIC_PRI11_INT44_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S 29
+#define NVIC_PRI12_INT50_S 21
+#define NVIC_PRI12_INT49_S 13
+#define NVIC_PRI12_INT48_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S 29
+#define NVIC_PRI13_INT54_S 21
+#define NVIC_PRI13_INT53_S 13
+#define NVIC_PRI13_INT52_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI14 register.
+//
+//*****************************************************************************
+#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask
+#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask
+#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask
+#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask
+#define NVIC_PRI14_INTD_S 29
+#define NVIC_PRI14_INTC_S 21
+#define NVIC_PRI14_INTB_S 13
+#define NVIC_PRI14_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI15 register.
+//
+//*****************************************************************************
+#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask
+#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask
+#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask
+#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask
+#define NVIC_PRI15_INTD_S 29
+#define NVIC_PRI15_INTC_S 21
+#define NVIC_PRI15_INTB_S 13
+#define NVIC_PRI15_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI16 register.
+//
+//*****************************************************************************
+#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask
+#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask
+#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask
+#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask
+#define NVIC_PRI16_INTD_S 29
+#define NVIC_PRI16_INTC_S 21
+#define NVIC_PRI16_INTB_S 13
+#define NVIC_PRI16_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI17 register.
+//
+//*****************************************************************************
+#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask
+#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask
+#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask
+#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask
+#define NVIC_PRI17_INTD_S 29
+#define NVIC_PRI17_INTC_S 21
+#define NVIC_PRI17_INTB_S 13
+#define NVIC_PRI17_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI18 register.
+//
+//*****************************************************************************
+#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask
+#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask
+#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask
+#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask
+#define NVIC_PRI18_INTD_S 29
+#define NVIC_PRI18_INTC_S 21
+#define NVIC_PRI18_INTB_S 13
+#define NVIC_PRI18_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI19 register.
+//
+//*****************************************************************************
+#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask
+#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask
+#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask
+#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask
+#define NVIC_PRI19_INTD_S 29
+#define NVIC_PRI19_INTC_S 21
+#define NVIC_PRI19_INTB_S 13
+#define NVIC_PRI19_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI20 register.
+//
+//*****************************************************************************
+#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask
+#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask
+#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask
+#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask
+#define NVIC_PRI20_INTD_S 29
+#define NVIC_PRI20_INTC_S 21
+#define NVIC_PRI20_INTB_S 13
+#define NVIC_PRI20_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI21 register.
+//
+//*****************************************************************************
+#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask
+#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask
+#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask
+#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask
+#define NVIC_PRI21_INTD_S 29
+#define NVIC_PRI21_INTC_S 21
+#define NVIC_PRI21_INTB_S 13
+#define NVIC_PRI21_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI22 register.
+//
+//*****************************************************************************
+#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask
+#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask
+#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask
+#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask
+#define NVIC_PRI22_INTD_S 29
+#define NVIC_PRI22_INTC_S 21
+#define NVIC_PRI22_INTB_S 13
+#define NVIC_PRI22_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI23 register.
+//
+//*****************************************************************************
+#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask
+#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask
+#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask
+#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask
+#define NVIC_PRI23_INTD_S 29
+#define NVIC_PRI23_INTC_S 21
+#define NVIC_PRI23_INTB_S 13
+#define NVIC_PRI23_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI24 register.
+//
+//*****************************************************************************
+#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask
+#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask
+#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask
+#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask
+#define NVIC_PRI24_INTD_S 29
+#define NVIC_PRI24_INTC_S 21
+#define NVIC_PRI24_INTB_S 13
+#define NVIC_PRI24_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI25 register.
+//
+//*****************************************************************************
+#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask
+#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask
+#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask
+#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask
+#define NVIC_PRI25_INTD_S 29
+#define NVIC_PRI25_INTC_S 21
+#define NVIC_PRI25_INTB_S 13
+#define NVIC_PRI25_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI26 register.
+//
+//*****************************************************************************
+#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask
+#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask
+#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask
+#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask
+#define NVIC_PRI26_INTD_S 29
+#define NVIC_PRI26_INTC_S 21
+#define NVIC_PRI26_INTB_S 13
+#define NVIC_PRI26_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI27 register.
+//
+//*****************************************************************************
+#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask
+#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask
+#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask
+#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask
+#define NVIC_PRI27_INTD_S 29
+#define NVIC_PRI27_INTC_S 21
+#define NVIC_PRI27_INTB_S 13
+#define NVIC_PRI27_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI28 register.
+//
+//*****************************************************************************
+#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask
+#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask
+#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask
+#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask
+#define NVIC_PRI28_INTD_S 29
+#define NVIC_PRI28_INTC_S 21
+#define NVIC_PRI28_INTB_S 13
+#define NVIC_PRI28_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI29 register.
+//
+//*****************************************************************************
+#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask
+#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask
+#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask
+#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask
+#define NVIC_PRI29_INTD_S 29
+#define NVIC_PRI29_INTC_S 21
+#define NVIC_PRI29_INTB_S 13
+#define NVIC_PRI29_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI30 register.
+//
+//*****************************************************************************
+#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask
+#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask
+#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask
+#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask
+#define NVIC_PRI30_INTD_S 29
+#define NVIC_PRI30_INTC_S 21
+#define NVIC_PRI30_INTB_S 13
+#define NVIC_PRI30_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI31 register.
+//
+//*****************************************************************************
+#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask
+#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask
+#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask
+#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask
+#define NVIC_PRI31_INTD_S 29
+#define NVIC_PRI31_INTC_S 21
+#define NVIC_PRI31_INTB_S 13
+#define NVIC_PRI31_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI32 register.
+//
+//*****************************************************************************
+#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask
+#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask
+#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask
+#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask
+#define NVIC_PRI32_INTD_S 29
+#define NVIC_PRI32_INTC_S 21
+#define NVIC_PRI32_INTB_S 13
+#define NVIC_PRI32_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI33 register.
+//
+//*****************************************************************************
+#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
+ // [4n+3]
+#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
+ // [4n+2]
+#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
+ // [4n+1]
+#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
+ // [4n]
+#define NVIC_PRI33_INTD_S 29
+#define NVIC_PRI33_INTC_S 21
+#define NVIC_PRI33_INTB_S 13
+#define NVIC_PRI33_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI34 register.
+//
+//*****************************************************************************
+#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
+ // [4n+3]
+#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
+ // [4n+2]
+#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
+ // [4n+1]
+#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
+ // [4n]
+#define NVIC_PRI34_INTD_S 29
+#define NVIC_PRI34_INTC_S 21
+#define NVIC_PRI34_INTB_S 13
+#define NVIC_PRI34_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code
+#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number
+#define NVIC_CPUID_CON_M 0x000F0000 // Constant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number
+#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor
+#define NVIC_CPUID_REV_M 0x0000000F // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+ 0x00002000 // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+ 0x00003000 // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+ 0x00004000 // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+ 0x00005000 // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+ 0x00006000 // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+ 0x0000B000 // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+ 0x0000E000 // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+ 0x0000F000 // SysTick
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception
+ // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and
+ // Fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S 21
+#define NVIC_SYS_PRI1_BUS_S 13
+#define NVIC_SYS_PRI1_MEM_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S 29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S 29
+#define NVIC_SYS_PRI3_PENDSV_S 21
+#define NVIC_SYS_PRI3_DEBUG_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+ 0x00001000 // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage
+ // Fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy
+ // State Preservation
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address
+ // Register Valid
+#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on
+ // Floating-Point Lazy State
+ // Preservation
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPAC register.
+//
+//*****************************************************************************
+#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access
+ // Privilege
+#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied
+#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only
+#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access
+#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access
+ // Privilege
+#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied
+#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only
+#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE_ADDR_S 5
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE1_ADDR_S 5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE2_ADDR_S 5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE3_ADDR_S 5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCC register.
+//
+//*****************************************************************************
+#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation
+ // Enable
+#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable
+#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready
+#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready
+#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready
+#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready
+#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode
+#define NVIC_FPCC_USER 0x00000002 // User Privilege Level
+#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCA register.
+//
+//*****************************************************************************
+#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address
+#define NVIC_FPCA_ADDRESS_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPDSC register.
+//
+//*****************************************************************************
+#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default
+#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default
+#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default
+#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default
+#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode
+#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP)
+ // mode
+#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity
+ // (RM) mode
+#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode
+
+#endif // __TM4C123GH6PGE_H__
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/main.c b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/main.c
new file mode 100644
index 00000000..5b61ccc3
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/main.c
@@ -0,0 +1,119 @@
+/************************************************************************************//**
+* \file Demo\ARMCM4_TM4C_DK_TM4C123G_IAR\Prog\main.c
+* \brief Demo program application source file.
+* \ingroup Prog_ARMCM4_TM4C_DK_TM4C123G_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+* C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+* Copyright (c) 2014 by Feaser http://www.feaser.com All rights reserved
+*
+*----------------------------------------------------------------------------------------
+* L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along with OpenBLT.
+* If not, see .
+*
+* A special exception to the GPL is included to allow you to distribute a combined work
+* that includes OpenBLT without being obliged to provide the source code for any
+* proprietary components. The exception text is included at the bottom of the license
+* file .
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h" /* generic header */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static void Init(void);
+
+
+/************************************************************************************//**
+** \brief This is the entry point for the bootloader application and is called
+** by the reset interrupt vector after the C-startup routines executed.
+** \return none.
+**
+****************************************************************************************/
+void main(void)
+{
+ /* initialize the microcontroller */
+ Init();
+ /* initialize the bootloader interface */
+ BootComInit();
+
+ /* start the infinite program loop */
+ while (1)
+ {
+ /* toggle LED with a fixed frequency */
+ LedToggle();
+ /* check for bootloader activation request */
+ BootComCheckActivationRequest();
+ }
+} /*** end of main ***/
+
+
+/************************************************************************************//**
+** \brief Initializes the microcontroller.
+** \return none.
+**
+****************************************************************************************/
+static void Init(void)
+{
+ /* enable lazy stacking for interrupt handlers. this allows floating-point
+ * instructions to be used within interrupt handlers, but at the expense of extra
+ * stack usage.
+ */
+ FPULazyStackingEnable();
+ /* set the clocking to run at 50MHz from the PLL */
+ SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
+ /* init the led driver */
+ LedInit();
+ /* init the timer driver */
+ TimeInit();
+ /* enable IRQ's, because they were initially disabled by the bootloader */
+ IrqInterruptEnable();
+} /*** end of Init ***/
+
+
+#ifdef DEBUG
+/************************************************************************************//**
+** \brief Called when a runtime assertion failed. It stores information about
+** where the assertion occurred and halts the software program.
+** \param pcFilename Name of the source file where the assertion occurred.
+** \param ulLine Linenumber in the source file where the assertion occurred.
+** \return none.
+**
+****************************************************************************************/
+void __error__(char *pcFilename, unsigned long ulLine)
+{
+ static volatile char *assert_failure_file;
+ static volatile unsigned long assert_failure_line;
+
+ /* store the file string and line number so that it can be read on a breakpoint*/
+ assert_failure_file = pcFilename;
+ assert_failure_line = ulLine;
+
+ /* hang the software so that it requires a hard reset */
+ for(;;)
+ {
+ }
+} /*** end of __error__ ***/
+#endif
+
+
+/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/memory.x b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/memory.x
new file mode 100644
index 00000000..073e5454
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/memory.x
@@ -0,0 +1,30 @@
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00002000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00002000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
+
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/prog.dox b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/prog.dox
new file mode 100644
index 00000000..0ed0084f
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/prog.dox
@@ -0,0 +1,7 @@
+/**
+\defgroup Prog_ARMCM4_TM4C_DK_TM4C123G_IAR User Program
+\brief User Program.
+\ingroup ARMCM4_TM4C_DK_TM4C123G_IAR
+*/
+
+
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/time.c b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/time.c
new file mode 100644
index 00000000..b35c2631
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/time.c
@@ -0,0 +1,114 @@
+/************************************************************************************//**
+* \file Demo\ARMCM4_TM4C_DK_TM4C123G_IAR\Prog\time.c
+* \brief Timer driver source file.
+* \ingroup Prog_ARMCM4_TM4C_DK_TM4C123G_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+* C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+* Copyright (c) 2014 by Feaser http://www.feaser.com All rights reserved
+*
+*----------------------------------------------------------------------------------------
+* L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along with OpenBLT.
+* If not, see .
+*
+* A special exception to the GPL is included to allow you to distribute a combined work
+* that includes OpenBLT without being obliged to provide the source code for any
+* proprietary components. The exception text is included at the bottom of the license
+* file .
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h" /* generic header */
+
+
+/****************************************************************************************
+* Local data declarations
+****************************************************************************************/
+/** \brief Local variable for storing the number of milliseconds that have elapsed since
+ * startup.
+ */
+static unsigned long millisecond_counter;
+
+
+/************************************************************************************//**
+** \brief Initializes the timer.
+** \return none.
+**
+****************************************************************************************/
+void TimeInit(void)
+{
+ /* configure the SysTick timer for 1 ms period */
+ SysTickPeriodSet((unsigned long)SysCtlClockGet() / 1000);
+ SysTickEnable();
+ SysTickIntEnable();
+ /* reset the millisecond counter */
+ TimeSet(0);
+} /*** end of TimeInit ***/
+
+
+/************************************************************************************//**
+** \brief Stops and disables the timer.
+** \return none.
+**
+****************************************************************************************/
+void TimeDeinit(void)
+{
+ SysTickIntDisable();
+ SysTickDisable();
+} /*** end of TimeDeinit ***/
+
+
+/************************************************************************************//**
+** \brief Sets the initial counter value of the millisecond timer.
+** \param timer_value initialize value of the millisecond timer.
+** \return none.
+**
+****************************************************************************************/
+void TimeSet(unsigned long timer_value)
+{
+ /* set the millisecond counter */
+ millisecond_counter = timer_value;
+} /*** end of TimeSet ***/
+
+
+/************************************************************************************//**
+** \brief Obtains the counter value of the millisecond timer.
+** \return Current value of the millisecond timer.
+**
+****************************************************************************************/
+unsigned long TimeGet(void)
+{
+ /* read and return the millisecond counter value */
+ return millisecond_counter;
+} /*** end of TimeGet ***/
+
+
+/************************************************************************************//**
+** \brief Interrupt service routine of the timer.
+** \return none.
+**
+****************************************************************************************/
+void TimeISRHandler(void)
+{
+ /* increment the millisecond counter */
+ millisecond_counter++;
+} /*** end of TimeISRHandler ***/
+
+
+/*********************************** end of time.c *************************************/
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/time.h b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/time.h
new file mode 100644
index 00000000..15d943af
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/time.h
@@ -0,0 +1,46 @@
+/************************************************************************************//**
+* \file Demo\ARMCM4_TM4C_DK_TM4C123G_IAR\Prog\time.h
+* \brief Timer driver header file.
+* \ingroup Prog_ARMCM4_TM4C_DK_TM4C123G_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+* C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+* Copyright (c) 2014 by Feaser http://www.feaser.com All rights reserved
+*
+*----------------------------------------------------------------------------------------
+* L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along with OpenBLT.
+* If not, see .
+*
+* A special exception to the GPL is included to allow you to distribute a combined work
+* that includes OpenBLT without being obliged to provide the source code for any
+* proprietary components. The exception text is included at the bottom of the license
+* file .
+*
+* \endinternal
+****************************************************************************************/
+#ifndef TIME_H
+#define TIME_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void TimeInit(void);
+void TimeDeinit(void);
+void TimeSet(unsigned long timer_value);
+unsigned long TimeGet(void);
+void TimeISRHandler(void);
+
+#endif /* TIME_H */
+/*********************************** end of time.h *************************************/
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/vectors.c b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/vectors.c
new file mode 100644
index 00000000..c7a3c705
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/Prog/vectors.c
@@ -0,0 +1,261 @@
+/************************************************************************************//**
+* \file Demo\ARMCM4_TM4C_DK_TM4C123G_IAR\Prog\vectors.c
+* \brief Demo program interrupt vectors source file.
+* \ingroup Prog_ARMCM4_TM4C_DK_TM4C123G_IAR
+* \internal
+*----------------------------------------------------------------------------------------
+* C O P Y R I G H T
+*----------------------------------------------------------------------------------------
+* Copyright (c) 2014 by Feaser http://www.feaser.com All rights reserved
+*
+*----------------------------------------------------------------------------------------
+* L I C E N S E
+*----------------------------------------------------------------------------------------
+* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as published by the Free
+* Software Foundation, either version 3 of the License, or (at your option) any later
+* version.
+*
+* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+* PURPOSE. See the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along with OpenBLT.
+* If not, see .
+*
+* A special exception to the GPL is included to allow you to distribute a combined work
+* that includes OpenBLT without being obliged to provide the source code for any
+* proprietary components. The exception text is included at the bottom of the license
+* file .
+*
+* \endinternal
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h" /* generic header */
+
+
+/****************************************************************************************
+* External functions
+****************************************************************************************/
+extern void __iar_program_start( void );
+
+
+/****************************************************************************************
+* Type definitions
+****************************************************************************************/
+/** \brief Structure type for vector table entries. */
+typedef union
+{
+ void (*func)(void); /**< for ISR function pointers */
+ void *ptr; /**< for stack pointer entry */
+}tIsrFunc;
+
+
+/************************************************************************************//**
+** \brief Interrrupt service routines for the reset event.
+** \return none.
+**
+****************************************************************************************/
+void ResetISR(void)
+{
+ /* enable the floating-point unit. this must be done here to handle the
+ * case where main() uses floating-point and the function prologue saves
+ * floating-point registers (which will fault if floating-point is not
+ * enabled). Any configuration of the floating-point unit using DriverLib
+ * APIs must be done here prior to the floating-point unit being enabled.
+ */
+ HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
+ ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
+ NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
+
+ /* Call the application's entry point */
+ __iar_program_start();
+} /*** end of ResetISR ***/
+
+
+/************************************************************************************//**
+** \brief Catch-all for unused interrrupt service routines.
+** \return none.
+**
+****************************************************************************************/
+void UnusedISR(void)
+{
+ /* unexpected interrupt occured, so halt the system */
+ while (1) { ; }
+} /*** end of UnusedISR ***/
+
+
+/****************************************************************************************
+* I N T E R R U P T V E C T O R T A B L E
+****************************************************************************************/
+#pragma language=extended /* enable IAR extensions */
+#pragma segment="CSTACK"
+
+/** \brief Interrupt vector table. */
+__root const tIsrFunc __vector_table[] @ ".intvec" =
+{
+ { .ptr = __sfe( "CSTACK" ) }, /* the initial stack pointer */
+ { ResetISR }, /* the reset handler */
+ { UnusedISR }, /* NMI Handler */
+ { UnusedISR }, /* Hard Fault Handler */
+ { UnusedISR }, /* MPU Fault Handler */
+ { UnusedISR }, /* Bus Fault Handler */
+ { UnusedISR }, /* Usage Fault Handler */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* SVCall Handler */
+ { UnusedISR }, /* Debug Monitor Handler */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* PendSV Handler */
+ { TimeISRHandler }, /* SysTick Handler */
+ { UnusedISR }, /* GPIO Port A */
+ { UnusedISR }, /* GPIO Port B */
+ { UnusedISR }, /* GPIO Port C */
+ { UnusedISR }, /* GPIO Port D */
+ { UnusedISR }, /* GPIO Port E */
+ { UnusedISR }, /* UART0 Rx and Tx */
+ { UnusedISR }, /* UART1 Rx and Tx */
+ { UnusedISR }, /* SSI0 Rx and Tx */
+ { UnusedISR }, /* I2C0 Master and Slave */
+ { UnusedISR }, /* PWM Fault */
+ { UnusedISR }, /* PWM Generator 0 */
+ { UnusedISR }, /* PWM Generator 1 */
+ { UnusedISR }, /* PWM Generator 2 */
+ { UnusedISR }, /* Quadrature Encoder 0 */
+ { UnusedISR }, /* ADC Sequence 0 */
+ { UnusedISR }, /* ADC Sequence 1 */
+ { UnusedISR }, /* ADC Sequence 2 */
+ { UnusedISR }, /* ADC Sequence 3 */
+ { UnusedISR }, /* Watchdog timer */
+ { UnusedISR }, /* Timer 0 subtimer A */
+ { UnusedISR }, /* Timer 0 subtimer B */
+ { UnusedISR }, /* Timer 1 subtimer A */
+ { UnusedISR }, /* Timer 1 subtimer B */
+ { UnusedISR }, /* Timer 2 subtimer A */
+ { UnusedISR }, /* Timer 2 subtimer B */
+ { UnusedISR }, /* Analog Comparator 0 */
+ { UnusedISR }, /* Analog Comparator 1 */
+ { UnusedISR }, /* Analog Comparator 2 */
+ { UnusedISR }, /* System Control (PLL, OSC, BO) */
+ { UnusedISR }, /* FLASH Control */
+ { UnusedISR }, /* GPIO Port F */
+ { UnusedISR }, /* GPIO Port G */
+ { UnusedISR }, /* GPIO Port H */
+ { UnusedISR }, /* UART2 Rx and Tx */
+ { UnusedISR }, /* SSI1 Rx and Tx */
+ { UnusedISR }, /* Timer 3 subtimer A */
+ { UnusedISR }, /* Timer 3 subtimer B */
+ { UnusedISR }, /* I2C1 Master and Slave */
+ { UnusedISR }, /* Quadrature Encoder 1 */
+ { UnusedISR }, /* CAN0 */
+ { UnusedISR }, /* CAN1 */
+ { UnusedISR }, /* CAN2 */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Hibernate */
+ { UnusedISR }, /* USB0 */
+ { UnusedISR }, /* PWM Generator 3 */
+ { UnusedISR }, /* uDMA Software Transfer */
+ { UnusedISR }, /* uDMA Error */
+ { UnusedISR }, /* ADC1 Sequence 0 */
+ { UnusedISR }, /* ADC1 Sequence 1 */
+ { UnusedISR }, /* ADC1 Sequence 2 */
+ { UnusedISR }, /* ADC1 Sequence 3 */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* GPIO Port J */
+ { UnusedISR }, /* GPIO Port K */
+ { UnusedISR }, /* GPIO Port L */
+ { UnusedISR }, /* SSI2 Rx and Tx */
+ { UnusedISR }, /* SSI3 Rx and Tx */
+ { UnusedISR }, /* UART3 Rx and Tx */
+ { UnusedISR }, /* UART4 Rx and Tx */
+ { UnusedISR }, /* UART5 Rx and Tx */
+ { UnusedISR }, /* UART6 Rx and Tx */
+ { UnusedISR }, /* UART7 Rx and Tx */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* I2C2 Master and Slave */
+ { UnusedISR }, /* I2C3 Master and Slave */
+ { UnusedISR }, /* Timer 4 subtimer A */
+ { UnusedISR }, /* Timer 4 subtimer B */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Timer 5 subtimer A */
+ { UnusedISR }, /* Timer 5 subtimer B */
+ { UnusedISR }, /* Wide Timer 0 subtimer A */
+ { UnusedISR }, /* Wide Timer 0 subtimer B */
+ { UnusedISR }, /* Wide Timer 1 subtimer A */
+ { UnusedISR }, /* Wide Timer 1 subtimer B */
+ { UnusedISR }, /* Wide Timer 2 subtimer A */
+ { UnusedISR }, /* Wide Timer 2 subtimer B */
+ { UnusedISR }, /* Wide Timer 3 subtimer A */
+ { UnusedISR }, /* Wide Timer 3 subtimer B */
+ { UnusedISR }, /* Wide Timer 4 subtimer A */
+ { UnusedISR }, /* Wide Timer 4 subtimer B */
+ { UnusedISR }, /* Wide Timer 5 subtimer A */
+ { UnusedISR }, /* Wide Timer 5 subtimer B */
+ { UnusedISR }, /* FPU */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* I2C4 Master and Slave */
+ { UnusedISR }, /* I2C5 Master and Slave */
+ { UnusedISR }, /* GPIO Port M */
+ { UnusedISR }, /* GPIO Port N */
+ { UnusedISR }, /* Quadrature Encoder 2 */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* GPIO Port P (Summary or P0) */
+ { UnusedISR }, /* GPIO Port P1 */
+ { UnusedISR }, /* GPIO Port P2 */
+ { UnusedISR }, /* GPIO Port P3 */
+ { UnusedISR }, /* GPIO Port P4 */
+ { UnusedISR }, /* GPIO Port P5 */
+ { UnusedISR }, /* GPIO Port P6 */
+ { UnusedISR }, /* GPIO Port P7 */
+ { UnusedISR }, /* GPIO Port Q (Summary or Q0) */
+ { UnusedISR }, /* GPIO Port Q1 */
+ { UnusedISR }, /* GPIO Port Q2 */
+ { UnusedISR }, /* GPIO Port Q3 */
+ { UnusedISR }, /* GPIO Port Q4 */
+ { UnusedISR }, /* GPIO Port Q5 */
+ { UnusedISR }, /* GPIO Port Q6 */
+ { UnusedISR }, /* GPIO Port Q7 */
+ { UnusedISR }, /* GPIO Port R */
+ { UnusedISR }, /* GPIO Port S */
+ { UnusedISR }, /* PWM 1 Generator 0 */
+ { UnusedISR }, /* PWM 1 Generator 1 */
+ { UnusedISR }, /* PWM 1 Generator 2 */
+ { UnusedISR }, /* PWM 1 Generator 3 */
+ { UnusedISR }, /* PWM 1 Fault */
+ { .ptr = (void*)0x55AA11EE } /* Reserved for OpenBLT checksum */
+};
+
+
+/************************************ end of vectors.c *********************************/
+
+
diff --git a/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/demo.dox b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/demo.dox
new file mode 100644
index 00000000..f3d7baea
--- /dev/null
+++ b/Target/Demo/ARMCM4_TM4C_DK_TM4C123G_IAR/demo.dox
@@ -0,0 +1,8 @@
+/**
+\defgroup ARMCM4_TM4C_DK_TM4C123G_IAR Demo for Texas Instruments DK-TM4C123G/IAR
+\brief Preconfigured programs for the Texas Instruments DK-TM4C123G and the IAR Embedded Workbench IDE.
+\details Refer to http://feaser.com/openblt/doku.php?id=manual:demos
+ for detailed getting started instructions.
+*/
+
+