.
+|
+****************************************************************************************/
+#ifndef LED_H
+#define LED_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void LedInit(void);
+void LedToggle(void);
+
+
+#endif /* LED_H */
+/*********************************** end of led.h **************************************/
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/EULA.txt b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/EULA.txt
new file mode 100644
index 00000000..7c1cfc7a
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/EULA.txt
@@ -0,0 +1,400 @@
+License Agreement
+
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+
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/adc.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/adc.c
new file mode 100644
index 00000000..d6ef5ccc
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/adc.c
@@ -0,0 +1,1470 @@
+//*****************************************************************************
+//
+// adc.c - Driver for the ADC.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup adc_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_adc.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/adc.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// These defines are used by the ADC driver to simplify access to the ADC
+// sequencer's registers.
+//
+//*****************************************************************************
+#define ADC_SEQ (ADC_O_SSMUX0)
+#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0)
+#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0)
+#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)
+#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
+#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
+#define ADC_SSOP (ADC_O_SSOP0 - ADC_O_SSMUX0)
+#define ADC_SSDC (ADC_O_SSDC0 - ADC_O_SSMUX0)
+
+//*****************************************************************************
+//
+// The currently configured software oversampling factor for each of the ADC
+// sequencers.
+//
+//*****************************************************************************
+static unsigned char g_pucOversampleFactor[3];
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for an ADC interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! ADC sample sequence interrupt occurs.
+//!
+//! This function sets the handler to be called when a sample sequence
+//! interrupt occurs. This will enable the global interrupt in the interrupt
+//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It
+//! is the interrupt handler's responsibility to clear the interrupt source via
+//! ADCIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
+ void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Determine the interrupt to register based on the sequence number.
+ //
+ ulInt = ((ulBase == ADC0_BASE) ? (INT_ADC0SS0 + ulSequenceNum) :
+ (INT_ADC1SS0 + ulSequenceNum));
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the timer interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for an ADC interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function unregisters the interrupt handler. This will disable the
+//! global interrupt in the interrupt controller; the sequence interrupt must
+//! be disabled via ADCIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntUnregister(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Determine the interrupt to unregister based on the sequence number.
+ //
+ ulInt = ((ulBase == ADC0_BASE) ? (INT_ADC0SS0 + ulSequenceNum) :
+ (INT_ADC1SS0 + ulSequenceNum));
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Disables a sample sequence interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function disables the requested sample sequence interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Disable this sample sequence interrupt.
+ //
+ HWREG(ulBase + ADC_O_IM) &= ~(1 << ulSequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Enables a sample sequence interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function enables the requested sample sequence interrupt. Any
+//! outstanding interrupts are cleared before enabling the sample sequence
+//! interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Clear any outstanding interrupts on this sample sequence.
+ //
+ HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
+
+ //
+ // Enable this sample sequence interrupt.
+ //
+ HWREG(ulBase + ADC_O_IM) |= 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the specified sample sequence.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return The current raw or masked interrupt status.
+//
+//*****************************************************************************
+unsigned long
+ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
+ tBoolean bMasked)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ ulTemp = HWREG(ulBase + ADC_O_ISC) & (0x10001 << ulSequenceNum);
+ }
+ else
+ {
+ ulTemp = HWREG(ulBase + ADC_O_RIS) & (0x10000 | (1 << ulSequenceNum));
+
+ //
+ // If the digital comparator status bit is set, reflect it to the
+ // appropriate sequence bit.
+ //
+ if(ulTemp & 0x10000)
+ {
+ ulTemp |= 0xF0000;
+ ulTemp &= ~(0x10000 << ulSequenceNum);
+ }
+ }
+
+ //
+ // Return the interrupt status
+ //
+ return(ulTemp);
+}
+
+//*****************************************************************************
+//
+//! Clears sample sequence interrupt source.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! The specified sample sequence interrupt is cleared, so that it no longer
+//! asserts. This must be done in the interrupt handler to keep it from being
+//! called again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Clear the interrupt.
+ //
+ HWREG(ulBase + ADC_O_ISC) = 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Enables a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! Allows the specified sample sequence to be captured when its trigger is
+//! detected. A sample sequence must be configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceEnable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Enable the specified sequence.
+ //
+ HWREG(ulBase + ADC_O_ACTSS) |= 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Disables a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! Prevents the specified sample sequence from being captured when its trigger
+//! is detected. A sample sequence should be disabled before it is configured.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Disable the specified sequences.
+ //
+ HWREG(ulBase + ADC_O_ACTSS) &= ~(1 << ulSequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Configures the trigger source and priority of a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param ulTrigger is the trigger source that initiates the sample sequence;
+//! must be one of the \b ADC_TRIGGER_* values.
+//! \param ulPriority is the relative priority of the sample sequence with
+//! respect to the other sample sequences.
+//!
+//! This function configures the initiation criteria for a sample sequence.
+//! Valid sample sequences range from zero to three; sequence zero will capture
+//! up to eight samples, sequences one and two will capture up to four samples,
+//! and sequence three will capture a single sample. The trigger condition and
+//! priority (with respect to other sample sequence execution) is set.
+//!
+//! The \e ulTrigger parameter can take on the following values:
+//!
+//! - \b ADC_TRIGGER_PROCESSOR - A trigger generated by the processor, via the
+//! ADCProcessorTrigger() function.
+//! - \b ADC_TRIGGER_COMP0 - A trigger generated by the first analog
+//! comparator; configured with ComparatorConfigure().
+//! - \b ADC_TRIGGER_COMP1 - A trigger generated by the second analog
+//! comparator; configured with ComparatorConfigure().
+//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog
+//! comparator; configured with ComparatorConfigure().
+//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port
+//! B4 pin.
+//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with
+//! TimerControlTrigger().
+//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;
+//! configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_PWM1 - A trigger generated by the second PWM generator;
+//! configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_PWM2 - A trigger generated by the third PWM generator;
+//! configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_PWM3 - A trigger generated by the fourth PWM generator;
+//! configured with PWMGenIntTrigEnable().
+//! - \b ADC_TRIGGER_ALWAYS - A trigger that is always asserted, causing the
+//! sample sequence to capture repeatedly (so long as
+//! there is not a higher priority source active).
+//!
+//! Note that not all trigger sources are available on all Stellaris family
+//! members; consult the data sheet for the device in question to determine the
+//! availability of triggers.
+//!
+//! The \e ulPriority parameter is a value between 0 and 3, where 0 represents
+//! the highest priority and 3 the lowest. Note that when programming the
+//! priority among a set of sample sequences, each must have unique priority;
+//! it is up to the caller to guarantee the uniqueness of the priorities.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
+ unsigned long ulTrigger, unsigned long ulPriority)
+{
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+ ASSERT((ulTrigger == ADC_TRIGGER_PROCESSOR) ||
+ (ulTrigger == ADC_TRIGGER_COMP0) ||
+ (ulTrigger == ADC_TRIGGER_COMP1) ||
+ (ulTrigger == ADC_TRIGGER_COMP2) ||
+ (ulTrigger == ADC_TRIGGER_EXTERNAL) ||
+ (ulTrigger == ADC_TRIGGER_TIMER) ||
+ (ulTrigger == ADC_TRIGGER_PWM0) ||
+ (ulTrigger == ADC_TRIGGER_PWM1) ||
+ (ulTrigger == ADC_TRIGGER_PWM2) ||
+ (ulTrigger == ADC_TRIGGER_PWM3) ||
+ (ulTrigger == ADC_TRIGGER_ALWAYS));
+ ASSERT(ulPriority < 4);
+
+ //
+ // Compute the shift for the bits that control this sample sequence.
+ //
+ ulSequenceNum *= 4;
+
+ //
+ // Set the trigger event for this sample sequence.
+ //
+ HWREG(ulBase + ADC_O_EMUX) = ((HWREG(ulBase + ADC_O_EMUX) &
+ ~(0xf << ulSequenceNum)) |
+ ((ulTrigger & 0xf) << ulSequenceNum));
+
+ //
+ // Set the priority for this sample sequence.
+ //
+ HWREG(ulBase + ADC_O_SSPRI) = ((HWREG(ulBase + ADC_O_SSPRI) &
+ ~(0xf << ulSequenceNum)) |
+ ((ulPriority & 0x3) << ulSequenceNum));
+}
+
+//*****************************************************************************
+//
+//! Configure a step of the sample sequencer.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param ulStep is the step to be configured.
+//! \param ulConfig is the configuration of this step; must be a logical OR of
+//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
+//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH15). For parts
+//! with the digital comparator feature, the follow values may also be OR'd
+//! into the \e ulConfig value to enable the digital comparater feature:
+//! \b ADC_CTL_CE and one of the comparater selects (\b ADC_CTL_CMP0 through
+//! \b ADC_CTL_CMP7).
+//!
+//! This function will set the configuration of the ADC for one step of a
+//! sample sequence. The ADC can be configured for single-ended or
+//! differential operation (the \b ADC_CTL_D bit selects differential
+//! operation when set), the channel to be sampled can be chosen (the
+//! \b ADC_CTL_CH0 through \b ADC_CTL_CH15 values), and the internal
+//! temperature sensor can be selected (the \b ADC_CTL_TS bit). Additionally,
+//! this step can be defined as the last in the sequence (the \b ADC_CTL_END
+//! bit) and it can be configured to cause an interrupt when the step is
+//! complete (the \b ADC_CTL_IE bit). If the digital comparators are present
+//! on the device, this step may also be configured send the ADC sample to
+//! the selected comparator (the \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7
+//! values) by using the \b ADC_CTL_CE bit. The configuration is used by the
+//! ADC at the appropriate time when the trigger for this sequence occurs.
+//!
+//! \note If the Digitial Comparator is present and enabled using the
+//! \b ADC_CTL_CE bit, the ADC sample will NOT be written into the ADC
+//! sequence data FIFO.
+//!
+//! The \e ulStep parameter determines the order in which the samples are
+//! captured by the ADC when the trigger occurs. It can range from zero to
+//! seven for the first sample sequence, from zero to three for the second and
+//! third sample sequence, and can only be zero for the fourth sample sequence.
+//!
+//! Differential mode only works with adjacent channel pairs (for example, 0
+//! and 1). The channel select must be the number of the channel pair to
+//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2
+//! and 3) or undefined results will be returned by the ADC. Additionally, if
+//! differential mode is selected when the temperature sensor is being sampled,
+//! undefined results will be returned by the ADC.
+//!
+//! It is the responsibility of the caller to ensure that a valid configuration
+//! is specified; this function does not check the validity of the specified
+//! configuration.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
+ unsigned long ulStep, unsigned long ulConfig)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arugments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+ ASSERT(((ulSequenceNum == 0) && (ulStep < 8)) ||
+ ((ulSequenceNum == 1) && (ulStep < 4)) ||
+ ((ulSequenceNum == 2) && (ulStep < 4)) ||
+ ((ulSequenceNum == 3) && (ulStep < 1)));
+
+ //
+ // Get the offset of the sequence to be configured.
+ //
+ ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
+
+ //
+ // Compute the shift for the bits that control this step.
+ //
+ ulStep *= 4;
+
+ //
+ // Set the analog mux value for this step.
+ //
+ HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
+ ~(0x0000000f << ulStep)) |
+ ((ulConfig & 0x0f) << ulStep));
+
+ //
+ // Set the control value for this step.
+ //
+ HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
+ ~(0x0000000f << ulStep)) |
+ (((ulConfig & 0xf0) >> 4) << ulStep));
+
+ //
+ // Enable digital comparator if specified in the ulConfig bit-fields.
+ //
+ if(ulConfig & 0x000F0000)
+ {
+ //
+ // Program the comparator for the specified step.
+ //
+ ulTemp = HWREG(ulBase + ADC_SSDC);
+ ulTemp &= ~(0xF << ulStep);
+ ulTemp |= (((ulConfig & 0x00070000) >> 16) << ulStep);
+ HWREG(ulBase + ADC_SSDC) = ulTemp;
+
+ //
+ // Enable the comparator.
+ //
+ ulTemp = HWREG(ulBase + ADC_SSOP);
+ ulTemp |= (1 << ulStep);
+ HWREG(ulBase + ADC_SSOP) = ulTemp;
+ }
+
+ //
+ // Disable digital comparator if not specified.
+ //
+ else
+ {
+ ulTemp = HWREG(ulBase + ADC_SSOP);
+ ulTemp &= ~(1 << ulStep);
+ HWREG(ulBase + ADC_SSOP) = ulTemp;
+ }
+}
+
+//*****************************************************************************
+//
+//! Determines if a sample sequence overflow occurred.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This determines if a sample sequence overflow has occurred. This will
+//! happen if the captured samples are not read from the FIFO before the next
+//! trigger occurs.
+//!
+//! \return Returns zero if there was not an overflow, and non-zero if there
+//! was.
+//
+//*****************************************************************************
+long
+ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Determine if there was an overflow on this sequence.
+ //
+ return(HWREG(ulBase + ADC_O_OSTAT) & (1 << ulSequenceNum));
+}
+
+//*****************************************************************************
+//
+//! Clears the overflow condition on a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This will clear an overflow condition on one of the sample sequences. The
+//! overflow condition must be cleared in order to detect a subsequent overflow
+//! condition (it otherwise causes no harm).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Clear the overflow condition for this sequence.
+ //
+ HWREG(ulBase + ADC_O_OSTAT) = 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Determines if a sample sequence underflow occurred.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This determines if a sample sequence underflow has occurred. This will
+//! happen if too many samples are read from the FIFO.
+//!
+//! \return Returns zero if there was not an underflow, and non-zero if there
+//! was.
+//
+//*****************************************************************************
+long
+ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Determine if there was an underflow on this sequence.
+ //
+ return(HWREG(ulBase + ADC_O_USTAT) & (1 << ulSequenceNum));
+}
+
+//*****************************************************************************
+//
+//! Clears the underflow condition on a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This will clear an underflow condition on one of the sample sequences. The
+//! underflow condition must be cleared in order to detect a subsequent
+//! underflow condition (it otherwise causes no harm).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Clear the underflow condition for this sequence.
+ //
+ HWREG(ulBase + ADC_O_USTAT) = 1 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the captured data for a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param pulBuffer is the address where the data is stored.
+//!
+//! This function copies data from the specified sample sequence output FIFO to
+//! a memory resident buffer. The number of samples available in the hardware
+//! FIFO are copied into the buffer, which is assumed to be large enough to
+//! hold that many samples. This will only return the samples that are
+//! presently available, which may not be the entire sample sequence if it is
+//! in the process of being executed.
+//!
+//! \return Returns the number of samples copied to the buffer.
+//
+//*****************************************************************************
+long
+ADCSequenceDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
+ unsigned long *pulBuffer)
+{
+ unsigned long ulCount;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Get the offset of the sequence to be read.
+ //
+ ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
+
+ //
+ // Read samples from the FIFO until it is empty.
+ //
+ ulCount = 0;
+ while(!(HWREG(ulBase + ADC_SSFSTAT) & ADC_SSFSTAT0_EMPTY) && (ulCount < 8))
+ {
+ //
+ // Read the FIFO and copy it to the destination.
+ //
+ *pulBuffer++ = HWREG(ulBase + ADC_SSFIFO);
+
+ //
+ // Increment the count of samples read.
+ //
+ ulCount++;
+ }
+
+ //
+ // Return the number of samples read.
+ //
+ return(ulCount);
+}
+
+//*****************************************************************************
+//
+//! Causes a processor trigger for a sample sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number, with
+//! \b ADC_TRIGGER_WAIT or \b ADC_TRIGGER_SIGNAL optionally ORed into it.
+//!
+//! This function triggers a processor-initiated sample sequence if the sample
+//! sequence trigger is configured to \b ADC_TRIGGER_PROCESSOR. If
+//! \b ADC_TRIGGER_WAIT is ORed into the sequence number, the
+//! processor-initiated trigger is delayed until a later processor-initiated
+//! trigger to a different ADC module that specifies \b ADC_TRIGGER_SIGNAL,
+//! allowing multiple ADCs to start from a processor-initiated trigger in a
+//! synchronous manner.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT((ulSequenceNum & 0xf) < 4);
+
+ //
+ // Generate a processor trigger for this sample sequence.
+ //
+ HWREG(ulBase + ADC_O_PSSI) = ((ulSequenceNum & 0xffff0000) |
+ (1 << (ulSequenceNum & 0xf)));
+}
+
+//*****************************************************************************
+//
+//! Configures the software oversampling factor of the ADC.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param ulFactor is the number of samples to be averaged.
+//!
+//! This function configures the software oversampling for the ADC, which can
+//! be used to provide better resolution on the sampled data. Oversampling is
+//! accomplished by averaging multiple samples from the same analog input.
+//! Three different oversampling rates are supported; 2x, 4x, and 8x.
+//!
+//! Oversampling is only supported on the sample sequencers that are more than
+//! one sample in depth (that is, the fourth sample sequencer is not
+//! supported). Oversampling by 2x (for example) divides the depth of the
+//! sample sequencer by two; so 2x oversampling on the first sample sequencer
+//! can only provide four samples per trigger. This also means that 8x
+//! oversampling is only available on the first sample sequencer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSoftwareOversampleConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulFactor)
+{
+ unsigned long ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 3);
+ ASSERT(((ulFactor == 2) || (ulFactor == 4) || (ulFactor == 8)) &&
+ ((ulSequenceNum == 0) || (ulFactor != 8)));
+
+ //
+ // Convert the oversampling factor to a shift factor.
+ //
+ for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
+ {
+ }
+
+ //
+ // Save the sfiht factor.
+ //
+ g_pucOversampleFactor[ulSequenceNum] = ulValue;
+}
+
+//*****************************************************************************
+//
+//! Configures a step of the software oversampled sequencer.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param ulStep is the step to be configured.
+//! \param ulConfig is the configuration of this step.
+//!
+//! This function configures a step of the sample sequencer when using the
+//! software oversampling feature. The number of steps available depends on
+//! the oversampling factor set by ADCSoftwareOversampleConfigure(). The value
+//! of \e ulConfig is the same as defined for ADCSequenceStepConfigure().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulStep,
+ unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 3);
+ ASSERT(((ulSequenceNum == 0) &&
+ (ulStep < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
+ (ulStep < (4 >> g_pucOversampleFactor[ulSequenceNum])));
+
+ //
+ // Get the offset of the sequence to be configured.
+ //
+ ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
+
+ //
+ // Compute the shift for the bits that control this step.
+ //
+ ulStep *= 4 << g_pucOversampleFactor[ulSequenceNum];
+
+ //
+ // Loop through the hardware steps that make up this step of the software
+ // oversampled sequence.
+ //
+ for(ulSequenceNum = 1 << g_pucOversampleFactor[ulSequenceNum];
+ ulSequenceNum; ulSequenceNum--)
+ {
+ //
+ // Set the analog mux value for this step.
+ //
+ HWREG(ulBase + ADC_SSMUX) = ((HWREG(ulBase + ADC_SSMUX) &
+ ~(0x0000000f << ulStep)) |
+ ((ulConfig & 0x0f) << ulStep));
+
+ //
+ // Set the control value for this step.
+ //
+ HWREG(ulBase + ADC_SSCTL) = ((HWREG(ulBase + ADC_SSCTL) &
+ ~(0x0000000f << ulStep)) |
+ (((ulConfig & 0xf0) >> 4) << ulStep));
+ if(ulSequenceNum != 1)
+ {
+ HWREG(ulBase + ADC_SSCTL) &= ~((ADC_SSCTL0_IE0 |
+ ADC_SSCTL0_END0) << ulStep);
+ }
+
+ //
+ // Go to the next hardware step.
+ //
+ ulStep += 4;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the captured data for a sample sequence using software oversampling.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//! \param pulBuffer is the address where the data is stored.
+//! \param ulCount is the number of samples to be read.
+//!
+//! This function copies data from the specified sample sequence output FIFO to
+//! a memory resident buffer with software oversampling applied. The requested
+//! number of samples are copied into the data buffer; if there are not enough
+//! samples in the hardware FIFO to satisfy this many oversampled data items
+//! then incorrect results will be returned. It is the caller's responsibility
+//! to read only the samples that are available and wait until enough data is
+//! available, for example as a result of receiving an interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
+ unsigned long *pulBuffer, unsigned long ulCount)
+{
+ unsigned long ulIdx, ulAccum;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 3);
+ ASSERT(((ulSequenceNum == 0) &&
+ (ulCount < (8 >> g_pucOversampleFactor[ulSequenceNum]))) ||
+ (ulCount < (4 >> g_pucOversampleFactor[ulSequenceNum])));
+
+ //
+ // Get the offset of the sequence to be read.
+ //
+ ulBase += ADC_SEQ + (ADC_SEQ_STEP * ulSequenceNum);
+
+ //
+ // Read the samples from the FIFO until it is empty.
+ //
+ while(ulCount--)
+ {
+ //
+ // Compute the sum of the samples.
+ //
+ ulAccum = 0;
+ for(ulIdx = 1 << g_pucOversampleFactor[ulSequenceNum]; ulIdx; ulIdx--)
+ {
+ //
+ // Read the FIFO and add it to the accumulator.
+ //
+ ulAccum += HWREG(ulBase + ADC_SSFIFO);
+ }
+
+ //
+ // Write the averaged sample to the output buffer.
+ //
+ *pulBuffer++ = ulAccum >> g_pucOversampleFactor[ulSequenceNum];
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the hardware oversampling factor of the ADC.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulFactor is the number of samples to be averaged.
+//!
+//! This function configures the hardware oversampling for the ADC, which can
+//! be used to provide better resolution on the sampled data. Oversampling is
+//! accomplished by averaging multiple samples from the same analog input. Six
+//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.
+//! Specifying an oversampling factor of zero will disable hardware
+//! oversampling.
+//!
+//! Hardware oversampling applies uniformly to all sample sequencers. It does
+//! not reduce the depth of the sample sequencers like the software
+//! oversampling APIs; each sample written into the sample sequence FIFO is a
+//! fully oversampled analog input reading.
+//!
+//! Enabling hardware averaging increases the precision of the ADC at the cost
+//! of throughput. For example, enabling 4x oversampling reduces the
+//! throughput of a 250 Ksps ADC to 62.5 Ksps.
+//!
+//! \note Hardware oversampling is available beginning with Rev C0 of the
+//! Stellaris microcontroller.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
+{
+ unsigned long ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(((ulFactor == 0) || (ulFactor == 2) || (ulFactor == 4) ||
+ (ulFactor == 8) || (ulFactor == 16) || (ulFactor == 32) ||
+ (ulFactor == 64)));
+
+ //
+ // Convert the oversampling factor to a shift factor.
+ //
+ for(ulValue = 0, ulFactor >>= 1; ulFactor; ulValue++, ulFactor >>= 1)
+ {
+ }
+
+ //
+ // Write the shift factor to the ADC to configure the hardware oversampler.
+ //
+ HWREG(ulBase + ADC_O_SAC) = ulValue;
+}
+
+//*****************************************************************************
+//
+//! Configures an ADC digital comparator.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulComp is the index of the comparator to configure.
+//! \param ulConfig is the configuration of the comparator.
+//!
+//! This function will configure a comparator. The \e ulConfig parameter is
+//! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and
+//! \b ADC_COMP_INT_xxx values.
+//!
+//! The \b ADC_COMP_TRIG_xxx term can take on the following values:
+//!
+//! - \b ADC_COMP_TRIG_NONE to never trigger PWM fault condition.
+//! - \b ADC_COMP_TRIG_LOW_ALWAYS to always trigger PWM fault condition when
+//! ADC output is in the low-band.
+//! - \b ADC_COMP_TRIG_LOW_ONCE to trigger PWM fault condition once when ADC
+//! output transitions into the low-band.
+//! - \b ADC_COMP_TRIG_LOW_HALWAYS to always trigger PWM fault condition when
+//! ADC output is in the low-band only if ADC output has been in the high-band
+//! since the last trigger output.
+//! - \b ADC_COMP_TRIG_LOW_HONCE to trigger PWM fault condition once when ADC
+//! output transitions into low-band only if ADC output has been in the
+//! high-band since the last trigger output.
+//! - \b ADC_COMP_TRIG_MID_ALWAYS to always trigger PWM fault condition when
+//! ADC output is in the mid-band.
+//! - \b ADC_COMP_TRIG_MID_ONCE to trigger PWM fault condition once when ADC
+//! output transitions into the mid-band.
+//! - \b ADC_COMP_TRIG_HIGH_ALWAYS to always trigger PWM fault condition when
+//! ADC output is in the high-band.
+//! - \b ADC_COMP_TRIG_HIGH_ONCE to trigger PWM fault condition once when ADC
+//! output transitions into the high-band.
+//! - \b ADC_COMP_TRIG_HIGH_HALWAYS to always trigger PWM fault condition when
+//! ADC output is in the high-band only if ADC output has been in the low-band
+//! since the last trigger output.
+//! - \b ADC_COMP_TRIG_HIGH_HONCE to trigger PWM fault condition once when ADC
+//! output transitions into high-band only if ADC output has been in the
+//! low-band since the last trigger output.
+//!
+//! The \b ADC_COMP_INT_xxx term can take on the following values:
+//!
+//! - \b ADC_COMP_INT_NONE to never generate ADC interrupt.
+//! - \b ADC_COMP_INT_LOW_ALWAYS to always generate ADC interrupt when ADC
+//! output is in the low-band.
+//! - \b ADC_COMP_INT_LOW_ONCE to generate ADC interrupt once when ADC output
+//! transitions into the low-band.
+//! - \b ADC_COMP__INT_LOW_HALWAYS to always generate ADC interrupt when ADC
+//! output is in the low-band only if ADC output has been in the high-band
+//! since the last trigger output.
+//! - \b ADC_COMP_INT_LOW_HONCE to generate ADC interrupt once when ADC output
+//! transitions into low-band only if ADC output has been in the high-band
+//! since the last trigger output.
+//! - \b ADC_COMP_INT_MID_ALWAYS to always generate ADC interrupt when ADC
+//! output is in the mid-band.
+//! - \b ADC_COMP_INT_MID_ONCE to generate ADC interrupt once when ADC output
+//! transitions into the mid-band.
+//! - \b ADC_COMP_INT_HIGH_ALWAYS to always generate ADC interrupt when ADC
+//! output is in the high-band.
+//! - \b ADC_COMP_INT_HIGH_ONCE to generate ADC interrupt once when ADC output
+//! transitions into the high-band.
+//! - \b ADC_COMP_INT_HIGH_HALWAYS to always generate ADC interrupt when ADC
+//! output is in the high-band only if ADC output has been in the low-band
+//! since the last trigger output.
+//! - \b ADC_COMP_INT_HIGH_HONCE to generate ADC interrupt once when ADC output
+//! transitions into high-band only if ADC output has been in the low-band
+//! since the last trigger output.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
+ unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulComp < 8);
+
+ //
+ // Save the new setting.
+ //
+ HWREG(ulBase + ADC_O_DCCTL0 + (ulComp * 4)) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Defines the ADC digital comparator regions.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulComp is the index of the comparator to configure.
+//! \param ulLowRef is the reference point for the low/mid band threshold.
+//! \param ulHighRef is the reference point for the mid/high band threshold.
+//!
+//! The ADC digital comparator operation is based on three ADC value regions:
+//! - \b low-band is defined as any ADC value less than or equal to the
+//! \e ulLowRef value.
+//! - \b mid-band is defined as any ADC value greater than the \e ulLowRef
+//! value but less than or equal to the \e ulHighRef value.
+//! - \b high-band is defined as any ADC value greater than the \e ulHighRef
+//! value.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
+ unsigned long ulLowRef, unsigned long ulHighRef)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulComp < 8);
+ ASSERT((ulLowRef < 1024) && (ulLowRef <= ulHighRef));
+ ASSERT(ulHighRef < 1024);
+
+ //
+ // Save the new region settings.
+ //
+ HWREG(ulBase + ADC_O_DCCMP0 + (ulComp * 4)) = (ulHighRef << 16) | ulLowRef;
+}
+
+//*****************************************************************************
+//
+//! Resets the current ADC digital comparator conditions.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulComp is the index of the comparator.
+//! \param bTrigger is the flag to indicate reset of Trigger conditions.
+//! \param bInterrupt is the flag to indicate reset of Interrupt conditions.
+//!
+//! Because the digital comparator uses current and previous ADC values, this
+//! function is provide to allow the comparator to be reset to its initial
+//! value to prevent stale data from being used when a sequence is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
+ tBoolean bTrigger, tBoolean bInterrupt)
+{
+ unsigned long ulTemp = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulComp < 8);
+
+ //
+ // Set the appropriate bits to reset the trigger and/or interrupt
+ // comparator conditions.
+ //
+ if(bTrigger)
+ {
+ ulTemp |= (1 << (16 + ulComp));
+ }
+ if(bInterrupt)
+ {
+ ulTemp |= (1 << ulComp);
+ }
+
+ HWREG(ulBase + ADC_O_DCRIC) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Disables a sample sequence comparator interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function disables the requested sample sequence comparator interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorIntDisable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Disable this sample sequence comparator interrupt.
+ //
+ HWREG(ulBase + ADC_O_IM) &= ~(0x10000 << ulSequenceNum);
+}
+
+//*****************************************************************************
+//
+//! Enables a sample sequence comparator interrupt.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulSequenceNum is the sample sequence number.
+//!
+//! This function enables the requested sample sequence comparator interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT(ulSequenceNum < 4);
+
+ //
+ // Enable this sample sequence interrupt.
+ //
+ HWREG(ulBase + ADC_O_IM) |= 0x10000 << ulSequenceNum;
+}
+
+//*****************************************************************************
+//
+//! Gets the current comparator interrupt status.
+//!
+//! \param ulBase is the base address of the ADC module.
+//!
+//! This returns the digitial comparator interrupt status bits. This status
+//! is sequence agnostic.
+//!
+//! \return The current comparator interrupt status.
+//
+//*****************************************************************************
+unsigned long
+ADCComparatorIntStatus(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+ //
+ // Return the digitial comparator interrupt status.
+ //
+ return(HWREG(ulBase + ADC_O_DCISC));
+}
+
+//*****************************************************************************
+//
+//! Clears sample sequence comparator interrupt source.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulStatus is the bit-mapped interrupts status to clear.
+//!
+//! The specified interrupt status is cleared.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+ //
+ // Clear the interrupt.
+ //
+ HWREG(ulBase + ADC_O_DCISC) = ulStatus;
+}
+
+//*****************************************************************************
+//
+//! Selects the ADC reference.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulRef is the reference to use.
+//!
+//! The ADC reference is set as specified by \e ulRef. It must be one of
+//! \b ADC_REF_INT or \b ADC_REF_EXT_3V, for internal or external reference.
+//! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and
+//! no external reference is needed. If \b ADC_REF_EXT_3V is chosen, then a 3V
+//! reference must be supplied to the AVREF pin.
+//!
+//! \note The ADC reference can only be selected on parts that have an external
+//! reference. Consult the data sheet for your part to determine if there is
+//! an external reference.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCReferenceSet(unsigned long ulBase, unsigned long ulRef)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT((ulRef == ADC_REF_INT) || (ulRef == ADC_REF_EXT_3V));
+
+ //
+ // Set the reference.
+ //
+ HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF) |
+ ulRef;
+}
+
+//*****************************************************************************
+//
+//! Returns the current setting of the ADC reference.
+//!
+//! \param ulBase is the base address of the ADC module.
+//!
+//! Returns the value of the ADC reference setting. The returned value will be
+//! one of \b ADC_REF_INT or \b ADC_REF_EXT_3V.
+//!
+//! \note The value returned by this function is only meaningful if used on a
+//! part that is capable of using an external reference. Consult the data
+//! sheet for your part to determine if it has an external reference input.
+//!
+//! \return The current setting of the ADC reference.
+//
+//*****************************************************************************
+unsigned long
+ADCReferenceGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+ //
+ // Return the value of the reference.
+ //
+ return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF);
+}
+
+//*****************************************************************************
+//
+//! Sets the phase delay between a trigger and the start of a sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//! \param ulPhase is the phase delay, specified as one of \b ADC_PHASE_0,
+//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90,
+//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180,
+//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270,
+//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5.
+//!
+//! This function sets the phase delay between the detection of an ADC trigger
+//! event and the start of the sample sequence. By selecting a different phase
+//! delay for a pair of ADC modules (such as \b ADC_PHASE_0 and
+//! \b ADC_PHASE_180) and having each ADC module sample the same analog input,
+//! it is possible to increase the sampling rate of the analog input (with
+//! samples N, N+2, N+4, and so on, coming from the first ADC and samples N+1,
+//! N+3, N+5, and so on, coming from the second ADC). The ADC module has a
+//! single phase delay that is applied to all sample sequences within that
+//! module.
+//!
+//! \note This capability is not available on all parts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+ ASSERT((ulPhase == ADC_PHASE_0) || (ulPhase == ADC_PHASE_22_5) ||
+ (ulPhase == ADC_PHASE_45) || (ulPhase == ADC_PHASE_67_5) ||
+ (ulPhase == ADC_PHASE_90) || (ulPhase == ADC_PHASE_112_5) ||
+ (ulPhase == ADC_PHASE_135) || (ulPhase == ADC_PHASE_157_5) ||
+ (ulPhase == ADC_PHASE_180) || (ulPhase == ADC_PHASE_202_5) ||
+ (ulPhase == ADC_PHASE_225) || (ulPhase == ADC_PHASE_247_5) ||
+ (ulPhase == ADC_PHASE_270) || (ulPhase == ADC_PHASE_292_5) ||
+ (ulPhase == ADC_PHASE_315) || (ulPhase == ADC_PHASE_337_5));
+
+ //
+ // Set the phase delay.
+ //
+ HWREG(ulBase + ADC_O_SPC) = ulPhase;
+}
+
+//*****************************************************************************
+//
+//! Gets the phase delay between a trigger and the start of a sequence.
+//!
+//! \param ulBase is the base address of the ADC module.
+//!
+//! This function gets the current phase delay between the detection of an ADC
+//! trigger event and the start of the sample sequence.
+//!
+//! \return Returns the phase delay, specified as one of \b ADC_PHASE_0,
+//! \b ADC_PHASE_22_5, \b ADC_PHASE_45, \b ADC_PHASE_67_5, \b ADC_PHASE_90,
+//! \b ADC_PHASE_112_5, \b ADC_PHASE_135, \b ADC_PHASE_157_5, \b ADC_PHASE_180,
+//! \b ADC_PHASE_202_5, \b ADC_PHASE_225, \b ADC_PHASE_247_5, \b ADC_PHASE_270,
+//! \b ADC_PHASE_292_5, \b ADC_PHASE_315, or \b ADC_PHASE_337_5.
+//
+//*****************************************************************************
+unsigned long
+ADCPhaseDelayGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
+
+ //
+ // Return the phase delay.
+ //
+ return(HWREG(ulBase + ADC_O_SPC));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/adc.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/adc.h
new file mode 100644
index 00000000..f47a21f7
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/adc.h
@@ -0,0 +1,258 @@
+//*****************************************************************************
+//
+// adc.h - ADC headers for using the ADC driver functions.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ADC_H__
+#define __ADC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger
+// parameter.
+//
+//*****************************************************************************
+#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
+#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
+#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
+#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
+#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
+#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
+#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
+#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
+#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
+#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event
+#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
+// parameter.
+//
+//*****************************************************************************
+#define ADC_CTL_TS 0x00000080 // Temperature sensor select
+#define ADC_CTL_IE 0x00000040 // Interrupt enable
+#define ADC_CTL_END 0x00000020 // Sequence end select
+#define ADC_CTL_D 0x00000010 // Differential select
+#define ADC_CTL_CH0 0x00000000 // Input channel 0
+#define ADC_CTL_CH1 0x00000001 // Input channel 1
+#define ADC_CTL_CH2 0x00000002 // Input channel 2
+#define ADC_CTL_CH3 0x00000003 // Input channel 3
+#define ADC_CTL_CH4 0x00000004 // Input channel 4
+#define ADC_CTL_CH5 0x00000005 // Input channel 5
+#define ADC_CTL_CH6 0x00000006 // Input channel 6
+#define ADC_CTL_CH7 0x00000007 // Input channel 7
+#define ADC_CTL_CH8 0x00000008 // Input channel 8
+#define ADC_CTL_CH9 0x00000009 // Input channel 9
+#define ADC_CTL_CH10 0x0000000A // Input channel 10
+#define ADC_CTL_CH11 0x0000000B // Input channel 11
+#define ADC_CTL_CH12 0x0000000C // Input channel 12
+#define ADC_CTL_CH13 0x0000000D // Input channel 13
+#define ADC_CTL_CH14 0x0000000E // Input channel 14
+#define ADC_CTL_CH15 0x0000000F // Input channel 15
+#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
+#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
+#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
+#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3
+#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4
+#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5
+#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6
+#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCComparatorConfigure as part of the
+// ulConfig parameter.
+//
+//*****************************************************************************
+#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled
+#define ADC_COMP_TRIG_LOW_ALWAYS \
+ 0x00001000 // Trigger Low Always
+#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once
+#define ADC_COMP_TRIG_LOW_HALWAYS \
+ 0x00001200 // Trigger Low Always (Hysteresis)
+#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis)
+#define ADC_COMP_TRIG_MID_ALWAYS \
+ 0x00001400 // Trigger Mid Always
+#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once
+#define ADC_COMP_TRIG_HIGH_ALWAYS \
+ 0x00001C00 // Trigger High Always
+#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once
+#define ADC_COMP_TRIG_HIGH_HALWAYS \
+ 0x00001E00 // Trigger High Always (Hysteresis)
+#define ADC_COMP_TRIG_HIGH_HONCE \
+ 0x00001F00 // Trigger High Once (Hysteresis)
+
+#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled
+#define ADC_COMP_INT_LOW_ALWAYS \
+ 0x00000010 // Interrupt Low Always
+#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once
+#define ADC_COMP_INT_LOW_HALWAYS \
+ 0x00000012 // Interrupt Low Always
+ // (Hysteresis)
+#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis)
+#define ADC_COMP_INT_MID_ALWAYS \
+ 0x00000014 // Interrupt Mid Always
+#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once
+#define ADC_COMP_INT_HIGH_ALWAYS \
+ 0x0000001C // Interrupt High Always
+#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once
+#define ADC_COMP_INT_HIGH_HALWAYS \
+ 0x0000001E // Interrupt High Always
+ // (Hysteresis)
+#define ADC_COMP_INT_HIGH_HONCE \
+ 0x0000001F // Interrupt High Once (Hysteresis)
+
+//*****************************************************************************
+//
+// Values that can be used to modify the sequence number passed to
+// ADCProcessorTrigger in order to get cross-module synchronous processor
+// triggers.
+//
+//*****************************************************************************
+#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger
+#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCPhaseDelaySet as the ulPhase parameter and
+// returned from ADCPhaseDelayGet.
+//
+//*****************************************************************************
+#define ADC_PHASE_0 0x00000000 // 0 degrees
+#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees
+#define ADC_PHASE_45 0x00000002 // 45 degrees
+#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees
+#define ADC_PHASE_90 0x00000004 // 90 degrees
+#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees
+#define ADC_PHASE_135 0x00000006 // 135 degrees
+#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees
+#define ADC_PHASE_180 0x00000008 // 180 degrees
+#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees
+#define ADC_PHASE_225 0x0000000A // 225 degrees
+#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees
+#define ADC_PHASE_270 0x0000000C // 270 degrees
+#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees
+#define ADC_PHASE_315 0x0000000E // 315 degrees
+#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCReferenceSet as the ulRef parameter.
+//
+//*****************************************************************************
+#define ADC_REF_INT 0x00000000 // Internal reference
+#define ADC_REF_EXT_3V 0x00000001 // External 3V reference
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
+ void (*pfnHandler)(void));
+extern void ADCIntUnregister(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
+extern unsigned long ADCIntStatus(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ tBoolean bMasked);
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
+extern void ADCSequenceEnable(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSequenceDisable(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSequenceConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulTrigger,
+ unsigned long ulPriority);
+extern void ADCSequenceStepConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulStep,
+ unsigned long ulConfig);
+extern long ADCSequenceOverflow(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSequenceOverflowClear(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern long ADCSequenceUnderflow(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSequenceUnderflowClear(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern long ADCSequenceDataGet(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long *pulBuffer);
+extern void ADCProcessorTrigger(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulFactor);
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long ulStep,
+ unsigned long ulConfig);
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
+ unsigned long ulSequenceNum,
+ unsigned long *pulBuffer,
+ unsigned long ulCount);
+extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
+ unsigned long ulFactor);
+extern void ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
+ unsigned long ulConfig);
+extern void ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
+ unsigned long ulLowRef,
+ unsigned long ulHighRef);
+extern void ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
+ tBoolean bTrigger, tBoolean bInterrupt);
+extern void ADCComparatorIntDisable(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern void ADCComparatorIntEnable(unsigned long ulBase,
+ unsigned long ulSequenceNum);
+extern unsigned long ADCComparatorIntStatus(unsigned long ulBase);
+extern void ADCComparatorIntClear(unsigned long ulBase,
+ unsigned long ulStatus);
+extern void ADCReferenceSet(unsigned long ulBase, unsigned long ulRef);
+extern unsigned long ADCReferenceGet(unsigned long ulBase);
+extern void ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase);
+extern unsigned long ADCPhaseDelayGet(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ADC_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/comp.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/comp.c
new file mode 100644
index 00000000..313fe8e3
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/comp.c
@@ -0,0 +1,436 @@
+//*****************************************************************************
+//
+// comp.c - Driver for the analog comparator.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup comp_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_comp.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/comp.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Configures a comparator.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator to configure.
+//! \param ulConfig is the configuration of the comparator.
+//!
+//! This function configures a comparator. The \e ulConfig parameter is the
+//! result of a logical OR operation between the \b COMP_TRIG_xxx,
+//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values.
+//!
+//! The \b COMP_TRIG_xxx term can take on the following values:
+//!
+//! - \b COMP_TRIG_NONE to have no trigger to the ADC.
+//! - \b COMP_TRIG_HIGH to trigger the ADC when the comparator output is high.
+//! - \b COMP_TRIG_LOW to trigger the ADC when the comparator output is low.
+//! - \b COMP_TRIG_FALL to trigger the ADC when the comparator output goes low.
+//! - \b COMP_TRIG_RISE to trigger the ADC when the comparator output goes
+//! high.
+//! - \b COMP_TRIG_BOTH to trigger the ADC when the comparator output goes low
+//! or high.
+//!
+//! The \b COMP_INT_xxx term can take on the following values:
+//!
+//! - \b COMP_INT_HIGH to generate an interrupt when the comparator output is
+//! high.
+//! - \b COMP_INT_LOW to generate an interrupt when the comparator output is
+//! low.
+//! - \b COMP_INT_FALL to generate an interrupt when the comparator output goes
+//! low.
+//! - \b COMP_INT_RISE to generate an interrupt when the comparator output goes
+//! high.
+//! - \b COMP_INT_BOTH to generate an interrupt when the comparator output goes
+//! low or high.
+//!
+//! The \b COMP_ASRCP_xxx term can take on the following values:
+//!
+//! - \b COMP_ASRCP_PIN to use the dedicated Comp+ pin as the reference
+//! voltage.
+//! - \b COMP_ASRCP_PIN0 to use the Comp0+ pin as the reference voltage (this
+//! the same as \b COMP_ASRCP_PIN for the comparator 0).
+//! - \b COMP_ASRCP_REF to use the internally generated voltage as the
+//! reference voltage.
+//!
+//! The \b COMP_OUTPUT_xxx term can take on the following values:
+//!
+//! - \b COMP_OUTPUT_NORMAL to enable a non-inverted output from the comparator
+//! to a device pin.
+//! - \b COMP_OUTPUT_INVERT to enable an inverted output from the comparator to
+//! a device pin.
+//! - \b COMP_OUTPUT_NONE is deprecated and behaves the same as
+//! \b COMP_OUTPUT_NORMAL.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
+ unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Configure this comparator.
+ //
+ HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACCTL0) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Sets the internal reference voltage.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulRef is the desired reference voltage.
+//!
+//! This function sets the internal reference voltage value. The voltage is
+//! specified as one of the following values:
+//!
+//! - \b COMP_REF_OFF to turn off the reference voltage
+//! - \b COMP_REF_0V to set the reference voltage to 0 V
+//! - \b COMP_REF_0_1375V to set the reference voltage to 0.1375 V
+//! - \b COMP_REF_0_275V to set the reference voltage to 0.275 V
+//! - \b COMP_REF_0_4125V to set the reference voltage to 0.4125 V
+//! - \b COMP_REF_0_55V to set the reference voltage to 0.55 V
+//! - \b COMP_REF_0_6875V to set the reference voltage to 0.6875 V
+//! - \b COMP_REF_0_825V to set the reference voltage to 0.825 V
+//! - \b COMP_REF_0_928125V to set the reference voltage to 0.928125 V
+//! - \b COMP_REF_0_9625V to set the reference voltage to 0.9625 V
+//! - \b COMP_REF_1_03125V to set the reference voltage to 1.03125 V
+//! - \b COMP_REF_1_134375V to set the reference voltage to 1.134375 V
+//! - \b COMP_REF_1_1V to set the reference voltage to 1.1 V
+//! - \b COMP_REF_1_2375V to set the reference voltage to 1.2375 V
+//! - \b COMP_REF_1_340625V to set the reference voltage to 1.340625 V
+//! - \b COMP_REF_1_375V to set the reference voltage to 1.375 V
+//! - \b COMP_REF_1_44375V to set the reference voltage to 1.44375 V
+//! - \b COMP_REF_1_5125V to set the reference voltage to 1.5125 V
+//! - \b COMP_REF_1_546875V to set the reference voltage to 1.546875 V
+//! - \b COMP_REF_1_65V to set the reference voltage to 1.65 V
+//! - \b COMP_REF_1_753125V to set the reference voltage to 1.753125 V
+//! - \b COMP_REF_1_7875V to set the reference voltage to 1.7875 V
+//! - \b COMP_REF_1_85625V to set the reference voltage to 1.85625 V
+//! - \b COMP_REF_1_925V to set the reference voltage to 1.925 V
+//! - \b COMP_REF_1_959375V to set the reference voltage to 1.959375 V
+//! - \b COMP_REF_2_0625V to set the reference voltage to 2.0625 V
+//! - \b COMP_REF_2_165625V to set the reference voltage to 2.165625 V
+//! - \b COMP_REF_2_26875V to set the reference voltage to 2.26875 V
+//! - \b COMP_REF_2_371875V to set the reference voltage to 2.371875 V
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorRefSet(unsigned long ulBase, unsigned long ulRef)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+
+ //
+ // Set the voltage reference voltage as requested.
+ //
+ HWREG(ulBase + COMP_O_ACREFCTL) = ulRef;
+}
+
+//*****************************************************************************
+//
+//! Gets the current comparator output value.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//!
+//! This function retrieves the current value of the comparator output.
+//!
+//! \return Returns \b true if the comparator output is high and \b false if
+//! the comparator output is low.
+//
+//*****************************************************************************
+tBoolean
+ComparatorValueGet(unsigned long ulBase, unsigned long ulComp)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Return the appropriate value based on the comparator's present output
+ // value.
+ //
+ if(HWREG(ulBase + (ulComp * 0x20) + COMP_O_ACSTAT0) & COMP_ACSTAT0_OVAL)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the comparator interrupt.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! comparator interrupt occurs.
+//!
+//! This sets the handler to be called when the comparator interrupt occurs
+//! and enables the interrupt in the interrupt controller. It is the interrupt
+//! handler's responsibility to clear the interrupt source via
+//! ComparatorIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
+ void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(INT_COMP0 + ulComp, pfnHandler);
+
+ //
+ // Enable the interrupt in the interrupt controller.
+ //
+ IntEnable(INT_COMP0 + ulComp);
+
+ //
+ // Enable the comparator interrupt.
+ //
+ HWREG(ulBase + COMP_O_ACINTEN) |= 1 << ulComp;
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for a comparator interrupt.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//!
+//! This function clears the handler to be called when a comparator interrupt
+//! occurs. This will also mask off the interrupt in the interrupt controller
+//! so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Disable the comparator interrupt.
+ //
+ HWREG(ulBase + COMP_O_ACINTEN) &= ~(1 << ulComp);
+
+ //
+ // Disable the interrupt in the interrupt controller.
+ //
+ IntDisable(INT_COMP0 + ulComp);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_COMP0 + ulComp);
+}
+
+//*****************************************************************************
+//
+//! Enables the comparator interrupt.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//!
+//! This function enables generation of an interrupt from the specified
+//! comparator. Only comparators whose interrupts are enabled can be reflected
+//! to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Enable the comparator interrupt.
+ //
+ HWREG(ulBase + COMP_O_ACINTEN) |= 1 << ulComp;
+}
+
+//*****************************************************************************
+//
+//! Disables the comparator interrupt.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//!
+//! This function disables generation of an interrupt from the specified
+//! comparator. Only comparators whose interrupts are enabled can be reflected
+//! to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Disable the comparator interrupt.
+ //
+ HWREG(ulBase + COMP_O_ACINTEN) &= ~(1 << ulComp);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the comparator. Either the raw or
+//! the masked interrupt status can be returned.
+//!
+//! \return \b true if the interrupt is asserted and \b false if it is not
+//! asserted.
+//
+//*****************************************************************************
+tBoolean
+ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
+ tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(((HWREG(ulBase + COMP_O_ACMIS) >> ulComp) & 1) ? true : false);
+ }
+ else
+ {
+ return(((HWREG(ulBase + COMP_O_ACRIS) >> ulComp) & 1) ? true : false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears a comparator interrupt.
+//!
+//! \param ulBase is the base address of the comparator module.
+//! \param ulComp is the index of the comparator.
+//!
+//! The comparator interrupt is cleared, so that it no longer asserts. This
+//! fucntion must be called in the interrupt handler to keep the handler from
+//! being called again immediately upon exit. Note that for a level-triggered
+//! interrupt, the interrupt cannot be cleared until it stops asserting.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+ComparatorIntClear(unsigned long ulBase, unsigned long ulComp)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == COMP_BASE);
+ ASSERT(ulComp < 3);
+
+ //
+ // Clear the interrupt.
+ //
+ HWREG(ulBase + COMP_O_ACMIS) = 1 << ulComp;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/comp.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/comp.h
new file mode 100644
index 00000000..e02e9e25
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/comp.h
@@ -0,0 +1,130 @@
+//*****************************************************************************
+//
+// comp.h - Prototypes for the analog comparator driver.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __COMP_H__
+#define __COMP_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to ComparatorConfigure() as the ulConfig
+// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
+// the values may be selected and combined together with values from the other
+// groups via a logical OR.
+//
+//*****************************************************************************
+#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
+#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
+#define COMP_TRIG_LOW 0x00000800 // Trigger when low
+#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
+#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
+#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
+#define COMP_INT_HIGH 0x00000010 // Interrupt when high
+#define COMP_INT_LOW 0x00000000 // Interrupt when low
+#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
+#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
+#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
+#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
+#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
+#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
+#ifndef DEPRECATED
+#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
+#endif
+#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal
+#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted
+
+//*****************************************************************************
+//
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
+//
+//*****************************************************************************
+#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
+#define COMP_REF_0V 0x00000300 // Internal reference of 0V
+#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
+#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
+#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
+#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
+#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
+#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
+#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
+#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
+#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
+#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
+#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
+#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
+#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
+#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
+#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
+#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
+#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
+#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
+#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
+#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
+#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
+#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
+#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
+#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
+#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
+#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
+#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
+ unsigned long ulConfig);
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
+ void (*pfnHandler)(void));
+extern void ComparatorIntUnregister(unsigned long ulBase,
+ unsigned long ulComp);
+extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
+extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
+ tBoolean bMasked);
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __COMP_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/cpu.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/cpu.c
new file mode 100644
index 00000000..a7d49bfc
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/cpu.c
@@ -0,0 +1,442 @@
+//*****************************************************************************
+//
+// cpu.c - Instruction wrappers for special CPU instructions needed by the
+// drivers.
+//
+// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#include "driverlib/cpu.h"
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSID instruction. Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUcpsid(void)
+{
+ unsigned long ulRet;
+
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsid i\n"
+ " bx lr\n"
+ : "=r" (ulRet));
+
+ //
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ //
+ return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUcpsid(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsid i\n");
+
+ //
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+ //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUcpsid(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ mrs r0, PRIMASK;
+ cpsid i;
+ bx lr
+}
+#endif
+#if defined(ccs)
+unsigned long
+CPUcpsid(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsid i\n"
+ " bx lr\n");
+
+ //
+ // The following keeps the compiler happy, because it wants to see a
+ // return value from this function. It will generate code to return
+ // a zero. However, the real return is the "bx lr" above, so the
+ // return(0) is never executed and the function returns with the value
+ // you expect in R0.
+ //
+ return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function returning the state of PRIMASK (indicating whether
+// interrupts are enabled or disabled).
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUprimask(void)
+{
+ unsigned long ulRet;
+
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " bx lr\n"
+ : "=r" (ulRet));
+
+ //
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ //
+ return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUprimask(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n");
+
+ //
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+ //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUprimask(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ mrs r0, PRIMASK;
+ bx lr
+}
+#endif
+#if defined(ccs)
+unsigned long
+CPUprimask(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " bx lr\n");
+
+ //
+ // The following keeps the compiler happy, because it wants to see a
+ // return value from this function. It will generate code to return
+ // a zero. However, the real return is the "bx lr" above, so the
+ // return(0) is never executed and the function returns with the value
+ // you expect in R0.
+ //
+ return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUcpsie(void)
+{
+ unsigned long ulRet;
+
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsie i\n"
+ " bx lr\n"
+ : "=r" (ulRet));
+
+ //
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ //
+ return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUcpsie(void)
+{
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsie i\n");
+
+ //
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+ //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUcpsie(void)
+{
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ mrs r0, PRIMASK;
+ cpsie i;
+ bx lr
+}
+#endif
+#if defined(ccs)
+unsigned long
+CPUcpsie(void)
+{
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsie i\n"
+ " bx lr\n");
+
+ //
+ // The following keeps the compiler happy, because it wants to see a
+ // return value from this function. It will generate code to return
+ // a zero. However, the real return is the "bx lr" above, so the
+ // return(0) is never executed and the function returns with the value
+ // you expect in R0.
+ //
+ return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the WFI instruction.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ __asm(" wfi\n"
+ " bx lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ __asm(" wfi\n");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ wfi;
+ bx lr
+}
+#endif
+#if defined(ccs)
+void
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ __asm(" wfi\n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for writing the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+
+ //
+ // Set the BASEPRI register
+ //
+ __asm(" msr BASEPRI, r0\n"
+ " bx lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+ //
+ // Set the BASEPRI register
+ //
+ __asm(" msr BASEPRI, r0\n");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+ //
+ // Set the BASEPRI register
+ //
+ msr BASEPRI, r0;
+ bx lr
+}
+#endif
+#if defined(ccs)
+void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+ //
+ // Set the BASEPRI register
+ //
+ __asm(" msr BASEPRI, r0\n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for reading the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+unsigned long __attribute__((naked))
+CPUbasepriGet(void)
+{
+ unsigned long ulRet;
+
+ //
+ // Read BASEPRI
+ //
+ __asm(" mrs r0, BASEPRI\n"
+ " bx lr\n"
+ : "=r" (ulRet));
+
+ //
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ //
+ return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUbasepriGet(void)
+{
+ //
+ // Read BASEPRI
+ //
+ __asm(" mrs r0, BASEPRI\n");
+
+ //
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+ //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm unsigned long
+CPUbasepriGet(void)
+{
+ //
+ // Read BASEPRI
+ //
+ mrs r0, BASEPRI;
+ bx lr
+}
+#endif
+#if defined(ccs)
+unsigned long
+CPUbasepriGet(void)
+{
+ //
+ // Read BASEPRI
+ //
+ __asm(" mrs r0, BASEPRI\n"
+ " bx lr\n");
+
+ //
+ // The following keeps the compiler happy, because it wants to see a
+ // return value from this function. It will generate code to return
+ // a zero. However, the real return is the "bx lr" above, so the
+ // return(0) is never executed and the function returns with the value
+ // you expect in R0.
+ //
+ return(0);
+}
+#endif
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/cpu.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/cpu.h
new file mode 100644
index 00000000..c0e073e1
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/cpu.h
@@ -0,0 +1,60 @@
+//*****************************************************************************
+//
+// cpu.h - Prototypes for the CPU instruction wrapper functions.
+//
+// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __CPU_H__
+#define __CPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern unsigned long CPUcpsid(void);
+extern unsigned long CPUcpsie(void);
+extern unsigned long CPUprimask(void);
+extern void CPUwfi(void);
+extern unsigned long CPUbasepriGet(void);
+extern void CPUbasepriSet(unsigned long ulNewBasepri);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CPU_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/debug.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/debug.h
new file mode 100644
index 00000000..6fe52fe5
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/debug.h
@@ -0,0 +1,53 @@
+//*****************************************************************************
+//
+// debug.h - Macros for assisting debug of the driver library.
+//
+// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+//*****************************************************************************
+//
+// Prototype for the function that is called when an invalid argument is passed
+// to an API. This is only used when doing a DEBUG build.
+//
+//*****************************************************************************
+extern void __error__(char *pcFilename, unsigned long ulLine);
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking. Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+#ifdef DEBUG
+#define ASSERT(expr) { \
+ if(!(expr)) \
+ { \
+ __error__(__FILE__, __LINE__); \
+ } \
+ }
+#else
+#define ASSERT(expr)
+#endif
+
+#endif // __DEBUG_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/epi.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/epi.c
new file mode 100644
index 00000000..ee53bd42
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/epi.c
@@ -0,0 +1,1176 @@
+//*****************************************************************************
+//
+// epi.c - Driver for the EPI module.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#include "inc/hw_epi.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/epi.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! \addtogroup epi_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! Sets the usage mode of the EPI module.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulMode is the usage mode of the EPI module.
+//!
+//! This functions sets the operating mode of the EPI module. The parameter
+//! \e ulMode must be one of the following:
+//!
+//! - \b EPI_MODE_GENERAL - use for general-purpose mode operation
+//! - \b EPI_MODE_SDRAM - use with SDRAM device
+//! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface
+//! - \b EPI_MODE_HB16 - use with host-bus 16-bit interface
+//! - \b EPI_MODE_DISABLE - disable the EPI module
+//!
+//! Selection of any of the above modes will enable the EPI module, except
+//! for \b EPI_MODE_DISABLE which should be used to disable the module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIModeSet(unsigned long ulBase, unsigned long ulMode)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT((ulMode == EPI_MODE_GENERAL) ||
+ (ulMode == EPI_MODE_SDRAM) ||
+ (ulMode == EPI_MODE_HB8) ||
+ (ulMode == EPI_MODE_HB16) ||
+ (ulMode == EPI_MODE_DISABLE));
+
+ //
+ // Write the mode word to the register.
+ //
+ HWREG(ulBase + EPI_O_CFG) = ulMode;
+}
+
+//*****************************************************************************
+//
+//! Sets the clock divider for the EPI module.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulDivider is the value of the clock divider to be applied to
+//! the external interface (0-65535).
+//!
+//! This functions sets the clock divider(s) that will be used to determine the
+//! clock rate of the external interface. The \e ulDivider value is used to
+//! derive the EPI clock rate from the system clock based upon the following
+//! formula.
+//!
+//! EPIClock = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2))
+//!
+//! For example, a divider value of 1 results in an EPI clock rate of half
+//! the system clock, value of 2 or 3 yield one quarter of the system clock and
+//! a value of 4 results in one sixth of the system clock rate.
+//!
+//! In cases where a dual chip select mode is in use and different clock rates
+//! are required for each chip select, the \e ulDivider parameter must contain
+//! two dividers. The lower 16 bits define the divider to be used with CS0n
+//! and the upper 16 bits define the divider for CS1n.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIDividerSet(unsigned long ulBase, unsigned long ulDivider)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+
+ //
+ // Write the divider value to the register.
+ //
+ HWREG(ulBase + EPI_O_BAUD) = ulDivider;
+}
+
+//*****************************************************************************
+//
+//! Configures the SDRAM mode of operation.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulConfig is the SDRAM interface configuration.
+//! \param ulRefresh is the refresh count in core clocks (0-2047).
+//!
+//! This function is used to configure the SDRAM interface, when the SDRAM
+//! mode is chosen with the function EPIModeSet(). The parameter \e ulConfig
+//! is the logical OR of several sets of choices:
+//!
+//! The processor core frequency must be specified with one of the following:
+//!
+//! - \b EPI_SDRAM_CORE_FREQ_0_15 - core clock is 0 MHz < clk <= 15 MHz
+//! - \b EPI_SDRAM_CORE_FREQ_15_30 - core clock is 15 MHz < clk <= 30 MHz
+//! - \b EPI_SDRAM_CORE_FREQ_30_50 - core clock is 30 MHz < clk <= 50 MHz
+//! - \b EPI_SDRAM_CORE_FREQ_50_100 - core clock is 50 MHz < clk <= 100 MHz
+//!
+//! The low power mode is specified with one of the following:
+//!
+//! - \b EPI_SDRAM_LOW_POWER - enter low power, self-refresh state
+//! - \b EPI_SDRAM_FULL_POWER - normal operating state
+//!
+//! The SDRAM device size is specified with one of the following:
+//!
+//! - \b EPI_SDRAM_SIZE_64MBIT - 64 Mbit device (8 MB)
+//! - \b EPI_SDRAM_SIZE_128MBIT - 128 Mbit device (16 MB)
+//! - \b EPI_SDRAM_SIZE_256MBIT - 256 Mbit device (32 MB)
+//! - \b EPI_SDRAM_SIZE_512MBIT - 512 Mbit device (64 MB)
+//!
+//! The parameter \e ulRefresh sets the refresh counter in units of core
+//! clock ticks. It is an 11-bit value with a range of 0 - 2047 counts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulRefresh)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulRefresh < 2048);
+
+ //
+ // Fill in the refresh count field of the configuration word.
+ //
+ ulConfig &= ~EPI_SDRAMCFG_RFSH_M;
+ ulConfig |= ulRefresh << EPI_SDRAMCFG_RFSH_S;
+
+ //
+ // Write the SDRAM configuration register.
+ //
+ HWREG(ulBase + EPI_O_SDRAMCFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Configures the interface for Host-bus 8 operation.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulConfig is the interface configuration.
+//! \param ulMaxWait is the maximum number of external clocks to wait
+//! if a FIFO ready signal is holding off the transaction.
+//!
+//! This function is used to configure the interface when used in Host-bus 8
+//! operation as chosen with the function EPIModeSet(). The parameter
+//! \e ulConfig is the logical OR of any of the following:
+//!
+//! - one of \b EPI_HB8_MODE_ADMUX, \b EPI_HB8_MODE_ADDEMUX,
+//! \b EPI_HB8_MODE_SRAM, or \b EPI_HB8_MODE_FIFO to select the HB8 mode
+//! - \b EPI_HB8_USE_TXEMPTY - enable TXEMPTY signal with FIFO
+//! - \b EPI_HB8_USE_RXFULL - enable RXFULL signal with FIFO
+//! - \b EPI_HB8_WRHIGH - use active high write strobe, otherwise it is
+//! active low
+//! - \b EPI_HB8_RDHIGH - use active high read strobe, otherwise it is
+//! active low
+//! - one of \b EPI_HB8_WRWAIT_0, \b EPI_HB8_WRWAIT_1, \b EPI_HB8_WRWAIT_2,
+//! or \b EPI_HB8_WRWAIT_3 to select the number of write wait states (default
+//! is 0 wait states)
+//! - one of \b EPI_HB8_RDWAIT_0, \b EPI_HB8_RDWAIT_1, \b EPI_HB8_RDWAIT_2,
+//! or \b EPI_HB8_RDWAIT_3 to select the number of read wait states (default
+//! is 0 wait states)
+//! - \b EPI_HB8_WORD_ACCESS - use Word Access mode to route bytes to the
+//! correct byte lanes allowing data to be stored in bits [31:8]. If absent,
+//! all data transfers use bits [7:0].
+//! - \b EPI_HB8_CSBAUD_DUAL - use different baud rates when accessing devices
+//! on each CSn. CS0n uses the baud rate specified by the lower 16 bits of the
+//! divider passed to EPIDividerSet() and CS1n uses the divider passed in the
+//! upper 16 bits. If this option is absent, both chip selects use the baud
+//! rate resulting from the divider in the lower 16 bits of the parameter passed
+//! to EPIDividerSet().
+//! - one of \b EPI_HB8_CSCFG_CS, \b EPI_HB8_CSCFG_ALE,
+//! \b EPI_HB8_CSCFG_DUAL_CS or \b EPI_HB8_CSCFG_ALE_DUAL_CS. \b
+//! EPI_HB8_CSCFG_CS sets EPI30 to operate as a Chip Select (CSn) signal. \b
+//! EPI_HB8_CSCFG_ALE sets EPI30 to operate as an address latch (ALE). \b
+//! EPI_HB8_CSCFG_DUAL_CS sets EPI30 to operate as CS0n and EPI27 as CS1n with
+//! the asserted chip select determined from the most significant address bit
+//! for the respective external address map. \b EPI_HB8_CSCFG_ALE_DUAL_CS sets
+//! EPI30 as an address latch (ALE), EPI27 as CS0n and EPI26 as CS1n with the
+//! asserted chip select determined from the most significant address bit for
+//! the respective external address map.
+//!
+//! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a
+//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this
+//! parameter determines the maximum number of clocks to wait when the
+//! transaction is being held off by by the FIFO using one of these ready
+//! signals. A value of 0 means to wait forever.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulMaxWait)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulMaxWait < 256);
+
+ //
+ // Determine the CS and word access modes.
+ //
+ HWREG(ulBase + EPI_O_HB8CFG2) = (((ulConfig & EPI_HB8_WORD_ACCESS) ?
+ EPI_HB8CFG2_WORD : 0) |
+ ((ulConfig & EPI_HB8_CSBAUD_DUAL) ?
+ EPI_HB8CFG2_CSBAUD : 0) |
+ ((ulConfig & EPI_HB8_CSCFG_MASK) << 15));
+ //
+ // Fill in the max wait field of the configuration word.
+ //
+ ulConfig &= ~EPI_HB8CFG_MAXWAIT_M;
+ ulConfig |= ulMaxWait << EPI_HB8CFG_MAXWAIT_S;
+
+ //
+ // Write the main HostBus8 configuration register.
+ //
+ HWREG(ulBase + EPI_O_HB8CFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Configures the interface for Host-bus 16 operation.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulConfig is the interface configuration.
+//! \param ulMaxWait is the maximum number of external clocks to wait
+//! if a FIFO ready signal is holding off the transaction.
+//!
+//! This function is used to configure the interface when used in Host-bus 16
+//! operation as chosen with the function EPIModeSet(). The parameter
+//! \e ulConfig is the logical OR of any of the following:
+//!
+//! - one of \b EPI_HB16_MODE_ADMUX, \b EPI_HB16_MODE_ADDEMUX,
+//! \b EPI_HB16_MODE_SRAM, or \b EPI_HB16_MODE_FIFO to select the HB16 mode
+//! - \b EPI_HB16_USE_TXEMPTY - enable TXEMPTY signal with FIFO
+//! - \b EPI_HB16_USE_RXFULL - enable RXFULL signal with FIFO
+//! - \b EPI_HB16_WRHIGH - use active high write strobe, otherwise it is
+//! active low
+//! - \b EPI_HB16_RDHIGH - use active high read strobe, otherwise it is
+//! active low
+//! - one of \b EPI_HB16_WRWAIT_0, \b EPI_HB16_WRWAIT_1, \b EPI_HB16_WRWAIT_2,
+//! or \b EPI_HB16_WRWAIT_3 to select the number of write wait states (default
+//! is 0 wait states)
+//! - one of \b EPI_HB16_RDWAIT_0, \b EPI_HB16_RDWAIT_1, \b EPI_HB16_RDWAIT_2,
+//! or \b EPI_HB16_RDWAIT_3 to select the number of read wait states (default
+//! is 0 wait states)
+//! - \b EPI_HB16_WORD_ACCESS - use Word Access mode to route bytes to the
+//! correct byte lanes allowing data to be stored in bits [31:8]. If absent,
+//! all data transfers use bits [7:0].
+//! - \b EPI_HB16_BSEL - enables byte selects. In this mode, two EPI signals
+//! operate as byte selects allowing 8-bit transfers. If this flag is not
+//! specified, data must be read and written using only 16-bit transfers.
+//! - \b EPI_HB16_CSBAUD_DUAL - use different baud rates when accessing devices
+//! on each CSn. CS0n uses the baud rate specified by the lower 16 bits of the
+//! divider passed to EPIDividerSet() and CS1n uses the divider passed in the
+//! upper 16 bits. If this option is absent, both chip selects use the baud
+//! rate resulting from the divider in the lower 16 bits of the parameter passed
+//! to EPIDividerSet().
+//! - one of \b EPI_HB16_CSCFG_CS, \b EPI_HB16_CSCFG_ALE,
+//! \b EPI_HB16_CSCFG_DUAL_CS or \b EPI_HB16_CSCFG_ALE_DUAL_CS. \b
+//! EPI_HB16_CSCFG_CS sets EPI30 to operate as a Chip Select (CSn) signal. \b
+//! EPI_HB16_CSCFG_ALE sets EPI30 to operate as an address latch (ALE).
+//! \b EPI_HB16_CSCFG_DUAL_CS sets EPI30 to operate as CS0n and EPI27 as CS1n
+//! with the asserted chip select determined from the most significant address
+//! bit for the respective external address map. \b EPI_HB16_CSCFG_ALE_DUAL_CS
+//! sets EPI30 as an address latch (ALE), EPI27 as CS0n and EPI26 as CS1n with
+//! the asserted chip select determined from the most significant address bit
+//! for the respective external address map.
+//!
+//! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a
+//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this
+//! parameter determines the maximum number of clocks to wait when the
+//! transaction is being held off by by the FIFO using one of these ready
+//! signals. A value of 0 means to wait forever.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulMaxWait)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulMaxWait < 256);
+
+ //
+ // Determine the CS and word access modes.
+ //
+ HWREG(ulBase + EPI_O_HB16CFG2) = (((ulConfig & EPI_HB16_WORD_ACCESS) ?
+ EPI_HB16CFG2_WORD : 0) |
+ ((ulConfig & EPI_HB16_CSBAUD_DUAL) ?
+ EPI_HB16CFG2_CSBAUD : 0) |
+ ((ulConfig & EPI_HB16_CSCFG_MASK) << 15));
+
+ //
+ // Fill in the max wait field of the configuration word.
+ //
+ ulConfig &= ~EPI_HB16CFG_MAXWAIT_M;
+ ulConfig |= ulMaxWait << EPI_HB16CFG_MAXWAIT_S;
+
+ //
+ // Write the main HostBus16 configuration register.
+ //
+ HWREG(ulBase + EPI_O_HB16CFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Configures the interface for general-purpose mode operation.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulConfig is the interface configuration.
+//! \param ulFrameCount is the frame size in clocks, if the frame signal
+//! is used (0-15).
+//! \param ulMaxWait is the maximum number of external clocks to wait
+//! when the external clock enable is holding off the transaction (0-255).
+//!
+//! This function is used to configure the interface when used in
+//! general-purpose operation as chosen with the function EPIModeSet(). The
+//! parameter
+//! \e ulConfig is the logical OR of any of the following:
+//!
+//! - \b EPI_GPMODE_CLKPIN - interface clock is output on a pin
+//! - \b EPI_GPMODE_CLKGATE - clock is stopped when there is no transaction,
+//! otherwise it is free-running
+//! - \b EPI_GPMODE_RDYEN - the external peripheral drives an iRDY signal into
+//! pin EPI0S27. If absent, the peripheral is assumed to be ready at all times.
+//! This flag may only be used with a free-running clock (\b EPI_GPMODE_CLKGATE
+//! is absent).
+//! - \b EPI_GPMODE_FRAMEPIN - framing signal is emitted on a pin
+//! - \b EPI_GPMODE_FRAME50 - framing signal is 50/50 duty cycle, otherwise it
+//! is a pulse
+//! - \b EPI_GPMODE_READWRITE - read and write strobes are emitted on pins
+//! - \b EPI_GPMODE_WRITE2CYCLE - a two cycle write is used, otherwise a
+//! single-cycle write is used
+//! - \b EPI_GPMODE_READ2CYCLE - a two cycle read is used, otherwise a
+//! single-cycle read is used
+//! - \b EPI_GPMODE_ASIZE_NONE, \b EPI_GPMODE_ASIZE_4,
+//! \b EPI_GPMODE_ASIZE_12, or \b EPI_GPMODE_ASIZE_20 to choose no address
+//! bus, or and address bus size of 4, 12, or 20 bits
+//! - \b EPI_GPMODE_DSIZE_8, \b EPI_GPMODE_DSIZE_16,
+//! \b EPI_GPMODE_DSIZE_24, or \b EPI_GPMODE_DSIZE_32 to select a data bus
+//! size of 8, 16, 24, or 32 bits
+//! - \b EPI_GPMODE_WORD_ACCESS - use Word Access mode to route bytes to the
+//! correct byte lanes allowing data to be stored in the upper bits of the word
+//! when necessary.
+//!
+//! The parameter \e ulFrameCount is the number of clocks used to form the
+//! framing signal, if the framing signal is used. The behavior depends on
+//! whether the frame signal is a pulse or a 50/50 duty cycle. This value
+//! is not used if the framing signal is not enabled with the option
+//! \b EPI_GPMODE_FRAMEPIN.
+//!
+//! The parameter \e ulMaxWait is used if the external clock enable is turned
+//! on with the \b EPI_GPMODE_CLKENA option is used. In the case that
+//! external clock enable is used, this parameter determines the maximum
+//! number of clocks to wait when the external clock enable signal is holding
+//! off a transaction. A value of 0 means to wait forever. If a non-zero
+//! value is used and exceeded, an interrupt will occur and the transaction
+//! aborted.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIConfigGPModeSet(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulFrameCount, unsigned long ulMaxWait)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulFrameCount < 16);
+ ASSERT(ulMaxWait < 256);
+
+ //
+ // Set the word access mode.
+ //
+ HWREG(ulBase + EPI_O_GPCFG2) = ((ulConfig & EPI_GPMODE_WORD_ACCESS) ?
+ EPI_GPCFG2_WORD : 0);
+
+ //
+ // Fill in the frame count field of the configuration word.
+ //
+ ulConfig &= ~EPI_GPCFG_FRMCNT_M;
+ ulConfig |= ulFrameCount << EPI_GPCFG_FRMCNT_S;
+
+ //
+ // Fill in the max wait field of the configuration word.
+ //
+ ulConfig &= ~EPI_GPCFG_MAXWAIT_M;
+ ulConfig |= ulMaxWait << EPI_GPCFG_MAXWAIT_S;
+
+ //
+ // Write the non-moded configuration register.
+ //
+ HWREG(ulBase + EPI_O_GPCFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Configures the address map for the external interface.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulMap is the address mapping configuration.
+//!
+//! This function is used to configure the address mapping for the external
+//! interface. This determines the base address of the external memory or
+//! device within the processor peripheral and/or memory space.
+//!
+//! The parameter \e ulMap is the logical OR of the following:
+//!
+//! - \b EPI_ADDR_PER_SIZE_256B, \b EPI_ADDR_PER_SIZE_64KB,
+//! \b EPI_ADDR_PER_SIZE_16MB, or \b EPI_ADDR_PER_SIZE_512MB to choose a
+//! peripheral address space of 256 bytes, 64 Kbytes, 16 Mbytes or 512 Mbytes
+//! - \b EPI_ADDR_PER_BASE_NONE, \b EPI_ADDR_PER_BASE_A, or
+//! \b EPI_ADDR_PER_BASE_C to choose the base address of the peripheral
+//! space as none, 0xA0000000, or 0xC0000000
+//! - \b EPI_ADDR_RAM_SIZE_256B, \b EPI_ADDR_RAM_SIZE_64KB,
+//! \b EPI_ADDR_RAM_SIZE_16MB, or \b EPI_ADDR_RAM_SIZE_512MB to choose a
+//! RAM address space of 256 bytes, 64 Kbytes, 16 Mbytes or 512 Mbytes
+//! - \b EPI_ADDR_RAM_BASE_NONE, \b EPI_ADDR_RAM_BASE_6, or
+//! \b EPI_ADDR_RAM_BASE_8 to choose the base address of the RAM space
+//! as none, 0x60000000, or 0x80000000
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulMap < 0x100);
+
+ //
+ // Set the value of the address mapping register.
+ //
+ HWREG(ulBase + EPI_O_ADDRMAP) = ulMap;
+}
+
+//*****************************************************************************
+//
+//! Configures a non-blocking read transaction.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulChannel is the read channel (0 or 1).
+//! \param ulDataSize is the size of the data items to read.
+//! \param ulAddress is the starting address to read.
+//!
+//! This function is used to configure a non-blocking read channel for a
+//! transaction. Two channels are available which can be used in a ping-pong
+//! method for continuous reading. It is not necessary to use both channels
+//! to perform a non-blocking read.
+//!
+//! The parameter \e ulDataSize is one of \b EPI_NBCONFIG_SIZE_8,
+//! \b EPI_NBCONFIG_SIZE_16, or \b EPI_NBCONFIG_SIZE_32 for 8-bit, 16-bit,
+//! or 32-bit sized data transfers.
+//!
+//! The parameter \e ulAddress is the starting address for the read, relative
+//! to the external device. The start of the device is address 0.
+//!
+//! Once configured, the non-blocking read is started by calling
+//! EPINonBlockingReadStart(). If the addresses to be read from the device
+//! are in a sequence, it is not necessary to call this function multiple
+//! times. Until it is changed, the EPI module will remember the last address
+//! that was used for a non-blocking read (per channel).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel,
+ unsigned long ulDataSize, unsigned long ulAddress)
+{
+ unsigned long ulOffset;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulChannel < 2);
+ ASSERT(ulDataSize < 4);
+ ASSERT(ulAddress < 0x20000000);
+
+ //
+ // Compute the offset needed to select the correct channel regs.
+ //
+ ulOffset = ulChannel * (EPI_O_RSIZE1 - EPI_O_RSIZE0);
+
+ //
+ // Write the data size register for the channel.
+ //
+ HWREG(ulBase + EPI_O_RSIZE0 + ulOffset) = ulDataSize;
+
+ //
+ // Write the starting address register for the channel.
+ //
+ HWREG(ulBase + EPI_O_RADDR0 + ulOffset) = ulAddress;
+}
+
+//*****************************************************************************
+//
+//! Starts a non-blocking read transaction.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulChannel is the read channel (0 or 1).
+//! \param ulCount is the number of items to read (1-4095).
+//!
+//! This function starts a non-blocking read that was previously configured
+//! with the function EPINonBlockingReadConfigure(). Once this function is
+//! called, the EPI module will begin reading data from the external device
+//! into the read FIFO. The EPI will stop reading when the FIFO fills up
+//! and resume reading when the application drains the FIFO, until the
+//! total specified count of data items has been read.
+//!
+//! Once a read transaction is completed and the FIFO drained, another
+//! transaction can be started from the next address by calling this
+//! function again.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPINonBlockingReadStart(unsigned long ulBase, unsigned long ulChannel,
+ unsigned long ulCount)
+{
+ unsigned long ulOffset;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulChannel < 2);
+ ASSERT(ulCount < 4096);
+
+ //
+ // Compute the offset needed to select the correct channel regs.
+ //
+ ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
+
+ //
+ // Write to the read count register.
+ //
+ HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = ulCount;
+}
+
+//*****************************************************************************
+//
+//! Stops a non-blocking read transaction.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulChannel is the read channel (0 or 1).
+//!
+//! This function cancels a non-blocking read transaction that is already
+//! in progress.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel)
+{
+ unsigned long ulOffset;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulChannel < 2);
+
+ //
+ // Compute the offset needed to select the correct channel regs.
+ //
+ ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
+
+ //
+ // Write a 0 to the read count register, which will cancel the transaction.
+ //
+ HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = 0;
+}
+
+//*****************************************************************************
+//
+//! Get the count remaining for a non-blocking transaction.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulChannel is the read channel (0 or 1).
+//!
+//! This function gets the remaining count of items for a non-blocking read
+//! transaction.
+//!
+//! \return The number of items remaining in the non-blocking read transaction.
+//
+//*****************************************************************************
+unsigned long
+EPINonBlockingReadCount(unsigned long ulBase, unsigned long ulChannel)
+{
+ unsigned long ulOffset;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulChannel < 2);
+
+ //
+ // Compute the offset needed to select the correct channel regs.
+ //
+ ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
+
+ //
+ // Read the count remaining and return the value to the caller.
+ //
+ return(HWREG(ulBase + EPI_O_RPSTD0 + ulOffset));
+}
+
+//*****************************************************************************
+//
+//! Get the count of items available in the read FIFO.
+//!
+//! \param ulBase is the EPI module base address.
+//!
+//! This function gets the number of items that are available to read in
+//! the read FIFO. The read FIFO is filled by a non-blocking read transaction
+//! which is configured by the functions EPINonBlockingReadConfigure() and
+//! EPINonBlockingReadStart().
+//!
+//! \return The number of items available to read in the read FIFO.
+//
+//*****************************************************************************
+unsigned long
+EPINonBlockingReadAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+
+ //
+ // Read the FIFO count and return it to the caller.
+ //
+ return(HWREG(ulBase + EPI_O_RFIFOCNT));
+}
+
+//*****************************************************************************
+//
+//! Read available data from the read FIFO, as 32-bit data items.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulCount is the maximum count of items to read.
+//! \param pulBuf is the caller supplied buffer where the read data should
+//! be stored.
+//!
+//! This function reads 32-bit data items from the read FIFO and stores
+//! the values in a caller supplied buffer. The function will read and store
+//! data from the FIFO until there is no more data in the FIFO or the maximum
+//! count is reached as specified in the parameter \e ulCount. The actual
+//! count of items will be returned.
+//!
+//! \return The number of items read from the FIFO.
+//
+//*****************************************************************************
+unsigned long
+EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount,
+ unsigned long *pulBuf)
+{
+ unsigned long ulCountRead = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulCount < 4096);
+ ASSERT(pulBuf);
+
+ //
+ // Read from the FIFO while there are any items to read, and
+ // the callers specified count is not exceeded.
+ //
+ while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
+ {
+ //
+ // Read from the FIFO and store in the caller supplied buffer.
+ //
+ *pulBuf = HWREG(ulBase + EPI_O_READFIFO);
+
+ //
+ // Update the caller's buffer pointer and the count of items read.
+ //
+ pulBuf++;
+ ulCountRead++;
+ }
+
+ //
+ // Return the count of items read to the caller.
+ //
+ return(ulCountRead);
+}
+
+//*****************************************************************************
+//
+//! Read available data from the read FIFO, as 16-bit data items.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulCount is the maximum count of items to read.
+//! \param pusBuf is the caller supplied buffer where the read data should
+//! be stored.
+//!
+//! This function reads 16-bit data items from the read FIFO and stores
+//! the values in a caller supplied buffer. The function will read and store
+//! data from the FIFO until there is no more data in the FIFO or the maximum
+//! count is reached as specified in the parameter \e ulCount. The actual
+//! count of items will be returned.
+//!
+//! \return The number of items read from the FIFO.
+//
+//*****************************************************************************
+unsigned long
+EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount,
+ unsigned short *pusBuf)
+{
+ unsigned long ulCountRead = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulCount < 4096);
+ ASSERT(pusBuf);
+
+ //
+ // Read from the FIFO while there are any items to read, and
+ // the callers specified count is not exceeded.
+ //
+ while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
+ {
+ //
+ // Read from the FIFO and store in the caller supplied buffer.
+ //
+ *pusBuf = (unsigned short)HWREG(ulBase + EPI_O_READFIFO);
+
+ //
+ // Update the caller's buffer pointer and the count of items read.
+ //
+ pusBuf++;
+ ulCountRead++;
+ }
+
+ //
+ // Return the count of items read to the caller.
+ //
+ return(ulCountRead);
+}
+
+//*****************************************************************************
+//
+//! Read available data from the read FIFO, as 8-bit data items.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulCount is the maximum count of items to read.
+//! \param pucBuf is the caller supplied buffer where the read data should
+//! be stored.
+//!
+//! This function reads 8-bit data items from the read FIFO and stores
+//! the values in a caller supplied buffer. The function will read and store
+//! data from the FIFO until there is no more data in the FIFO or the maximum
+//! count is reached as specified in the parameter \e ulCount. The actual
+//! count of items will be returned.
+//!
+//! \return The number of items read from the FIFO.
+//
+//*****************************************************************************
+unsigned long
+EPINonBlockingReadGet8(unsigned long ulBase, unsigned long ulCount,
+ unsigned char *pucBuf)
+{
+ unsigned long ulCountRead = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulCount < 4096);
+ ASSERT(pucBuf);
+
+ //
+ // Read from the FIFO while there are any items to read, and
+ // the callers specified count is not exceeded.
+ //
+ while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
+ {
+ //
+ // Read from the FIFO and store in the caller supplied buffer.
+ //
+ *pucBuf = (unsigned char)HWREG(ulBase + EPI_O_READFIFO);
+
+ //
+ // Update the caller's buffer pointer and the count of items read.
+ //
+ pucBuf++;
+ ulCountRead++;
+ }
+
+ //
+ // Return the count of items read to the caller.
+ //
+ return(ulCountRead);
+}
+
+//*****************************************************************************
+//
+//! Configures the read FIFO.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulConfig is the FIFO configuration.
+//!
+//! This function configures the FIFO trigger levels and error
+//! generation. The parameter \e ulConfig is the logical OR of the
+//! following:
+//!
+//! - \b EPI_FIFO_CONFIG_WTFULLERR - enables an error interrupt when a write is
+//! attempted and the write FIFO is full
+//! - \b EPI_FIFO_CONFIG_RSTALLERR - enables an error interrupt when a read is
+//! stalled due to an interleaved write or other reason
+//! - \b EPI_FIFO_CONFIG_TX_EMPTY, \b EPI_FIFO_CONFIG_TX_1_4,
+//! \b EPI_FIFO_CONFIG_TX_1_2, or \b EPI_FIFO_CONFIG_TX_3_4 to set the
+//! TX FIFO trigger level to empty, 1/4, 1/2, or 3/4 level
+//! - \b EPI_FIFO_CONFIG_RX_1_8, \b EPI_FIFO_CONFIG_RX_1_4,
+//! \b EPI_FIFO_CONFIG_RX_1_2, \b EPI_FIFO_CONFIG_RX_3_4,
+//! \b EPI_FIFO_CONFIG_RX_7_8, or \b EPI_FIFO_CONFIG_RX_FULL to set the
+//! RX FIFO trigger level to 1/8, 1/4, 1/2, 3/4, 7/8 or full level
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulConfig == (ulConfig & 0x00030077));
+
+ //
+ // Load the configuration into the FIFO config reg.
+ //
+ HWREG(ulBase + EPI_O_FIFOLVL) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Reads the number of empty slots in the write transaction FIFO.
+//!
+//! \param ulBase is the EPI module base address.
+//!
+//! This function returns the number of slots available in the transaction
+//! FIFO. It can be used in a polling method to avoid attempting a write
+//! that would stall.
+//!
+//! \return The number of empty slots in the transaction FIFO.
+//
+//*****************************************************************************
+unsigned long
+EPIWriteFIFOCountGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+
+ //
+ // Read the FIFO count and return it to the caller.
+ //
+ return(HWREG(ulBase + EPI_O_WFIFOCNT));
+}
+
+//*****************************************************************************
+//
+//! Enables EPI interrupt sources.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the specified EPI sources to generate interrupts.
+//! The \e ulIntFlags parameter can be the logical OR of any of the following
+//! values:
+//!
+//! - \b EPI_INT_TXREQ - transmit FIFO is below the trigger level
+//! - \b EPI_INT_RXREQ - read FIFO is above the trigger level
+//! - \b EPI_INT_ERR - an error condition occurred
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulIntFlags < 16);
+
+ //
+ // Write the interrupt flags mask to the mask register.
+ //
+ HWREG(ulBase + EPI_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables EPI interrupt sources.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the specified EPI sources for interrupt
+//! generation. The \e ulIntFlags parameter can be the logical OR
+//! of any of the following values: \b EPI_INT_RXREQ, \b EPI_INT_TXREQ, or
+//! \b I2S_INT_ERR.
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulIntFlags < 16);
+
+ //
+ // Write the interrupt flags mask to the mask register.
+ //
+ HWREG(ulBase + EPI_O_IM) &= ~ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the EPI interrupt status.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param bMasked is set \b true to get the masked interrupt status, or
+//! \b false to get the raw interrupt status.
+//!
+//! This function returns the EPI interrupt status. It can return either
+//! the raw or masked interrupt status.
+//!
+//! \return Returns the masked or raw EPI interrupt status, as a bit field
+//! of any of the following values: \b EPI_INT_TXREQ, \b EPI_INT_RXREQ,
+//! or \b EPI_INT_ERR
+//
+//*****************************************************************************
+unsigned long
+EPIIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + EPI_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + EPI_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the EPI error interrupt status.
+//!
+//! \param ulBase is the EPI module base address.
+//!
+//! This function returns the error status of the EPI. If the return value of
+//! the function EPIIntStatus() has the flag \b EPI_INT_ERR set, then this
+//! function can be used to determine the cause of the error.
+//!
+//! This function returns a bit mask of error flags, which can be the logical
+//! OR of any of the following:
+//!
+//! - \b EPI_INT_ERR_WTFULL - occurs when a write stalled when the transaction
+//! FIFO was full
+//! - \b EPI_INT_ERR_RSTALL - occurs when a read stalled
+//! - \b EPI_INT_ERR_TIMEOUT - occurs when the external clock enable held
+//! off a transaction longer than the configured maximum wait time
+//!
+//! \return Returns the interrupt error flags as the logical OR of any of
+//! the following: \b EPI_INT_ERR_WTFULL, \b EPI_INT_ERR_RSTALL, or
+//! \b EPI_INT_ERR_TIMEOUT.
+//
+//*****************************************************************************
+unsigned long
+EPIIntErrorStatus(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+
+ //
+ // Read the error status and return to caller.
+ //
+ return(HWREG(ulBase + EPI_O_EISC));
+}
+
+//*****************************************************************************
+//
+//! Clears pending EPI error sources.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param ulErrFlags is a bit mask of the error sources to be cleared.
+//!
+//! This function clears the specified pending EPI errors. The \e ulErrFlags
+//! parameter can be the logical OR of any of the following values:
+//! \b EPI_INT_ERR_WTFULL, \b EPI_INT_ERR_RSTALL, or \b EPI_INT_ERR_TIMEOUT.
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(ulErrFlags < 16);
+
+ //
+ // Write the error flags to the register to clear the pending errors.
+ //
+ HWREG(ulBase + EPI_O_EISC) = ulErrFlags;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the EPI module.
+//!
+//! \param ulBase is the EPI module base address.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! This sets and enables the handler to be called when the EPI module
+//! generates an interrupt. Specific EPI interrupts must still be enabled
+//! with the EPIIntEnable() function.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+ ASSERT(pfnHandler);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_EPI0, pfnHandler);
+
+ //
+ // Enable the EPI interface interrupt.
+ //
+ IntEnable(INT_EPI0);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the EPI module.
+//!
+//! \param ulBase is the EPI module base address.
+//!
+//! This function will disable and clear the handler to be called when the
+//! EPI interrupt occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EPIIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == EPI0_BASE);
+
+ //
+ // Disable the EPI interface interrupt.
+ //
+ IntDisable(INT_EPI0);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_EPI0);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/epi.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/epi.h
new file mode 100644
index 00000000..44ccb4dc
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/epi.h
@@ -0,0 +1,304 @@
+//*****************************************************************************
+//
+// epi.h - Prototypes and macros for the EPI module.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __EPI_H__
+#define __EPI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIModeSet()
+//
+//*****************************************************************************
+#define EPI_MODE_GENERAL 0x00000010
+#define EPI_MODE_SDRAM 0x00000011
+#define EPI_MODE_HB8 0x00000012
+#define EPI_MODE_HB16 0x00000013
+#define EPI_MODE_DISABLE 0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigSDRAMSet()
+//
+//*****************************************************************************
+#define EPI_SDRAM_CORE_FREQ_0_15 0x00000000
+#define EPI_SDRAM_CORE_FREQ_15_30 0x40000000
+#define EPI_SDRAM_CORE_FREQ_30_50 0x80000000
+#define EPI_SDRAM_CORE_FREQ_50_100 0xC0000000
+#define EPI_SDRAM_LOW_POWER 0x00000200
+#define EPI_SDRAM_FULL_POWER 0x00000000
+#define EPI_SDRAM_SIZE_64MBIT 0x00000000
+#define EPI_SDRAM_SIZE_128MBIT 0x00000001
+#define EPI_SDRAM_SIZE_256MBIT 0x00000002
+#define EPI_SDRAM_SIZE_512MBIT 0x00000003
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigGPModeSet()
+//
+//*****************************************************************************
+#define EPI_GPMODE_CLKPIN 0x80000000
+#define EPI_GPMODE_CLKGATE 0x40000000
+#define EPI_GPMODE_RDYEN 0x10000000
+#define EPI_GPMODE_FRAMEPIN 0x08000000
+#define EPI_GPMODE_FRAME50 0x04000000
+#define EPI_GPMODE_READWRITE 0x00200000
+#define EPI_GPMODE_WRITE2CYCLE 0x00080000
+#define EPI_GPMODE_READ2CYCLE 0x00040000
+#define EPI_GPMODE_ASIZE_NONE 0x00000000
+#define EPI_GPMODE_ASIZE_4 0x00000010
+#define EPI_GPMODE_ASIZE_12 0x00000020
+#define EPI_GPMODE_ASIZE_20 0x00000030
+#define EPI_GPMODE_DSIZE_8 0x00000000
+#define EPI_GPMODE_DSIZE_16 0x00000001
+#define EPI_GPMODE_DSIZE_24 0x00000002
+#define EPI_GPMODE_DSIZE_32 0x00000003
+#define EPI_GPMODE_WORD_ACCESS 0x00000100
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigHB8ModeSet()
+//
+//*****************************************************************************
+#define EPI_HB8_USE_TXEMPTY 0x00800000
+#define EPI_HB8_USE_RXFULL 0x00400000
+#define EPI_HB8_WRHIGH 0x00200000
+#define EPI_HB8_RDHIGH 0x00100000
+#define EPI_HB8_WRWAIT_0 0x00000000
+#define EPI_HB8_WRWAIT_1 0x00000040
+#define EPI_HB8_WRWAIT_2 0x00000080
+#define EPI_HB8_WRWAIT_3 0x000000C0
+#define EPI_HB8_RDWAIT_0 0x00000000
+#define EPI_HB8_RDWAIT_1 0x00000010
+#define EPI_HB8_RDWAIT_2 0x00000020
+#define EPI_HB8_RDWAIT_3 0x00000030
+#define EPI_HB8_MODE_ADMUX 0x00000000
+#define EPI_HB8_MODE_ADDEMUX 0x00000001
+#define EPI_HB8_MODE_SRAM 0x00000002
+#define EPI_HB8_MODE_FIFO 0x00000003
+#define EPI_HB8_WORD_ACCESS 0x00000100
+#define EPI_HB8_CSCFG_ALE 0x00000000
+#define EPI_HB8_CSCFG_CS 0x00000200
+#define EPI_HB8_CSCFG_DUAL_CS 0x00000400
+#define EPI_HB8_CSCFG_ALE_DUAL_CS 0x00000600
+#define EPI_HB8_CSBAUD_DUAL 0x00000800
+
+#define EPI_HB8_CSCFG_MASK 0x00000600
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigHB16ModeSet()
+//
+//*****************************************************************************
+#define EPI_HB16_USE_TXEMPTY 0x00800000
+#define EPI_HB16_USE_RXFULL 0x00400000
+#define EPI_HB16_WRHIGH 0x00200000
+#define EPI_HB16_RDHIGH 0x00100000
+#define EPI_HB16_WRWAIT_0 0x00000000
+#define EPI_HB16_WRWAIT_1 0x00000040
+#define EPI_HB16_WRWAIT_2 0x00000080
+#define EPI_HB16_WRWAIT_3 0x000000C0
+#define EPI_HB16_RDWAIT_0 0x00000000
+#define EPI_HB16_RDWAIT_1 0x00000010
+#define EPI_HB16_RDWAIT_2 0x00000020
+#define EPI_HB16_RDWAIT_3 0x00000030
+#define EPI_HB16_MODE_ADMUX 0x00000000
+#define EPI_HB16_MODE_ADDEMUX 0x00000001
+#define EPI_HB16_MODE_SRAM 0x00000002
+#define EPI_HB16_MODE_FIFO 0x00000003
+#define EPI_HB16_BSEL 0x00000004
+#define EPI_HB16_WORD_ACCESS 0x00000100
+#define EPI_HB16_CSCFG_ALE 0x00000000
+#define EPI_HB16_CSCFG_CS 0x00000200
+#define EPI_HB16_CSCFG_DUAL_CS 0x00000400
+#define EPI_HB16_CSCFG_ALE_DUAL_CS 0x00000600
+#define EPI_HB16_CSBAUD_DUAL 0x00000800
+
+#define EPI_HB16_CSCFG_MASK 0x00000600
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIConfigSDRAMSet()
+//
+//*****************************************************************************
+#define EPI_ADDR_PER_SIZE_256B 0x00000000
+#define EPI_ADDR_PER_SIZE_64KB 0x00000040
+#define EPI_ADDR_PER_SIZE_16MB 0x00000080
+#define EPI_ADDR_PER_SIZE_256MB 0x000000C0
+#define EPI_ADDR_PER_BASE_NONE 0x00000000
+#define EPI_ADDR_PER_BASE_A 0x00000010
+#define EPI_ADDR_PER_BASE_C 0x00000020
+#define EPI_ADDR_RAM_SIZE_256B 0x00000000
+#define EPI_ADDR_RAM_SIZE_64KB 0x00000004
+#define EPI_ADDR_RAM_SIZE_16MB 0x00000008
+#define EPI_ADDR_RAM_SIZE_256MB 0x0000000C
+#define EPI_ADDR_RAM_BASE_NONE 0x00000000
+#define EPI_ADDR_RAM_BASE_6 0x00000001
+#define EPI_ADDR_RAM_BASE_8 0x00000002
+
+//*****************************************************************************
+//
+// Values that can be passed to EPINonBlockingReadConfigure()
+//
+//*****************************************************************************
+#define EPI_NBCONFIG_SIZE_8 1
+#define EPI_NBCONFIG_SIZE_16 2
+#define EPI_NBCONFIG_SIZE_32 3
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIFIFOConfig()
+//
+//*****************************************************************************
+#define EPI_FIFO_CONFIG_WTFULLERR 0x00020000
+#define EPI_FIFO_CONFIG_RSTALLERR 0x00010000
+#define EPI_FIFO_CONFIG_TX_EMPTY 0x00000000
+#define EPI_FIFO_CONFIG_TX_1_4 0x00000020
+#define EPI_FIFO_CONFIG_TX_1_2 0x00000030
+#define EPI_FIFO_CONFIG_TX_3_4 0x00000040
+#define EPI_FIFO_CONFIG_RX_1_8 0x00000001
+#define EPI_FIFO_CONFIG_RX_1_4 0x00000002
+#define EPI_FIFO_CONFIG_RX_1_2 0x00000003
+#define EPI_FIFO_CONFIG_RX_3_4 0x00000004
+#define EPI_FIFO_CONFIG_RX_7_8 0x00000005
+#define EPI_FIFO_CONFIG_RX_FULL 0x00000006
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIIntEnable(), EPIIntDisable(), or returned
+// as flags from EPIIntStatus()
+//
+//*****************************************************************************
+#define EPI_INT_TXREQ 0x00000004
+#define EPI_INT_RXREQ 0x00000002
+#define EPI_INT_ERR 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to EPIIntErrorClear(), or returned as flags from
+// EPIIntErrorStatus()
+//
+//*****************************************************************************
+#define EPI_INT_ERR_WTFULL 0x00000004
+#define EPI_INT_ERR_RSTALL 0x00000002
+#define EPI_INT_ERR_TIMEOUT 0x00000001
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void EPIModeSet(unsigned long ulBase, unsigned long ulMode);
+extern void EPIDividerSet(unsigned long ulBase, unsigned long ulDivider);
+extern void EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulRefresh);
+extern void EPIConfigGPModeSet(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulFrameCount,
+ unsigned long ulMaxWait);
+extern void EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulMaxWait);
+extern void EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulMaxWait);
+extern void EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap);
+extern void EPINonBlockingReadConfigure(unsigned long ulBase,
+ unsigned long ulChannel,
+ unsigned long ulDataSize,
+ unsigned long ulAddress);
+extern void EPINonBlockingReadStart(unsigned long ulBase,
+ unsigned long ulChannel,
+ unsigned long ulCount);
+extern void EPINonBlockingReadStop(unsigned long ulBase,
+ unsigned long ulChannel);
+extern unsigned long EPINonBlockingReadCount(unsigned long ulBase,
+ unsigned long ulChannel);
+extern unsigned long EPINonBlockingReadAvail(unsigned long ulBase);
+extern unsigned long EPINonBlockingReadGet32(unsigned long ulBase,
+ unsigned long ulCount,
+ unsigned long *pulBuf);
+extern unsigned long EPINonBlockingReadGet16(unsigned long ulBase,
+ unsigned long ulCount,
+ unsigned short *pusBuf);
+extern unsigned long EPINonBlockingReadGet8(unsigned long ulBase,
+ unsigned long ulCount,
+ unsigned char *pucBuf);
+extern void EPIFIFOConfig(unsigned long ulBase, unsigned long ulConfig);
+extern unsigned long EPIWriteFIFOCountGet(unsigned long ulBase);
+extern void EPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void EPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long EPIIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern unsigned long EPIIntErrorStatus(unsigned long ulBase);
+extern void EPIIntErrorClear(unsigned long ulBase, unsigned long ulErrFlags);
+extern void EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern void EPIIntUnregister(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several EPI APIs and labels have been renamed, with the original definition
+// name being deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define EPI_MODE_NONE EPI_MODE_GENERAL
+#define EPI_NONMODE_CLKPIN EPI_GPMODE_CLKPIN
+#define EPI_NONMODE_CLKSTOP EPI_GPMODE_CLKGATE
+#define EPI_NONMODE_CLKENA EPI_GPMODE_RDYEN
+#define EPI_NONMODE_FRAMEPIN EPI_GPMODE_FRAMEPIN
+#define EPI_NONMODE_FRAME50 EPI_GPMODE_FRAME50
+#define EPI_NONMODE_READWRITE EPI_GPMODE_READWRITE
+#define EPI_NONMODE_WRITE2CYCLE EPI_GPMODE_WRITE2CYCLE
+#define EPI_NONMODE_READ2CYCLE EPI_GPMODE_READ2CYCLE
+#define EPI_NONMODE_ASIZE_NONE EPI_GPMODE_ASIZE_NONE
+#define EPI_NONMODE_ASIZE_4 EPI_GPMODE_ASIZE_4
+#define EPI_NONMODE_ASIZE_12 EPI_GPMODE_ASIZE_12
+#define EPI_NONMODE_ASIZE_20 EPI_GPMODE_ASIZE_20
+#define EPI_NONMODE_DSIZE_8 EPI_GPMODE_DSIZE_8
+#define EPI_NONMODE_DSIZE_16 EPI_GPMODE_DSIZE_16
+#define EPI_NONMODE_DSIZE_24 EPI_GPMODE_DSIZE_24
+#define EPI_NONMODE_DSIZE_32 EPI_GPMODE_DSIZE_32
+#define EPI_NONMODE_WORD_ACCESS EPI_GPMODE_WORD_ACCESS
+
+#define EPINonBlockingWriteCount(a) EPIWriteFIFOCountGet(a)
+#define EPIConfigNoModeSet(a, b, c, d) EPIConfigGPModeSet((a), (b), (c), (d))
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __EPI_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/ethernet.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/ethernet.c
new file mode 100644
index 00000000..29ade99f
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/ethernet.c
@@ -0,0 +1,1327 @@
+//*****************************************************************************
+//
+// ethernet.c - Driver for the Integrated Ethernet Controller
+//
+// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup ethernet_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ethernet.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/ethernet.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Initializes the Ethernet controller for operation.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulEthClk is the rate of the clock supplied to the Ethernet module.
+//!
+//! This function will prepare the Ethernet controller for first time use in
+//! a given hardware/software configuration. This function should be called
+//! before any other Ethernet API functions are called.
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original EthernetInit() API and performs the
+//! same actions. A macro is provided in ethernet.h to map the
+//! original API to this API.
+//!
+//! \note If the device configuration is changed (for example, the system clock
+//! is reprogrammed to a different speed), then the Ethernet controller must be
+//! disabled by calling the EthernetDisable() function and the controller must
+//! be reinitialized by calling the EthernetInitExpClk() function again. After
+//! the controller has been reinitialized, the controller should be
+//! reconfigured using the appropriate Ethernet API calls.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk)
+{
+ unsigned long ulDiv;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Set the Management Clock Divider register for access to the PHY
+ // register set (via EthernetPHYRead/Write).
+ //
+ // The MDC clock divided down from the system clock using the following
+ // formula. A maximum of 2.5MHz is allowed for F(mdc).
+ //
+ // F(mdc) = F(sys) / (2 * (div + 1))
+ // div = (F(sys) / (2 * F(mdc))) - 1
+ // div = (F(sys) / 2 / F(mdc)) - 1
+ //
+ // Note: Because we should round up, to ensure we don't violate the
+ // maximum clock speed, we can simplify this as follows:
+ //
+ // div = F(sys) / 2 / F(mdc)
+ //
+ // For example, given a system clock of 6.0MHz, and a div value of 1,
+ // the mdc clock would be programmed as 1.5 MHz.
+ //
+ ulDiv = (ulEthClk / 2) / 2500000;
+ HWREG(ulBase + MAC_O_MDV) = (ulDiv & MAC_MDV_DIV_M);
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration of the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulConfig is the configuration for the controller.
+//!
+//! After the EthernetInitExpClk() function has been called, this API function
+//! can be used to configure the various features of the Ethernet controller.
+//!
+//! The Ethernet controller provides three control registers that are used
+//! to configure the controller's operation. The transmit control register
+//! provides settings to enable full duplex operation, to auto-generate the
+//! frame check sequence, and to pad the transmit packets to the minimum
+//! length as required by the IEEE standard. The receive control register
+//! provides settings to enable reception of packets with bad frame check
+//! sequence values and to enable multi-cast or promiscuous modes. The
+//! timestamp control register provides settings that enable support logic in
+//! the controller that allow the use of the General Purpose Timer 3 to capture
+//! timestamps for the transmitted and received packets.
+//!
+//! The \e ulConfig parameter is the logical OR of the following values:
+//!
+//! - \b ETH_CFG_TS_TSEN - Enable TX and RX interrupt status as CCP timer
+//! inputs
+//! - \b ETH_CFG_RX_BADCRCDIS - Disable reception of packets with a bad CRC
+//! - \b ETH_CFG_RX_PRMSEN - Enable promiscuous mode reception (all packets)
+//! - \b ETH_CFG_RX_AMULEN - Enable reception of multicast packets
+//! - \b ETH_CFG_TX_DPLXEN - Enable full duplex transmit mode
+//! - \b ETH_CFG_TX_CRCEN - Enable transmit with auto CRC generation
+//! - \b ETH_CFG_TX_PADEN - Enable padding of transmit data to minimum size
+//!
+//! These bit-mapped values are programmed into the transmit, receive, and/or
+//! timestamp control register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT((ulConfig & ~(ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN |
+ ETH_CFG_TX_PADEN | ETH_CFG_RX_BADCRCDIS |
+ ETH_CFG_RX_PRMSEN | ETH_CFG_RX_AMULEN |
+ ETH_CFG_TS_TSEN)) == 0);
+
+ //
+ // Setup the Transmit Control Register.
+ //
+ ulTemp = HWREG(ulBase + MAC_O_TCTL);
+ ulTemp &= ~(MAC_TCTL_DUPLEX | MAC_TCTL_CRC | MAC_TCTL_PADEN);
+ ulTemp |= ulConfig & 0x0FF;
+ HWREG(ulBase + MAC_O_TCTL) = ulTemp;
+
+ //
+ // Setup the Receive Control Register.
+ //
+ ulTemp = HWREG(ulBase + MAC_O_RCTL);
+ ulTemp &= ~(MAC_RCTL_BADCRC | MAC_RCTL_PRMS | MAC_RCTL_AMUL);
+ ulTemp |= (ulConfig >> 8) & 0x0FF;
+ HWREG(ulBase + MAC_O_RCTL) = ulTemp;
+
+ //
+ // Setup the Time Stamp Configuration register.
+ //
+ ulTemp = HWREG(ulBase + MAC_O_TS);
+ ulTemp &= ~(MAC_TS_TSEN);
+ ulTemp |= (ulConfig >> 16) & 0x0FF;
+ HWREG(ulBase + MAC_O_TS) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration of the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! This function will query the control registers of the Ethernet controller
+//! and return a bit-mapped configuration value.
+//!
+//! \sa The description of the EthernetConfigSet() function provides detailed
+//! information for the bit-mapped configuration values that will be returned.
+//!
+//! \return Returns the bit-mapped Ethernet controller configuration value.
+//
+//*****************************************************************************
+unsigned long
+EthernetConfigGet(unsigned long ulBase)
+{
+ unsigned long ulConfig;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Read and return the Ethernet controller configuration parameters,
+ // properly shifted into the appropriate bit field positions.
+ //
+ ulConfig = HWREG(ulBase + MAC_O_TS) << 16;
+ ulConfig |= (HWREG(ulBase + MAC_O_RCTL) & ~(MAC_RCTL_RXEN)) << 8;
+ ulConfig |= HWREG(ulBase + MAC_O_TCTL) & ~(MAC_TCTL_TXEN);
+ return(ulConfig);
+}
+
+//*****************************************************************************
+//
+//! Sets the MAC address of the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucMACAddr is the pointer to the array of MAC-48 address octets.
+//!
+//! This function will program the IEEE-defined MAC-48 address specified in
+//! \e pucMACAddr into the Ethernet controller. This address is used by the
+//! Ethernet controller for hardware-level filtering of incoming Ethernet
+//! packets (when promiscuous mode is not enabled).
+//!
+//! The MAC-48 address is defined as 6 octets, illustrated by the following
+//! example address. The numbers are shown in hexadecimal format.
+//!
+//! AC-DE-48-00-00-80
+//!
+//! In this representation, the first three octets (AC-DE-48) are the
+//! Organizationally Unique Identifier (OUI). This is a number assigned by
+//! the IEEE to an organization that requests a block of MAC addresses. The
+//! last three octets (00-00-80) are a 24-bit number managed by the OUI owner
+//! to uniquely identify a piece of hardware within that organization that is
+//! to be connected to the Ethernet.
+//!
+//! In this representation, the octets are transmitted from left to right,
+//! with the ``AC'' octet being transmitted first and the ``80'' octet being
+//! transmitted last. Within an octet, the bits are transmitted LSB to MSB.
+//! For this address, the first bit to be transmitted would be ``0'', the LSB
+//! of ``AC'', and the last bit to be transmitted would be ``1'', the MSB of
+//! ``80''.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr)
+{
+ unsigned long ulTemp;
+ unsigned char *pucTemp = (unsigned char *)&ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucMACAddr != 0);
+
+ //
+ // Program the MAC Address into the device. The first four bytes of the
+ // MAC Address are placed into the IA0 register. The remaining two bytes
+ // of the MAC address are placed into the IA1 register.
+ //
+ pucTemp[0] = pucMACAddr[0];
+ pucTemp[1] = pucMACAddr[1];
+ pucTemp[2] = pucMACAddr[2];
+ pucTemp[3] = pucMACAddr[3];
+ HWREG(ulBase + MAC_O_IA0) = ulTemp;
+ ulTemp = 0;
+ pucTemp[0] = pucMACAddr[4];
+ pucTemp[1] = pucMACAddr[5];
+ HWREG(ulBase + MAC_O_IA1) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the MAC address of the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucMACAddr is the pointer to the location in which to store the
+//! array of MAC-48 address octets.
+//!
+//! This function will read the currently programmed MAC address into the
+//! \e pucMACAddr buffer.
+//!
+//! \sa Refer to EthernetMACAddrSet() API description for more details about
+//! the MAC address format.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr)
+{
+ unsigned long ulTemp;
+ unsigned char *pucTemp = (unsigned char *)&ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucMACAddr != 0);
+
+ //
+ // Read the MAC address from the device. The first four bytes of the
+ // MAC address are read from the IA0 register. The remaining two bytes
+ // of the MAC addres
+ //
+ ulTemp = HWREG(ulBase + MAC_O_IA0);
+ pucMACAddr[0] = pucTemp[0];
+ pucMACAddr[1] = pucTemp[1];
+ pucMACAddr[2] = pucTemp[2];
+ pucMACAddr[3] = pucTemp[3];
+ ulTemp = HWREG(ulBase + MAC_O_IA1);
+ pucMACAddr[4] = pucTemp[0];
+ pucMACAddr[5] = pucTemp[1];
+}
+
+//*****************************************************************************
+//
+//! Enables the Ethernet controller for normal operation.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! Once the Ethernet controller has been configured using the
+//! EthernetConfigSet() function and the MAC address has been programmed using
+//! the EthernetMACAddrSet() function, this API function can be called to
+//! enable the controller for normal operation.
+//!
+//! This function will enable the controller's transmitter and receiver, and
+//! will reset the receive FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Reset the receive FIFO.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
+
+ //
+ // Enable the Ethernet receiver.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RXEN;
+
+ //
+ // Enable Ethernet transmitter.
+ //
+ HWREG(ulBase + MAC_O_TCTL) |= MAC_TCTL_TXEN;
+
+ //
+ // Reset the receive FIFO again, after the receiver has been enabled.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
+}
+
+//*****************************************************************************
+//
+//! Disables the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! When terminating operations on the Ethernet interface, this function should
+//! be called. This function will disable the transmitter and receiver, and
+//! will clear out the receive FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Reset the receive FIFO.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
+
+ //
+ // Disable the Ethernet transmitter.
+ //
+ HWREG(ulBase + MAC_O_TCTL) &= ~(MAC_TCTL_TXEN);
+
+ //
+ // Disable the Ethernet receiver.
+ //
+ HWREG(ulBase + MAC_O_RCTL) &= ~(MAC_RCTL_RXEN);
+
+ //
+ // Reset the receive FIFO again, after the receiver has been disabled.
+ //
+ HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
+}
+
+//*****************************************************************************
+//
+//! Check for packet available from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! The Ethernet controller provides a register that contains the number of
+//! packets available in the receive FIFO. When the last bytes of a packet are
+//! successfully received (that is, the frame check sequence bytes), the packet
+//! count is incremented. Once the packet has been fully read (including the
+//! frame check sequence bytes) from the FIFO, the packet count will be
+//! decremented.
+//!
+//! \return Returns \b true if there are one or more packets available in the
+//! receive FIFO, including the current packet being read, and \b false
+//! otherwise.
+//
+//*****************************************************************************
+tBoolean
+EthernetPacketAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Return the availability of packets.
+ //
+ return((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Checks for packet space available in the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! The Ethernet controller's transmit FIFO is designed to support a single
+//! packet at a time. After the packet has been written into the FIFO, the
+//! transmit request bit must be set to enable the transmission of the packet.
+//! Only after the packet has been transmitted can a new packet be written
+//! into the FIFO. This function will simply check to see if a packet is
+//! in progress. If so, there is no space available in the transmit FIFO.
+//!
+//! \return Returns \b true if a space is available in the transmit FIFO, and
+//! \b false otherwise.
+//
+//*****************************************************************************
+tBoolean
+EthernetSpaceAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Return the availability of space.
+ //
+ return((HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Internal function for reading a packet from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is the maximum number of bytes to be read into the buffer.
+//!
+//! Based on the following table of how the receive frame is stored in the
+//! receive FIFO, this function will extract a packet from the FIFO and store
+//! it in the packet buffer that was passed in.
+//!
+//! Format of the data in the RX FIFO is as follows:
+//!
+//! \verbatim
+//! +---------+----------+----------+----------+----------+
+//! | | 31:24 | 23:16 | 15:8 | 7:0 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 0 | DA 2 | DA 1 | FL MSB | FL LSB |
+//! +---------+----------+----------+----------+----------+
+//! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 |
+//! +---------+----------+----------+----------+----------+
+//! | ... | | | | |
+//! +---------+----------+----------+----------+----------+
+//! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 |
+//! +---------+----------+----------+----------+----------+
+//! | Word Y | FCS 4 | FCS 3 | FCS 2 | FCS 1 |
+//! +---------+----------+----------+----------+----------+
+//! \endverbatim
+//!
+//! Where FL is Frame Length, (FL + DA + SA + FT + DATA + FCS) Bytes.
+//! Where DA is Destination (MAC) Address.
+//! Where SA is Source (MAC) Address.
+//! Where FT is Frame Type (or Frame Length for Ethernet).
+//! Where DATA is Payload Data for the Ethernet Frame.
+//! Where FCS is the Frame Check Sequence.
+//!
+//! \return Returns the negated packet length \b -n if the packet is too large
+//! for \e pucBuf, and returns the packet length \b n otherwise.
+//
+//*****************************************************************************
+static long
+EthernetPacketGetInternal(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ unsigned long ulTemp;
+ long lFrameLen, lTempLen;
+ long i = 0;
+
+ //
+ // Read WORD 0 (see format above) from the FIFO, set the receive
+ // Frame Length and store the first two bytes of the destination
+ // address in the receive buffer.
+ //
+ ulTemp = HWREG(ulBase + MAC_O_DATA);
+ lFrameLen = (long)(ulTemp & 0xFFFF);
+ pucBuf[i++] = (unsigned char) ((ulTemp >> 16) & 0xff);
+ pucBuf[i++] = (unsigned char) ((ulTemp >> 24) & 0xff);
+
+ //
+ // Read all but the last WORD into the receive buffer.
+ //
+ lTempLen = (lBufLen < (lFrameLen - 6)) ? lBufLen : (lFrameLen - 6);
+ while(i <= (lTempLen - 4))
+ {
+ *(unsigned long *)&pucBuf[i] = HWREG(ulBase + MAC_O_DATA);
+ i += 4;
+ }
+
+ //
+ // Read the last 1, 2, or 3 BYTES into the buffer
+ //
+ if(i < lTempLen)
+ {
+ ulTemp = HWREG(ulBase + MAC_O_DATA);
+ if(i == lTempLen - 3)
+ {
+ pucBuf[i++] = ((ulTemp >> 0) & 0xff);
+ pucBuf[i++] = ((ulTemp >> 8) & 0xff);
+ pucBuf[i++] = ((ulTemp >> 16) & 0xff);
+ i += 1;
+ }
+ else if(i == lTempLen - 2)
+ {
+ pucBuf[i++] = ((ulTemp >> 0) & 0xff);
+ pucBuf[i++] = ((ulTemp >> 8) & 0xff);
+ i += 2;
+ }
+ else if(i == lTempLen - 1)
+ {
+ pucBuf[i++] = ((ulTemp >> 0) & 0xff);
+ i += 3;
+ }
+ }
+
+ //
+ // Read any remaining WORDS (that did not fit into the buffer).
+ //
+ while(i < (lFrameLen - 2))
+ {
+ ulTemp = HWREG(ulBase + MAC_O_DATA);
+ i += 4;
+ }
+
+ //
+ // If frame was larger than the buffer, return the "negative" frame length
+ //
+ lFrameLen -= 6;
+ if(lFrameLen > lBufLen)
+ {
+ return(-lFrameLen);
+ }
+
+ //
+ // Return the Frame Length
+ //
+ return(lFrameLen);
+}
+
+//*****************************************************************************
+//
+//! Receives a packet from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is the maximum number of bytes to be read into the buffer.
+//!
+//! This function reads a packet from the receive FIFO of the controller and
+//! places it into \e pucBuf. If no packet is available the function will
+//! return immediately. Otherwise, the function will read the entire packet
+//! from the receive FIFO. If there are more bytes in the packet than will fit
+//! into \e pucBuf (as specified by \e lBufLen), the function will return the
+//! negated length of the packet and the buffer will contain \e lBufLen bytes
+//! of the packet. Otherwise, the function will return the length of the
+//! packet that was read and \e pucBuf will contain the entire packet
+//! (excluding the frame check sequence bytes).
+//!
+//! This function replaces the original EthernetPacketNonBlockingGet() API and
+//! performs the same actions. A macro is provided in ethernet.h to
+//! map the original API to this API.
+//!
+//! \note This function will return immediately if no packet is available.
+//!
+//! \return Returns \b 0 if no packet is available, the negated packet length
+//! \b -n if the packet is too large for \e pucBuf, and the packet length \b n
+//! otherwise.
+//
+//*****************************************************************************
+long
+EthernetPacketGetNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucBuf != 0);
+ ASSERT(lBufLen > 0);
+
+ //
+ // Check to see if any packets are available.
+ //
+ if((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0)
+ {
+ return(0);
+ }
+
+ //
+ // Read the packet, and return.
+ //
+ return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen));
+}
+
+//*****************************************************************************
+//
+//! Waits for a packet from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is the maximum number of bytes to be read into the buffer.
+//!
+//! This function reads a packet from the receive FIFO of the controller and
+//! places it into \e pucBuf. The function will wait until a packet is
+//! available in the FIFO. Then the function will read the entire packet
+//! from the receive FIFO. If there are more bytes in the packet than will
+//! fit into \e pucBuf (as specified by \e lBufLen), the function will return
+//! the negated length of the packet and the buffer will contain \e lBufLen
+//! bytes of the packet. Otherwise, the function will return the length of
+//! the packet that was read and \e pucBuf will contain the entire packet
+//! (excluding the frame check sequence bytes).
+//!
+//! \note This function is blocking and will not return until a packet arrives.
+//!
+//! \return Returns the negated packet length \b -n if the packet is too large
+//! for \e pucBuf, and returns the packet length \b n otherwise.
+//
+//*****************************************************************************
+long
+EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucBuf != 0);
+ ASSERT(lBufLen > 0);
+
+ //
+ // Wait for a packet to become available
+ //
+ while((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR_M) == 0)
+ {
+ }
+
+ //
+ // Read the packet
+ //
+ return(EthernetPacketGetInternal(ulBase, pucBuf, lBufLen));
+}
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Internal function for sending a packet to the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is number of bytes in the packet to be transmitted.
+//!
+//! Puts a packet into the transmit FIFO of the controller.
+//!
+//! Format of the data in the TX FIFO is as follows:
+//!
+//! \verbatim
+//! +---------+----------+----------+----------+----------+
+//! | | 31:24 | 23:16 | 15:8 | 7:0 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 0 | DA 2 | DA 1 | PL MSB | PL LSB |
+//! +---------+----------+----------+----------+----------+
+//! | Word 1 | DA 6 | DA 5 | DA 4 | DA 3 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 2 | SA 4 | SA 3 | SA 2 | SA 1 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 3 | FT LSB | FT MSB | SA 6 | SA 5 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 4 | DATA 4 | DATA 3 | DATA 2 | DATA 1 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 5 | DATA 8 | DATA 7 | DATA 6 | DATA 5 |
+//! +---------+----------+----------+----------+----------+
+//! | Word 6 | DATA 12 | DATA 11 | DATA 10 | DATA 9 |
+//! +---------+----------+----------+----------+----------+
+//! | ... | | | | |
+//! +---------+----------+----------+----------+----------+
+//! | Word X | DATA n | DATA n-1 | DATA n-2 | DATA n-3 |
+//! +---------+----------+----------+----------+----------+
+//! \endverbatim
+//!
+//! Where PL is Payload Length, (DATA) only
+//! Where DA is Destination (MAC) Address
+//! Where SA is Source (MAC) Address
+//! Where FT is Frame Type (or Frame Length for Ethernet)
+//! Where DATA is Payload Data for the Ethernet Frame
+//!
+//! \return Returns the negated packet length \b -lBufLen if the packet is too
+//! large for FIFO, and the packet length \b lBufLen otherwise.
+//
+//*****************************************************************************
+static long
+EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ unsigned long ulTemp;
+ long i = 0;
+
+ //
+ // If the packet is too large, return the negative packet length as
+ // an error code.
+ //
+ if(lBufLen > (2048 - 2))
+ {
+ return(-lBufLen);
+ }
+
+ //
+ // Build and write WORD 0 (see format above) to the transmit FIFO.
+ //
+ ulTemp = (unsigned long)(lBufLen - 14);
+ ulTemp |= (pucBuf[i++] << 16);
+ ulTemp |= (pucBuf[i++] << 24);
+ HWREG(ulBase + MAC_O_DATA) = ulTemp;
+
+ //
+ // Write each subsequent WORD n to the transmit FIFO, except for the last
+ // WORD (if the word does not contain 4 bytes).
+ //
+ while(i <= (lBufLen - 4))
+ {
+ HWREG(ulBase + MAC_O_DATA) = *(unsigned long *)&pucBuf[i];
+ i += 4;
+ }
+
+ //
+ // Build the last word of the remaining 1, 2, or 3 bytes, and store
+ // the WORD into the transmit FIFO.
+ //
+ if(i != lBufLen)
+ {
+ if(i == (lBufLen - 3))
+ {
+ ulTemp = (pucBuf[i++] << 0);
+ ulTemp |= (pucBuf[i++] << 8);
+ ulTemp |= (pucBuf[i++] << 16);
+ HWREG(ulBase + MAC_O_DATA) = ulTemp;
+ }
+ else if(i == (lBufLen - 2))
+ {
+ ulTemp = (pucBuf[i++] << 0);
+ ulTemp |= (pucBuf[i++] << 8);
+ HWREG(ulBase + MAC_O_DATA) = ulTemp;
+ }
+ else if(i == (lBufLen - 1))
+ {
+ ulTemp = (pucBuf[i++] << 0);
+ HWREG(ulBase + MAC_O_DATA) = ulTemp;
+ }
+ }
+
+ //
+ // Activate the transmitter
+ //
+ HWREG(ulBase + MAC_O_TR) = MAC_TR_NEWTX;
+
+ //
+ // Return the Buffer Length transmitted.
+ //
+ return(lBufLen);
+}
+
+//*****************************************************************************
+//
+//! Sends a packet to the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is number of bytes in the packet to be transmitted.
+//!
+//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
+//! into the transmit FIFO of the controller and then activates the
+//! transmitter for this packet. If no space is available in the FIFO, the
+//! function will return immediately. If space is available, the
+//! function will return once \e lBufLen bytes of the packet have been placed
+//! into the FIFO and the transmitter has been started. The function will not
+//! wait for the transmission to complete. The function will return the
+//! negated \e lBufLen if the length is larger than the space available in
+//! the transmit FIFO.
+//!
+//! This function replaces the original EthernetPacketNonBlockingPut() API and
+//! performs the same actions. A macro is provided in ethernet.h to
+//! map the original API to this API.
+//!
+//! \note This function does not block and will return immediately if no space
+//! is available for the transmit packet.
+//!
+//! \return Returns \b 0 if no space is available in the transmit FIFO, the
+//! negated packet length \b -lBufLen if the packet is too large for FIFO, and
+//! the packet length \b lBufLen otherwise.
+//
+//*****************************************************************************
+long
+EthernetPacketPutNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucBuf != 0);
+ ASSERT(lBufLen > 0);
+
+ //
+ // Check if the transmit FIFO is in use and return the appropriate code.
+ //
+ if(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
+ {
+ return(0);
+ }
+
+ //
+ // Send the packet and return.
+ //
+ return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen));
+}
+
+//*****************************************************************************
+//
+//! Waits to send a packet from the Ethernet controller.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pucBuf is the pointer to the packet buffer.
+//! \param lBufLen is number of bytes in the packet to be transmitted.
+//!
+//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
+//! into the transmit FIFO of the controller and then activates the transmitter
+//! for this packet. This function will wait until the transmit FIFO is empty.
+//! Once space is available, the function will return once \e lBufLen bytes of
+//! the packet have been placed into the FIFO and the transmitter has been
+//! started. The function will not wait for the transmission to complete. The
+//! function will return the negated \e lBufLen if the length is larger than
+//! the space available in the transmit FIFO.
+//!
+//! \note This function blocks and will wait until space is available for the
+//! transmit packet before returning.
+//!
+//! \return Returns the negated packet length \b -lBufLen if the packet is too
+//! large for FIFO, and the packet length \b lBufLen otherwise.
+//
+//*****************************************************************************
+long
+EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pucBuf != 0);
+ ASSERT(lBufLen > 0);
+
+ //
+ // Wait for current packet (if any) to complete.
+ //
+ while(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
+ {
+ }
+
+ //
+ // Send the packet and return.
+ //
+ return(EthernetPacketPutInternal(ulBase, pucBuf, lBufLen));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for an Ethernet interrupt.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled Ethernet interrupts occur.
+//!
+//! This function sets the handler to be called when the Ethernet interrupt
+//! occurs. This will enable the global interrupt in the interrupt controller;
+//! specific Ethernet interrupts must be enabled via EthernetIntEnable(). It
+//! is the interrupt handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(pfnHandler != 0);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_ETH, pfnHandler);
+
+ //
+ // Enable the Ethernet interrupt.
+ //
+ IntEnable(INT_ETH);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for an Ethernet interrupt.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! This function unregisters the interrupt handler. This will disable the
+//! global interrupt in the interrupt controller so that the interrupt handler
+//! no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_ETH);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_ETH);
+}
+
+//*****************************************************************************
+//
+//! Enables individual Ethernet interrupt sources.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated Ethernet interrupt sources. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b ETH_INT_PHY - An interrupt from the PHY has occurred. The integrated
+//! PHY supports a number of interrupt conditions. The PHY register, PHY_MR17,
+//! must be read to determine which PHY interrupt has occurred. This register
+//! can be read using the EthernetPHYRead() API function.
+//! - \b ETH_INT_MDIO - This interrupt indicates that a transaction on the
+//! management interface has completed successfully.
+//! - \b ETH_INT_RXER - This interrupt indicates that an error has occurred
+//! during reception of a frame. This error can indicate a length mismatch, a
+//! CRC failure, or an error indication from the PHY.
+//! - \b ETH_INT_RXOF - This interrupt indicates that a frame has been received
+//! that exceeds the available space in the RX FIFO.
+//! - \b ETH_INT_TX - This interrupt indicates that the packet stored in the TX
+//! FIFO has been successfully transmitted.
+//! - \b ETH_INT_TXER - This interrupt indicates that an error has occurred
+//! during the transmission of a packet. This error can be either a retry
+//! failure during the back-off process, or an invalid length stored in the TX
+//! FIFO.
+//! - \b ETH_INT_RX - This interrupt indicates that one (or more) packets are
+//! available in the RX FIFO for processing.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
+ ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
+ ETH_INT_RX)));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + MAC_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual Ethernet interrupt sources.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated Ethernet interrupt sources. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to EthernetIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
+ ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
+ ETH_INT_RX)));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + MAC_O_IM) &= ~ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the current Ethernet interrupt status.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param bMasked is false if the raw interrupt status is required and true
+//! if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the Ethernet controller. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in EthernetIntEnable().
+//
+//*****************************************************************************
+unsigned long
+EthernetIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Read the unmasked status.
+ //
+ ulStatus = HWREG(ulBase + MAC_O_RIS);
+
+ //
+ // If masked status is requested, mask it off.
+ //
+ if(bMasked)
+ {
+ ulStatus &= HWREG(ulBase + MAC_O_IM);
+ }
+
+ //
+ // Return the interrupt status value.
+ //
+ return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Clears Ethernet interrupt sources.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified Ethernet interrupt sources are cleared so that they no longer
+//! assert. This must be done in the interrupt handler to keep it from being
+//! called again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to EthernetIntEnable().
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+ ASSERT(!(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
+ ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER |
+ ETH_INT_RX)));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + MAC_O_IACK) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Writes to the PHY register.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ucRegAddr is the address of the PHY register to be accessed.
+//! \param ulData is the data to be written to the PHY register.
+//!
+//! This function will write the \e ulData to the PHY register specified by
+//! \e ucRegAddr.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
+ unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Wait for any pending transaction to complete.
+ //
+ while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+ {
+ }
+
+ //
+ // Program the DATA to be written.
+ //
+ HWREG(ulBase + MAC_O_MTXD) = ulData & MAC_MTXD_MDTX_M;
+
+ //
+ // Program the PHY register address and initiate the transaction.
+ //
+ HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) |
+ MAC_MCTL_WRITE | MAC_MCTL_START);
+
+ //
+ // Wait for the write transaction to complete.
+ //
+ while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! Reads from a PHY register.
+//!
+//! \param ulBase is the base address of the controller.
+//! \param ucRegAddr is the address of the PHY register to be accessed.
+//!
+//! This function will return the contents of the PHY register specified by
+//! \e ucRegAddr.
+//!
+//! \return Returns the 16-bit value read from the PHY.
+//
+//*****************************************************************************
+unsigned long
+EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == ETH_BASE);
+
+ //
+ // Wait for any pending transaction to complete.
+ //
+ while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+ {
+ }
+
+ //
+ // Program the PHY register address and initiate the transaction.
+ //
+ HWREG(ulBase + MAC_O_MCTL) = (((ucRegAddr << 3) & MAC_MCTL_REGADR_M) |
+ MAC_MCTL_START);
+
+ //
+ // Wait for the transaction to complete.
+ //
+ while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
+ {
+ }
+
+ //
+ // Return the PHY data that was read.
+ //
+ return(HWREG(ulBase + MAC_O_MRXD) & MAC_MRXD_MDRX_M);
+}
+
+//*****************************************************************************
+//
+//! Powers off the Ethernet PHY.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! This function will power off the Ethernet PHY, reducing the current
+//! consuption of the device. While in the powered off state, the Ethernet
+//! controller will be unable to connect to the Ethernet.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetPHYPowerOff(unsigned long ulBase)
+{
+ //
+ // Set the PWRDN bit and clear the ANEGEN bit in the PHY, putting it into
+ // its low power mode.
+ //
+ EthernetPHYWrite(ulBase, PHY_MR0,
+ (EthernetPHYRead(ulBase, PHY_MR0) & ~PHY_MR0_ANEGEN) |
+ PHY_MR0_PWRDN);
+}
+
+//*****************************************************************************
+//
+//! Powers on the Ethernet PHY.
+//!
+//! \param ulBase is the base address of the controller.
+//!
+//! This function will power on the Ethernet PHY, enabling it return to normal
+//! operation. By default, the PHY is powered on, so this function only needs
+//! to be called if EthernetPHYPowerOff() has previously been called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+EthernetPHYPowerOn(unsigned long ulBase)
+{
+ //
+ // Clear the PWRDN bit and set the ANEGEN bit in the PHY, putting it into
+ // normal operating mode.
+ //
+ EthernetPHYWrite(ulBase, PHY_MR0,
+ (EthernetPHYRead(ulBase, PHY_MR0) & ~PHY_MR0_PWRDN) |
+ PHY_MR0_ANEGEN);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/ethernet.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/ethernet.h
new file mode 100644
index 00000000..860a1365
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/ethernet.h
@@ -0,0 +1,171 @@
+//*****************************************************************************
+//
+// ethernet.h - Defines and Macros for the ethernet module.
+//
+// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ETHERNET_H__
+#define __ETHERNET_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to EthernetConfigSet as the ulConfig value, and
+// returned from EthernetConfigGet.
+//
+//*****************************************************************************
+#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP)
+#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets
+#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous
+#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast
+#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode
+#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation
+#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding
+
+//*****************************************************************************
+//
+// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and
+// EthernetIntClear as the ulIntFlags parameter, and returned from
+// EthernetIntStatus.
+//
+//*****************************************************************************
+#define ETH_INT_PHY 0x040 // PHY Event/Interrupt
+#define ETH_INT_MDIO 0x020 // Management Transaction
+#define ETH_INT_RXER 0x010 // RX Error
+#define ETH_INT_RXOF 0x008 // RX FIFO Overrun
+#define ETH_INT_TX 0x004 // TX Complete
+#define ETH_INT_TXER 0x002 // TX Error
+#define ETH_INT_RX 0x001 // RX Complete
+
+//*****************************************************************************
+//
+// Helper Macros for Ethernet Processing
+//
+//*****************************************************************************
+//
+// htonl/ntohl - big endian/little endian byte swapping macros for
+// 32-bit (long) values
+//
+//*****************************************************************************
+#ifndef htonl
+ #define htonl(a) \
+ ((((a) >> 24) & 0x000000ff) | \
+ (((a) >> 8) & 0x0000ff00) | \
+ (((a) << 8) & 0x00ff0000) | \
+ (((a) << 24) & 0xff000000))
+#endif
+
+#ifndef ntohl
+ #define ntohl(a) htonl((a))
+#endif
+
+//*****************************************************************************
+//
+// htons/ntohs - big endian/little endian byte swapping macros for
+// 16-bit (short) values
+//
+//*****************************************************************************
+#ifndef htons
+ #define htons(a) \
+ ((((a) >> 8) & 0x00ff) | \
+ (((a) << 8) & 0xff00))
+#endif
+
+#ifndef ntohs
+ #define ntohs(a) htons((a))
+#endif
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk);
+extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig);
+extern unsigned long EthernetConfigGet(unsigned long ulBase);
+extern void EthernetMACAddrSet(unsigned long ulBase,
+ unsigned char *pucMACAddr);
+extern void EthernetMACAddrGet(unsigned long ulBase,
+ unsigned char *pucMACAddr);
+extern void EthernetEnable(unsigned long ulBase);
+extern void EthernetDisable(unsigned long ulBase);
+extern tBoolean EthernetPacketAvail(unsigned long ulBase);
+extern tBoolean EthernetSpaceAvail(unsigned long ulBase);
+extern long EthernetPacketGetNonBlocking(unsigned long ulBase,
+ unsigned char *pucBuf,
+ long lBufLen);
+extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen);
+extern long EthernetPacketPutNonBlocking(unsigned long ulBase,
+ unsigned char *pucBuf,
+ long lBufLen);
+extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
+ long lBufLen);
+extern void EthernetIntRegister(unsigned long ulBase,
+ void (*pfnHandler)(void));
+extern void EthernetIntUnregister(unsigned long ulBase);
+extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
+ unsigned long ulData);
+extern unsigned long EthernetPHYRead(unsigned long ulBase,
+ unsigned char ucRegAddr);
+extern void EthernetPHYPowerOff(unsigned long ulBase);
+extern void EthernetPHYPowerOn(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several Ethernet APIs have been renamed, with the original function name
+// being deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "driverlib/sysctl.h"
+#define EthernetInit(a) \
+ EthernetInitExpClk(a, SysCtlClockGet())
+#define EthernetPacketNonBlockingGet(a, b, c) \
+ EthernetPacketGetNonBlocking(a, b, c)
+#define EthernetPacketNonBlockingPut(a, b, c) \
+ EthernetPacketPutNonBlocking(a, b, c)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ETHERNET_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/flash.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/flash.c
new file mode 100644
index 00000000..09585467
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/flash.c
@@ -0,0 +1,912 @@
+//*****************************************************************************
+//
+// flash.c - Driver for programming the on-chip flash.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup flash_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_flash.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/flash.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// An array that maps the specified memory bank to the appropriate Flash
+// Memory Protection Program Enable (FMPPE) register.
+//
+//*****************************************************************************
+static const unsigned long g_pulFMPPERegs[] =
+{
+ FLASH_FMPPE,
+ FLASH_FMPPE1,
+ FLASH_FMPPE2,
+ FLASH_FMPPE3
+};
+
+//*****************************************************************************
+//
+// An array that maps the specified memory bank to the appropriate Flash
+// Memory Protection Read Enable (FMPRE) register.
+//
+//*****************************************************************************
+static const unsigned long g_pulFMPRERegs[] =
+{
+ FLASH_FMPRE,
+ FLASH_FMPRE1,
+ FLASH_FMPRE2,
+ FLASH_FMPRE3
+};
+
+//*****************************************************************************
+//
+//! Gets the number of processor clocks per micro-second.
+//!
+//! This function returns the number of clocks per micro-second, as presently
+//! known by the flash controller.
+//!
+//! \return Returns the number of processor clocks per micro-second.
+//
+//*****************************************************************************
+unsigned long
+FlashUsecGet(void)
+{
+ //
+ // Return the number of clocks per micro-second.
+ //
+ return(HWREG(FLASH_USECRL) + 1);
+}
+
+//*****************************************************************************
+//
+//! Sets the number of processor clocks per micro-second.
+//!
+//! \param ulClocks is the number of processor clocks per micro-second.
+//!
+//! This function is used to tell the flash controller the number of processor
+//! clocks per micro-second. This value must be programmed correctly or the
+//! flash most likely will not program correctly; it has no affect on reading
+//! flash.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashUsecSet(unsigned long ulClocks)
+{
+ //
+ // Set the number of clocks per micro-second.
+ //
+ HWREG(FLASH_USECRL) = ulClocks - 1;
+}
+
+//*****************************************************************************
+//
+//! Erases a block of flash.
+//!
+//! \param ulAddress is the start address of the flash block to be erased.
+//!
+//! This function will erase a 1 kB block of the on-chip flash. After erasing,
+//! the block will be filled with 0xFF bytes. Read-only and execute-only
+//! blocks cannot be erased.
+//!
+//! This function will not return until the block has been erased.
+//!
+//! \return Returns 0 on success, or -1 if an invalid block address was
+//! specified or the block is write-protected.
+//
+//*****************************************************************************
+long
+FlashErase(unsigned long ulAddress)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1)));
+
+ //
+ // Clear the flash access interrupt.
+ //
+ HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
+
+ //
+ // Erase the block.
+ //
+ HWREG(FLASH_FMA) = ulAddress;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_ERASE;
+
+ //
+ // Wait until the block has been erased.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_ERASE)
+ {
+ }
+
+ //
+ // Return an error if an access violation occurred.
+ //
+ if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
+ {
+ return(-1);
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Programs flash.
+//!
+//! \param pulData is a pointer to the data to be programmed.
+//! \param ulAddress is the starting address in flash to be programmed. Must
+//! be a multiple of four.
+//! \param ulCount is the number of bytes to be programmed. Must be a multiple
+//! of four.
+//!
+//! This function will program a sequence of words into the on-chip flash.
+//! Programming each location consists of the result of an AND operation
+//! of the new data and the existing data; in other words bits that contain
+//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
+//! to 1. Therefore, a word can be programmed multiple times as long as these
+//! rules are followed; if a program operation attempts to change a 0 bit to
+//! a 1 bit, that bit will not have its value changed.
+//!
+//! Since the flash is programmed one word at a time, the starting address and
+//! byte count must both be multiples of four. It is up to the caller to
+//! verify the programmed contents, if such verification is required.
+//!
+//! This function will not return until the data has been programmed.
+//!
+//! \return Returns 0 on success, or -1 if a programming error is encountered.
+//
+//*****************************************************************************
+long
+FlashProgram(unsigned long *pulData, unsigned long ulAddress,
+ unsigned long ulCount)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulAddress & 3));
+ ASSERT(!(ulCount & 3));
+
+ //
+ // Clear the flash access interrupt.
+ //
+ HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
+
+ //
+ // See if this device has a write buffer.
+ //
+ if(HWREG(SYSCTL_NVMSTAT) & SYSCTL_NVMSTAT_FWB)
+ {
+ //
+ // Loop over the words to be programmed.
+ //
+ while(ulCount)
+ {
+ //
+ // Set the address of this block of words.
+ //
+ HWREG(FLASH_FMA) = ulAddress & ~(0x7f);
+
+ //
+ // Loop over the words in this 32-word block.
+ //
+ while(((ulAddress & 0x7c) || (HWREG(FLASH_FWBVAL) == 0)) &&
+ (ulCount != 0))
+ {
+ //
+ // Write this word into the write buffer.
+ //
+ HWREG(FLASH_FWBN + (ulAddress & 0x7c)) = *pulData++;
+ ulAddress += 4;
+ ulCount -= 4;
+ }
+
+ //
+ // Program the contents of the write buffer into flash.
+ //
+ HWREG(FLASH_FMC2) = FLASH_FMC2_WRKEY | FLASH_FMC2_WRBUF;
+
+ //
+ // Wait until the write buffer has been programmed.
+ //
+ while(HWREG(FLASH_FMC2) & FLASH_FMC2_WRBUF)
+ {
+ }
+ }
+ }
+ else
+ {
+ //
+ // Loop over the words to be programmed.
+ //
+ while(ulCount)
+ {
+ //
+ // Program the next word.
+ //
+ HWREG(FLASH_FMA) = ulAddress;
+ HWREG(FLASH_FMD) = *pulData;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
+
+ //
+ // Wait until the word has been programmed.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_WRITE)
+ {
+ }
+
+ //
+ // Increment to the next word.
+ //
+ pulData++;
+ ulAddress += 4;
+ ulCount -= 4;
+ }
+ }
+
+ //
+ // Return an error if an access violation occurred.
+ //
+ if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
+ {
+ return(-1);
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Gets the protection setting for a block of flash.
+//!
+//! \param ulAddress is the start address of the flash block to be queried.
+//!
+//! This function will get the current protection for the specified 2 kB block
+//! of flash. Each block can be read/write, read-only, or execute-only.
+//! Read/write blocks can be read, executed, erased, and programmed. Read-only
+//! blocks can be read and executed. Execute-only blocks can only be executed;
+//! processor and debugger data reads are not allowed.
+//!
+//! \return Returns the protection setting for this block. See
+//! FlashProtectSet() for possible values.
+//
+//*****************************************************************************
+tFlashProtection
+FlashProtectGet(unsigned long ulAddress)
+{
+ unsigned long ulFMPRE, ulFMPPE;
+ unsigned long ulBank;
+
+ //
+ // Check the argument.
+ //
+ ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
+
+ //
+ // Calculate the Flash Bank from Base Address, and mask off the Bank
+ // from ulAddress for subsequent reference.
+ //
+ ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 4);
+ ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1);
+
+ //
+ // Read the appropriate flash protection registers for the specified
+ // flash bank.
+ //
+ ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]);
+ ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]);
+
+ //
+ // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
+ // bits of the FMPPE register are used for JTAG protect options, and are
+ // not available for the FLASH protection scheme. When Querying Block
+ // Protection, assume these bits are 1.
+ //
+ if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
+ {
+ ulFMPRE |= (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
+ }
+
+ //
+ // Check the appropriate protection bits for the block of memory that
+ // is specified by the address.
+ //
+ switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &
+ FLASH_FMP_BLOCK_0) << 1) |
+ ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))
+ {
+ //
+ // This block is marked as execute only (that is, it can not be erased
+ // or programmed, and the only reads allowed are via the instruction
+ // fetch interface).
+ //
+ case 0:
+ case 1:
+ {
+ return(FlashExecuteOnly);
+ }
+
+ //
+ // This block is marked as read only (that is, it can not be erased or
+ // programmed).
+ //
+ case 2:
+ {
+ return(FlashReadOnly);
+ }
+
+ //
+ // This block is read/write; it can be read, erased, and programmed.
+ //
+ case 3:
+ default:
+ {
+ return(FlashReadWrite);
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the protection setting for a block of flash.
+//!
+//! \param ulAddress is the start address of the flash block to be protected.
+//! \param eProtect is the protection to be applied to the block. Can be one
+//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
+//!
+//! This function will set the protection for the specified 2 kB block of
+//! flash. Blocks which are read/write can be made read-only or execute-only.
+//! Blocks which are read-only can be made execute-only. Blocks which are
+//! execute-only cannot have their protection modified. Attempts to make the
+//! block protection less stringent (that is, read-only to read/write) will
+//! result in a failure (and be prevented by the hardware).
+//!
+//! Changes to the flash protection are maintained only until the next reset.
+//! This allows the application to be executed in the desired flash protection
+//! environment to check for inappropriate flash access (via the flash
+//! interrupt). To make the flash protection permanent, use the
+//! FlashProtectSave() function.
+//!
+//! \return Returns 0 on success, or -1 if an invalid address or an invalid
+//! protection was specified.
+//
+//*****************************************************************************
+long
+FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
+{
+ unsigned long ulProtectRE, ulProtectPE;
+ unsigned long ulBank;
+
+ //
+ // Check the argument.
+ //
+ ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
+ ASSERT((eProtect == FlashReadWrite) || (eProtect == FlashReadOnly) ||
+ (eProtect == FlashExecuteOnly));
+
+ //
+ // Convert the address into a block number.
+ //
+ ulAddress /= FLASH_PROTECT_SIZE;
+
+ //
+ // ulAddress contains a "raw" block number. Derive the Flash Bank from
+ // the "raw" block number, and convert ulAddress to a "relative"
+ // block number.
+ //
+ ulBank = ((ulAddress / 32) % 4);
+ ulAddress %= 32;
+
+ //
+ // Get the current protection for the specified flash bank.
+ //
+ ulProtectRE = HWREG(g_pulFMPRERegs[ulBank]);
+ ulProtectPE = HWREG(g_pulFMPPERegs[ulBank]);
+
+ //
+ // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
+ // bits of the FMPPE register are used for JTAG protect options, and are
+ // not available for the FLASH protection scheme. When setting protection,
+ // check to see if block 30 or 31 and protection is FlashExecuteOnly. If
+ // so, return an error condition.
+ //
+ if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
+ {
+ if((ulAddress >= 30) && (eProtect == FlashExecuteOnly))
+ {
+ return(-1);
+ }
+ }
+
+ //
+ // Set the protection based on the requested proection.
+ //
+ switch(eProtect)
+ {
+ //
+ // Make this block execute only.
+ //
+ case FlashExecuteOnly:
+ {
+ //
+ // Turn off the read and program bits for this block.
+ //
+ ulProtectRE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
+ ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
+
+ //
+ // We're done handling this protection.
+ //
+ break;
+ }
+
+ //
+ // Make this block read only.
+ //
+ case FlashReadOnly:
+ {
+ //
+ // The block can not be made read only if it is execute only.
+ //
+ if(((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
+ FLASH_FMP_BLOCK_0)
+ {
+ return(-1);
+ }
+
+ //
+ // Make this block read only.
+ //
+ ulProtectPE &= ~(FLASH_FMP_BLOCK_0 << ulAddress);
+
+ //
+ // We're done handling this protection.
+ //
+ break;
+ }
+
+ //
+ // Make this block read/write.
+ //
+ case FlashReadWrite:
+ default:
+ {
+ //
+ // The block can not be made read/write if it is not already
+ // read/write.
+ //
+ if((((ulProtectRE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
+ FLASH_FMP_BLOCK_0) ||
+ (((ulProtectPE >> ulAddress) & FLASH_FMP_BLOCK_0) !=
+ FLASH_FMP_BLOCK_0))
+ {
+ return(-1);
+ }
+
+ //
+ // The block is already read/write, so there is nothing to do.
+ //
+ return(0);
+ }
+ }
+
+ //
+ // For Stellaris Sandstorm-class devices, revision C1 and C2, the upper
+ // bits of the FMPPE register are used for JTAG options, and are not
+ // available for the FLASH protection scheme. When setting block
+ // protection, ensure that these bits are not altered.
+ //
+ if(CLASS_IS_SANDSTORM && (REVISION_IS_C1 || REVISION_IS_C2))
+ {
+ ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
+ ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) &
+ (FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
+ }
+
+ //
+ // Set the new protection for the specified flash bank.
+ //
+ HWREG(g_pulFMPRERegs[ulBank]) = ulProtectRE;
+ HWREG(g_pulFMPPERegs[ulBank]) = ulProtectPE;
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Saves the flash protection settings.
+//!
+//! This function will make the currently programmed flash protection settings
+//! permanent. This is a non-reversible operation; a chip reset or power cycle
+//! will not change the flash protection.
+//!
+//! This function will not return until the protection has been saved.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+long
+FlashProtectSave(void)
+{
+ int ulTemp, ulLimit;
+
+ //
+ // If running on a Sandstorm-class device, only trigger a save of the first
+ // two protection registers (FMPRE and FMPPE). Otherwise, save the
+ // entire bank of flash protection registers.
+ //
+ ulLimit = CLASS_IS_SANDSTORM ? 2 : 8;
+ for(ulTemp = 0; ulTemp < ulLimit; ulTemp++)
+ {
+ //
+ // Tell the flash controller to write the flash protection register.
+ //
+ HWREG(FLASH_FMA) = ulTemp;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+ //
+ // Wait until the write has completed.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+ {
+ }
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Gets the user registers.
+//!
+//! \param pulUser0 is a pointer to the location to store USER Register 0.
+//! \param pulUser1 is a pointer to the location to store USER Register 1.
+//!
+//! This function will read the contents of user registers (0 and 1), and
+//! store them in the specified locations.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+long
+FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1)
+{
+ //
+ // Verify that the pointers are valid.
+ //
+ ASSERT(pulUser0 != 0);
+ ASSERT(pulUser1 != 0);
+
+ //
+ // Verify that hardware supports user registers.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ return(-1);
+ }
+
+ //
+ // Get and store the current value of the user registers.
+ //
+ *pulUser0 = HWREG(FLASH_USERREG0);
+ *pulUser1 = HWREG(FLASH_USERREG1);
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Sets the user registers.
+//!
+//! \param ulUser0 is the value to store in USER Register 0.
+//! \param ulUser1 is the value to store in USER Register 1.
+//!
+//! This function will set the contents of the user registers (0 and 1) to
+//! the specified values.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+long
+FlashUserSet(unsigned long ulUser0, unsigned long ulUser1)
+{
+ //
+ // Verify that hardware supports user registers.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ return(-1);
+ }
+
+ //
+ // Save the new values into the user registers.
+ //
+ HWREG(FLASH_USERREG0) = ulUser0;
+ HWREG(FLASH_USERREG1) = ulUser1;
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Saves the user registers.
+//!
+//! This function will make the currently programmed user register settings
+//! permanent. This is a non-reversible operation; a chip reset or power cycle
+//! will not change this setting.
+//!
+//! This function will not return until the protection has been saved.
+//!
+//! \return Returns 0 on success, or -1 if a hardware error is encountered.
+//
+//*****************************************************************************
+long
+FlashUserSave(void)
+{
+ //
+ // Verify that hardware supports user registers.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ return(-1);
+ }
+
+ //
+ // Setting the MSB of FMA will trigger a permanent save of a USER
+ // register. Bit 0 will indicate User 0 (0) or User 1 (1).
+ //
+ HWREG(FLASH_FMA) = 0x80000000;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+ //
+ // Wait until the write has completed.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+ {
+ }
+
+ //
+ // Tell the flash controller to write the USER1 Register.
+ //
+ HWREG(FLASH_FMA) = 0x80000001;
+ HWREG(FLASH_FMC) = FLASH_FMC_WRKEY | FLASH_FMC_COMT;
+
+ //
+ // Wait until the write has completed.
+ //
+ while(HWREG(FLASH_FMC) & FLASH_FMC_COMT)
+ {
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the flash interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the flash
+//! interrupt occurs.
+//!
+//! This sets the handler to be called when the flash interrupt occurs. The
+//! flash controller can generate an interrupt when an invalid flash access
+//! occurs, such as trying to program or erase a read-only block, or trying to
+//! read from an execute-only block. It can also generate an interrupt when a
+//! program or erase operation has completed. The interrupt will be
+//! automatically enabled when the handler is registered.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(INT_FLASH, pfnHandler);
+
+ //
+ // Enable the flash interrupt.
+ //
+ IntEnable(INT_FLASH);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the flash interrupt.
+//!
+//! This function will clear the handler to be called when the flash interrupt
+//! occurs. This will also mask off the interrupt in the interrupt controller
+//! so that the interrupt handler is no longer called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntUnregister(void)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_FLASH);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_FLASH);
+}
+
+//*****************************************************************************
+//
+//! Enables individual flash controller interrupt sources.
+//!
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
+//!
+//! Enables the indicated flash controller interrupt sources. Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntEnable(unsigned long ulIntFlags)
+{
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(FLASH_FCIM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual flash controller interrupt sources.
+//!
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
+//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
+//!
+//! Disables the indicated flash controller interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntDisable(unsigned long ulIntFlags)
+{
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(FLASH_FCIM) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the flash controller. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b FLASH_INT_PROGRAM and \b FLASH_INT_ACCESS.
+//
+//*****************************************************************************
+unsigned long
+FlashIntStatus(tBoolean bMasked)
+{
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(FLASH_FCMISC));
+ }
+ else
+ {
+ return(HWREG(FLASH_FCRIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears flash controller interrupt sources.
+//!
+//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
+//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_AMISC values.
+//!
+//! The specified flash controller interrupt sources are cleared, so that they
+//! no longer assert. This must be done in the interrupt handler to keep it
+//! from being called again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+FlashIntClear(unsigned long ulIntFlags)
+{
+ //
+ // Clear the flash interrupt.
+ //
+ HWREG(FLASH_FCMISC) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/flash.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/flash.h
new file mode 100644
index 00000000..36203673
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/flash.h
@@ -0,0 +1,106 @@
+//*****************************************************************************
+//
+// flash.h - Prototypes for the flash driver.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __FLASH_H__
+#define __FLASH_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to FlashProtectSet(), and returned by
+// FlashProtectGet().
+//
+//*****************************************************************************
+typedef enum
+{
+ FlashReadWrite, // Flash can be read and written
+ FlashReadOnly, // Flash can only be read
+ FlashExecuteOnly // Flash can only be executed
+}
+tFlashProtection;
+
+//*****************************************************************************
+//
+// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
+// returned from FlashIntStatus().
+//
+//*****************************************************************************
+#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
+#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern unsigned long FlashUsecGet(void);
+extern void FlashUsecSet(unsigned long ulClocks);
+extern long FlashErase(unsigned long ulAddress);
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
+ unsigned long ulCount);
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
+extern long FlashProtectSet(unsigned long ulAddress,
+ tFlashProtection eProtect);
+extern long FlashProtectSave(void);
+extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1);
+extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1);
+extern long FlashUserSave(void);
+extern void FlashIntRegister(void (*pfnHandler)(void));
+extern void FlashIntUnregister(void);
+extern void FlashIntEnable(unsigned long ulIntFlags);
+extern void FlashIntDisable(unsigned long ulIntFlags);
+extern unsigned long FlashIntStatus(tBoolean bMasked);
+extern void FlashIntClear(unsigned long ulIntFlags);
+
+//*****************************************************************************
+//
+// Deprecated function names. These definitions ensure backwards compatibility
+// but new code should avoid using deprecated function names since these will
+// be removed at some point in the future.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define FlashIntGetStatus FlashIntStatus
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __FLASH_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/gpio.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/gpio.c
new file mode 100644
index 00000000..4e5afa7c
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/gpio.c
@@ -0,0 +1,1600 @@
+//*****************************************************************************
+//
+// gpio.c - API for GPIO ports
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup gpio_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_gpio.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/gpio.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// The base addresses of all the GPIO modules. Both the APB and AHB apertures
+// are provided.
+//
+//*****************************************************************************
+static const unsigned long g_pulGPIOBaseAddrs[] =
+{
+ GPIO_PORTA_BASE, GPIO_PORTA_AHB_BASE,
+ GPIO_PORTB_BASE, GPIO_PORTB_AHB_BASE,
+ GPIO_PORTC_BASE, GPIO_PORTC_AHB_BASE,
+ GPIO_PORTD_BASE, GPIO_PORTD_AHB_BASE,
+ GPIO_PORTE_BASE, GPIO_PORTE_AHB_BASE,
+ GPIO_PORTF_BASE, GPIO_PORTF_AHB_BASE,
+ GPIO_PORTG_BASE, GPIO_PORTG_AHB_BASE,
+ GPIO_PORTH_BASE, GPIO_PORTH_AHB_BASE,
+ GPIO_PORTJ_BASE, GPIO_PORTJ_AHB_BASE,
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a GPIO base address.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function determines if a GPIO port base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+GPIOBaseValid(unsigned long ulPort)
+{
+ return((ulPort == GPIO_PORTA_BASE) || (ulPort == GPIO_PORTA_AHB_BASE) ||
+ (ulPort == GPIO_PORTB_BASE) || (ulPort == GPIO_PORTB_AHB_BASE) ||
+ (ulPort == GPIO_PORTC_BASE) || (ulPort == GPIO_PORTC_AHB_BASE) ||
+ (ulPort == GPIO_PORTD_BASE) || (ulPort == GPIO_PORTD_AHB_BASE) ||
+ (ulPort == GPIO_PORTE_BASE) || (ulPort == GPIO_PORTE_AHB_BASE) ||
+ (ulPort == GPIO_PORTF_BASE) || (ulPort == GPIO_PORTF_AHB_BASE) ||
+ (ulPort == GPIO_PORTG_BASE) || (ulPort == GPIO_PORTG_AHB_BASE) ||
+ (ulPort == GPIO_PORTH_BASE) || (ulPort == GPIO_PORTH_AHB_BASE) ||
+ (ulPort == GPIO_PORTJ_BASE) || (ulPort == GPIO_PORTJ_AHB_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Gets the GPIO interrupt number.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! Given a GPIO base address, returns the corresponding interrupt number.
+//!
+//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid.
+//
+//*****************************************************************************
+static long
+GPIOGetIntNumber(unsigned long ulPort)
+{
+ unsigned int ulInt;
+
+ //
+ // Determine the GPIO interrupt number for the given module.
+ //
+ switch(ulPort)
+ {
+ case GPIO_PORTA_BASE:
+ case GPIO_PORTA_AHB_BASE:
+ {
+ ulInt = INT_GPIOA;
+ break;
+ }
+
+ case GPIO_PORTB_BASE:
+ case GPIO_PORTB_AHB_BASE:
+ {
+ ulInt = INT_GPIOB;
+ break;
+ }
+
+ case GPIO_PORTC_BASE:
+ case GPIO_PORTC_AHB_BASE:
+ {
+ ulInt = INT_GPIOC;
+ break;
+ }
+
+ case GPIO_PORTD_BASE:
+ case GPIO_PORTD_AHB_BASE:
+ {
+ ulInt = INT_GPIOD;
+ break;
+ }
+
+ case GPIO_PORTE_BASE:
+ case GPIO_PORTE_AHB_BASE:
+ {
+ ulInt = INT_GPIOE;
+ break;
+ }
+
+ case GPIO_PORTF_BASE:
+ case GPIO_PORTF_AHB_BASE:
+ {
+ ulInt = INT_GPIOF;
+ break;
+ }
+
+ case GPIO_PORTG_BASE:
+ case GPIO_PORTG_AHB_BASE:
+ {
+ ulInt = INT_GPIOG;
+ break;
+ }
+
+ case GPIO_PORTH_BASE:
+ case GPIO_PORTH_AHB_BASE:
+ {
+ ulInt = INT_GPIOH;
+ break;
+ }
+
+ case GPIO_PORTJ_BASE:
+ case GPIO_PORTJ_AHB_BASE:
+ {
+ ulInt = INT_GPIOJ;
+ break;
+ }
+
+ default:
+ {
+ return(-1);
+ }
+ }
+
+ //
+ // Return GPIO interrupt number.
+ //
+ return(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Sets the direction and mode of the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulPinIO is the pin direction and/or mode.
+//!
+//! This function will set the specified pin(s) on the selected GPIO port
+//! as either an input or output under software control, or it will set the
+//! pin to be under hardware control.
+//!
+//! The parameter \e ulPinIO is an enumerated data type that can be one of
+//! the following values:
+//!
+//! - \b GPIO_DIR_MODE_IN
+//! - \b GPIO_DIR_MODE_OUT
+//! - \b GPIO_DIR_MODE_HW
+//!
+//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as
+//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin
+//! will be programmed as a software controlled output, and
+//! \b GPIO_DIR_MODE_HW specifies that the pin will be placed under
+//! hardware control.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note GPIOPadConfigSet() must also be used to configure the corresponding
+//! pad(s) in order for them to propagate the signal to/from the GPIO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulPinIO)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT) ||
+ (ulPinIO == GPIO_DIR_MODE_HW));
+
+ //
+ // Set the pin direction and mode.
+ //
+ HWREG(ulPort + GPIO_O_DIR) = ((ulPinIO & 1) ?
+ (HWREG(ulPort + GPIO_O_DIR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DIR) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_AFSEL) = ((ulPinIO & 2) ?
+ (HWREG(ulPort + GPIO_O_AFSEL) | ucPins) :
+ (HWREG(ulPort + GPIO_O_AFSEL) &
+ ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the direction and mode of a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//!
+//! This function gets the direction and control mode for a specified pin on
+//! the selected GPIO port. The pin can be configured as either an input or
+//! output under software control, or it can be under hardware control. The
+//! type of control and direction are returned as an enumerated data type.
+//!
+//! \return Returns one of the enumerated data types described for
+//! GPIODirModeSet().
+//
+//*****************************************************************************
+unsigned long
+GPIODirModeGet(unsigned long ulPort, unsigned char ucPin)
+{
+ unsigned long ulDir, ulAFSEL;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT(ucPin < 8);
+
+ //
+ // Convert from a pin number to a bit position.
+ //
+ ucPin = 1 << ucPin;
+
+ //
+ // Return the pin direction and mode.
+ //
+ ulDir = HWREG(ulPort + GPIO_O_DIR);
+ ulAFSEL = HWREG(ulPort + GPIO_O_AFSEL);
+ return(((ulDir & ucPin) ? 1 : 0) | ((ulAFSEL & ucPin) ? 2 : 0));
+}
+
+//*****************************************************************************
+//
+//! Sets the interrupt type for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulIntType specifies the type of interrupt trigger mechanism.
+//!
+//! This function sets up the various interrupt trigger mechanisms for the
+//! specified pin(s) on the selected GPIO port.
+//!
+//! The parameter \e ulIntType is an enumerated data type that can be one of
+//! the following values:
+//!
+//! - \b GPIO_FALLING_EDGE
+//! - \b GPIO_RISING_EDGE
+//! - \b GPIO_BOTH_EDGES
+//! - \b GPIO_LOW_LEVEL
+//! - \b GPIO_HIGH_LEVEL
+//!
+//! where the different values describe the interrupt detection mechanism
+//! (edge or level) and the particular triggering event (falling, rising,
+//! or both edges for edge detect, low or high for level detect).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note In order to avoid any spurious interrupts, the user must
+//! ensure that the GPIO inputs remain stable for the duration of
+//! this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulIntType)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT((ulIntType == GPIO_FALLING_EDGE) ||
+ (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) ||
+ (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL));
+
+ //
+ // Set the pin interrupt type.
+ //
+ HWREG(ulPort + GPIO_O_IBE) = ((ulIntType & 1) ?
+ (HWREG(ulPort + GPIO_O_IBE) | ucPins) :
+ (HWREG(ulPort + GPIO_O_IBE) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_IS) = ((ulIntType & 2) ?
+ (HWREG(ulPort + GPIO_O_IS) | ucPins) :
+ (HWREG(ulPort + GPIO_O_IS) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_IEV) = ((ulIntType & 4) ?
+ (HWREG(ulPort + GPIO_O_IEV) | ucPins) :
+ (HWREG(ulPort + GPIO_O_IEV) & ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the interrupt type for a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//!
+//! This function gets the interrupt type for a specified pin on the selected
+//! GPIO port. The pin can be configured as a falling edge, rising edge, or
+//! both edge detected interrupt, or it can be configured as a low level or
+//! high level detected interrupt. The type of interrupt detection mechanism
+//! is returned as an enumerated data type.
+//!
+//! \return Returns one of the enumerated data types described for
+//! GPIOIntTypeSet().
+//
+//*****************************************************************************
+unsigned long
+GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin)
+{
+ unsigned long ulIBE, ulIS, ulIEV;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT(ucPin < 8);
+
+ //
+ // Convert from a pin number to a bit position.
+ //
+ ucPin = 1 << ucPin;
+
+ //
+ // Return the pin interrupt type.
+ //
+ ulIBE = HWREG(ulPort + GPIO_O_IBE);
+ ulIS = HWREG(ulPort + GPIO_O_IS);
+ ulIEV = HWREG(ulPort + GPIO_O_IEV);
+ return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) |
+ ((ulIEV & ucPin) ? 4 : 0));
+}
+
+//*****************************************************************************
+//
+//! Sets the pad configuration for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulStrength specifies the output drive strength.
+//! \param ulPinType specifies the pin type.
+//!
+//! This function sets the drive strength and type for the specified pin(s)
+//! on the selected GPIO port. For pin(s) configured as input ports, the
+//! pad is configured as requested, but the only real effect on the input
+//! is the configuration of the pull-up or pull-down termination.
+//!
+//! The parameter \e ulStrength can be one of the following values:
+//!
+//! - \b GPIO_STRENGTH_2MA
+//! - \b GPIO_STRENGTH_4MA
+//! - \b GPIO_STRENGTH_8MA
+//! - \b GPIO_STRENGTH_8MA_SC
+//!
+//! where \b GPIO_STRENGTH_xMA specifies either 2, 4, or 8 mA output drive
+//! strength, and \b GPIO_OUT_STRENGTH_8MA_SC specifies 8 mA output drive with
+//! slew control.
+//!
+//! The parameter \e ulPinType can be one of the following values:
+//!
+//! - \b GPIO_PIN_TYPE_STD
+//! - \b GPIO_PIN_TYPE_STD_WPU
+//! - \b GPIO_PIN_TYPE_STD_WPD
+//! - \b GPIO_PIN_TYPE_OD
+//! - \b GPIO_PIN_TYPE_OD_WPU
+//! - \b GPIO_PIN_TYPE_OD_WPD
+//! - \b GPIO_PIN_TYPE_ANALOG
+//!
+//! where \b GPIO_PIN_TYPE_STD* specifies a push-pull pin, \b GPIO_PIN_TYPE_OD*
+//! specifies an open-drain pin, \b *_WPU specifies a weak pull-up, \b *_WPD
+//! specifies a weak pull-down, and \b GPIO_PIN_TYPE_ANALOG specifies an
+//! analog input (for the comparators).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulStrength, unsigned long ulPinType)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT((ulStrength == GPIO_STRENGTH_2MA) ||
+ (ulStrength == GPIO_STRENGTH_4MA) ||
+ (ulStrength == GPIO_STRENGTH_8MA) ||
+ (ulStrength == GPIO_STRENGTH_8MA_SC));
+ ASSERT((ulPinType == GPIO_PIN_TYPE_STD) ||
+ (ulPinType == GPIO_PIN_TYPE_STD_WPU) ||
+ (ulPinType == GPIO_PIN_TYPE_STD_WPD) ||
+ (ulPinType == GPIO_PIN_TYPE_OD) ||
+ (ulPinType == GPIO_PIN_TYPE_OD_WPU) ||
+ (ulPinType == GPIO_PIN_TYPE_OD_WPD) ||
+ (ulPinType == GPIO_PIN_TYPE_ANALOG))
+
+ //
+ // Set the output drive strength.
+ //
+ HWREG(ulPort + GPIO_O_DR2R) = ((ulStrength & 1) ?
+ (HWREG(ulPort + GPIO_O_DR2R) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DR2R) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_DR4R) = ((ulStrength & 2) ?
+ (HWREG(ulPort + GPIO_O_DR4R) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DR4R) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_DR8R) = ((ulStrength & 4) ?
+ (HWREG(ulPort + GPIO_O_DR8R) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DR8R) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_SLR) = ((ulStrength & 8) ?
+ (HWREG(ulPort + GPIO_O_SLR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_SLR) & ~(ucPins)));
+
+ //
+ // Set the pin type.
+ //
+ HWREG(ulPort + GPIO_O_ODR) = ((ulPinType & 1) ?
+ (HWREG(ulPort + GPIO_O_ODR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_ODR) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_PUR) = ((ulPinType & 2) ?
+ (HWREG(ulPort + GPIO_O_PUR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_PUR) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_PDR) = ((ulPinType & 4) ?
+ (HWREG(ulPort + GPIO_O_PDR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_PDR) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_DEN) = ((ulPinType & 8) ?
+ (HWREG(ulPort + GPIO_O_DEN) | ucPins) :
+ (HWREG(ulPort + GPIO_O_DEN) & ~(ucPins)));
+
+ //
+ // Set the analog mode select register. This register only appears in
+ // DustDevil-class (and later) devices, but is a harmless write on
+ // Sandstorm- and Fury-class devices.
+ //
+ HWREG(ulPort + GPIO_O_AMSEL) =
+ ((ulPinType == GPIO_PIN_TYPE_ANALOG) ?
+ (HWREG(ulPort + GPIO_O_AMSEL) | ucPins) :
+ (HWREG(ulPort + GPIO_O_AMSEL) & ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the pad configuration for a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//! \param pulStrength is a pointer to storage for the output drive strength.
+//! \param pulPinType is a pointer to storage for the output drive type.
+//!
+//! This function gets the pad configuration for a specified pin on the
+//! selected GPIO port. The values returned in \e pulStrength and
+//! \e pulPinType correspond to the values used in GPIOPadConfigSet(). This
+//! function also works for pin(s) configured as input pin(s); however, the
+//! only meaningful data returned is whether the pin is terminated with a
+//! pull-up or down resistor.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
+ unsigned long *pulStrength, unsigned long *pulPinType)
+{
+ unsigned long ulTemp1, ulTemp2, ulTemp3, ulTemp4;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT(ucPin < 8);
+
+ //
+ // Convert from a pin number to a bit position.
+ //
+ ucPin = (1 << ucPin);
+
+ //
+ // Get the drive strength for this pin.
+ //
+ ulTemp1 = HWREG(ulPort + GPIO_O_DR2R);
+ ulTemp2 = HWREG(ulPort + GPIO_O_DR4R);
+ ulTemp3 = HWREG(ulPort + GPIO_O_DR8R);
+ ulTemp4 = HWREG(ulPort + GPIO_O_SLR);
+ *pulStrength = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) |
+ ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0));
+
+ //
+ // Get the pin type.
+ //
+ ulTemp1 = HWREG(ulPort + GPIO_O_ODR);
+ ulTemp2 = HWREG(ulPort + GPIO_O_PUR);
+ ulTemp3 = HWREG(ulPort + GPIO_O_PDR);
+ ulTemp4 = HWREG(ulPort + GPIO_O_DEN);
+ *pulPinType = (((ulTemp1 & ucPin) ? 1 : 0) | ((ulTemp2 & ucPin) ? 2 : 0) |
+ ((ulTemp3 & ucPin) ? 4 : 0) | ((ulTemp4 & ucPin) ? 8 : 0));
+}
+
+//*****************************************************************************
+//
+//! Enables interrupts for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Unmasks the interrupt for the specified pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Enable the interrupts.
+ //
+ HWREG(ulPort + GPIO_O_IM) |= ucPins;
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Masks the interrupt for the specified pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Disable the interrupts.
+ //
+ HWREG(ulPort + GPIO_O_IM) &= ~(ucPins);
+}
+
+//*****************************************************************************
+//
+//! Gets interrupt status for the specified GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status will be returned.
+//!
+//! \return Returns a bit-packed byte, where each bit that is set identifies
+//! an active masked or raw interrupt, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//! Bits 31:8 should be ignored.
+//
+//*****************************************************************************
+long
+GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Return the interrupt status.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulPort + GPIO_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulPort + GPIO_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the interrupt for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Clears the interrupt for the specified pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Clear the interrupts.
+ //
+ HWREG(ulPort + GPIO_O_ICR) = ucPins;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
+//! function.
+//!
+//! This function will ensure that the interrupt handler specified by
+//! \e pfnIntHandler is called when an interrupt is detected from the selected
+//! GPIO port. This function will also enable the corresponding GPIO interrupt
+//! in the interrupt controller; individual pin interrupts and interrupt
+//! sources must be enabled with GPIOPinIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPortIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Get the interrupt number associated with the specified GPIO.
+ //
+ ulPort = GPIOGetIntNumber(ulPort);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulPort, pfnIntHandler);
+
+ //
+ // Enable the GPIO interrupt.
+ //
+ IntEnable(ulPort);
+}
+
+//*****************************************************************************
+//
+//! Removes an interrupt handler for a GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function will unregister the interrupt handler for the specified
+//! GPIO port. This function will also disable the corresponding
+//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
+//! and interrupt sources must be disabled with GPIOPinIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPortIntUnregister(unsigned long ulPort)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Get the interrupt number associated with the specified GPIO.
+ //
+ ulPort = GPIOGetIntNumber(ulPort);
+
+ //
+ // Disable the GPIO interrupt.
+ //
+ IntDisable(ulPort);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulPort);
+}
+
+//*****************************************************************************
+//
+//! Reads the values present of the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The values at the specified pin(s) are read, as specified by \e ucPins.
+//! Values are returned for both input and output pin(s), and the value
+//! for pin(s) that are not specified by \e ucPins are set to 0.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return Returns a bit-packed byte providing the state of the specified
+//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents
+//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins
+//! is returned as a 0. Bits 31:8 should be ignored.
+//
+//*****************************************************************************
+long
+GPIOPinRead(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Return the pin value(s).
+ //
+ return(HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))));
+}
+
+//*****************************************************************************
+//
+//! Writes a value to the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ucVal is the value to write to the pin(s).
+//!
+//! Writes the corresponding bit values to the output pin(s) specified by
+//! \e ucPins. Writing to a pin configured as an input pin has no effect.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Write the pins.
+ //
+ HWREG(ulPort + (GPIO_O_DATA + (ucPins << 2))) = ucVal;
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as analog-to-digital converter inputs.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The analog-to-digital converter input pins must be properly configured
+//! to function correctly on DustDevil-class devices. This function provides
+//! the proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an ADC input; it only
+//! configures an ADC input pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+ //
+ // Set the pad(s) for analog operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as a CAN device.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The CAN pins must be properly configured for the CAN peripherals to
+//! function correctly. This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a CAN pin; it only
+//! configures a CAN pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as an analog comparator input.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The analog comparator input pins must be properly configured for the analog
+//! comparator to function correctly. This function provides the proper
+//! configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an analog comparator input;
+//! it only configures an analog comparator pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+ //
+ // Set the pad(s) for analog operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as GPIO inputs.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! GPIO inputs; this is especially true of Fury-class devices where the
+//! digital input enable is turned off by default. This function provides the
+//! proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as GPIO outputs.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! GPIO outputs; this is especially true of Fury-class devices where the
+//! digital input enable is turned off by default. This function provides the
+//! proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be outputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use as GPIO open drain outputs.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The GPIO pins must be properly configured in order to function correctly as
+//! GPIO outputs; this is especially true of Fury-class devices where the
+//! digital input enable is turned off by default. This function provides the
+//! proper configuration for those pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeGPIOOutputOD(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be outputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_OUT);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the I2C peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The I2C pins must be properly configured for the I2C peripheral to function
+//! correctly. This function provides the proper configuration for those
+//! pin(s).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an I2C pin; it only
+//! configures an I2C pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for open-drain operation with a weak pull-up.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD_WPU);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the PWM peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The PWM pins must be properly configured for the PWM peripheral to function
+//! correctly. This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a PWM pin; it only
+//! configures a PWM pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the QEI peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The QEI pins must be properly configured for the QEI peripheral to function
+//! correctly. This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, not using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a QEI pin; it only
+//! configures a QEI pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation with a weak pull-up.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the SSI peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The SSI pins must be properly configured for the SSI peripheral to function
+//! correctly. This function provides a typical configuration for those
+//! pin(s); other configurations may work as well depending upon the board
+//! setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a SSI pin; it only
+//! configures a SSI pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the Timer peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The CCP pins must be properly configured for the timer peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a timer pin; it only
+//! configures a timer pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the UART peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The UART pins must be properly configured for the UART peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a UART pin; it only
+//! configures a UART pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the USB peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Some USB digital pins must be properly configured for the USB peripheral to
+//! function correctly. This function provides a typical configuration for
+//! the digital USB pin(s); other configurations may work as well depending
+//! upon the board setup (for example, using the on-chip pull-ups).
+//!
+//! This function should only be used with EPEN and PFAULT pins as all other
+//! USB pins are analog in nature or are not used in devices without OTG
+//! functionality.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a USB pin; it only
+//! configures a USB pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the USB peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Some USB analog pins must be properly configured for the USB peripheral to
+//! function correctly. This function provides the proper configuration for
+//! any USB pin(s). This can also be used to configure the EPEN and PFAULT pins
+//! so that they are no longer used by the USB controller.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a USB pin; it only
+//! configures a USB pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be inputs.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_IN);
+
+ //
+ // Set the pad(s) for analog operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the I2S peripheral.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! Some I2S pins must be properly configured for the I2S peripheral to
+//! function correctly. This function provides a typical configuration for
+//! the digital I2S pin(s); other configurations may work as well depending
+//! upon the board setup (for example, using the on-chip pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into a I2S pin; it only
+//! configures a I2S pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the Ethernet peripheral as LED signals.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The Ethernet peripheral provides two signals that can be used to drive
+//! an LED (e.g. for link status/activity). This function provides a typical
+//! configuration for the pins.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an Ethernet LED pin; it only
+//! configures an Ethernet LED pin for proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures pin(s) for use by the external peripheral interface.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The external peripheral interface pins must be properly configured for the
+//! external peripheral interface to function correctly. This function
+//! provides a typica configuration for those pin(s); other configurations may
+//! work as well depending upon the board setup (for exampe, using the on-chip
+//! pull-ups).
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note This cannot be used to turn any pin into an external peripheral
+//! interface pin; it only configures an external peripheral interface pin for
+//! proper operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Make the pin(s) be peripheral controlled.
+ //
+ GPIODirModeSet(ulPort, ucPins, GPIO_DIR_MODE_HW);
+
+ //
+ // Set the pad(s) for standard push-pull operation.
+ //
+ GPIOPadConfigSet(ulPort, ucPins, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
+}
+
+//*****************************************************************************
+//
+//! Configures the alternate function of a GPIO pin.
+//!
+//! \param ulPinConfig is the pin configuration value, specified as only one of
+//! the \b GPIO_P??_??? values.
+//!
+//! This function configures the pin mux that selects the peripheral function
+//! associated with a particular GPIO pin. Only one peripheral function at a
+//! time can be associated with a GPIO pin, and each peripheral function should
+//! only be associated with a single GPIO pin at a time (despite the fact that
+//! many of them can be associated with more than one GPIO pin).
+//!
+//! \note This function is only valid on Tempest-class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinConfigure(unsigned long ulPinConfig)
+{
+ unsigned long ulBase, ulShift;
+
+ //
+ // Check the argument.
+ //
+ ASSERT(((ulPinConfig >> 16) & 0xff) < 9);
+ ASSERT(((ulPinConfig >> 8) & 0xe3) == 0);
+
+ //
+ // Extract the base address index from the input value.
+ //
+ ulBase = (ulPinConfig >> 16) & 0xff;
+
+ //
+ // Get the base address of the GPIO module, selecting either the APB or the
+ // AHB aperture as appropriate.
+ //
+ if(HWREG(SYSCTL_GPIOHBCTL) & (1 << ulBase))
+ {
+ ulBase = g_pulGPIOBaseAddrs[(ulBase << 1) + 1];
+ }
+ else
+ {
+ ulBase = g_pulGPIOBaseAddrs[ulBase << 1];
+ }
+
+ //
+ // Extract the shift from the input value.
+ //
+ ulShift = (ulPinConfig >> 8) & 0xff;
+
+ //
+ // Write the requested pin muxing value for this GPIO pin.
+ //
+ HWREG(ulBase + GPIO_O_PCTL) = ((HWREG(ulBase + GPIO_O_PCTL) &
+ ~(0xf << ulShift)) |
+ ((ulPinConfig & 0xf) << ulShift));
+
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/gpio.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/gpio.h
new file mode 100644
index 00000000..3b60fc77
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/gpio.h
@@ -0,0 +1,767 @@
+//*****************************************************************************
+//
+// gpio.h - Defines and Macros for GPIO API.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following values define the bit field for the ucPins argument to several
+// of the APIs.
+//
+//*****************************************************************************
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
+// returned from GPIODirModeGet.
+//
+//*****************************************************************************
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
+#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
+// returned from GPIOIntTypeGet.
+//
+//*****************************************************************************
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
+#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.
+//
+//*****************************************************************************
+#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
+#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
+#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
+#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.
+//
+//*****************************************************************************
+#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
+#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
+#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
+#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
+#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
+#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
+#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOPinConfigure as the ulPinConfig parameter.
+//
+//*****************************************************************************
+//
+// GPIO pin A0
+//
+#define GPIO_PA0_U0RX 0x00000001
+#define GPIO_PA0_I2C1SCL 0x00000008
+#define GPIO_PA0_U1RX 0x00000009
+
+//
+// GPIO pin A1
+//
+#define GPIO_PA1_U0TX 0x00000401
+#define GPIO_PA1_I2C1SDA 0x00000408
+#define GPIO_PA1_U1TX 0x00000409
+
+//
+// GPIO pin A2
+//
+#define GPIO_PA2_SSI0CLK 0x00000801
+#define GPIO_PA2_PWM4 0x00000804
+#define GPIO_PA2_I2S0RXSD 0x00000809
+
+//
+// GPIO pin A3
+//
+#define GPIO_PA3_SSI0FSS 0x00000c01
+#define GPIO_PA3_PWM5 0x00000c04
+#define GPIO_PA3_I2S0RXMCLK 0x00000c09
+
+//
+// GPIO pin A4
+//
+#define GPIO_PA4_SSI0RX 0x00001001
+#define GPIO_PA4_PWM6 0x00001004
+#define GPIO_PA4_CAN0RX 0x00001005
+#define GPIO_PA4_I2S0TXSCK 0x00001009
+
+//
+// GPIO pin A5
+//
+#define GPIO_PA5_SSI0TX 0x00001401
+#define GPIO_PA5_PWM7 0x00001404
+#define GPIO_PA5_CAN0TX 0x00001405
+#define GPIO_PA5_I2S0TXWS 0x00001409
+
+//
+// GPIO pin A6
+//
+#define GPIO_PA6_I2C1SCL 0x00001801
+#define GPIO_PA6_CCP1 0x00001802
+#define GPIO_PA6_PWM0 0x00001804
+#define GPIO_PA6_PWM4 0x00001805
+#define GPIO_PA6_CAN0RX 0x00001806
+#define GPIO_PA6_USB0EPEN 0x00001808
+#define GPIO_PA6_U1CTS 0x00001809
+
+//
+// GPIO pin A7
+//
+#define GPIO_PA7_I2C1SDA 0x00001c01
+#define GPIO_PA7_CCP4 0x00001c02
+#define GPIO_PA7_PWM1 0x00001c04
+#define GPIO_PA7_PWM5 0x00001c05
+#define GPIO_PA7_CAN0TX 0x00001c06
+#define GPIO_PA7_CCP3 0x00001c07
+#define GPIO_PA7_USB0PFLT 0x00001c08
+#define GPIO_PA7_U1DCD 0x00001c09
+
+//
+// GPIO pin B0
+//
+#define GPIO_PB0_CCP0 0x00010001
+#define GPIO_PB0_PWM2 0x00010002
+#define GPIO_PB0_U1RX 0x00010005
+
+//
+// GPIO pin B1
+//
+#define GPIO_PB1_CCP2 0x00010401
+#define GPIO_PB1_PWM3 0x00010402
+#define GPIO_PB1_CCP1 0x00010404
+#define GPIO_PB1_U1TX 0x00010405
+
+//
+// GPIO pin B2
+//
+#define GPIO_PB2_I2C0SCL 0x00010801
+#define GPIO_PB2_IDX0 0x00010802
+#define GPIO_PB2_CCP3 0x00010804
+#define GPIO_PB2_CCP0 0x00010805
+#define GPIO_PB2_USB0EPEN 0x00010808
+
+//
+// GPIO pin B3
+//
+#define GPIO_PB3_I2C0SDA 0x00010c01
+#define GPIO_PB3_FAULT0 0x00010c02
+#define GPIO_PB3_FAULT3 0x00010c04
+#define GPIO_PB3_USB0PFLT 0x00010c08
+
+//
+// GPIO pin B4
+//
+#define GPIO_PB4_U2RX 0x00011004
+#define GPIO_PB4_CAN0RX 0x00011005
+#define GPIO_PB4_IDX0 0x00011006
+#define GPIO_PB4_U1RX 0x00011007
+#define GPIO_PB4_EPI0S23 0x00011008
+
+//
+// GPIO pin B5
+//
+#define GPIO_PB5_C0O 0x00011401
+#define GPIO_PB5_CCP5 0x00011402
+#define GPIO_PB5_CCP6 0x00011403
+#define GPIO_PB5_CCP0 0x00011404
+#define GPIO_PB5_CAN0TX 0x00011405
+#define GPIO_PB5_CCP2 0x00011406
+#define GPIO_PB5_U1TX 0x00011407
+#define GPIO_PB5_EPI0S22 0x00011408
+
+//
+// GPIO pin B6
+//
+#define GPIO_PB6_CCP1 0x00011801
+#define GPIO_PB6_CCP7 0x00011802
+#define GPIO_PB6_C0O 0x00011803
+#define GPIO_PB6_FAULT1 0x00011804
+#define GPIO_PB6_IDX0 0x00011805
+#define GPIO_PB6_CCP5 0x00011806
+#define GPIO_PB6_I2S0TXSCK 0x00011809
+
+//
+// GPIO pin B7
+//
+#define GPIO_PB7_NMI 0x00011c04
+
+//
+// GPIO pin C0
+//
+#define GPIO_PC0_TCK 0x00020003
+
+//
+// GPIO pin C1
+//
+#define GPIO_PC1_TMS 0x00020403
+
+//
+// GPIO pin C2
+//
+#define GPIO_PC2_TDI 0x00020803
+
+//
+// GPIO pin C3
+//
+#define GPIO_PC3_TDO 0x00020c03
+
+//
+// GPIO pin C4
+//
+#define GPIO_PC4_CCP5 0x00021001
+#define GPIO_PC4_PHA0 0x00021002
+#define GPIO_PC4_PWM6 0x00021004
+#define GPIO_PC4_CCP2 0x00021005
+#define GPIO_PC4_CCP4 0x00021006
+#define GPIO_PC4_EPI0S2 0x00021008
+#define GPIO_PC4_CCP1 0x00021009
+
+//
+// GPIO pin C5
+//
+#define GPIO_PC5_CCP1 0x00021401
+#define GPIO_PC5_C1O 0x00021402
+#define GPIO_PC5_C0O 0x00021403
+#define GPIO_PC5_FAULT2 0x00021404
+#define GPIO_PC5_CCP3 0x00021405
+#define GPIO_PC5_USB0EPEN 0x00021406
+#define GPIO_PC5_EPI0S3 0x00021408
+
+//
+// GPIO pin C6
+//
+#define GPIO_PC6_CCP3 0x00021801
+#define GPIO_PC6_PHB0 0x00021802
+#define GPIO_PC6_C2O 0x00021803
+#define GPIO_PC6_PWM7 0x00021804
+#define GPIO_PC6_U1RX 0x00021805
+#define GPIO_PC6_CCP0 0x00021806
+#define GPIO_PC6_USB0PFLT 0x00021807
+#define GPIO_PC6_EPI0S4 0x00021808
+
+//
+// GPIO pin C7
+//
+#define GPIO_PC7_CCP4 0x00021c01
+#define GPIO_PC7_PHB0 0x00021c02
+#define GPIO_PC7_CCP0 0x00021c04
+#define GPIO_PC7_U1TX 0x00021c05
+#define GPIO_PC7_USB0PFLT 0x00021c06
+#define GPIO_PC7_C1O 0x00021c07
+#define GPIO_PC7_EPI0S5 0x00021c08
+
+//
+// GPIO pin D0
+//
+#define GPIO_PD0_PWM0 0x00030001
+#define GPIO_PD0_CAN0RX 0x00030002
+#define GPIO_PD0_IDX0 0x00030003
+#define GPIO_PD0_U2RX 0x00030004
+#define GPIO_PD0_U1RX 0x00030005
+#define GPIO_PD0_CCP6 0x00030006
+#define GPIO_PD0_I2S0RXSCK 0x00030008
+#define GPIO_PD0_U1CTS 0x00030009
+
+//
+// GPIO pin D1
+//
+#define GPIO_PD1_PWM1 0x00030401
+#define GPIO_PD1_CAN0TX 0x00030402
+#define GPIO_PD1_PHA0 0x00030403
+#define GPIO_PD1_U2TX 0x00030404
+#define GPIO_PD1_U1TX 0x00030405
+#define GPIO_PD1_CCP7 0x00030406
+#define GPIO_PD1_I2S0RXWS 0x00030408
+#define GPIO_PD1_U1DCD 0x00030409
+#define GPIO_PD1_CCP2 0x0003040a
+#define GPIO_PD1_PHB1 0x0003040b
+
+//
+// GPIO pin D2
+//
+#define GPIO_PD2_U1RX 0x00030801
+#define GPIO_PD2_CCP6 0x00030802
+#define GPIO_PD2_PWM2 0x00030803
+#define GPIO_PD2_CCP5 0x00030804
+#define GPIO_PD2_EPI0S20 0x00030808
+
+//
+// GPIO pin D3
+//
+#define GPIO_PD3_U1TX 0x00030c01
+#define GPIO_PD3_CCP7 0x00030c02
+#define GPIO_PD3_PWM3 0x00030c03
+#define GPIO_PD3_CCP0 0x00030c04
+#define GPIO_PD3_EPI0S21 0x00030c08
+
+//
+// GPIO pin D4
+//
+#define GPIO_PD4_CCP0 0x00031001
+#define GPIO_PD4_CCP3 0x00031002
+#define GPIO_PD4_I2S0RXSD 0x00031008
+#define GPIO_PD4_U1RI 0x00031009
+#define GPIO_PD4_EPI0S19 0x0003100a
+
+//
+// GPIO pin D5
+//
+#define GPIO_PD5_CCP2 0x00031401
+#define GPIO_PD5_CCP4 0x00031402
+#define GPIO_PD5_I2S0RXMCLK 0x00031408
+#define GPIO_PD5_U2RX 0x00031409
+#define GPIO_PD5_EPI0S28 0x0003140a
+
+//
+// GPIO pin D6
+//
+#define GPIO_PD6_FAULT0 0x00031801
+#define GPIO_PD6_I2S0TXSCK 0x00031808
+#define GPIO_PD6_U2TX 0x00031809
+#define GPIO_PD6_EPI0S29 0x0003180a
+
+//
+// GPIO pin D7
+//
+#define GPIO_PD7_IDX0 0x00031c01
+#define GPIO_PD7_C0O 0x00031c02
+#define GPIO_PD7_CCP1 0x00031c03
+#define GPIO_PD7_I2S0TXWS 0x00031c08
+#define GPIO_PD7_U1DTR 0x00031c09
+#define GPIO_PD7_EPI0S30 0x00031c0a
+
+//
+// GPIO pin E0
+//
+#define GPIO_PE0_PWM4 0x00040001
+#define GPIO_PE0_SSI1CLK 0x00040002
+#define GPIO_PE0_CCP3 0x00040003
+#define GPIO_PE0_EPI0S8 0x00040008
+#define GPIO_PE0_USB0PFLT 0x00040009
+
+//
+// GPIO pin E1
+//
+#define GPIO_PE1_PWM5 0x00040401
+#define GPIO_PE1_SSI1FSS 0x00040402
+#define GPIO_PE1_FAULT0 0x00040403
+#define GPIO_PE1_CCP2 0x00040404
+#define GPIO_PE1_CCP6 0x00040405
+#define GPIO_PE1_EPI0S9 0x00040408
+
+//
+// GPIO pin E2
+//
+#define GPIO_PE2_CCP4 0x00040801
+#define GPIO_PE2_SSI1RX 0x00040802
+#define GPIO_PE2_PHB1 0x00040803
+#define GPIO_PE2_PHA0 0x00040804
+#define GPIO_PE2_CCP2 0x00040805
+#define GPIO_PE2_EPI0S24 0x00040808
+
+//
+// GPIO pin E3
+//
+#define GPIO_PE3_CCP1 0x00040c01
+#define GPIO_PE3_SSI1TX 0x00040c02
+#define GPIO_PE3_PHA1 0x00040c03
+#define GPIO_PE3_PHB0 0x00040c04
+#define GPIO_PE3_CCP7 0x00040c05
+#define GPIO_PE3_EPI0S25 0x00040c08
+
+//
+// GPIO pin E4
+//
+#define GPIO_PE4_CCP3 0x00041001
+#define GPIO_PE4_FAULT0 0x00041004
+#define GPIO_PE4_U2TX 0x00041005
+#define GPIO_PE4_CCP2 0x00041006
+#define GPIO_PE4_I2S0TXWS 0x00041009
+
+//
+// GPIO pin E5
+//
+#define GPIO_PE5_CCP5 0x00041401
+#define GPIO_PE5_I2S0TXSD 0x00041409
+
+//
+// GPIO pin E6
+//
+#define GPIO_PE6_PWM4 0x00041801
+#define GPIO_PE6_C1O 0x00041802
+#define GPIO_PE6_U1CTS 0x00041809
+
+//
+// GPIO pin E7
+//
+#define GPIO_PE7_PWM5 0x00041c01
+#define GPIO_PE7_C2O 0x00041c02
+#define GPIO_PE7_U1DCD 0x00041c09
+
+//
+// GPIO pin F0
+//
+#define GPIO_PF0_CAN1RX 0x00050001
+#define GPIO_PF0_PHB0 0x00050002
+#define GPIO_PF0_PWM0 0x00050003
+#define GPIO_PF0_I2S0TXSD 0x00050008
+#define GPIO_PF0_U1DSR 0x00050009
+
+//
+// GPIO pin F1
+//
+#define GPIO_PF1_CAN1TX 0x00050401
+#define GPIO_PF1_IDX1 0x00050402
+#define GPIO_PF1_PWM1 0x00050403
+#define GPIO_PF1_I2S0TXMCLK 0x00050408
+#define GPIO_PF1_U1RTS 0x00050409
+#define GPIO_PF1_CCP3 0x0005040a
+
+//
+// GPIO pin F2
+//
+#define GPIO_PF2_LED1 0x00050801
+#define GPIO_PF2_PWM4 0x00050802
+#define GPIO_PF2_PWM2 0x00050804
+#define GPIO_PF2_SSI1CLK 0x00050809
+
+//
+// GPIO pin F3
+//
+#define GPIO_PF3_LED0 0x00050c01
+#define GPIO_PF3_PWM5 0x00050c02
+#define GPIO_PF3_PWM3 0x00050c04
+#define GPIO_PF3_SSI1FSS 0x00050c09
+
+//
+// GPIO pin F4
+//
+#define GPIO_PF4_CCP0 0x00051001
+#define GPIO_PF4_C0O 0x00051002
+#define GPIO_PF4_FAULT0 0x00051004
+#define GPIO_PF4_EPI0S12 0x00051008
+#define GPIO_PF4_SSI1RX 0x00051009
+
+//
+// GPIO pin F5
+//
+#define GPIO_PF5_CCP2 0x00051401
+#define GPIO_PF5_C1O 0x00051402
+#define GPIO_PF5_EPI0S15 0x00051408
+#define GPIO_PF5_SSI1TX 0x00051409
+
+//
+// GPIO pin F6
+//
+#define GPIO_PF6_CCP1 0x00051801
+#define GPIO_PF6_C2O 0x00051802
+#define GPIO_PF6_PHA0 0x00051804
+#define GPIO_PF6_I2S0TXMCLK 0x00051809
+#define GPIO_PF6_U1RTS 0x0005180a
+
+//
+// GPIO pin F7
+//
+#define GPIO_PF7_CCP4 0x00051c01
+#define GPIO_PF7_PHB0 0x00051c04
+#define GPIO_PF7_EPI0S12 0x00051c08
+#define GPIO_PF7_FAULT1 0x00051c09
+
+//
+// GPIO pin G0
+//
+#define GPIO_PG0_U2RX 0x00060001
+#define GPIO_PG0_PWM0 0x00060002
+#define GPIO_PG0_I2C1SCL 0x00060003
+#define GPIO_PG0_PWM4 0x00060004
+#define GPIO_PG0_USB0EPEN 0x00060007
+#define GPIO_PG0_EPI0S13 0x00060008
+
+//
+// GPIO pin G1
+//
+#define GPIO_PG1_U2TX 0x00060401
+#define GPIO_PG1_PWM1 0x00060402
+#define GPIO_PG1_I2C1SDA 0x00060403
+#define GPIO_PG1_PWM5 0x00060404
+#define GPIO_PG1_EPI0S14 0x00060408
+
+//
+// GPIO pin G2
+//
+#define GPIO_PG2_PWM0 0x00060801
+#define GPIO_PG2_FAULT0 0x00060804
+#define GPIO_PG2_IDX1 0x00060808
+#define GPIO_PG2_I2S0RXSD 0x00060809
+
+//
+// GPIO pin G3
+//
+#define GPIO_PG3_PWM1 0x00060c01
+#define GPIO_PG3_FAULT2 0x00060c04
+#define GPIO_PG3_FAULT0 0x00060c08
+#define GPIO_PG3_I2S0RXMCLK 0x00060c09
+
+//
+// GPIO pin G4
+//
+#define GPIO_PG4_CCP3 0x00061001
+#define GPIO_PG4_FAULT1 0x00061004
+#define GPIO_PG4_EPI0S15 0x00061008
+#define GPIO_PG4_PWM6 0x00061009
+#define GPIO_PG4_U1RI 0x0006100a
+
+//
+// GPIO pin G5
+//
+#define GPIO_PG5_CCP5 0x00061401
+#define GPIO_PG5_IDX0 0x00061404
+#define GPIO_PG5_FAULT1 0x00061405
+#define GPIO_PG5_PWM7 0x00061408
+#define GPIO_PG5_I2S0RXSCK 0x00061409
+#define GPIO_PG5_U1DTR 0x0006140a
+
+//
+// GPIO pin G6
+//
+#define GPIO_PG6_PHA1 0x00061801
+#define GPIO_PG6_PWM6 0x00061804
+#define GPIO_PG6_FAULT1 0x00061808
+#define GPIO_PG6_I2S0RXWS 0x00061809
+#define GPIO_PG6_U1RI 0x0006180a
+
+//
+// GPIO pin G7
+//
+#define GPIO_PG7_PHB1 0x00061c01
+#define GPIO_PG7_PWM7 0x00061c04
+#define GPIO_PG7_CCP5 0x00061c08
+#define GPIO_PG7_EPI0S31 0x00061c09
+
+//
+// GPIO pin H0
+//
+#define GPIO_PH0_CCP6 0x00070001
+#define GPIO_PH0_PWM2 0x00070002
+#define GPIO_PH0_EPI0S6 0x00070008
+#define GPIO_PH0_PWM4 0x00070009
+
+//
+// GPIO pin H1
+//
+#define GPIO_PH1_CCP7 0x00070401
+#define GPIO_PH1_PWM3 0x00070402
+#define GPIO_PH1_EPI0S7 0x00070408
+#define GPIO_PH1_PWM5 0x00070409
+
+//
+// GPIO pin H2
+//
+#define GPIO_PH2_IDX1 0x00070801
+#define GPIO_PH2_C1O 0x00070802
+#define GPIO_PH2_FAULT3 0x00070804
+#define GPIO_PH2_EPI0S1 0x00070808
+
+//
+// GPIO pin H3
+//
+#define GPIO_PH3_PHB0 0x00070c01
+#define GPIO_PH3_FAULT0 0x00070c02
+#define GPIO_PH3_USB0EPEN 0x00070c04
+#define GPIO_PH3_EPI0S0 0x00070c08
+
+//
+// GPIO pin H4
+//
+#define GPIO_PH4_USB0PFLT 0x00071004
+#define GPIO_PH4_EPI0S10 0x00071008
+#define GPIO_PH4_SSI1CLK 0x0007100b
+
+//
+// GPIO pin H5
+//
+#define GPIO_PH5_EPI0S11 0x00071408
+#define GPIO_PH5_FAULT2 0x0007140a
+#define GPIO_PH5_SSI1FSS 0x0007140b
+
+//
+// GPIO pin H6
+//
+#define GPIO_PH6_EPI0S26 0x00071808
+#define GPIO_PH6_PWM4 0x0007180a
+#define GPIO_PH6_SSI1RX 0x0007180b
+
+//
+// GPIO pin H7
+//
+#define GPIO_PH7_EPI0S27 0x00071c08
+#define GPIO_PH7_PWM5 0x00071c0a
+#define GPIO_PH7_SSI1TX 0x00071c0b
+
+//
+// GPIO pin J0
+//
+#define GPIO_PJ0_EPI0S16 0x00080008
+#define GPIO_PJ0_PWM0 0x0008000a
+#define GPIO_PJ0_I2C1SCL 0x0008000b
+
+//
+// GPIO pin J1
+//
+#define GPIO_PJ1_EPI0S17 0x00080408
+#define GPIO_PJ1_USB0PFLT 0x00080409
+#define GPIO_PJ1_PWM1 0x0008040a
+#define GPIO_PJ1_I2C1SDA 0x0008040b
+
+//
+// GPIO pin J2
+//
+#define GPIO_PJ2_EPI0S18 0x00080808
+#define GPIO_PJ2_CCP0 0x00080809
+#define GPIO_PJ2_FAULT0 0x0008080a
+
+//
+// GPIO pin J3
+//
+#define GPIO_PJ3_EPI0S19 0x00080c08
+#define GPIO_PJ3_U1CTS 0x00080c09
+#define GPIO_PJ3_CCP6 0x00080c0a
+
+//
+// GPIO pin J4
+//
+#define GPIO_PJ4_EPI0S28 0x00081008
+#define GPIO_PJ4_U1DCD 0x00081009
+#define GPIO_PJ4_CCP4 0x0008100a
+
+//
+// GPIO pin J5
+//
+#define GPIO_PJ5_EPI0S29 0x00081408
+#define GPIO_PJ5_U1DSR 0x00081409
+#define GPIO_PJ5_CCP2 0x0008140a
+
+//
+// GPIO pin J6
+//
+#define GPIO_PJ6_EPI0S30 0x00081808
+#define GPIO_PJ6_U1RTS 0x00081809
+#define GPIO_PJ6_CCP1 0x0008180a
+
+//
+// GPIO pin J7
+//
+#define GPIO_PJ7_U1DTR 0x00081c09
+#define GPIO_PJ7_CCP0 0x00081c0a
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulPinIO);
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulIntType);
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulStrength,
+ unsigned long ulPadType);
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
+ unsigned long *pulStrength,
+ unsigned long *pulPadType);
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPortIntRegister(unsigned long ulPort,
+ void (*pfnIntHandler)(void));
+extern void GPIOPortIntUnregister(unsigned long ulPort);
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
+ unsigned char ucVal);
+extern void GPIOPinConfigure(unsigned long ulPinConfig);
+extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
+ unsigned char ucPins);
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __GPIO_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/hibernate.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/hibernate.c
new file mode 100644
index 00000000..2e4f858e
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/hibernate.c
@@ -0,0 +1,962 @@
+//*****************************************************************************
+//
+// hibernate.c - Driver for the Hibernation module
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup hibernate_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_hibernate.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/hibernate.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+
+//*****************************************************************************
+//
+// The delay in microseconds for writing to the Hibernation module registers.
+//
+//*****************************************************************************
+#define DELAY_USECS 95
+
+//*****************************************************************************
+//
+// The number of processor cycles to execute one pass of the delay loop.
+//
+//*****************************************************************************
+#define LOOP_CYCLES 3
+
+//*****************************************************************************
+//
+// The calculated number of delay loops to achieve the write delay.
+//
+//*****************************************************************************
+static unsigned long g_ulWriteDelay;
+
+//*****************************************************************************
+//
+//! \internal
+//!
+//! Polls until the write complete (WRC) bit in the hibernate control register
+//! is set.
+//!
+//! \param None.
+//!
+//! On non-Fury-class devices, the hibernate module provides an indication when
+//! any write is completed. This is used to pace writes to the module. This
+//! function merely polls this bit and returns as soon as it is set. At this
+//! point, it is safe to perform another write to the module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateWriteComplete(void)
+{
+ //
+ // Spin until the write complete bit is set.
+ //
+ while(!(HWREG(HIB_CTL) & HIB_CTL_WRC))
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables the Hibernation module for operation.
+//!
+//! \param ulHibClk is the rate of the clock supplied to the Hibernation
+//! module.
+//!
+//! Enables the Hibernation module for operation. This function should be
+//! called before any of the Hibernation module features are used.
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original HibernateEnable() API and performs the
+//! same actions. A macro is provided in hibernate.h to map the
+//! original API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateEnableExpClk(unsigned long ulHibClk)
+{
+ //
+ // Turn on the clock enable bit.
+ //
+ HWREG(HIB_CTL) |= HIB_CTL_CLK32EN;
+
+ //
+ // For Fury-class devices, compute the number of delay loops that must be
+ // used to achieve the desired delay for writes to the hibernation
+ // registers. This value will be used in calls to SysCtlDelay().
+ //
+ if(CLASS_IS_FURY)
+ {
+ g_ulWriteDelay = (((ulHibClk / 1000) * DELAY_USECS) /
+ (1000L * LOOP_CYCLES));
+ g_ulWriteDelay++;
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables the Hibernation module for operation.
+//!
+//! Disables the Hibernation module for operation. After this function is
+//! called, none of the Hibernation module features are available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateDisable(void)
+{
+ //
+ // Turn off the clock enable bit.
+ //
+ HWREG(HIB_CTL) &= ~HIB_CTL_CLK32EN;
+}
+
+//*****************************************************************************
+//
+//! Selects the clock input for the Hibernation module.
+//!
+//! \param ulClockInput specifies the clock input.
+//!
+//! Configures the clock input for the Hibernation module. The configuration
+//! option chosen depends entirely on hardware design. The clock input for the
+//! module will either be a 32.768 kHz oscillator or a 4.194304 MHz crystal.
+//! The \e ulClockFlags parameter must be one of the following:
+//!
+//! - \b HIBERNATE_CLOCK_SEL_RAW - use the raw signal from a 32.768 kHz
+//! oscillator.
+//! - \b HIBERNATE_CLOCK_SEL_DIV128 - use the crystal input, divided by 128.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateClockSelect(unsigned long ulClockInput)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulClockInput == HIBERNATE_CLOCK_SEL_RAW) ||
+ (ulClockInput == HIBERNATE_CLOCK_SEL_DIV128));
+
+ //
+ // Set the clock selection bit according to the parameter.
+ //
+ HWREG(HIB_CTL) = ulClockInput | (HWREG(HIB_CTL) & ~HIB_CTL_CLKSEL);
+}
+
+//*****************************************************************************
+//
+//! Enables the RTC feature of the Hibernation module.
+//!
+//! Enables the RTC in the Hibernation module. The RTC can be used to wake the
+//! processor from hibernation at a certain time, or to generate interrupts at
+//! certain times. This function must be called before using any of the RTC
+//! features of the Hibernation module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCEnable(void)
+{
+ //
+ // Turn on the RTC enable bit.
+ //
+ HWREG(HIB_CTL) |= HIB_CTL_RTCEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the RTC feature of the Hibernation module.
+//!
+//! Disables the RTC in the Hibernation module. After calling this function
+//! the RTC features of the Hibernation module will not be available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCDisable(void)
+{
+ //
+ // Turn off the RTC enable bit.
+ //
+ HWREG(HIB_CTL) &= ~HIB_CTL_RTCEN;
+}
+
+//*****************************************************************************
+//
+//! Configures the wake conditions for the Hibernation module.
+//!
+//! \param ulWakeFlags specifies which conditions should be used for waking.
+//!
+//! Enables the conditions under which the Hibernation module will wake. The
+//! \e ulWakeFlags parameter is the logical OR of any combination of the
+//! following:
+//!
+//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted.
+//! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateWakeSet(unsigned long ulWakeFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulWakeFlags & ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC)));
+
+ //
+ // Set the specified wake flags in the control register.
+ //
+ HWREG(HIB_CTL) = (ulWakeFlags |
+ (HWREG(HIB_CTL) &
+ ~(HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC)));
+}
+
+//*****************************************************************************
+//
+//! Gets the currently configured wake conditions for the Hibernation module.
+//!
+//! Returns the flags representing the wake configuration for the Hibernation
+//! module. The return value will be a combination of the following flags:
+//!
+//! - \b HIBERNATE_WAKE_PIN - wake when the external wake pin is asserted.
+//! - \b HIBERNATE_WAKE_RTC - wake when one of the RTC matches occurs.
+//!
+//! \return Returns flags indicating the configured wake conditions.
+//
+//*****************************************************************************
+unsigned long
+HibernateWakeGet(void)
+{
+ //
+ // Read the wake bits from the control register and return
+ // those bits to the caller.
+ //
+ return(HWREG(HIB_CTL) & (HIBERNATE_WAKE_PIN | HIBERNATE_WAKE_RTC));
+}
+
+//*****************************************************************************
+//
+//! Configures the low battery detection.
+//!
+//! \param ulLowBatFlags specifies behavior of low battery detection.
+//!
+//! Enables the low battery detection and whether hibernation is allowed if a
+//! low battery is detected. If low battery detection is enabled, then a low
+//! battery condition will be indicated in the raw interrupt status register,
+//! and can also trigger an interrupt. Optionally, hibernation can be aborted
+//! if a low battery is detected.
+//!
+//! The \e ulLowBatFlags parameter is one of the following values:
+//!
+//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low battery condition.
+//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low battery condition, and abort
+//! hibernation if low battery is detected.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateLowBatSet(unsigned long ulLowBatFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulLowBatFlags == HIBERNATE_LOW_BAT_DETECT) ||
+ (ulLowBatFlags == HIBERNATE_LOW_BAT_ABORT));
+
+ //
+ // Set the low battery detect and abort bits in the control register,
+ // according to the parameter.
+ //
+ HWREG(HIB_CTL) = (ulLowBatFlags |
+ (HWREG(HIB_CTL) & ~HIBERNATE_LOW_BAT_ABORT));
+}
+
+//*****************************************************************************
+//
+//! Gets the currently configured low battery detection behavior.
+//!
+//! Returns a value representing the currently configured low battery detection
+//! behavior. The return value will be one of the following:
+//!
+//! - \b HIBERNATE_LOW_BAT_DETECT - detect a low battery condition.
+//! - \b HIBERNATE_LOW_BAT_ABORT - detect a low battery condition, and abort
+//! hibernation if low battery is detected.
+//!
+//! \return Returns a value indicating the configured low battery detection.
+//
+//*****************************************************************************
+unsigned long
+HibernateLowBatGet(void)
+{
+ //
+ // Read the low bat bits from the control register and return those bits to
+ // the caller.
+ //
+ return(HWREG(HIB_CTL) & HIBERNATE_LOW_BAT_ABORT);
+}
+
+//*****************************************************************************
+//
+//! Sets the value of the real time clock (RTC) counter.
+//!
+//! \param ulRTCValue is the new value for the RTC.
+//!
+//! Sets the value of the RTC. The RTC will count seconds if the hardware is
+//! configured correctly. The RTC must be enabled by calling
+//! HibernateRTCEnable() before calling this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCSet(unsigned long ulRTCValue)
+{
+ //
+ // Write the new RTC value to the RTC load register.
+ //
+ HWREG(HIB_RTCLD) = ulRTCValue;
+
+ //
+ // Add a delay here to enforce the required delay between write accesses to
+ // certain Hibernation module registers.
+ //
+ if(CLASS_IS_FURY)
+ {
+ //
+ // Delay a fixed time on Fury-class devices
+ //
+ SysCtlDelay(g_ulWriteDelay);
+ }
+ else
+ {
+ //
+ // Wait for write complete to be signaled on later devices.
+ //
+ HibernateWriteComplete();
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the value of the real time clock (RTC) counter.
+//!
+//! Gets the value of the RTC and returns it to the caller.
+//!
+//! \return Returns the value of the RTC.
+//
+//*****************************************************************************
+unsigned long
+HibernateRTCGet(void)
+{
+ //
+ // Return the value of the RTC counter register to the caller.
+ //
+ return(HWREG(HIB_RTCC));
+}
+
+//*****************************************************************************
+//
+//! Sets the value of the RTC match 0 register.
+//!
+//! \param ulMatch is the value for the match register.
+//!
+//! Sets the match 0 register for the RTC. The Hibernation module can be
+//! configured to wake from hibernation, and/or generate an interrupt when the
+//! value of the RTC counter is the same as the match register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCMatch0Set(unsigned long ulMatch)
+{
+ //
+ // Write the new match value to the match register.
+ //
+ HWREG(HIB_RTCM0) = ulMatch;
+
+ //
+ // Add a delay here to enforce the required delay between write accesses to
+ // certain Hibernation module registers.
+ //
+ if(CLASS_IS_FURY)
+ {
+ //
+ // Delay a fixed time on Fury-class devices
+ //
+ SysCtlDelay(g_ulWriteDelay);
+ }
+ else
+ {
+ //
+ // Wait for write complete to be signaled on later devices.
+ //
+ HibernateWriteComplete();
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the value of the RTC match 0 register.
+//!
+//! Gets the value of the match 0 register for the RTC.
+//!
+//! \return Returns the value of the match register.
+//
+//*****************************************************************************
+unsigned long
+HibernateRTCMatch0Get(void)
+{
+ //
+ // Return the value of the match register to the caller.
+ //
+ return(HWREG(HIB_RTCM0));
+}
+
+//*****************************************************************************
+//
+//! Sets the value of the RTC match 1 register.
+//!
+//! \param ulMatch is the value for the match register.
+//!
+//! Sets the match 1 register for the RTC. The Hibernation module can be
+//! configured to wake from hibernation, and/or generate an interrupt when the
+//! value of the RTC counter is the same as the match register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCMatch1Set(unsigned long ulMatch)
+{
+ //
+ // Write the new match value to the match register.
+ //
+ HWREG(HIB_RTCM1) = ulMatch;
+
+ //
+ // Add a delay here to enforce the required delay between write accesses to
+ // certain Hibernation module registers.
+ //
+ if(CLASS_IS_FURY)
+ {
+ //
+ // Delay a fixed time on Fury-class devices
+ //
+ SysCtlDelay(g_ulWriteDelay);
+ }
+ else
+ {
+ //
+ // Wait for write complete to be signaled on later devices.
+ //
+ HibernateWriteComplete();
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the value of the RTC match 1 register.
+//!
+//! Gets the value of the match 1 register for the RTC.
+//!
+//! \return Returns the value of the match register.
+//
+//*****************************************************************************
+unsigned long
+HibernateRTCMatch1Get(void)
+{
+ //
+ // Return the value of the match register to the caller.
+ //
+ return(HWREG(HIB_RTCM1));
+}
+
+//*****************************************************************************
+//
+//! Sets the value of the RTC predivider trim register.
+//!
+//! \param ulTrim is the new value for the pre-divider trim register.
+//!
+//! Sets the value of the pre-divider trim register. The input time source is
+//! divided by the pre-divider to achieve a one-second clock rate. Once every
+//! 64 seconds, the value of the pre-divider trim register is applied to the
+//! predivider to allow fine-tuning of the RTC rate, in order to make
+//! corrections to the rate. The software application can make adjustments to
+//! the predivider trim register to account for variations in the accuracy of
+//! the input time source. The nominal value is 0x7FFF, and it can be adjusted
+//! up or down in order to fine-tune the RTC rate.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRTCTrimSet(unsigned long ulTrim)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulTrim < 0x10000);
+
+ //
+ // Write the new trim value to the trim register.
+ //
+ HWREG(HIB_RTCT) = ulTrim;
+
+ //
+ // Add a delay here to enforce the required delay between write accesses to
+ // certain Hibernation module registers.
+ //
+ if(CLASS_IS_FURY)
+ {
+ //
+ // Delay a fixed time on Fury-class devices
+ //
+ SysCtlDelay(g_ulWriteDelay);
+ }
+ else
+ {
+ //
+ // Wait for write complete to be signaled on later devices.
+ //
+ HibernateWriteComplete();
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the value of the RTC predivider trim register.
+//!
+//! Gets the value of the pre-divider trim register. This function can be used
+//! to get the current value of the trim register prior to making an adjustment
+//! by using the HibernateRTCTrimSet() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long
+HibernateRTCTrimGet(void)
+{
+ //
+ // Return the value of the trim register to the caller.
+ //
+ return(HWREG(HIB_RTCT));
+}
+
+//*****************************************************************************
+//
+//! Stores data in the non-volatile memory of the Hibernation module.
+//!
+//! \param pulData points to the data that the caller wants to store in the
+//! memory of the Hibernation module.
+//! \param ulCount is the count of 32-bit words to store.
+//!
+//! Stores a set of data in the Hibernation module non-volatile memory. This
+//! memory will be preserved when the power to the processor is turned off, and
+//! can be used to store application state information which will be available
+//! when the processor wakes. Up to 64 32-bit words can be stored in the
+//! non-volatile memory. The data can be restored by calling the
+//! HibernateDataGet() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateDataSet(unsigned long *pulData, unsigned long ulCount)
+{
+ unsigned int uIdx;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulCount <= 64);
+ ASSERT(pulData != 0);
+
+ //
+ // Loop through all the words to be stored, storing one at a time.
+ //
+ for(uIdx = 0; uIdx < ulCount; uIdx++)
+ {
+ //
+ // Write a word to the non-volatile storage area.
+ //
+ HWREG(HIB_DATA + (uIdx * 4)) = pulData[uIdx];
+
+ //
+ // Add a delay between writes to the data area.
+ //
+ if(CLASS_IS_FURY)
+ {
+ //
+ // Delay a fixed time on Fury-class devices
+ //
+ SysCtlDelay(g_ulWriteDelay);
+ }
+ else
+ {
+ //
+ // Wait for write complete to be signaled on later devices.
+ //
+ HibernateWriteComplete();
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Reads a set of data from the non-volatile memory of the Hibernation module.
+//!
+//! \param pulData points to a location where the data that is read from the
+//! Hibernation module will be stored.
+//! \param ulCount is the count of 32-bit words to read.
+//!
+//! Retrieves a set of data from the Hibernation module non-volatile memory
+//! that was previously stored with the HibernateDataSet() function. The
+//! caller must ensure that \e pulData points to a large enough memory block to
+//! hold all the data that is read from the non-volatile memory.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateDataGet(unsigned long *pulData, unsigned long ulCount)
+{
+ unsigned int uIdx;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulCount <= 64);
+ ASSERT(pulData != 0);
+
+ //
+ // Loop through all the words to be restored, reading one at a time.
+ //
+ for(uIdx = 0; uIdx < ulCount; uIdx++)
+ {
+ //
+ // Read a word from the non-volatile storage area. No delay is
+ // required between reads.
+ //
+ pulData[uIdx] = HWREG(HIB_DATA + (uIdx * 4));
+ }
+}
+
+//*****************************************************************************
+//
+//! Requests hibernation mode.
+//!
+//! This function requests the Hibernation module to disable the external
+//! regulator, thus removing power from the processor and all peripherals. The
+//! Hibernation module will remain powered from the battery or auxiliary power
+//! supply.
+//!
+//! The Hibernation module will re-enable the external regulator when one of
+//! the configured wake conditions occurs (such as RTC match or external
+//! \b WAKE pin). When the power is restored the processor will go through a
+//! normal power-on reset. The processor can retrieve saved state information
+//! with the HibernateDataGet() function. Prior to calling the function to
+//! request hibernation mode, the conditions for waking must have already been
+//! set by using the HibernateWakeSet() function.
+//!
+//! Note that this function may return because some time may elapse before the
+//! power is actually removed, or it may not be removed at all. For this
+//! reason, the processor will continue to execute instructions for some time
+//! and the caller should be prepared for this function to return. There are
+//! various reasons why the power may not be removed. For example, if the
+//! HibernateLowBatSet() function was used to configure an abort if low
+//! battery is detected, then the power will not be removed if the battery
+//! voltage is too low. There may be other reasons, related to the external
+//! circuit design, that a request for hibernation may not actually occur.
+//!
+//! For all these reasons, the caller must be prepared for this function to
+//! return. The simplest way to handle it is to just enter an infinite loop
+//! and wait for the power to be removed.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateRequest(void)
+{
+ //
+ // Set the bit in the control register to cut main power to the processor.
+ //
+ HWREG(HIB_CTL) |= HIB_CTL_HIBREQ;
+}
+
+//*****************************************************************************
+//
+//! Enables interrupts for the Hibernation module.
+//!
+//! \param ulIntFlags is the bit mask of the interrupts to be enabled.
+//!
+//! Enables the specified interrupt sources from the Hibernation module.
+//!
+//! The \e ulIntFlags parameter must be the logical OR of any combination of
+//! the following:
+//!
+//! - \b HIBERNATE_INT_PIN_WAKE - wake from pin interrupt
+//! - \b HIBERNATE_INT_LOW_BAT - low battery interrupt
+//! - \b HIBERNATE_INT_RTC_MATCH_0 - RTC match 0 interrupt
+//! - \b HIBERNATE_INT_RTC_MATCH_1 - RTC match 1 interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntEnable(unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
+ HIBERNATE_INT_RTC_MATCH_0 |
+ HIBERNATE_INT_RTC_MATCH_1)));
+
+ //
+ // Set the specified interrupt mask bits.
+ //
+ HWREG(HIB_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts for the Hibernation module.
+//!
+//! \param ulIntFlags is the bit mask of the interrupts to be disabled.
+//!
+//! Disables the specified interrupt sources from the Hibernation module.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to the HibernateIntEnable() function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntDisable(unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
+ HIBERNATE_INT_RTC_MATCH_0 |
+ HIBERNATE_INT_RTC_MATCH_1)));
+
+ //
+ // Clear the specified interrupt mask bits.
+ //
+ HWREG(HIB_IM) &= ~ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the Hibernation module interrupt.
+//!
+//! \param pfnHandler points to the function to be called when a hibernation
+//! interrupt occurs.
+//!
+//! Registers the interrupt handler in the system interrupt controller. The
+//! interrupt is enabled at the global level, but individual interrupt sources
+//! must still be enabled with a call to HibernateIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_HIBERNATE, pfnHandler);
+
+ //
+ // Enable the hibernate module interrupt.
+ //
+ IntEnable(INT_HIBERNATE);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the Hibernation module interrupt.
+//!
+//! Unregisters the interrupt handler in the system interrupt controller. The
+//! interrupt is disabled at the global level, and the interrupt handler will
+//! no longer be called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntUnregister(void)
+{
+ //
+ // Disable the hibernate interrupt.
+ //
+ IntDisable(INT_HIBERNATE);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_HIBERNATE);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status of the Hibernation module.
+//!
+//! \param bMasked is false to retrieve the raw interrupt status, and true to
+//! retrieve the masked interrupt status.
+//!
+//! Returns the interrupt status of the Hibernation module. The caller can use
+//! this to determine the cause of a hibernation interrupt. Either the masked
+//! or raw interrupt status can be returned.
+//!
+//! \return Returns the interrupt status as a bit field with the values as
+//! described in the HibernateIntEnable() function.
+//
+//*****************************************************************************
+unsigned long
+HibernateIntStatus(tBoolean bMasked)
+{
+ //
+ // Read and return the Hibernation module raw or masked interrupt status.
+ //
+ if(bMasked == true)
+ {
+ return(HWREG(HIB_MIS) & 0xf);
+ }
+ else
+ {
+ return(HWREG(HIB_RIS) & 0xf);
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears pending interrupts from the Hibernation module.
+//!
+//! \param ulIntFlags is the bit mask of the interrupts to be cleared.
+//!
+//! Clears the specified interrupt sources. This must be done from within the
+//! interrupt handler or else the handler will be called again upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to the HibernateIntEnable() function.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+HibernateIntClear(unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulIntFlags & ~(HIBERNATE_INT_PIN_WAKE | HIBERNATE_INT_LOW_BAT |
+ HIBERNATE_INT_RTC_MATCH_0 |
+ HIBERNATE_INT_RTC_MATCH_1)));
+
+ //
+ // Write the specified interrupt bits into the interrupt clear register.
+ //
+ HWREG(HIB_IC) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Checks to see if the Hibernation module is already powered up.
+//!
+//! This function queries the control register to determine if the module is
+//! already active. This function can be called at a power-on reset to help
+//! determine if the reset is due to a wake from hibernation or a cold start.
+//! If the Hibernation module is already active, then it does not need to be
+//! re-enabled and its status can be queried immediately.
+//!
+//! The software application should also use the HibernateIntStatus() function
+//! to read the raw interrupt status to determine the cause of the wake. The
+//! HibernateDataGet() function can be used to restore state. These
+//! combinations of functions can be used by the software to determine if the
+//! processor is waking from hibernation and the appropriate action to take as
+//! a result.
+//!
+//! \return Returns \b true if the module is already active, and \b false if
+//! not.
+//
+//*****************************************************************************
+unsigned int
+HibernateIsActive(void)
+{
+ //
+ // Read the control register, and return true if the module is enabled.
+ //
+ return(HWREG(HIB_CTL) & HIB_CTL_CLK32EN ? 1 : 0);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/hibernate.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/hibernate.h
new file mode 100644
index 00000000..b5df6f2b
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/hibernate.h
@@ -0,0 +1,127 @@
+//*****************************************************************************
+//
+// hibernate.h - API definition for the Hibernation module.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __HIBERNATE_H__
+#define __HIBERNATE_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Macros needed for selecting the clock source for HibernateClockSelect()
+//
+//*****************************************************************************
+#define HIBERNATE_CLOCK_SEL_RAW 0x04
+#define HIBERNATE_CLOCK_SEL_DIV128 0x00
+
+//*****************************************************************************
+//
+// Macros need to configure wake events for HibernateWakeSet()
+//
+//*****************************************************************************
+#define HIBERNATE_WAKE_PIN 0x10
+#define HIBERNATE_WAKE_RTC 0x08
+
+//*****************************************************************************
+//
+// Macros needed to configure low battery detect for HibernateLowBatSet()
+//
+//*****************************************************************************
+#define HIBERNATE_LOW_BAT_DETECT 0x20
+#define HIBERNATE_LOW_BAT_ABORT 0xA0
+
+//*****************************************************************************
+//
+// Macros defining interrupt source bits for the interrupt functions.
+//
+//*****************************************************************************
+#define HIBERNATE_INT_PIN_WAKE 0x08
+#define HIBERNATE_INT_LOW_BAT 0x04
+#define HIBERNATE_INT_RTC_MATCH_0 0x01
+#define HIBERNATE_INT_RTC_MATCH_1 0x02
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void HibernateEnableExpClk(unsigned long ulHibClk);
+extern void HibernateDisable(void);
+extern void HibernateClockSelect(unsigned long ulClockInput);
+extern void HibernateRTCEnable(void);
+extern void HibernateRTCDisable(void);
+extern void HibernateWakeSet(unsigned long ulWakeFlags);
+extern unsigned long HibernateWakeGet(void);
+extern void HibernateLowBatSet(unsigned long ulLowBatFlags);
+extern unsigned long HibernateLowBatGet(void);
+extern void HibernateRTCSet(unsigned long ulRTCValue);
+extern unsigned long HibernateRTCGet(void);
+extern void HibernateRTCMatch0Set(unsigned long ulMatch);
+extern unsigned long HibernateRTCMatch0Get(void);
+extern void HibernateRTCMatch1Set(unsigned long ulMatch);
+extern unsigned long HibernateRTCMatch1Get(void);
+extern void HibernateRTCTrimSet(unsigned long ulTrim);
+extern unsigned long HibernateRTCTrimGet(void);
+extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);
+extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);
+extern void HibernateRequest(void);
+extern void HibernateIntEnable(unsigned long ulIntFlags);
+extern void HibernateIntDisable(unsigned long ulIntFlags);
+extern void HibernateIntRegister(void (*pfnHandler)(void));
+extern void HibernateIntUnregister(void);
+extern unsigned long HibernateIntStatus(tBoolean bMasked);
+extern void HibernateIntClear(unsigned long ulIntFlags);
+extern unsigned int HibernateIsActive(void);
+
+//*****************************************************************************
+//
+// Several Hibernate module APIs have been renamed, with the original function
+// name being deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "driverlib/sysctl.h"
+#define HibernateEnable(a) \
+ HibernateEnableExpClk(a, SysCtlClockGet())
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HIBERNATE_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/i2c.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/i2c.c
new file mode 100644
index 00000000..ed9ef655
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/i2c.c
@@ -0,0 +1,1106 @@
+//*****************************************************************************
+//
+// i2c.c - Driver for Inter-IC (I2C) bus block.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup i2c_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_i2c.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/i2c.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Initializes the I2C Master block.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//! \param ulI2CClk is the rate of the clock supplied to the I2C module.
+//! \param bFast set up for fast data transfers
+//!
+//! This function initializes operation of the I2C Master block. Upon
+//! successful initialization of the I2C block, this function will have set the
+//! bus speed for the master, and will have enabled the I2C Master block.
+//!
+//! If the parameter \e bFast is \b true, then the master block will be set up
+//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data
+//! at 100 kbps.
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original I2CMasterInit() API and performs the
+//! same actions. A macro is provided in i2c.h to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
+ tBoolean bFast)
+{
+ unsigned long ulSCLFreq;
+ unsigned long ulTPR;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Must enable the device before doing anything else.
+ //
+ I2CMasterEnable(ulBase);
+
+ //
+ // Get the desired SCL speed.
+ //
+ if(bFast == true)
+ {
+ ulSCLFreq = 400000;
+ }
+ else
+ {
+ ulSCLFreq = 100000;
+ }
+
+ //
+ // Compute the clock divider that achieves the fastest speed less than or
+ // equal to the desired speed. The numerator is biased to favor a larger
+ // clock divider so that the resulting clock is always less than or equal
+ // to the desired clock, never greater.
+ //
+ ulTPR = ((ulI2CClk + (2 * 10 * ulSCLFreq) - 1) / (2 * 10 * ulSCLFreq)) - 1;
+ HWREG(ulBase + I2C_O_MTPR) = ulTPR;
+}
+
+//*****************************************************************************
+//
+//! Initializes the I2C Slave block.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param ucSlaveAddr 7-bit slave address
+//!
+//! This function initializes operation of the I2C Slave block. Upon
+//! successful initialization of the I2C blocks, this function will have set
+//! the slave address and have enabled the I2C Slave block.
+//!
+//! The parameter \e ucSlaveAddr is the value that will be compared against the
+//! slave address sent by an I2C master.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+ ASSERT(!(ucSlaveAddr & 0x80));
+
+ //
+ // Must enable the device before doing anything else.
+ //
+ I2CSlaveEnable(ulBase);
+
+ //
+ // Set up the slave address.
+ //
+ HWREG(ulBase + I2C_O_SOAR) = ucSlaveAddr;
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Master block.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This will enable operation of the I2C Master block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Enable the master block.
+ //
+ HWREG(ulBase + I2C_O_MCR) |= I2C_MCR_MFE;
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Slave block.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! This will enable operation of the I2C Slave block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Enable the clock to the slave block.
+ //
+ HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) |=
+ I2C_MCR_SFE;
+
+ //
+ // Enable the slave.
+ //
+ HWREG(ulBase + I2C_O_SCSR) = I2C_SCSR_DA;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C master block.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This will disable operation of the I2C master block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Disable the master block.
+ //
+ HWREG(ulBase + I2C_O_MCR) &= ~(I2C_MCR_MFE);
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C slave block.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! This will disable operation of the I2C slave block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Disable the slave.
+ //
+ HWREG(ulBase + I2C_O_SCSR) = 0;
+
+ //
+ // Disable the clock to the slave block.
+ //
+ HWREG(ulBase - I2C0_SLAVE_BASE + I2C0_MASTER_BASE + I2C_O_MCR) &=
+ ~(I2C_MCR_SFE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the I2C module.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! I2C interrupt occurs.
+//!
+//! This sets the handler to be called when an I2C interrupt occurs. This will
+//! enable the global interrupt in the interrupt controller; specific I2C
+//! interrupts must be enabled via I2CMasterIntEnable() and
+//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's
+//! responsibility to clear the interrupt source via I2CMasterIntClear() and
+//! I2CSlaveIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Determine the interrupt number based on the I2C port.
+ //
+ ulInt = (ulBase == I2C0_MASTER_BASE) ? INT_I2C0 : INT_I2C1;
+
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the I2C interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the I2C module.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This function will clear the handler to be called when an I2C interrupt
+//! occurs. This will also mask off the interrupt in the interrupt controller
+//! so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Determine the interrupt number based on the I2C port.
+ //
+ ulInt = (ulBase == I2C0_MASTER_BASE) ? INT_I2C0 : INT_I2C1;
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Master interrupt.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! Enables the I2C Master interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Enable the master interrupt.
+ //
+ HWREG(ulBase + I2C_O_MIMR) = 1;
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Slave interrupt.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! Enables the I2C Slave interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Enable the slave interrupt.
+ //
+ HWREG(ulBase + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA;
+}
+
+//*****************************************************************************
+//
+//! Enables individual I2C Slave interrupt sources.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated I2C Slave interrupt sources. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt
+//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt
+//! - \b I2C_SLAVE_INT_DATA - Data interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Enable the slave interrupt.
+ //
+ HWREG(ulBase + I2C_O_SIMR) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C Master interrupt.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! Disables the I2C Master interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Disable the master interrupt.
+ //
+ HWREG(ulBase + I2C_O_MIMR) = 0;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C Slave interrupt.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! Disables the I2C Slave interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Disable the slave interrupt.
+ //
+ HWREG(ulBase + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA;
+}
+
+//*****************************************************************************
+//
+//! Disables individual I2C Slave interrupt sources.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated I2C Slave interrupt sources. Only the sources that
+//! are enabled can be reflected to the processor interrupt; disabled sources
+//! have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to I2CSlaveIntEnableEx().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntDisableEx(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Disable the slave interrupt.
+ //
+ HWREG(ulBase + I2C_O_SIMR) &= ~ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Master interrupt status.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This returns the interrupt status for the I2C Master module. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, returned as \b true if active
+//! or \b false if not active.
+//
+//*****************************************************************************
+tBoolean
+I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return((HWREG(ulBase + I2C_O_MMIS)) ? true : false);
+ }
+ else
+ {
+ return((HWREG(ulBase + I2C_O_MRIS)) ? true : false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Slave interrupt status.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This returns the interrupt status for the I2C Slave module. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return The current interrupt status, returned as \b true if active
+//! or \b false if not active.
+//
+//*****************************************************************************
+tBoolean
+I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return((HWREG(ulBase + I2C_O_SMIS)) ? true : false);
+ }
+ else
+ {
+ return((HWREG(ulBase + I2C_O_SRIS)) ? true : false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Slave interrupt status.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This returns the interrupt status for the I2C Slave module. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in I2CSlaveIntEnableEx().
+//
+//*****************************************************************************
+unsigned long
+I2CSlaveIntStatusEx(unsigned long ulBase, tBoolean bMasked)
+{
+ unsigned long ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ //
+ // Workaround for I2C slave masked interrupt status register errata
+ // (7.1) for Dustdevil Rev A0 devices.
+ //
+ if(CLASS_IS_DUSTDEVIL && REVISION_IS_A0)
+ {
+ ulValue = HWREG(ulBase + I2C_O_SRIS);
+ return(ulValue & HWREG(ulBase + I2C_O_SIMR));
+ }
+ else
+ {
+ return(HWREG(ulBase + I2C_O_SMIS));
+ }
+ }
+ else
+ {
+ return(HWREG(ulBase + I2C_O_SRIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Master interrupt sources.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! The I2C Master interrupt source is cleared, so that it no longer asserts.
+//! This must be done in the interrupt handler to keep it from being called
+//! again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Clear the I2C master interrupt source.
+ //
+ HWREG(ulBase + I2C_O_MICR) = I2C_MICR_IC;
+
+ //
+ // Workaround for I2C master interrupt clear errata for rev B Stellaris
+ // devices. For later devices, this write is ignored and therefore
+ // harmless (other than the slight performance hit).
+ //
+ HWREG(ulBase + I2C_O_MMIS) = I2C_MICR_IC;
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Slave interrupt sources.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! The I2C Slave interrupt source is cleared, so that it no longer asserts.
+//! This must be done in the interrupt handler to keep it from being called
+//! again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Clear the I2C slave interrupt source.
+ //
+ HWREG(ulBase + I2C_O_SICR) = I2C_SICR_DATAIC;
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Slave interrupt sources.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified I2C Slave interrupt sources are cleared, so that they no
+//! longer assert. This must be done in the interrupt handler to keep it from
+//! being called again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to I2CSlaveIntEnableEx().
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Clear the I2C slave interrupt source.
+ //
+ HWREG(ulBase + I2C_O_SICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Sets the address that the I2C Master will place on the bus.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//! \param ucSlaveAddr 7-bit slave address
+//! \param bReceive flag indicating the type of communication with the slave
+//!
+//! This function will set the address that the I2C Master will place on the
+//! bus when initiating a transaction. When the \e bReceive parameter is set
+//! to \b true, the address will indicate that the I2C Master is initiating a
+//! read from the slave; otherwise the address will indicate that the I2C
+//! Master is initiating a write to the slave.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterSlaveAddrSet(unsigned long ulBase, unsigned char ucSlaveAddr,
+ tBoolean bReceive)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+ ASSERT(!(ucSlaveAddr & 0x80));
+
+ //
+ // Set the address of the slave with which the master will communicate.
+ //
+ HWREG(ulBase + I2C_O_MSA) = (ucSlaveAddr << 1) | bReceive;
+}
+
+//*****************************************************************************
+//
+//! Indicates whether or not the I2C Master is busy.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This function returns an indication of whether or not the I2C Master is
+//! busy transmitting or receiving data.
+//!
+//! \return Returns \b true if the I2C Master is busy; otherwise, returns
+//! \b false.
+//
+//*****************************************************************************
+tBoolean
+I2CMasterBusy(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Return the busy status.
+ //
+ if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSY)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Indicates whether or not the I2C bus is busy.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This function returns an indication of whether or not the I2C bus is busy.
+//! This function can be used in a multi-master environment to determine if
+//! another master is currently using the bus.
+//!
+//! \return Returns \b true if the I2C bus is busy; otherwise, returns
+//! \b false.
+//
+//*****************************************************************************
+tBoolean
+I2CMasterBusBusy(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Return the bus busy status.
+ //
+ if(HWREG(ulBase + I2C_O_MCS) & I2C_MCS_BUSBSY)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Controls the state of the I2C Master module.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//! \param ulCmd command to be issued to the I2C Master module
+//!
+//! This function is used to control the state of the Master module send and
+//! receive operations. The \e ucCmd parameter can be one of the following
+//! values:
+//!
+//! - \b I2C_MASTER_CMD_SINGLE_SEND
+//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE
+//! - \b I2C_MASTER_CMD_BURST_SEND_START
+//! - \b I2C_MASTER_CMD_BURST_SEND_CONT
+//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH
+//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterControl(unsigned long ulBase, unsigned long ulCmd)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+ ASSERT((ulCmd == I2C_MASTER_CMD_SINGLE_SEND) ||
+ (ulCmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_SEND_START) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
+ (ulCmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP));
+
+ //
+ // Send the command.
+ //
+ HWREG(ulBase + I2C_O_MCS) = ulCmd;
+}
+
+//*****************************************************************************
+//
+//! Gets the error status of the I2C Master module.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This function is used to obtain the error status of the Master module send
+//! and receive operations.
+//!
+//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE,
+//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or
+//! \b I2C_MASTER_ERR_ARB_LOST.
+//
+//*****************************************************************************
+unsigned long
+I2CMasterErr(unsigned long ulBase)
+{
+ unsigned long ulErr;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Get the raw error state
+ //
+ ulErr = HWREG(ulBase + I2C_O_MCS);
+
+ //
+ // If the I2C master is busy, then all the other bit are invalid, and
+ // don't have an error to report.
+ //
+ if(ulErr & I2C_MCS_BUSY)
+ {
+ return(I2C_MASTER_ERR_NONE);
+ }
+
+ //
+ // Check for errors.
+ //
+ if(ulErr & (I2C_MCS_ERROR | I2C_MCS_ARBLST))
+ {
+ return(ulErr & (I2C_MCS_ARBLST | I2C_MCS_DATACK | I2C_MCS_ADRACK));
+ }
+ else
+ {
+ return(I2C_MASTER_ERR_NONE);
+ }
+}
+
+//*****************************************************************************
+//
+//! Transmits a byte from the I2C Master.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//! \param ucData data to be transmitted from the I2C Master
+//!
+//! This function will place the supplied data into I2C Master Data Register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterDataPut(unsigned long ulBase, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Write the byte.
+ //
+ HWREG(ulBase + I2C_O_MDR) = ucData;
+}
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the I2C Master.
+//!
+//! \param ulBase is the base address of the I2C Master module.
+//!
+//! This function reads a byte of data from the I2C Master Data Register.
+//!
+//! \return Returns the byte received from by the I2C Master, cast as an
+//! unsigned long.
+//
+//*****************************************************************************
+unsigned long
+I2CMasterDataGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE));
+
+ //
+ // Read a byte.
+ //
+ return(HWREG(ulBase + I2C_O_MDR));
+}
+
+//*****************************************************************************
+//
+//! Gets the I2C Slave module status
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! This function will return the action requested from a master, if any.
+//! Possible values are:
+//!
+//! - \b I2C_SLAVE_ACT_NONE
+//! - \b I2C_SLAVE_ACT_RREQ
+//! - \b I2C_SLAVE_ACT_TREQ
+//! - \b I2C_SLAVE_ACT_RREQ_FBR
+//!
+//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been
+//! requested of the I2C Slave module, \b I2C_SLAVE_ACT_RREQ to indicate that
+//! an I2C master has sent data to the I2C Slave module, \b I2C_SLAVE_ACT_TREQ
+//! to indicate that an I2C master has requested that the I2C Slave module send
+//! data, and \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent
+//! data to the I2C slave and the first byte following the slave's own address
+//! has been received.
+//
+//*****************************************************************************
+unsigned long
+I2CSlaveStatus(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Return the slave status.
+ //
+ return(HWREG(ulBase + I2C_O_SCSR));
+}
+
+//*****************************************************************************
+//
+//! Transmits a byte from the I2C Slave.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//! \param ucData data to be transmitted from the I2C Slave
+//!
+//! This function will place the supplied data into I2C Slave Data Register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Write the byte.
+ //
+ HWREG(ulBase + I2C_O_SDR) = ucData;
+}
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the I2C Slave.
+//!
+//! \param ulBase is the base address of the I2C Slave module.
+//!
+//! This function reads a byte of data from the I2C Slave Data Register.
+//!
+//! \return Returns the byte received from by the I2C Slave, cast as an
+//! unsigned long.
+//
+//*****************************************************************************
+unsigned long
+I2CSlaveDataGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE));
+
+ //
+ // Read a byte.
+ //
+ return(HWREG(ulBase + I2C_O_SDR));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/i2c.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/i2c.h
new file mode 100644
index 00000000..d277dce3
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/i2c.h
@@ -0,0 +1,179 @@
+//*****************************************************************************
+//
+// i2c.h - Prototypes for the I2C Driver.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Defines for the API.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Interrupt defines.
+//
+//*****************************************************************************
+#define I2C_INT_MASTER 0x00000001
+#define I2C_INT_SLAVE 0x00000002
+
+//*****************************************************************************
+//
+// I2C Master commands.
+//
+//*****************************************************************************
+#define I2C_MASTER_CMD_SINGLE_SEND \
+ 0x00000007
+#define I2C_MASTER_CMD_SINGLE_RECEIVE \
+ 0x00000007
+#define I2C_MASTER_CMD_BURST_SEND_START \
+ 0x00000003
+#define I2C_MASTER_CMD_BURST_SEND_CONT \
+ 0x00000001
+#define I2C_MASTER_CMD_BURST_SEND_FINISH \
+ 0x00000005
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
+ 0x00000004
+#define I2C_MASTER_CMD_BURST_RECEIVE_START \
+ 0x0000000b
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
+ 0x00000009
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
+ 0x00000005
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
+ 0x00000004
+
+//*****************************************************************************
+//
+// I2C Master error status.
+//
+//*****************************************************************************
+#define I2C_MASTER_ERR_NONE 0
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010
+
+//*****************************************************************************
+//
+// I2C Slave action requests
+//
+//*****************************************************************************
+#define I2C_SLAVE_ACT_NONE 0
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
+#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
+
+//*****************************************************************************
+//
+// Miscellaneous I2C driver definitions.
+//
+//*****************************************************************************
+#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
+
+
+//*****************************************************************************
+//
+// I2C Slave interrupts.
+//
+//*****************************************************************************
+#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt.
+#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt.
+#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt.
+
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
+extern void I2CIntUnregister(unsigned long ulBase);
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
+extern tBoolean I2CMasterBusy(unsigned long ulBase);
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
+extern void I2CMasterDisable(unsigned long ulBase);
+extern void I2CMasterEnable(unsigned long ulBase);
+extern unsigned long I2CMasterErr(unsigned long ulBase);
+extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
+ tBoolean bFast);
+extern void I2CMasterIntClear(unsigned long ulBase);
+extern void I2CMasterIntDisable(unsigned long ulBase);
+extern void I2CMasterIntEnable(unsigned long ulBase);
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
+ unsigned char ucSlaveAddr,
+ tBoolean bReceive);
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
+extern void I2CSlaveDisable(unsigned long ulBase);
+extern void I2CSlaveEnable(unsigned long ulBase);
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
+extern void I2CSlaveIntClear(unsigned long ulBase);
+extern void I2CSlaveIntDisable(unsigned long ulBase);
+extern void I2CSlaveIntEnable(unsigned long ulBase);
+extern void I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags);
+extern void I2CSlaveIntDisableEx(unsigned long ulBase,
+ unsigned long ulIntFlags);
+extern void I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags);
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern unsigned long I2CSlaveIntStatusEx(unsigned long ulBase,
+ tBoolean bMasked);
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several I2C APIs have been renamed, with the original function name being
+// deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "driverlib/sysctl.h"
+#define I2CMasterInit(a, b) \
+ I2CMasterInitExpClk(a, SysCtlClockGet(), b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __I2C_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/i2s.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/i2s.c
new file mode 100644
index 00000000..42749354
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/i2s.c
@@ -0,0 +1,1136 @@
+//*****************************************************************************
+//
+// i2s.c - Driver for the I2S controller.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup i2s_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_i2s.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/i2s.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+//! Enables the I2S transmit module for operation.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function enables the transmit module for operation. The module
+//! should be enabled after configuration. When the module is disabled,
+//! no data or clocks will be generated on the I2S signals.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Enable the tx FIFO service request.
+ //
+ HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM;
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2S transmit module for operation.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function disables the transmit module for operation. The module
+//! should be disabled before configuration. When the module is disabled,
+//! no data or clocks will be generated on the I2S signals.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_TXEN;
+}
+
+//*****************************************************************************
+//
+//! Writes data samples to the I2S transmit FIFO with blocking.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulData is the single or dual channel I2S data.
+//!
+//! This function writes a single channel sample or combined left-right
+//! samples to the I2S transmit FIFO. The format of the sample is determined
+//! by the configuration that was used with the function I2STxConfigSet().
+//! If the transmit mode is I2S_MODE_DUAL_STEREO then the \e ulData parameter
+//! contains either the left or right sample. The left and right sample
+//! alternate with each write to the FIFO, left sample first. If the transmit
+//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
+//! \e ulData parameter contains both the left and right samples. If the
+//! transmit mode is I2S_MODE_SINGLE_MONO then the \e ulData parameter
+//! contains the single channel sample.
+//!
+//! For the compact modes, both the left and right samples are written at
+//! the same time. If 16-bit compact mode is used, then the least significant
+//! 16 bits contain the left sample, and the most significant 16 bits contain
+//! the right sample. If 8-bit compact mode is used, then the lower 8 bits
+//! contain the left sample, and the next 8 bits contain the right sample,
+//! with the upper 16 bits unused.
+//!
+//! If there is no room in the transmit FIFO, then this function will wait
+//! in a polling loop until the data can be written.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxDataPut(unsigned long ulBase, unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Wait until there is space.
+ //
+ while(HWREG(ulBase + I2S_O_TXLEV) >= 16)
+ {
+ }
+
+ //
+ // Write the data to the I2S.
+ //
+ HWREG(ulBase + I2S_O_TXFIFO) = ulData;
+}
+
+//*****************************************************************************
+//
+//! Writes data samples to the I2S transmit FIFO without blocking.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulData is the single or dual channel I2S data.
+//!
+//! This function writes a single channel sample or combined left-right
+//! samples to the I2S transmit FIFO. The format of the sample is determined
+//! by the configuration that was used with the function I2STxConfigSet().
+//! If the transmit mode is I2S_MODE_DUAL_STEREO then the \e ulData parameter
+//! contains either the left or right sample. The left and right sample
+//! alternate with each write to the FIFO, left sample first. If the transmit
+//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
+//! \e ulData parameter contains both the left and right samples. If the
+//! transmit mode is I2S_MODE_SINGLE_MONO then the \e ulData parameter
+//! contains the single channel sample.
+//!
+//! For the compact modes, both the left and right samples are written at
+//! the same time. If 16-bit compact mode is used, then the least significant
+//! 16 bits contain the left sample, and the most significant 16 bits contain
+//! the right sample. If 8-bit compact mode is used, then the lower 8 bits
+//! contain the left sample, and the next 8 bits contain the right sample,
+//! with the upper 16 bits unused.
+//!
+//! If there is no room in the transmit FIFO, then this function will return
+//! immediately without writing any data to the FIFO.
+//!
+//! \return The number of elements written to the I2S transmit FIFO (1 or 0).
+//
+//*****************************************************************************
+long
+I2STxDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Check for space to write.
+ //
+ if(HWREG(ulBase + I2S_O_TXLEV) < 16)
+ {
+ HWREG(ulBase + I2S_O_TXFIFO) = ulData;
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the I2S transmit module.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulConfig is the logical OR of the configuration options.
+//!
+//! This function is used to configure the options for the I2S transmit
+//! channel. The parameter \e ulConfig is the logical OR of the following
+//! options:
+//!
+//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format,
+//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
+//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
+//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock.
+//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo,
+//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
+//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
+//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
+//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether
+//! the I2S transmitter is the clock master or slave.
+//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
+//! to select the number of bits per sample.
+//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
+//! to select the number of bits per word that are transferred on the data
+//! line.
+//! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether
+//! the module transmits zeroes or repeats the last sample when the FIFO is
+//! empty.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK |
+ I2S_CONFIG_EMPTY_MASK | I2S_CONFIG_CLK_MASK |
+ I2S_CONFIG_SAMPLE_SIZE_MASK |
+ I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig);
+
+ //
+ // Check to see if a compact mode is used.
+ //
+ if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8)
+ {
+ //
+ // If compact 8 mode is used, then need to adjust some bits
+ // before writing the config register. Also set the FIFO
+ // config register for 8 bit compact samples.
+ //
+ ulConfig &= ~I2S_CONFIG_MODE_MONO;
+ HWREG(ulBase + I2S_O_TXFIFOCFG) = I2S_TXFIFOCFG_CSS;
+ }
+ else
+ {
+ //
+ // If compact 8 mode is not used, then set the FIFO config
+ // register for 16 bit. This is okay if a compact mode is
+ // not used.
+ //
+ HWREG(ulBase + I2S_O_TXFIFOCFG) = 0;
+ }
+
+ //
+ // Write the configuration register. Since all the fields are
+ // specified by the configuration parameter, it is not necessary
+ // to do a read-modify-write.
+ //
+ HWREG(ulBase + I2S_O_TXCFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO level at which a service request is generated.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulLevel is the FIFO service request limit.
+//!
+//! This function is used to set the transmit FIFO fullness level at which
+//! a service request will occur. The service request is used to generate
+//! an interrupt or a DMA transfer request. The transmit FIFO will
+//! generate a service request when the number of items in the FIFO is
+//! less than the level specified in the \e ulLevel parameter. For example,
+//! if \e ulLevel is 8, then a service request will be generated when
+//! there are less than 8 samples remaining in the transmit FIFO.
+//!
+//! For the purposes of counting the FIFO level, a left-right sample pair
+//! counts as 2, whether the mode is dual or compact stereo. When mono
+//! mode is used, internally the mono sample is still treated as a sample
+//! pair, so a single mono sample counts as 2. Since the FIFO always deals
+//! with sample pairs, the level must be an even number from 0 to 16. The
+//! maximum value is 16, which will cause a service request when there
+//! is any room in the FIFO. The minimum value is 0, which disables the
+//! service request.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT(ulLevel <= 16);
+
+ //
+ // Write the FIFO limit
+ //
+ HWREG(ulBase + I2S_O_TXLIMIT) = ulLevel;
+}
+
+//*****************************************************************************
+//
+//! Gets the current setting of the FIFO service request level.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function is used to get the value of the transmit FIFO service
+//! request level. This value is set using the I2STxFIFOLimitSet()
+//! function.
+//!
+//! \return Returns the current value of the FIFO service request limit.
+//
+//*****************************************************************************
+unsigned long
+I2STxFIFOLimitGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Read and return the FIFO limit
+ //
+ return(HWREG(ulBase + I2S_O_TXLIMIT));
+}
+
+//*****************************************************************************
+//
+//! Gets the number of samples in the transmit FIFO.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function is used to get the number of samples in the transmit
+//! FIFO. For the purposes of measuring the FIFO level, a left-right sample
+//! pair counts as 2, whether the mode is dual or compact stereo. When mono
+//! mode is used, internally the mono sample is still treated as a sample
+//! pair, so a single mono sample counts as 2. Since the FIFO always deals
+//! with sample pairs, normally the level will be an even number from 0 to
+//! 16. If dual stereo mode is used and only the left sample has been
+//! written without the matching right sample, then the FIFO level will be an
+//! odd value. If the FIFO level is odd, it indicates a left-right sample
+//! mismatch.
+//!
+//! \return Returns the number of samples in the transmit FIFO, which will
+//! normally be an even number.
+//
+//*****************************************************************************
+unsigned long
+I2STxFIFOLevelGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Read and return the transmit FIFO level.
+ //
+ return(HWREG(ulBase + I2S_O_TXLEV));
+}
+
+//*****************************************************************************
+//
+//! Enables the I2S receive module for operation.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function enables the receive module for operation. The module
+//! should be enabled after configuration. When the module is disabled,
+//! no data will be clocked in regardless of the signals on the I2S interface.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SRxEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Enable the tx FIFO service request.
+ //
+ HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM;
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_RXEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2S receive module for operation.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function disables the receive module for operation. The module
+//! should be disabled before configuration. When the module is disabled,
+//! no data will be clocked in regardless of the signals on the I2S interface.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SRxDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + I2S_O_CFG) &= ~I2S_CFG_RXEN;
+}
+
+//*****************************************************************************
+//
+//! Reads data samples from the I2S receive FIFO with blocking.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param pulData points to storage for the returned I2S sample data.
+//!
+//! This function reads a single channel sample or combined left-right
+//! samples from the I2S receive FIFO. The format of the sample is determined
+//! by the configuration that was used with the function I2SRxConfigSet().
+//! If the receive mode is I2S_MODE_DUAL_STEREO then the returned value
+//! contains either the left or right sample. The left and right sample
+//! alternate with each read from the FIFO, left sample first. If the receive
+//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
+//! returned data contains both the left and right samples. If the
+//! receive mode is I2S_MODE_SINGLE_MONO then the returned data
+//! contains the single channel sample.
+//!
+//! For the compact modes, both the left and right samples are read at
+//! the same time. If 16-bit compact mode is used, then the least significant
+//! 16 bits contain the left sample, and the most significant 16 bits contain
+//! the right sample. If 8-bit compact mode is used, then the lower 8 bits
+//! contain the left sample, and the next 8 bits contain the right sample,
+//! with the upper 16 bits unused.
+//!
+//! If there is no data in the receive FIFO, then this function will wait
+//! in a polling loop until data is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SRxDataGet(unsigned long ulBase, unsigned long *pulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Wait until there is data available.
+ //
+ while(HWREG(ulBase + I2S_O_RXLEV) == 0)
+ {
+ }
+
+ //
+ // Read data from the I2S receive FIFO.
+ //
+ *pulData = HWREG(ulBase + I2S_O_RXFIFO);
+}
+
+//*****************************************************************************
+//
+//! Reads data samples from the I2S receive FIFO without blocking.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param pulData points to storage for the returned I2S sample data.
+//!
+//! This function reads a single channel sample or combined left-right
+//! samples from the I2S receive FIFO. The format of the sample is determined
+//! by the configuration that was used with the function I2SRxConfigSet().
+//! If the receive mode is I2S_MODE_DUAL_STEREO then the received data
+//! contains either the left or right sample. The left and right sample
+//! alternate with each read from the FIFO, left sample first. If the receive
+//! mode is I2S_MODE_COMPACT_STEREO_16 or I2S_MODE_COMPACT_STEREO_8, then the
+//! received data contains both the left and right samples. If the
+//! receive mode is I2S_MODE_SINGLE_MONO then the received data
+//! contains the single channel sample.
+//!
+//! For the compact modes, both the left and right samples are read at
+//! the same time. If 16-bit compact mode is used, then the least significant
+//! 16 bits contain the left sample, and the most significant 16 bits contain
+//! the right sample. If 8-bit compact mode is used, then the lower 8 bits
+//! contain the left sample, and the next 8 bits contain the right sample,
+//! with the upper 16 bits unused.
+//!
+//! If there is no data in the receive FIFO, then this function will return
+//! immediately without reading any data from the FIFO.
+//!
+//! \return The number of elements read from the I2S receive FIFO (1 or 0).
+//
+//*****************************************************************************
+long
+I2SRxDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Check for available samples.
+ //
+ if(HWREG(ulBase + I2S_O_RXLEV) != 0)
+ {
+ *pulData = HWREG(ulBase + I2S_O_RXFIFO);
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the I2S receive module.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulConfig is the logical OR of the configuration options.
+//!
+//! This function is used to configure the options for the I2S receive
+//! channel. The parameter \e ulConfig is the logical OR of the following
+//! options:
+//!
+//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format,
+//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
+//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
+//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock.
+//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo,
+//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
+//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
+//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
+//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether
+//! the I2S receiver is the clock master or slave.
+//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
+//! to select the number of bits per sample.
+//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
+//! to select the number of bits per word that are transferred on the data
+//! line.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK |
+ I2S_CONFIG_CLK_MASK | I2S_CONFIG_SAMPLE_SIZE_MASK |
+ I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig);
+
+ //
+ // Clear out any prior config of the RX FIFO config register.
+ //
+ HWREG(ulBase + I2S_O_RXFIFOCFG) = 0;
+
+ //
+ // If mono mode is used, then the FMM bit needs to be set.
+ //
+ if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_MONO)
+ {
+ HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM;
+ }
+
+ //
+ // If a compact mode is used, then the CSS bit needs to be set.
+ //
+ else if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8)
+ {
+ HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS;
+ }
+
+ //
+ // The "mono" bits needs to be removed from the configuration word
+ // prior to writing to hardware, because the RX configuration register
+ // does not actually use these bits.
+ //
+ ulConfig &= ~I2S_CONFIG_MODE_MONO;
+
+ //
+ // Write the configuration register. Since all the fields are
+ // specified by the configuration parameter, it is not necessary
+ // to do a read-modify-write.
+ //
+ HWREG(ulBase + I2S_O_RXCFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO level at which a service request is generated.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulLevel is the FIFO service request limit.
+//!
+//! This function is used to set the receive FIFO fullness level at which
+//! a service request will occur. The service request is used to generate
+//! an interrupt or a DMA transfer request. The receive FIFO will
+//! generate a service request when the number of items in the FIFO is
+//! greater than the level specified in the \e ulLevel parameter. For example,
+//! if \e ulLevel is 4, then a service request will be generated when
+//! there are more than 4 samples available in the receive FIFO.
+//!
+//! For the purposes of counting the FIFO level, a left-right sample pair
+//! counts as 2, whether the mode is dual or compact stereo. When mono
+//! mode is used, internally the mono sample is still treated as a sample
+//! pair, so a single mono sample counts as 2. Since the FIFO always deals
+//! with sample pairs, the level must be an even number from 0 to 16. The
+//! minimum value is 0, which will cause a service request when there
+//! is any data available in the FIFO. The maximum value is 16, which
+//! disables the service request (because there cannot be more than 16
+//! items in the FIFO).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SRxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT(ulLevel <= 16);
+
+ //
+ // Write the FIFO limit
+ //
+ HWREG(ulBase + I2S_O_RXLIMIT) = ulLevel;
+}
+
+//*****************************************************************************
+//
+//! Gets the current setting of the FIFO service request level.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function is used to get the value of the receive FIFO service
+//! request level. This value is set using the I2SRxFIFOLimitSet()
+//! function.
+//!
+//! \return Returns the current value of the FIFO service request limit.
+//
+//*****************************************************************************
+unsigned long
+I2SRxFIFOLimitGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Read and return the FIFO limit. The lower bit is masked
+ // because it always reads as 1, and has no meaning.
+ //
+ return(HWREG(ulBase + I2S_O_RXLIMIT) & 0xFFFE);
+}
+
+//*****************************************************************************
+//
+//! Gets the number of samples in the receive FIFO.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function is used to get the number of samples in the receive
+//! FIFO. For the purposes of measuring the FIFO level, a left-right sample
+//! pair counts as 2, whether the mode is dual or compact stereo. When mono
+//! mode is used, internally the mono sample is still treated as a sample
+//! pair, so a single mono sample counts as 2. Since the FIFO always deals
+//! with sample pairs, normally the level will be an even number from 0 to
+//! 16. If dual stereo mode is used and only the left sample has been
+//! read without reading the matching right sample, then the FIFO level will
+//! be an odd value. If the FIFO level is odd, it indicates a left-right
+//! sample mismatch.
+//!
+//! \return Returns the number of samples in the transmit FIFO, which will
+//! normally be an even number.
+//
+//*****************************************************************************
+unsigned long
+I2SRxFIFOLevelGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Read and return the receive FIFO level.
+ //
+ return(HWREG(ulBase + I2S_O_RXLEV));
+}
+
+//*****************************************************************************
+//
+//! Enables the I2S transmit and receive modules for operation.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function simultaneously enables the transmit and receive modules for
+//! operation, providing a synchronized SCLK and LRCLK. The module should be
+//! enabled after configuration. When the module is disabled, no data or
+//! clocks will be generated on the I2S signals.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxRxEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Enable the Tx FIFO service request.
+ //
+ HWREG(ulBase + I2S_O_TXISM) = I2S_TXISM_FFM;
+
+ //
+ // Enable the Rx FIFO service request.
+ //
+ HWREG(ulBase + I2S_O_RXISM) = I2S_RXISM_FFM;
+
+ //
+ // Enable the transmit and receive modules.
+ //
+ HWREG(ulBase + I2S_O_CFG) |= I2S_CFG_TXEN | I2S_CFG_RXEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2S transmit and receive modules.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function simultaneously disables the transmit and receive modules.
+//! When the module is disabled, no data or clocks will be generated on the I2S
+//! signals.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxRxDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Disable the transmit and receive modules.
+ //
+ HWREG(ulBase + I2S_O_CFG) &= ~(I2S_CFG_TXEN | I2S_CFG_RXEN);
+}
+
+//*****************************************************************************
+//
+//! Configures the I2S transmit and receive modules.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulConfig is the logical OR of the configuration options.
+//!
+//! This function is used to configure the options for the I2S transmit and
+//! receive channels with identical parameters. The parameter \e ulConfig is
+//! the logical OR of the following options:
+//!
+//! - \b I2S_CONFIG_FORMAT_I2S for standard I2S format,
+//! \b I2S_CONFIG_FORMAT_LEFT_JUST for left justified format, or
+//! \b I2S_CONFIG_FORMAT_RIGHT_JUST for right justified format.
+//! - \b I2S_CONFIG_SCLK_INVERT to invert the polarity of the serial bit clock.
+//! - \b I2S_CONFIG_MODE_DUAL for dual channel stereo,
+//! \b I2S_CONFIG_MODE_COMPACT_16 for 16-bit compact stereo mode,
+//! \b I2S_CONFIG_MODE_COMPACT_8 for 8-bit compact stereo mode, or
+//! \b I2S_CONFIG_MODE_MONO for single channel mono format.
+//! - \b I2S_CONFIG_CLK_MASTER or \b I2S_CONFIG_CLK_SLAVE to select whether
+//! the I2S transmitter is the clock master or slave.
+//! - \b I2S_CONFIG_SAMPLE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
+//! to select the number of bits per sample.
+//! - \b I2S_CONFIG_WIRE_SIZE_32, \b _24, \b _20, \b _16, or \b _8
+//! to select the number of bits per word that are transferred on the data
+//! line.
+//! - \b I2S_CONFIG_EMPTY_ZERO or \b I2S_CONFIG_EMPTY_REPEAT to select whether
+//! the module transmits zeroes or repeats the last sample when the FIFO is
+//! empty.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulConfig & (I2S_CONFIG_FORMAT_MASK | I2S_CONFIG_MODE_MASK |
+ I2S_CONFIG_EMPTY_MASK | I2S_CONFIG_CLK_MASK |
+ I2S_CONFIG_SAMPLE_SIZE_MASK |
+ I2S_CONFIG_WIRE_SIZE_MASK)) == ulConfig);
+
+ //
+ // Clear out any prior configuration of the FIFO config registers.
+ //
+ HWREG(ulBase + I2S_O_TXFIFOCFG) = 0;
+ HWREG(ulBase + I2S_O_RXFIFOCFG) = 0;
+
+ //
+ // If mono mode is used, then the FMM bit needs to be set.
+ //
+ if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_MONO)
+ {
+ HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_FMM;
+ ulConfig &= ~(I2S_CONFIG_MODE_MONO);
+ }
+
+ //
+ // If a compact mode is used, then the CSS bit needs to be set.
+ //
+ if((ulConfig & I2S_CONFIG_MODE_MASK) == I2S_CONFIG_MODE_COMPACT_8)
+ {
+ HWREG(ulBase + I2S_O_TXFIFOCFG) |= I2S_TXFIFOCFG_CSS;
+ HWREG(ulBase + I2S_O_RXFIFOCFG) |= I2S_RXFIFOCFG_CSS;
+ }
+
+ //
+ // Write the configuration register. Since all the fields are specified by
+ // the configuration parameter, it is not necessary to do a
+ // read-modify-write.
+ //
+ HWREG(ulBase + I2S_O_TXCFG) = ulConfig;
+ HWREG(ulBase + I2S_O_RXCFG) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Selects the source of the master clock, internal or external.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulMClock is the logical OR of the master clock configuration
+//! choices.
+//!
+//! This function selects whether the master clock is sourced from the device
+//! internal PLL, or comes from an external pin. The I2S serial bit clock
+//! (SCLK) and left-right word clock (LRCLK) are derived from the I2S master
+//! clock. The transmit and receive modules can be configured independently.
+//! The \e ulMClock parameter is chosen from the following:
+//!
+//! - one of \b I2S_TX_MCLK_EXT or \b I2S_TX_MCLK_INT
+//! - one of \b I2S_RX_MCLK_EXT or \b I2S_RX_MCLK_INT
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock)
+{
+ unsigned long ulConfig;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulMClock & (I2S_TX_MCLK_EXT | I2S_RX_MCLK_EXT)) == ulMClock);
+
+ //
+ // Set the clock selection bits in the configuation word.
+ //
+ ulConfig = HWREG(ulBase + I2S_O_CFG) &
+ ~(I2S_TX_MCLK_EXT | I2S_RX_MCLK_EXT);
+ HWREG(ulBase + I2S_O_CFG) = ulConfig | ulMClock;
+}
+
+//*****************************************************************************
+//
+//! Enables I2S interrupt sources.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the specified I2S sources to generate interrupts.
+//! The \e ulIntFlags parameter can be the logical OR of any of the following
+//! values:
+//!
+//! - \b I2S_INT_RXERR for receive errors
+//! - \b I2S_INT_RXREQ for receive FIFO service requests
+//! - \b I2S_INT_TXERR for transmit errors
+//! - \b I2S_INT_TXREQ for transmit FIFO service requests
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ |
+ I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags);
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + I2S_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables I2S interrupt sources.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the specified I2S sources for interrupt
+//! generation. The \e ulIntFlags parameter can be the logical OR
+//! of any of the following values: \b I2S_INT_RXERR, \b I2S_INT_RXREQ,
+//! \b I2S_INT_TXERR, or \b I2S_INT_TXREQ.
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ |
+ I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags);
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + I2S_O_IM) &= ~ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the I2S interrupt status.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param bMasked is set \b true to get the masked interrupt status, or
+//! \b false to get the raw interrupt status.
+//!
+//! This function returns the I2S interrupt status. It can return either
+//! the raw or masked interrupt status.
+//!
+//! \return Returns the masked or raw I2S interrupt status, as a bit field
+//! of any of the following values: \b I2S_INT_RXERR, \b I2S_INT_RXREQ,
+//! \b I2S_INT_TXERR, or \b I2S_INT_TXREQ
+//
+//*****************************************************************************
+unsigned long
+I2SIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + I2S_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + I2S_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears pending I2S interrupt sources.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! This function clears the specified pending I2S interrupts. This must
+//! be done in the interrupt handler to keep the handler from being called
+//! again immediately upon exit. The \e ulIntFlags parameter can be the
+//! logical OR of any of the following values: \b I2S_INT_RXERR,
+//! \b I2S_INT_RXREQ, \b I2S_INT_TXERR, or \b I2S_INT_TXREQ.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return Returns None.
+//
+//*****************************************************************************
+void
+I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT((ulIntFlags & (I2S_INT_RXERR | I2S_INT_RXREQ |
+ I2S_INT_TXERR | I2S_INT_TXREQ)) == ulIntFlags);
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + I2S_O_IC) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the I2S controller.
+//!
+//! \param ulBase is the I2S module base address.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! This sets and enables the handler to be called when the I2S controller
+//! generates an interrupt. Specific I2S interrupts must still be enabled
+//! with the I2SIntEnable() function. It is the responsibility of the
+//! interrupt handler to clear any pending interrupts with I2SIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+ ASSERT(pfnHandler);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_I2S0, pfnHandler);
+
+ //
+ // Enable the I2S interface interrupt.
+ //
+ IntEnable(INT_I2S0);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the I2S controller.
+//!
+//! \param ulBase is the I2S module base address.
+//!
+//! This function will disable and clear the handler to be called when the
+//! I2S interrupt occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2SIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == I2S0_BASE);
+
+ //
+ // Disable the I2S interface interrupt.
+ //
+ IntDisable(INT_I2S0);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_I2S0);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/i2s.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/i2s.h
new file mode 100644
index 00000000..5782c61b
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/i2s.h
@@ -0,0 +1,154 @@
+//*****************************************************************************
+//
+// i2s.h - Prototypes and macros for the I2S controller.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __I2S_H__
+#define __I2S_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to I2STxConfigSet() and I2SRxConfigSet()
+//
+//*****************************************************************************
+#define I2S_CONFIG_FORMAT_MASK 0x3C000000 // JST, DLY, SCP, LRP
+#define I2S_CONFIG_FORMAT_I2S 0x14000000 // !JST, DLY, !SCP, LRP
+#define I2S_CONFIG_FORMAT_LEFT_JUST \
+ 0x00000000 // !JST, !DLY, !SCP, !LRP
+#define I2S_CONFIG_FORMAT_RIGHT_JUST \
+ 0x20000000 // JST, !DLY, !SCP, !LRP
+
+#define I2S_CONFIG_SCLK_INVERT 0x08000000
+
+#define I2S_CONFIG_MODE_MASK 0x03000000
+#define I2S_CONFIG_MODE_DUAL 0x00000000
+#define I2S_CONFIG_MODE_COMPACT_16 \
+ 0x01000000
+#define I2S_CONFIG_MODE_COMPACT_8 \
+ 0x03000000
+#define I2S_CONFIG_MODE_MONO 0x02000000
+
+#define I2S_CONFIG_EMPTY_MASK 0x00800000
+#define I2S_CONFIG_EMPTY_ZERO 0x00000000
+#define I2S_CONFIG_EMPTY_REPEAT 0x00800000
+
+#define I2S_CONFIG_CLK_MASK 0x00400000
+#define I2S_CONFIG_CLK_MASTER 0x00400000
+#define I2S_CONFIG_CLK_SLAVE 0x00000000
+
+#define I2S_CONFIG_SAMPLE_SIZE_MASK \
+ 0x0000FC00
+#define I2S_CONFIG_SAMPLE_SIZE_32 \
+ 0x00007C00
+#define I2S_CONFIG_SAMPLE_SIZE_24 \
+ 0x00005C00
+#define I2S_CONFIG_SAMPLE_SIZE_20 \
+ 0x00004C00
+#define I2S_CONFIG_SAMPLE_SIZE_16 \
+ 0x00003C00
+#define I2S_CONFIG_SAMPLE_SIZE_8 \
+ 0x00001C00
+
+#define I2S_CONFIG_WIRE_SIZE_MASK \
+ 0x000003F0
+#define I2S_CONFIG_WIRE_SIZE_32 0x000001F0
+#define I2S_CONFIG_WIRE_SIZE_24 0x00000170
+#define I2S_CONFIG_WIRE_SIZE_20 0x00000130
+#define I2S_CONFIG_WIRE_SIZE_16 0x000000F0
+#define I2S_CONFIG_WIRE_SIZE_8 0x00000070
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SMasterClockSelect()
+//
+//*****************************************************************************
+#define I2S_TX_MCLK_EXT 0x00000010
+#define I2S_TX_MCLK_INT 0x00000000
+#define I2S_RX_MCLK_EXT 0x00000020
+#define I2S_RX_MCLK_INT 0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SIntEnable(), I2SIntDisable(), and
+// I2SIntClear()
+//
+//*****************************************************************************
+#define I2S_INT_RXERR 0x00000020
+#define I2S_INT_RXREQ 0x00000010
+#define I2S_INT_TXERR 0x00000002
+#define I2S_INT_TXREQ 0x00000001
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void I2STxEnable(unsigned long ulBase);
+extern void I2STxDisable(unsigned long ulBase);
+extern void I2STxDataPut(unsigned long ulBase, unsigned long ulData);
+extern long I2STxDataPutNonBlocking(unsigned long ulBase,
+ unsigned long ulData);
+extern void I2STxConfigSet(unsigned long ulBase, unsigned long ulConfig);
+extern void I2STxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel);
+extern unsigned long I2STxFIFOLimitGet(unsigned long ulBase);
+extern unsigned long I2STxFIFOLevelGet(unsigned long ulBase);
+extern void I2SRxEnable(unsigned long ulBase);
+extern void I2SRxDisable(unsigned long ulBase);
+extern void I2SRxDataGet(unsigned long ulBase, unsigned long *pulData);
+extern long I2SRxDataGetNonBlocking(unsigned long ulBase,
+ unsigned long *pulData);
+extern void I2SRxConfigSet(unsigned long ulBase, unsigned long ulConfig);
+extern void I2SRxFIFOLimitSet(unsigned long ulBase, unsigned long ulLevel);
+extern unsigned long I2SRxFIFOLimitGet(unsigned long ulBase);
+extern unsigned long I2SRxFIFOLevelGet(unsigned long ulBase);
+extern void I2STxRxEnable(unsigned long ulBase);
+extern void I2STxRxDisable(unsigned long ulBase);
+extern void I2STxRxConfigSet(unsigned long ulBase, unsigned long ulConfig);
+extern void I2SMasterClockSelect(unsigned long ulBase, unsigned long ulMClock);
+extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long I2SIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern void I2SIntUnregister(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __I2S_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/interrupt.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/interrupt.c
new file mode 100644
index 00000000..20e3a052
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/interrupt.c
@@ -0,0 +1,723 @@
+//*****************************************************************************
+//
+// interrupt.c - Driver for the NVIC Interrupt Controller.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup interrupt_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/cpu.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+
+//*****************************************************************************
+//
+// This is a mapping between priority grouping encodings and the number of
+// preemption priority bits.
+//
+//*****************************************************************************
+static const unsigned long g_pulPriority[] =
+{
+ NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
+ NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
+ NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
+};
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number and the register that contains
+// the priority encoding for that interrupt.
+//
+//*****************************************************************************
+static const unsigned long g_pulRegs[] =
+{
+ 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
+ NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
+ NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! The default interrupt handler.
+//!
+//! This is the default interrupt handler for all interrupts. It simply loops
+//! forever so that the system state is preserved for observation by a
+//! debugger. Since interrupts should be disabled before unregistering the
+//! corresponding handler, this should never be called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+IntDefaultHandler(void)
+{
+ //
+ // Go into an infinite loop.
+ //
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// The processor vector table.
+//
+// This contains a list of the handlers for the various interrupt sources in
+// the system. The layout of this list is defined by the hardware; assertion
+// of an interrupt causes the processor to start executing directly at the
+// address given in the corresponding location in this list.
+//
+//*****************************************************************************
+#if defined(ewarm)
+static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
+#elif defined(sourcerygxx)
+static __attribute__((section(".cs3.region-head.ram")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
+#elif defined(ccs)
+#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
+#else
+static __attribute__((section("vtable")))
+void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
+#endif
+
+//*****************************************************************************
+//
+//! Enables the processor interrupt.
+//!
+//! Allows the processor to respond to interrupts. This does not affect the
+//! set of interrupts enabled in the interrupt controller; it just gates the
+//! single interrupt from the controller to the processor.
+//!
+//! \note Previously, this function had no return value. As such, it was
+//! possible to include interrupt.h and call this function without
+//! having included hw_types.h. Now that the return is a
+//! tBoolean, a compiler error will occur in this case. The solution
+//! is to include hw_types.h before including interrupt.h.
+//!
+//! \return Returns \b true if interrupts were disabled when the function was
+//! called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+tBoolean
+IntMasterEnable(void)
+{
+ //
+ // Enable processor interrupts.
+ //
+ return(CPUcpsie());
+}
+
+//*****************************************************************************
+//
+//! Disables the processor interrupt.
+//!
+//! Prevents the processor from receiving interrupts. This does not affect the
+//! set of interrupts enabled in the interrupt controller; it just gates the
+//! single interrupt from the controller to the processor.
+//!
+//! \note Previously, this function had no return value. As such, it was
+//! possible to include interrupt.h and call this function without
+//! having included hw_types.h. Now that the return is a
+//! tBoolean, a compiler error will occur in this case. The solution
+//! is to include hw_types.h before including interrupt.h.
+//!
+//! \return Returns \b true if interrupts were already disabled when the
+//! function was called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+tBoolean
+IntMasterDisable(void)
+{
+ //
+ // Disable processor interrupts.
+ //
+ return(CPUcpsid());
+}
+
+//*****************************************************************************
+//
+//! Registers a function to be called when an interrupt occurs.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//! \param pfnHandler is a pointer to the function to be called.
+//!
+//! This function is used to specify the handler function to be called when the
+//! given interrupt is asserted to the processor. When the interrupt occurs,
+//! if it is enabled (via IntEnable()), the handler function will be called in
+//! interrupt context. Since the handler function can preempt other code, care
+//! must be taken to protect memory or peripherals that are accessed by the
+//! handler and other non-handler code.
+//!
+//! \note The use of this function (directly or indirectly via a peripheral
+//! driver interrupt register function) moves the interrupt vector table from
+//! flash to SRAM. Therefore, care must be taken when linking the application
+//! to ensure that the SRAM vector table is located at the beginning of SRAM;
+//! otherwise NVIC will not look in the correct portion of memory for the
+//! vector table (it requires the vector table be on a 1 kB memory alignment).
+//! Normally, the SRAM vector table is so placed via the use of linker scripts.
+//! See the discussion of compile-time versus run-time interrupt handler
+//! registration in the introduction to this chapter.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
+{
+ unsigned long ulIdx, ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Make sure that the RAM vector table is correctly aligned.
+ //
+ ASSERT(((unsigned long)g_pfnRAMVectors & 0x000003ff) == 0);
+
+ //
+ // See if the RAM vector table has been initialized.
+ //
+ if(HWREG(NVIC_VTABLE) != (unsigned long)g_pfnRAMVectors)
+ {
+ //
+ // Copy the vector table from the beginning of FLASH to the RAM vector
+ // table.
+ //
+ ulValue = HWREG(NVIC_VTABLE);
+ for(ulIdx = 0; ulIdx < NUM_INTERRUPTS; ulIdx++)
+ {
+ g_pfnRAMVectors[ulIdx] = (void (*)(void))HWREG((ulIdx * 4) +
+ ulValue);
+ }
+
+ //
+ // Point NVIC at the RAM vector table.
+ //
+ HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;
+ }
+
+ //
+ // Save the interrupt handler.
+ //
+ g_pfnRAMVectors[ulInterrupt] = pfnHandler;
+}
+
+//*****************************************************************************
+//
+//! Unregisters the function to be called when an interrupt occurs.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//!
+//! This function is used to indicate that no handler should be called when the
+//! given interrupt is asserted to the processor. The interrupt source will be
+//! automatically disabled (via IntDisable()) if necessary.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntUnregister(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Reset the interrupt handler.
+ //
+ g_pfnRAMVectors[ulInterrupt] = IntDefaultHandler;
+}
+
+//*****************************************************************************
+//
+//! Sets the priority grouping of the interrupt controller.
+//!
+//! \param ulBits specifies the number of bits of preemptable priority.
+//!
+//! This function specifies the split between preemptable priority levels and
+//! subpriority levels in the interrupt priority specification. The range of
+//! the grouping values are dependent upon the hardware implementation; on
+//! the Stellaris family, three bits are available for hardware interrupt
+//! prioritization and therefore priority grouping values of three through
+//! seven have the same effect.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPriorityGroupingSet(unsigned long ulBits)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBits < NUM_PRIORITY);
+
+ //
+ // Set the priority grouping.
+ //
+ HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
+}
+
+//*****************************************************************************
+//
+//! Gets the priority grouping of the interrupt controller.
+//!
+//! This function returns the split between preemptable priority levels and
+//! subpriority levels in the interrupt priority specification.
+//!
+//! \return The number of bits of preemptable priority.
+//
+//*****************************************************************************
+unsigned long
+IntPriorityGroupingGet(void)
+{
+ unsigned long ulLoop, ulValue;
+
+ //
+ // Read the priority grouping.
+ //
+ ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
+
+ //
+ // Loop through the priority grouping values.
+ //
+ for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
+ {
+ //
+ // Stop looping if this value matches.
+ //
+ if(ulValue == g_pulPriority[ulLoop])
+ {
+ break;
+ }
+ }
+
+ //
+ // Return the number of priority bits.
+ //
+ return(ulLoop);
+}
+
+//*****************************************************************************
+//
+//! Sets the priority of an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//! \param ucPriority specifies the priority of the interrupt.
+//!
+//! This function is used to set the priority of an interrupt. When multiple
+//! interrupts are asserted simultaneously, the ones with the highest priority
+//! are processed before the lower priority interrupts. Smaller numbers
+//! correspond to higher interrupt priorities; priority 0 is the highest
+//! interrupt priority.
+//!
+//! The hardware priority mechanism will only look at the upper N bits of the
+//! priority level (where N is 3 for the Stellaris family), so any
+//! prioritization must be performed in those bits. The remaining bits can be
+//! used to sub-prioritize the interrupt sources, and may be used by the
+//! hardware priority mechanism on a future part. This arrangement allows
+//! priorities to migrate to different NVIC implementations without changing
+//! the gross prioritization of the interrupts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
+
+ //
+ // Set the interrupt priority.
+ //
+ ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
+ ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
+ ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
+ HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the priority of an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//!
+//! This function gets the priority of an interrupt. See IntPrioritySet() for
+//! a definition of the priority value.
+//!
+//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
+//! specified.
+//
+//*****************************************************************************
+long
+IntPriorityGet(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
+
+ //
+ // Return the interrupt priority.
+ //
+ return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
+ 0xFF);
+}
+
+//*****************************************************************************
+//
+//! Enables an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be enabled.
+//!
+//! The specified interrupt is enabled in the interrupt controller. Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntEnable(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Determine the interrupt to enable.
+ //
+ if(ulInterrupt == FAULT_MPU)
+ {
+ //
+ // Enable the MemManage interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
+ }
+ else if(ulInterrupt == FAULT_BUS)
+ {
+ //
+ // Enable the bus fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
+ }
+ else if(ulInterrupt == FAULT_USAGE)
+ {
+ //
+ // Enable the usage fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
+ }
+ else if(ulInterrupt == FAULT_SYSTICK)
+ {
+ //
+ // Enable the System Tick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+ }
+ else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
+ {
+ //
+ // Enable the general interrupt.
+ //
+ HWREG(NVIC_EN0) = 1 << (ulInterrupt - 16);
+ }
+ else if(ulInterrupt >= 48)
+ {
+ //
+ // Enable the general interrupt.
+ //
+ HWREG(NVIC_EN1) = 1 << (ulInterrupt - 48);
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be disabled.
+//!
+//! The specified interrupt is disabled in the interrupt controller. Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntDisable(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Determine the interrupt to disable.
+ //
+ if(ulInterrupt == FAULT_MPU)
+ {
+ //
+ // Disable the MemManage interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
+ }
+ else if(ulInterrupt == FAULT_BUS)
+ {
+ //
+ // Disable the bus fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
+ }
+ else if(ulInterrupt == FAULT_USAGE)
+ {
+ //
+ // Disable the usage fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
+ }
+ else if(ulInterrupt == FAULT_SYSTICK)
+ {
+ //
+ // Disable the System Tick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+ }
+ else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
+ {
+ //
+ // Disable the general interrupt.
+ //
+ HWREG(NVIC_DIS0) = 1 << (ulInterrupt - 16);
+ }
+ else if(ulInterrupt >= 48)
+ {
+ //
+ // Disable the general interrupt.
+ //
+ HWREG(NVIC_DIS1) = 1 << (ulInterrupt - 48);
+ }
+}
+
+//*****************************************************************************
+//
+//! Pends an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be pended.
+//!
+//! The specified interrupt is pended in the interrupt controller. This will
+//! cause the interrupt controller to execute the corresponding interrupt
+//! handler at the next available time, based on the current interrupt state
+//! priorities. For example, if called by a higher priority interrupt handler,
+//! the specified interrupt handler will not be called until after the current
+//! interrupt handler has completed execution. The interrupt must have been
+//! enabled for it to be called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPendSet(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Determine the interrupt to pend.
+ //
+ if(ulInterrupt == FAULT_NMI)
+ {
+ //
+ // Pend the NMI interrupt.
+ //
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
+ }
+ else if(ulInterrupt == FAULT_PENDSV)
+ {
+ //
+ // Pend the PendSV interrupt.
+ //
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
+ }
+ else if(ulInterrupt == FAULT_SYSTICK)
+ {
+ //
+ // Pend the SysTick interrupt.
+ //
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
+ }
+ else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
+ {
+ //
+ // Pend the general interrupt.
+ //
+ HWREG(NVIC_PEND0) = 1 << (ulInterrupt - 16);
+ }
+ else if(ulInterrupt >= 48)
+ {
+ //
+ // Pend the general interrupt.
+ //
+ HWREG(NVIC_PEND1) = 1 << (ulInterrupt - 48);
+ }
+}
+
+//*****************************************************************************
+//
+//! Unpends an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be unpended.
+//!
+//! The specified interrupt is unpended in the interrupt controller. This will
+//! cause any previously generated interrupts that have not been handled yet
+//! (due to higher priority interrupts or the interrupt no having been enabled
+//! yet) to be discarded.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPendClear(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Determine the interrupt to unpend.
+ //
+ if(ulInterrupt == FAULT_PENDSV)
+ {
+ //
+ // Unpend the PendSV interrupt.
+ //
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
+ }
+ else if(ulInterrupt == FAULT_SYSTICK)
+ {
+ //
+ // Unpend the SysTick interrupt.
+ //
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
+ }
+ else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
+ {
+ //
+ // Unpend the general interrupt.
+ //
+ HWREG(NVIC_UNPEND0) = 1 << (ulInterrupt - 16);
+ }
+ else if(ulInterrupt >= 48)
+ {
+ //
+ // Unpend the general interrupt.
+ //
+ HWREG(NVIC_UNPEND1) = 1 << (ulInterrupt - 48);
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the priority masking level
+//!
+//! \param ulPriorityMask is the priority level that will be masked.
+//!
+//! This function sets the interrupt priority masking level so that all
+//! interrupts at the specified or lesser priority level is masked. This
+//! can be used to globally disable a set of interrupts with priority below
+//! a predetermined threshold. A value of 0 disables priority
+//! masking.
+//!
+//! Smaller numbers correspond to higher interrupt priorities. So for example
+//! a priority level mask of 4 will allow interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater will be blocked.
+//!
+//! The hardware priority mechanism will only look at the upper N bits of the
+//! priority level (where N is 3 for the Stellaris family), so any
+//! prioritization must be performed in those bits.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPriorityMaskSet(unsigned long ulPriorityMask)
+{
+ CPUbasepriSet(ulPriorityMask);
+}
+
+//*****************************************************************************
+//
+//! Gets the priority masking level
+//!
+//! This function gets the current setting of the interrupt priority masking
+//! level. The value returned is the priority level such that all interrupts
+//! of that and lesser priority are masked. A value of 0 means that priority
+//! masking is disabled.
+//!
+//! Smaller numbers correspond to higher interrupt priorities. So for example
+//! a priority level mask of 4 will allow interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater will be blocked.
+//!
+//! The hardware priority mechanism will only look at the upper N bits of the
+//! priority level (where N is 3 for the Stellaris family), so any
+//! prioritization must be performed in those bits.
+//!
+//! \return Returns the value of the interrupt priority level mask.
+//
+//*****************************************************************************
+unsigned long
+IntPriorityMaskGet(void)
+{
+ return(CPUbasepriGet());
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/interrupt.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/interrupt.h
new file mode 100644
index 00000000..954f5775
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/interrupt.h
@@ -0,0 +1,77 @@
+//*****************************************************************************
+//
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Macro to generate an interrupt priority mask based on the number of bits
+// of priority supported by the hardware.
+//
+//*****************************************************************************
+#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern tBoolean IntMasterEnable(void);
+extern tBoolean IntMasterDisable(void);
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
+extern void IntUnregister(unsigned long ulInterrupt);
+extern void IntPriorityGroupingSet(unsigned long ulBits);
+extern unsigned long IntPriorityGroupingGet(void);
+extern void IntPrioritySet(unsigned long ulInterrupt,
+ unsigned char ucPriority);
+extern long IntPriorityGet(unsigned long ulInterrupt);
+extern void IntEnable(unsigned long ulInterrupt);
+extern void IntDisable(unsigned long ulInterrupt);
+extern void IntPendSet(unsigned long ulInterrupt);
+extern void IntPendClear(unsigned long ulInterrupt);
+extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
+extern unsigned long IntPriorityMaskGet(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __INTERRUPT_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/mpu.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/mpu.c
new file mode 100644
index 00000000..cb570006
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/mpu.c
@@ -0,0 +1,446 @@
+//*****************************************************************************
+//
+// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup mpu_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/mpu.h"
+
+//*****************************************************************************
+//
+//! Enables and configures the MPU for use.
+//!
+//! \param ulMPUConfig is the logical OR of the possible configurations.
+//!
+//! This function enables the Cortex-M3 memory protection unit. It also
+//! configures the default behavior when in privileged mode and while
+//! handling a hard fault or NMI. Prior to enabling the MPU, at least one
+//! region must be set by calling MPURegionSet() or else by enabling the
+//! default region for privileged mode by passing the
+//! \b MPU_CONFIG_PRIV_DEFAULT flag to MPUEnable().
+//! Once the MPU is enabled, a memory management fault will be generated
+//! for any memory access violations.
+//!
+//! The \e ulMPUConfig parameter should be the logical OR of any of the
+//! following:
+//!
+//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in
+//! privileged mode and when no other regions are defined. If this option
+//! is not enabled, then there must be at least one valid region already
+//! defined when the MPU is enabled.
+//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI
+//! exception handler. If this option is not enabled, then the MPU is
+//! disabled while in one of these exception handlers and the default
+//! memory map is applied.
+//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case,
+//! no default memory map is provided in privileged mode, and the MPU will
+//! not be enabled in the fault handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPUEnable(unsigned long ulMPUConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulMPUConfig & ~(MPU_CONFIG_PRIV_DEFAULT |
+ MPU_CONFIG_HARDFLT_NMI)));
+
+ //
+ // Set the MPU control bits according to the flags passed by the user,
+ // and also set the enable bit.
+ //
+ HWREG(NVIC_MPU_CTRL) = ulMPUConfig | NVIC_MPU_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the MPU for use.
+//!
+//! This function disables the Cortex-M3 memory protection unit. When the
+//! MPU is disabled, the default memory map is used and memory management
+//! faults are not generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPUDisable(void)
+{
+ //
+ // Turn off the MPU enable bit.
+ //
+ HWREG(NVIC_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Gets the count of regions supported by the MPU.
+//!
+//! This function is used to get the number of regions that are supported by
+//! the MPU. This is the total number that are supported, including regions
+//! that are already programmed.
+//!
+//! \return The number of memory protection regions that are available
+//! for programming using MPURegionSet().
+//
+//*****************************************************************************
+unsigned long
+MPURegionCountGet(void)
+{
+ //
+ // Read the DREGION field of the MPU type register, and mask off
+ // the bits of interest to get the count of regions.
+ //
+ return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M)
+ >> NVIC_MPU_TYPE_DREGION_S);
+}
+
+//*****************************************************************************
+//
+//! Enables a specific region.
+//!
+//! \param ulRegion is the region number to enable.
+//!
+//! This function is used to enable a memory protection region. The region
+//! should already be set up with the MPURegionSet() function. Once enabled,
+//! the memory protection rules of the region will be applied and access
+//! violations will cause a memory management fault.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPURegionEnable(unsigned long ulRegion)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulRegion < 8);
+
+ //
+ // Select the region to modify.
+ //
+ HWREG(NVIC_MPU_NUMBER) = ulRegion;
+
+ //
+ // Modify the enable bit in the region attributes.
+ //
+ HWREG(NVIC_MPU_ATTR) |= NVIC_MPU_ATTR_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables a specific region.
+//!
+//! \param ulRegion is the region number to disable.
+//!
+//! This function is used to disable a previously enabled memory protection
+//! region. The region will remain configured if it is not overwritten with
+//! another call to MPURegionSet(), and can be enabled again by calling
+//! MPURegionEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPURegionDisable(unsigned long ulRegion)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulRegion < 8);
+
+ //
+ // Select the region to modify.
+ //
+ HWREG(NVIC_MPU_NUMBER) = ulRegion;
+
+ //
+ // Modify the enable bit in the region attributes.
+ //
+ HWREG(NVIC_MPU_ATTR) &= ~NVIC_MPU_ATTR_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Sets up the access rules for a specific region.
+//!
+//! \param ulRegion is the region number to set up.
+//! \param ulAddr is the base address of the region. It must be aligned
+//! according to the size of the region specified in ulFlags.
+//! \param ulFlags is a set of flags to define the attributes of the region.
+//!
+//! This function sets up the protection rules for a region. The region has
+//! a base address and a set of attributes including the size, which must
+//! be a power of 2. The base address parameter, \e ulAddr, must be aligned
+//! according to the size.
+//!
+//! The \e ulFlags parameter is the logical OR of all of the attributes
+//! of the region. It is a combination of choices for region size,
+//! execute permission, read/write permissions, disabled sub-regions,
+//! and a flag to determine if the region is enabled.
+//!
+//! The size flag determines the size of a region, and must be one of the
+//! following:
+//!
+//! - \b MPU_RGN_SIZE_32B
+//! - \b MPU_RGN_SIZE_64B
+//! - \b MPU_RGN_SIZE_128B
+//! - \b MPU_RGN_SIZE_256B
+//! - \b MPU_RGN_SIZE_512B
+//! - \b MPU_RGN_SIZE_1K
+//! - \b MPU_RGN_SIZE_2K
+//! - \b MPU_RGN_SIZE_4K
+//! - \b MPU_RGN_SIZE_8K
+//! - \b MPU_RGN_SIZE_16K
+//! - \b MPU_RGN_SIZE_32K
+//! - \b MPU_RGN_SIZE_64K
+//! - \b MPU_RGN_SIZE_128K
+//! - \b MPU_RGN_SIZE_256K
+//! - \b MPU_RGN_SIZE_512K
+//! - \b MPU_RGN_SIZE_1M
+//! - \b MPU_RGN_SIZE_2M
+//! - \b MPU_RGN_SIZE_4M
+//! - \b MPU_RGN_SIZE_8M
+//! - \b MPU_RGN_SIZE_16M
+//! - \b MPU_RGN_SIZE_32M
+//! - \b MPU_RGN_SIZE_64M
+//! - \b MPU_RGN_SIZE_128M
+//! - \b MPU_RGN_SIZE_256M
+//! - \b MPU_RGN_SIZE_512M
+//! - \b MPU_RGN_SIZE_1G
+//! - \b MPU_RGN_SIZE_2G
+//! - \b MPU_RGN_SIZE_4G
+//!
+//! The execute permission flag must be one of the following:
+//!
+//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code
+//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code
+//!
+//! The read/write access permissions are applied separately for the
+//! privileged and user modes. The read/write access flags must be one
+//! of the following:
+//!
+//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode
+//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access
+//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only
+//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write
+//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access
+//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only
+//!
+//! The region is automatically divided into 8 equally-sized sub-regions by
+//! the MPU. Sub-regions can only be used in regions of size 256 bytes
+//! or larger. Any of these 8 sub-regions can be disabled. This allows
+//! for creation of ``holes'' in a region which can be left open, or overlaid
+//! by another region with different attributes. Any of the 8 sub-regions
+//! can be disabled with a logical OR of any of the following flags:
+//!
+//! - \b MPU_SUB_RGN_DISABLE_0
+//! - \b MPU_SUB_RGN_DISABLE_1
+//! - \b MPU_SUB_RGN_DISABLE_2
+//! - \b MPU_SUB_RGN_DISABLE_3
+//! - \b MPU_SUB_RGN_DISABLE_4
+//! - \b MPU_SUB_RGN_DISABLE_5
+//! - \b MPU_SUB_RGN_DISABLE_6
+//! - \b MPU_SUB_RGN_DISABLE_7
+//!
+//! Finally, the region can be initially enabled or disabled with one of
+//! the following flags:
+//!
+//! - \b MPU_RGN_ENABLE
+//! - \b MPU_RGN_DISABLE
+//!
+//! As an example, to set a region with the following attributes: size of
+//! 32 KB, execution enabled, read-only for both privileged and user, one
+//! sub-region disabled, and initially enabled; the \e ulFlags parameter would
+//! have the following value:
+//!
+//!
+//! (MPU_RG_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |
+//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
+//!
+//!
+//! \note This function will write to multiple registers and is not protected
+//! from interrupts. It is possible that an interrupt which accesses a
+//! region may occur while that region is in the process of being changed.
+//! The safest way to handle this is to disable a region before changing it.
+//! Refer to the discussion of this in the API Detailed Description section.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulRegion < 8);
+ ASSERT((ulAddr & ~0 << (((ulFlags & NVIC_MPU_ATTR_SIZE_M) >> 1) + 1))
+ == ulAddr);
+
+ //
+ // Program the base address, use the region field to select the
+ // region at the same time.
+ //
+ HWREG(NVIC_MPU_BASE) = ulAddr | ulRegion | NVIC_MPU_BASE_VALID;
+
+ //
+ // Program the region attributes. Set the TEX field and the S, C,
+ // and B bits to fixed values that are suitable for all Stellaris
+ // memory.
+ //
+ HWREG(NVIC_MPU_ATTR) = (ulFlags & ~(NVIC_MPU_ATTR_TEX_M |
+ NVIC_MPU_ATTR_CACHEABLE)) |
+ NVIC_MPU_ATTR_SHAREABLE |
+ NVIC_MPU_ATTR_BUFFRABLE;
+}
+
+//*****************************************************************************
+//
+//! Gets the current settings for a specific region.
+//!
+//! \param ulRegion is the region number to get.
+//! \param pulAddr points to storage for the base address of the region.
+//! \param pulFlags points to the attribute flags for the region.
+//!
+//! This function retrieves the configuration of a specific region. The
+//! meanings and format of the parameters is the same as that of the
+//! MPURegionSet() function.
+//!
+//! This function can be used to save the configuration of a region for
+//! later use with the MPURegionSet() function. The region's enable state
+//! will be preserved in the attributes that are saved.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
+ unsigned long *pulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulRegion < 8);
+ ASSERT(pulAddr);
+ ASSERT(pulFlags);
+
+ //
+ // Select the region to get.
+ //
+ HWREG(NVIC_MPU_NUMBER) = ulRegion;
+
+ //
+ // Read and store the base address for the region.
+ //
+ *pulAddr = HWREG(NVIC_MPU_BASE);
+
+ //
+ // Read and store the region attributes.
+ //
+ *pulFlags = HWREG(NVIC_MPU_ATTR);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the memory management fault.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! memory management fault occurs.
+//!
+//! This sets and enables the handler to be called when the MPU generates
+//! a memory management fault due to a protection region access violation.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPUIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(pfnHandler);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(FAULT_MPU, pfnHandler);
+
+ //
+ // Enable the memory management fault.
+ //
+ IntEnable(FAULT_MPU);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the memory management fault.
+//!
+//! This function will disable and clear the handler to be called when a
+//! memory management fault occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+MPUIntUnregister(void)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(FAULT_MPU);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(FAULT_MPU);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/mpu.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/mpu.h
new file mode 100644
index 00000000..744be354
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/mpu.h
@@ -0,0 +1,147 @@
+//*****************************************************************************
+//
+// mpu.h - Defines and Macros for the memory protection unit.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __MPU_H__
+#define __MPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Flags that can be passed to MPUEnable.
+//
+//*****************************************************************************
+#define MPU_CONFIG_PRIV_DEFAULT 4
+#define MPU_CONFIG_HARDFLT_NMI 2
+#define MPU_CONFIG_NONE 0
+
+//*****************************************************************************
+//
+// Flags for the region size to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_SIZE_32B (4 << 1)
+#define MPU_RGN_SIZE_64B (5 << 1)
+#define MPU_RGN_SIZE_128B (6 << 1)
+#define MPU_RGN_SIZE_256B (7 << 1)
+#define MPU_RGN_SIZE_512B (8 << 1)
+
+#define MPU_RGN_SIZE_1K (9 << 1)
+#define MPU_RGN_SIZE_2K (10 << 1)
+#define MPU_RGN_SIZE_4K (11 << 1)
+#define MPU_RGN_SIZE_8K (12 << 1)
+#define MPU_RGN_SIZE_16K (13 << 1)
+#define MPU_RGN_SIZE_32K (14 << 1)
+#define MPU_RGN_SIZE_64K (15 << 1)
+#define MPU_RGN_SIZE_128K (16 << 1)
+#define MPU_RGN_SIZE_256K (17 << 1)
+#define MPU_RGN_SIZE_512K (18 << 1)
+
+#define MPU_RGN_SIZE_1M (19 << 1)
+#define MPU_RGN_SIZE_2M (20 << 1)
+#define MPU_RGN_SIZE_4M (21 << 1)
+#define MPU_RGN_SIZE_8M (22 << 1)
+#define MPU_RGN_SIZE_16M (23 << 1)
+#define MPU_RGN_SIZE_32M (24 << 1)
+#define MPU_RGN_SIZE_64M (25 << 1)
+#define MPU_RGN_SIZE_128M (26 << 1)
+#define MPU_RGN_SIZE_256M (27 << 1)
+#define MPU_RGN_SIZE_512M (28 << 1)
+
+#define MPU_RGN_SIZE_1G (29 << 1)
+#define MPU_RGN_SIZE_2G (30 << 1)
+#define MPU_RGN_SIZE_4G (31 << 1)
+
+//*****************************************************************************
+//
+// Flags for the permissions to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_PERM_EXEC 0x00000000
+#define MPU_RGN_PERM_NOEXEC 0x10000000
+#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000
+#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000
+#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000
+#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000
+#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000
+#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000
+
+//*****************************************************************************
+//
+// Flags for the sub-region to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_SUB_RGN_DISABLE_0 0x00000100
+#define MPU_SUB_RGN_DISABLE_1 0x00000200
+#define MPU_SUB_RGN_DISABLE_2 0x00000400
+#define MPU_SUB_RGN_DISABLE_3 0x00000800
+#define MPU_SUB_RGN_DISABLE_4 0x00001000
+#define MPU_SUB_RGN_DISABLE_5 0x00002000
+#define MPU_SUB_RGN_DISABLE_6 0x00004000
+#define MPU_SUB_RGN_DISABLE_7 0x00008000
+
+//*****************************************************************************
+//
+// Flags to enable or disable a region, to be passed to MPURegionSet.
+//
+//*****************************************************************************
+#define MPU_RGN_ENABLE 1
+#define MPU_RGN_DISABLE 0
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void MPUEnable(unsigned long ulMPUConfig);
+extern void MPUDisable(void);
+extern unsigned long MPURegionCountGet(void);
+extern void MPURegionEnable(unsigned long ulRegion);
+extern void MPURegionDisable(unsigned long ulRegion);
+extern void MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
+ unsigned long ulFlags);
+extern void MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
+ unsigned long *pulFlags);
+extern void MPUIntRegister(void (*pfnHandler)(void));
+extern void MPUIntUnregister(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __MPU_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/pin_map.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/pin_map.h
new file mode 100644
index 00000000..d946c355
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/pin_map.h
@@ -0,0 +1,20413 @@
+//*****************************************************************************
+//
+// pin_map.h - Mapping of peripherals to pins for all parts.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __PIN_MAP_H__
+#define __PIN_MAP_H__
+
+//*****************************************************************************
+//
+// LM3S101 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S101
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define 32KHZ_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define 32KHZ_PORT (GPIO_PORTB_BASE)
+#define 32KHZ_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S101
+
+//*****************************************************************************
+//
+// LM3S102 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S102
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define 32KHZ_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define 32KHZ_PORT (GPIO_PORTB_BASE)
+#define 32KHZ_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S102
+
+//*****************************************************************************
+//
+// LM3S300 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S300
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S300
+
+//*****************************************************************************
+//
+// LM3S301 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S301
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S301
+
+//*****************************************************************************
+//
+// LM3S308 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S308
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S308
+
+//*****************************************************************************
+//
+// LM3S310 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S310
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S310
+
+//*****************************************************************************
+//
+// LM3S315 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S315
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S315
+
+//*****************************************************************************
+//
+// LM3S316 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S316
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S316
+
+//*****************************************************************************
+//
+// LM3S317 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S317
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S317
+
+//*****************************************************************************
+//
+// LM3S328 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S328
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S328
+
+//*****************************************************************************
+//
+// LM3S600 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S600
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S600
+
+//*****************************************************************************
+//
+// LM3S601 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S601
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define IDX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX_PORT (GPIO_PORTD_BASE)
+#define IDX_PIN (GPIO_PIN_7)
+
+#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA_PORT (GPIO_PORTC_BASE)
+#define PHA_PIN (GPIO_PIN_4)
+
+#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB_PORT (GPIO_PORTC_BASE)
+#define PHB_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S601
+
+//*****************************************************************************
+//
+// LM3S608 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S608
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S608
+
+//*****************************************************************************
+//
+// LM3S610 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S610
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S610
+
+//*****************************************************************************
+//
+// LM3S611 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S611
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S611
+
+//*****************************************************************************
+//
+// LM3S612 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S612
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S612
+
+//*****************************************************************************
+//
+// LM3S613 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S613
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S613
+
+//*****************************************************************************
+//
+// LM3S615 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S615
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S615
+
+//*****************************************************************************
+//
+// LM3S617 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S617
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S617
+
+//*****************************************************************************
+//
+// LM3S618 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S618
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define IDX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define IDX_PORT (GPIO_PORTB_BASE)
+#define IDX_PIN (GPIO_PIN_2)
+
+#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA_PORT (GPIO_PORTC_BASE)
+#define PHA_PIN (GPIO_PIN_4)
+
+#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB_PORT (GPIO_PORTC_BASE)
+#define PHB_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S618
+
+//*****************************************************************************
+//
+// LM3S628 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S628
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S628
+
+//*****************************************************************************
+//
+// LM3S800 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S800
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S800
+
+//*****************************************************************************
+//
+// LM3S801 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S801
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define IDX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX_PORT (GPIO_PORTD_BASE)
+#define IDX_PIN (GPIO_PIN_7)
+
+#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA_PORT (GPIO_PORTC_BASE)
+#define PHA_PIN (GPIO_PIN_4)
+
+#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB_PORT (GPIO_PORTC_BASE)
+#define PHB_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S801
+
+//*****************************************************************************
+//
+// LM3S808 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S808
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S808
+
+//*****************************************************************************
+//
+// LM3S811 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S811
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S811
+
+//*****************************************************************************
+//
+// LM3S812 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S812
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S812
+
+//*****************************************************************************
+//
+// LM3S815 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S815
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S815
+
+//*****************************************************************************
+//
+// LM3S817 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S817
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S817
+
+//*****************************************************************************
+//
+// LM3S818 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S818
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define IDX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define IDX_PORT (GPIO_PORTB_BASE)
+#define IDX_PIN (GPIO_PIN_2)
+
+#define PHA_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA_PORT (GPIO_PORTC_BASE)
+#define PHA_PIN (GPIO_PIN_4)
+
+#define PHB_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB_PORT (GPIO_PORTC_BASE)
+#define PHB_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S818
+
+//*****************************************************************************
+//
+// LM3S828 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S828
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2CSCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSCL_PORT (GPIO_PORTB_BASE)
+#define I2CSCL_PIN (GPIO_PIN_2)
+
+#define I2CSDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2CSDA_PORT (GPIO_PORTB_BASE)
+#define I2CSDA_PIN (GPIO_PIN_3)
+
+#define SSICLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSICLK_PORT (GPIO_PORTA_BASE)
+#define SSICLK_PIN (GPIO_PIN_2)
+
+#define SSIFSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIFSS_PORT (GPIO_PORTA_BASE)
+#define SSIFSS_PIN (GPIO_PIN_3)
+
+#define SSIRX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSIRX_PORT (GPIO_PORTA_BASE)
+#define SSIRX_PIN (GPIO_PIN_4)
+
+#define SSITX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSITX_PORT (GPIO_PORTA_BASE)
+#define SSITX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S828
+
+//*****************************************************************************
+//
+// LM3S1110 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1110
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1110
+
+//*****************************************************************************
+//
+// LM3S1133 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1133
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1133
+
+//*****************************************************************************
+//
+// LM3S1138 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1138
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP3_PORT (GPIO_PORTG_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP4_PORT (GPIO_PORTF_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1138
+
+//*****************************************************************************
+//
+// LM3S1150 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1150
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1150
+
+//*****************************************************************************
+//
+// LM3S1162 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1162
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1162
+
+//*****************************************************************************
+//
+// LM3S1165 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1165
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP6_PORT (GPIO_PORTB_BASE)
+#define CCP6_PIN (GPIO_PIN_5)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1165
+
+//*****************************************************************************
+//
+// LM3S1332 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1332
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1332
+
+//*****************************************************************************
+//
+// LM3S1435 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1435
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1435
+
+//*****************************************************************************
+//
+// LM3S1439 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1439
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1439
+
+//*****************************************************************************
+//
+// LM3S1512 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1512
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C2O_PORT (GPIO_PORTF_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP4_PORT (GPIO_PORTD_BASE)
+#define CCP4_PIN (GPIO_PIN_5)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1512
+
+//*****************************************************************************
+//
+// LM3S1538 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1538
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1538
+
+//*****************************************************************************
+//
+// LM3S1601 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1601
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1601
+
+//*****************************************************************************
+//
+// LM3S1607 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1607
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_1)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_0)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_5)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U2RX_PORT (GPIO_PORTB_BASE)
+#define U2RX_PIN (GPIO_PIN_4)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define U2TX_PORT (GPIO_PORTE_BASE)
+#define U2TX_PIN (GPIO_PIN_4)
+
+#endif // PART_LM3S1607
+
+//*****************************************************************************
+//
+// LM3S1608 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1608
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1608
+
+//*****************************************************************************
+//
+// LM3S1620 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1620
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1620
+
+//*****************************************************************************
+//
+// LM3S1625 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1625
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_7)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1625
+
+//*****************************************************************************
+//
+// LM3S1626 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1626
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_6)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_5)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM0_PORT (GPIO_PORTA_BASE)
+#define PWM0_PIN (GPIO_PIN_6)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM1_PORT (GPIO_PORTA_BASE)
+#define PWM1_PIN (GPIO_PIN_7)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_4)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_5)
+
+#endif // PART_LM3S1626
+
+//*****************************************************************************
+//
+// LM3S1627 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1627
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_6)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_5)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define IDX0_PORT (GPIO_PORTB_BASE)
+#define IDX0_PIN (GPIO_PIN_4)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM2_PORT (GPIO_PORTD_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM3_PORT (GPIO_PORTD_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1627
+
+//*****************************************************************************
+//
+// LM3S1635 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1635
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1635
+
+//*****************************************************************************
+//
+// LM3S1637 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1637
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1637
+
+//*****************************************************************************
+//
+// LM3S1751 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1751
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1751
+
+//*****************************************************************************
+//
+// LM3S1776 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1776
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT1_PORT (GPIO_PORTB_BASE)
+#define FAULT1_PIN (GPIO_PIN_6)
+
+#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define FAULT2_PORT (GPIO_PORTC_BASE)
+#define FAULT2_PIN (GPIO_PIN_5)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PWM6_PORT (GPIO_PORTC_BASE)
+#define PWM6_PIN (GPIO_PIN_4)
+
+#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PWM7_PORT (GPIO_PORTC_BASE)
+#define PWM7_PIN (GPIO_PIN_6)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1776
+
+//*****************************************************************************
+//
+// LM3S1850 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1850
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1850
+
+//*****************************************************************************
+//
+// LM3S1911 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1911
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1911
+
+//*****************************************************************************
+//
+// LM3S1918 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1918
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1918
+
+//*****************************************************************************
+//
+// LM3S1937 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1937
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S1937
+
+//*****************************************************************************
+//
+// LM3S1958 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1958
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1958
+
+//*****************************************************************************
+//
+// LM3S1960 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1960
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C2O_PORT (GPIO_PORTF_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP4_PORT (GPIO_PORTF_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define IDX1_PORT (GPIO_PORTH_BASE)
+#define IDX1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PHA1_PORT (GPIO_PORTG_BASE)
+#define PHA1_PIN (GPIO_PIN_6)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PHB0_PORT (GPIO_PORTH_BASE)
+#define PHB0_PIN (GPIO_PIN_3)
+
+#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PHB1_PORT (GPIO_PORTG_BASE)
+#define PHB1_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1960
+
+//*****************************************************************************
+//
+// LM3S1968 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S1968
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP3_PORT (GPIO_PORTG_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define FAULT_PORT (GPIO_PORTH_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define IDX1_PORT (GPIO_PORTF_BASE)
+#define IDX1_PIN (GPIO_PIN_1)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PHA1_PORT (GPIO_PORTG_BASE)
+#define PHA1_PIN (GPIO_PIN_6)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PHB1_PORT (GPIO_PORTG_BASE)
+#define PHB1_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM0_PORT (GPIO_PORTG_BASE)
+#define PWM0_PIN (GPIO_PIN_2)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S1968
+
+//*****************************************************************************
+//
+// LM3S2016 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2016
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2016
+
+//*****************************************************************************
+//
+// LM3S2110 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2110
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2110
+
+//*****************************************************************************
+//
+// LM3S2139 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2139
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2139
+
+//*****************************************************************************
+//
+// LM3S2276 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2276
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0RX_PORT (GPIO_PORTB_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0TX_PORT (GPIO_PORTB_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_7)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT1_PORT (GPIO_PORTB_BASE)
+#define FAULT1_PIN (GPIO_PIN_6)
+
+#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define FAULT2_PORT (GPIO_PORTC_BASE)
+#define FAULT2_PIN (GPIO_PIN_5)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PWM6_PORT (GPIO_PORTC_BASE)
+#define PWM6_PIN (GPIO_PIN_4)
+
+#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PWM7_PORT (GPIO_PORTC_BASE)
+#define PWM7_PIN (GPIO_PIN_6)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2276
+
+//*****************************************************************************
+//
+// LM3S2410 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2410
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2410
+
+//*****************************************************************************
+//
+// LM3S2412 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2412
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2412
+
+//*****************************************************************************
+//
+// LM3S2432 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2432
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2432
+
+//*****************************************************************************
+//
+// LM3S2533 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2533
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2533
+
+//*****************************************************************************
+//
+// LM3S2601 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2601
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2601
+
+//*****************************************************************************
+//
+// LM3S2608 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2608
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2608
+
+//*****************************************************************************
+//
+// LM3S2616 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2616
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_7)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_7)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CAN0RX_PORT (GPIO_PORTA_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CAN0TX_PORT (GPIO_PORTA_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM0_PORT (GPIO_PORTA_BASE)
+#define PWM0_PIN (GPIO_PIN_6)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM1_PORT (GPIO_PORTA_BASE)
+#define PWM1_PIN (GPIO_PIN_7)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2616
+
+//*****************************************************************************
+//
+// LM3S2620 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2620
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C2O_PORT (GPIO_PORTE_BASE)
+#define C2O_PIN (GPIO_PIN_7)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PHB0_PORT (GPIO_PORTH_BASE)
+#define PHB0_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM0_PORT (GPIO_PORTG_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM1_PORT (GPIO_PORTG_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM2_PORT (GPIO_PORTD_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM3_PORT (GPIO_PORTD_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2620
+
+//*****************************************************************************
+//
+// LM3S2637 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2637
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2637
+
+//*****************************************************************************
+//
+// LM3S2651 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2651
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2651
+
+//*****************************************************************************
+//
+// LM3S2671 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2671
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_7)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_7)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_5)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_1)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM0_PORT (GPIO_PORTA_BASE)
+#define PWM0_PIN (GPIO_PIN_6)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM1_PORT (GPIO_PORTA_BASE)
+#define PWM1_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2671
+
+//*****************************************************************************
+//
+// LM3S2678 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2678
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_1)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_0)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0RX_PORT (GPIO_PORTB_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0TX_PORT (GPIO_PORTB_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_6)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP1_PORT (GPIO_PORTC_BASE)
+#define CCP1_PIN (GPIO_PIN_5)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT0_PORT (GPIO_PORTB_BASE)
+#define FAULT0_PIN (GPIO_PIN_3)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT1_PORT (GPIO_PORTB_BASE)
+#define FAULT1_PIN (GPIO_PIN_6)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define IDX0_PORT (GPIO_PORTB_BASE)
+#define IDX0_PIN (GPIO_PIN_2)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM0_PORT (GPIO_PORTA_BASE)
+#define PWM0_PIN (GPIO_PIN_6)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM1_PORT (GPIO_PORTA_BASE)
+#define PWM1_PIN (GPIO_PIN_7)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2678
+
+//*****************************************************************************
+//
+// LM3S2730 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2730
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2730
+
+//*****************************************************************************
+//
+// LM3S2739 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2739
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2739
+
+//*****************************************************************************
+//
+// LM3S2776 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2776
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0RX_PORT (GPIO_PORTB_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0TX_PORT (GPIO_PORTB_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_7)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT1_PORT (GPIO_PORTB_BASE)
+#define FAULT1_PIN (GPIO_PIN_6)
+
+#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define FAULT2_PORT (GPIO_PORTC_BASE)
+#define FAULT2_PIN (GPIO_PIN_5)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PWM6_PORT (GPIO_PORTC_BASE)
+#define PWM6_PIN (GPIO_PIN_4)
+
+#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PWM7_PORT (GPIO_PORTC_BASE)
+#define PWM7_PIN (GPIO_PIN_6)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2776
+
+//*****************************************************************************
+//
+// LM3S2911 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2911
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2911
+
+//*****************************************************************************
+//
+// LM3S2918 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2918
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S2918
+
+//*****************************************************************************
+//
+// LM3S2939 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2939
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PHB0_PORT (GPIO_PORTH_BASE)
+#define PHB0_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2939
+
+//*****************************************************************************
+//
+// LM3S2948 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2948
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP3_PORT (GPIO_PORTG_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2948
+
+//*****************************************************************************
+//
+// LM3S2950 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2950
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C2O_PORT (GPIO_PORTF_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP5_PORT (GPIO_PORTE_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PHB0_PORT (GPIO_PORTH_BASE)
+#define PHB0_PIN (GPIO_PIN_3)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM0_PORT (GPIO_PORTG_BASE)
+#define PWM0_PIN (GPIO_PIN_2)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM1_PORT (GPIO_PORTG_BASE)
+#define PWM1_PIN (GPIO_PIN_3)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2950
+
+//*****************************************************************************
+//
+// LM3S2965 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S2965
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP4_PORT (GPIO_PORTD_BASE)
+#define CCP4_PIN (GPIO_PIN_5)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP5_PORT (GPIO_PORTG_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define IDX1_PORT (GPIO_PORTH_BASE)
+#define IDX1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PHA1_PORT (GPIO_PORTG_BASE)
+#define PHA1_PIN (GPIO_PIN_6)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PHB0_PORT (GPIO_PORTH_BASE)
+#define PHB0_PIN (GPIO_PIN_3)
+
+#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PHB1_PORT (GPIO_PORTG_BASE)
+#define PHB1_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM0_PORT (GPIO_PORTG_BASE)
+#define PWM0_PIN (GPIO_PIN_2)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM1_PORT (GPIO_PORTG_BASE)
+#define PWM1_PIN (GPIO_PIN_3)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S2965
+
+//*****************************************************************************
+//
+// LM3S3651 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3651
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_7)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_3)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP5_PORT (GPIO_PORTD_BASE)
+#define CCP5_PIN (GPIO_PIN_2)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP6_PORT (GPIO_PORTD_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP7_PORT (GPIO_PORTD_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0ID_PORT (GPIO_PORTB_BASE)
+#define USB0ID_PIN (GPIO_PIN_0)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0VBUS_PORT (GPIO_PORTB_BASE)
+#define USB0VBUS_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S3651
+
+//*****************************************************************************
+//
+// LM3S3739 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3739
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_6)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP3_PORT (GPIO_PORTG_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP5_PORT (GPIO_PORTD_BASE)
+#define CCP5_PIN (GPIO_PIN_2)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP7_PORT (GPIO_PORTD_BASE)
+#define CCP7_PIN (GPIO_PIN_3)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U2RX_PORT (GPIO_PORTD_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U2TX_PORT (GPIO_PORTD_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0EPEN_PORT (GPIO_PORTH_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_3)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0PFLT_PORT (GPIO_PORTH_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_4)
+
+#endif // PART_LM3S3739
+
+//*****************************************************************************
+//
+// LM3S3748 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3748
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_3)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP2_PORT (GPIO_PORTF_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP3_PORT (GPIO_PORTG_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_4)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP5_PORT (GPIO_PORTD_BASE)
+#define CCP5_PIN (GPIO_PIN_2)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP7_PORT (GPIO_PORTH_BASE)
+#define CCP7_PIN (GPIO_PIN_1)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define FAULT0_PORT (GPIO_PORTF_BASE)
+#define FAULT0_PIN (GPIO_PIN_4)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT1_PORT (GPIO_PORTG_BASE)
+#define FAULT1_PIN (GPIO_PIN_5)
+
+#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT2_PORT (GPIO_PORTG_BASE)
+#define FAULT2_PIN (GPIO_PIN_3)
+
+#define FAULT3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define FAULT3_PORT (GPIO_PORTH_BASE)
+#define FAULT3_PIN (GPIO_PIN_2)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM2_PORT (GPIO_PORTF_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM3_PORT (GPIO_PORTF_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM4_PORT (GPIO_PORTG_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM5_PORT (GPIO_PORTG_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM6_PORT (GPIO_PORTG_BASE)
+#define PWM6_PIN (GPIO_PIN_6)
+
+#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM7_PORT (GPIO_PORTG_BASE)
+#define PWM7_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define U1RX_PORT (GPIO_PORTC_BASE)
+#define U1RX_PIN (GPIO_PIN_6)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define U1TX_PORT (GPIO_PORTC_BASE)
+#define U1TX_PIN (GPIO_PIN_7)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0EPEN_PORT (GPIO_PORTH_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_3)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0PFLT_PORT (GPIO_PORTH_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_4)
+
+#endif // PART_LM3S3748
+
+//*****************************************************************************
+//
+// LM3S3749 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S3749
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_7)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_3)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP2_PORT (GPIO_PORTF_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP3_PORT (GPIO_PORTA_BASE)
+#define CCP3_PIN (GPIO_PIN_7)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP4_PORT (GPIO_PORTF_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP6_PORT (GPIO_PORTD_BASE)
+#define CCP6_PIN (GPIO_PIN_2)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT0_PORT (GPIO_PORTG_BASE)
+#define FAULT0_PIN (GPIO_PIN_2)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT1_PORT (GPIO_PORTG_BASE)
+#define FAULT1_PIN (GPIO_PIN_4)
+
+#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT2_PORT (GPIO_PORTG_BASE)
+#define FAULT2_PIN (GPIO_PIN_3)
+
+#define FAULT3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define FAULT3_PORT (GPIO_PORTH_BASE)
+#define FAULT3_PIN (GPIO_PIN_2)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define I2C1SCL_PORT (GPIO_PORTG_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_0)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define I2C1SDA_PORT (GPIO_PORTG_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_1)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define IDX0_PORT (GPIO_PORTG_BASE)
+#define IDX0_PIN (GPIO_PIN_5)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHA0_PORT (GPIO_PORTF_BASE)
+#define PHA0_PIN (GPIO_PIN_6)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_6)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM6_PORT (GPIO_PORTG_BASE)
+#define PWM6_PIN (GPIO_PIN_6)
+
+#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM7_PORT (GPIO_PORTG_BASE)
+#define PWM7_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U2RX_PORT (GPIO_PORTD_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U2TX_PORT (GPIO_PORTD_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0EPEN_PORT (GPIO_PORTH_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_3)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0PFLT_PORT (GPIO_PORTH_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_4)
+
+#endif // PART_LM3S3749
+
+//*****************************************************************************
+//
+// LM3S5632 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5632
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_5)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#endif // PART_LM3S5632
+
+//*****************************************************************************
+//
+// LM3S5652 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5652
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_5)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP2_PORT (GPIO_PORTE_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP3_PORT (GPIO_PORTA_BASE)
+#define CCP3_PIN (GPIO_PIN_7)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0ID_PORT (GPIO_PORTB_BASE)
+#define USB0ID_PIN (GPIO_PIN_0)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0VBUS_PORT (GPIO_PORTB_BASE)
+#define USB0VBUS_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S5652
+
+//*****************************************************************************
+//
+// LM3S5662 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5662
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0RX_PORT (GPIO_PORTB_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0TX_PORT (GPIO_PORTB_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_2)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT0_PORT (GPIO_PORTB_BASE)
+#define FAULT0_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM2_PORT (GPIO_PORTD_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM3_PORT (GPIO_PORTD_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0ID_PORT (GPIO_PORTB_BASE)
+#define USB0ID_PIN (GPIO_PIN_0)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0VBUS_PORT (GPIO_PORTB_BASE)
+#define USB0VBUS_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S5662
+
+//*****************************************************************************
+//
+// LM3S5732 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5732
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_5)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#endif // PART_LM3S5732
+
+//*****************************************************************************
+//
+// LM3S5737 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5737
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_1)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#endif // PART_LM3S5737
+
+//*****************************************************************************
+//
+// LM3S5739 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5739
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CAN0RX_PORT (GPIO_PORTA_BASE)
+#define CAN0RX_PIN (GPIO_PIN_6)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CAN0TX_PORT (GPIO_PORTA_BASE)
+#define CAN0TX_PIN (GPIO_PIN_7)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP0_PORT (GPIO_PORTC_BASE)
+#define CCP0_PIN (GPIO_PIN_6)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CCP1_PORT (GPIO_PORTF_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define CCP3_PORT (GPIO_PORTG_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP5_PORT (GPIO_PORTD_BASE)
+#define CCP5_PIN (GPIO_PIN_2)
+
+#define CCP6_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define CCP6_PORT (GPIO_PORTH_BASE)
+#define CCP6_PIN (GPIO_PIN_0)
+
+#define CCP7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP7_PORT (GPIO_PORTD_BASE)
+#define CCP7_PIN (GPIO_PIN_3)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define I2C1SCL_PORT (GPIO_PORTG_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_0)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define I2C1SDA_PORT (GPIO_PORTG_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_1)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1RX_PORT (GPIO_PORTB_BASE)
+#define U1RX_PIN (GPIO_PIN_0)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define U1TX_PORT (GPIO_PORTB_BASE)
+#define U1TX_PIN (GPIO_PIN_1)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U2RX_PORT (GPIO_PORTD_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U2TX_PORT (GPIO_PORTD_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0EPEN_PORT (GPIO_PORTH_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_3)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0PFLT_PORT (GPIO_PORTH_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_4)
+
+#endif // PART_LM3S5739
+
+//*****************************************************************************
+//
+// LM3S5747 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5747
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0RX_PORT (GPIO_PORTB_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0TX_PORT (GPIO_PORTB_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT0_PORT (GPIO_PORTE_BASE)
+#define FAULT0_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM2_PORT (GPIO_PORTD_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM3_PORT (GPIO_PORTD_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#endif // PART_LM3S5747
+
+//*****************************************************************************
+//
+// LM3S5749 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5749
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_7)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_6)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_5)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_4)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_7)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_6)
+
+#define ADC6_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC6_PORT (GPIO_PORTD_BASE)
+#define ADC6_PIN (GPIO_PIN_5)
+
+#define ADC7_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC7_PORT (GPIO_PORTD_BASE)
+#define ADC7_PIN (GPIO_PIN_4)
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C0O_PORT (GPIO_PORTF_BASE)
+#define C0O_PIN (GPIO_PIN_4)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define C1O_PORT (GPIO_PORTF_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_1)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT0_PORT (GPIO_PORTG_BASE)
+#define FAULT0_PIN (GPIO_PIN_2)
+
+#define FAULT1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT1_PORT (GPIO_PORTG_BASE)
+#define FAULT1_PIN (GPIO_PIN_4)
+
+#define FAULT2_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define FAULT2_PORT (GPIO_PORTG_BASE)
+#define FAULT2_PIN (GPIO_PIN_3)
+
+#define FAULT3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define FAULT3_PORT (GPIO_PORTH_BASE)
+#define FAULT3_PIN (GPIO_PIN_2)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define IDX0_PORT (GPIO_PORTG_BASE)
+#define IDX0_PIN (GPIO_PIN_5)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHA0_PORT (GPIO_PORTF_BASE)
+#define PHA0_PIN (GPIO_PIN_6)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM0_PORT (GPIO_PORTG_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM1_PORT (GPIO_PORTG_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM2_PORT (GPIO_PORTH_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define PWM3_PORT (GPIO_PORTH_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM4_PORT (GPIO_PORTF_BASE)
+#define PWM4_PIN (GPIO_PIN_2)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM5_PORT (GPIO_PORTF_BASE)
+#define PWM5_PIN (GPIO_PIN_3)
+
+#define PWM6_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM6_PORT (GPIO_PORTG_BASE)
+#define PWM6_PIN (GPIO_PIN_6)
+
+#define PWM7_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM7_PORT (GPIO_PORTG_BASE)
+#define PWM7_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0EPEN_PORT (GPIO_PORTH_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_3)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOH)
+#define USB0PFLT_PORT (GPIO_PORTH_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_4)
+
+#endif // PART_LM3S5749
+
+//*****************************************************************************
+//
+// LM3S5752 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5752
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define ADC4_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC4_PORT (GPIO_PORTD_BASE)
+#define ADC4_PIN (GPIO_PIN_3)
+
+#define ADC5_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define ADC5_PORT (GPIO_PORTD_BASE)
+#define ADC5_PIN (GPIO_PIN_2)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_5)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP2_PORT (GPIO_PORTE_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP3_PORT (GPIO_PORTA_BASE)
+#define CCP3_PIN (GPIO_PIN_7)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0ID_PORT (GPIO_PORTB_BASE)
+#define USB0ID_PIN (GPIO_PIN_0)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0VBUS_PORT (GPIO_PORTB_BASE)
+#define USB0VBUS_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S5752
+
+//*****************************************************************************
+//
+// LM3S5762 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S5762
+
+#define ADC0_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC0_PORT (GPIO_PORTE_BASE)
+#define ADC0_PIN (GPIO_PIN_3)
+
+#define ADC1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC1_PORT (GPIO_PORTE_BASE)
+#define ADC1_PIN (GPIO_PIN_2)
+
+#define ADC2_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC2_PORT (GPIO_PORTE_BASE)
+#define ADC2_PIN (GPIO_PIN_1)
+
+#define ADC3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define ADC3_PORT (GPIO_PORTE_BASE)
+#define ADC3_PIN (GPIO_PIN_0)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0RX_PORT (GPIO_PORTB_BASE)
+#define CAN0RX_PIN (GPIO_PIN_4)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CAN0TX_PORT (GPIO_PORTB_BASE)
+#define CAN0TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_2)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP1_PORT (GPIO_PORTB_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP2_PORT (GPIO_PORTC_BASE)
+#define CCP2_PIN (GPIO_PIN_4)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define FAULT0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT0_PORT (GPIO_PORTB_BASE)
+#define FAULT0_PIN (GPIO_PIN_3)
+
+#define NMI_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define NMI_PORT (GPIO_PORTB_BASE)
+#define NMI_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM2_PORT (GPIO_PORTD_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM3_PORT (GPIO_PORTD_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM4_PORT (GPIO_PORTA_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define PWM5_PORT (GPIO_PORTA_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define USB0EPEN_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0EPEN_PORT (GPIO_PORTC_BASE)
+#define USB0EPEN_PIN (GPIO_PIN_5)
+
+#define USB0ID_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0ID_PORT (GPIO_PORTB_BASE)
+#define USB0ID_PIN (GPIO_PIN_0)
+
+#define USB0PFLT_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define USB0PFLT_PORT (GPIO_PORTC_BASE)
+#define USB0PFLT_PIN (GPIO_PIN_6)
+
+#define USB0VBUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define USB0VBUS_PORT (GPIO_PORTB_BASE)
+#define USB0VBUS_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S5762
+
+//*****************************************************************************
+//
+// LM3S6100 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6100
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6100
+
+//*****************************************************************************
+//
+// LM3S6110 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6110
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6110
+
+//*****************************************************************************
+//
+// LM3S6420 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6420
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6420
+
+//*****************************************************************************
+//
+// LM3S6422 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6422
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6422
+
+//*****************************************************************************
+//
+// LM3S6432 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6432
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6432
+
+//*****************************************************************************
+//
+// LM3S6537 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6537
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6537
+
+//*****************************************************************************
+//
+// LM3S6610 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6610
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C2O_PORT (GPIO_PORTE_BASE)
+#define C2O_PIN (GPIO_PIN_7)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_0)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6610
+
+//*****************************************************************************
+//
+// LM3S6611 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6611
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6611
+
+//*****************************************************************************
+//
+// LM3S6618 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6618
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define I2C1SCL_PORT (GPIO_PORTG_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_0)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6618
+
+//*****************************************************************************
+//
+// LM3S6633 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6633
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6633
+
+//*****************************************************************************
+//
+// LM3S6637 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6637
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6637
+
+//*****************************************************************************
+//
+// LM3S6730 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6730
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6730
+
+//*****************************************************************************
+//
+// LM3S6753 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6753
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6753
+
+//*****************************************************************************
+//
+// LM3S6816 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6816
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT_PORT (GPIO_PORTE_BASE)
+#define FAULT_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6816
+
+//*****************************************************************************
+//
+// LM3S6911 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6911
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define C1O_PORT (GPIO_PORTE_BASE)
+#define C1O_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6911
+
+//*****************************************************************************
+//
+// LM3S6916 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6916
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define FAULT_PORT (GPIO_PORTE_BASE)
+#define FAULT_PIN (GPIO_PIN_1)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6916
+
+//*****************************************************************************
+//
+// LM3S6918 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6918
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP4_PORT (GPIO_PORTC_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define I2C1SCL_PORT (GPIO_PORTG_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_0)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S6918
+
+//*****************************************************************************
+//
+// LM3S6938 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6938
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_0)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6938
+
+//*****************************************************************************
+//
+// LM3S6950 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6950
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PHA0_PORT (GPIO_PORTD_BASE)
+#define PHA0_PIN (GPIO_PIN_1)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_6)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_7)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6950
+
+//*****************************************************************************
+//
+// LM3S6952 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6952
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_0)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PHB0_PORT (GPIO_PORTF_BASE)
+#define PHB0_PIN (GPIO_PIN_0)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM0_PORT (GPIO_PORTD_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6952
+
+//*****************************************************************************
+//
+// LM3S6965 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S6965
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP1_PORT (GPIO_PORTD_BASE)
+#define CCP1_PIN (GPIO_PIN_7)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP2_PORT (GPIO_PORTD_BASE)
+#define CCP2_PIN (GPIO_PIN_5)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_0)
+
+#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define IDX1_PORT (GPIO_PORTF_BASE)
+#define IDX1_PIN (GPIO_PIN_1)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PHA1_PORT (GPIO_PORTE_BASE)
+#define PHA1_PIN (GPIO_PIN_3)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PHB1_PORT (GPIO_PORTE_BASE)
+#define PHB1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM1_PORT (GPIO_PORTD_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S6965
+
+//*****************************************************************************
+//
+// LM3S8530 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8530
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CAN2RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CAN2RX_PORT (GPIO_PORTE_BASE)
+#define CAN2RX_PIN (GPIO_PIN_4)
+
+#define CAN2TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CAN2TX_PORT (GPIO_PORTE_BASE)
+#define CAN2TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S8530
+
+//*****************************************************************************
+//
+// LM3S8538 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8538
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_0)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8538
+
+//*****************************************************************************
+//
+// LM3S8630 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8630
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8630
+
+//*****************************************************************************
+//
+// LM3S8730 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8730
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8730
+
+//*****************************************************************************
+//
+// LM3S8733 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8733
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8733
+
+//*****************************************************************************
+//
+// LM3S8738 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8738
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S8738
+
+//*****************************************************************************
+//
+// LM3S8930 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8930
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S8930
+
+//*****************************************************************************
+//
+// LM3S8933 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8933
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define C0O_PORT (GPIO_PORTD_BASE)
+#define C0O_PIN (GPIO_PIN_7)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP3_PORT (GPIO_PORTD_BASE)
+#define CCP3_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8933
+
+//*****************************************************************************
+//
+// LM3S8938 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8938
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_6)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define C1O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1O_PORT (GPIO_PORTC_BASE)
+#define C1O_PIN (GPIO_PIN_5)
+
+#define C1_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C1_MINUS_PORT (GPIO_PORTB_BASE)
+#define C1_MINUS_PIN (GPIO_PIN_5)
+
+#define C1_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C1_PLUS_PORT (GPIO_PORTC_BASE)
+#define C1_PLUS_PIN (GPIO_PIN_5)
+
+#define C2O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2O_PORT (GPIO_PORTC_BASE)
+#define C2O_PIN (GPIO_PIN_6)
+
+#define C2_MINUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_MINUS_PORT (GPIO_PORTC_BASE)
+#define C2_MINUS_PIN (GPIO_PIN_7)
+
+#define C2_PLUS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C2_PLUS_PORT (GPIO_PORTC_BASE)
+#define C2_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP1_PORT (GPIO_PORTE_BASE)
+#define CCP1_PIN (GPIO_PIN_3)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP3_PORT (GPIO_PORTE_BASE)
+#define CCP3_PIN (GPIO_PIN_0)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CCP4_PORT (GPIO_PORTE_BASE)
+#define CCP4_PIN (GPIO_PIN_2)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP5_PORT (GPIO_PORTC_BASE)
+#define CCP5_PIN (GPIO_PIN_4)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define I2C1SCL_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SCL_PORT (GPIO_PORTA_BASE)
+#define I2C1SCL_PIN (GPIO_PIN_6)
+
+#define I2C1SDA_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define I2C1SDA_PORT (GPIO_PORTA_BASE)
+#define I2C1SDA_PIN (GPIO_PIN_7)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#define U2RX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2RX_PORT (GPIO_PORTG_BASE)
+#define U2RX_PIN (GPIO_PIN_0)
+
+#define U2TX_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define U2TX_PORT (GPIO_PORTG_BASE)
+#define U2TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S8938
+
+//*****************************************************************************
+//
+// LM3S8962 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8962
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0O_PORT (GPIO_PORTB_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CCP0_PORT (GPIO_PORTD_BASE)
+#define CCP0_PIN (GPIO_PIN_4)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define FAULT_PORT (GPIO_PORTD_BASE)
+#define FAULT_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define IDX0_PORT (GPIO_PORTD_BASE)
+#define IDX0_PIN (GPIO_PIN_7)
+
+#define IDX1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define IDX1_PORT (GPIO_PORTF_BASE)
+#define IDX1_PIN (GPIO_PIN_1)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHA1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PHA1_PORT (GPIO_PORTE_BASE)
+#define PHA1_PIN (GPIO_PIN_3)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_6)
+
+#define PHB1_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PHB1_PORT (GPIO_PORTE_BASE)
+#define PHB1_PIN (GPIO_PIN_2)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOG)
+#define PWM1_PORT (GPIO_PORTG_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM2_PORT (GPIO_PORTB_BASE)
+#define PWM2_PIN (GPIO_PIN_0)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define PWM3_PORT (GPIO_PORTB_BASE)
+#define PWM3_PIN (GPIO_PIN_1)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8962
+
+//*****************************************************************************
+//
+// LM3S8970 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8970
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CAN1RX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1RX_PORT (GPIO_PORTF_BASE)
+#define CAN1RX_PIN (GPIO_PIN_0)
+
+#define CAN1TX_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define CAN1TX_PORT (GPIO_PORTF_BASE)
+#define CAN1TX_PIN (GPIO_PIN_1)
+
+#define CAN2RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CAN2RX_PORT (GPIO_PORTE_BASE)
+#define CAN2RX_PIN (GPIO_PIN_4)
+
+#define CAN2TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define CAN2TX_PORT (GPIO_PORTE_BASE)
+#define CAN2TX_PIN (GPIO_PIN_5)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define I2C0SCL_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SCL_PORT (GPIO_PORTB_BASE)
+#define I2C0SCL_PIN (GPIO_PIN_2)
+
+#define I2C0SDA_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define I2C0SDA_PORT (GPIO_PORTB_BASE)
+#define I2C0SDA_PIN (GPIO_PIN_3)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SSI1CLK_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1CLK_PORT (GPIO_PORTE_BASE)
+#define SSI1CLK_PIN (GPIO_PIN_0)
+
+#define SSI1FSS_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1FSS_PORT (GPIO_PORTE_BASE)
+#define SSI1FSS_PIN (GPIO_PIN_1)
+
+#define SSI1RX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1RX_PORT (GPIO_PORTE_BASE)
+#define SSI1RX_PIN (GPIO_PIN_2)
+
+#define SSI1TX_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define SSI1TX_PORT (GPIO_PORTE_BASE)
+#define SSI1TX_PIN (GPIO_PIN_3)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#define U1RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1RX_PORT (GPIO_PORTD_BASE)
+#define U1RX_PIN (GPIO_PIN_2)
+
+#define U1TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define U1TX_PORT (GPIO_PORTD_BASE)
+#define U1TX_PIN (GPIO_PIN_3)
+
+#endif // PART_LM3S8970
+
+//*****************************************************************************
+//
+// LM3S8971 Port/Pin Mapping Definitions
+//
+//*****************************************************************************
+#ifdef PART_LM3S8971
+
+#define C0O_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define C0O_PORT (GPIO_PORTC_BASE)
+#define C0O_PIN (GPIO_PIN_5)
+
+#define C0_MINUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_MINUS_PORT (GPIO_PORTB_BASE)
+#define C0_MINUS_PIN (GPIO_PIN_4)
+
+#define C0_PLUS_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define C0_PLUS_PORT (GPIO_PORTB_BASE)
+#define C0_PLUS_PIN (GPIO_PIN_6)
+
+#define CAN0RX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0RX_PORT (GPIO_PORTD_BASE)
+#define CAN0RX_PIN (GPIO_PIN_0)
+
+#define CAN0TX_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define CAN0TX_PORT (GPIO_PORTD_BASE)
+#define CAN0TX_PIN (GPIO_PIN_1)
+
+#define CCP0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP0_PORT (GPIO_PORTB_BASE)
+#define CCP0_PIN (GPIO_PIN_0)
+
+#define CCP1_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP1_PORT (GPIO_PORTA_BASE)
+#define CCP1_PIN (GPIO_PIN_6)
+
+#define CCP2_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP2_PORT (GPIO_PORTB_BASE)
+#define CCP2_PIN (GPIO_PIN_1)
+
+#define CCP3_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define CCP3_PORT (GPIO_PORTC_BASE)
+#define CCP3_PIN (GPIO_PIN_6)
+
+#define CCP4_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define CCP4_PORT (GPIO_PORTA_BASE)
+#define CCP4_PIN (GPIO_PIN_7)
+
+#define CCP5_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define CCP5_PORT (GPIO_PORTB_BASE)
+#define CCP5_PIN (GPIO_PIN_5)
+
+#define FAULT_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define FAULT_PORT (GPIO_PORTB_BASE)
+#define FAULT_PIN (GPIO_PIN_3)
+
+#define IDX0_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define IDX0_PORT (GPIO_PORTB_BASE)
+#define IDX0_PIN (GPIO_PIN_2)
+
+#define LED0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED0_PORT (GPIO_PORTF_BASE)
+#define LED0_PIN (GPIO_PIN_3)
+
+#define LED1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define LED1_PORT (GPIO_PORTF_BASE)
+#define LED1_PIN (GPIO_PIN_2)
+
+#define PHA0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHA0_PORT (GPIO_PORTC_BASE)
+#define PHA0_PIN (GPIO_PIN_4)
+
+#define PHB0_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define PHB0_PORT (GPIO_PORTC_BASE)
+#define PHB0_PIN (GPIO_PIN_7)
+
+#define PWM0_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM0_PORT (GPIO_PORTF_BASE)
+#define PWM0_PIN (GPIO_PIN_0)
+
+#define PWM1_PERIPH (SYSCTL_PERIPH_GPIOF)
+#define PWM1_PORT (GPIO_PORTF_BASE)
+#define PWM1_PIN (GPIO_PIN_1)
+
+#define PWM2_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM2_PORT (GPIO_PORTD_BASE)
+#define PWM2_PIN (GPIO_PIN_2)
+
+#define PWM3_PERIPH (SYSCTL_PERIPH_GPIOD)
+#define PWM3_PORT (GPIO_PORTD_BASE)
+#define PWM3_PIN (GPIO_PIN_3)
+
+#define PWM4_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM4_PORT (GPIO_PORTE_BASE)
+#define PWM4_PIN (GPIO_PIN_0)
+
+#define PWM5_PERIPH (SYSCTL_PERIPH_GPIOE)
+#define PWM5_PORT (GPIO_PORTE_BASE)
+#define PWM5_PIN (GPIO_PIN_1)
+
+#define SSI0CLK_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0CLK_PORT (GPIO_PORTA_BASE)
+#define SSI0CLK_PIN (GPIO_PIN_2)
+
+#define SSI0FSS_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0FSS_PORT (GPIO_PORTA_BASE)
+#define SSI0FSS_PIN (GPIO_PIN_3)
+
+#define SSI0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0RX_PORT (GPIO_PORTA_BASE)
+#define SSI0RX_PIN (GPIO_PIN_4)
+
+#define SSI0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define SSI0TX_PORT (GPIO_PORTA_BASE)
+#define SSI0TX_PIN (GPIO_PIN_5)
+
+#define SWCLK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWCLK_PORT (GPIO_PORTC_BASE)
+#define SWCLK_PIN (GPIO_PIN_0)
+
+#define SWDIO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWDIO_PORT (GPIO_PORTC_BASE)
+#define SWDIO_PIN (GPIO_PIN_1)
+
+#define SWO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define SWO_PORT (GPIO_PORTC_BASE)
+#define SWO_PIN (GPIO_PIN_3)
+
+#define TCK_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TCK_PORT (GPIO_PORTC_BASE)
+#define TCK_PIN (GPIO_PIN_0)
+
+#define TDI_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDI_PORT (GPIO_PORTC_BASE)
+#define TDI_PIN (GPIO_PIN_2)
+
+#define TDO_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TDO_PORT (GPIO_PORTC_BASE)
+#define TDO_PIN (GPIO_PIN_3)
+
+#define TMS_PERIPH (SYSCTL_PERIPH_GPIOC)
+#define TMS_PORT (GPIO_PORTC_BASE)
+#define TMS_PIN (GPIO_PIN_1)
+
+#define TRST_PERIPH (SYSCTL_PERIPH_GPIOB)
+#define TRST_PORT (GPIO_PORTB_BASE)
+#define TRST_PIN (GPIO_PIN_7)
+
+#define U0RX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0RX_PORT (GPIO_PORTA_BASE)
+#define U0RX_PIN (GPIO_PIN_0)
+
+#define U0TX_PERIPH (SYSCTL_PERIPH_GPIOA)
+#define U0TX_PORT (GPIO_PORTA_BASE)
+#define U0TX_PIN (GPIO_PIN_1)
+
+#endif // PART_LM3S8971
+
+//*****************************************************************************
+//
+// Pin Mapping Functions
+//
+// This section describes the code that is responsible for handling the
+// mapping of peripheral functions to their physical location on the pins of
+// a device.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Definitions to support mapping GPIO Ports and Pins to their function.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Configures the specified ADC pin to function as an ADC pin.
+//
+// \param ulName is one of the valid names for the ADC pins.
+//
+// This function takes on of the valid names for an ADC pin and configures
+// the pin for its ADC functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b ADC0, \b ADC1, \b ADC2,
+// \b ADC3, \b ADC4, \b ADC5, \b ADC6, or \b ADC7.
+//
+// \sa GPIOPinTypeADC() in order to configure multiple ADC pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeADC(ulName) GPIOPinTypeADC(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified CAN pin to function as a CAN pin.
+//
+// \param ulName is one of the valid names for the CAN pins.
+//
+// This function takes one of the valid names for a CAN pin and configures
+// the pin for its CAN functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b CAN0RX, \b CAN0TX,
+// \b CAN1RX, \b CAN1TX, \b CAN2RX, or \b CAN2TX.
+//
+// \sa GPIOPinTypeCAN() in order to configure multiple CAN pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeCAN(ulName) GPIOPinTypeCAN(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified comparator pin to function as a comparator pin.
+//
+// \param ulName is one of the valid names for the Comparator pins.
+//
+// This function takes one of the valid names for a comparator pin and
+// configures the pin for its comparator functionality depending on the part
+// that is defined.
+//
+// The valid names for the pins are as follows: \b C0_MINUS, \b C0_PLUS,
+// \b C1_MINUS, \b C1_PLUS, \b C2_MINUS, or \b C2_PLUS.
+//
+// \sa GPIOPinTypeComparator() in order to configure multiple comparator pins
+// at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeComparator(ulName) \
+ GPIOPinTypeComparator(ulName##_PORT, \
+ ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified I2C pin to function as an I2C pin.
+//
+// \param ulName is one of the valid names for the I2C pins.
+//
+// This function takes one of the valid names for an I2C pin and configures
+// the pin for its I2C functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b I2C0SCL, \b I2C0SDA,
+// \b I2C1SCL, or \b I2C1SDA.
+//
+// \sa GPIOPinTypeI2C() in order to configure multiple I2C pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeI2C(ulName) GPIOPinTypeI2C(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified PWM pin to function as a PWM pin.
+//
+// \param ulName is one of the valid names for the PWM pins.
+//
+// This function takes one of the valid names for a PWM pin and configures
+// the pin for its PWM functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b PWM0, \b PWM1, \b PWM2,
+// \b PWM3, \b PWM4, \b PWM5, or \b FAULT.
+//
+// \sa GPIOPinTypePWM() in order to configure multiple PWM pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypePWM(ulName) GPIOPinTypePWM(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified QEI pin to function as a QEI pin.
+//
+// \param ulName is one of the valid names for the QEI pins.
+//
+// This function takes one of the valid names for a QEI pin and configures
+// the pin for its QEI functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b PHA0, \b PHB0, \b IDX0,
+// \b PHA1, \b PHB1, or \b IDX1.
+//
+// \sa GPIOPinTypeQEI() in order to configure multiple QEI pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeQEI(ulName) GPIOPinTypeQEI(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified SSI pin to function as an SSI pin.
+//
+// \param ulName is one of the valid names for the SSI pins.
+//
+// This function takes one of the valid names for an SSI pin and configures
+// the pin for its SSI functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b SSI0CLK, \b SSI0FSS,
+// \b SSI0RX, \b SSI0TX, \b SSI1CLK, \b SSI1FSS, \b SSI1RX, or \b SSI1TX.
+//
+// \sa GPIOPinTypeSSI() in order to configure multiple SSI pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeSSI(ulName) GPIOPinTypeSSI(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified Timer pin to function as a Timer pin.
+//
+// \param ulName is one of the valid names for the Timer pins.
+//
+// This function takes one of the valid names for a Timer pin and configures
+// the pin for its Timer functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b CCP0, \b CCP1, \b CCP2,
+// \b CCP3, \b CCP4, \b CCP5, \b CCP6, or \b CCP7.
+//
+// \sa GPIOPinTypeTimer() in order to configure multiple CCP pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeTimer(ulName) GPIOPinTypeTimer(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+// Configures the specified UART pin to function as a UART pin.
+//
+// \param ulName is one of the valid names for the UART pins.
+//
+// This function takes one of the valid names for a UART pin and configures
+// the pin for its UART functionality depending on the part that is defined.
+//
+// The valid names for the pins are as follows: \b U0RX, \b U0TX, \b U1RX,
+// \b U1TX, \b U2RX, or \b U2TX.
+//
+// \sa GPIOPinTypeUART() in order to configure multiple UART pins at once.
+//
+// \return None.
+//
+//*****************************************************************************
+#define PinTypeUART(ulName) GPIOPinTypeUART(ulName##_PORT, ulName##_PIN)
+
+//*****************************************************************************
+//
+//! Configures the specified USB digital pin to function as a USB pin.
+//!
+//! \param ulName is one of the valid names for a USB digital pin.
+//!
+//! This function takes one of the valid names for a USB digital pin and
+//! configures the pin for its USB functionality depending on the part that is
+//! defined.
+//!
+//! The valid names for the pins are as follows: \b EPEN or \b PFAULT.
+//!
+//! \sa GPIOPinTypeUSBDigital() in order to configure multiple USB pins at
+//! once.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define PinTypeUSBDigital(ulName) \
+ GPIOPinTypeUSBDigital(ulName##_PORT, \
+ ulName##_PIN)
+
+//*****************************************************************************
+//
+//! Enables the peripheral port used by the given pin.
+//!
+//! \param ulName is one of the valid names for a pin.
+//!
+//! This function takes one of the valid names for a pin function and
+//! enables the peripheral port for that pin depending on the part that is
+//! defined.
+//!
+//! Any valid pin name can be used.
+//!
+//! \sa SysCtlPeripheralEnable() in order to enable a single port when
+//! multiple pins are on the same port.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#define PeripheralEnable(ulName) \
+ SysCtlPeripheralEnable(ulName##_PERIPH)
+
+#endif // __PIN_MAP_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/pwm.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/pwm.c
new file mode 100644
index 00000000..5f82c487
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/pwm.c
@@ -0,0 +1,1748 @@
+//*****************************************************************************
+//
+// pwm.c - API for the PWM modules
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup pwm_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_pwm.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/pwm.h"
+
+//*****************************************************************************
+//
+// Misc macros for manipulating the encoded generator and output defines used
+// by the API.
+//
+//*****************************************************************************
+#define PWM_GEN_BADDR(_mod_, _gen_) \
+ ((_mod_) + (_gen_))
+#define PWM_GEN_EXT_BADDR(_mod_, _gen_) \
+ ((_mod_) + PWM_GEN_EXT_0 + \
+ ((_gen_) - PWM_GEN_0) * 2)
+#define PWM_OUT_BADDR(_mod_, _out_) \
+ ((_mod_) + ((_out_) & 0xFFFFFFC0))
+#define PWM_IS_OUTPUT_ODD(_out_) \
+ ((_out_) & 0x00000001)
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a PWM generator number.
+//!
+//! \param ulGen is the generator number.
+//!
+//! This function determines if a PWM generator number is valid.
+//!
+//! \return Returnes \b true if the generator number is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+PWMGenValid(unsigned long ulGen)
+{
+ return((ulGen == PWM_GEN_0) || (ulGen == PWM_GEN_1) ||
+ (ulGen == PWM_GEN_2) || (ulGen == PWM_GEN_3));
+}
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a PWM output number.
+//!
+//! \param ulPWMOut is the output number.
+//!
+//! This function determines if a PWM output number is valid.
+//!
+//! \return Returns \b true if the output number is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+PWMOutValid(unsigned long ulPWMOut)
+{
+ return((ulPWMOut == PWM_OUT_0) || (ulPWMOut == PWM_OUT_1) ||
+ (ulPWMOut == PWM_OUT_2) || (ulPWMOut == PWM_OUT_3) ||
+ (ulPWMOut == PWM_OUT_4) || (ulPWMOut == PWM_OUT_5) ||
+ (ulPWMOut == PWM_OUT_6) || (ulPWMOut == PWM_OUT_7));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Configures a PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to configure. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulConfig is the configuration for the PWM generator.
+//!
+//! This function is used to set the mode of operation for a PWM generator.
+//! The counting mode, synchronization mode, and debug behavior are all
+//! configured. After configuration, the generator is left in the disabled
+//! state.
+//!
+//! A PWM generator can count in two different modes: count down mode or count
+//! up/down mode. In count down mode, it will count from a value down to zero,
+//! and then reset to the preset value. This will produce left-aligned PWM
+//! signals (that is the rising edge of the two PWM signals produced by the
+//! generator will occur at the same time). In count up/down mode, it will
+//! count up from zero to the preset value, count back down to zero, and then
+//! repeat the process. This will produce center-aligned PWM signals (that is,
+//! the middle of the high/low period of the PWM signals produced by the
+//! generator will occur at the same time).
+//!
+//! When the PWM generator parameters (period and pulse width) are modified,
+//! their affect on the output PWM signals can be delayed. In synchronous
+//! mode, the parameter updates are not applied until a synchronization event
+//! occurs. This allows multiple parameters to be modified and take affect
+//! simultaneously, instead of one at a time. Additionally, parameters to
+//! multiple PWM generators in synchronous mode can be updated simultaneously,
+//! allowing them to be treated as if they were a unified generator. In
+//! non-synchronous mode, the parameter updates are not delayed until a
+//! synchronization event. In either mode, the parameter updates only occur
+//! when the counter is at zero to help prevent oddly formed PWM signals during
+//! the update (that is, a PWM pulse that is too short or too long).
+//!
+//! The PWM generator can either pause or continue running when the processor
+//! is stopped via the debugger. If configured to pause, it will continue to
+//! count until it reaches zero, at which point it will pause until the
+//! processor is restarted. If configured to continue running, it will keep
+//! counting as if nothing had happened.
+//!
+//! The \e ulConfig parameter contains the desired configuration. It is the
+//! logical OR of the following:
+//!
+//! - \b PWM_GEN_MODE_DOWN or \b PWM_GEN_MODE_UP_DOWN to specify the counting
+//! mode
+//! - \b PWM_GEN_MODE_SYNC or \b PWM_GEN_MODE_NO_SYNC to specify the counter
+//! load and comparator update synchronization mode
+//! - \b PWM_GEN_MODE_DBG_RUN or \b PWM_GEN_MODE_DBG_STOP to specify the debug
+//! behavior
+//! - \b PWM_GEN_MODE_GEN_NO_SYNC, \b PWM_GEN_MODE_GEN_SYNC_LOCAL, or
+//! \b PWM_GEN_MODE_GEN_SYNC_GLOBAL to specify the update synchronization
+//! mode for generator counting mode changes
+//! - \b PWM_GEN_MODE_DB_NO_SYNC, \b PWM_GEN_MODE_DB_SYNC_LOCAL, or
+//! \b PWM_GEN_MODE_DB_SYNC_GLOBAL to specify the deadband parameter
+//! synchronization mode
+//! - \b PWM_GEN_MODE_FAULT_LATCHED or \b PWM_GEN_MODE_FAULT_UNLATCHED to
+//! specify whether fault conditions are latched or not
+//! - \b PWM_GEN_MODE_FAULT_MINPER or \b PWM_GEN_MODE_FAULT_NO_MINPER to
+//! specify whether minimum fault period support is required
+//! - \b PWM_GEN_MODE_FAULT_EXT or \b PWM_GEN_MODE_FAULT_LEGACY to specify
+//! whether extended fault source selection support is enabled or not
+//!
+//! Setting \b PWM_GEN_MODE_FAULT_MINPER allows an application to set the
+//! minimum duration of a PWM fault signal. Fault will be signaled for at
+//! least this time even if the external fault pin deasserts earlier. Care
+//! should be taken when using this mode since during the fault signal period,
+//! the fault interrupt from the PWM generator will remain asserted. The fault
+//! interrupt handler may, therefore, reenter immediately if it exits prior to
+//! expiration of the fault timer.
+//!
+//! \note Changes to the counter mode will affect the period of the PWM signals
+//! produced. PWMGenPeriodSet() and PWMPulseWidthSet() should be called after
+//! any changes to the counter mode of a generator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Change the global configuration of the generator.
+ //
+ HWREG(ulGen + PWM_O_X_CTL) = ((HWREG(ulGen + PWM_O_X_CTL) &
+ ~(PWM_X_CTL_MODE | PWM_X_CTL_DEBUG |
+ PWM_X_CTL_LATCH | PWM_X_CTL_MINFLTPER |
+ PWM_X_CTL_FLTSRC | PWM_X_CTL_DBFALLUPD_M |
+ PWM_X_CTL_DBRISEUPD_M |
+ PWM_X_CTL_DBCTLUPD_M |
+ PWM_X_CTL_GENBUPD_M |
+ PWM_X_CTL_GENAUPD_M |
+ PWM_X_CTL_LOADUPD | PWM_X_CTL_CMPAUPD |
+ PWM_X_CTL_CMPBUPD)) | ulConfig);
+
+ //
+ // Set the individual PWM generator controls.
+ //
+ if(ulConfig & PWM_X_CTL_MODE)
+ {
+ //
+ // In up/down count mode, set the signal high on up count comparison
+ // and low on down count comparison (that is, center align the
+ // signals).
+ //
+ HWREG(ulGen + PWM_O_X_GENA) = (PWM_X_GENA_ACTCMPAU_ONE |
+ PWM_X_GENA_ACTCMPAD_ZERO);
+ HWREG(ulGen + PWM_O_X_GENB) = (PWM_X_GENB_ACTCMPBU_ONE |
+ PWM_X_GENB_ACTCMPBD_ZERO);
+ }
+ else
+ {
+ //
+ // In down count mode, set the signal high on load and low on count
+ // comparison (that is, left align the signals).
+ //
+ HWREG(ulGen + PWM_O_X_GENA) = (PWM_X_GENA_ACTLOAD_ONE |
+ PWM_X_GENA_ACTCMPAD_ZERO);
+ HWREG(ulGen + PWM_O_X_GENB) = (PWM_X_GENB_ACTLOAD_ONE |
+ PWM_X_GENB_ACTCMPBD_ZERO);
+ }
+}
+
+//*****************************************************************************
+//
+//! Set the period of a PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to be modified. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulPeriod specifies the period of PWM generator output, measured
+//! in clock ticks.
+//!
+//! This function sets the period of the specified PWM generator block, where
+//! the period of the generator block is defined as the number of PWM clock
+//! ticks between pulses on the generator block zero signal.
+//!
+//! \note Any subsequent calls made to this function before an update occurs
+//! will cause the previous values to be overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulPeriod)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Set the reload register based on the mode.
+ //
+ if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+ {
+ //
+ // In up/down count mode, set the reload register to half the requested
+ // period.
+ //
+ ASSERT((ulPeriod / 2) < 65536);
+ HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod / 2;
+ }
+ else
+ {
+ //
+ // In down count mode, set the reload register to the requested period
+ // minus one.
+ //
+ ASSERT((ulPeriod <= 65536) && (ulPeriod != 0));
+ HWREG(ulGen + PWM_O_X_LOAD) = ulPeriod - 1;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the period of a PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to query. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function gets the period of the specified PWM generator block. The
+//! period of the generator block is defined as the number of PWM clock ticks
+//! between pulses on the generator block zero signal.
+//!
+//! If the update of the counter for the specified PWM generator has yet
+//! to be completed, the value returned may not be the active period. The
+//! value returned is the programmed period, measured in PWM clock ticks.
+//!
+//! \return Returns the programmed period of the specified generator block
+//! in PWM clock ticks.
+//
+//*****************************************************************************
+unsigned long
+PWMGenPeriodGet(unsigned long ulBase, unsigned long ulGen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Figure out the counter mode.
+ //
+ if(HWREG(ulGen + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+ {
+ //
+ // The period is twice the reload register value.
+ //
+ return(HWREG(ulGen + PWM_O_X_LOAD) * 2);
+ }
+ else
+ {
+ //
+ // The period is the reload register value plus one.
+ //
+ return(HWREG(ulGen + PWM_O_X_LOAD) + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables the timer/counter for a PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to be enabled. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function allows the PWM clock to drive the timer/counter for the
+//! specified generator block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenEnable(unsigned long ulBase, unsigned long ulGen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Enable the PWM generator.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_CTL) |= PWM_X_CTL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the timer/counter for a PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to be disabled. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function blocks the PWM clock from driving the timer/counter for the
+//! specified generator block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenDisable(unsigned long ulBase, unsigned long ulGen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Disable the PWM generator.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, + ulGen) + PWM_O_X_CTL) &= ~(PWM_X_CTL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Sets the pulse width for the specified PWM output.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOut is the PWM output to modify. Must be one of \b PWM_OUT_0,
+//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5,
+//! \b PWM_OUT_6, or \b PWM_OUT_7.
+//! \param ulWidth specifies the width of the positive portion of the pulse.
+//!
+//! This function sets the pulse width for the specified PWM output, where the
+//! pulse width is defined as the number of PWM clock ticks.
+//!
+//! \note Any subsequent calls made to this function before an update occurs
+//! will cause the previous values to be overwritten.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
+ unsigned long ulWidth)
+{
+ unsigned long ulGenBase, ulReg;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMOutValid(ulPWMOut));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);
+
+ //
+ // If the counter is in up/down count mode, divide the width by two.
+ //
+ if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+ {
+ ulWidth /= 2;
+ }
+
+ //
+ // Get the period.
+ //
+ ulReg = HWREG(ulGenBase + PWM_O_X_LOAD);
+
+ //
+ // Make sure the width is not too large.
+ //
+ ASSERT(ulWidth < ulReg);
+
+ //
+ // Compute the compare value.
+ //
+ ulReg = ulReg - ulWidth;
+
+ //
+ // Write to the appropriate registers.
+ //
+ if(PWM_IS_OUTPUT_ODD(ulPWMOut))
+ {
+ HWREG(ulGenBase + PWM_O_X_CMPB) = ulReg;
+ }
+ else
+ {
+ HWREG(ulGenBase + PWM_O_X_CMPA) = ulReg;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the pulse width of a PWM output.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOut is the PWM output to query. Must be one of \b PWM_OUT_0,
+//! \b PWM_OUT_1, \b PWM_OUT_2, \b PWM_OUT_3, \b PWM_OUT_4, \b PWM_OUT_5,
+//! \b PWM_OUT_6, or \b PWM_OUT_7.
+//!
+//! This function gets the currently programmed pulse width for the specified
+//! PWM output. If the update of the comparator for the specified output has
+//! yet to be completed, the value returned may not be the active pulse width.
+//! The value returned is the programmed pulse width, measured in PWM clock
+//! ticks.
+//!
+//! \return Returns the width of the pulse in PWM clock ticks.
+//
+//*****************************************************************************
+unsigned long
+PWMPulseWidthGet(unsigned long ulBase, unsigned long ulPWMOut)
+{
+ unsigned long ulGenBase, ulReg, ulLoad;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMOutValid(ulPWMOut));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGenBase = PWM_OUT_BADDR(ulBase, ulPWMOut);
+
+ //
+ // Then compute the pulse width. If mode is UpDown, set
+ // width = (load - compare) * 2. Otherwise, set width = load - compare.
+ //
+ ulLoad = HWREG(ulGenBase + PWM_O_X_LOAD);
+ if(PWM_IS_OUTPUT_ODD(ulPWMOut))
+ {
+ ulReg = HWREG(ulGenBase + PWM_O_X_CMPB);
+ }
+ else
+ {
+ ulReg = HWREG(ulGenBase + PWM_O_X_CMPA);
+ }
+ ulReg = ulLoad - ulReg;
+
+ //
+ // If in up/down count mode, double the pulse width.
+ //
+ if(HWREG(ulGenBase + PWM_O_X_CTL) & PWM_X_CTL_MODE)
+ {
+ ulReg = ulReg * 2;
+ }
+
+ //
+ // Return the pulse width.
+ //
+ return(ulReg);
+}
+
+//*****************************************************************************
+//
+//! Enables the PWM dead band output, and sets the dead band delays.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to modify. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param usRise specifies the width of delay from the rising edge.
+//! \param usFall specifies the width of delay from the falling edge.
+//!
+//! This function sets the dead bands for the specified PWM generator,
+//! where the dead bands are defined as the number of \b PWM clock ticks
+//! from the rising or falling edge of the generator's \b OutA signal.
+//! Note that this function causes the coupling of \b OutB to \b OutA.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
+ unsigned short usRise, unsigned short usFall)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT(usRise < 4096);
+ ASSERT(usFall < 4096);
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Write the dead band delay values.
+ //
+ HWREG(ulGen + PWM_O_X_DBRISE) = usRise;
+ HWREG(ulGen + PWM_O_X_DBFALL) = usFall;
+
+ //
+ // Enable the deadband functionality.
+ //
+ HWREG(ulGen + PWM_O_X_DBCTL) |= PWM_X_DBCTL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the PWM dead band output.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to modify. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function disables the dead band mode for the specified PWM generator.
+//! Doing so decouples the \b OutA and \b OutB signals.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Disable the deadband functionality.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_DBCTL) &=
+ ~(PWM_X_DBCTL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Synchronizes all pending updates.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGenBits are the PWM generator blocks to be updated. Must be the
+//! logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT,
+//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT.
+//!
+//! For the selected PWM generators, this function causes all queued updates to
+//! the period or pulse width to be applied the next time the corresponding
+//! counter becomes zero.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT |
+ PWM_GEN_3_BIT)));
+
+ //
+ // Synchronize pending PWM register changes.
+ //
+ HWREG(ulBase + PWM_O_CTL) = ulGenBits;
+}
+
+//*****************************************************************************
+//
+//! Synchronizes the counters in one or multiple PWM generator blocks.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGenBits are the PWM generator blocks to be synchronized. Must be
+//! the logical OR of any of \b PWM_GEN_0_BIT, \b PWM_GEN_1_BIT,
+//! \b PWM_GEN_2_BIT, or \b PWM_GEN_3_BIT.
+//!
+//! For the selected PWM module, this function synchronizes the time base
+//! of the generator blocks by causing the specified generator counters to be
+//! reset to zero.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulGenBits & ~(PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT |
+ PWM_GEN_3_BIT)));
+
+ //
+ // Synchronize the counters in the specified generators by writing to the
+ // module's synchronization register.
+ //
+ HWREG(ulBase + PWM_O_SYNC) = ulGenBits;
+}
+
+//*****************************************************************************
+//
+//! Enables or disables PWM outputs.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT,
+//! or \b PWM_OUT_7_BIT.
+//! \param bEnable determines if the signal is enabled or disabled.
+//!
+//! This function is used to enable or disable the selected PWM outputs. The
+//! outputs are selected using the parameter \e ulPWMOutBits. The parameter
+//! \e bEnable determines the state of the selected outputs. If \e bEnable is
+//! \b true, then the selected PWM outputs are enabled, or placed in the active
+//! state. If \e bEnable is \b false, then the selected outputs are disabled,
+//! or placed in the inactive state.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bEnable)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+ PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+ //
+ // Read the module's ENABLE output control register, and set or clear the
+ // requested bits.
+ //
+ if(bEnable == true)
+ {
+ HWREG(ulBase + PWM_O_ENABLE) |= ulPWMOutBits;
+ }
+ else
+ {
+ HWREG(ulBase + PWM_O_ENABLE) &= ~(ulPWMOutBits);
+ }
+}
+
+//*****************************************************************************
+//
+//! Selects the inversion mode for PWM outputs.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or
+//! \b PWM_OUT_7_BIT.
+//! \param bInvert determines if the signal is inverted or passed through.
+//!
+//! This function is used to select the inversion mode for the selected PWM
+//! outputs. The outputs are selected using the parameter \e ulPWMOutBits.
+//! The parameter \e bInvert determines the inversion mode for the selected
+//! outputs. If \e bInvert is \b true, this function will cause the specified
+//! PWM output signals to be inverted, or made active low. If \e bInvert is
+//! \b false, the specified output will be passed through as is, or be made
+//! active high.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bInvert)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+ PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+ //
+ // Read the module's INVERT output control register, and set or clear the
+ // requested bits.
+ //
+ if(bInvert == true)
+ {
+ HWREG(ulBase + PWM_O_INVERT) |= ulPWMOutBits;
+ }
+ else
+ {
+ HWREG(ulBase + PWM_O_INVERT) &= ~(ulPWMOutBits);
+ }
+}
+
+//*****************************************************************************
+//
+//! Specifies the level of PWM outputs suppressed in response to a fault
+//! condition.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or
+//! \b PWM_OUT_7_BIT.
+//! \param bDriveHigh determines if the signal is driven high or low during an
+//! active fault condition.
+//!
+//! This function determines whether a PWM output pin that is suppressed in
+//! response to a fault condition will be driven high or low. The affected
+//! outputs are selected using the parameter \e ulPWMOutBits. The parameter
+//! \e bDriveHigh determines the output level for the pins identified by
+//! \e ulPWMOutBits. If \e bDriveHigh is \b true then the selected outputs
+//! will be driven high when a fault is detected. If it is \e false, the pins
+//! will be driven low.
+//!
+//! In a fault condition, pins which have not been configured to be suppressed
+//! via a call to PWMOutputFault() are unaffected by this function.
+//!
+//! \note This function is available only on devices which support extended
+//! PWM fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputFaultLevel(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bDriveHigh)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+ PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+ //
+ // Read the module's FAULT output control register, and set or clear the
+ // requested bits.
+ //
+ if(bDriveHigh == true)
+ {
+ HWREG(ulBase + PWM_O_FAULTVAL) |= ulPWMOutBits;
+ }
+ else
+ {
+ HWREG(ulBase + PWM_O_FAULTVAL) &= ~(ulPWMOutBits);
+ }
+}
+
+//*****************************************************************************
+//
+//! Specifies the state of PWM outputs in response to a fault condition.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulPWMOutBits are the PWM outputs to be modified. Must be the
+//! logical OR of any of \b PWM_OUT_0_BIT, \b PWM_OUT_1_BIT, \b PWM_OUT_2_BIT,
+//! \b PWM_OUT_3_BIT, \b PWM_OUT_4_BIT, \b PWM_OUT_5_BIT, \b PWM_OUT_6_BIT, or
+//! \b PWM_OUT_7_BIT.
+//! \param bFaultSuppress determines if the signal is suppressed or passed
+//! through during an active fault condition.
+//!
+//! This function sets the fault handling characteristics of the selected PWM
+//! outputs. The outputs are selected using the parameter \e ulPWMOutBits.
+//! The parameter \e bFaultSuppress determines the fault handling
+//! characteristics for the selected outputs. If \e bFaultSuppress is \b true,
+//! then the selected outputs will be made inactive. If \e bFaultSuppress is
+//! \b false, then the selected outputs are unaffected by the detected fault.
+//!
+//! On devices supporting extended PWM fault handling, the state the affected
+//! output pins are driven to can be configured with PWMOutputFaultLevel(). If
+//! not configured, or if the device does not support extended PWM fault
+//! handling, affected outputs will be driven low on a fault condition.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bFaultSuppress)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(!(ulPWMOutBits & ~(PWM_OUT_0_BIT | PWM_OUT_1_BIT | PWM_OUT_2_BIT |
+ PWM_OUT_3_BIT | PWM_OUT_4_BIT | PWM_OUT_5_BIT |
+ PWM_OUT_6_BIT | PWM_OUT_7_BIT)));
+
+ //
+ // Read the module's FAULT output control register, and set or clear the
+ // requested bits.
+ //
+ if(bFaultSuppress == true)
+ {
+ HWREG(ulBase + PWM_O_FAULT) |= ulPWMOutBits;
+ }
+ else
+ {
+ HWREG(ulBase + PWM_O_FAULT) &= ~(ulPWMOutBits);
+ }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator in question. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param pfnIntHandler is a pointer to the function to be called when the PWM
+//! generator interrupt occurs.
+//!
+//! This function will ensure that the interrupt handler specified by
+//! \e pfnIntHandler is called when an interrupt is detected for the specified
+//! PWM generator block. This function will also enable the corresponding
+//! PWM generator interrupt in the interrupt controller; individual generator
+//! interrupts and interrupt sources must be enabled with PWMIntEnable() and
+//! PWMGenIntTrigEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
+ void (*pfnIntHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Get the interrupt number associated with the specified generator.
+ //
+ if(ulGen == PWM_GEN_3)
+ {
+ ulInt = INT_PWM3;
+ }
+ else
+ {
+ ulInt = INT_PWM0 + (ulGen >> 6) - 1;
+ }
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulInt, pfnIntHandler);
+
+ //
+ // Enable the PWMx interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Removes an interrupt handler for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator in question. Must be one of
+//! \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//!
+//! This function will unregister the interrupt handler for the specified
+//! PWM generator block. This function will also disable the corresponding
+//! PWM generator interrupt in the interrupt controller; individual generator
+//! interrupts and interrupt sources must be disabled with PWMIntDisable() and
+//! PWMGenIntTrigDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Get the interrupt number associated with the specified generator.
+ //
+ if(ulGen == PWM_GEN_3)
+ {
+ ulInt = INT_PWM3;
+ }
+ else
+ {
+ ulInt = INT_PWM0 + (ulGen >> 6) - 1;
+ }
+
+ //
+ // Disable the PWMx interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a fault condition detected in a PWM
+//! module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param pfnIntHandler is a pointer to the function to be called when the PWM
+//! fault interrupt occurs.
+//!
+//! This function will ensure that the interrupt handler specified by
+//! \e pfnIntHandler is called when a fault interrupt is detected for the
+//! selected PWM module. This function will also enable the PWM fault
+//! interrupt in the NVIC; the PWM fault interrupt must also be enabled at the
+//! module level using PWMIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntRegister(unsigned long ulBase, void (*pfnIntHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+
+ //
+ // Register the interrupt handler, returning an error if one occurs.
+ //
+ IntRegister(INT_PWM_FAULT, pfnIntHandler);
+
+ //
+ // Enable the PWM fault interrupt.
+ //
+ IntEnable(INT_PWM_FAULT);
+}
+
+//*****************************************************************************
+//
+//! Removes the PWM fault condition interrupt handler.
+//!
+//! \param ulBase is the base address of the PWM module.
+//!
+//! This function will remove the interrupt handler for a PWM fault interrupt
+//! from the selected PWM module. This function will also disable the PWM
+//! fault interrupt in the NVIC; the PWM fault interrupt must also be disabled
+//! at the module level using PWMIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+
+ //
+ // Disable the PWM fault interrupt.
+ //
+ IntDisable(INT_PWM_FAULT);
+
+ //
+ // Unregister the interrupt handler, returning an error if one occurs.
+ //
+ IntUnregister(INT_PWM_FAULT);
+}
+
+//*****************************************************************************
+//
+//! Enables interrupts and triggers for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to have interrupts and triggers enabled.
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulIntTrig specifies the interrupts and triggers to be enabled.
+//!
+//! Unmasks the specified interrupt(s) and trigger(s) by setting the
+//! specified bits of the interrupt/trigger enable register for the specified
+//! PWM generator. The \e ulIntTrig parameter is the logical OR of
+//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU,
+//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD,
+//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD,
+//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulIntTrig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD |
+ PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU |
+ PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | PWM_TR_CNT_LOAD |
+ PWM_TR_CNT_AU | PWM_TR_CNT_AD | PWM_TR_CNT_BU |
+ PWM_TR_CNT_BD)) == 0);
+
+ //
+ // Enable the specified interrupts/triggers.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) |= ulIntTrig;
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to have interrupts and triggers disabled.
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulIntTrig specifies the interrupts and triggers to be disabled.
+//!
+//! Masks the specified interrupt(s) and trigger(s) by clearing the
+//! specified bits of the interrupt/trigger enable register for the specified
+//! PWM generator. The \e ulIntTrig parameter is the logical OR of
+//! \b PWM_INT_CNT_ZERO, \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU,
+//! \b PWM_INT_CNT_AD, \b PWM_INT_CNT_BU, \b PWM_INT_CNT_BD,
+//! \b PWM_TR_CNT_ZERO, \b PWM_TR_CNT_LOAD, \b PWM_TR_CNT_AU, \b PWM_TR_CNT_AD,
+//! \b PWM_TR_CNT_BU, or \b PWM_TR_CNT_BD.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulIntTrig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulIntTrig & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD |
+ PWM_INT_CNT_AU | PWM_INT_CNT_AD | PWM_INT_CNT_BU |
+ PWM_INT_CNT_BD | PWM_TR_CNT_ZERO | PWM_TR_CNT_LOAD |
+ PWM_TR_CNT_AU | PWM_TR_CNT_AD | PWM_TR_CNT_BU |
+ PWM_TR_CNT_BD)) == 0);
+
+ //
+ // Disable the specified interrupts/triggers.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_INTEN) &= ~(ulIntTrig);
+}
+
+//*****************************************************************************
+//
+//! Gets interrupt status for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,
+//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status will be returned.
+//!
+//! \return Returns the contents of the interrupt status register, or the
+//! contents of the raw interrupt status register, for the specified
+//! PWM generator.
+//
+//*****************************************************************************
+unsigned long
+PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+
+ //
+ // Compute the generator's base address.
+ //
+ ulGen = PWM_GEN_BADDR(ulBase, ulGen);
+
+ //
+ // Read and return the specified generator's raw or enabled interrupt
+ // status.
+ //
+ if(bMasked == true)
+ {
+ return(HWREG(ulGen + PWM_O_X_ISC));
+ }
+ else
+ {
+ return(HWREG(ulGen + PWM_O_X_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the specified interrupt(s) for the specified PWM generator block.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator to query. Must be one of \b PWM_GEN_0,
+//! \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulInts specifies the interrupts to be cleared.
+//!
+//! Clears the specified interrupt(s) by writing a 1 to the specified bits
+//! of the interrupt status register for the specified PWM generator. The
+//! \e ulInts parameter is the logical OR of \b PWM_INT_CNT_ZERO,
+//! \b PWM_INT_CNT_LOAD, \b PWM_INT_CNT_AU, \b PWM_INT_CNT_AD,
+//! \b PWM_INT_CNT_BU, or \b PWM_INT_CNT_BD.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, unsigned long ulInts)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulInts & ~(PWM_INT_CNT_ZERO | PWM_INT_CNT_LOAD | PWM_INT_CNT_AU |
+ PWM_INT_CNT_AD | PWM_INT_CNT_BU | PWM_INT_CNT_BD)) ==
+ 0);
+
+ //
+ // Clear the requested interrupts by writing ones to the specified bit
+ // of the module's interrupt enable register.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_ISC) = ulInts;
+}
+
+//*****************************************************************************
+//
+//! Enables generator and fault interrupts for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGenFault contains the interrupts to be enabled. Must be a logical
+//! OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2,
+//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2,
+//! or \b PWM_INT_FAULT3.
+//!
+//! Unmasks the specified interrupt(s) by setting the specified bits of
+//! the interrupt enable register for the selected PWM module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 |
+ PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 |
+ PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
+
+ //
+ // Read the module's interrupt enable register, and enable interrupts
+ // for the specified PWM generators.
+ //
+ HWREG(ulBase + PWM_O_INTEN) |= ulGenFault;
+}
+
+//*****************************************************************************
+//
+//! Disables generator and fault interrupts for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGenFault contains the interrupts to be disabled. Must be a
+//! logical OR of any of \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2,
+//! \b PWM_INT_GEN_3, \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2,
+//! or \b PWM_INT_FAULT3.
+//!
+//! Masks the specified interrupt(s) by clearing the specified bits of
+//! the interrupt enable register for the selected PWM module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT((ulGenFault & ~(PWM_INT_GEN_0 | PWM_INT_GEN_1 | PWM_INT_GEN_2 |
+ PWM_INT_GEN_3 | PWM_INT_FAULT0 | PWM_INT_FAULT1 |
+ PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
+
+ //
+ // Read the module's interrupt enable register, and disable interrupts
+ // for the specified PWM generators.
+ //
+ HWREG(ulBase + PWM_O_INTEN) &= ~(ulGenFault);
+}
+
+//*****************************************************************************
+//
+//! Clears the fault interrupt for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//!
+//! Clears the fault interrupt by writing to the appropriate bit of the
+//! interrupt status register for the selected PWM module.
+//!
+//! This function clears only the FAULT0 interrupt and is retained for
+//! backwards compatibility. It is recommended that PWMFaultIntClearExt() be
+//! used instead since it supports all fault interrupts supported on devices
+//! with and without extended PWM fault handling support.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+
+ //
+ // Write the only writeable bit in the module's interrupt register.
+ //
+ HWREG(ulBase + PWM_O_ISC) = PWM_ISC_INTFAULT0;
+}
+
+//*****************************************************************************
+//
+//! Gets the interrupt status for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status will be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b PWM_INT_GEN_0, \b PWM_INT_GEN_1, \b PWM_INT_GEN_2, \b PWM_INT_GEN_3,
+//! \b PWM_INT_FAULT0, \b PWM_INT_FAULT1, \b PWM_INT_FAULT2, and
+//! \b PWM_INT_FAULT3.
+//!
+//*****************************************************************************
+unsigned long
+PWMIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+
+ //
+ // Read and return either the module's raw or enabled interrupt status.
+ //
+ if(bMasked == true)
+ {
+ return(HWREG(ulBase + PWM_O_ISC));
+ }
+ else
+ {
+ return(HWREG(ulBase + PWM_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the fault interrupt for a PWM module.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulFaultInts specifies the fault interrupts to clear.
+//!
+//! Clears one or more fault interrupts by writing to the appropriate bit of
+//! the PWM interrupt status register. The parameter \e ulFaultInts must be
+//! the logical OR of any of \b PWM_INT_FAULT0, \b PWM_INT_FAULT1,
+//! \b PWM_INT_FAULT2, or \b PWM_INT_FAULT3.
+//!
+//! When running on a device supporting extended PWM fault handling, the fault
+//! interrupts are derived by performing a logical OR of each of the configured
+//! fault trigger signals for a given generator. Therefore, these interrupts
+//! are not directly related to the four possible FAULTn inputs to the device
+//! but indicate that a fault has been signaled to one of the four possible PWM
+//! generators. On a device without extended PWM fault handling, the interrupt
+//! is directly related to the state of the single FAULT pin.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMFaultIntClearExt(unsigned long ulBase, unsigned long ulFaultInts)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT((ulFaultInts & ~(PWM_INT_FAULT0 | PWM_INT_FAULT1 |
+ PWM_INT_FAULT2 | PWM_INT_FAULT3)) == 0);
+
+ //
+ // Clear the supplied fault bits.
+ //
+ HWREG(ulBase + PWM_O_ISC) = ulFaultInts;
+}
+
+//*****************************************************************************
+//
+//! Configures the minimum fault period and fault pin senses for a given
+//! PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault configuration is being set.
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulMinFaultPeriod is the minimum fault active period expressed in
+//! PWM clock cycles.
+//! \param ulFaultSenses indicates which sense of each FAULT input should be
+//! considered the ``asserted'' state. Valid values are logical OR
+//! combinations of \b PWM_FAULTn_SENSE_HIGH and \b PWM_FAULTn_SENSE_LOW.
+//!
+//! This function sets the minimum fault period for a given generator along
+//! with the sense of each of the 4 possible fault inputs. The minimum fault
+//! period is expressed in PWM clock cycles and takes effect only if
+//! PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_PER set in the
+//! \e ulConfig parameter. When a fault input is asserted, the minimum fault
+//! period timer ensures that it remains asserted for at least the number of
+//! clock cycles specified.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulMinFaultPeriod,
+ unsigned long ulFaultSenses)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT(ulMinFaultPeriod < PWM_X_MINFLTPER_M);
+ ASSERT((ulFaultSenses & ~(PWM_FAULT0_SENSE_HIGH | PWM_FAULT0_SENSE_LOW |
+ PWM_FAULT1_SENSE_HIGH | PWM_FAULT1_SENSE_LOW |
+ PWM_FAULT2_SENSE_HIGH | PWM_FAULT2_SENSE_LOW |
+ PWM_FAULT3_SENSE_HIGH | PWM_FAULT3_SENSE_LOW)) ==
+ 0);
+
+ //
+ // Write the minimum fault period.
+ //
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_MINFLTPER) = ulMinFaultPeriod;
+
+ //
+ // Write the fault senses.
+ //
+ HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSEN) = ulFaultSenses;
+}
+
+//*****************************************************************************
+//
+//! Configures the set of fault triggers for a given PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault triggers are being set. Must
+//! be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulGroup indicates the subset of possible faults that are to be
+//! configured. This must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
+//! \param ulFaultTriggers defines the set of inputs that are to contribute
+//! towards generation of the fault signal to the given PWM generator. For
+//! \b PWM_FAULT_GROUP_0, this will be the logical OR of \b PWM_FAULT_FAULT0,
+//! \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or \b PWM_FAULT_FAULT3. For
+//! \b PWM_FAULT_GROUP_1, this will be the logical OR of \b PWM_FAULT_DCMP0,
+//! \b PWM_FAULT_DCMP1, \b PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b
+//! PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5, \b PWM_FAULT_DCMP6, or \b
+//! PWM_FAULT_DCMP7.
+//!
+//! This function allows selection of the set of fault inputs that will be
+//! combined to generate a fault condition to a given PWM generator. By
+//! default, all generators use only FAULT0 (for backwards compatibility) but
+//! if PWMGenConfigure() is called with flag \b PWM_GEN_MODE_FAULT_SRC in the
+//! \e ulConfig parameter, extended fault handling is enabled and this function
+//! must be called to configure the fault triggers.
+//!
+//! The fault signal to the PWM generator is generated by ORing together each
+//! of the signals whose inputs are specified in the \e ulFaultTriggers
+//! parameter after having adjusted the sense of each FAULTn input based on the
+//! configuration previously set using a call to PWMGenFaultConfigure().
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup, unsigned long ulFaultTriggers)
+{
+ //
+ // Check for valid parameters.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) &&
+ ((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
+ PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_1) &&
+ ((ulFaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 |
+ PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 |
+ PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 |
+ PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0));
+
+ //
+ // Write the fault triggers to the appropriate register.
+ //
+ if(ulGroup == PWM_FAULT_GROUP_0)
+ {
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0) =
+ ulFaultTriggers;
+ }
+ else
+ {
+ HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC1) =
+ ulFaultTriggers;
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the set of fault triggers currently configured for a given PWM
+//! generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault triggers are being queried.
+//! Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or \b PWM_GEN_3.
+//! \param ulGroup indicates the subset of faults that are being queried. This
+//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
+//!
+//! This function allows an application to query the current set of inputs that
+//! contribute towards the generation of a fault condition to a given PWM
+//! generator.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return Returns the current fault triggers configured for the fault group
+//! provided. For \b PWM_FAULT_GROUP_0, the returned value will be a logical
+//! OR of \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
+//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value will be
+//! the logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, \b
+//! PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5,
+//! \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7.
+//
+//*****************************************************************************
+unsigned long
+PWMGenFaultTriggerGet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup)
+{
+ //
+ // Check for valid parameters.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
+
+ //
+ // Return the current fault triggers.
+ //
+ if(ulGroup == PWM_FAULT_GROUP_0)
+ {
+ return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC0));
+ }
+ else
+ {
+ return(HWREG(PWM_GEN_BADDR(ulBase, ulGen) + PWM_O_X_FLTSRC1));
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the current state of the fault triggers for a given PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault trigger states are being
+//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
+//! \b PWM_GEN_3.
+//! \param ulGroup indicates the subset of faults that are being queried. This
+//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
+//!
+//! This function allows an application to query the current state of each of
+//! the fault trigger inputs to a given PWM generator. The current state of
+//! each fault trigger input is returned unless PWMGenConfigure() has
+//! previously been called with flag \b PWM_GEN_MODE_LATCH_FAULT in the
+//! \e ulConfig parameter in which case the returned status is the latched
+//! fault trigger status.
+//!
+//! If latched faults are configured, the application must call
+//! PWMGenFaultClear() to clear each trigger.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return Returns the current state of the fault triggers for the given PWM
+//! generator. A set bit indicates that the associated trigger is active. For
+//! \b PWM_FAULT_GROUP_0, the returned value will be a logical OR of
+//! \b PWM_FAULT_FAULT0, \b PWM_FAULT_FAULT1, \b PWM_FAULT_FAULT2, or
+//! \b PWM_FAULT_FAULT3. For \b PWM_FAULT_GROUP_1, the return value will be
+//! the logical OR of \b PWM_FAULT_DCMP0, \b PWM_FAULT_DCMP1, \b
+//! PWM_FAULT_DCMP2, \b PWM_FAULT_DCMP3, \b PWM_FAULT_DCMP4, \b PWM_FAULT_DCMP5,
+//! \b PWM_FAULT_DCMP6, or \b PWM_FAULT_DCMP7.
+//
+//*****************************************************************************
+unsigned long
+PWMGenFaultStatus(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup)
+{
+ //
+ // Check for valid parameters.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
+
+ //
+ // Return the current fault status.
+ //
+ if(ulGroup == PWM_FAULT_GROUP_0)
+ {
+ return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0));
+ }
+ else
+ {
+ return(HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT1));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears one or more latched fault triggers for a given PWM generator.
+//!
+//! \param ulBase is the base address of the PWM module.
+//! \param ulGen is the PWM generator whose fault trigger states are being
+//! queried. Must be one of \b PWM_GEN_0, \b PWM_GEN_1, \b PWM_GEN_2, or
+//! \b PWM_GEN_3.
+//! \param ulGroup indicates the subset of faults that are being queried. This
+//! must be \b PWM_FAULT_GROUP_0 or \b PWM_FAULT_GROUP_1.
+//! \param ulFaultTriggers is the set of fault triggers which are to be
+//! cleared.
+//!
+//! This function allows an application to clear the fault triggers for a given
+//! PWM generator. This is only required if PWMGenConfigure() has previously
+//! been called with flag \b PWM_GEN_MODE_LATCH_FAULT in parameter \e ulConfig.
+//!
+//! \note This function is only available on devices supporting extended PWM
+//! fault handling.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup, unsigned long ulFaultTriggers)
+{
+ //
+ // Check for valid parameters.
+ //
+ ASSERT(HWREG(SYSCTL_DC5) & SYSCTL_DC5_PWMEFLT);
+ ASSERT(ulBase == PWM_BASE);
+ ASSERT(PWMGenValid(ulGen));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) || (ulGroup == PWM_FAULT_GROUP_1));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_0) &&
+ ((ulFaultTriggers & ~(PWM_FAULT_FAULT0 | PWM_FAULT_FAULT1 |
+ PWM_FAULT_FAULT2 | PWM_FAULT_FAULT3)) == 0));
+ ASSERT((ulGroup == PWM_FAULT_GROUP_1) &&
+ ((ulFaultTriggers & ~(PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1 |
+ PWM_FAULT_DCMP2 | PWM_FAULT_DCMP3 |
+ PWM_FAULT_DCMP4 | PWM_FAULT_DCMP5 |
+ PWM_FAULT_DCMP6 | PWM_FAULT_DCMP7)) == 0));
+
+ //
+ // Clear the given faults.
+ //
+ if(ulGroup == PWM_FAULT_GROUP_0)
+ {
+ HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT0) =
+ ulFaultTriggers;
+ }
+ else
+ {
+ HWREG(PWM_GEN_EXT_BADDR(ulBase, ulGen) + PWM_O_X_FLTSTAT1) =
+ ulFaultTriggers;
+ }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/pwm.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/pwm.h
new file mode 100644
index 00000000..8eca5912
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/pwm.h
@@ -0,0 +1,283 @@
+//*****************************************************************************
+//
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __PWM_H__
+#define __PWM_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are passed to PWMGenConfigure() as the ulConfig
+// parameter and specify the configuration of the PWM generator.
+//
+//*****************************************************************************
+#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
+#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
+#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
+#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
+#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
+#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
+#define PWM_GEN_MODE_FAULT_LATCHED \
+ 0x00040000 // Fault is latched
+#define PWM_GEN_MODE_FAULT_UNLATCHED \
+ 0x00000000 // Fault is not latched
+#define PWM_GEN_MODE_FAULT_MINPER \
+ 0x00020000 // Enable min fault period
+#define PWM_GEN_MODE_FAULT_NO_MINPER \
+ 0x00000000 // Disable min fault period
+#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
+#define PWM_GEN_MODE_FAULT_LEGACY \
+ 0x00000000 // Disable extended fault support
+#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
+ // immediately
+#define PWM_GEN_MODE_DB_SYNC_LOCAL \
+ 0x0000A800 // Deadband updates locally
+ // synchronized
+#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
+ 0x0000FC00 // Deadband updates globally
+ // synchronized
+#define PWM_GEN_MODE_GEN_NO_SYNC \
+ 0x00000000 // Generator mode updates occur
+ // immediately
+#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
+ 0x00000280 // Generator mode updates locally
+ // synchronized
+#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
+ 0x000003C0 // Generator mode updates globally
+ // synchronized
+
+//*****************************************************************************
+//
+// Defines for enabling, disabling, and clearing PWM generator interrupts and
+// triggers.
+//
+//*****************************************************************************
+#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
+#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
+#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
+#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
+#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
+#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
+#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
+#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
+#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
+#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
+#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
+#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
+
+//*****************************************************************************
+//
+// Defines for enabling, disabling, and clearing PWM interrupts.
+//
+//*****************************************************************************
+#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
+#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
+#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
+#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
+#ifndef DEPRECATED
+#define PWM_INT_FAULT 0x00010000 // Fault interrupt
+#endif
+#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
+#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
+#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
+#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
+#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
+
+//*****************************************************************************
+//
+// Defines to identify the generators within a module.
+//
+//*****************************************************************************
+#define PWM_GEN_0 0x00000040 // Offset address of Gen0
+#define PWM_GEN_1 0x00000080 // Offset address of Gen1
+#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
+#define PWM_GEN_3 0x00000100 // Offset address of Gen3
+
+#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
+#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
+#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
+#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
+
+#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
+#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
+#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
+#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
+
+//*****************************************************************************
+//
+// Defines to identify the outputs within a module.
+//
+//*****************************************************************************
+#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
+#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
+#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
+#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
+#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
+#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
+#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
+#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
+
+#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
+#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
+#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
+#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
+#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
+#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
+#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
+#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
+
+//*****************************************************************************
+//
+// Defines to identify each of the possible fault trigger conditions in
+// PWM_FAULT_GROUP_0.
+//
+//*****************************************************************************
+#define PWM_FAULT_GROUP_0 0
+
+#define PWM_FAULT_FAULT0 0x00000001
+#define PWM_FAULT_FAULT1 0x00000002
+#define PWM_FAULT_FAULT2 0x00000004
+#define PWM_FAULT_FAULT3 0x00000008
+#define PWM_FAULT_ACMP0 0x00010000
+#define PWM_FAULT_ACMP1 0x00020000
+#define PWM_FAULT_ACMP2 0x00040000
+
+//*****************************************************************************
+//
+// Defines to identify each of the possible fault trigger conditions in
+// PWM_FAULT_GROUP_1.
+//
+//*****************************************************************************
+#define PWM_FAULT_GROUP_1 1
+
+#define PWM_FAULT_DCMP0 0x00000001
+#define PWM_FAULT_DCMP1 0x00000002
+#define PWM_FAULT_DCMP2 0x00000004
+#define PWM_FAULT_DCMP3 0x00000008
+#define PWM_FAULT_DCMP4 0x00000010
+#define PWM_FAULT_DCMP5 0x00000020
+#define PWM_FAULT_DCMP6 0x00000040
+#define PWM_FAULT_DCMP7 0x00000080
+
+//*****************************************************************************
+//
+// Defines to identify the sense of each of the external FAULTn signals
+//
+//*****************************************************************************
+#define PWM_FAULT0_SENSE_HIGH 0x00000000
+#define PWM_FAULT0_SENSE_LOW 0x00000001
+#define PWM_FAULT1_SENSE_HIGH 0x00000000
+#define PWM_FAULT1_SENSE_LOW 0x00000002
+#define PWM_FAULT2_SENSE_HIGH 0x00000000
+#define PWM_FAULT2_SENSE_LOW 0x00000004
+#define PWM_FAULT3_SENSE_HIGH 0x00000000
+#define PWM_FAULT3_SENSE_LOW 0x00000008
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulConfig);
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulPeriod);
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
+ unsigned long ulGen);
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
+ unsigned long ulWidth);
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
+ unsigned long ulPWMOut);
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
+ unsigned short usRise, unsigned short usFall);
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bEnable);
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bInvert);
+extern void PWMOutputFaultLevel(unsigned long ulBase,
+ unsigned long ulPWMOutBits,
+ tBoolean bDriveHigh);
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
+ tBoolean bFaultSuppress);
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
+ void (*pfnIntHandler)(void));
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
+extern void PWMFaultIntRegister(unsigned long ulBase,
+ void (*pfnIntHandler)(void));
+extern void PWMFaultIntUnregister(unsigned long ulBase);
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulIntTrig);
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulIntTrig);
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
+ tBoolean bMasked);
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulInts);
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
+extern void PWMFaultIntClear(unsigned long ulBase);
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void PWMFaultIntClearExt(unsigned long ulBase,
+ unsigned long ulFaultInts);
+extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulMinFaultPeriod,
+ unsigned long ulFaultSenses);
+extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup,
+ unsigned long ulFaultTriggers);
+extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,
+ unsigned long ulGen,
+ unsigned long ulGroup);
+extern unsigned long PWMGenFaultStatus(unsigned long ulBase,
+ unsigned long ulGen,
+ unsigned long ulGroup);
+extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
+ unsigned long ulGroup,
+ unsigned long ulFaultTriggers);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __PWM_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/qei.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/qei.c
new file mode 100644
index 00000000..4615846e
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/qei.c
@@ -0,0 +1,616 @@
+//*****************************************************************************
+//
+// qei.c - Driver for the Quadrature Encoder with Index.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup qei_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_qei.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/qei.h"
+
+//*****************************************************************************
+//
+//! Enables the quadrature encoder.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This will enable operation of the quadrature encoder module. It must be
+//! configured before it is enabled.
+//!
+//! \sa QEIConfigure()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Enable the QEI module.
+ //
+ HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the quadrature encoder.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This will disable operation of the quadrature encoder module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Disable the QEI module.
+ //
+ HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Configures the quadrature encoder.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param ulConfig is the configuration for the quadrature encoder. See below
+//! for a description of this parameter.
+//! \param ulMaxPosition specifies the maximum position value.
+//!
+//! This will configure the operation of the quadrature encoder. The
+//! \e ulConfig parameter provides the configuration of the encoder and is the
+//! logical OR of several values:
+//!
+//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges
+//! on channel A or on both channels A and B should be counted by the
+//! position integrator and velocity accumulator.
+//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the
+//! position integrator should be reset when the index pulse is detected.
+//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if
+//! quadrature signals are being provided on ChA and ChB, or if a direction
+//! signal and a clock are being provided instead.
+//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals
+//! provided on ChA and ChB should be swapped before being processed.
+//!
+//! \e ulMaxPosition is the maximum value of the position integrator, and is
+//! the value used to reset the position capture when in index reset mode and
+//! moving in the reverse (negative) direction.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulMaxPosition)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Write the new configuration to the hardware.
+ //
+ HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) &
+ ~(QEI_CTL_CAPMODE | QEI_CTL_RESMODE |
+ QEI_CTL_SIGMODE | QEI_CTL_SWAP)) |
+ ulConfig);
+
+ //
+ // Set the maximum position.
+ //
+ HWREG(ulBase + QEI_O_MAXPOS) = ulMaxPosition;
+}
+
+//*****************************************************************************
+//
+//! Gets the current encoder position.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This returns the current position of the encoder. Depending upon the
+//! configuration of the encoder, and the incident of an index pulse, this
+//! value may or may not contain the expected data (that is, if in reset on
+//! index mode, if an index pulse has not been encountered, the position
+//! counter will not be aligned with the index pulse yet).
+//!
+//! \return The current position of the encoder.
+//
+//*****************************************************************************
+unsigned long
+QEIPositionGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Return the current position counter.
+ //
+ return(HWREG(ulBase + QEI_O_POS));
+}
+
+//*****************************************************************************
+//
+//! Sets the current encoder position.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param ulPosition is the new position for the encoder.
+//!
+//! This sets the current position of the encoder; the encoder position will
+//! then be measured relative to this value.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIPositionSet(unsigned long ulBase, unsigned long ulPosition)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Set the position counter.
+ //
+ HWREG(ulBase + QEI_O_POS) = ulPosition;
+}
+
+//*****************************************************************************
+//
+//! Gets the current direction of rotation.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This returns the current direction of rotation. In this case, current
+//! means the most recently detected direction of the encoder; it may not be
+//! presently moving but this is the direction it last moved before it stopped.
+//!
+//! \return Returns 1 if moving in the forward direction or -1 if moving in the
+//! reverse direction.
+//
+//*****************************************************************************
+long
+QEIDirectionGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Return the direction of rotation.
+ //
+ return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_DIRECTION) ? -1 : 1);
+}
+
+//*****************************************************************************
+//
+//! Gets the encoder error indicator.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This returns the error indicator for the quadrature encoder. It is an
+//! error for both of the signals of the quadrature input to change at the same
+//! time.
+//!
+//! \return Returns \b true if an error has occurred and \b false otherwise.
+//
+//*****************************************************************************
+tBoolean
+QEIErrorGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Return the error indicator.
+ //
+ return((HWREG(ulBase + QEI_O_STAT) & QEI_STAT_ERROR) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Enables the velocity capture.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This will enable operation of the velocity capture in the quadrature
+//! encoder module. It must be configured before it is enabled. Velocity
+//! capture will not occur if the quadrature encoder is not enabled.
+//!
+//! \sa QEIVelocityConfigure() and QEIEnable()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIVelocityEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Enable the velocity capture.
+ //
+ HWREG(ulBase + QEI_O_CTL) |= QEI_CTL_VELEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the velocity capture.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This will disable operation of the velocity capture in the quadrature
+//! encoder module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIVelocityDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Disable the velocity capture.
+ //
+ HWREG(ulBase + QEI_O_CTL) &= ~(QEI_CTL_VELEN);
+}
+
+//*****************************************************************************
+//
+//! Configures the velocity capture.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param ulPreDiv specifies the predivider applied to the input quadrature
+//! signal before it is counted; can be one of \b QEI_VELDIV_1,
+//! \b QEI_VELDIV_2, \b QEI_VELDIV_4, \b QEI_VELDIV_8, \b QEI_VELDIV_16,
+//! \b QEI_VELDIV_32, \b QEI_VELDIV_64, or \b QEI_VELDIV_128.
+//! \param ulPeriod specifies the number of clock ticks over which to measure
+//! the velocity; must be non-zero.
+//!
+//! This will configure the operation of the velocity capture portion of the
+//! quadrature encoder. The position increment signal is predivided as
+//! specified by \e ulPreDiv before being accumulated by the velocity capture.
+//! The divided signal is accumulated over \e ulPeriod system clock before
+//! being saved and resetting the accumulator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
+ unsigned long ulPeriod)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+ ASSERT(!(ulPreDiv & ~(QEI_CTL_VELDIV_M)));
+ ASSERT(ulPeriod != 0);
+
+ //
+ // Set the velocity predivider.
+ //
+ HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) &
+ ~(QEI_CTL_VELDIV_M)) | ulPreDiv);
+
+ //
+ // Set the timer period.
+ //
+ HWREG(ulBase + QEI_O_LOAD) = ulPeriod - 1;
+}
+
+//*****************************************************************************
+//
+//! Gets the current encoder speed.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This returns the current speed of the encoder. The value returned is the
+//! number of pulses detected in the specified time period; this number can be
+//! multiplied by the number of time periods per second and divided by the
+//! number of pulses per revolution to obtain the number of revolutions per
+//! second.
+//!
+//! \return Returns the number of pulses captured in the given time period.
+//
+//*****************************************************************************
+unsigned long
+QEIVelocityGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Return the speed capture value.
+ //
+ return(HWREG(ulBase + QEI_O_SPEED));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the quadrature encoder interrupt.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! quadrature encoder interrupt occurs.
+//!
+//! This sets the handler to be called when a quadrature encoder interrupt
+//! occurs. This will enable the global interrupt in the interrupt controller;
+//! specific quadrature encoder interrupts must be enabled via QEIIntEnable().
+//! It is the interrupt handler's responsibility to clear the interrupt source
+//! via QEIIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Determine the interrupt number based on the QEI module.
+ //
+ ulInt = (ulBase == QEI0_BASE) ? INT_QEI0 : INT_QEI1;
+
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the quadrature encoder interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the quadrature encoder interrupt.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//!
+//! This function will clear the handler to be called when a quadrature encoder
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Determine the interrupt number based on the QEI module.
+ //
+ ulInt = (ulBase == QEI0_BASE) ? INT_QEI0 : INT_QEI1;
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Enables individual quadrature encoder interrupt sources.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
+//! \b QEI_INTINDEX values.
+//!
+//! Enables the indicated quadrature encoder interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + QEI_O_INTEN) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual quadrature encoder interrupt sources.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
+//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
+//! \b QEI_INTINDEX values.
+//!
+//! Disables the indicated quadrature encoder interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + QEI_O_INTEN) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the quadrature encoder module.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX.
+//
+//*****************************************************************************
+unsigned long
+QEIIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + QEI_O_ISC));
+ }
+ else
+ {
+ return(HWREG(ulBase + QEI_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears quadrature encoder interrupt sources.
+//!
+//! \param ulBase is the base address of the quadrature encoder module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
+//! \b QEI_INTINDEX values.
+//!
+//! The specified quadrature encoder interrupt sources are cleared, so that
+//! they no longer assert. This must be done in the interrupt handler to keep
+//! it from being called again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + QEI_O_ISC) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/qei.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/qei.h
new file mode 100644
index 00000000..0ad5e1e9
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/qei.h
@@ -0,0 +1,112 @@
+//*****************************************************************************
+//
+// qei.h - Prototypes for the Quadrature Encoder Driver.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __QEI_H__
+#define __QEI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIConfigure as the ulConfig paramater.
+//
+//*****************************************************************************
+#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only
+#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges
+#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse
+#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse
+#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature
+#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir
+#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB
+#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter.
+//
+//*****************************************************************************
+#define QEI_VELDIV_1 0x00000000 // Predivide by 1
+#define QEI_VELDIV_2 0x00000040 // Predivide by 2
+#define QEI_VELDIV_4 0x00000080 // Predivide by 4
+#define QEI_VELDIV_8 0x000000C0 // Predivide by 8
+#define QEI_VELDIV_16 0x00000100 // Predivide by 16
+#define QEI_VELDIV_32 0x00000140 // Predivide by 32
+#define QEI_VELDIV_64 0x00000180 // Predivide by 64
+#define QEI_VELDIV_128 0x000001C0 // Predivide by 128
+
+//*****************************************************************************
+//
+// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts
+// as the ulIntFlags parameter, and returned by QEIGetIntStatus.
+//
+//*****************************************************************************
+#define QEI_INTERROR 0x00000008 // Phase error detected
+#define QEI_INTDIR 0x00000004 // Direction change
+#define QEI_INTTIMER 0x00000002 // Velocity timer expired
+#define QEI_INTINDEX 0x00000001 // Index pulse detected
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void QEIEnable(unsigned long ulBase);
+extern void QEIDisable(unsigned long ulBase);
+extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
+ unsigned long ulMaxPosition);
+extern unsigned long QEIPositionGet(unsigned long ulBase);
+extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition);
+extern long QEIDirectionGet(unsigned long ulBase);
+extern tBoolean QEIErrorGet(unsigned long ulBase);
+extern void QEIVelocityEnable(unsigned long ulBase);
+extern void QEIVelocityDisable(unsigned long ulBase);
+extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
+ unsigned long ulPeriod);
+extern unsigned long QEIVelocityGet(unsigned long ulBase);
+extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern void QEIIntUnregister(unsigned long ulBase);
+extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __QEI_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/rom.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/rom.h
new file mode 100644
index 00000000..467d6c20
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/rom.h
@@ -0,0 +1,3584 @@
+//*****************************************************************************
+//
+// rom.h - Macros to facilitate calling functions in the ROM.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ROM_H__
+#define __ROM_H__
+
+//*****************************************************************************
+//
+// Pointers to the main API tables.
+//
+//*****************************************************************************
+#define ROM_APITABLE ((unsigned long *)0x01000010)
+#define ROM_VERSION (ROM_APITABLE[0])
+#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1]))
+#define ROM_SSITABLE ((unsigned long *)(ROM_APITABLE[2]))
+#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[3]))
+#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[4]))
+#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[5]))
+#define ROM_COMPARATORTABLE ((unsigned long *)(ROM_APITABLE[6]))
+#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[7]))
+#define ROM_PWMTABLE ((unsigned long *)(ROM_APITABLE[8]))
+#define ROM_QEITABLE ((unsigned long *)(ROM_APITABLE[9]))
+#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[10]))
+#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[11]))
+#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[12]))
+#define ROM_SYSCTLTABLE ((unsigned long *)(ROM_APITABLE[13]))
+#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[14]))
+#define ROM_ETHERNETTABLE ((unsigned long *)(ROM_APITABLE[15]))
+#define ROM_USBTABLE ((unsigned long *)(ROM_APITABLE[16]))
+#define ROM_UDMATABLE ((unsigned long *)(ROM_APITABLE[17]))
+#define ROM_CANTABLE ((unsigned long *)(ROM_APITABLE[18]))
+#define ROM_HIBERNATETABLE ((unsigned long *)(ROM_APITABLE[19]))
+#define ROM_MPUTABLE ((unsigned long *)(ROM_APITABLE[20]))
+#define ROM_SOFTWARETABLE ((unsigned long *)(ROM_APITABLE[21]))
+#define ROM_I2STABLE ((unsigned long *)(ROM_APITABLE[22]))
+#define ROM_EPITABLE ((unsigned long *)(ROM_APITABLE[23]))
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the ADC API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCSequenceDataGet \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum, \
+ unsigned long *pulBuffer))ROM_ADCTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum, \
+ tBoolean bMasked))ROM_ADCTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCSequenceEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCSequenceDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCSequenceConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum, \
+ unsigned long ulTrigger, \
+ unsigned long ulPriority))ROM_ADCTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCSequenceStepConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum, \
+ unsigned long ulStep, \
+ unsigned long ulConfig))ROM_ADCTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCSequenceOverflow \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCSequenceOverflowClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCSequenceUnderflow \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCSequenceUnderflowClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCProcessorTrigger \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCHardwareOversampleConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFactor))ROM_ADCTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCComparatorConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp, \
+ unsigned long ulConfig))ROM_ADCTABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCComparatorRegionSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp, \
+ unsigned long ulLowRef, \
+ unsigned long ulHighRef))ROM_ADCTABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCComparatorReset \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp, \
+ tBoolean bTrigger, \
+ tBoolean bInterrupt))ROM_ADCTABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCComparatorIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCComparatorIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSequenceNum))ROM_ADCTABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCComparatorIntStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCComparatorIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulStatus))ROM_ADCTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCReferenceSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulRef))ROM_ADCTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCReferenceGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCPhaseDelaySet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPhase))ROM_ADCTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ADCPhaseDelayGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[25])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CAN API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntClr))ROM_CANTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANInit \
+ ((void (*)(unsigned long ulBase))ROM_CANTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANEnable \
+ ((void (*)(unsigned long ulBase))ROM_CANTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANDisable \
+ ((void (*)(unsigned long ulBase))ROM_CANTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANBitTimingSet \
+ ((void (*)(unsigned long ulBase, \
+ tCANBitClkParms *pClkParms))ROM_CANTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANBitTimingGet \
+ ((void (*)(unsigned long ulBase, \
+ tCANBitClkParms *pClkParms))ROM_CANTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANMessageSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulObjID, \
+ tCANMsgObject *pMsgObject, \
+ tMsgObjType eMsgType))ROM_CANTABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANMessageGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulObjID, \
+ tCANMsgObject *pMsgObject, \
+ tBoolean bClrPendingInt))ROM_CANTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANStatusGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tCANStsReg eStatusReg))ROM_CANTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANMessageClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulObjID))ROM_CANTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_CANTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_CANTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tCANIntStsReg eIntStsReg))ROM_CANTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANRetryGet \
+ ((tBoolean (*)(unsigned long ulBase))ROM_CANTABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANRetrySet \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bAutoRetry))ROM_CANTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANErrCntrGet \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long *pulRxCount, \
+ unsigned long *pulTxCount))ROM_CANTABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_CANBitRateSet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulSourceClock, \
+ unsigned long ulBitRate))ROM_CANTABLE[16])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Comparator API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ComparatorIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp))ROM_COMPARATORTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ComparatorConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp, \
+ unsigned long ulConfig))ROM_COMPARATORTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ComparatorRefSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulRef))ROM_COMPARATORTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ComparatorValueGet \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long ulComp))ROM_COMPARATORTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ComparatorIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp))ROM_COMPARATORTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ComparatorIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulComp))ROM_COMPARATORTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_ComparatorIntStatus \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long ulComp, \
+ tBoolean bMasked))ROM_COMPARATORTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Ethernet API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_EPITABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIModeSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulMode))ROM_EPITABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIDividerSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDivider))ROM_EPITABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIConfigSDRAMSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig, \
+ unsigned long ulRefresh))ROM_EPITABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIConfigGPModeSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig, \
+ unsigned long ulFrameCount, \
+ unsigned long ulMaxWait))ROM_EPITABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIConfigHB8Set \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig, \
+ unsigned long ulMaxWait))ROM_EPITABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIConfigHB16Set \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig, \
+ unsigned long ulMaxWait))ROM_EPITABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIAddressMapSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulMap))ROM_EPITABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPINonBlockingReadConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel, \
+ unsigned long ulDataSize, \
+ unsigned long ulAddress))ROM_EPITABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPINonBlockingReadStart \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel, \
+ unsigned long ulCount))ROM_EPITABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPINonBlockingReadStop \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_EPITABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPINonBlockingReadCount \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_EPITABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPINonBlockingReadAvail \
+ ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPINonBlockingReadGet32 \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulCount, \
+ unsigned long *pulBuf))ROM_EPITABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPINonBlockingReadGet16 \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulCount, \
+ unsigned short *pusBuf))ROM_EPITABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPINonBlockingReadGet8 \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulCount, \
+ unsigned char *pucBuf))ROM_EPITABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIFIFOConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig))ROM_EPITABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIWriteFIFOCountGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_EPITABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_EPITABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIIntErrorStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_EPITABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EPIIntErrorClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulErrFlags))ROM_EPITABLE[21])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Ethernet API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_ETHERNETTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetInitExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEthClk))ROM_ETHERNETTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetConfigSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig))ROM_ETHERNETTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetConfigGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_ETHERNETTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetMACAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char *pucMACAddr))ROM_ETHERNETTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetMACAddrGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char *pucMACAddr))ROM_ETHERNETTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetEnable \
+ ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetDisable \
+ ((void (*)(unsigned long ulBase))ROM_ETHERNETTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetPacketAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetSpaceAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_ETHERNETTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetPacketGetNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *pucBuf, \
+ long lBufLen))ROM_ETHERNETTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetPacketGet \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *pucBuf, \
+ long lBufLen))ROM_ETHERNETTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetPacketPutNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *pucBuf, \
+ long lBufLen))ROM_ETHERNETTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetPacketPut \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *pucBuf, \
+ long lBufLen))ROM_ETHERNETTABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_ETHERNETTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_ETHERNETTABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_ETHERNETTABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetPHYWrite \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucRegAddr, \
+ unsigned long ulData))ROM_ETHERNETTABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_EthernetPHYRead \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned char ucRegAddr))ROM_ETHERNETTABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UpdateEthernet \
+ ((void (*)(unsigned long ulClock))ROM_ETHERNETTABLE[19])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Flash API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashProgram \
+ ((long (*)(unsigned long *pulData, \
+ unsigned long ulAddress, \
+ unsigned long ulCount))ROM_FLASHTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashUsecGet \
+ ((unsigned long (*)(void))ROM_FLASHTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashUsecSet \
+ ((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashErase \
+ ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashProtectGet \
+ ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashProtectSet \
+ ((long (*)(unsigned long ulAddress, \
+ tFlashProtection eProtect))ROM_FLASHTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashProtectSave \
+ ((long (*)(void))ROM_FLASHTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashUserGet \
+ ((long (*)(unsigned long *pulUser0, \
+ unsigned long *pulUser1))ROM_FLASHTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashUserSet \
+ ((long (*)(unsigned long ulUser0, \
+ unsigned long ulUser1))ROM_FLASHTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashUserSave \
+ ((long (*)(void))ROM_FLASHTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashIntEnable \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashIntDisable \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashIntStatus \
+ ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_FlashIntClear \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the GPIO API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinWrite \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned char ucVal))ROM_GPIOTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIODirModeSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulPinIO))ROM_GPIOTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIODirModeGet \
+ ((unsigned long (*)(unsigned long ulPort, \
+ unsigned char ucPin))ROM_GPIOTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOIntTypeSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulIntType))ROM_GPIOTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOIntTypeGet \
+ ((unsigned long (*)(unsigned long ulPort, \
+ unsigned char ucPin))ROM_GPIOTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPadConfigSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulStrength, \
+ unsigned long ulPadType))ROM_GPIOTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPadConfigGet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPin, \
+ unsigned long *pulStrength, \
+ unsigned long *pulPadType))ROM_GPIOTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinIntEnable \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinIntDisable \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinIntStatus \
+ ((long (*)(unsigned long ulPort, \
+ tBoolean bMasked))ROM_GPIOTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinIntClear \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinRead \
+ ((long (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeCAN \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeComparator \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeGPIOInput \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeGPIOOutput \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeI2C \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypePWM \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeQEI \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeSSI \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeTimer \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeUART \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeGPIOOutputOD \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeADC \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeUSBDigital \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeI2S \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinConfigure \
+ ((void (*)(unsigned long ulPinConfig))ROM_GPIOTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeEthernetLED \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeUSBAnalog \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[28])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeEPI \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[29])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_GPIOPinTypeEthernetMII \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[30])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Hibernate API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateIntClear \
+ ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateEnableExpClk \
+ ((void (*)(unsigned long ulHibClk))ROM_HIBERNATETABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateDisable \
+ ((void (*)(void))ROM_HIBERNATETABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateClockSelect \
+ ((void (*)(unsigned long ulClockInput))ROM_HIBERNATETABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateRTCEnable \
+ ((void (*)(void))ROM_HIBERNATETABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateRTCDisable \
+ ((void (*)(void))ROM_HIBERNATETABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateWakeSet \
+ ((void (*)(unsigned long ulWakeFlags))ROM_HIBERNATETABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateWakeGet \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateLowBatSet \
+ ((void (*)(unsigned long ulLowBatFlags))ROM_HIBERNATETABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateLowBatGet \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateRTCSet \
+ ((void (*)(unsigned long ulRTCValue))ROM_HIBERNATETABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateRTCGet \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateRTCMatch0Set \
+ ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateRTCMatch0Get \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateRTCMatch1Set \
+ ((void (*)(unsigned long ulMatch))ROM_HIBERNATETABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateRTCMatch1Get \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateRTCTrimSet \
+ ((void (*)(unsigned long ulTrim))ROM_HIBERNATETABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateRTCTrimGet \
+ ((unsigned long (*)(void))ROM_HIBERNATETABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateDataSet \
+ ((void (*)(unsigned long *pulData, \
+ unsigned long ulCount))ROM_HIBERNATETABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateDataGet \
+ ((void (*)(unsigned long *pulData, \
+ unsigned long ulCount))ROM_HIBERNATETABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateRequest \
+ ((void (*)(void))ROM_HIBERNATETABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateIntEnable \
+ ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateIntDisable \
+ ((void (*)(unsigned long ulIntFlags))ROM_HIBERNATETABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateIntStatus \
+ ((unsigned long (*)(tBoolean bMasked))ROM_HIBERNATETABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_HibernateIsActive \
+ ((unsigned int (*)(void))ROM_HIBERNATETABLE[24])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2C API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_I2CTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterInitExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulI2CClk, \
+ tBoolean bFast))ROM_I2CTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveInit \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucSlaveAddr))ROM_I2CTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterIntEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveIntEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterIntDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveIntDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterIntStatus \
+ ((tBoolean (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_I2CTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveIntStatus \
+ ((tBoolean (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_I2CTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterIntClear \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveIntClear \
+ ((void (*)(unsigned long ulBase))ROM_I2CTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterSlaveAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucSlaveAddr, \
+ tBoolean bReceive))ROM_I2CTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterBusy \
+ ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterBusBusy \
+ ((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterControl \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulCmd))ROM_I2CTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterErr \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CMasterDataGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_I2CTABLE[22])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveDataGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UpdateI2C \
+ ((void (*)(void))ROM_I2CTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveIntEnableEx \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_I2CTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveIntDisableEx \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_I2CTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveIntStatusEx \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_I2CTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2CSlaveIntClearEx \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_I2CTABLE[28])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2S API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_I2STABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2STxEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2STxDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2STxDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_I2STABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2STxDataPutNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_I2STABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2STxConfigSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig))ROM_I2STABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2STxFIFOLimitSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulLevel))ROM_I2STABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2STxFIFOLimitGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2STxFIFOLevelGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SRxEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SRxDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SRxDataGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulData))ROM_I2STABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SRxDataGetNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long *pulData))ROM_I2STABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SRxConfigSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig))ROM_I2STABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SRxFIFOLimitSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulLevel))ROM_I2STABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SRxFIFOLimitGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SRxFIFOLevelGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2STxRxEnable \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2STxRxDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[18])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2STxRxConfigSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig))ROM_I2STABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SMasterClockSelect \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulMClock))ROM_I2STABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_I2STABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_I2STABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_I2SIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_I2STABLE[23])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Interrupt API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_IntEnable \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_IntMasterEnable \
+ ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_IntMasterDisable \
+ ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_IntDisable \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_IntPriorityGroupingSet \
+ ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_IntPriorityGroupingGet \
+ ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_IntPrioritySet \
+ ((void (*)(unsigned long ulInterrupt, \
+ unsigned char ucPriority))ROM_INTERRUPTTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_IntPriorityGet \
+ ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_IntPendSet \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_IntPendClear \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[9])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the MPU API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_MPUEnable \
+ ((void (*)(unsigned long ulMPUConfig))ROM_MPUTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_MPUDisable \
+ ((void (*)(void))ROM_MPUTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_MPURegionCountGet \
+ ((unsigned long (*)(void))ROM_MPUTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_MPURegionEnable \
+ ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_MPURegionDisable \
+ ((void (*)(unsigned long ulRegion))ROM_MPUTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_MPURegionSet \
+ ((void (*)(unsigned long ulRegion, \
+ unsigned long ulAddr, \
+ unsigned long ulFlags))ROM_MPUTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_MPURegionGet \
+ ((void (*)(unsigned long ulRegion, \
+ unsigned long *pulAddr, \
+ unsigned long *pulFlags))ROM_MPUTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the PWM API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMPulseWidthSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOut, \
+ unsigned long ulWidth))ROM_PWMTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulConfig))ROM_PWMTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenPeriodSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulPeriod))ROM_PWMTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenPeriodGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulGen))ROM_PWMTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen))ROM_PWMTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen))ROM_PWMTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMPulseWidthGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulPWMOut))ROM_PWMTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMDeadBandEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned short usRise, \
+ unsigned short usFall))ROM_PWMTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMDeadBandDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen))ROM_PWMTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMSyncUpdate \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGenBits))ROM_PWMTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMSyncTimeBase \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGenBits))ROM_PWMTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMOutputState \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOutBits, \
+ tBoolean bEnable))ROM_PWMTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMOutputInvert \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOutBits, \
+ tBoolean bInvert))ROM_PWMTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMOutputFault \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOutBits, \
+ tBoolean bFaultSuppress))ROM_PWMTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenIntTrigEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulIntTrig))ROM_PWMTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenIntTrigDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulIntTrig))ROM_PWMTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ tBoolean bMasked))ROM_PWMTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulInts))ROM_PWMTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGenFault))ROM_PWMTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGenFault))ROM_PWMTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMFaultIntClear \
+ ((void (*)(unsigned long ulBase))ROM_PWMTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_PWMTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMOutputFaultLevel \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPWMOutBits, \
+ tBoolean bDriveHigh))ROM_PWMTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMFaultIntClearExt \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFaultInts))ROM_PWMTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenFaultConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulMinFaultPeriod, \
+ unsigned long ulFaultSenses))ROM_PWMTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenFaultTriggerSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulGroup, \
+ unsigned long ulFaultTriggers))ROM_PWMTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenFaultTriggerGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulGroup))ROM_PWMTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenFaultStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulGroup))ROM_PWMTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_PWMGenFaultClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulGen, \
+ unsigned long ulGroup, \
+ unsigned long ulFaultTriggers))ROM_PWMTABLE[28])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the QEI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIPositionGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIEnable \
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIDisable \
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig, \
+ unsigned long ulMaxPosition))ROM_QEITABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIPositionSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPosition))ROM_QEITABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIDirectionGet \
+ ((long (*)(unsigned long ulBase))ROM_QEITABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIErrorGet \
+ ((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIVelocityEnable \
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIVelocityDisable \
+ ((void (*)(unsigned long ulBase))ROM_QEITABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIVelocityConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulPreDiv, \
+ unsigned long ulPeriod))ROM_QEITABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIVelocityGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_QEITABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_QEITABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_QEITABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_QEIIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_QEITABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SSI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SSITABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIConfigSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSSIClk, \
+ unsigned long ulProtocol, \
+ unsigned long ulMode, \
+ unsigned long ulBitRate, \
+ unsigned long ulDataWidth))ROM_SSITABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIEnable \
+ ((void (*)(unsigned long ulBase))ROM_SSITABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIDisable \
+ ((void (*)(unsigned long ulBase))ROM_SSITABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SSITABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SSITABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_SSITABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SSITABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIDataPutNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SSITABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIDataGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulData))ROM_SSITABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIDataGetNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long *pulData))ROM_SSITABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UpdateSSI \
+ ((void (*)(void))ROM_SSITABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIDMAEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_SSITABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIDMADisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_SSITABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SSIBusy \
+ ((tBoolean (*)(unsigned long ulBase))ROM_SSITABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysCtl API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlSleep \
+ ((void (*)(void))ROM_SYSCTLTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlSRAMSizeGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlFlashSizeGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlPinPresent \
+ ((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlPeripheralPresent \
+ ((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlPeripheralReset \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlPeripheralEnable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlPeripheralDisable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlPeripheralSleepEnable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlPeripheralSleepDisable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlPeripheralDeepSleepEnable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlPeripheralDeepSleepDisable \
+ ((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlPeripheralClockGating \
+ ((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlIntEnable \
+ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlIntDisable \
+ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlIntClear \
+ ((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlIntStatus \
+ ((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlLDOSet \
+ ((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlLDOGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlReset \
+ ((void (*)(void))ROM_SYSCTLTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlDeepSleep \
+ ((void (*)(void))ROM_SYSCTLTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlResetCauseGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[21])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlResetCauseClear \
+ ((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlClockSet \
+ ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlClockGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[24])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlPWMClockSet \
+ ((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlPWMClockGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[26])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlADCSpeedSet \
+ ((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlADCSpeedGet \
+ ((unsigned long (*)(void))ROM_SYSCTLTABLE[28])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlGPIOAHBEnable \
+ ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlGPIOAHBDisable \
+ ((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlUSBPLLEnable \
+ ((void (*)(void))ROM_SYSCTLTABLE[31])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlUSBPLLDisable \
+ ((void (*)(void))ROM_SYSCTLTABLE[32])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlI2SMClkSet \
+ ((unsigned long (*)(unsigned long ulInputClock, \
+ unsigned long ulMClk))ROM_SYSCTLTABLE[33])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysCtlDelay \
+ ((void (*)(unsigned long ulCount))ROM_SYSCTLTABLE[34])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SysTick API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysTickValueGet \
+ ((unsigned long (*)(void))ROM_SYSTICKTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysTickEnable \
+ ((void (*)(void))ROM_SYSTICKTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysTickDisable \
+ ((void (*)(void))ROM_SYSTICKTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysTickIntEnable \
+ ((void (*)(void))ROM_SYSTICKTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysTickIntDisable \
+ ((void (*)(void))ROM_SYSTICKTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysTickPeriodSet \
+ ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_SysTickPeriodGet \
+ ((unsigned long (*)(void))ROM_SYSTICKTABLE[6])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Timer API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig))ROM_TIMERTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerControlLevel \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bInvert))ROM_TIMERTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerControlTrigger \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bEnable))ROM_TIMERTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerControlEvent \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulEvent))ROM_TIMERTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerControlStall \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bStall))ROM_TIMERTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerRTCEnable \
+ ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerRTCDisable \
+ ((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerPrescaleSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerPrescaleGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerPrescaleMatchSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerPrescaleMatchGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerLoadSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerLoadGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerValueGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerMatchSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerMatchGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_TIMERTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_TimerControlWaitOnTrigger \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bWait))ROM_TIMERTABLE[22])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the UART API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTCharPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_UARTTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTParityModeSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulParity))ROM_UARTTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTParityModeGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTFIFOLevelSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTxLevel, \
+ unsigned long ulRxLevel))ROM_UARTTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTFIFOLevelGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulTxLevel, \
+ unsigned long *pulRxLevel))ROM_UARTTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTConfigSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulUARTClk, \
+ unsigned long ulBaud, \
+ unsigned long ulConfig))ROM_UARTTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTConfigGetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulUARTClk, \
+ unsigned long *pulBaud, \
+ unsigned long *pulConfig))ROM_UARTTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTEnable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTDisable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTEnableSIR \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bLowPower))ROM_UARTTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTDisableSIR \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTCharsAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTSpaceAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTCharGetNonBlocking \
+ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTCharGet \
+ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[14])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTCharPutNonBlocking \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_UARTTABLE[15])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTBreakCtl \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bBreakState))ROM_UARTTABLE[16])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[17])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[18])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_UARTTABLE[19])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[20])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UpdateUART \
+ ((void (*)(void))ROM_UARTTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTDMAEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_UARTTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTDMADisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_UARTTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTFIFOEnable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTFIFODisable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTBusy \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTTxIntModeSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulMode))ROM_UARTTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTTxIntModeGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[28])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTRxErrorGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[29])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_UARTRxErrorClear \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[30])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the uDMA API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelTransferSet \
+ ((void (*)(unsigned long ulChannelStructIndex, \
+ unsigned long ulMode, \
+ void *pvSrcAddr, \
+ void *pvDstAddr, \
+ unsigned long ulTransferSize))ROM_UDMATABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAEnable \
+ ((void (*)(void))ROM_UDMATABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMADisable \
+ ((void (*)(void))ROM_UDMATABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAErrorStatusGet \
+ ((unsigned long (*)(void))ROM_UDMATABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAErrorStatusClear \
+ ((void (*)(void))ROM_UDMATABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelEnable \
+ ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelDisable \
+ ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelIsEnabled \
+ ((tBoolean (*)(unsigned long ulChannelNum))ROM_UDMATABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAControlBaseSet \
+ ((void (*)(void *pControlTable))ROM_UDMATABLE[8])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAControlBaseGet \
+ ((void * (*)(void))ROM_UDMATABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelRequest \
+ ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelAttributeEnable \
+ ((void (*)(unsigned long ulChannelNum, \
+ unsigned long ulAttr))ROM_UDMATABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelAttributeDisable \
+ ((void (*)(unsigned long ulChannelNum, \
+ unsigned long ulAttr))ROM_UDMATABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelAttributeGet \
+ ((unsigned long (*)(unsigned long ulChannelNum))ROM_UDMATABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelControlSet \
+ ((void (*)(unsigned long ulChannelStructIndex, \
+ unsigned long ulControl))ROM_UDMATABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelSizeGet \
+ ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelModeGet \
+ ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelSelectSecondary \
+ ((void (*)(unsigned long ulSecPeriphs))ROM_UDMATABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_uDMAChannelSelectDefault \
+ ((void (*)(unsigned long ulDefPeriphs))ROM_UDMATABLE[18])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the USB API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBIntStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[0])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBDevAddrGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBDevAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulAddress))ROM_USBTABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBDevConnect \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[3])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBDevDisconnect \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[4])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBDevEndpointConfigSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulMaxPacketSize, \
+ unsigned long ulFlags))ROM_USBTABLE[5])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBDevEndpointDataAck \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ tBoolean bIsLastPacket))ROM_USBTABLE[6])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBDevEndpointStall \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[7])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBDevEndpointStatusClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[9])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBEndpointDataGet \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned char *pucData, \
+ unsigned long *pulSize))ROM_USBTABLE[10])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBEndpointDataPut \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned char *pucData, \
+ unsigned long ulSize))ROM_USBTABLE[11])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBEndpointDataSend \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulTransType))ROM_USBTABLE[12])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBEndpointDataToggleClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[13])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBEndpointStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[14])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBFIFOAddrGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[15])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBFIFOConfigGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long *pulFIFOAddress, \
+ unsigned long *pulFIFOSize, \
+ unsigned long ulFlags))ROM_USBTABLE[16])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBFIFOConfigSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFIFOAddress, \
+ unsigned long ulFIFOSize, \
+ unsigned long ulFlags))ROM_USBTABLE[17])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBFrameNumberGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[19])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostAddrGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[20])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulAddr, \
+ unsigned long ulFlags))ROM_USBTABLE[21])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostEndpointConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulMaxPacketSize, \
+ unsigned long ulNAKPollInterval, \
+ unsigned long ulTargetEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[22])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostEndpointDataAck \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[23])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostEndpointDataToggle \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ tBoolean bDataToggle, \
+ unsigned long ulFlags))ROM_USBTABLE[24])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostEndpointStatusClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[25])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostHubAddrGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulFlags))ROM_USBTABLE[26])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostHubAddrSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulAddr, \
+ unsigned long ulFlags))ROM_USBTABLE[27])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostPwrDisable \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[28])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostPwrEnable \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[29])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostPwrConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFlags))ROM_USBTABLE[30])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostPwrFaultDisable \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[31])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostPwrFaultEnable \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[32])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostRequestIN \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[33])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostRequestStatus \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[34])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostReset \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bStart))ROM_USBTABLE[35])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostResume \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bStart))ROM_USBTABLE[36])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostSpeedGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[37])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBHostSuspend \
+ ((void (*)(unsigned long ulBase))ROM_USBTABLE[38])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_USBTABLE[39])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_USBTABLE[40])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBDevEndpointConfigGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long *pulMaxPacketSize, \
+ unsigned long *pulFlags))ROM_USBTABLE[41])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBEndpointDataAvail \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint))ROM_USBTABLE[44])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBOTGHostRequest \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bHNP))ROM_USBTABLE[45])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBModeGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[46])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBEndpointDMAChannel \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulEndpoint, \
+ unsigned long ulChannel))ROM_USBTABLE[47])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBIntDisableControl \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_USBTABLE[48])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBIntEnableControl \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_USBTABLE[49])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBIntStatusControl \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[50])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBIntDisableEndpoint \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_USBTABLE[51])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBIntEnableEndpoint \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_USBTABLE[52])
+#endif
+#if defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_USBIntStatusEndpoint \
+ ((unsigned long (*)(unsigned long ulBase))ROM_USBTABLE[53])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Watchdog API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogIntClear \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogRunning \
+ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogResetEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogResetDisable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogLock \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogUnlock \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogLockState \
+ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogReloadSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogReloadGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogValueGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogIntEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_WATCHDOGTABLE[12])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogStallEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13])
+#endif
+#if defined(TARGET_IS_DUSTDEVIL_RA0) || \
+ defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_WatchdogStallDisable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Software API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_Crc16Array \
+ ((unsigned short (*)(unsigned long ulWordLen, \
+ const unsigned long *pulData))ROM_SOFTWARETABLE[1])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_Crc16Array3 \
+ ((void (*)(unsigned long ulWordLen, \
+ const unsigned long *pulData, \
+ unsigned short *pusCrc3))ROM_SOFTWARETABLE[2])
+#endif
+#if defined(TARGET_IS_TEMPEST_RB1) || \
+ defined(TARGET_IS_TEMPEST_RC1) || \
+ defined(TARGET_IS_TEMPEST_RC3)
+#define ROM_pvAESTable \
+ ((void *)&(ROM_SOFTWARETABLE[7]))
+#endif
+
+//*****************************************************************************
+//
+// Deprecated ROM functions.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#ifdef ROM_FlashIntStatus
+#define ROM_FlashIntGetStatus \
+ ROM_FlashIntStatus
+#endif
+#ifdef ROM_USBDevEndpointConfigSet
+#define ROM_USBDevEndpointConfig \
+ ROM_USBDevEndpointConfigSet
+#endif
+#ifdef ROM_USBHostPwrConfig
+#define ROM_USBHostPwrFaultConfig \
+ ROM_USBHostPwrConfig
+#endif
+#endif
+
+#endif // __ROM_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/rom_map.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/rom_map.h
new file mode 100644
index 00000000..cc6682f3
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/rom_map.h
@@ -0,0 +1,3444 @@
+//*****************************************************************************
+//
+// rom_map.h - Macros to facilitate calling functions in the ROM when they are
+// available and in flash otherwise.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ROM_MAP_H__
+#define __ROM_MAP_H__
+
+//*****************************************************************************
+//
+// Macros for the ADC API.
+//
+//*****************************************************************************
+#ifdef ROM_ADCSequenceDataGet
+#define MAP_ADCSequenceDataGet \
+ ROM_ADCSequenceDataGet
+#else
+#define MAP_ADCSequenceDataGet \
+ ADCSequenceDataGet
+#endif
+#ifdef ROM_ADCIntDisable
+#define MAP_ADCIntDisable \
+ ROM_ADCIntDisable
+#else
+#define MAP_ADCIntDisable \
+ ADCIntDisable
+#endif
+#ifdef ROM_ADCIntEnable
+#define MAP_ADCIntEnable \
+ ROM_ADCIntEnable
+#else
+#define MAP_ADCIntEnable \
+ ADCIntEnable
+#endif
+#ifdef ROM_ADCIntStatus
+#define MAP_ADCIntStatus \
+ ROM_ADCIntStatus
+#else
+#define MAP_ADCIntStatus \
+ ADCIntStatus
+#endif
+#ifdef ROM_ADCIntClear
+#define MAP_ADCIntClear \
+ ROM_ADCIntClear
+#else
+#define MAP_ADCIntClear \
+ ADCIntClear
+#endif
+#ifdef ROM_ADCSequenceEnable
+#define MAP_ADCSequenceEnable \
+ ROM_ADCSequenceEnable
+#else
+#define MAP_ADCSequenceEnable \
+ ADCSequenceEnable
+#endif
+#ifdef ROM_ADCSequenceDisable
+#define MAP_ADCSequenceDisable \
+ ROM_ADCSequenceDisable
+#else
+#define MAP_ADCSequenceDisable \
+ ADCSequenceDisable
+#endif
+#ifdef ROM_ADCSequenceConfigure
+#define MAP_ADCSequenceConfigure \
+ ROM_ADCSequenceConfigure
+#else
+#define MAP_ADCSequenceConfigure \
+ ADCSequenceConfigure
+#endif
+#ifdef ROM_ADCSequenceStepConfigure
+#define MAP_ADCSequenceStepConfigure \
+ ROM_ADCSequenceStepConfigure
+#else
+#define MAP_ADCSequenceStepConfigure \
+ ADCSequenceStepConfigure
+#endif
+#ifdef ROM_ADCSequenceOverflow
+#define MAP_ADCSequenceOverflow \
+ ROM_ADCSequenceOverflow
+#else
+#define MAP_ADCSequenceOverflow \
+ ADCSequenceOverflow
+#endif
+#ifdef ROM_ADCSequenceOverflowClear
+#define MAP_ADCSequenceOverflowClear \
+ ROM_ADCSequenceOverflowClear
+#else
+#define MAP_ADCSequenceOverflowClear \
+ ADCSequenceOverflowClear
+#endif
+#ifdef ROM_ADCSequenceUnderflow
+#define MAP_ADCSequenceUnderflow \
+ ROM_ADCSequenceUnderflow
+#else
+#define MAP_ADCSequenceUnderflow \
+ ADCSequenceUnderflow
+#endif
+#ifdef ROM_ADCSequenceUnderflowClear
+#define MAP_ADCSequenceUnderflowClear \
+ ROM_ADCSequenceUnderflowClear
+#else
+#define MAP_ADCSequenceUnderflowClear \
+ ADCSequenceUnderflowClear
+#endif
+#ifdef ROM_ADCProcessorTrigger
+#define MAP_ADCProcessorTrigger \
+ ROM_ADCProcessorTrigger
+#else
+#define MAP_ADCProcessorTrigger \
+ ADCProcessorTrigger
+#endif
+#ifdef ROM_ADCHardwareOversampleConfigure
+#define MAP_ADCHardwareOversampleConfigure \
+ ROM_ADCHardwareOversampleConfigure
+#else
+#define MAP_ADCHardwareOversampleConfigure \
+ ADCHardwareOversampleConfigure
+#endif
+#ifdef ROM_ADCComparatorConfigure
+#define MAP_ADCComparatorConfigure \
+ ROM_ADCComparatorConfigure
+#else
+#define MAP_ADCComparatorConfigure \
+ ADCComparatorConfigure
+#endif
+#ifdef ROM_ADCComparatorRegionSet
+#define MAP_ADCComparatorRegionSet \
+ ROM_ADCComparatorRegionSet
+#else
+#define MAP_ADCComparatorRegionSet \
+ ADCComparatorRegionSet
+#endif
+#ifdef ROM_ADCComparatorReset
+#define MAP_ADCComparatorReset \
+ ROM_ADCComparatorReset
+#else
+#define MAP_ADCComparatorReset \
+ ADCComparatorReset
+#endif
+#ifdef ROM_ADCComparatorIntDisable
+#define MAP_ADCComparatorIntDisable \
+ ROM_ADCComparatorIntDisable
+#else
+#define MAP_ADCComparatorIntDisable \
+ ADCComparatorIntDisable
+#endif
+#ifdef ROM_ADCComparatorIntEnable
+#define MAP_ADCComparatorIntEnable \
+ ROM_ADCComparatorIntEnable
+#else
+#define MAP_ADCComparatorIntEnable \
+ ADCComparatorIntEnable
+#endif
+#ifdef ROM_ADCComparatorIntStatus
+#define MAP_ADCComparatorIntStatus \
+ ROM_ADCComparatorIntStatus
+#else
+#define MAP_ADCComparatorIntStatus \
+ ADCComparatorIntStatus
+#endif
+#ifdef ROM_ADCComparatorIntClear
+#define MAP_ADCComparatorIntClear \
+ ROM_ADCComparatorIntClear
+#else
+#define MAP_ADCComparatorIntClear \
+ ADCComparatorIntClear
+#endif
+#ifdef ROM_ADCReferenceSet
+#define MAP_ADCReferenceSet \
+ ROM_ADCReferenceSet
+#else
+#define MAP_ADCReferenceSet \
+ ADCReferenceSet
+#endif
+#ifdef ROM_ADCReferenceGet
+#define MAP_ADCReferenceGet \
+ ROM_ADCReferenceGet
+#else
+#define MAP_ADCReferenceGet \
+ ADCReferenceGet
+#endif
+#ifdef ROM_ADCPhaseDelaySet
+#define MAP_ADCPhaseDelaySet \
+ ROM_ADCPhaseDelaySet
+#else
+#define MAP_ADCPhaseDelaySet \
+ ADCPhaseDelaySet
+#endif
+#ifdef ROM_ADCPhaseDelayGet
+#define MAP_ADCPhaseDelayGet \
+ ROM_ADCPhaseDelayGet
+#else
+#define MAP_ADCPhaseDelayGet \
+ ADCPhaseDelayGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the CAN API.
+//
+//*****************************************************************************
+#ifdef ROM_CANIntClear
+#define MAP_CANIntClear \
+ ROM_CANIntClear
+#else
+#define MAP_CANIntClear \
+ CANIntClear
+#endif
+#ifdef ROM_CANInit
+#define MAP_CANInit \
+ ROM_CANInit
+#else
+#define MAP_CANInit \
+ CANInit
+#endif
+#ifdef ROM_CANEnable
+#define MAP_CANEnable \
+ ROM_CANEnable
+#else
+#define MAP_CANEnable \
+ CANEnable
+#endif
+#ifdef ROM_CANDisable
+#define MAP_CANDisable \
+ ROM_CANDisable
+#else
+#define MAP_CANDisable \
+ CANDisable
+#endif
+#ifdef ROM_CANBitTimingSet
+#define MAP_CANBitTimingSet \
+ ROM_CANBitTimingSet
+#else
+#define MAP_CANBitTimingSet \
+ CANBitTimingSet
+#endif
+#ifdef ROM_CANBitTimingGet
+#define MAP_CANBitTimingGet \
+ ROM_CANBitTimingGet
+#else
+#define MAP_CANBitTimingGet \
+ CANBitTimingGet
+#endif
+#ifdef ROM_CANMessageSet
+#define MAP_CANMessageSet \
+ ROM_CANMessageSet
+#else
+#define MAP_CANMessageSet \
+ CANMessageSet
+#endif
+#ifdef ROM_CANMessageGet
+#define MAP_CANMessageGet \
+ ROM_CANMessageGet
+#else
+#define MAP_CANMessageGet \
+ CANMessageGet
+#endif
+#ifdef ROM_CANStatusGet
+#define MAP_CANStatusGet \
+ ROM_CANStatusGet
+#else
+#define MAP_CANStatusGet \
+ CANStatusGet
+#endif
+#ifdef ROM_CANMessageClear
+#define MAP_CANMessageClear \
+ ROM_CANMessageClear
+#else
+#define MAP_CANMessageClear \
+ CANMessageClear
+#endif
+#ifdef ROM_CANIntEnable
+#define MAP_CANIntEnable \
+ ROM_CANIntEnable
+#else
+#define MAP_CANIntEnable \
+ CANIntEnable
+#endif
+#ifdef ROM_CANIntDisable
+#define MAP_CANIntDisable \
+ ROM_CANIntDisable
+#else
+#define MAP_CANIntDisable \
+ CANIntDisable
+#endif
+#ifdef ROM_CANIntStatus
+#define MAP_CANIntStatus \
+ ROM_CANIntStatus
+#else
+#define MAP_CANIntStatus \
+ CANIntStatus
+#endif
+#ifdef ROM_CANRetryGet
+#define MAP_CANRetryGet \
+ ROM_CANRetryGet
+#else
+#define MAP_CANRetryGet \
+ CANRetryGet
+#endif
+#ifdef ROM_CANRetrySet
+#define MAP_CANRetrySet \
+ ROM_CANRetrySet
+#else
+#define MAP_CANRetrySet \
+ CANRetrySet
+#endif
+#ifdef ROM_CANErrCntrGet
+#define MAP_CANErrCntrGet \
+ ROM_CANErrCntrGet
+#else
+#define MAP_CANErrCntrGet \
+ CANErrCntrGet
+#endif
+#ifdef ROM_CANBitRateSet
+#define MAP_CANBitRateSet \
+ ROM_CANBitRateSet
+#else
+#define MAP_CANBitRateSet \
+ CANBitRateSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Comparator API.
+//
+//*****************************************************************************
+#ifdef ROM_ComparatorIntClear
+#define MAP_ComparatorIntClear \
+ ROM_ComparatorIntClear
+#else
+#define MAP_ComparatorIntClear \
+ ComparatorIntClear
+#endif
+#ifdef ROM_ComparatorConfigure
+#define MAP_ComparatorConfigure \
+ ROM_ComparatorConfigure
+#else
+#define MAP_ComparatorConfigure \
+ ComparatorConfigure
+#endif
+#ifdef ROM_ComparatorRefSet
+#define MAP_ComparatorRefSet \
+ ROM_ComparatorRefSet
+#else
+#define MAP_ComparatorRefSet \
+ ComparatorRefSet
+#endif
+#ifdef ROM_ComparatorValueGet
+#define MAP_ComparatorValueGet \
+ ROM_ComparatorValueGet
+#else
+#define MAP_ComparatorValueGet \
+ ComparatorValueGet
+#endif
+#ifdef ROM_ComparatorIntEnable
+#define MAP_ComparatorIntEnable \
+ ROM_ComparatorIntEnable
+#else
+#define MAP_ComparatorIntEnable \
+ ComparatorIntEnable
+#endif
+#ifdef ROM_ComparatorIntDisable
+#define MAP_ComparatorIntDisable \
+ ROM_ComparatorIntDisable
+#else
+#define MAP_ComparatorIntDisable \
+ ComparatorIntDisable
+#endif
+#ifdef ROM_ComparatorIntStatus
+#define MAP_ComparatorIntStatus \
+ ROM_ComparatorIntStatus
+#else
+#define MAP_ComparatorIntStatus \
+ ComparatorIntStatus
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Ethernet API.
+//
+//*****************************************************************************
+#ifdef ROM_EPIIntStatus
+#define MAP_EPIIntStatus \
+ ROM_EPIIntStatus
+#else
+#define MAP_EPIIntStatus \
+ EPIIntStatus
+#endif
+#ifdef ROM_EPIModeSet
+#define MAP_EPIModeSet \
+ ROM_EPIModeSet
+#else
+#define MAP_EPIModeSet \
+ EPIModeSet
+#endif
+#ifdef ROM_EPIDividerSet
+#define MAP_EPIDividerSet \
+ ROM_EPIDividerSet
+#else
+#define MAP_EPIDividerSet \
+ EPIDividerSet
+#endif
+#ifdef ROM_EPIConfigSDRAMSet
+#define MAP_EPIConfigSDRAMSet \
+ ROM_EPIConfigSDRAMSet
+#else
+#define MAP_EPIConfigSDRAMSet \
+ EPIConfigSDRAMSet
+#endif
+#ifdef ROM_EPIConfigGPModeSet
+#define MAP_EPIConfigGPModeSet \
+ ROM_EPIConfigGPModeSet
+#else
+#define MAP_EPIConfigGPModeSet \
+ EPIConfigGPModeSet
+#endif
+#ifdef ROM_EPIConfigHB8Set
+#define MAP_EPIConfigHB8Set \
+ ROM_EPIConfigHB8Set
+#else
+#define MAP_EPIConfigHB8Set \
+ EPIConfigHB8Set
+#endif
+#ifdef ROM_EPIConfigHB16Set
+#define MAP_EPIConfigHB16Set \
+ ROM_EPIConfigHB16Set
+#else
+#define MAP_EPIConfigHB16Set \
+ EPIConfigHB16Set
+#endif
+#ifdef ROM_EPIAddressMapSet
+#define MAP_EPIAddressMapSet \
+ ROM_EPIAddressMapSet
+#else
+#define MAP_EPIAddressMapSet \
+ EPIAddressMapSet
+#endif
+#ifdef ROM_EPINonBlockingReadConfigure
+#define MAP_EPINonBlockingReadConfigure \
+ ROM_EPINonBlockingReadConfigure
+#else
+#define MAP_EPINonBlockingReadConfigure \
+ EPINonBlockingReadConfigure
+#endif
+#ifdef ROM_EPINonBlockingReadStart
+#define MAP_EPINonBlockingReadStart \
+ ROM_EPINonBlockingReadStart
+#else
+#define MAP_EPINonBlockingReadStart \
+ EPINonBlockingReadStart
+#endif
+#ifdef ROM_EPINonBlockingReadStop
+#define MAP_EPINonBlockingReadStop \
+ ROM_EPINonBlockingReadStop
+#else
+#define MAP_EPINonBlockingReadStop \
+ EPINonBlockingReadStop
+#endif
+#ifdef ROM_EPINonBlockingReadCount
+#define MAP_EPINonBlockingReadCount \
+ ROM_EPINonBlockingReadCount
+#else
+#define MAP_EPINonBlockingReadCount \
+ EPINonBlockingReadCount
+#endif
+#ifdef ROM_EPINonBlockingReadAvail
+#define MAP_EPINonBlockingReadAvail \
+ ROM_EPINonBlockingReadAvail
+#else
+#define MAP_EPINonBlockingReadAvail \
+ EPINonBlockingReadAvail
+#endif
+#ifdef ROM_EPINonBlockingReadGet32
+#define MAP_EPINonBlockingReadGet32 \
+ ROM_EPINonBlockingReadGet32
+#else
+#define MAP_EPINonBlockingReadGet32 \
+ EPINonBlockingReadGet32
+#endif
+#ifdef ROM_EPINonBlockingReadGet16
+#define MAP_EPINonBlockingReadGet16 \
+ ROM_EPINonBlockingReadGet16
+#else
+#define MAP_EPINonBlockingReadGet16 \
+ EPINonBlockingReadGet16
+#endif
+#ifdef ROM_EPINonBlockingReadGet8
+#define MAP_EPINonBlockingReadGet8 \
+ ROM_EPINonBlockingReadGet8
+#else
+#define MAP_EPINonBlockingReadGet8 \
+ EPINonBlockingReadGet8
+#endif
+#ifdef ROM_EPIFIFOConfig
+#define MAP_EPIFIFOConfig \
+ ROM_EPIFIFOConfig
+#else
+#define MAP_EPIFIFOConfig \
+ EPIFIFOConfig
+#endif
+#ifdef ROM_EPIWriteFIFOCountGet
+#define MAP_EPIWriteFIFOCountGet \
+ ROM_EPIWriteFIFOCountGet
+#else
+#define MAP_EPIWriteFIFOCountGet \
+ EPIWriteFIFOCountGet
+#endif
+#ifdef ROM_EPIIntEnable
+#define MAP_EPIIntEnable \
+ ROM_EPIIntEnable
+#else
+#define MAP_EPIIntEnable \
+ EPIIntEnable
+#endif
+#ifdef ROM_EPIIntDisable
+#define MAP_EPIIntDisable \
+ ROM_EPIIntDisable
+#else
+#define MAP_EPIIntDisable \
+ EPIIntDisable
+#endif
+#ifdef ROM_EPIIntErrorStatus
+#define MAP_EPIIntErrorStatus \
+ ROM_EPIIntErrorStatus
+#else
+#define MAP_EPIIntErrorStatus \
+ EPIIntErrorStatus
+#endif
+#ifdef ROM_EPIIntErrorClear
+#define MAP_EPIIntErrorClear \
+ ROM_EPIIntErrorClear
+#else
+#define MAP_EPIIntErrorClear \
+ EPIIntErrorClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Ethernet API.
+//
+//*****************************************************************************
+#ifdef ROM_EthernetIntClear
+#define MAP_EthernetIntClear \
+ ROM_EthernetIntClear
+#else
+#define MAP_EthernetIntClear \
+ EthernetIntClear
+#endif
+#ifdef ROM_EthernetInitExpClk
+#define MAP_EthernetInitExpClk \
+ ROM_EthernetInitExpClk
+#else
+#define MAP_EthernetInitExpClk \
+ EthernetInitExpClk
+#endif
+#ifdef ROM_EthernetConfigSet
+#define MAP_EthernetConfigSet \
+ ROM_EthernetConfigSet
+#else
+#define MAP_EthernetConfigSet \
+ EthernetConfigSet
+#endif
+#ifdef ROM_EthernetConfigGet
+#define MAP_EthernetConfigGet \
+ ROM_EthernetConfigGet
+#else
+#define MAP_EthernetConfigGet \
+ EthernetConfigGet
+#endif
+#ifdef ROM_EthernetMACAddrSet
+#define MAP_EthernetMACAddrSet \
+ ROM_EthernetMACAddrSet
+#else
+#define MAP_EthernetMACAddrSet \
+ EthernetMACAddrSet
+#endif
+#ifdef ROM_EthernetMACAddrGet
+#define MAP_EthernetMACAddrGet \
+ ROM_EthernetMACAddrGet
+#else
+#define MAP_EthernetMACAddrGet \
+ EthernetMACAddrGet
+#endif
+#ifdef ROM_EthernetEnable
+#define MAP_EthernetEnable \
+ ROM_EthernetEnable
+#else
+#define MAP_EthernetEnable \
+ EthernetEnable
+#endif
+#ifdef ROM_EthernetDisable
+#define MAP_EthernetDisable \
+ ROM_EthernetDisable
+#else
+#define MAP_EthernetDisable \
+ EthernetDisable
+#endif
+#ifdef ROM_EthernetPacketAvail
+#define MAP_EthernetPacketAvail \
+ ROM_EthernetPacketAvail
+#else
+#define MAP_EthernetPacketAvail \
+ EthernetPacketAvail
+#endif
+#ifdef ROM_EthernetSpaceAvail
+#define MAP_EthernetSpaceAvail \
+ ROM_EthernetSpaceAvail
+#else
+#define MAP_EthernetSpaceAvail \
+ EthernetSpaceAvail
+#endif
+#ifdef ROM_EthernetPacketGetNonBlocking
+#define MAP_EthernetPacketGetNonBlocking \
+ ROM_EthernetPacketGetNonBlocking
+#else
+#define MAP_EthernetPacketGetNonBlocking \
+ EthernetPacketGetNonBlocking
+#endif
+#ifdef ROM_EthernetPacketGet
+#define MAP_EthernetPacketGet \
+ ROM_EthernetPacketGet
+#else
+#define MAP_EthernetPacketGet \
+ EthernetPacketGet
+#endif
+#ifdef ROM_EthernetPacketPutNonBlocking
+#define MAP_EthernetPacketPutNonBlocking \
+ ROM_EthernetPacketPutNonBlocking
+#else
+#define MAP_EthernetPacketPutNonBlocking \
+ EthernetPacketPutNonBlocking
+#endif
+#ifdef ROM_EthernetPacketPut
+#define MAP_EthernetPacketPut \
+ ROM_EthernetPacketPut
+#else
+#define MAP_EthernetPacketPut \
+ EthernetPacketPut
+#endif
+#ifdef ROM_EthernetIntEnable
+#define MAP_EthernetIntEnable \
+ ROM_EthernetIntEnable
+#else
+#define MAP_EthernetIntEnable \
+ EthernetIntEnable
+#endif
+#ifdef ROM_EthernetIntDisable
+#define MAP_EthernetIntDisable \
+ ROM_EthernetIntDisable
+#else
+#define MAP_EthernetIntDisable \
+ EthernetIntDisable
+#endif
+#ifdef ROM_EthernetIntStatus
+#define MAP_EthernetIntStatus \
+ ROM_EthernetIntStatus
+#else
+#define MAP_EthernetIntStatus \
+ EthernetIntStatus
+#endif
+#ifdef ROM_EthernetPHYWrite
+#define MAP_EthernetPHYWrite \
+ ROM_EthernetPHYWrite
+#else
+#define MAP_EthernetPHYWrite \
+ EthernetPHYWrite
+#endif
+#ifdef ROM_EthernetPHYRead
+#define MAP_EthernetPHYRead \
+ ROM_EthernetPHYRead
+#else
+#define MAP_EthernetPHYRead \
+ EthernetPHYRead
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Flash API.
+//
+//*****************************************************************************
+#ifdef ROM_FlashProgram
+#define MAP_FlashProgram \
+ ROM_FlashProgram
+#else
+#define MAP_FlashProgram \
+ FlashProgram
+#endif
+#ifdef ROM_FlashUsecGet
+#define MAP_FlashUsecGet \
+ ROM_FlashUsecGet
+#else
+#define MAP_FlashUsecGet \
+ FlashUsecGet
+#endif
+#ifdef ROM_FlashUsecSet
+#define MAP_FlashUsecSet \
+ ROM_FlashUsecSet
+#else
+#define MAP_FlashUsecSet \
+ FlashUsecSet
+#endif
+#ifdef ROM_FlashErase
+#define MAP_FlashErase \
+ ROM_FlashErase
+#else
+#define MAP_FlashErase \
+ FlashErase
+#endif
+#ifdef ROM_FlashProtectGet
+#define MAP_FlashProtectGet \
+ ROM_FlashProtectGet
+#else
+#define MAP_FlashProtectGet \
+ FlashProtectGet
+#endif
+#ifdef ROM_FlashProtectSet
+#define MAP_FlashProtectSet \
+ ROM_FlashProtectSet
+#else
+#define MAP_FlashProtectSet \
+ FlashProtectSet
+#endif
+#ifdef ROM_FlashProtectSave
+#define MAP_FlashProtectSave \
+ ROM_FlashProtectSave
+#else
+#define MAP_FlashProtectSave \
+ FlashProtectSave
+#endif
+#ifdef ROM_FlashUserGet
+#define MAP_FlashUserGet \
+ ROM_FlashUserGet
+#else
+#define MAP_FlashUserGet \
+ FlashUserGet
+#endif
+#ifdef ROM_FlashUserSet
+#define MAP_FlashUserSet \
+ ROM_FlashUserSet
+#else
+#define MAP_FlashUserSet \
+ FlashUserSet
+#endif
+#ifdef ROM_FlashUserSave
+#define MAP_FlashUserSave \
+ ROM_FlashUserSave
+#else
+#define MAP_FlashUserSave \
+ FlashUserSave
+#endif
+#ifdef ROM_FlashIntEnable
+#define MAP_FlashIntEnable \
+ ROM_FlashIntEnable
+#else
+#define MAP_FlashIntEnable \
+ FlashIntEnable
+#endif
+#ifdef ROM_FlashIntDisable
+#define MAP_FlashIntDisable \
+ ROM_FlashIntDisable
+#else
+#define MAP_FlashIntDisable \
+ FlashIntDisable
+#endif
+#ifdef ROM_FlashIntStatus
+#define MAP_FlashIntStatus \
+ ROM_FlashIntStatus
+#else
+#define MAP_FlashIntStatus \
+ FlashIntStatus
+#endif
+#ifdef ROM_FlashIntClear
+#define MAP_FlashIntClear \
+ ROM_FlashIntClear
+#else
+#define MAP_FlashIntClear \
+ FlashIntClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the GPIO API.
+//
+//*****************************************************************************
+#ifdef ROM_GPIOPinWrite
+#define MAP_GPIOPinWrite \
+ ROM_GPIOPinWrite
+#else
+#define MAP_GPIOPinWrite \
+ GPIOPinWrite
+#endif
+#ifdef ROM_GPIODirModeSet
+#define MAP_GPIODirModeSet \
+ ROM_GPIODirModeSet
+#else
+#define MAP_GPIODirModeSet \
+ GPIODirModeSet
+#endif
+#ifdef ROM_GPIODirModeGet
+#define MAP_GPIODirModeGet \
+ ROM_GPIODirModeGet
+#else
+#define MAP_GPIODirModeGet \
+ GPIODirModeGet
+#endif
+#ifdef ROM_GPIOIntTypeSet
+#define MAP_GPIOIntTypeSet \
+ ROM_GPIOIntTypeSet
+#else
+#define MAP_GPIOIntTypeSet \
+ GPIOIntTypeSet
+#endif
+#ifdef ROM_GPIOIntTypeGet
+#define MAP_GPIOIntTypeGet \
+ ROM_GPIOIntTypeGet
+#else
+#define MAP_GPIOIntTypeGet \
+ GPIOIntTypeGet
+#endif
+#ifdef ROM_GPIOPadConfigSet
+#define MAP_GPIOPadConfigSet \
+ ROM_GPIOPadConfigSet
+#else
+#define MAP_GPIOPadConfigSet \
+ GPIOPadConfigSet
+#endif
+#ifdef ROM_GPIOPadConfigGet
+#define MAP_GPIOPadConfigGet \
+ ROM_GPIOPadConfigGet
+#else
+#define MAP_GPIOPadConfigGet \
+ GPIOPadConfigGet
+#endif
+#ifdef ROM_GPIOPinIntEnable
+#define MAP_GPIOPinIntEnable \
+ ROM_GPIOPinIntEnable
+#else
+#define MAP_GPIOPinIntEnable \
+ GPIOPinIntEnable
+#endif
+#ifdef ROM_GPIOPinIntDisable
+#define MAP_GPIOPinIntDisable \
+ ROM_GPIOPinIntDisable
+#else
+#define MAP_GPIOPinIntDisable \
+ GPIOPinIntDisable
+#endif
+#ifdef ROM_GPIOPinIntStatus
+#define MAP_GPIOPinIntStatus \
+ ROM_GPIOPinIntStatus
+#else
+#define MAP_GPIOPinIntStatus \
+ GPIOPinIntStatus
+#endif
+#ifdef ROM_GPIOPinIntClear
+#define MAP_GPIOPinIntClear \
+ ROM_GPIOPinIntClear
+#else
+#define MAP_GPIOPinIntClear \
+ GPIOPinIntClear
+#endif
+#ifdef ROM_GPIOPinRead
+#define MAP_GPIOPinRead \
+ ROM_GPIOPinRead
+#else
+#define MAP_GPIOPinRead \
+ GPIOPinRead
+#endif
+#ifdef ROM_GPIOPinTypeCAN
+#define MAP_GPIOPinTypeCAN \
+ ROM_GPIOPinTypeCAN
+#else
+#define MAP_GPIOPinTypeCAN \
+ GPIOPinTypeCAN
+#endif
+#ifdef ROM_GPIOPinTypeComparator
+#define MAP_GPIOPinTypeComparator \
+ ROM_GPIOPinTypeComparator
+#else
+#define MAP_GPIOPinTypeComparator \
+ GPIOPinTypeComparator
+#endif
+#ifdef ROM_GPIOPinTypeGPIOInput
+#define MAP_GPIOPinTypeGPIOInput \
+ ROM_GPIOPinTypeGPIOInput
+#else
+#define MAP_GPIOPinTypeGPIOInput \
+ GPIOPinTypeGPIOInput
+#endif
+#ifdef ROM_GPIOPinTypeGPIOOutput
+#define MAP_GPIOPinTypeGPIOOutput \
+ ROM_GPIOPinTypeGPIOOutput
+#else
+#define MAP_GPIOPinTypeGPIOOutput \
+ GPIOPinTypeGPIOOutput
+#endif
+#ifdef ROM_GPIOPinTypeI2C
+#define MAP_GPIOPinTypeI2C \
+ ROM_GPIOPinTypeI2C
+#else
+#define MAP_GPIOPinTypeI2C \
+ GPIOPinTypeI2C
+#endif
+#ifdef ROM_GPIOPinTypePWM
+#define MAP_GPIOPinTypePWM \
+ ROM_GPIOPinTypePWM
+#else
+#define MAP_GPIOPinTypePWM \
+ GPIOPinTypePWM
+#endif
+#ifdef ROM_GPIOPinTypeQEI
+#define MAP_GPIOPinTypeQEI \
+ ROM_GPIOPinTypeQEI
+#else
+#define MAP_GPIOPinTypeQEI \
+ GPIOPinTypeQEI
+#endif
+#ifdef ROM_GPIOPinTypeSSI
+#define MAP_GPIOPinTypeSSI \
+ ROM_GPIOPinTypeSSI
+#else
+#define MAP_GPIOPinTypeSSI \
+ GPIOPinTypeSSI
+#endif
+#ifdef ROM_GPIOPinTypeTimer
+#define MAP_GPIOPinTypeTimer \
+ ROM_GPIOPinTypeTimer
+#else
+#define MAP_GPIOPinTypeTimer \
+ GPIOPinTypeTimer
+#endif
+#ifdef ROM_GPIOPinTypeUART
+#define MAP_GPIOPinTypeUART \
+ ROM_GPIOPinTypeUART
+#else
+#define MAP_GPIOPinTypeUART \
+ GPIOPinTypeUART
+#endif
+#ifdef ROM_GPIOPinTypeGPIOOutputOD
+#define MAP_GPIOPinTypeGPIOOutputOD \
+ ROM_GPIOPinTypeGPIOOutputOD
+#else
+#define MAP_GPIOPinTypeGPIOOutputOD \
+ GPIOPinTypeGPIOOutputOD
+#endif
+#ifdef ROM_GPIOPinTypeADC
+#define MAP_GPIOPinTypeADC \
+ ROM_GPIOPinTypeADC
+#else
+#define MAP_GPIOPinTypeADC \
+ GPIOPinTypeADC
+#endif
+#ifdef ROM_GPIOPinTypeUSBDigital
+#define MAP_GPIOPinTypeUSBDigital \
+ ROM_GPIOPinTypeUSBDigital
+#else
+#define MAP_GPIOPinTypeUSBDigital \
+ GPIOPinTypeUSBDigital
+#endif
+#ifdef ROM_GPIOPinTypeI2S
+#define MAP_GPIOPinTypeI2S \
+ ROM_GPIOPinTypeI2S
+#else
+#define MAP_GPIOPinTypeI2S \
+ GPIOPinTypeI2S
+#endif
+#ifdef ROM_GPIOPinConfigure
+#define MAP_GPIOPinConfigure \
+ ROM_GPIOPinConfigure
+#else
+#define MAP_GPIOPinConfigure \
+ GPIOPinConfigure
+#endif
+#ifdef ROM_GPIOPinTypeEthernetLED
+#define MAP_GPIOPinTypeEthernetLED \
+ ROM_GPIOPinTypeEthernetLED
+#else
+#define MAP_GPIOPinTypeEthernetLED \
+ GPIOPinTypeEthernetLED
+#endif
+#ifdef ROM_GPIOPinTypeUSBAnalog
+#define MAP_GPIOPinTypeUSBAnalog \
+ ROM_GPIOPinTypeUSBAnalog
+#else
+#define MAP_GPIOPinTypeUSBAnalog \
+ GPIOPinTypeUSBAnalog
+#endif
+#ifdef ROM_GPIOPinTypeEPI
+#define MAP_GPIOPinTypeEPI \
+ ROM_GPIOPinTypeEPI
+#else
+#define MAP_GPIOPinTypeEPI \
+ GPIOPinTypeEPI
+#endif
+#ifdef ROM_GPIOPinTypeEthernetMII
+#define MAP_GPIOPinTypeEthernetMII \
+ ROM_GPIOPinTypeEthernetMII
+#else
+#define MAP_GPIOPinTypeEthernetMII \
+ GPIOPinTypeEthernetMII
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Hibernate API.
+//
+//*****************************************************************************
+#ifdef ROM_HibernateIntClear
+#define MAP_HibernateIntClear \
+ ROM_HibernateIntClear
+#else
+#define MAP_HibernateIntClear \
+ HibernateIntClear
+#endif
+#ifdef ROM_HibernateEnableExpClk
+#define MAP_HibernateEnableExpClk \
+ ROM_HibernateEnableExpClk
+#else
+#define MAP_HibernateEnableExpClk \
+ HibernateEnableExpClk
+#endif
+#ifdef ROM_HibernateDisable
+#define MAP_HibernateDisable \
+ ROM_HibernateDisable
+#else
+#define MAP_HibernateDisable \
+ HibernateDisable
+#endif
+#ifdef ROM_HibernateClockSelect
+#define MAP_HibernateClockSelect \
+ ROM_HibernateClockSelect
+#else
+#define MAP_HibernateClockSelect \
+ HibernateClockSelect
+#endif
+#ifdef ROM_HibernateRTCEnable
+#define MAP_HibernateRTCEnable \
+ ROM_HibernateRTCEnable
+#else
+#define MAP_HibernateRTCEnable \
+ HibernateRTCEnable
+#endif
+#ifdef ROM_HibernateRTCDisable
+#define MAP_HibernateRTCDisable \
+ ROM_HibernateRTCDisable
+#else
+#define MAP_HibernateRTCDisable \
+ HibernateRTCDisable
+#endif
+#ifdef ROM_HibernateWakeSet
+#define MAP_HibernateWakeSet \
+ ROM_HibernateWakeSet
+#else
+#define MAP_HibernateWakeSet \
+ HibernateWakeSet
+#endif
+#ifdef ROM_HibernateWakeGet
+#define MAP_HibernateWakeGet \
+ ROM_HibernateWakeGet
+#else
+#define MAP_HibernateWakeGet \
+ HibernateWakeGet
+#endif
+#ifdef ROM_HibernateLowBatSet
+#define MAP_HibernateLowBatSet \
+ ROM_HibernateLowBatSet
+#else
+#define MAP_HibernateLowBatSet \
+ HibernateLowBatSet
+#endif
+#ifdef ROM_HibernateLowBatGet
+#define MAP_HibernateLowBatGet \
+ ROM_HibernateLowBatGet
+#else
+#define MAP_HibernateLowBatGet \
+ HibernateLowBatGet
+#endif
+#ifdef ROM_HibernateRTCSet
+#define MAP_HibernateRTCSet \
+ ROM_HibernateRTCSet
+#else
+#define MAP_HibernateRTCSet \
+ HibernateRTCSet
+#endif
+#ifdef ROM_HibernateRTCGet
+#define MAP_HibernateRTCGet \
+ ROM_HibernateRTCGet
+#else
+#define MAP_HibernateRTCGet \
+ HibernateRTCGet
+#endif
+#ifdef ROM_HibernateRTCMatch0Set
+#define MAP_HibernateRTCMatch0Set \
+ ROM_HibernateRTCMatch0Set
+#else
+#define MAP_HibernateRTCMatch0Set \
+ HibernateRTCMatch0Set
+#endif
+#ifdef ROM_HibernateRTCMatch0Get
+#define MAP_HibernateRTCMatch0Get \
+ ROM_HibernateRTCMatch0Get
+#else
+#define MAP_HibernateRTCMatch0Get \
+ HibernateRTCMatch0Get
+#endif
+#ifdef ROM_HibernateRTCMatch1Set
+#define MAP_HibernateRTCMatch1Set \
+ ROM_HibernateRTCMatch1Set
+#else
+#define MAP_HibernateRTCMatch1Set \
+ HibernateRTCMatch1Set
+#endif
+#ifdef ROM_HibernateRTCMatch1Get
+#define MAP_HibernateRTCMatch1Get \
+ ROM_HibernateRTCMatch1Get
+#else
+#define MAP_HibernateRTCMatch1Get \
+ HibernateRTCMatch1Get
+#endif
+#ifdef ROM_HibernateRTCTrimSet
+#define MAP_HibernateRTCTrimSet \
+ ROM_HibernateRTCTrimSet
+#else
+#define MAP_HibernateRTCTrimSet \
+ HibernateRTCTrimSet
+#endif
+#ifdef ROM_HibernateRTCTrimGet
+#define MAP_HibernateRTCTrimGet \
+ ROM_HibernateRTCTrimGet
+#else
+#define MAP_HibernateRTCTrimGet \
+ HibernateRTCTrimGet
+#endif
+#ifdef ROM_HibernateDataSet
+#define MAP_HibernateDataSet \
+ ROM_HibernateDataSet
+#else
+#define MAP_HibernateDataSet \
+ HibernateDataSet
+#endif
+#ifdef ROM_HibernateDataGet
+#define MAP_HibernateDataGet \
+ ROM_HibernateDataGet
+#else
+#define MAP_HibernateDataGet \
+ HibernateDataGet
+#endif
+#ifdef ROM_HibernateRequest
+#define MAP_HibernateRequest \
+ ROM_HibernateRequest
+#else
+#define MAP_HibernateRequest \
+ HibernateRequest
+#endif
+#ifdef ROM_HibernateIntEnable
+#define MAP_HibernateIntEnable \
+ ROM_HibernateIntEnable
+#else
+#define MAP_HibernateIntEnable \
+ HibernateIntEnable
+#endif
+#ifdef ROM_HibernateIntDisable
+#define MAP_HibernateIntDisable \
+ ROM_HibernateIntDisable
+#else
+#define MAP_HibernateIntDisable \
+ HibernateIntDisable
+#endif
+#ifdef ROM_HibernateIntStatus
+#define MAP_HibernateIntStatus \
+ ROM_HibernateIntStatus
+#else
+#define MAP_HibernateIntStatus \
+ HibernateIntStatus
+#endif
+#ifdef ROM_HibernateIsActive
+#define MAP_HibernateIsActive \
+ ROM_HibernateIsActive
+#else
+#define MAP_HibernateIsActive \
+ HibernateIsActive
+#endif
+
+//*****************************************************************************
+//
+// Macros for the I2C API.
+//
+//*****************************************************************************
+#ifdef ROM_I2CMasterDataPut
+#define MAP_I2CMasterDataPut \
+ ROM_I2CMasterDataPut
+#else
+#define MAP_I2CMasterDataPut \
+ I2CMasterDataPut
+#endif
+#ifdef ROM_I2CMasterInitExpClk
+#define MAP_I2CMasterInitExpClk \
+ ROM_I2CMasterInitExpClk
+#else
+#define MAP_I2CMasterInitExpClk \
+ I2CMasterInitExpClk
+#endif
+#ifdef ROM_I2CSlaveInit
+#define MAP_I2CSlaveInit \
+ ROM_I2CSlaveInit
+#else
+#define MAP_I2CSlaveInit \
+ I2CSlaveInit
+#endif
+#ifdef ROM_I2CMasterEnable
+#define MAP_I2CMasterEnable \
+ ROM_I2CMasterEnable
+#else
+#define MAP_I2CMasterEnable \
+ I2CMasterEnable
+#endif
+#ifdef ROM_I2CSlaveEnable
+#define MAP_I2CSlaveEnable \
+ ROM_I2CSlaveEnable
+#else
+#define MAP_I2CSlaveEnable \
+ I2CSlaveEnable
+#endif
+#ifdef ROM_I2CMasterDisable
+#define MAP_I2CMasterDisable \
+ ROM_I2CMasterDisable
+#else
+#define MAP_I2CMasterDisable \
+ I2CMasterDisable
+#endif
+#ifdef ROM_I2CSlaveDisable
+#define MAP_I2CSlaveDisable \
+ ROM_I2CSlaveDisable
+#else
+#define MAP_I2CSlaveDisable \
+ I2CSlaveDisable
+#endif
+#ifdef ROM_I2CMasterIntEnable
+#define MAP_I2CMasterIntEnable \
+ ROM_I2CMasterIntEnable
+#else
+#define MAP_I2CMasterIntEnable \
+ I2CMasterIntEnable
+#endif
+#ifdef ROM_I2CSlaveIntEnable
+#define MAP_I2CSlaveIntEnable \
+ ROM_I2CSlaveIntEnable
+#else
+#define MAP_I2CSlaveIntEnable \
+ I2CSlaveIntEnable
+#endif
+#ifdef ROM_I2CMasterIntDisable
+#define MAP_I2CMasterIntDisable \
+ ROM_I2CMasterIntDisable
+#else
+#define MAP_I2CMasterIntDisable \
+ I2CMasterIntDisable
+#endif
+#ifdef ROM_I2CSlaveIntDisable
+#define MAP_I2CSlaveIntDisable \
+ ROM_I2CSlaveIntDisable
+#else
+#define MAP_I2CSlaveIntDisable \
+ I2CSlaveIntDisable
+#endif
+#ifdef ROM_I2CMasterIntStatus
+#define MAP_I2CMasterIntStatus \
+ ROM_I2CMasterIntStatus
+#else
+#define MAP_I2CMasterIntStatus \
+ I2CMasterIntStatus
+#endif
+#ifdef ROM_I2CSlaveIntStatus
+#define MAP_I2CSlaveIntStatus \
+ ROM_I2CSlaveIntStatus
+#else
+#define MAP_I2CSlaveIntStatus \
+ I2CSlaveIntStatus
+#endif
+#ifdef ROM_I2CMasterIntClear
+#define MAP_I2CMasterIntClear \
+ ROM_I2CMasterIntClear
+#else
+#define MAP_I2CMasterIntClear \
+ I2CMasterIntClear
+#endif
+#ifdef ROM_I2CSlaveIntClear
+#define MAP_I2CSlaveIntClear \
+ ROM_I2CSlaveIntClear
+#else
+#define MAP_I2CSlaveIntClear \
+ I2CSlaveIntClear
+#endif
+#ifdef ROM_I2CMasterSlaveAddrSet
+#define MAP_I2CMasterSlaveAddrSet \
+ ROM_I2CMasterSlaveAddrSet
+#else
+#define MAP_I2CMasterSlaveAddrSet \
+ I2CMasterSlaveAddrSet
+#endif
+#ifdef ROM_I2CMasterBusy
+#define MAP_I2CMasterBusy \
+ ROM_I2CMasterBusy
+#else
+#define MAP_I2CMasterBusy \
+ I2CMasterBusy
+#endif
+#ifdef ROM_I2CMasterBusBusy
+#define MAP_I2CMasterBusBusy \
+ ROM_I2CMasterBusBusy
+#else
+#define MAP_I2CMasterBusBusy \
+ I2CMasterBusBusy
+#endif
+#ifdef ROM_I2CMasterControl
+#define MAP_I2CMasterControl \
+ ROM_I2CMasterControl
+#else
+#define MAP_I2CMasterControl \
+ I2CMasterControl
+#endif
+#ifdef ROM_I2CMasterErr
+#define MAP_I2CMasterErr \
+ ROM_I2CMasterErr
+#else
+#define MAP_I2CMasterErr \
+ I2CMasterErr
+#endif
+#ifdef ROM_I2CMasterDataGet
+#define MAP_I2CMasterDataGet \
+ ROM_I2CMasterDataGet
+#else
+#define MAP_I2CMasterDataGet \
+ I2CMasterDataGet
+#endif
+#ifdef ROM_I2CSlaveStatus
+#define MAP_I2CSlaveStatus \
+ ROM_I2CSlaveStatus
+#else
+#define MAP_I2CSlaveStatus \
+ I2CSlaveStatus
+#endif
+#ifdef ROM_I2CSlaveDataPut
+#define MAP_I2CSlaveDataPut \
+ ROM_I2CSlaveDataPut
+#else
+#define MAP_I2CSlaveDataPut \
+ I2CSlaveDataPut
+#endif
+#ifdef ROM_I2CSlaveDataGet
+#define MAP_I2CSlaveDataGet \
+ ROM_I2CSlaveDataGet
+#else
+#define MAP_I2CSlaveDataGet \
+ I2CSlaveDataGet
+#endif
+#ifdef ROM_I2CSlaveIntEnableEx
+#define MAP_I2CSlaveIntEnableEx \
+ ROM_I2CSlaveIntEnableEx
+#else
+#define MAP_I2CSlaveIntEnableEx \
+ I2CSlaveIntEnableEx
+#endif
+#ifdef ROM_I2CSlaveIntDisableEx
+#define MAP_I2CSlaveIntDisableEx \
+ ROM_I2CSlaveIntDisableEx
+#else
+#define MAP_I2CSlaveIntDisableEx \
+ I2CSlaveIntDisableEx
+#endif
+#ifdef ROM_I2CSlaveIntStatusEx
+#define MAP_I2CSlaveIntStatusEx \
+ ROM_I2CSlaveIntStatusEx
+#else
+#define MAP_I2CSlaveIntStatusEx \
+ I2CSlaveIntStatusEx
+#endif
+#ifdef ROM_I2CSlaveIntClearEx
+#define MAP_I2CSlaveIntClearEx \
+ ROM_I2CSlaveIntClearEx
+#else
+#define MAP_I2CSlaveIntClearEx \
+ I2CSlaveIntClearEx
+#endif
+
+//*****************************************************************************
+//
+// Macros for the I2S API.
+//
+//*****************************************************************************
+#ifdef ROM_I2SIntStatus
+#define MAP_I2SIntStatus \
+ ROM_I2SIntStatus
+#else
+#define MAP_I2SIntStatus \
+ I2SIntStatus
+#endif
+#ifdef ROM_I2STxEnable
+#define MAP_I2STxEnable \
+ ROM_I2STxEnable
+#else
+#define MAP_I2STxEnable \
+ I2STxEnable
+#endif
+#ifdef ROM_I2STxDisable
+#define MAP_I2STxDisable \
+ ROM_I2STxDisable
+#else
+#define MAP_I2STxDisable \
+ I2STxDisable
+#endif
+#ifdef ROM_I2STxDataPut
+#define MAP_I2STxDataPut \
+ ROM_I2STxDataPut
+#else
+#define MAP_I2STxDataPut \
+ I2STxDataPut
+#endif
+#ifdef ROM_I2STxDataPutNonBlocking
+#define MAP_I2STxDataPutNonBlocking \
+ ROM_I2STxDataPutNonBlocking
+#else
+#define MAP_I2STxDataPutNonBlocking \
+ I2STxDataPutNonBlocking
+#endif
+#ifdef ROM_I2STxConfigSet
+#define MAP_I2STxConfigSet \
+ ROM_I2STxConfigSet
+#else
+#define MAP_I2STxConfigSet \
+ I2STxConfigSet
+#endif
+#ifdef ROM_I2STxFIFOLimitSet
+#define MAP_I2STxFIFOLimitSet \
+ ROM_I2STxFIFOLimitSet
+#else
+#define MAP_I2STxFIFOLimitSet \
+ I2STxFIFOLimitSet
+#endif
+#ifdef ROM_I2STxFIFOLimitGet
+#define MAP_I2STxFIFOLimitGet \
+ ROM_I2STxFIFOLimitGet
+#else
+#define MAP_I2STxFIFOLimitGet \
+ I2STxFIFOLimitGet
+#endif
+#ifdef ROM_I2STxFIFOLevelGet
+#define MAP_I2STxFIFOLevelGet \
+ ROM_I2STxFIFOLevelGet
+#else
+#define MAP_I2STxFIFOLevelGet \
+ I2STxFIFOLevelGet
+#endif
+#ifdef ROM_I2SRxEnable
+#define MAP_I2SRxEnable \
+ ROM_I2SRxEnable
+#else
+#define MAP_I2SRxEnable \
+ I2SRxEnable
+#endif
+#ifdef ROM_I2SRxDisable
+#define MAP_I2SRxDisable \
+ ROM_I2SRxDisable
+#else
+#define MAP_I2SRxDisable \
+ I2SRxDisable
+#endif
+#ifdef ROM_I2SRxDataGet
+#define MAP_I2SRxDataGet \
+ ROM_I2SRxDataGet
+#else
+#define MAP_I2SRxDataGet \
+ I2SRxDataGet
+#endif
+#ifdef ROM_I2SRxDataGetNonBlocking
+#define MAP_I2SRxDataGetNonBlocking \
+ ROM_I2SRxDataGetNonBlocking
+#else
+#define MAP_I2SRxDataGetNonBlocking \
+ I2SRxDataGetNonBlocking
+#endif
+#ifdef ROM_I2SRxConfigSet
+#define MAP_I2SRxConfigSet \
+ ROM_I2SRxConfigSet
+#else
+#define MAP_I2SRxConfigSet \
+ I2SRxConfigSet
+#endif
+#ifdef ROM_I2SRxFIFOLimitSet
+#define MAP_I2SRxFIFOLimitSet \
+ ROM_I2SRxFIFOLimitSet
+#else
+#define MAP_I2SRxFIFOLimitSet \
+ I2SRxFIFOLimitSet
+#endif
+#ifdef ROM_I2SRxFIFOLimitGet
+#define MAP_I2SRxFIFOLimitGet \
+ ROM_I2SRxFIFOLimitGet
+#else
+#define MAP_I2SRxFIFOLimitGet \
+ I2SRxFIFOLimitGet
+#endif
+#ifdef ROM_I2SRxFIFOLevelGet
+#define MAP_I2SRxFIFOLevelGet \
+ ROM_I2SRxFIFOLevelGet
+#else
+#define MAP_I2SRxFIFOLevelGet \
+ I2SRxFIFOLevelGet
+#endif
+#ifdef ROM_I2STxRxEnable
+#define MAP_I2STxRxEnable \
+ ROM_I2STxRxEnable
+#else
+#define MAP_I2STxRxEnable \
+ I2STxRxEnable
+#endif
+#ifdef ROM_I2STxRxDisable
+#define MAP_I2STxRxDisable \
+ ROM_I2STxRxDisable
+#else
+#define MAP_I2STxRxDisable \
+ I2STxRxDisable
+#endif
+#ifdef ROM_I2STxRxConfigSet
+#define MAP_I2STxRxConfigSet \
+ ROM_I2STxRxConfigSet
+#else
+#define MAP_I2STxRxConfigSet \
+ I2STxRxConfigSet
+#endif
+#ifdef ROM_I2SMasterClockSelect
+#define MAP_I2SMasterClockSelect \
+ ROM_I2SMasterClockSelect
+#else
+#define MAP_I2SMasterClockSelect \
+ I2SMasterClockSelect
+#endif
+#ifdef ROM_I2SIntEnable
+#define MAP_I2SIntEnable \
+ ROM_I2SIntEnable
+#else
+#define MAP_I2SIntEnable \
+ I2SIntEnable
+#endif
+#ifdef ROM_I2SIntDisable
+#define MAP_I2SIntDisable \
+ ROM_I2SIntDisable
+#else
+#define MAP_I2SIntDisable \
+ I2SIntDisable
+#endif
+#ifdef ROM_I2SIntClear
+#define MAP_I2SIntClear \
+ ROM_I2SIntClear
+#else
+#define MAP_I2SIntClear \
+ I2SIntClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Interrupt API.
+//
+//*****************************************************************************
+#ifdef ROM_IntEnable
+#define MAP_IntEnable \
+ ROM_IntEnable
+#else
+#define MAP_IntEnable \
+ IntEnable
+#endif
+#ifdef ROM_IntMasterEnable
+#define MAP_IntMasterEnable \
+ ROM_IntMasterEnable
+#else
+#define MAP_IntMasterEnable \
+ IntMasterEnable
+#endif
+#ifdef ROM_IntMasterDisable
+#define MAP_IntMasterDisable \
+ ROM_IntMasterDisable
+#else
+#define MAP_IntMasterDisable \
+ IntMasterDisable
+#endif
+#ifdef ROM_IntDisable
+#define MAP_IntDisable \
+ ROM_IntDisable
+#else
+#define MAP_IntDisable \
+ IntDisable
+#endif
+#ifdef ROM_IntPriorityGroupingSet
+#define MAP_IntPriorityGroupingSet \
+ ROM_IntPriorityGroupingSet
+#else
+#define MAP_IntPriorityGroupingSet \
+ IntPriorityGroupingSet
+#endif
+#ifdef ROM_IntPriorityGroupingGet
+#define MAP_IntPriorityGroupingGet \
+ ROM_IntPriorityGroupingGet
+#else
+#define MAP_IntPriorityGroupingGet \
+ IntPriorityGroupingGet
+#endif
+#ifdef ROM_IntPrioritySet
+#define MAP_IntPrioritySet \
+ ROM_IntPrioritySet
+#else
+#define MAP_IntPrioritySet \
+ IntPrioritySet
+#endif
+#ifdef ROM_IntPriorityGet
+#define MAP_IntPriorityGet \
+ ROM_IntPriorityGet
+#else
+#define MAP_IntPriorityGet \
+ IntPriorityGet
+#endif
+#ifdef ROM_IntPendSet
+#define MAP_IntPendSet \
+ ROM_IntPendSet
+#else
+#define MAP_IntPendSet \
+ IntPendSet
+#endif
+#ifdef ROM_IntPendClear
+#define MAP_IntPendClear \
+ ROM_IntPendClear
+#else
+#define MAP_IntPendClear \
+ IntPendClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the MPU API.
+//
+//*****************************************************************************
+#ifdef ROM_MPUEnable
+#define MAP_MPUEnable \
+ ROM_MPUEnable
+#else
+#define MAP_MPUEnable \
+ MPUEnable
+#endif
+#ifdef ROM_MPUDisable
+#define MAP_MPUDisable \
+ ROM_MPUDisable
+#else
+#define MAP_MPUDisable \
+ MPUDisable
+#endif
+#ifdef ROM_MPURegionCountGet
+#define MAP_MPURegionCountGet \
+ ROM_MPURegionCountGet
+#else
+#define MAP_MPURegionCountGet \
+ MPURegionCountGet
+#endif
+#ifdef ROM_MPURegionEnable
+#define MAP_MPURegionEnable \
+ ROM_MPURegionEnable
+#else
+#define MAP_MPURegionEnable \
+ MPURegionEnable
+#endif
+#ifdef ROM_MPURegionDisable
+#define MAP_MPURegionDisable \
+ ROM_MPURegionDisable
+#else
+#define MAP_MPURegionDisable \
+ MPURegionDisable
+#endif
+#ifdef ROM_MPURegionSet
+#define MAP_MPURegionSet \
+ ROM_MPURegionSet
+#else
+#define MAP_MPURegionSet \
+ MPURegionSet
+#endif
+#ifdef ROM_MPURegionGet
+#define MAP_MPURegionGet \
+ ROM_MPURegionGet
+#else
+#define MAP_MPURegionGet \
+ MPURegionGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the PWM API.
+//
+//*****************************************************************************
+#ifdef ROM_PWMPulseWidthSet
+#define MAP_PWMPulseWidthSet \
+ ROM_PWMPulseWidthSet
+#else
+#define MAP_PWMPulseWidthSet \
+ PWMPulseWidthSet
+#endif
+#ifdef ROM_PWMGenConfigure
+#define MAP_PWMGenConfigure \
+ ROM_PWMGenConfigure
+#else
+#define MAP_PWMGenConfigure \
+ PWMGenConfigure
+#endif
+#ifdef ROM_PWMGenPeriodSet
+#define MAP_PWMGenPeriodSet \
+ ROM_PWMGenPeriodSet
+#else
+#define MAP_PWMGenPeriodSet \
+ PWMGenPeriodSet
+#endif
+#ifdef ROM_PWMGenPeriodGet
+#define MAP_PWMGenPeriodGet \
+ ROM_PWMGenPeriodGet
+#else
+#define MAP_PWMGenPeriodGet \
+ PWMGenPeriodGet
+#endif
+#ifdef ROM_PWMGenEnable
+#define MAP_PWMGenEnable \
+ ROM_PWMGenEnable
+#else
+#define MAP_PWMGenEnable \
+ PWMGenEnable
+#endif
+#ifdef ROM_PWMGenDisable
+#define MAP_PWMGenDisable \
+ ROM_PWMGenDisable
+#else
+#define MAP_PWMGenDisable \
+ PWMGenDisable
+#endif
+#ifdef ROM_PWMPulseWidthGet
+#define MAP_PWMPulseWidthGet \
+ ROM_PWMPulseWidthGet
+#else
+#define MAP_PWMPulseWidthGet \
+ PWMPulseWidthGet
+#endif
+#ifdef ROM_PWMDeadBandEnable
+#define MAP_PWMDeadBandEnable \
+ ROM_PWMDeadBandEnable
+#else
+#define MAP_PWMDeadBandEnable \
+ PWMDeadBandEnable
+#endif
+#ifdef ROM_PWMDeadBandDisable
+#define MAP_PWMDeadBandDisable \
+ ROM_PWMDeadBandDisable
+#else
+#define MAP_PWMDeadBandDisable \
+ PWMDeadBandDisable
+#endif
+#ifdef ROM_PWMSyncUpdate
+#define MAP_PWMSyncUpdate \
+ ROM_PWMSyncUpdate
+#else
+#define MAP_PWMSyncUpdate \
+ PWMSyncUpdate
+#endif
+#ifdef ROM_PWMSyncTimeBase
+#define MAP_PWMSyncTimeBase \
+ ROM_PWMSyncTimeBase
+#else
+#define MAP_PWMSyncTimeBase \
+ PWMSyncTimeBase
+#endif
+#ifdef ROM_PWMOutputState
+#define MAP_PWMOutputState \
+ ROM_PWMOutputState
+#else
+#define MAP_PWMOutputState \
+ PWMOutputState
+#endif
+#ifdef ROM_PWMOutputInvert
+#define MAP_PWMOutputInvert \
+ ROM_PWMOutputInvert
+#else
+#define MAP_PWMOutputInvert \
+ PWMOutputInvert
+#endif
+#ifdef ROM_PWMOutputFault
+#define MAP_PWMOutputFault \
+ ROM_PWMOutputFault
+#else
+#define MAP_PWMOutputFault \
+ PWMOutputFault
+#endif
+#ifdef ROM_PWMGenIntTrigEnable
+#define MAP_PWMGenIntTrigEnable \
+ ROM_PWMGenIntTrigEnable
+#else
+#define MAP_PWMGenIntTrigEnable \
+ PWMGenIntTrigEnable
+#endif
+#ifdef ROM_PWMGenIntTrigDisable
+#define MAP_PWMGenIntTrigDisable \
+ ROM_PWMGenIntTrigDisable
+#else
+#define MAP_PWMGenIntTrigDisable \
+ PWMGenIntTrigDisable
+#endif
+#ifdef ROM_PWMGenIntStatus
+#define MAP_PWMGenIntStatus \
+ ROM_PWMGenIntStatus
+#else
+#define MAP_PWMGenIntStatus \
+ PWMGenIntStatus
+#endif
+#ifdef ROM_PWMGenIntClear
+#define MAP_PWMGenIntClear \
+ ROM_PWMGenIntClear
+#else
+#define MAP_PWMGenIntClear \
+ PWMGenIntClear
+#endif
+#ifdef ROM_PWMIntEnable
+#define MAP_PWMIntEnable \
+ ROM_PWMIntEnable
+#else
+#define MAP_PWMIntEnable \
+ PWMIntEnable
+#endif
+#ifdef ROM_PWMIntDisable
+#define MAP_PWMIntDisable \
+ ROM_PWMIntDisable
+#else
+#define MAP_PWMIntDisable \
+ PWMIntDisable
+#endif
+#ifdef ROM_PWMFaultIntClear
+#define MAP_PWMFaultIntClear \
+ ROM_PWMFaultIntClear
+#else
+#define MAP_PWMFaultIntClear \
+ PWMFaultIntClear
+#endif
+#ifdef ROM_PWMIntStatus
+#define MAP_PWMIntStatus \
+ ROM_PWMIntStatus
+#else
+#define MAP_PWMIntStatus \
+ PWMIntStatus
+#endif
+#ifdef ROM_PWMOutputFaultLevel
+#define MAP_PWMOutputFaultLevel \
+ ROM_PWMOutputFaultLevel
+#else
+#define MAP_PWMOutputFaultLevel \
+ PWMOutputFaultLevel
+#endif
+#ifdef ROM_PWMFaultIntClearExt
+#define MAP_PWMFaultIntClearExt \
+ ROM_PWMFaultIntClearExt
+#else
+#define MAP_PWMFaultIntClearExt \
+ PWMFaultIntClearExt
+#endif
+#ifdef ROM_PWMGenFaultConfigure
+#define MAP_PWMGenFaultConfigure \
+ ROM_PWMGenFaultConfigure
+#else
+#define MAP_PWMGenFaultConfigure \
+ PWMGenFaultConfigure
+#endif
+#ifdef ROM_PWMGenFaultTriggerSet
+#define MAP_PWMGenFaultTriggerSet \
+ ROM_PWMGenFaultTriggerSet
+#else
+#define MAP_PWMGenFaultTriggerSet \
+ PWMGenFaultTriggerSet
+#endif
+#ifdef ROM_PWMGenFaultTriggerGet
+#define MAP_PWMGenFaultTriggerGet \
+ ROM_PWMGenFaultTriggerGet
+#else
+#define MAP_PWMGenFaultTriggerGet \
+ PWMGenFaultTriggerGet
+#endif
+#ifdef ROM_PWMGenFaultStatus
+#define MAP_PWMGenFaultStatus \
+ ROM_PWMGenFaultStatus
+#else
+#define MAP_PWMGenFaultStatus \
+ PWMGenFaultStatus
+#endif
+#ifdef ROM_PWMGenFaultClear
+#define MAP_PWMGenFaultClear \
+ ROM_PWMGenFaultClear
+#else
+#define MAP_PWMGenFaultClear \
+ PWMGenFaultClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the QEI API.
+//
+//*****************************************************************************
+#ifdef ROM_QEIPositionGet
+#define MAP_QEIPositionGet \
+ ROM_QEIPositionGet
+#else
+#define MAP_QEIPositionGet \
+ QEIPositionGet
+#endif
+#ifdef ROM_QEIEnable
+#define MAP_QEIEnable \
+ ROM_QEIEnable
+#else
+#define MAP_QEIEnable \
+ QEIEnable
+#endif
+#ifdef ROM_QEIDisable
+#define MAP_QEIDisable \
+ ROM_QEIDisable
+#else
+#define MAP_QEIDisable \
+ QEIDisable
+#endif
+#ifdef ROM_QEIConfigure
+#define MAP_QEIConfigure \
+ ROM_QEIConfigure
+#else
+#define MAP_QEIConfigure \
+ QEIConfigure
+#endif
+#ifdef ROM_QEIPositionSet
+#define MAP_QEIPositionSet \
+ ROM_QEIPositionSet
+#else
+#define MAP_QEIPositionSet \
+ QEIPositionSet
+#endif
+#ifdef ROM_QEIDirectionGet
+#define MAP_QEIDirectionGet \
+ ROM_QEIDirectionGet
+#else
+#define MAP_QEIDirectionGet \
+ QEIDirectionGet
+#endif
+#ifdef ROM_QEIErrorGet
+#define MAP_QEIErrorGet \
+ ROM_QEIErrorGet
+#else
+#define MAP_QEIErrorGet \
+ QEIErrorGet
+#endif
+#ifdef ROM_QEIVelocityEnable
+#define MAP_QEIVelocityEnable \
+ ROM_QEIVelocityEnable
+#else
+#define MAP_QEIVelocityEnable \
+ QEIVelocityEnable
+#endif
+#ifdef ROM_QEIVelocityDisable
+#define MAP_QEIVelocityDisable \
+ ROM_QEIVelocityDisable
+#else
+#define MAP_QEIVelocityDisable \
+ QEIVelocityDisable
+#endif
+#ifdef ROM_QEIVelocityConfigure
+#define MAP_QEIVelocityConfigure \
+ ROM_QEIVelocityConfigure
+#else
+#define MAP_QEIVelocityConfigure \
+ QEIVelocityConfigure
+#endif
+#ifdef ROM_QEIVelocityGet
+#define MAP_QEIVelocityGet \
+ ROM_QEIVelocityGet
+#else
+#define MAP_QEIVelocityGet \
+ QEIVelocityGet
+#endif
+#ifdef ROM_QEIIntEnable
+#define MAP_QEIIntEnable \
+ ROM_QEIIntEnable
+#else
+#define MAP_QEIIntEnable \
+ QEIIntEnable
+#endif
+#ifdef ROM_QEIIntDisable
+#define MAP_QEIIntDisable \
+ ROM_QEIIntDisable
+#else
+#define MAP_QEIIntDisable \
+ QEIIntDisable
+#endif
+#ifdef ROM_QEIIntStatus
+#define MAP_QEIIntStatus \
+ ROM_QEIIntStatus
+#else
+#define MAP_QEIIntStatus \
+ QEIIntStatus
+#endif
+#ifdef ROM_QEIIntClear
+#define MAP_QEIIntClear \
+ ROM_QEIIntClear
+#else
+#define MAP_QEIIntClear \
+ QEIIntClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SSI API.
+//
+//*****************************************************************************
+#ifdef ROM_SSIDataPut
+#define MAP_SSIDataPut \
+ ROM_SSIDataPut
+#else
+#define MAP_SSIDataPut \
+ SSIDataPut
+#endif
+#ifdef ROM_SSIConfigSetExpClk
+#define MAP_SSIConfigSetExpClk \
+ ROM_SSIConfigSetExpClk
+#else
+#define MAP_SSIConfigSetExpClk \
+ SSIConfigSetExpClk
+#endif
+#ifdef ROM_SSIEnable
+#define MAP_SSIEnable \
+ ROM_SSIEnable
+#else
+#define MAP_SSIEnable \
+ SSIEnable
+#endif
+#ifdef ROM_SSIDisable
+#define MAP_SSIDisable \
+ ROM_SSIDisable
+#else
+#define MAP_SSIDisable \
+ SSIDisable
+#endif
+#ifdef ROM_SSIIntEnable
+#define MAP_SSIIntEnable \
+ ROM_SSIIntEnable
+#else
+#define MAP_SSIIntEnable \
+ SSIIntEnable
+#endif
+#ifdef ROM_SSIIntDisable
+#define MAP_SSIIntDisable \
+ ROM_SSIIntDisable
+#else
+#define MAP_SSIIntDisable \
+ SSIIntDisable
+#endif
+#ifdef ROM_SSIIntStatus
+#define MAP_SSIIntStatus \
+ ROM_SSIIntStatus
+#else
+#define MAP_SSIIntStatus \
+ SSIIntStatus
+#endif
+#ifdef ROM_SSIIntClear
+#define MAP_SSIIntClear \
+ ROM_SSIIntClear
+#else
+#define MAP_SSIIntClear \
+ SSIIntClear
+#endif
+#ifdef ROM_SSIDataPutNonBlocking
+#define MAP_SSIDataPutNonBlocking \
+ ROM_SSIDataPutNonBlocking
+#else
+#define MAP_SSIDataPutNonBlocking \
+ SSIDataPutNonBlocking
+#endif
+#ifdef ROM_SSIDataGet
+#define MAP_SSIDataGet \
+ ROM_SSIDataGet
+#else
+#define MAP_SSIDataGet \
+ SSIDataGet
+#endif
+#ifdef ROM_SSIDataGetNonBlocking
+#define MAP_SSIDataGetNonBlocking \
+ ROM_SSIDataGetNonBlocking
+#else
+#define MAP_SSIDataGetNonBlocking \
+ SSIDataGetNonBlocking
+#endif
+#ifdef ROM_SSIDMAEnable
+#define MAP_SSIDMAEnable \
+ ROM_SSIDMAEnable
+#else
+#define MAP_SSIDMAEnable \
+ SSIDMAEnable
+#endif
+#ifdef ROM_SSIDMADisable
+#define MAP_SSIDMADisable \
+ ROM_SSIDMADisable
+#else
+#define MAP_SSIDMADisable \
+ SSIDMADisable
+#endif
+#ifdef ROM_SSIBusy
+#define MAP_SSIBusy \
+ ROM_SSIBusy
+#else
+#define MAP_SSIBusy \
+ SSIBusy
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SysCtl API.
+//
+//*****************************************************************************
+#ifdef ROM_SysCtlSleep
+#define MAP_SysCtlSleep \
+ ROM_SysCtlSleep
+#else
+#define MAP_SysCtlSleep \
+ SysCtlSleep
+#endif
+#ifdef ROM_SysCtlSRAMSizeGet
+#define MAP_SysCtlSRAMSizeGet \
+ ROM_SysCtlSRAMSizeGet
+#else
+#define MAP_SysCtlSRAMSizeGet \
+ SysCtlSRAMSizeGet
+#endif
+#ifdef ROM_SysCtlFlashSizeGet
+#define MAP_SysCtlFlashSizeGet \
+ ROM_SysCtlFlashSizeGet
+#else
+#define MAP_SysCtlFlashSizeGet \
+ SysCtlFlashSizeGet
+#endif
+#ifdef ROM_SysCtlPinPresent
+#define MAP_SysCtlPinPresent \
+ ROM_SysCtlPinPresent
+#else
+#define MAP_SysCtlPinPresent \
+ SysCtlPinPresent
+#endif
+#ifdef ROM_SysCtlPeripheralPresent
+#define MAP_SysCtlPeripheralPresent \
+ ROM_SysCtlPeripheralPresent
+#else
+#define MAP_SysCtlPeripheralPresent \
+ SysCtlPeripheralPresent
+#endif
+#ifdef ROM_SysCtlPeripheralReset
+#define MAP_SysCtlPeripheralReset \
+ ROM_SysCtlPeripheralReset
+#else
+#define MAP_SysCtlPeripheralReset \
+ SysCtlPeripheralReset
+#endif
+#ifdef ROM_SysCtlPeripheralEnable
+#define MAP_SysCtlPeripheralEnable \
+ ROM_SysCtlPeripheralEnable
+#else
+#define MAP_SysCtlPeripheralEnable \
+ SysCtlPeripheralEnable
+#endif
+#ifdef ROM_SysCtlPeripheralDisable
+#define MAP_SysCtlPeripheralDisable \
+ ROM_SysCtlPeripheralDisable
+#else
+#define MAP_SysCtlPeripheralDisable \
+ SysCtlPeripheralDisable
+#endif
+#ifdef ROM_SysCtlPeripheralSleepEnable
+#define MAP_SysCtlPeripheralSleepEnable \
+ ROM_SysCtlPeripheralSleepEnable
+#else
+#define MAP_SysCtlPeripheralSleepEnable \
+ SysCtlPeripheralSleepEnable
+#endif
+#ifdef ROM_SysCtlPeripheralSleepDisable
+#define MAP_SysCtlPeripheralSleepDisable \
+ ROM_SysCtlPeripheralSleepDisable
+#else
+#define MAP_SysCtlPeripheralSleepDisable \
+ SysCtlPeripheralSleepDisable
+#endif
+#ifdef ROM_SysCtlPeripheralDeepSleepEnable
+#define MAP_SysCtlPeripheralDeepSleepEnable \
+ ROM_SysCtlPeripheralDeepSleepEnable
+#else
+#define MAP_SysCtlPeripheralDeepSleepEnable \
+ SysCtlPeripheralDeepSleepEnable
+#endif
+#ifdef ROM_SysCtlPeripheralDeepSleepDisable
+#define MAP_SysCtlPeripheralDeepSleepDisable \
+ ROM_SysCtlPeripheralDeepSleepDisable
+#else
+#define MAP_SysCtlPeripheralDeepSleepDisable \
+ SysCtlPeripheralDeepSleepDisable
+#endif
+#ifdef ROM_SysCtlPeripheralClockGating
+#define MAP_SysCtlPeripheralClockGating \
+ ROM_SysCtlPeripheralClockGating
+#else
+#define MAP_SysCtlPeripheralClockGating \
+ SysCtlPeripheralClockGating
+#endif
+#ifdef ROM_SysCtlIntEnable
+#define MAP_SysCtlIntEnable \
+ ROM_SysCtlIntEnable
+#else
+#define MAP_SysCtlIntEnable \
+ SysCtlIntEnable
+#endif
+#ifdef ROM_SysCtlIntDisable
+#define MAP_SysCtlIntDisable \
+ ROM_SysCtlIntDisable
+#else
+#define MAP_SysCtlIntDisable \
+ SysCtlIntDisable
+#endif
+#ifdef ROM_SysCtlIntClear
+#define MAP_SysCtlIntClear \
+ ROM_SysCtlIntClear
+#else
+#define MAP_SysCtlIntClear \
+ SysCtlIntClear
+#endif
+#ifdef ROM_SysCtlIntStatus
+#define MAP_SysCtlIntStatus \
+ ROM_SysCtlIntStatus
+#else
+#define MAP_SysCtlIntStatus \
+ SysCtlIntStatus
+#endif
+#ifdef ROM_SysCtlLDOSet
+#define MAP_SysCtlLDOSet \
+ ROM_SysCtlLDOSet
+#else
+#define MAP_SysCtlLDOSet \
+ SysCtlLDOSet
+#endif
+#ifdef ROM_SysCtlLDOGet
+#define MAP_SysCtlLDOGet \
+ ROM_SysCtlLDOGet
+#else
+#define MAP_SysCtlLDOGet \
+ SysCtlLDOGet
+#endif
+#ifdef ROM_SysCtlReset
+#define MAP_SysCtlReset \
+ ROM_SysCtlReset
+#else
+#define MAP_SysCtlReset \
+ SysCtlReset
+#endif
+#ifdef ROM_SysCtlDeepSleep
+#define MAP_SysCtlDeepSleep \
+ ROM_SysCtlDeepSleep
+#else
+#define MAP_SysCtlDeepSleep \
+ SysCtlDeepSleep
+#endif
+#ifdef ROM_SysCtlResetCauseGet
+#define MAP_SysCtlResetCauseGet \
+ ROM_SysCtlResetCauseGet
+#else
+#define MAP_SysCtlResetCauseGet \
+ SysCtlResetCauseGet
+#endif
+#ifdef ROM_SysCtlResetCauseClear
+#define MAP_SysCtlResetCauseClear \
+ ROM_SysCtlResetCauseClear
+#else
+#define MAP_SysCtlResetCauseClear \
+ SysCtlResetCauseClear
+#endif
+#ifdef ROM_SysCtlClockSet
+#define MAP_SysCtlClockSet \
+ ROM_SysCtlClockSet
+#else
+#define MAP_SysCtlClockSet \
+ SysCtlClockSet
+#endif
+#ifdef ROM_SysCtlClockGet
+#define MAP_SysCtlClockGet \
+ ROM_SysCtlClockGet
+#else
+#define MAP_SysCtlClockGet \
+ SysCtlClockGet
+#endif
+#ifdef ROM_SysCtlPWMClockSet
+#define MAP_SysCtlPWMClockSet \
+ ROM_SysCtlPWMClockSet
+#else
+#define MAP_SysCtlPWMClockSet \
+ SysCtlPWMClockSet
+#endif
+#ifdef ROM_SysCtlPWMClockGet
+#define MAP_SysCtlPWMClockGet \
+ ROM_SysCtlPWMClockGet
+#else
+#define MAP_SysCtlPWMClockGet \
+ SysCtlPWMClockGet
+#endif
+#ifdef ROM_SysCtlADCSpeedSet
+#define MAP_SysCtlADCSpeedSet \
+ ROM_SysCtlADCSpeedSet
+#else
+#define MAP_SysCtlADCSpeedSet \
+ SysCtlADCSpeedSet
+#endif
+#ifdef ROM_SysCtlADCSpeedGet
+#define MAP_SysCtlADCSpeedGet \
+ ROM_SysCtlADCSpeedGet
+#else
+#define MAP_SysCtlADCSpeedGet \
+ SysCtlADCSpeedGet
+#endif
+#ifdef ROM_SysCtlGPIOAHBEnable
+#define MAP_SysCtlGPIOAHBEnable \
+ ROM_SysCtlGPIOAHBEnable
+#else
+#define MAP_SysCtlGPIOAHBEnable \
+ SysCtlGPIOAHBEnable
+#endif
+#ifdef ROM_SysCtlGPIOAHBDisable
+#define MAP_SysCtlGPIOAHBDisable \
+ ROM_SysCtlGPIOAHBDisable
+#else
+#define MAP_SysCtlGPIOAHBDisable \
+ SysCtlGPIOAHBDisable
+#endif
+#ifdef ROM_SysCtlUSBPLLEnable
+#define MAP_SysCtlUSBPLLEnable \
+ ROM_SysCtlUSBPLLEnable
+#else
+#define MAP_SysCtlUSBPLLEnable \
+ SysCtlUSBPLLEnable
+#endif
+#ifdef ROM_SysCtlUSBPLLDisable
+#define MAP_SysCtlUSBPLLDisable \
+ ROM_SysCtlUSBPLLDisable
+#else
+#define MAP_SysCtlUSBPLLDisable \
+ SysCtlUSBPLLDisable
+#endif
+#ifdef ROM_SysCtlI2SMClkSet
+#define MAP_SysCtlI2SMClkSet \
+ ROM_SysCtlI2SMClkSet
+#else
+#define MAP_SysCtlI2SMClkSet \
+ SysCtlI2SMClkSet
+#endif
+#ifdef ROM_SysCtlDelay
+#define MAP_SysCtlDelay \
+ ROM_SysCtlDelay
+#else
+#define MAP_SysCtlDelay \
+ SysCtlDelay
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SysTick API.
+//
+//*****************************************************************************
+#ifdef ROM_SysTickValueGet
+#define MAP_SysTickValueGet \
+ ROM_SysTickValueGet
+#else
+#define MAP_SysTickValueGet \
+ SysTickValueGet
+#endif
+#ifdef ROM_SysTickEnable
+#define MAP_SysTickEnable \
+ ROM_SysTickEnable
+#else
+#define MAP_SysTickEnable \
+ SysTickEnable
+#endif
+#ifdef ROM_SysTickDisable
+#define MAP_SysTickDisable \
+ ROM_SysTickDisable
+#else
+#define MAP_SysTickDisable \
+ SysTickDisable
+#endif
+#ifdef ROM_SysTickIntEnable
+#define MAP_SysTickIntEnable \
+ ROM_SysTickIntEnable
+#else
+#define MAP_SysTickIntEnable \
+ SysTickIntEnable
+#endif
+#ifdef ROM_SysTickIntDisable
+#define MAP_SysTickIntDisable \
+ ROM_SysTickIntDisable
+#else
+#define MAP_SysTickIntDisable \
+ SysTickIntDisable
+#endif
+#ifdef ROM_SysTickPeriodSet
+#define MAP_SysTickPeriodSet \
+ ROM_SysTickPeriodSet
+#else
+#define MAP_SysTickPeriodSet \
+ SysTickPeriodSet
+#endif
+#ifdef ROM_SysTickPeriodGet
+#define MAP_SysTickPeriodGet \
+ ROM_SysTickPeriodGet
+#else
+#define MAP_SysTickPeriodGet \
+ SysTickPeriodGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Timer API.
+//
+//*****************************************************************************
+#ifdef ROM_TimerIntClear
+#define MAP_TimerIntClear \
+ ROM_TimerIntClear
+#else
+#define MAP_TimerIntClear \
+ TimerIntClear
+#endif
+#ifdef ROM_TimerEnable
+#define MAP_TimerEnable \
+ ROM_TimerEnable
+#else
+#define MAP_TimerEnable \
+ TimerEnable
+#endif
+#ifdef ROM_TimerDisable
+#define MAP_TimerDisable \
+ ROM_TimerDisable
+#else
+#define MAP_TimerDisable \
+ TimerDisable
+#endif
+#ifdef ROM_TimerConfigure
+#define MAP_TimerConfigure \
+ ROM_TimerConfigure
+#else
+#define MAP_TimerConfigure \
+ TimerConfigure
+#endif
+#ifdef ROM_TimerControlLevel
+#define MAP_TimerControlLevel \
+ ROM_TimerControlLevel
+#else
+#define MAP_TimerControlLevel \
+ TimerControlLevel
+#endif
+#ifdef ROM_TimerControlTrigger
+#define MAP_TimerControlTrigger \
+ ROM_TimerControlTrigger
+#else
+#define MAP_TimerControlTrigger \
+ TimerControlTrigger
+#endif
+#ifdef ROM_TimerControlEvent
+#define MAP_TimerControlEvent \
+ ROM_TimerControlEvent
+#else
+#define MAP_TimerControlEvent \
+ TimerControlEvent
+#endif
+#ifdef ROM_TimerControlStall
+#define MAP_TimerControlStall \
+ ROM_TimerControlStall
+#else
+#define MAP_TimerControlStall \
+ TimerControlStall
+#endif
+#ifdef ROM_TimerRTCEnable
+#define MAP_TimerRTCEnable \
+ ROM_TimerRTCEnable
+#else
+#define MAP_TimerRTCEnable \
+ TimerRTCEnable
+#endif
+#ifdef ROM_TimerRTCDisable
+#define MAP_TimerRTCDisable \
+ ROM_TimerRTCDisable
+#else
+#define MAP_TimerRTCDisable \
+ TimerRTCDisable
+#endif
+#ifdef ROM_TimerPrescaleSet
+#define MAP_TimerPrescaleSet \
+ ROM_TimerPrescaleSet
+#else
+#define MAP_TimerPrescaleSet \
+ TimerPrescaleSet
+#endif
+#ifdef ROM_TimerPrescaleGet
+#define MAP_TimerPrescaleGet \
+ ROM_TimerPrescaleGet
+#else
+#define MAP_TimerPrescaleGet \
+ TimerPrescaleGet
+#endif
+#ifdef ROM_TimerPrescaleMatchSet
+#define MAP_TimerPrescaleMatchSet \
+ ROM_TimerPrescaleMatchSet
+#else
+#define MAP_TimerPrescaleMatchSet \
+ TimerPrescaleMatchSet
+#endif
+#ifdef ROM_TimerPrescaleMatchGet
+#define MAP_TimerPrescaleMatchGet \
+ ROM_TimerPrescaleMatchGet
+#else
+#define MAP_TimerPrescaleMatchGet \
+ TimerPrescaleMatchGet
+#endif
+#ifdef ROM_TimerLoadSet
+#define MAP_TimerLoadSet \
+ ROM_TimerLoadSet
+#else
+#define MAP_TimerLoadSet \
+ TimerLoadSet
+#endif
+#ifdef ROM_TimerLoadGet
+#define MAP_TimerLoadGet \
+ ROM_TimerLoadGet
+#else
+#define MAP_TimerLoadGet \
+ TimerLoadGet
+#endif
+#ifdef ROM_TimerValueGet
+#define MAP_TimerValueGet \
+ ROM_TimerValueGet
+#else
+#define MAP_TimerValueGet \
+ TimerValueGet
+#endif
+#ifdef ROM_TimerMatchSet
+#define MAP_TimerMatchSet \
+ ROM_TimerMatchSet
+#else
+#define MAP_TimerMatchSet \
+ TimerMatchSet
+#endif
+#ifdef ROM_TimerMatchGet
+#define MAP_TimerMatchGet \
+ ROM_TimerMatchGet
+#else
+#define MAP_TimerMatchGet \
+ TimerMatchGet
+#endif
+#ifdef ROM_TimerIntEnable
+#define MAP_TimerIntEnable \
+ ROM_TimerIntEnable
+#else
+#define MAP_TimerIntEnable \
+ TimerIntEnable
+#endif
+#ifdef ROM_TimerIntDisable
+#define MAP_TimerIntDisable \
+ ROM_TimerIntDisable
+#else
+#define MAP_TimerIntDisable \
+ TimerIntDisable
+#endif
+#ifdef ROM_TimerIntStatus
+#define MAP_TimerIntStatus \
+ ROM_TimerIntStatus
+#else
+#define MAP_TimerIntStatus \
+ TimerIntStatus
+#endif
+#ifdef ROM_TimerControlWaitOnTrigger
+#define MAP_TimerControlWaitOnTrigger \
+ ROM_TimerControlWaitOnTrigger
+#else
+#define MAP_TimerControlWaitOnTrigger \
+ TimerControlWaitOnTrigger
+#endif
+
+//*****************************************************************************
+//
+// Macros for the UART API.
+//
+//*****************************************************************************
+#ifdef ROM_UARTCharPut
+#define MAP_UARTCharPut \
+ ROM_UARTCharPut
+#else
+#define MAP_UARTCharPut \
+ UARTCharPut
+#endif
+#ifdef ROM_UARTParityModeSet
+#define MAP_UARTParityModeSet \
+ ROM_UARTParityModeSet
+#else
+#define MAP_UARTParityModeSet \
+ UARTParityModeSet
+#endif
+#ifdef ROM_UARTParityModeGet
+#define MAP_UARTParityModeGet \
+ ROM_UARTParityModeGet
+#else
+#define MAP_UARTParityModeGet \
+ UARTParityModeGet
+#endif
+#ifdef ROM_UARTFIFOLevelSet
+#define MAP_UARTFIFOLevelSet \
+ ROM_UARTFIFOLevelSet
+#else
+#define MAP_UARTFIFOLevelSet \
+ UARTFIFOLevelSet
+#endif
+#ifdef ROM_UARTFIFOLevelGet
+#define MAP_UARTFIFOLevelGet \
+ ROM_UARTFIFOLevelGet
+#else
+#define MAP_UARTFIFOLevelGet \
+ UARTFIFOLevelGet
+#endif
+#ifdef ROM_UARTConfigSetExpClk
+#define MAP_UARTConfigSetExpClk \
+ ROM_UARTConfigSetExpClk
+#else
+#define MAP_UARTConfigSetExpClk \
+ UARTConfigSetExpClk
+#endif
+#ifdef ROM_UARTConfigGetExpClk
+#define MAP_UARTConfigGetExpClk \
+ ROM_UARTConfigGetExpClk
+#else
+#define MAP_UARTConfigGetExpClk \
+ UARTConfigGetExpClk
+#endif
+#ifdef ROM_UARTEnable
+#define MAP_UARTEnable \
+ ROM_UARTEnable
+#else
+#define MAP_UARTEnable \
+ UARTEnable
+#endif
+#ifdef ROM_UARTDisable
+#define MAP_UARTDisable \
+ ROM_UARTDisable
+#else
+#define MAP_UARTDisable \
+ UARTDisable
+#endif
+#ifdef ROM_UARTEnableSIR
+#define MAP_UARTEnableSIR \
+ ROM_UARTEnableSIR
+#else
+#define MAP_UARTEnableSIR \
+ UARTEnableSIR
+#endif
+#ifdef ROM_UARTDisableSIR
+#define MAP_UARTDisableSIR \
+ ROM_UARTDisableSIR
+#else
+#define MAP_UARTDisableSIR \
+ UARTDisableSIR
+#endif
+#ifdef ROM_UARTCharsAvail
+#define MAP_UARTCharsAvail \
+ ROM_UARTCharsAvail
+#else
+#define MAP_UARTCharsAvail \
+ UARTCharsAvail
+#endif
+#ifdef ROM_UARTSpaceAvail
+#define MAP_UARTSpaceAvail \
+ ROM_UARTSpaceAvail
+#else
+#define MAP_UARTSpaceAvail \
+ UARTSpaceAvail
+#endif
+#ifdef ROM_UARTCharGetNonBlocking
+#define MAP_UARTCharGetNonBlocking \
+ ROM_UARTCharGetNonBlocking
+#else
+#define MAP_UARTCharGetNonBlocking \
+ UARTCharGetNonBlocking
+#endif
+#ifdef ROM_UARTCharGet
+#define MAP_UARTCharGet \
+ ROM_UARTCharGet
+#else
+#define MAP_UARTCharGet \
+ UARTCharGet
+#endif
+#ifdef ROM_UARTCharPutNonBlocking
+#define MAP_UARTCharPutNonBlocking \
+ ROM_UARTCharPutNonBlocking
+#else
+#define MAP_UARTCharPutNonBlocking \
+ UARTCharPutNonBlocking
+#endif
+#ifdef ROM_UARTBreakCtl
+#define MAP_UARTBreakCtl \
+ ROM_UARTBreakCtl
+#else
+#define MAP_UARTBreakCtl \
+ UARTBreakCtl
+#endif
+#ifdef ROM_UARTIntEnable
+#define MAP_UARTIntEnable \
+ ROM_UARTIntEnable
+#else
+#define MAP_UARTIntEnable \
+ UARTIntEnable
+#endif
+#ifdef ROM_UARTIntDisable
+#define MAP_UARTIntDisable \
+ ROM_UARTIntDisable
+#else
+#define MAP_UARTIntDisable \
+ UARTIntDisable
+#endif
+#ifdef ROM_UARTIntStatus
+#define MAP_UARTIntStatus \
+ ROM_UARTIntStatus
+#else
+#define MAP_UARTIntStatus \
+ UARTIntStatus
+#endif
+#ifdef ROM_UARTIntClear
+#define MAP_UARTIntClear \
+ ROM_UARTIntClear
+#else
+#define MAP_UARTIntClear \
+ UARTIntClear
+#endif
+#ifdef ROM_UARTDMAEnable
+#define MAP_UARTDMAEnable \
+ ROM_UARTDMAEnable
+#else
+#define MAP_UARTDMAEnable \
+ UARTDMAEnable
+#endif
+#ifdef ROM_UARTDMADisable
+#define MAP_UARTDMADisable \
+ ROM_UARTDMADisable
+#else
+#define MAP_UARTDMADisable \
+ UARTDMADisable
+#endif
+#ifdef ROM_UARTFIFOEnable
+#define MAP_UARTFIFOEnable \
+ ROM_UARTFIFOEnable
+#else
+#define MAP_UARTFIFOEnable \
+ UARTFIFOEnable
+#endif
+#ifdef ROM_UARTFIFODisable
+#define MAP_UARTFIFODisable \
+ ROM_UARTFIFODisable
+#else
+#define MAP_UARTFIFODisable \
+ UARTFIFODisable
+#endif
+#ifdef ROM_UARTBusy
+#define MAP_UARTBusy \
+ ROM_UARTBusy
+#else
+#define MAP_UARTBusy \
+ UARTBusy
+#endif
+#ifdef ROM_UARTTxIntModeSet
+#define MAP_UARTTxIntModeSet \
+ ROM_UARTTxIntModeSet
+#else
+#define MAP_UARTTxIntModeSet \
+ UARTTxIntModeSet
+#endif
+#ifdef ROM_UARTTxIntModeGet
+#define MAP_UARTTxIntModeGet \
+ ROM_UARTTxIntModeGet
+#else
+#define MAP_UARTTxIntModeGet \
+ UARTTxIntModeGet
+#endif
+#ifdef ROM_UARTRxErrorGet
+#define MAP_UARTRxErrorGet \
+ ROM_UARTRxErrorGet
+#else
+#define MAP_UARTRxErrorGet \
+ UARTRxErrorGet
+#endif
+#ifdef ROM_UARTRxErrorClear
+#define MAP_UARTRxErrorClear \
+ ROM_UARTRxErrorClear
+#else
+#define MAP_UARTRxErrorClear \
+ UARTRxErrorClear
+#endif
+
+//*****************************************************************************
+//
+// Macros for the uDMA API.
+//
+//*****************************************************************************
+#ifdef ROM_uDMAChannelTransferSet
+#define MAP_uDMAChannelTransferSet \
+ ROM_uDMAChannelTransferSet
+#else
+#define MAP_uDMAChannelTransferSet \
+ uDMAChannelTransferSet
+#endif
+#ifdef ROM_uDMAEnable
+#define MAP_uDMAEnable \
+ ROM_uDMAEnable
+#else
+#define MAP_uDMAEnable \
+ uDMAEnable
+#endif
+#ifdef ROM_uDMADisable
+#define MAP_uDMADisable \
+ ROM_uDMADisable
+#else
+#define MAP_uDMADisable \
+ uDMADisable
+#endif
+#ifdef ROM_uDMAErrorStatusGet
+#define MAP_uDMAErrorStatusGet \
+ ROM_uDMAErrorStatusGet
+#else
+#define MAP_uDMAErrorStatusGet \
+ uDMAErrorStatusGet
+#endif
+#ifdef ROM_uDMAErrorStatusClear
+#define MAP_uDMAErrorStatusClear \
+ ROM_uDMAErrorStatusClear
+#else
+#define MAP_uDMAErrorStatusClear \
+ uDMAErrorStatusClear
+#endif
+#ifdef ROM_uDMAChannelEnable
+#define MAP_uDMAChannelEnable \
+ ROM_uDMAChannelEnable
+#else
+#define MAP_uDMAChannelEnable \
+ uDMAChannelEnable
+#endif
+#ifdef ROM_uDMAChannelDisable
+#define MAP_uDMAChannelDisable \
+ ROM_uDMAChannelDisable
+#else
+#define MAP_uDMAChannelDisable \
+ uDMAChannelDisable
+#endif
+#ifdef ROM_uDMAChannelIsEnabled
+#define MAP_uDMAChannelIsEnabled \
+ ROM_uDMAChannelIsEnabled
+#else
+#define MAP_uDMAChannelIsEnabled \
+ uDMAChannelIsEnabled
+#endif
+#ifdef ROM_uDMAControlBaseSet
+#define MAP_uDMAControlBaseSet \
+ ROM_uDMAControlBaseSet
+#else
+#define MAP_uDMAControlBaseSet \
+ uDMAControlBaseSet
+#endif
+#ifdef ROM_uDMAControlBaseGet
+#define MAP_uDMAControlBaseGet \
+ ROM_uDMAControlBaseGet
+#else
+#define MAP_uDMAControlBaseGet \
+ uDMAControlBaseGet
+#endif
+#ifdef ROM_uDMAChannelRequest
+#define MAP_uDMAChannelRequest \
+ ROM_uDMAChannelRequest
+#else
+#define MAP_uDMAChannelRequest \
+ uDMAChannelRequest
+#endif
+#ifdef ROM_uDMAChannelAttributeEnable
+#define MAP_uDMAChannelAttributeEnable \
+ ROM_uDMAChannelAttributeEnable
+#else
+#define MAP_uDMAChannelAttributeEnable \
+ uDMAChannelAttributeEnable
+#endif
+#ifdef ROM_uDMAChannelAttributeDisable
+#define MAP_uDMAChannelAttributeDisable \
+ ROM_uDMAChannelAttributeDisable
+#else
+#define MAP_uDMAChannelAttributeDisable \
+ uDMAChannelAttributeDisable
+#endif
+#ifdef ROM_uDMAChannelAttributeGet
+#define MAP_uDMAChannelAttributeGet \
+ ROM_uDMAChannelAttributeGet
+#else
+#define MAP_uDMAChannelAttributeGet \
+ uDMAChannelAttributeGet
+#endif
+#ifdef ROM_uDMAChannelControlSet
+#define MAP_uDMAChannelControlSet \
+ ROM_uDMAChannelControlSet
+#else
+#define MAP_uDMAChannelControlSet \
+ uDMAChannelControlSet
+#endif
+#ifdef ROM_uDMAChannelSizeGet
+#define MAP_uDMAChannelSizeGet \
+ ROM_uDMAChannelSizeGet
+#else
+#define MAP_uDMAChannelSizeGet \
+ uDMAChannelSizeGet
+#endif
+#ifdef ROM_uDMAChannelModeGet
+#define MAP_uDMAChannelModeGet \
+ ROM_uDMAChannelModeGet
+#else
+#define MAP_uDMAChannelModeGet \
+ uDMAChannelModeGet
+#endif
+#ifdef ROM_uDMAChannelSelectSecondary
+#define MAP_uDMAChannelSelectSecondary \
+ ROM_uDMAChannelSelectSecondary
+#else
+#define MAP_uDMAChannelSelectSecondary \
+ uDMAChannelSelectSecondary
+#endif
+#ifdef ROM_uDMAChannelSelectDefault
+#define MAP_uDMAChannelSelectDefault \
+ ROM_uDMAChannelSelectDefault
+#else
+#define MAP_uDMAChannelSelectDefault \
+ uDMAChannelSelectDefault
+#endif
+
+//*****************************************************************************
+//
+// Macros for the USB API.
+//
+//*****************************************************************************
+#ifdef ROM_USBIntStatus
+#define MAP_USBIntStatus \
+ ROM_USBIntStatus
+#else
+#define MAP_USBIntStatus \
+ USBIntStatus
+#endif
+#ifdef ROM_USBDevAddrGet
+#define MAP_USBDevAddrGet \
+ ROM_USBDevAddrGet
+#else
+#define MAP_USBDevAddrGet \
+ USBDevAddrGet
+#endif
+#ifdef ROM_USBDevAddrSet
+#define MAP_USBDevAddrSet \
+ ROM_USBDevAddrSet
+#else
+#define MAP_USBDevAddrSet \
+ USBDevAddrSet
+#endif
+#ifdef ROM_USBDevConnect
+#define MAP_USBDevConnect \
+ ROM_USBDevConnect
+#else
+#define MAP_USBDevConnect \
+ USBDevConnect
+#endif
+#ifdef ROM_USBDevDisconnect
+#define MAP_USBDevDisconnect \
+ ROM_USBDevDisconnect
+#else
+#define MAP_USBDevDisconnect \
+ USBDevDisconnect
+#endif
+#ifdef ROM_USBDevEndpointConfigSet
+#define MAP_USBDevEndpointConfigSet \
+ ROM_USBDevEndpointConfigSet
+#else
+#define MAP_USBDevEndpointConfigSet \
+ USBDevEndpointConfigSet
+#endif
+#ifdef ROM_USBDevEndpointDataAck
+#define MAP_USBDevEndpointDataAck \
+ ROM_USBDevEndpointDataAck
+#else
+#define MAP_USBDevEndpointDataAck \
+ USBDevEndpointDataAck
+#endif
+#ifdef ROM_USBDevEndpointStall
+#define MAP_USBDevEndpointStall \
+ ROM_USBDevEndpointStall
+#else
+#define MAP_USBDevEndpointStall \
+ USBDevEndpointStall
+#endif
+#ifdef ROM_USBDevEndpointStatusClear
+#define MAP_USBDevEndpointStatusClear \
+ ROM_USBDevEndpointStatusClear
+#else
+#define MAP_USBDevEndpointStatusClear \
+ USBDevEndpointStatusClear
+#endif
+#ifdef ROM_USBEndpointDataGet
+#define MAP_USBEndpointDataGet \
+ ROM_USBEndpointDataGet
+#else
+#define MAP_USBEndpointDataGet \
+ USBEndpointDataGet
+#endif
+#ifdef ROM_USBEndpointDataPut
+#define MAP_USBEndpointDataPut \
+ ROM_USBEndpointDataPut
+#else
+#define MAP_USBEndpointDataPut \
+ USBEndpointDataPut
+#endif
+#ifdef ROM_USBEndpointDataSend
+#define MAP_USBEndpointDataSend \
+ ROM_USBEndpointDataSend
+#else
+#define MAP_USBEndpointDataSend \
+ USBEndpointDataSend
+#endif
+#ifdef ROM_USBEndpointDataToggleClear
+#define MAP_USBEndpointDataToggleClear \
+ ROM_USBEndpointDataToggleClear
+#else
+#define MAP_USBEndpointDataToggleClear \
+ USBEndpointDataToggleClear
+#endif
+#ifdef ROM_USBEndpointStatus
+#define MAP_USBEndpointStatus \
+ ROM_USBEndpointStatus
+#else
+#define MAP_USBEndpointStatus \
+ USBEndpointStatus
+#endif
+#ifdef ROM_USBFIFOAddrGet
+#define MAP_USBFIFOAddrGet \
+ ROM_USBFIFOAddrGet
+#else
+#define MAP_USBFIFOAddrGet \
+ USBFIFOAddrGet
+#endif
+#ifdef ROM_USBFIFOConfigGet
+#define MAP_USBFIFOConfigGet \
+ ROM_USBFIFOConfigGet
+#else
+#define MAP_USBFIFOConfigGet \
+ USBFIFOConfigGet
+#endif
+#ifdef ROM_USBFIFOConfigSet
+#define MAP_USBFIFOConfigSet \
+ ROM_USBFIFOConfigSet
+#else
+#define MAP_USBFIFOConfigSet \
+ USBFIFOConfigSet
+#endif
+#ifdef ROM_USBFrameNumberGet
+#define MAP_USBFrameNumberGet \
+ ROM_USBFrameNumberGet
+#else
+#define MAP_USBFrameNumberGet \
+ USBFrameNumberGet
+#endif
+#ifdef ROM_USBHostAddrGet
+#define MAP_USBHostAddrGet \
+ ROM_USBHostAddrGet
+#else
+#define MAP_USBHostAddrGet \
+ USBHostAddrGet
+#endif
+#ifdef ROM_USBHostAddrSet
+#define MAP_USBHostAddrSet \
+ ROM_USBHostAddrSet
+#else
+#define MAP_USBHostAddrSet \
+ USBHostAddrSet
+#endif
+#ifdef ROM_USBHostEndpointConfig
+#define MAP_USBHostEndpointConfig \
+ ROM_USBHostEndpointConfig
+#else
+#define MAP_USBHostEndpointConfig \
+ USBHostEndpointConfig
+#endif
+#ifdef ROM_USBHostEndpointDataAck
+#define MAP_USBHostEndpointDataAck \
+ ROM_USBHostEndpointDataAck
+#else
+#define MAP_USBHostEndpointDataAck \
+ USBHostEndpointDataAck
+#endif
+#ifdef ROM_USBHostEndpointDataToggle
+#define MAP_USBHostEndpointDataToggle \
+ ROM_USBHostEndpointDataToggle
+#else
+#define MAP_USBHostEndpointDataToggle \
+ USBHostEndpointDataToggle
+#endif
+#ifdef ROM_USBHostEndpointStatusClear
+#define MAP_USBHostEndpointStatusClear \
+ ROM_USBHostEndpointStatusClear
+#else
+#define MAP_USBHostEndpointStatusClear \
+ USBHostEndpointStatusClear
+#endif
+#ifdef ROM_USBHostHubAddrGet
+#define MAP_USBHostHubAddrGet \
+ ROM_USBHostHubAddrGet
+#else
+#define MAP_USBHostHubAddrGet \
+ USBHostHubAddrGet
+#endif
+#ifdef ROM_USBHostHubAddrSet
+#define MAP_USBHostHubAddrSet \
+ ROM_USBHostHubAddrSet
+#else
+#define MAP_USBHostHubAddrSet \
+ USBHostHubAddrSet
+#endif
+#ifdef ROM_USBHostPwrDisable
+#define MAP_USBHostPwrDisable \
+ ROM_USBHostPwrDisable
+#else
+#define MAP_USBHostPwrDisable \
+ USBHostPwrDisable
+#endif
+#ifdef ROM_USBHostPwrEnable
+#define MAP_USBHostPwrEnable \
+ ROM_USBHostPwrEnable
+#else
+#define MAP_USBHostPwrEnable \
+ USBHostPwrEnable
+#endif
+#ifdef ROM_USBHostPwrConfig
+#define MAP_USBHostPwrConfig \
+ ROM_USBHostPwrConfig
+#else
+#define MAP_USBHostPwrConfig \
+ USBHostPwrConfig
+#endif
+#ifdef ROM_USBHostPwrFaultDisable
+#define MAP_USBHostPwrFaultDisable \
+ ROM_USBHostPwrFaultDisable
+#else
+#define MAP_USBHostPwrFaultDisable \
+ USBHostPwrFaultDisable
+#endif
+#ifdef ROM_USBHostPwrFaultEnable
+#define MAP_USBHostPwrFaultEnable \
+ ROM_USBHostPwrFaultEnable
+#else
+#define MAP_USBHostPwrFaultEnable \
+ USBHostPwrFaultEnable
+#endif
+#ifdef ROM_USBHostRequestIN
+#define MAP_USBHostRequestIN \
+ ROM_USBHostRequestIN
+#else
+#define MAP_USBHostRequestIN \
+ USBHostRequestIN
+#endif
+#ifdef ROM_USBHostRequestStatus
+#define MAP_USBHostRequestStatus \
+ ROM_USBHostRequestStatus
+#else
+#define MAP_USBHostRequestStatus \
+ USBHostRequestStatus
+#endif
+#ifdef ROM_USBHostReset
+#define MAP_USBHostReset \
+ ROM_USBHostReset
+#else
+#define MAP_USBHostReset \
+ USBHostReset
+#endif
+#ifdef ROM_USBHostResume
+#define MAP_USBHostResume \
+ ROM_USBHostResume
+#else
+#define MAP_USBHostResume \
+ USBHostResume
+#endif
+#ifdef ROM_USBHostSpeedGet
+#define MAP_USBHostSpeedGet \
+ ROM_USBHostSpeedGet
+#else
+#define MAP_USBHostSpeedGet \
+ USBHostSpeedGet
+#endif
+#ifdef ROM_USBHostSuspend
+#define MAP_USBHostSuspend \
+ ROM_USBHostSuspend
+#else
+#define MAP_USBHostSuspend \
+ USBHostSuspend
+#endif
+#ifdef ROM_USBIntDisable
+#define MAP_USBIntDisable \
+ ROM_USBIntDisable
+#else
+#define MAP_USBIntDisable \
+ USBIntDisable
+#endif
+#ifdef ROM_USBIntEnable
+#define MAP_USBIntEnable \
+ ROM_USBIntEnable
+#else
+#define MAP_USBIntEnable \
+ USBIntEnable
+#endif
+#ifdef ROM_USBDevEndpointConfigGet
+#define MAP_USBDevEndpointConfigGet \
+ ROM_USBDevEndpointConfigGet
+#else
+#define MAP_USBDevEndpointConfigGet \
+ USBDevEndpointConfigGet
+#endif
+#ifdef ROM_USBEndpointDataAvail
+#define MAP_USBEndpointDataAvail \
+ ROM_USBEndpointDataAvail
+#else
+#define MAP_USBEndpointDataAvail \
+ USBEndpointDataAvail
+#endif
+#ifdef ROM_USBOTGHostRequest
+#define MAP_USBOTGHostRequest \
+ ROM_USBOTGHostRequest
+#else
+#define MAP_USBOTGHostRequest \
+ USBOTGHostRequest
+#endif
+#ifdef ROM_USBModeGet
+#define MAP_USBModeGet \
+ ROM_USBModeGet
+#else
+#define MAP_USBModeGet \
+ USBModeGet
+#endif
+#ifdef ROM_USBEndpointDMAChannel
+#define MAP_USBEndpointDMAChannel \
+ ROM_USBEndpointDMAChannel
+#else
+#define MAP_USBEndpointDMAChannel \
+ USBEndpointDMAChannel
+#endif
+#ifdef ROM_USBIntDisableControl
+#define MAP_USBIntDisableControl \
+ ROM_USBIntDisableControl
+#else
+#define MAP_USBIntDisableControl \
+ USBIntDisableControl
+#endif
+#ifdef ROM_USBIntEnableControl
+#define MAP_USBIntEnableControl \
+ ROM_USBIntEnableControl
+#else
+#define MAP_USBIntEnableControl \
+ USBIntEnableControl
+#endif
+#ifdef ROM_USBIntStatusControl
+#define MAP_USBIntStatusControl \
+ ROM_USBIntStatusControl
+#else
+#define MAP_USBIntStatusControl \
+ USBIntStatusControl
+#endif
+#ifdef ROM_USBIntDisableEndpoint
+#define MAP_USBIntDisableEndpoint \
+ ROM_USBIntDisableEndpoint
+#else
+#define MAP_USBIntDisableEndpoint \
+ USBIntDisableEndpoint
+#endif
+#ifdef ROM_USBIntEnableEndpoint
+#define MAP_USBIntEnableEndpoint \
+ ROM_USBIntEnableEndpoint
+#else
+#define MAP_USBIntEnableEndpoint \
+ USBIntEnableEndpoint
+#endif
+#ifdef ROM_USBIntStatusEndpoint
+#define MAP_USBIntStatusEndpoint \
+ ROM_USBIntStatusEndpoint
+#else
+#define MAP_USBIntStatusEndpoint \
+ USBIntStatusEndpoint
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Watchdog API.
+//
+//*****************************************************************************
+#ifdef ROM_WatchdogIntClear
+#define MAP_WatchdogIntClear \
+ ROM_WatchdogIntClear
+#else
+#define MAP_WatchdogIntClear \
+ WatchdogIntClear
+#endif
+#ifdef ROM_WatchdogRunning
+#define MAP_WatchdogRunning \
+ ROM_WatchdogRunning
+#else
+#define MAP_WatchdogRunning \
+ WatchdogRunning
+#endif
+#ifdef ROM_WatchdogEnable
+#define MAP_WatchdogEnable \
+ ROM_WatchdogEnable
+#else
+#define MAP_WatchdogEnable \
+ WatchdogEnable
+#endif
+#ifdef ROM_WatchdogResetEnable
+#define MAP_WatchdogResetEnable \
+ ROM_WatchdogResetEnable
+#else
+#define MAP_WatchdogResetEnable \
+ WatchdogResetEnable
+#endif
+#ifdef ROM_WatchdogResetDisable
+#define MAP_WatchdogResetDisable \
+ ROM_WatchdogResetDisable
+#else
+#define MAP_WatchdogResetDisable \
+ WatchdogResetDisable
+#endif
+#ifdef ROM_WatchdogLock
+#define MAP_WatchdogLock \
+ ROM_WatchdogLock
+#else
+#define MAP_WatchdogLock \
+ WatchdogLock
+#endif
+#ifdef ROM_WatchdogUnlock
+#define MAP_WatchdogUnlock \
+ ROM_WatchdogUnlock
+#else
+#define MAP_WatchdogUnlock \
+ WatchdogUnlock
+#endif
+#ifdef ROM_WatchdogLockState
+#define MAP_WatchdogLockState \
+ ROM_WatchdogLockState
+#else
+#define MAP_WatchdogLockState \
+ WatchdogLockState
+#endif
+#ifdef ROM_WatchdogReloadSet
+#define MAP_WatchdogReloadSet \
+ ROM_WatchdogReloadSet
+#else
+#define MAP_WatchdogReloadSet \
+ WatchdogReloadSet
+#endif
+#ifdef ROM_WatchdogReloadGet
+#define MAP_WatchdogReloadGet \
+ ROM_WatchdogReloadGet
+#else
+#define MAP_WatchdogReloadGet \
+ WatchdogReloadGet
+#endif
+#ifdef ROM_WatchdogValueGet
+#define MAP_WatchdogValueGet \
+ ROM_WatchdogValueGet
+#else
+#define MAP_WatchdogValueGet \
+ WatchdogValueGet
+#endif
+#ifdef ROM_WatchdogIntEnable
+#define MAP_WatchdogIntEnable \
+ ROM_WatchdogIntEnable
+#else
+#define MAP_WatchdogIntEnable \
+ WatchdogIntEnable
+#endif
+#ifdef ROM_WatchdogIntStatus
+#define MAP_WatchdogIntStatus \
+ ROM_WatchdogIntStatus
+#else
+#define MAP_WatchdogIntStatus \
+ WatchdogIntStatus
+#endif
+#ifdef ROM_WatchdogStallEnable
+#define MAP_WatchdogStallEnable \
+ ROM_WatchdogStallEnable
+#else
+#define MAP_WatchdogStallEnable \
+ WatchdogStallEnable
+#endif
+#ifdef ROM_WatchdogStallDisable
+#define MAP_WatchdogStallDisable \
+ ROM_WatchdogStallDisable
+#else
+#define MAP_WatchdogStallDisable \
+ WatchdogStallDisable
+#endif
+
+//*****************************************************************************
+//
+// Deprecated ROM functions.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define MAP_FlashIntGetStatus \
+ MAP_FlashIntStatus
+#define MAP_USBDevEndpointConfig \
+ MAP_USBDevEndpointConfigSet
+#define MAP_USBHostPwrFaultConfig \
+ MAP_USBHostPwrConfig
+#endif
+
+#endif // __ROM_MAP_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/ssi.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/ssi.c
new file mode 100644
index 00000000..48923091
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/ssi.c
@@ -0,0 +1,706 @@
+//*****************************************************************************
+//
+// ssi.c - Driver for Synchronous Serial Interface.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup ssi_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_ssi.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/ssi.h"
+
+//*****************************************************************************
+//
+//! Configures the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulSSIClk is the rate of the clock supplied to the SSI module.
+//! \param ulProtocol specifies the data transfer protocol.
+//! \param ulMode specifies the mode of operation.
+//! \param ulBitRate specifies the clock rate.
+//! \param ulDataWidth specifies number of bits transferred per frame.
+//!
+//! This function configures the synchronous serial interface. It sets
+//! the SSI protocol, mode of operation, bit rate, and data width.
+//!
+//! The \e ulProtocol parameter defines the data frame format. The
+//! \e ulProtocol parameter can be one of the following values:
+//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
+//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola
+//! frame formats imply the following polarity and phase configurations:
+//!
+//!
+//! Polarity Phase Mode
+//! 0 0 SSI_FRF_MOTO_MODE_0
+//! 0 1 SSI_FRF_MOTO_MODE_1
+//! 1 0 SSI_FRF_MOTO_MODE_2
+//! 1 1 SSI_FRF_MOTO_MODE_3
+//!
+//!
+//! The \e ulMode parameter defines the operating mode of the SSI module. The
+//! SSI module can operate as a master or slave; if a slave, the SSI can be
+//! configured to disable output on its serial output line. The \e ulMode
+//! parameter can be one of the following values: \b SSI_MODE_MASTER,
+//! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
+//!
+//! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate
+//! must satisfy the following clock ratio criteria:
+//!
+//! - FSSI >= 2 * bit rate (master mode)
+//! - FSSI >= 12 * bit rate (slave modes)
+//!
+//! where FSSI is the frequency of the clock supplied to the SSI module.
+//!
+//! The \e ulDataWidth parameter defines the width of the data transfers, and
+//! can be a value between 4 and 16, inclusive.
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original SSIConfig() API and performs the same
+//! actions. A macro is provided in ssi.h to map the original API to
+//! this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
+ unsigned long ulProtocol, unsigned long ulMode,
+ unsigned long ulBitRate, unsigned long ulDataWidth)
+{
+ unsigned long ulMaxBitRate;
+ unsigned long ulRegVal;
+ unsigned long ulPreDiv;
+ unsigned long ulSCR;
+ unsigned long ulSPH_SPO;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+ ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) ||
+ (ulProtocol == SSI_FRF_MOTO_MODE_1) ||
+ (ulProtocol == SSI_FRF_MOTO_MODE_2) ||
+ (ulProtocol == SSI_FRF_MOTO_MODE_3) ||
+ (ulProtocol == SSI_FRF_TI) ||
+ (ulProtocol == SSI_FRF_NMW));
+ ASSERT((ulMode == SSI_MODE_MASTER) ||
+ (ulMode == SSI_MODE_SLAVE) ||
+ (ulMode == SSI_MODE_SLAVE_OD));
+ ASSERT(((ulMode == SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 2))) ||
+ ((ulMode != SSI_MODE_MASTER) && (ulBitRate <= (ulSSIClk / 12))));
+ ASSERT((ulSSIClk / ulBitRate) <= (254 * 256));
+ ASSERT((ulDataWidth >= 4) && (ulDataWidth <= 16));
+
+ //
+ // Set the mode.
+ //
+ ulRegVal = (ulMode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0;
+ ulRegVal |= (ulMode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS;
+ HWREG(ulBase + SSI_O_CR1) = ulRegVal;
+
+ //
+ // Set the clock predivider.
+ //
+ ulMaxBitRate = ulSSIClk / ulBitRate;
+ ulPreDiv = 0;
+ do
+ {
+ ulPreDiv += 2;
+ ulSCR = (ulMaxBitRate / ulPreDiv) - 1;
+ }
+ while(ulSCR > 255);
+ HWREG(ulBase + SSI_O_CPSR) = ulPreDiv;
+
+ //
+ // Set protocol and clock rate.
+ //
+ ulSPH_SPO = (ulProtocol & 3) << 6;
+ ulProtocol &= SSI_CR0_FRF_M;
+ ulRegVal = (ulSCR << 8) | ulSPH_SPO | ulProtocol | (ulDataWidth - 1);
+ HWREG(ulBase + SSI_O_CR0) = ulRegVal;
+}
+
+//*****************************************************************************
+//
+//! Enables the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//!
+//! This function enables operation of the synchronous serial interface. The
+//! synchronous serial interface must be configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + SSI_O_CR1) |= SSI_CR1_SSE;
+}
+
+//*****************************************************************************
+//
+//! Disables the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//!
+//! This function disables operation of the synchronous serial interface.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Read-modify-write the enable bit.
+ //
+ HWREG(ulBase + SSI_O_CR1) &= ~(SSI_CR1_SSE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! synchronous serial interface interrupt occurs.
+//!
+//! This sets the handler to be called when an SSI interrupt
+//! occurs. This will enable the global interrupt in the interrupt controller;
+//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary,
+//! it is the interrupt handler's responsibility to clear the interrupt source
+//! via SSIIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Determine the interrupt number based on the SSI port.
+ //
+ ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
+
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the synchronous serial interface interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the synchronous serial interface.
+//!
+//! \param ulBase specifies the SSI module base address.
+//!
+//! This function will clear the handler to be called when a SSI
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Determine the interrupt number based on the SSI port.
+ //
+ ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Enables individual SSI interrupt sources.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated SSI interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor. The \e ulIntFlags parameter can be any of the
+//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR values.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + SSI_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual SSI interrupt sources.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated SSI interrupt sources. The \e ulIntFlags parameter
+//! can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR
+//! values.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + SSI_O_IM) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param bMasked is \b false if the raw interrupt status is required or
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the SSI module. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, and \b SSI_RXOR.
+//
+//*****************************************************************************
+unsigned long
+SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + SSI_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + SSI_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears SSI interrupt sources.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified SSI interrupt sources are cleared so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupts from being recognized again immediately upon exit. The
+//! \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO and
+//! \b SSI_RXOR values.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + SSI_O_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Puts a data element into the SSI transmit FIFO.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulData is the data to be transmitted over the SSI interface.
+//!
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module.
+//!
+//! \note The upper 32 - N bits of the \e ulData are discarded by the hardware,
+//! where N is the data width as configured by SSIConfigSetExpClk(). For
+//! example, if the interface is configured for 8-bit data width, the upper 24
+//! bits of \e ulData are discarded.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDataPut(unsigned long ulBase, unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+ ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
+ SSI_CR0_DSS_M))) == 0);
+
+ //
+ // Wait until there is space.
+ //
+ while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF))
+ {
+ }
+
+ //
+ // Write the data to the SSI.
+ //
+ HWREG(ulBase + SSI_O_DR) = ulData;
+}
+
+//*****************************************************************************
+//
+//! Puts a data element into the SSI transmit FIFO.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param ulData is the data to be transmitted over the SSI interface.
+//!
+//! This function places the supplied data into the transmit FIFO of the
+//! specified SSI module. If there is no space in the FIFO, then this function
+//! returns a zero.
+//!
+//! This function replaces the original SSIDataNonBlockingPut() API and
+//! performs the same actions. A macro is provided in ssi.h to map
+//! the original API to this API.
+//!
+//! \note The upper 32 - N bits of the \e ulData are discarded by the hardware,
+//! where N is the data width as configured by SSIConfigSetExpClk(). For
+//! example, if the interface is configured for 8-bit data width, the upper 24
+//! bits of \e ulData are discarded.
+//!
+//! \return Returns the number of elements written to the SSI transmit FIFO.
+//
+//*****************************************************************************
+long
+SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+ ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
+ SSI_CR0_DSS_M))) == 0);
+
+ //
+ // Check for space to write.
+ //
+ if(HWREG(ulBase + SSI_O_SR) & SSI_SR_TNF)
+ {
+ HWREG(ulBase + SSI_O_DR) = ulData;
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets a data element from the SSI receive FIFO.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param pulData is a pointer to a storage location for data that was
+//! received over the SSI interface.
+//!
+//! This function gets received data from the receive FIFO of the specified
+//! SSI module and places that data into the location specified by the
+//! \e pulData parameter.
+//!
+//! \note Only the lower N bits of the value written to \e pulData contain
+//! valid data, where N is the data width as configured by
+//! SSIConfigSetExpClk(). For example, if the interface is configured for
+//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
+//! contain valid data.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDataGet(unsigned long ulBase, unsigned long *pulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Wait until there is data to be read.
+ //
+ while(!(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE))
+ {
+ }
+
+ //
+ // Read data from SSI.
+ //
+ *pulData = HWREG(ulBase + SSI_O_DR);
+}
+
+//*****************************************************************************
+//
+//! Gets a data element from the SSI receive FIFO.
+//!
+//! \param ulBase specifies the SSI module base address.
+//! \param pulData is a pointer to a storage location for data that was
+//! received over the SSI interface.
+//!
+//! This function gets received data from the receive FIFO of the specified SSI
+//! module and places that data into the location specified by the \e ulData
+//! parameter. If there is no data in the FIFO, then this function returns a
+//! zero.
+//!
+//! This function replaces the original SSIDataNonBlockingGet() API and
+//! performs the same actions. A macro is provided in ssi.h to map
+//! the original API to this API.
+//!
+//! \note Only the lower N bits of the value written to \e pulData contain
+//! valid data, where N is the data width as configured by
+//! SSIConfigSetExpClk(). For example, if the interface is configured for
+//! 8-bit data width, only the lower 8 bits of the value written to \e pulData
+//! contain valid data.
+//!
+//! \return Returns the number of elements read from the SSI receive FIFO.
+//
+//*****************************************************************************
+long
+SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Check for data to read.
+ //
+ if(HWREG(ulBase + SSI_O_SR) & SSI_SR_RNE)
+ {
+ *pulData = HWREG(ulBase + SSI_O_DR);
+ return(1);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enable SSI DMA operation.
+//!
+//! \param ulBase is the base address of the SSI port.
+//! \param ulDMAFlags is a bit mask of the DMA features to enable.
+//!
+//! The specified SSI DMA features are enabled. The SSI can be
+//! configured to use DMA for transmit and/or receive data transfers.
+//! The \e ulDMAFlags parameter is the logical OR of any of the following
+//! values:
+//!
+//! - SSI_DMA_RX - enable DMA for receive
+//! - SSI_DMA_TX - enable DMA for transmit
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the SSI.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Set the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Disable SSI DMA operation.
+//!
+//! \param ulBase is the base address of the SSI port.
+//! \param ulDMAFlags is a bit mask of the DMA features to disable.
+//!
+//! This function is used to disable SSI DMA features that were enabled
+//! by SSIDMAEnable(). The specified SSI DMA features are disabled. The
+//! \e ulDMAFlags parameter is the logical OR of any of the following values:
+//!
+//! - SSI_DMA_RX - disable DMA for receive
+//! - SSI_DMA_TX - disable DMA for transmit
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Clear the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Determines whether the SSI transmitter is busy or not.
+//!
+//! \param ulBase is the base address of the SSI port.
+//!
+//! Allows the caller to determine whether all transmitted bytes have cleared
+//! the transmitter hardware. If \b false is returned, then the transmit FIFO
+//! is empty and all bits of the last transmitted word have left the hardware
+//! shift register.
+//!
+//! \return Returns \b true if the SSI is transmitting or \b false if all
+//! transmissions are complete.
+//
+//*****************************************************************************
+tBoolean
+SSIBusy(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
+
+ //
+ // Determine if the SSI is busy.
+ //
+ return((HWREG(ulBase + SSI_O_SR) & SSI_SR_BSY) ? true : false);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/ssi.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/ssi.h
new file mode 100644
index 00000000..7970bdda
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/ssi.h
@@ -0,0 +1,125 @@
+//*****************************************************************************
+//
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __SSI_H__
+#define __SSI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
+// as the ulIntFlags parameter, and returned by SSIIntStatus.
+//
+//*****************************************************************************
+#define SSI_TXFF 0x00000008 // TX FIFO half full or less
+#define SSI_RXFF 0x00000004 // RX FIFO half full or more
+#define SSI_RXTO 0x00000002 // RX timeout
+#define SSI_RXOR 0x00000001 // RX overrun
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIConfigSetExpClk.
+//
+//*****************************************************************************
+#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
+#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
+#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
+#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
+#define SSI_FRF_TI 0x00000010 // TI frame format
+#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
+
+#define SSI_MODE_MASTER 0x00000000 // SSI master
+#define SSI_MODE_SLAVE 0x00000001 // SSI slave
+#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
+
+//*****************************************************************************
+//
+// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
+//
+//*****************************************************************************
+#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
+#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
+ unsigned long ulProtocol, unsigned long ulMode,
+ unsigned long ulBitRate,
+ unsigned long ulDataWidth);
+extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
+extern long SSIDataGetNonBlocking(unsigned long ulBase,
+ unsigned long *pulData);
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
+extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
+extern void SSIDisable(unsigned long ulBase);
+extern void SSIEnable(unsigned long ulBase);
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void SSIIntUnregister(unsigned long ulBase);
+extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern tBoolean SSIBusy(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several SSI APIs have been renamed, with the original function name being
+// deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "driverlib/sysctl.h"
+#define SSIConfig(a, b, c, d, e) \
+ SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
+#define SSIDataNonBlockingGet(a, b) \
+ SSIDataGetNonBlocking(a, b)
+#define SSIDataNonBlockingPut(a, b) \
+ SSIDataPutNonBlocking(a, b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SSI_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/sysctl.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/sysctl.c
new file mode 100644
index 00000000..e0023a9d
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/sysctl.c
@@ -0,0 +1,2366 @@
+//*****************************************************************************
+//
+// sysctl.c - Driver for the system controller.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup sysctl_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "driverlib/cpu.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/sysctl.h"
+
+//*****************************************************************************
+//
+// This macro extracts the array index out of the peripheral number.
+//
+//*****************************************************************************
+#define SYSCTL_PERIPH_INDEX(a) (((a) >> 28) & 0xf)
+
+//*****************************************************************************
+//
+// This macro constructs the peripheral bit mask from the peripheral number.
+//
+//*****************************************************************************
+#define SYSCTL_PERIPH_MASK(a) (((a) & 0xffff) << (((a) & 0x001f0000) >> 16))
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL DC? register that
+// contains the peripheral present bit for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulDCRegs[] =
+{
+ SYSCTL_DC1,
+ SYSCTL_DC2,
+ SYSCTL_DC4,
+ SYSCTL_DC1
+};
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SRCR? register that
+// controls the software reset for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulSRCRRegs[] =
+{
+ SYSCTL_SRCR0,
+ SYSCTL_SRCR1,
+ SYSCTL_SRCR2
+};
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register that
+// controls the run-mode enable for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulRCGCRegs[] =
+{
+ SYSCTL_RCGC0,
+ SYSCTL_RCGC1,
+ SYSCTL_RCGC2
+};
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_SCGC? register that
+// controls the sleep-mode enable for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulSCGCRegs[] =
+{
+ SYSCTL_SCGC0,
+ SYSCTL_SCGC1,
+ SYSCTL_SCGC2
+};
+
+//*****************************************************************************
+//
+// An array that maps the "peripheral set" number (which is stored in the upper
+// nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_DCGC? register that
+// controls the deep-sleep-mode enable for that peripheral.
+//
+//*****************************************************************************
+static const unsigned long g_pulDCGCRegs[] =
+{
+ SYSCTL_DCGC0,
+ SYSCTL_DCGC1,
+ SYSCTL_DCGC2
+};
+
+//*****************************************************************************
+//
+// An array that maps the crystal number in RCC to a frequency.
+//
+//*****************************************************************************
+static const unsigned long g_pulXtals[] =
+{
+ 1000000,
+ 1843200,
+ 2000000,
+ 2457600,
+ 3579545,
+ 3686400,
+ 4000000,
+ 4096000,
+ 4915200,
+ 5000000,
+ 5120000,
+ 6000000,
+ 6144000,
+ 7372800,
+ 8000000,
+ 8192000,
+ 10000000,
+ 12000000,
+ 12288000,
+ 13560000,
+ 14318180,
+ 16000000,
+ 16384000
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a peripheral identifier.
+//!
+//! \param ulPeripheral is the peripheral identifier.
+//!
+//! This function determines if a peripheral identifier is valid.
+//!
+//! \return Returns \b true if the peripheral identifier is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+SysCtlPeripheralValid(unsigned long ulPeripheral)
+{
+ return((ulPeripheral == SYSCTL_PERIPH_ADC0) ||
+ (ulPeripheral == SYSCTL_PERIPH_ADC1) ||
+ (ulPeripheral == SYSCTL_PERIPH_CAN0) ||
+ (ulPeripheral == SYSCTL_PERIPH_CAN1) ||
+ (ulPeripheral == SYSCTL_PERIPH_CAN2) ||
+ (ulPeripheral == SYSCTL_PERIPH_COMP0) ||
+ (ulPeripheral == SYSCTL_PERIPH_COMP1) ||
+ (ulPeripheral == SYSCTL_PERIPH_COMP2) ||
+ (ulPeripheral == SYSCTL_PERIPH_EPI0) ||
+ (ulPeripheral == SYSCTL_PERIPH_ETH) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOA) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOB) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOC) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOD) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOE) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOF) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOG) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOH) ||
+ (ulPeripheral == SYSCTL_PERIPH_GPIOJ) ||
+ (ulPeripheral == SYSCTL_PERIPH_HIBERNATE) ||
+ (ulPeripheral == SYSCTL_PERIPH_I2C0) ||
+ (ulPeripheral == SYSCTL_PERIPH_I2C1) ||
+ (ulPeripheral == SYSCTL_PERIPH_I2S0) ||
+ (ulPeripheral == SYSCTL_PERIPH_IEEE1588) ||
+ (ulPeripheral == SYSCTL_PERIPH_MPU) ||
+ (ulPeripheral == SYSCTL_PERIPH_PLL) ||
+ (ulPeripheral == SYSCTL_PERIPH_PWM) ||
+ (ulPeripheral == SYSCTL_PERIPH_QEI0) ||
+ (ulPeripheral == SYSCTL_PERIPH_QEI1) ||
+ (ulPeripheral == SYSCTL_PERIPH_SSI0) ||
+ (ulPeripheral == SYSCTL_PERIPH_SSI1) ||
+ (ulPeripheral == SYSCTL_PERIPH_TEMP) ||
+ (ulPeripheral == SYSCTL_PERIPH_TIMER0) ||
+ (ulPeripheral == SYSCTL_PERIPH_TIMER1) ||
+ (ulPeripheral == SYSCTL_PERIPH_TIMER2) ||
+ (ulPeripheral == SYSCTL_PERIPH_TIMER3) ||
+ (ulPeripheral == SYSCTL_PERIPH_UART0) ||
+ (ulPeripheral == SYSCTL_PERIPH_UART1) ||
+ (ulPeripheral == SYSCTL_PERIPH_UART2) ||
+ (ulPeripheral == SYSCTL_PERIPH_UDMA) ||
+ (ulPeripheral == SYSCTL_PERIPH_USB0) ||
+ (ulPeripheral == SYSCTL_PERIPH_WDOG0) ||
+ (ulPeripheral == SYSCTL_PERIPH_WDOG1));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Gets the size of the SRAM.
+//!
+//! This function determines the size of the SRAM on the Stellaris device.
+//!
+//! \return The total number of bytes of SRAM.
+//
+//*****************************************************************************
+unsigned long
+SysCtlSRAMSizeGet(void)
+{
+ //
+ // Compute the size of the SRAM.
+ //
+ return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_SRAMSZ_M) >> 8) + 0x100);
+}
+
+//*****************************************************************************
+//
+//! Gets the size of the flash.
+//!
+//! This function determines the size of the flash on the Stellaris device.
+//!
+//! \return The total number of bytes of flash.
+//
+//*****************************************************************************
+unsigned long
+SysCtlFlashSizeGet(void)
+{
+ //
+ // Compute the size of the flash.
+ //
+ return(((HWREG(SYSCTL_DC0) & SYSCTL_DC0_FLASHSZ_M) << 11) + 0x800);
+}
+
+//*****************************************************************************
+//
+//! Determines if a pin is present.
+//!
+//! \param ulPin is the pin in question.
+//!
+//! Determines if a particular pin is present in the device. The PWM, analog
+//! comparators, ADC, and timers have a varying number of pins across members
+//! of the Stellaris family; this will determine which are present on this
+//! device.
+//!
+//! The \e ulPin argument must be only one of the following values:
+//! \b SYSCTL_PIN_PWM0, \b SYSCTL_PIN_PWM1, \b SYSCTL_PIN_PWM2,
+//! \b SYSCTL_PIN_PWM3, \b SYSCTL_PIN_PWM4, \b SYSCTL_PIN_PWM5,
+//! \b SYSCTL_PIN_C0MINUS, \b SYSCTL_PIN_C0PLUS, \b SYSCTL_PIN_C0O,
+//! \b SYSCTL_PIN_C1MINUS, \b SYSCTL_PIN_C1PLUS, \b SYSCTL_PIN_C1O,
+//! \b SYSCTL_PIN_C2MINUS, \b SYSCTL_PIN_C2PLUS, \b SYSCTL_PIN_C2O,
+//! \b SYSCTL_PIN_ADC0, \b SYSCTL_PIN_ADC1, \b SYSCTL_PIN_ADC2,
+//! \b SYSCTL_PIN_ADC3, \b SYSCTL_PIN_ADC4, \b SYSCTL_PIN_ADC5,
+//! \b SYSCTL_PIN_ADC6, \b SYSCTL_PIN_ADC7, \b SYSCTL_PIN_CCP0,
+//! \b SYSCTL_PIN_CCP1, \b SYSCTL_PIN_CCP2, \b SYSCTL_PIN_CCP3,
+//! \b SYSCTL_PIN_CCP4, \b SYSCTL_PIN_CCP5, \b SYSCTL_PIN_CCP6,
+//! \b SYSCTL_PIN_CCP7, \b SYSCTL_PIN_32KHZ, or \b SYSCTL_PIN_MC_FAULT0.
+//!
+//! \return Returns \b true if the specified pin is present and \b false if it
+//! is not.
+//
+//*****************************************************************************
+tBoolean
+SysCtlPinPresent(unsigned long ulPin)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulPin == SYSCTL_PIN_PWM0) ||
+ (ulPin == SYSCTL_PIN_PWM1) ||
+ (ulPin == SYSCTL_PIN_PWM2) ||
+ (ulPin == SYSCTL_PIN_PWM3) ||
+ (ulPin == SYSCTL_PIN_PWM4) ||
+ (ulPin == SYSCTL_PIN_PWM5) ||
+ (ulPin == SYSCTL_PIN_C0MINUS) ||
+ (ulPin == SYSCTL_PIN_C0PLUS) ||
+ (ulPin == SYSCTL_PIN_C0O) ||
+ (ulPin == SYSCTL_PIN_C1MINUS) ||
+ (ulPin == SYSCTL_PIN_C1PLUS) ||
+ (ulPin == SYSCTL_PIN_C1O) ||
+ (ulPin == SYSCTL_PIN_C2MINUS) ||
+ (ulPin == SYSCTL_PIN_C2PLUS) ||
+ (ulPin == SYSCTL_PIN_C2O) ||
+ (ulPin == SYSCTL_PIN_MC_FAULT0) ||
+ (ulPin == SYSCTL_PIN_ADC0) ||
+ (ulPin == SYSCTL_PIN_ADC1) ||
+ (ulPin == SYSCTL_PIN_ADC2) ||
+ (ulPin == SYSCTL_PIN_ADC3) ||
+ (ulPin == SYSCTL_PIN_ADC4) ||
+ (ulPin == SYSCTL_PIN_ADC5) ||
+ (ulPin == SYSCTL_PIN_ADC6) ||
+ (ulPin == SYSCTL_PIN_ADC7) ||
+ (ulPin == SYSCTL_PIN_CCP0) ||
+ (ulPin == SYSCTL_PIN_CCP1) ||
+ (ulPin == SYSCTL_PIN_CCP2) ||
+ (ulPin == SYSCTL_PIN_CCP3) ||
+ (ulPin == SYSCTL_PIN_CCP4) ||
+ (ulPin == SYSCTL_PIN_CCP5) ||
+ (ulPin == SYSCTL_PIN_32KHZ));
+
+ //
+ // Determine if this pin is present.
+ //
+ if(HWREG(SYSCTL_DC3) & ulPin)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Determines if a peripheral is present.
+//!
+//! \param ulPeripheral is the peripheral in question.
+//!
+//! Determines if a particular peripheral is present in the device. Each
+//! member of the Stellaris family has a different peripheral set; this will
+//! determine which are present on this device.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_IEEE1588,
+//! \b SYSCTL_PERIPH_MPU, \b SYSCTL_PERIPH_PLL, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
+//!
+//! \return Returns \b true if the specified peripheral is present and \b false
+//! if it is not.
+//
+//*****************************************************************************
+tBoolean
+SysCtlPeripheralPresent(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Read the correct DC register and determine if this peripheral exists.
+ //
+ if(ulPeripheral == SYSCTL_PERIPH_USB0)
+ {
+ //
+ // USB is a special case since the DC bit is missing for USB0.
+ //
+ if(HWREG(SYSCTL_DC6) & SYSCTL_DC6_USB0_M)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+ }
+ else if(HWREG(g_pulDCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &
+ SYSCTL_PERIPH_MASK(ulPeripheral))
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Performs a software reset of a peripheral.
+//!
+//! \param ulPeripheral is the peripheral to reset.
+//!
+//! This function performs a software reset of the specified peripheral. An
+//! individual peripheral reset signal is asserted for a brief period and then
+//! deasserted, returning the internal state of the peripheral to its reset
+//! condition.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralReset(unsigned long ulPeripheral)
+{
+ volatile unsigned long ulDelay;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Put the peripheral into the reset state.
+ //
+ HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
+ SYSCTL_PERIPH_MASK(ulPeripheral);
+
+ //
+ // Delay for a little bit.
+ //
+ for(ulDelay = 0; ulDelay < 16; ulDelay++)
+ {
+ }
+
+ //
+ // Take the peripheral out of the reset state.
+ //
+ HWREG(g_pulSRCRRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
+ ~SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral.
+//!
+//! \param ulPeripheral is the peripheral to enable.
+//!
+//! Peripherals are enabled with this function. At power-up, all peripherals
+//! are disabled; they must be enabled in order to operate or respond to
+//! register reads/writes.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
+//!
+//! \note It takes five clock cycles after the write to enable a peripheral
+//! before the the peripheral is actually enabled. During this time, attempts
+//! to access the peripheral will result in a bus fault. Care should be taken
+//! to ensure that the peripheral is not accessed during this brief time
+//! period.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralEnable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Enable this peripheral.
+ //
+ HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
+ SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral.
+//!
+//! \param ulPeripheral is the peripheral to disable.
+//!
+//! Peripherals are disabled with this function. Once disabled, they will not
+//! operate or respond to register reads/writes.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDisable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Disable this peripheral.
+ //
+ HWREG(g_pulRCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
+ ~SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral in sleep mode.
+//!
+//! \param ulPeripheral is the peripheral to enable in sleep mode.
+//!
+//! This function allows a peripheral to continue operating when the processor
+//! goes into sleep mode. Since the clocking configuration of the device does
+//! not change, any peripheral can safely continue operating while the
+//! processor is in sleep mode, and can therefore wake the processor from sleep
+//! mode.
+//!
+//! Sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
+//! configuration is maintained but has no effect when sleep mode is entered.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralSleepEnable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Enable this peripheral in sleep mode.
+ //
+ HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
+ SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral in sleep mode.
+//!
+//! \param ulPeripheral is the peripheral to disable in sleep mode.
+//!
+//! This function causes a peripheral to stop operating when the processor goes
+//! into sleep mode. Disabling peripherals while in sleep mode helps to lower
+//! the current draw of the device. If enabled (via SysCtlPeripheralEnable()),
+//! the peripheral will automatically resume operation when the processor
+//! leaves sleep mode, maintaining its entire state from before sleep mode was
+//! entered.
+//!
+//! Sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral sleep mode
+//! configuration is maintained but has no effect when sleep mode is entered.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralSleepDisable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Disable this peripheral in sleep mode.
+ //
+ HWREG(g_pulSCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
+ ~SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Enables a peripheral in deep-sleep mode.
+//!
+//! \param ulPeripheral is the peripheral to enable in deep-sleep mode.
+//!
+//! This function allows a peripheral to continue operating when the processor
+//! goes into deep-sleep mode. Since the clocking configuration of the device
+//! may change, not all peripherals can safely continue operating while the
+//! processor is in sleep mode. Those that must run at a particular frequency
+//! (such as a UART) will not work as expected if the clock changes. It is the
+//! responsibility of the caller to make sensible choices.
+//!
+//! Deep-sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
+//! configuration is maintained but has no effect when deep-sleep mode is
+//! entered.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Enable this peripheral in deep-sleep mode.
+ //
+ HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) |=
+ SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Disables a peripheral in deep-sleep mode.
+//!
+//! \param ulPeripheral is the peripheral to disable in deep-sleep mode.
+//!
+//! This function causes a peripheral to stop operating when the processor goes
+//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps
+//! to lower the current draw of the device, and can keep peripherals that
+//! require a particular clock frequency from operating when the clock changes
+//! as a result of entering deep-sleep mode. If enabled (via
+//! SysCtlPeripheralEnable()), the peripheral will automatically resume
+//! operation when the processor leaves deep-sleep mode, maintaining its entire
+//! state from before deep-sleep mode was entered.
+//!
+//! Deep-sleep mode clocking of peripherals must be enabled via
+//! SysCtlPeripheralClockGating(); if disabled, the peripheral deep-sleep mode
+//! configuration is maintained but has no effect when deep-sleep mode is
+//! entered.
+//!
+//! The \e ulPeripheral parameter must be only one of the following values:
+//! \b SYSCTL_PERIPH_ADC0, \b SYSCTL_PERIPH_ADC1, \b SYSCTL_PERIPH_CAN0,
+//! \b SYSCTL_PERIPH_CAN1, \b SYSCTL_PERIPH_CAN2, \b SYSCTL_PERIPH_COMP0,
+//! \b SYSCTL_PERIPH_COMP1, \b SYSCTL_PERIPH_COMP2, \b SYSCTL_PERIPH_EPI0,
+//! \b SYSCTL_PERIPH_ETH, \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB,
+//! \b SYSCTL_PERIPH_GPIOC, \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE,
+//! \b SYSCTL_PERIPH_GPIOF, \b SYSCTL_PERIPH_GPIOG, \b SYSCTL_PERIPH_GPIOH,
+//! \b SYSCTL_PERIPH_GPIOJ, \b SYSCTL_PERIPH_HIBERNATE, \b SYSCTL_PERIPH_I2C0,
+//! \b SYSCTL_PERIPH_I2C1, \b SYSCTL_PERIPH_I2S0, \b SYSCTL_PERIPH_PWM,
+//! \b SYSCTL_PERIPH_QEI0, \b SYSCTL_PERIPH_QEI1, \b SYSCTL_PERIPH_SSI0,
+//! \b SYSCTL_PERIPH_SSI1, \b SYSCTL_PERIPH_TIMER0, \b SYSCTL_PERIPH_TIMER1,
+//! \b SYSCTL_PERIPH_TIMER2, \b SYSCTL_PERIPH_TIMER3, \b SYSCTL_PERIPH_TEMP,
+//! \b SYSCTL_PERIPH_UART0, \b SYSCTL_PERIPH_UART1, \b SYSCTL_PERIPH_UART2,
+//! \b SYSCTL_PERIPH_UDMA, \b SYSCTL_PERIPH_USB0, \b SYSCTL_PERIPH_WDOG0, or
+//! \b SYSCTL_PERIPH_WDOG1.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(SysCtlPeripheralValid(ulPeripheral));
+
+ //
+ // Disable this peripheral in deep-sleep mode.
+ //
+ HWREG(g_pulDCGCRegs[SYSCTL_PERIPH_INDEX(ulPeripheral)]) &=
+ ~SYSCTL_PERIPH_MASK(ulPeripheral);
+}
+
+//*****************************************************************************
+//
+//! Controls peripheral clock gating in sleep and deep-sleep mode.
+//!
+//! \param bEnable is a boolean that is \b true if the sleep and deep-sleep
+//! peripheral configuration should be used and \b false if not.
+//!
+//! This function controls how peripherals are clocked when the processor goes
+//! into sleep or deep-sleep mode. By default, the peripherals are clocked the
+//! same as in run mode; if peripheral clock gating is enabled they are clocked
+//! according to the configuration set by SysCtlPeripheralSleepEnable(),
+//! SysCtlPeripheralSleepDisable(), SysCtlPeripheralDeepSleepEnable(), and
+//! SysCtlPeripheralDeepSleepDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPeripheralClockGating(tBoolean bEnable)
+{
+ //
+ // Enable peripheral clock gating as requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_ACG;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_ACG);
+ }
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the system control interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the system
+//! control interrupt occurs.
+//!
+//! This sets the handler to be called when a system control interrupt occurs.
+//! This will enable the global interrupt in the interrupt controller; specific
+//! system control interrupts must be enabled via SysCtlIntEnable(). It is the
+//! interrupt handler's responsibility to clear the interrupt source via
+//! SysCtlIntClear().
+//!
+//! System control can generate interrupts when the PLL achieves lock, if the
+//! internal LDO current limit is exceeded, if the internal oscillator fails,
+//! if the main oscillator fails, if the internal LDO output voltage droops too
+//! much, if the external voltage droops too much, or if the PLL fails.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(INT_SYSCTL, pfnHandler);
+
+ //
+ // Enable the system control interrupt.
+ //
+ IntEnable(INT_SYSCTL);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the system control interrupt.
+//!
+//! This function will clear the handler to be called when a system control
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntUnregister(void)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_SYSCTL);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_SYSCTL);
+}
+
+//*****************************************************************************
+//
+//! Enables individual system control interrupt sources.
+//!
+//! \param ulInts is a bit mask of the interrupt sources to be enabled. Must
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
+//!
+//! Enables the indicated system control interrupt sources. Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntEnable(unsigned long ulInts)
+{
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(SYSCTL_IMC) |= ulInts;
+}
+
+//*****************************************************************************
+//
+//! Disables individual system control interrupt sources.
+//!
+//! \param ulInts is a bit mask of the interrupt sources to be disabled. Must
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
+//!
+//! Disables the indicated system control interrupt sources. Only the sources
+//! that are enabled can be reflected to the processor interrupt; disabled
+//! sources have no effect on the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntDisable(unsigned long ulInts)
+{
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(SYSCTL_IMC) &= ~(ulInts);
+}
+
+//*****************************************************************************
+//
+//! Clears system control interrupt sources.
+//!
+//! \param ulInts is a bit mask of the interrupt sources to be cleared. Must
+//! be a logical OR of \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT,
+//! \b SYSCTL_INT_IOSC_FAIL, \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR,
+//! \b SYSCTL_INT_BOR, and/or \b SYSCTL_INT_PLL_FAIL.
+//!
+//! The specified system control interrupt sources are cleared, so that they no
+//! longer assert. This must be done in the interrupt handler to keep it from
+//! being called again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIntClear(unsigned long ulInts)
+{
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(SYSCTL_MISC) = ulInts;
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the system controller. Either the
+//! raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! \b SYSCTL_INT_PLL_LOCK, \b SYSCTL_INT_CUR_LIMIT, \b SYSCTL_INT_IOSC_FAIL,
+//! \b SYSCTL_INT_MOSC_FAIL, \b SYSCTL_INT_POR, \b SYSCTL_INT_BOR, and
+//! \b SYSCTL_INT_PLL_FAIL.
+//
+//*****************************************************************************
+unsigned long
+SysCtlIntStatus(tBoolean bMasked)
+{
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(SYSCTL_MISC));
+ }
+ else
+ {
+ return(HWREG(SYSCTL_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the output voltage of the LDO.
+//!
+//! \param ulVoltage is the required output voltage from the LDO. Must be one
+//! of \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V,
+//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V,
+//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V,
+//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V.
+//!
+//! This function sets the output voltage of the LDO. The default voltage is
+//! 2.5 V; it can be adjusted +/- 10%.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlLDOSet(unsigned long ulVoltage)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulVoltage == SYSCTL_LDO_2_25V) ||
+ (ulVoltage == SYSCTL_LDO_2_30V) ||
+ (ulVoltage == SYSCTL_LDO_2_35V) ||
+ (ulVoltage == SYSCTL_LDO_2_40V) ||
+ (ulVoltage == SYSCTL_LDO_2_45V) ||
+ (ulVoltage == SYSCTL_LDO_2_50V) ||
+ (ulVoltage == SYSCTL_LDO_2_55V) ||
+ (ulVoltage == SYSCTL_LDO_2_60V) ||
+ (ulVoltage == SYSCTL_LDO_2_65V) ||
+ (ulVoltage == SYSCTL_LDO_2_70V) ||
+ (ulVoltage == SYSCTL_LDO_2_75V));
+
+ //
+ // Set the LDO voltage to the requested value.
+ //
+ HWREG(SYSCTL_LDOPCTL) = ulVoltage;
+}
+
+//*****************************************************************************
+//
+//! Gets the output voltage of the LDO.
+//!
+//! This function determines the output voltage of the LDO, as specified by the
+//! control register.
+//!
+//! \return Returns the current voltage of the LDO; will be one of
+//! \b SYSCTL_LDO_2_25V, \b SYSCTL_LDO_2_30V, \b SYSCTL_LDO_2_35V,
+//! \b SYSCTL_LDO_2_40V, \b SYSCTL_LDO_2_45V, \b SYSCTL_LDO_2_50V,
+//! \b SYSCTL_LDO_2_55V, \b SYSCTL_LDO_2_60V, \b SYSCTL_LDO_2_65V,
+//! \b SYSCTL_LDO_2_70V, or \b SYSCTL_LDO_2_75V.
+//
+//*****************************************************************************
+unsigned long
+SysCtlLDOGet(void)
+{
+ //
+ // Return the LDO voltage setting.
+ //
+ return(HWREG(SYSCTL_LDOPCTL));
+}
+
+//*****************************************************************************
+//
+//! Configures the LDO failure control.
+//!
+//! \param ulConfig is the required LDO failure control setting; can be either
+//! \b SYSCTL_LDOCFG_ARST or \b SYSCTL_LDOCFG_NORST.
+//!
+//! This function allows the LDO to be configured to cause a processor reset
+//! when the output voltage becomes unregulated.
+//!
+//! The LDO failure control is only available on Sandstorm-class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlLDOConfigSet(unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulConfig == SYSCTL_LDOCFG_ARST) ||
+ (ulConfig == SYSCTL_LDOCFG_NORST));
+
+ //
+ // Set the reset control as requested.
+ //
+ HWREG(SYSCTL_LDOARST) = ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Resets the device.
+//!
+//! This function will perform a software reset of the entire device. The
+//! processor and all peripherals will be reset and all device registers will
+//! return to their default values (with the exception of the reset cause
+//! register, which will maintain its current value but have the software reset
+//! bit set as well).
+//!
+//! \return This function does not return.
+//
+//*****************************************************************************
+void
+SysCtlReset(void)
+{
+ //
+ // Perform a software reset request. This will cause the device to reset,
+ // no further code will be executed.
+ //
+ HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | NVIC_APINT_SYSRESETREQ;
+
+ //
+ // The device should have reset, so this should never be reached. Just in
+ // case, loop forever.
+ //
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! Puts the processor into sleep mode.
+//!
+//! This function places the processor into sleep mode; it will not return
+//! until the processor returns to run mode. The peripherals that are enabled
+//! via SysCtlPeripheralSleepEnable() continue to operate and can wake up the
+//! processor (if automatic clock gating is enabled with
+//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
+//! operate).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlSleep(void)
+{
+ //
+ // Wait for an interrupt.
+ //
+ CPUwfi();
+}
+
+//*****************************************************************************
+//
+//! Puts the processor into deep-sleep mode.
+//!
+//! This function places the processor into deep-sleep mode; it will not return
+//! until the processor returns to run mode. The peripherals that are enabled
+//! via SysCtlPeripheralDeepSleepEnable() continue to operate and can wake up
+//! the processor (if automatic clock gating is enabled with
+//! SysCtlPeripheralClockGating(), otherwise all peripherals continue to
+//! operate).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlDeepSleep(void)
+{
+ //
+ // Enable deep-sleep.
+ //
+ HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP;
+
+ //
+ // Wait for an interrupt.
+ //
+ CPUwfi();
+
+ //
+ // Disable deep-sleep so that a future sleep will work correctly.
+ //
+ HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP);
+}
+
+//*****************************************************************************
+//
+//! Gets the reason for a reset.
+//!
+//! This function will return the reason(s) for a reset. Since the reset
+//! reasons are sticky until either cleared by software or an external reset,
+//! multiple reset reasons may be returned if multiple resets have occurred.
+//! The reset reason will be a logical OR of \b SYSCTL_CAUSE_LDO,
+//! \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG, \b SYSCTL_CAUSE_BOR,
+//! \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
+//!
+//! \return Returns the reason(s) for a reset.
+//
+//*****************************************************************************
+unsigned long
+SysCtlResetCauseGet(void)
+{
+ //
+ // Return the reset reasons.
+ //
+ return(HWREG(SYSCTL_RESC));
+}
+
+//*****************************************************************************
+//
+//! Clears reset reasons.
+//!
+//! \param ulCauses are the reset causes to be cleared; must be a logical OR of
+//! \b SYSCTL_CAUSE_LDO, \b SYSCTL_CAUSE_SW, \b SYSCTL_CAUSE_WDOG,
+//! \b SYSCTL_CAUSE_BOR, \b SYSCTL_CAUSE_POR, and/or \b SYSCTL_CAUSE_EXT.
+//!
+//! This function clears the specified sticky reset reasons. Once cleared,
+//! another reset for the same reason can be detected, and a reset for a
+//! different reason can be distinguished (instead of having two reset causes
+//! set). If the reset reason is used by an application, all reset causes
+//! should be cleared after they are retrieved with SysCtlResetCauseGet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlResetCauseClear(unsigned long ulCauses)
+{
+ //
+ // Clear the given reset reasons.
+ //
+ HWREG(SYSCTL_RESC) &= ~(ulCauses);
+}
+
+//*****************************************************************************
+//
+//! Configures the brown-out control.
+//!
+//! \param ulConfig is the desired configuration of the brown-out control.
+//! Must be the logical OR of \b SYSCTL_BOR_RESET and/or
+//! \b SYSCTL_BOR_RESAMPLE.
+//! \param ulDelay is the number of internal oscillator cycles to wait before
+//! resampling an asserted brown-out signal. This value only has meaning when
+//! \b SYSCTL_BOR_RESAMPLE is set and must be less than 8192.
+//!
+//! This function configures how the brown-out control operates. It can detect
+//! a brown-out by looking at only the brown-out output, or it can wait for it
+//! to be active for two consecutive samples separated by a configurable time.
+//! When it detects a brown-out condition, it can either reset the device or
+//! generate a processor interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlBrownOutConfigSet(unsigned long ulConfig, unsigned long ulDelay)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!(ulConfig & ~(SYSCTL_BOR_RESET | SYSCTL_BOR_RESAMPLE)));
+ ASSERT(ulDelay < 8192);
+
+ //
+ // Configure the brown-out reset control.
+ //
+ HWREG(SYSCTL_PBORCTL) = (ulDelay << SYSCTL_PBORCTL_BORTIM_S) | ulConfig;
+}
+
+//*****************************************************************************
+//
+//! Provides a small delay.
+//!
+//! \param ulCount is the number of delay loop iterations to perform.
+//!
+//! This function provides a means of generating a constant length delay. It
+//! is written in assembly to keep the delay consistent across tool chains,
+//! avoiding the need to tune the delay based on the tool chain in use.
+//!
+//! The loop takes 3 cycles/loop.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#if defined(ewarm) || defined(DOXYGEN)
+void
+SysCtlDelay(unsigned long ulCount)
+{
+ __asm(" subs r0, #1\n"
+ " bne.n SysCtlDelay\n"
+ " bx lr");
+}
+#endif
+#if defined(codered) || defined(gcc) || defined(sourcerygxx)
+void __attribute__((naked))
+SysCtlDelay(unsigned long ulCount)
+{
+ __asm(" subs r0, #1\n"
+ " bne SysCtlDelay\n"
+ " bx lr");
+}
+#endif
+#if defined(rvmdk) || defined(__ARMCC_VERSION)
+__asm void
+SysCtlDelay(unsigned long ulCount)
+{
+ subs r0, #1;
+ bne SysCtlDelay;
+ bx lr;
+}
+#endif
+//
+// For CCS implement this function in pure assembly. This prevents the TI
+// compiler from doing funny things with the optimizer.
+//
+#if defined(ccs)
+ __asm(" .sect \".text:SysCtlDelay\"\n"
+ " .clink\n"
+ " .thumbfunc SysCtlDelay\n"
+ " .thumb\n"
+ " .global SysCtlDelay\n"
+ "SysCtlDelay:\n"
+ " subs r0, #1\n"
+ " bne.n SysCtlDelay\n"
+ " bx lr\n");
+#endif
+
+
+//*****************************************************************************
+//
+//! Sets the clocking of the device.
+//!
+//! \param ulConfig is the required configuration of the device clocking.
+//!
+//! This function configures the clocking of the device. The input crystal
+//! frequency, oscillator to be used, use of the PLL, and the system clock
+//! divider are all configured with this function.
+//!
+//! The \e ulConfig parameter is the logical OR of several different values,
+//! many of which are grouped into sets where only one can be chosen.
+//!
+//! The system clock divider is chosen with one of the following values:
+//! \b SYSCTL_SYSDIV_1, \b SYSCTL_SYSDIV_2, \b SYSCTL_SYSDIV_3, ...
+//! \b SYSCTL_SYSDIV_64. Only \b SYSCTL_SYSDIV_1 through \b SYSCTL_SYSDIV_16
+//! are valid on Sandstorm-class devices.
+//!
+//! The use of the PLL is chosen with either \b SYSCTL_USE_PLL or
+//! \b SYSCTL_USE_OSC.
+//!
+//! The external crystal frequency is chosen with one of the following values:
+//! \b SYSCTL_XTAL_1MHZ, \b SYSCTL_XTAL_1_84MHZ, \b SYSCTL_XTAL_2MHZ,
+//! \b SYSCTL_XTAL_2_45MHZ, \b SYSCTL_XTAL_3_57MHZ, \b SYSCTL_XTAL_3_68MHZ,
+//! \b SYSCTL_XTAL_4MHZ, \b SYSCTL_XTAL_4_09MHZ, \b SYSCTL_XTAL_4_91MHZ,
+//! \b SYSCTL_XTAL_5MHZ, \b SYSCTL_XTAL_5_12MHZ, \b SYSCTL_XTAL_6MHZ,
+//! \b SYSCTL_XTAL_6_14MHZ, \b SYSCTL_XTAL_7_37MHZ, \b SYSCTL_XTAL_8MHZ,
+//! \b SYSCTL_XTAL_8_19MHZ, \b SYSCTL_XTAL_10MHZ, \b SYSCTL_XTAL_12MHZ,
+//! \b SYSCTL_XTAL_12_2MHZ, \b SYSCTL_XTAL_13_5MHZ, \b SYSCTL_XTAL_14_3MHZ,
+//! \b SYSCTL_XTAL_16MHZ, or \b SYSCTL_XTAL_16_3MHZ. Values below
+//! \b SYSCTL_XTAL_3_57MHZ are not valid when the PLL is in operation. On
+//! Sandstorm- and Fury-class devices, values above \b SYSCTL_XTAL_8_19MHZ are
+//! not valid.
+//!
+//! The oscillator source is chosen with one of the following values:
+//! \b SYSCTL_OSC_MAIN, \b SYSCTL_OSC_INT, \b SYSCTL_OSC_INT4,
+//! \b SYSCTL_OSC_INT30, or \b SYSCTL_OSC_EXT32. On Sandstorm-class devices,
+//! \b SYSCTL_OSC_INT30 and \b SYSCTL_OSC_EXT32 are not valid.
+//! \b SYSCTL_OSC_EXT32 is only available on devices with the hibernate module,
+//! and then only when the hibernate module has been enabled.
+//!
+//! The internal and main oscillators are disabled with the
+//! \b SYSCTL_INT_OSC_DIS and \b SYSCTL_MAIN_OSC_DIS flags, respectively.
+//! The external oscillator must be enabled in order to use an external clock
+//! source. Note that attempts to disable the oscillator used to clock the
+//! device will be prevented by the hardware.
+//!
+//! To clock the system from an external source (such as an external crystal
+//! oscillator), use \b SYSCTL_USE_OSC \b | \b SYSCTL_OSC_MAIN. To clock the
+//! system from the main oscillator, use \b SYSCTL_USE_OSC \b |
+//! \b SYSCTL_OSC_MAIN. To clock the system from the PLL, use
+//! \b SYSCTL_USE_PLL \b | \b SYSCTL_OSC_MAIN, and select the appropriate
+//! crystal with one of the \b SYSCTL_XTAL_xxx values.
+//!
+//! \note If selecting the PLL as the system clock source (that is, via
+//! \b SYSCTL_USE_PLL), this function will poll the PLL lock interrupt to
+//! determine when the PLL has locked. If an interrupt handler for the
+//! system control interrupt is in place, and it responds to and clears the
+//! PLL lock interrupt, this function will delay until its timeout has occurred
+//! instead of completing as soon as PLL lock is achieved.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlClockSet(unsigned long ulConfig)
+{
+ unsigned long ulDelay, ulRCC, ulRCC2;
+
+ //
+ // See if this is a Sandstorm-class device and clocking features from newer
+ // devices were requested.
+ //
+ if(CLASS_IS_SANDSTORM && (ulConfig & SYSCTL_RCC2_USERCC2))
+ {
+ //
+ // Return without changing the clocking since the requested
+ // configuration can not be achieved.
+ //
+ return;
+ }
+
+ //
+ // Get the current value of the RCC and RCC2 registers. If using a
+ // Sandstorm-class device, the RCC2 register will read back as zero and the
+ // writes to it from within this function will be ignored.
+ //
+ ulRCC = HWREG(SYSCTL_RCC);
+ ulRCC2 = HWREG(SYSCTL_RCC2);
+
+ //
+ // Bypass the PLL and system clock dividers for now.
+ //
+ ulRCC |= SYSCTL_RCC_BYPASS;
+ ulRCC &= ~(SYSCTL_RCC_USESYSDIV);
+ ulRCC2 |= SYSCTL_RCC2_BYPASS2;
+
+ //
+ // Write the new RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ulRCC;
+ HWREG(SYSCTL_RCC2) = ulRCC2;
+
+ //
+ // See if either oscillator needs to be enabled.
+ //
+ if(((ulRCC & SYSCTL_RCC_IOSCDIS) && !(ulConfig & SYSCTL_RCC_IOSCDIS)) ||
+ ((ulRCC & SYSCTL_RCC_MOSCDIS) && !(ulConfig & SYSCTL_RCC_MOSCDIS)))
+ {
+ //
+ // Make sure that the required oscillators are enabled. For now, the
+ // previously enabled oscillators must be enabled along with the newly
+ // requested oscillators.
+ //
+ ulRCC &= (~(SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS) |
+ (ulConfig & (SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS)));
+
+ //
+ // Write the new RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ulRCC;
+
+ //
+ // Wait for a bit, giving the oscillator time to stabilize. The number
+ // of iterations is adjusted based on the current clock source; a
+ // smaller number of iterations is required for slower clock rates.
+ //
+ if(((ulRCC2 & SYSCTL_RCC2_USERCC2) &&
+ (((ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_30) ||
+ ((ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) == SYSCTL_RCC2_OSCSRC2_32))) ||
+ (!(ulRCC2 & SYSCTL_RCC2_USERCC2) &&
+ ((ulRCC & SYSCTL_RCC_OSCSRC_M) == SYSCTL_RCC_OSCSRC_30)))
+ {
+ //
+ // Delay for 4096 iterations.
+ //
+ SysCtlDelay(4096);
+ }
+ else
+ {
+ //
+ // Delay for 524,288 iterations.
+ //
+ SysCtlDelay(524288);
+ }
+ }
+
+ //
+ // Set the new crystal value, oscillator source, and PLL configuration.
+ // Since the OSCSRC2 field in RCC2 overlaps the XTAL field in RCC, the
+ // OSCSRC field has a special encoding within ulConfig to avoid the
+ // overlap.
+ //
+ ulRCC &= ~(SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M |
+ SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN);
+ ulRCC |= ulConfig & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M |
+ SYSCTL_RCC_PWRDN | SYSCTL_RCC_OEN);
+ ulRCC2 &= ~(SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_OSCSRC2_M |
+ SYSCTL_RCC2_PWRDN2);
+ ulRCC2 |= ulConfig & (SYSCTL_RCC2_USERCC2 | SYSCTL_RCC_OSCSRC_M |
+ SYSCTL_RCC2_PWRDN2);
+ ulRCC2 |= (ulConfig & 0x00000008) << 3;
+
+ //
+ // Clear the PLL lock interrupt.
+ //
+ HWREG(SYSCTL_MISC) = SYSCTL_INT_PLL_LOCK;
+
+ //
+ // Write the new RCC value.
+ //
+ if(ulRCC2 & SYSCTL_RCC2_USERCC2)
+ {
+ HWREG(SYSCTL_RCC2) = ulRCC2;
+ HWREG(SYSCTL_RCC) = ulRCC;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) = ulRCC;
+ HWREG(SYSCTL_RCC2) = ulRCC2;
+ }
+
+ //
+ // Wait for a bit so that new crystal value and oscillator source can take
+ // effect.
+ //
+ SysCtlDelay(16);
+
+ //
+ // Set the requested system divider and disable the appropriate
+ // oscillators. This will not get written immediately.
+ //
+ ulRCC &= ~(SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
+ SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
+ ulRCC |= ulConfig & (SYSCTL_RCC_SYSDIV_M | SYSCTL_RCC_USESYSDIV |
+ SYSCTL_RCC_IOSCDIS | SYSCTL_RCC_MOSCDIS);
+ ulRCC2 &= ~(SYSCTL_RCC2_SYSDIV2_M);
+ ulRCC2 |= ulConfig & SYSCTL_RCC2_SYSDIV2_M;
+ if(ulConfig & SYSCTL_RCC2_DIV400)
+ {
+ ulRCC |= SYSCTL_RCC_USESYSDIV;
+ ulRCC2 &= ~(SYSCTL_RCC_USESYSDIV);
+ ulRCC2 |= ulConfig & (SYSCTL_RCC2_DIV400 | SYSCTL_RCC2_SYSDIV2LSB);
+ }
+ else
+ {
+ ulRCC2 &= ~(SYSCTL_RCC2_DIV400);
+ }
+
+ //
+ // See if the PLL output is being used to clock the system.
+ //
+ if(!(ulConfig & SYSCTL_RCC_BYPASS))
+ {
+ //
+ // Wait until the PLL has locked.
+ //
+ for(ulDelay = 32768; ulDelay > 0; ulDelay--)
+ {
+ if(HWREG(SYSCTL_RIS) & SYSCTL_INT_PLL_LOCK)
+ {
+ break;
+ }
+ }
+
+ //
+ // Enable use of the PLL.
+ //
+ ulRCC &= ~(SYSCTL_RCC_BYPASS);
+ ulRCC2 &= ~(SYSCTL_RCC2_BYPASS2);
+ }
+
+ //
+ // Write the final RCC value.
+ //
+ HWREG(SYSCTL_RCC) = ulRCC;
+ HWREG(SYSCTL_RCC2) = ulRCC2;
+
+ //
+ // Delay for a little bit so that the system divider takes effect.
+ //
+ SysCtlDelay(16);
+}
+
+//*****************************************************************************
+//
+//! Gets the processor clock rate.
+//!
+//! This function determines the clock rate of the processor clock. This is
+//! also the clock rate of all the peripheral modules (with the exception of
+//! PWM, which has its own clock divider).
+//!
+//! \note This will not return accurate results if SysCtlClockSet() has not
+//! been called to configure the clocking of the device, or if the device is
+//! directly clocked from a crystal (or a clock source) that is not one of the
+//! supported crystal frequencies. In the later case, this function should be
+//! modified to directly return the correct system clock rate.
+//!
+//! \return The processor clock rate.
+//
+//*****************************************************************************
+unsigned long
+SysCtlClockGet(void)
+{
+ unsigned long ulRCC, ulRCC2, ulPLL, ulClk;
+
+ //
+ // Read RCC and RCC2. For Sandstorm-class devices (which do not have
+ // RCC2), the RCC2 read will return 0, which indicates that RCC2 is
+ // disabled (since the SYSCTL_RCC2_USERCC2 bit is clear).
+ //
+ ulRCC = HWREG(SYSCTL_RCC);
+ ulRCC2 = HWREG(SYSCTL_RCC2);
+
+ //
+ // Get the base clock rate.
+ //
+ switch((ulRCC2 & SYSCTL_RCC2_USERCC2) ?
+ (ulRCC2 & SYSCTL_RCC2_OSCSRC2_M) :
+ (ulRCC & SYSCTL_RCC_OSCSRC_M))
+ {
+ //
+ // The main oscillator is the clock source. Determine its rate from
+ // the crystal setting field.
+ //
+ case SYSCTL_RCC_OSCSRC_MAIN:
+ {
+ ulClk = g_pulXtals[(ulRCC & SYSCTL_RCC_XTAL_M) >>
+ SYSCTL_RCC_XTAL_S];
+ break;
+ }
+
+ //
+ // The internal oscillator is the source clock.
+ //
+ case SYSCTL_RCC_OSCSRC_INT:
+ {
+ //
+ // See if this is a Sandstorm-class or Fury-class device.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ //
+ // The internal oscillator on a Sandstorm-class device is
+ // 15 MHz +/- 50%.
+ //
+ ulClk = 15000000;
+ }
+ else if((CLASS_IS_FURY && REVISION_IS_A2) ||
+ (CLASS_IS_DUSTDEVIL && REVISION_IS_A0))
+ {
+ //
+ // The internal oscillator on a rev A2 Fury-class device and a
+ // rev A0 Dustdevil-class device is 12 MHz +/- 30%.
+ //
+ ulClk = 12000000;
+ }
+ else
+ {
+ //
+ // The internal oscillator on all other devices is 16 MHz.
+ //
+ ulClk = 16000000;
+ }
+ break;
+ }
+
+ //
+ // The internal oscillator divided by four is the source clock.
+ //
+ case SYSCTL_RCC_OSCSRC_INT4:
+ {
+ //
+ // See if this is a Sandstorm-class or Fury-class device.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ //
+ // The internal oscillator on a Sandstorm-class device is
+ // 15 MHz +/- 50%.
+ //
+ ulClk = 15000000 / 4;
+ }
+ else if((CLASS_IS_FURY && REVISION_IS_A2) ||
+ (CLASS_IS_DUSTDEVIL && REVISION_IS_A0))
+ {
+ //
+ // The internal oscillator on a rev A2 Fury-class device and a
+ // rev A0 Dustdevil-class device is 12 MHz +/- 30%.
+ //
+ ulClk = 12000000 / 4;
+ }
+ else
+ {
+ //
+ // The internal oscillator on a Tempest-class device is 16 MHz.
+ //
+ ulClk = 16000000 / 4;
+ }
+ break;
+ }
+
+ //
+ // The internal 30 KHz oscillator is the source clock.
+ //
+ case SYSCTL_RCC_OSCSRC_30:
+ {
+ //
+ // The internal 30 KHz oscillator has an accuracy of +/- 30%.
+ //
+ ulClk = 30000;
+ break;
+ }
+
+ //
+ // The 4.19 MHz clock from the hibernate module is the clock source.
+ //
+ case SYSCTL_RCC2_OSCSRC2_419:
+ {
+ ulClk = 4194304;
+ break;
+ }
+
+ //
+ // The 32 KHz clock from the hibernate module is the source clock.
+ //
+ case SYSCTL_RCC2_OSCSRC2_32:
+ {
+ ulClk = 32768;
+ break;
+ }
+
+ //
+ // An unknown setting, so return a zero clock (that is, an unknown
+ // clock rate).
+ //
+ default:
+ {
+ return(0);
+ }
+ }
+
+ //
+ // See if the PLL is being used.
+ //
+ if(((ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) ||
+ (!(ulRCC2 & SYSCTL_RCC2_USERCC2) && !(ulRCC & SYSCTL_RCC_BYPASS)))
+ {
+ //
+ // Get the PLL configuration.
+ //
+ ulPLL = HWREG(SYSCTL_PLLCFG);
+
+ //
+ // See if this is a Sandstorm-class or Fury-class device.
+ //
+ if(CLASS_IS_SANDSTORM)
+ {
+ //
+ // Compute the PLL output frequency based on its input frequency.
+ // The formula for a Sandstorm-class devices is
+ // "(xtal * (f + 2)) / (r + 2)".
+ //
+ ulClk = ((ulClk * (((ulPLL & SYSCTL_PLLCFG_F_M) >>
+ SYSCTL_PLLCFG_F_S) + 2)) /
+ (((ulPLL & SYSCTL_PLLCFG_R_M) >>
+ SYSCTL_PLLCFG_R_S) + 2));
+ }
+ else
+ {
+ //
+ // Compute the PLL output frequency based on its input frequency.
+ // The formula for a Fury-class device is
+ // "(xtal * f) / ((r + 1) * 2)".
+ //
+ ulClk = ((ulClk * ((ulPLL & SYSCTL_PLLCFG_F_M) >>
+ SYSCTL_PLLCFG_F_S)) /
+ ((((ulPLL & SYSCTL_PLLCFG_R_M) >>
+ SYSCTL_PLLCFG_R_S) + 1) * 2));
+ }
+
+ //
+ // See if the optional output divide by 2 is being used.
+ //
+ if(ulPLL & SYSCTL_PLLCFG_OD_2)
+ {
+ ulClk /= 2;
+ }
+
+ //
+ // See if the optional output divide by 4 is being used.
+ //
+ if(ulPLL & SYSCTL_PLLCFG_OD_4)
+ {
+ ulClk /= 4;
+ }
+
+ //
+ // Force the system divider to be enabled. It is always used when
+ // using the PLL, but in some cases it will not read as being enabled.
+ //
+ ulRCC |= SYSCTL_RCC_USESYSDIV;
+ }
+
+ //
+ // See if the system divider is being used.
+ //
+ if(ulRCC & SYSCTL_RCC_USESYSDIV)
+ {
+ //
+ // Adjust the clock rate by the system clock divider.
+ //
+ if(ulRCC2 & SYSCTL_RCC2_USERCC2)
+ {
+ if((ulRCC2 & SYSCTL_RCC2_DIV400) &&
+ (((ulRCC2 & SYSCTL_RCC2_USERCC2) &&
+ !(ulRCC2 & SYSCTL_RCC2_BYPASS2)) ||
+ (!(ulRCC2 & SYSCTL_RCC2_USERCC2) &&
+ !(ulRCC & SYSCTL_RCC_BYPASS))))
+
+ {
+ ulClk = ((ulClk * 2) / (((ulRCC2 & (SYSCTL_RCC2_SYSDIV2_M |
+ SYSCTL_RCC2_SYSDIV2LSB)) >>
+ (SYSCTL_RCC2_SYSDIV2_S - 1)) + 1));
+ }
+ else
+ {
+ ulClk /= (((ulRCC2 & SYSCTL_RCC2_SYSDIV2_M) >>
+ SYSCTL_RCC2_SYSDIV2_S) + 1);
+ }
+ }
+ else
+ {
+ ulClk /= (((ulRCC & SYSCTL_RCC_SYSDIV_M) >> SYSCTL_RCC_SYSDIV_S) +
+ 1);
+ }
+ }
+
+ //
+ // Return the computed clock rate.
+ //
+ return(ulClk);
+}
+
+//*****************************************************************************
+//
+//! Sets the PWM clock configuration.
+//!
+//! \param ulConfig is the configuration for the PWM clock; it must be one of
+//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
+//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
+//! \b SYSCTL_PWMDIV_64.
+//!
+//! This function sets the rate of the clock provided to the PWM module as a
+//! ratio of the processor clock. This clock is used by the PWM module to
+//! generate PWM signals; its rate forms the basis for all PWM signals.
+//!
+//! \note The clocking of the PWM is dependent upon the system clock rate as
+//! configured by SysCtlClockSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPWMClockSet(unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulConfig == SYSCTL_PWMDIV_1) ||
+ (ulConfig == SYSCTL_PWMDIV_2) ||
+ (ulConfig == SYSCTL_PWMDIV_4) ||
+ (ulConfig == SYSCTL_PWMDIV_8) ||
+ (ulConfig == SYSCTL_PWMDIV_16) ||
+ (ulConfig == SYSCTL_PWMDIV_32) ||
+ (ulConfig == SYSCTL_PWMDIV_64));
+
+ //
+ // Check that there is a PWM block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM);
+
+ //
+ // Set the PWM clock configuration into the run-mode clock configuration
+ // register.
+ //
+ HWREG(SYSCTL_RCC) = ((HWREG(SYSCTL_RCC) &
+ ~(SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M)) |
+ ulConfig);
+}
+
+//*****************************************************************************
+//
+//! Gets the current PWM clock configuration.
+//!
+//! This function returns the current PWM clock configuration.
+//!
+//! \return Returns the current PWM clock configuration; will be one of
+//! \b SYSCTL_PWMDIV_1, \b SYSCTL_PWMDIV_2, \b SYSCTL_PWMDIV_4,
+//! \b SYSCTL_PWMDIV_8, \b SYSCTL_PWMDIV_16, \b SYSCTL_PWMDIV_32, or
+//! \b SYSCTL_PWMDIV_64.
+//
+//*****************************************************************************
+unsigned long
+SysCtlPWMClockGet(void)
+{
+ //
+ // Check that there is a PWM block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_PWM);
+
+ //
+ // Return the current PWM clock configuration. Make sure that
+ // SYSCTL_PWMDIV_1 is returned in all cases where the divider is disabled.
+ //
+ if(!(HWREG(SYSCTL_RCC) & SYSCTL_RCC_USEPWMDIV))
+ {
+ //
+ // The divider is not active so reflect this in the value we return.
+ //
+ return(SYSCTL_PWMDIV_1);
+ }
+ else
+ {
+ //
+ // The divider is active so directly return the masked register value.
+ //
+ return(HWREG(SYSCTL_RCC) &
+ (SYSCTL_RCC_USEPWMDIV | SYSCTL_RCC_PWMDIV_M));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the sample rate of the ADC.
+//!
+//! \param ulSpeed is the desired sample rate of the ADC; must be one of
+//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,
+//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.
+//!
+//! This function sets the rate at which the ADC samples are captured by the
+//! ADC block. The sampling speed may be limited by the hardware, so the
+//! sample rate may end up being slower than requested. SysCtlADCSpeedGet()
+//! will return the actual speed in use.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlADCSpeedSet(unsigned long ulSpeed)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulSpeed == SYSCTL_ADCSPEED_1MSPS) ||
+ (ulSpeed == SYSCTL_ADCSPEED_500KSPS) ||
+ (ulSpeed == SYSCTL_ADCSPEED_250KSPS) ||
+ (ulSpeed == SYSCTL_ADCSPEED_125KSPS));
+
+ //
+ // Check that there is an ADC block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC0);
+
+ //
+ // Set the ADC speed in run, sleep, and deep-sleep mode.
+ //
+ HWREG(SYSCTL_RCGC0) = ((HWREG(SYSCTL_RCGC0) & ~(SYSCTL_RCGC0_ADCSPD_M)) |
+ ulSpeed);
+ HWREG(SYSCTL_SCGC0) = ((HWREG(SYSCTL_SCGC0) & ~(SYSCTL_SCGC0_ADCSPD_M)) |
+ ulSpeed);
+}
+
+//*****************************************************************************
+//
+//! Gets the sample rate of the ADC.
+//!
+//! This function gets the current sample rate of the ADC.
+//!
+//! \return Returns the current ADC sample rate; will be one of
+//! \b SYSCTL_ADCSPEED_1MSPS, \b SYSCTL_ADCSPEED_500KSPS,
+//! \b SYSCTL_ADCSPEED_250KSPS, or \b SYSCTL_ADCSPEED_125KSPS.
+//
+//*****************************************************************************
+unsigned long
+SysCtlADCSpeedGet(void)
+{
+ //
+ // Check that there is an ADC block on this part.
+ //
+ ASSERT(HWREG(SYSCTL_DC1) & SYSCTL_DC1_ADC0);
+
+ //
+ // Return the current ADC speed.
+ //
+ return(HWREG(SYSCTL_RCGC0) & SYSCTL_RCGC0_ADCSPD_M);
+}
+
+//*****************************************************************************
+//
+//! Configures the internal oscillator verification timer.
+//!
+//! \param bEnable is a boolean that is \b true if the internal oscillator
+//! verification timer should be enabled.
+//!
+//! This function allows the internal oscillator verification timer to be
+//! enabled or disabled. When enabled, an interrupt will be generated if the
+//! internal oscillator ceases to operate.
+//!
+//! The internal oscillator verification timer is only available on
+//! Sandstorm-class devices.
+//!
+//! \note Both oscillators (main and internal) must be enabled for this
+//! verification timer to operate as the main oscillator will verify the
+//! internal oscillator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlIOSCVerificationSet(tBoolean bEnable)
+{
+ //
+ // Enable or disable the internal oscillator verification timer as
+ // requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_IOSCVER;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_IOSCVER);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the main oscillator verification timer.
+//!
+//! \param bEnable is a boolean that is \b true if the main oscillator
+//! verification timer should be enabled.
+//!
+//! This function allows the main oscillator verification timer to be enabled
+//! or disabled. When enabled, an interrupt will be generated if the main
+//! oscillator ceases to operate.
+//!
+//! The main oscillator verification timer is only available on
+//! Sandstorm-class devices.
+//!
+//! \note Both oscillators (main and internal) must be enabled for this
+//! verification timer to operate as the internal oscillator will verify the
+//! main oscillator.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlMOSCVerificationSet(tBoolean bEnable)
+{
+ //
+ // Enable or disable the main oscillator verification timer as requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_MOSCVER;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_MOSCVER);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configures the PLL verification timer.
+//!
+//! \param bEnable is a boolean that is \b true if the PLL verification timer
+//! should be enabled.
+//!
+//! This function allows the PLL verification timer to be enabled or disabled.
+//! When enabled, an interrupt will be generated if the PLL ceases to operate.
+//!
+//! The PLL verification timer is only available on Sandstorm-class devices.
+//!
+//! \note The main oscillator must be enabled for this verification timer to
+//! operate as it is used to check the PLL. Also, the verification timer
+//! should be disabled while the PLL is being reconfigured via
+//! SysCtlClockSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlPLLVerificationSet(tBoolean bEnable)
+{
+ //
+ // Enable or disable the PLL verification timer as requested.
+ //
+ if(bEnable)
+ {
+ HWREG(SYSCTL_RCC) |= SYSCTL_RCC_PLLVER;
+ }
+ else
+ {
+ HWREG(SYSCTL_RCC) &= ~(SYSCTL_RCC_PLLVER);
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the clock verification status.
+//!
+//! This function clears the status of the clock verification timers, allowing
+//! them to assert another failure if detected.
+//!
+//! The clock verification timers are only available on Sandstorm-class
+//! devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlClkVerificationClear(void)
+{
+ //
+ // Clear the clock verification.
+ //
+ HWREG(SYSCTL_CLKVCLR) = SYSCTL_CLKVCLR_VERCLR;
+
+ //
+ // The bit does not self-reset, so clear it.
+ //
+ HWREG(SYSCTL_CLKVCLR) = 0;
+}
+
+//*****************************************************************************
+//
+//! Enables a GPIO peripheral for access from the AHB.
+//!
+//! \param ulGPIOPeripheral is the GPIO peripheral to enable.
+//!
+//! This function is used to enable the specified GPIO peripheral to be
+//! accessed from the Advanced Host Bus (AHB) instead of the legacy Advanced
+//! Peripheral Bus (APB). When a GPIO peripheral is enabled for AHB access,
+//! the \b _AHB_BASE form of the base address should be used for GPIO
+//! functions. For example, instead of using \b GPIO_PORTA_BASE as the base
+//! address for GPIO functions, use \b GPIO_PORTA_AHB_BASE instead.
+//!
+//! The \e ulGPIOPeripheral argument must be only one of the following values:
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulGPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
+
+ //
+ // Enable this GPIO for AHB access.
+ //
+ HWREG(SYSCTL_GPIOHBCTL) |= ulGPIOPeripheral & 0xFFFF;
+}
+
+//*****************************************************************************
+//
+//! Disables a GPIO peripheral for access from the AHB.
+//!
+//! \param ulGPIOPeripheral is the GPIO peripheral to disable.
+//!
+//! This function disables the specified GPIO peripheral for access from the
+//! Advanced Host Bus (AHB). Once disabled, the GPIO peripheral is accessed
+//! from the legacy Advanced Peripheral Bus (AHB).
+//!
+//! The \b ulGPIOPeripheral argument must be only one of the following values:
+//! \b SYSCTL_PERIPH_GPIOA, \b SYSCTL_PERIPH_GPIOB, \b SYSCTL_PERIPH_GPIOC,
+//! \b SYSCTL_PERIPH_GPIOD, \b SYSCTL_PERIPH_GPIOE, \b SYSCTL_PERIPH_GPIOF,
+//! \b SYSCTL_PERIPH_GPIOG, or \b SYSCTL_PERIPH_GPIOH.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulGPIOPeripheral == SYSCTL_PERIPH_GPIOA) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOB) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOC) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOD) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOE) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOF) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOG) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOH) ||
+ (ulGPIOPeripheral == SYSCTL_PERIPH_GPIOJ));
+
+ //
+ // Disable this GPIO for AHB access.
+ //
+ HWREG(SYSCTL_GPIOHBCTL) &= ~(ulGPIOPeripheral & 0xFFFF);
+}
+
+//*****************************************************************************
+//
+//! Powers up the USB PLL.
+//!
+//! This function will enable the USB controller's PLL which is used by it's
+//! physical layer. This call is necessary before connecting to any external
+//! devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlUSBPLLEnable(void)
+{
+ //
+ // Turn on the USB PLL.
+ //
+ HWREG(SYSCTL_RCC2) &= ~SYSCTL_RCC2_USBPWRDN;
+}
+
+//*****************************************************************************
+//
+//! Powers down the USB PLL.
+//!
+//! This function will disable the USB controller's PLL which is used by it's
+//! physical layer. The USB registers are still accessible, but the physical
+//! layer will no longer function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysCtlUSBPLLDisable(void)
+{
+ //
+ // Turn of USB PLL.
+ //
+ HWREG(SYSCTL_RCC2) |= SYSCTL_RCC2_USBPWRDN;
+}
+
+//*****************************************************************************
+//
+//! Sets the MCLK frequency provided to the I2S module.
+//!
+//! \param ulInputClock is the input clock to the MCLK divider. If this is
+//! zero, the value is computed from the current PLL configuration.
+//! \param ulMClk is the desired MCLK frequency. If this is zero, MCLK output
+//! is disabled.
+//!
+//! This function sets the dividers to provide MCLK to the I2S module. A MCLK
+//! divider will be chosen that produces the MCLK frequency that is the closest
+//! possible to the requested frequency, which may be above or below the
+//! requested frequency.
+//!
+//! The actual MCLK frequency will be returned. It is the responsibility of
+//! the application to determine if the selected MCLK is acceptable; in general
+//! the human ear can not discern the frequency difference if it is within 0.3%
+//! of the desired frequency (though there is a very small percentage of the
+//! population that can discern lower frequency deviations).
+//!
+//! \return Returns the actual MCLK frequency.
+//
+//*****************************************************************************
+unsigned long
+SysCtlI2SMClkSet(unsigned long ulInputClock, unsigned long ulMClk)
+{
+ unsigned long ulDivInt, ulDivFrac, ulPLL;
+
+ //
+ // See if the I2S MCLK should be disabled.
+ //
+ if(ulMClk == 0)
+ {
+ //
+ // Disable the I2S MCLK and return.
+ //
+ HWREG(SYSCTL_I2SMCLKCFG) = 0;
+ return(0);
+ }
+
+ //
+ // See if the input clock was specified.
+ //
+ if(ulInputClock == 0)
+ {
+ //
+ // The input clock was not specified, so compute the output frequency
+ // of the PLL. Get the current PLL configuration.
+ //
+ ulPLL = HWREG(SYSCTL_PLLCFG);
+
+ //
+ // Get the frequency of the crystal in use.
+ //
+ ulInputClock = g_pulXtals[(HWREG(SYSCTL_RCC) & SYSCTL_RCC_XTAL_M) >>
+ SYSCTL_RCC_XTAL_S];
+
+ //
+ // Calculate the PLL output frequency.
+ //
+ ulInputClock = ((ulInputClock * ((ulPLL & SYSCTL_PLLCFG_F_M) >>
+ SYSCTL_PLLCFG_F_S)) /
+ ((((ulPLL & SYSCTL_PLLCFG_R_M) >>
+ SYSCTL_PLLCFG_R_S) + 1)));
+
+ //
+ // See if the optional output divide by 2 is being used.
+ //
+ if(ulPLL & SYSCTL_PLLCFG_OD_2)
+ {
+ ulInputClock /= 2;
+ }
+
+ //
+ // See if the optional output divide by 4 is being used.
+ //
+ if(ulPLL & SYSCTL_PLLCFG_OD_4)
+ {
+ ulInputClock /= 4;
+ }
+ }
+
+ //
+ // Verify that the requested MCLK frequency is attainable.
+ //
+ ASSERT(ulMClk < ulInputClock);
+
+ //
+ // Add a rounding factor to the input clock, so that the MCLK frequency
+ // that is closest to the desire value is selected.
+ //
+ ulInputClock += (ulMClk / 32) - 1;
+
+ //
+ // Compute the integer portion of the MCLK divider.
+ //
+ ulDivInt = ulInputClock / ulMClk;
+
+ //
+ // If the divisor is too large, then simply use the maximum divisor.
+ //
+ if(CLASS_IS_TEMPEST && REVISION_IS_B1 && (ulDivInt > 255))
+ {
+ ulDivInt = 255;
+ ulDivFrac = 15;
+ }
+ else if(ulDivInt > 1023)
+ {
+ ulDivInt = 1023;
+ ulDivFrac = 15;
+ }
+ else
+ {
+ //
+ // Compute the fractional portion of the MCLK divider.
+ //
+ ulDivFrac = ((ulInputClock - (ulDivInt * ulMClk)) * 16) / ulMClk;
+ }
+
+ //
+ // Set the divisor for the Tx and Rx MCLK generators and enable the clocks.
+ //
+ HWREG(SYSCTL_I2SMCLKCFG) = (SYSCTL_I2SMCLKCFG_RXEN |
+ (ulDivInt << SYSCTL_I2SMCLKCFG_RXI_S) |
+ (ulDivFrac << SYSCTL_I2SMCLKCFG_RXF_S) |
+ SYSCTL_I2SMCLKCFG_TXEN |
+ (ulDivInt << SYSCTL_I2SMCLKCFG_TXI_S) |
+ (ulDivFrac << SYSCTL_I2SMCLKCFG_TXF_S));
+
+ //
+ // Return the actual MCLK frequency.
+ //
+ ulInputClock -= (ulMClk / 32) - 1;
+ ulDivInt = (ulDivInt * 16) + ulDivFrac;
+ ulMClk = (ulInputClock / ulDivInt) * 16;
+ ulMClk += ((ulInputClock - ((ulMClk / 16) * ulDivInt)) * 16) / ulDivInt;
+ return(ulMClk);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/sysctl.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/sysctl.h
new file mode 100644
index 00000000..d5b00681
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/sysctl.h
@@ -0,0 +1,466 @@
+//*****************************************************************************
+//
+// sysctl.h - Prototypes for the system control driver.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __SYSCTL_H__
+#define __SYSCTL_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
+// ulPeripheral parameter. The peripherals in the fourth group (upper nibble
+// is 3) can only be used with the SysCtlPeripheralPresent() API.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog
+#endif
+#define SYSCTL_PERIPH_WDOG0 0x00000008 // Watchdog 0
+#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_ADC 0x00100001 // ADC
+#endif
+#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
+#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
+#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
+#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
+#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
+#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
+#define SYSCTL_PERIPH_WDOG1 0x00101000 // Watchdog 1
+#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0
+#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1
+#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_SSI 0x10000010 // SSI
+#endif
+#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0
+#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_QEI 0x10000100 // QEI
+#endif
+#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0
+#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1
+#ifndef DEPRECATED
+#define SYSCTL_PERIPH_I2C 0x10001000 // I2C
+#endif
+#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0
+#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1
+#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0
+#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1
+#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2
+#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3
+#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0
+#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1
+#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2
+#define SYSCTL_PERIPH_I2S0 0x10101000 // I2S0
+#define SYSCTL_PERIPH_EPI0 0x10104000 // EPI0
+#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A
+#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B
+#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C
+#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D
+#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E
+#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F
+#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G
+#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H
+#define SYSCTL_PERIPH_GPIOJ 0x20000100 // GPIO J
+#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA
+#define SYSCTL_PERIPH_USB0 0x20100001 // USB0
+#define SYSCTL_PERIPH_ETH 0x20105000 // ETH
+#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588
+#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
+#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
+#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPinPresent() API
+// as the ulPin parameter.
+//
+//*****************************************************************************
+#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin
+#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin
+#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin
+#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin
+#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin
+#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin
+#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin
+#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin
+#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin
+#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin
+#define SYSCTL_PIN_C0O 0x00000100 // C0o pin
+#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin
+#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin
+#define SYSCTL_PIN_C1O 0x00000800 // C1o pin
+#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin
+#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin
+#define SYSCTL_PIN_C2O 0x00004000 // C2o pin
+#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin
+#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin
+#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin
+#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin
+#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin
+#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin
+#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin
+#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin
+#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin
+#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin
+#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin
+#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin
+#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin
+#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin
+#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin
+#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlLDOSet() API as
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.
+//
+//*****************************************************************************
+#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V
+#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V
+#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V
+#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V
+#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V
+#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V
+#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V
+#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V
+#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V
+#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V
+#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.
+//
+//*****************************************************************************
+#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset
+#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlIntEnable(),
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask
+// by the SysCtlIntStatus() API.
+//
+//*****************************************************************************
+#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt
+#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlResetCauseClear()
+// API or returned by the SysCtlResetCauseGet() API.
+//
+//*****************************************************************************
+#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
+#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
+#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
+#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
+#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset
+#define SYSCTL_CAUSE_EXT 0x00000001 // External reset
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()
+// API as the ulConfig parameter.
+//
+//*****************************************************************************
+#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting
+#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlPWMClockSet() API
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()
+// API.
+//
+//*****************************************************************************
+#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1
+#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2
+#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4
+#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8
+#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16
+#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32
+#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlADCSpeedSet() API
+// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet()
+// API.
+//
+//*****************************************************************************
+#define SYSCTL_ADCSPEED_1MSPS 0x00000F00 // 1,000,000 samples per second
+#define SYSCTL_ADCSPEED_500KSPS 0x00000A00 // 500,000 samples per second
+#define SYSCTL_ADCSPEED_250KSPS 0x00000500 // 250,000 samples per second
+#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlClockSet() API as
+// the ulConfig parameter.
+//
+//*****************************************************************************
+#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1
+#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2
+#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3
+#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4
+#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5
+#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6
+#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7
+#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8
+#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9
+#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10
+#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11
+#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12
+#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13
+#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14
+#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15
+#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16
+#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17
+#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18
+#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19
+#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20
+#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21
+#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22
+#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23
+#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24
+#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25
+#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26
+#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27
+#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28
+#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29
+#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30
+#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31
+#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32
+#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33
+#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34
+#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35
+#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36
+#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37
+#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38
+#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39
+#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40
+#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41
+#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42
+#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43
+#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44
+#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45
+#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46
+#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47
+#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48
+#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49
+#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50
+#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51
+#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52
+#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53
+#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54
+#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55
+#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56
+#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57
+#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58
+#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59
+#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60
+#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61
+#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62
+#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63
+#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64
+#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5
+#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5
+#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5
+#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5
+#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5
+#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5
+#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5
+#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5
+#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5
+#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5
+#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5
+#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5
+#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5
+#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5
+#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5
+#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5
+#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5
+#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5
+#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5
+#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5
+#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5
+#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5
+#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5
+#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5
+#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5
+#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5
+#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5
+#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5
+#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5
+#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5
+#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5
+#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5
+#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5
+#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5
+#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5
+#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5
+#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5
+#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5
+#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5
+#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5
+#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5
+#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5
+#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5
+#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5
+#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5
+#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5
+#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5
+#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5
+#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5
+#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5
+#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5
+#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5
+#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5
+#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5
+#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5
+#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5
+#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5
+#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5
+#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5
+#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5
+#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5
+#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5
+#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock
+#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock
+#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz
+#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz
+#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz
+#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz
+#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz
+#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz
+#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz
+#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz
+#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz
+#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz
+#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz
+#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz
+#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz
+#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz
+#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz
+#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz
+#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz
+#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz
+#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz
+#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz
+#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
+#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
+#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
+#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
+#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
+#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
+#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
+#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
+#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
+#define SYSCTL_INT_PIOSC_DIS 0x00000004 // Disable interal precision osc.
+#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
+#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern unsigned long SysCtlSRAMSizeGet(void);
+extern unsigned long SysCtlFlashSizeGet(void);
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);
+extern void SysCtlIntRegister(void (*pfnHandler)(void));
+extern void SysCtlIntUnregister(void);
+extern void SysCtlIntEnable(unsigned long ulInts);
+extern void SysCtlIntDisable(unsigned long ulInts);
+extern void SysCtlIntClear(unsigned long ulInts);
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);
+extern void SysCtlLDOSet(unsigned long ulVoltage);
+extern unsigned long SysCtlLDOGet(void);
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);
+extern void SysCtlReset(void);
+extern void SysCtlSleep(void);
+extern void SysCtlDeepSleep(void);
+extern unsigned long SysCtlResetCauseGet(void);
+extern void SysCtlResetCauseClear(unsigned long ulCauses);
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
+ unsigned long ulDelay);
+extern void SysCtlDelay(unsigned long ulCount);
+extern void SysCtlClockSet(unsigned long ulConfig);
+extern unsigned long SysCtlClockGet(void);
+extern void SysCtlPWMClockSet(unsigned long ulConfig);
+extern unsigned long SysCtlPWMClockGet(void);
+extern void SysCtlADCSpeedSet(unsigned long ulSpeed);
+extern unsigned long SysCtlADCSpeedGet(void);
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);
+extern void SysCtlClkVerificationClear(void);
+extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);
+extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral);
+extern void SysCtlUSBPLLEnable(void);
+extern void SysCtlUSBPLLDisable(void);
+extern unsigned long SysCtlI2SMClkSet(unsigned long ulInputClock,
+ unsigned long ulMClk);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSCTL_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/systick.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/systick.c
new file mode 100644
index 00000000..f19f19e7
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/systick.c
@@ -0,0 +1,259 @@
+//*****************************************************************************
+//
+// systick.c - Driver for the SysTick timer in NVIC.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup systick_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/systick.h"
+
+//*****************************************************************************
+//
+//! Enables the SysTick counter.
+//!
+//! This will start the SysTick counter. If an interrupt handler has been
+//! registered, it will be called when the SysTick counter rolls over.
+//!
+//! \note Calling this function will cause the SysTick counter to (re)commence
+//! counting from its current value. The counter is not automatically reloaded
+//! with the period as specified in a previous call to SysTickPeriodSet(). If
+//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
+//! written to force this. Any write to this register clears the SysTick
+//! counter to 0 and will cause a reload with the supplied period on the next
+//! clock.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickEnable(void)
+{
+ //
+ // Enable SysTick.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick counter.
+//!
+//! This will stop the SysTick counter. If an interrupt handler has been
+//! registered, it will no longer be called until SysTick is restarted.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickDisable(void)
+{
+ //
+ // Disable SysTick.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the SysTick interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! SysTick interrupt occurs.
+//!
+//! This sets the handler to be called when a SysTick interrupt occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(FAULT_SYSTICK, pfnHandler);
+
+ //
+ // Enable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the SysTick interrupt.
+//!
+//! This function will clear the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntUnregister(void)
+{
+ //
+ // Disable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(FAULT_SYSTICK);
+}
+
+//*****************************************************************************
+//
+//! Enables the SysTick interrupt.
+//!
+//! This function will enable the SysTick interrupt, allowing it to be
+//! reflected to the processor.
+//!
+//! \note The SysTick interrupt handler does not need to clear the SysTick
+//! interrupt source as this is done automatically by NVIC when the interrupt
+//! handler is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntEnable(void)
+{
+ //
+ // Enable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick interrupt.
+//!
+//! This function will disable the SysTick interrupt, preventing it from being
+//! reflected to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntDisable(void)
+{
+ //
+ // Disable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+}
+
+//*****************************************************************************
+//
+//! Sets the period of the SysTick counter.
+//!
+//! \param ulPeriod is the number of clock ticks in each period of the SysTick
+//! counter; must be between 1 and 16,777,216, inclusive.
+//!
+//! This function sets the rate at which the SysTick counter wraps; this
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \note Calling this function does not cause the SysTick counter to reload
+//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
+//! register must be written. Any write to this register clears the SysTick
+//! counter to 0 and will cause a reload with the \e ulPeriod supplied here on
+//! the next clock after the SysTick is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickPeriodSet(unsigned long ulPeriod)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));
+
+ //
+ // Set the period of the SysTick counter.
+ //
+ HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;
+}
+
+//*****************************************************************************
+//
+//! Gets the period of the SysTick counter.
+//!
+//! This function returns the rate at which the SysTick counter wraps; this
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \return Returns the period of the SysTick counter.
+//
+//*****************************************************************************
+unsigned long
+SysTickPeriodGet(void)
+{
+ //
+ // Return the period of the SysTick counter.
+ //
+ return(HWREG(NVIC_ST_RELOAD) + 1);
+}
+
+//*****************************************************************************
+//
+//! Gets the current value of the SysTick counter.
+//!
+//! This function returns the current value of the SysTick counter; this will
+//! be a value between the period - 1 and zero, inclusive.
+//!
+//! \return Returns the current value of the SysTick counter.
+//
+//*****************************************************************************
+unsigned long
+SysTickValueGet(void)
+{
+ //
+ // Return the current value of the SysTick counter.
+ //
+ return(HWREG(NVIC_ST_CURRENT));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/systick.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/systick.h
new file mode 100644
index 00000000..31a7e5d1
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/systick.h
@@ -0,0 +1,63 @@
+//*****************************************************************************
+//
+// systick.h - Prototypes for the SysTick driver.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __SYSTICK_H__
+#define __SYSTICK_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SysTickEnable(void);
+extern void SysTickDisable(void);
+extern void SysTickIntRegister(void (*pfnHandler)(void));
+extern void SysTickIntUnregister(void);
+extern void SysTickIntEnable(void);
+extern void SysTickIntDisable(void);
+extern void SysTickPeriodSet(unsigned long ulPeriod);
+extern unsigned long SysTickPeriodGet(void);
+extern unsigned long SysTickValueGet(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSTICK_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/timer.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/timer.c
new file mode 100644
index 00000000..9fd98c8a
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/timer.c
@@ -0,0 +1,1161 @@
+//*****************************************************************************
+//
+// timer.c - Driver for the timer module.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup timer_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_timer.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/timer.h"
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a timer base address.
+//!
+//! \param ulBase is the base address of the timer module.
+//!
+//! This function determines if a timer module base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+TimerBaseValid(unsigned long ulBase)
+{
+ return((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) ||
+ (ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Enables the timer(s).
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This will enable operation of the timer module. The timer must be
+//! configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerEnable(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Enable the timer(s) module.
+ //
+ HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN);
+}
+
+//*****************************************************************************
+//
+//! Disables the timer(s).
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to disable; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This will disable operation of the timer module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerDisable(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Disable the timer module.
+ //
+ HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer &
+ (TIMER_CTL_TAEN | TIMER_CTL_TBEN));
+}
+
+//*****************************************************************************
+//
+//! Configures the timer(s).
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulConfig is the configuration for the timer.
+//!
+//! This function configures the operating mode of the timer(s). The timer
+//! module is disabled before being configured, and is left in the disabled
+//! state. The configuration is specified in \e ulConfig as one of the
+//! following values:
+//!
+//! - \b TIMER_CFG_32_BIT_OS - 32-bit one-shot timer
+//! - \b TIMER_CFG_32_BIT_OS_UP - 32-bit one-shot timer that counts up instead
+//! of down (not available on all parts)
+//! - \b TIMER_CFG_32_BIT_PER - 32-bit periodic timer
+//! - \b TIMER_CFG_32_BIT_PER_UP - 32-bit periodic timer that counts up instead
+//! of down (not available on all parts)
+//! - \b TIMER_CFG_32_RTC - 32-bit real time clock timer
+//! - \b TIMER_CFG_16_BIT_PAIR - Two 16-bit timers
+//!
+//! When configured for a pair of 16-bit timers, each timer is separately
+//! configured. The first timer is configured by setting \e ulConfig to
+//! the result of a logical OR operation between one of the following values
+//! and \e ulConfig:
+//!
+//! - \b TIMER_CFG_A_ONE_SHOT - 16-bit one-shot timer
+//! - \b TIMER_CFG_A_ONE_SHOT_UP - 16-bit one-shot timer that counts up instead
+//! of down (not available on all parts)
+//! - \b TIMER_CFG_A_PERIODIC - 16-bit periodic timer
+//! - \b TIMER_CFG_A_PERIODIC_UP - 16-bit periodic timer that counts up instead
+//! of down (not available on all parts)
+//! - \b TIMER_CFG_A_CAP_COUNT - 16-bit edge count capture
+//! - \b TIMER_CFG_A_CAP_TIME - 16-bit edge time capture
+//! - \b TIMER_CFG_A_PWM - 16-bit PWM output
+//!
+//! Similarly, the second timer is configured by setting \e ulConfig to
+//! the result of a logical OR operation between one of the corresponding
+//! \b TIMER_CFG_B_* values and \e ulConfig.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulConfig == TIMER_CFG_32_BIT_OS) ||
+ (ulConfig == TIMER_CFG_32_BIT_OS_UP) ||
+ (ulConfig == TIMER_CFG_32_BIT_PER) ||
+ (ulConfig == TIMER_CFG_32_BIT_PER_UP) ||
+ (ulConfig == TIMER_CFG_32_RTC) ||
+ ((ulConfig & 0xff000000) == TIMER_CFG_16_BIT_PAIR));
+ ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_16_BIT_PAIR) ||
+ ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) &&
+ (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))));
+
+ //
+ // Disable the timers.
+ //
+ HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN);
+
+ //
+ // Set the global timer configuration.
+ //
+ HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24;
+
+ //
+ // Set the configuration of the A and B timers. Note that the B timer
+ // configuration is ignored by the hardware in 32-bit modes.
+ //
+ HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255;
+ HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255;
+}
+
+//*****************************************************************************
+//
+//! Controls the output level.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param bInvert specifies the output level.
+//!
+//! This function sets the PWM output level for the specified timer. If the
+//! \e bInvert parameter is \b true, then the timer's output will be made
+//! active low; otherwise, it will be made active high.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bInvert)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the output levels as requested.
+ //
+ ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML;
+ HWREG(ulBase + TIMER_O_CTL) = (bInvert ?
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
+}
+
+//*****************************************************************************
+//
+//! Enables or disables the trigger output.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param bEnable specifies the desired trigger state.
+//!
+//! This function controls the trigger output for the specified timer. If the
+//! \e bEnable parameter is \b true, then the timer's output trigger is
+//! enabled; otherwise it is disabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bEnable)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the trigger output as requested.
+ //
+ ulTimer &= TIMER_CTL_TAOTE | TIMER_CTL_TBOTE;
+ HWREG(ulBase + TIMER_O_CTL) = (bEnable ?
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
+}
+
+//*****************************************************************************
+//
+//! Controls the event type.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param ulEvent specifies the type of event; must be one of
+//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or
+//! \b TIMER_EVENT_BOTH_EDGES.
+//!
+//! This function sets the signal edge(s) that will trigger the timer when in
+//! capture mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulEvent)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the event type.
+ //
+ ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M);
+ HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) &
+ ~(TIMER_CTL_TAEVENT_M |
+ TIMER_CTL_TBEVENT_M)) | ulEvent);
+}
+
+//*****************************************************************************
+//
+//! Controls the stall handling.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bStall specifies the response to a stall signal.
+//!
+//! This function controls the stall response for the specified timer. If the
+//! \e bStall parameter is \b true, then the timer will stop counting if the
+//! processor enters debug mode; otherwise the timer will keep running while in
+//! debug mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bStall)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the stall mode.
+ //
+ ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL;
+ HWREG(ulBase + TIMER_O_CTL) = (bStall ?
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
+}
+
+//*****************************************************************************
+//
+//! Controls the wait on trigger handling.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bWait specifies if the timer should wait for a trigger input.
+//!
+//! This function controls whether or not a timer waits for a trigger input to
+//! start counting. When enabled, the previous timer in the trigger chain must
+//! count to its timeout in order for this timer to start counting. Refer to
+//! the part's data sheet for a description of the trigger chain.
+//!
+//! \note This functionality is not available on all parts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlWaitOnTrigger(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bWait)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the wait on trigger mode for timer A.
+ //
+ if((ulTimer & TIMER_A) != 0)
+ {
+ if(bWait)
+ {
+ HWREG(ulBase + TIMER_O_TAMR) |= TIMER_TAMR_TAWOT;
+ }
+ else
+ {
+ HWREG(ulBase + TIMER_O_TAMR) &= ~(TIMER_TAMR_TAWOT);
+ }
+ }
+
+ //
+ // Set the wait on trigger mode for timer A.
+ //
+ if((ulTimer & TIMER_B) != 0)
+ {
+ if(bWait)
+ {
+ HWREG(ulBase + TIMER_O_TBMR) |= TIMER_TBMR_TBWOT;
+ }
+ else
+ {
+ HWREG(ulBase + TIMER_O_TBMR) &= ~(TIMER_TBMR_TBWOT);
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Enable RTC counting.
+//!
+//! \param ulBase is the base address of the timer module.
+//!
+//! This function causes the timer to start counting when in RTC mode. If not
+//! configured for RTC mode, this will do nothing.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerRTCEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Enable RTC counting.
+ //
+ HWREG(ulBase + TIMER_O_CTL) |= TIMER_CTL_RTCEN;
+}
+
+//*****************************************************************************
+//
+//! Disable RTC counting.
+//!
+//! \param ulBase is the base address of the timer module.
+//!
+//! This function causes the timer to stop counting when in RTC mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerRTCDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Disable RTC counting.
+ //
+ HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_RTCEN);
+}
+
+//*****************************************************************************
+//
+//! Set the timer prescale value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param ulValue is the timer prescale value; must be between 0 and 255,
+//! inclusive.
+//!
+//! This function sets the value of the input clock prescaler. The prescaler
+//! is only operational when in 16-bit mode and is used to extend the range of
+//! the 16-bit timer modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+ ASSERT(ulValue < 256);
+
+ //
+ // Set the timer A prescaler if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAPR) = ulValue;
+ }
+
+ //
+ // Set the timer B prescaler if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBPR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Get the timer prescale value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.
+//!
+//! This function gets the value of the input clock prescaler. The prescaler
+//! is only operational when in 16-bit mode and is used to extend the range of
+//! the 16-bit timer modes.
+//!
+//! \return The value of the timer prescaler.
+//
+//*****************************************************************************
+unsigned long
+TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Return the appropriate prescale value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) :
+ HWREG(ulBase + TIMER_O_TBPR));
+}
+
+//*****************************************************************************
+//
+//! Set the timer prescale match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param ulValue is the timer prescale match value; must be between 0 and
+//! 255, inclusive.
+//!
+//! This function sets the value of the input clock prescaler match value.
+//! When in a 16-bit mode that uses the counter match and the prescaler, the
+//! prescale match effectively extends the range of the counter to 24-bits.
+//!
+//! \note This functionality is not available on all parts.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+ ASSERT(ulValue < 256);
+
+ //
+ // Set the timer A prescale match if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAPMR) = ulValue;
+ }
+
+ //
+ // Set the timer B prescale match if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBPMR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Get the timer prescale match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.
+//!
+//! This function gets the value of the input clock prescaler match value.
+//! When in a 16-bit mode that uses the counter match and prescaler, the
+//! prescale match effectively extends the range of the counter to 24-bits.
+//!
+//! \note This functionality is not available on all parts.
+//!
+//! \return The value of the timer prescale match.
+//
+//*****************************************************************************
+unsigned long
+TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Return the appropriate prescale match value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) :
+ HWREG(ulBase + TIMER_O_TBPMR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer load value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
+//! timer is configured for 32-bit operation.
+//! \param ulValue is the load value.
+//!
+//! This function sets the timer load value; if the timer is running then the
+//! value will be immediately loaded into the timer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the timer A load value if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAILR) = ulValue;
+ }
+
+ //
+ // Set the timer B load value if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBILR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer load value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for 32-bit operation.
+//!
+//! This function gets the currently programmed interval load value for the
+//! specified timer.
+//!
+//! \return Returns the load value for the timer.
+//
+//*****************************************************************************
+unsigned long
+TimerLoadGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
+
+ //
+ // Return the appropriate load value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) :
+ HWREG(ulBase + TIMER_O_TBILR));
+}
+
+//*****************************************************************************
+//
+//! Gets the current timer value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for 32-bit operation.
+//!
+//! This function reads the current value of the specified timer.
+//!
+//! \return Returns the current value of the timer.
+//
+//*****************************************************************************
+unsigned long
+TimerValueGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
+
+ //
+ // Return the appropriate timer value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) :
+ HWREG(ulBase + TIMER_O_TBR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
+//! timer is configured for 32-bit operation.
+//! \param ulValue is the match value.
+//!
+//! This function sets the match value for a timer. This is used in capture
+//! count mode to determine when to interrupt the processor and in PWM mode to
+//! determine the duty cycle of the output signal.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the timer A match value if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue;
+ }
+
+ //
+ // Set the timer B match value if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for 32-bit operation.
+//!
+//! This function gets the match value for the specified timer.
+//!
+//! \return Returns the match value for the timer.
+//
+//*****************************************************************************
+unsigned long
+TimerMatchGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
+
+ //
+ // Return the appropriate match value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) :
+ HWREG(ulBase + TIMER_O_TBMATCHR));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the timer interrupt.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param pfnHandler is a pointer to the function to be called when the timer
+//! interrupt occurs.
+//!
+//! This sets the handler to be called when a timer interrupt occurs. This
+//! will enable the global interrupt in the interrupt controller; specific
+//! timer interrupts must be enabled via TimerIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source via TimerIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
+ void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Get the interrupt number for this timer module.
+ //
+ ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :
+ ((ulBase == TIMER1_BASE) ? INT_TIMER1A :
+ ((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A)));
+
+ //
+ // Register an interrupt handler for timer A if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulBase, pfnHandler);
+
+ //
+ // Enable the interrupt.
+ //
+ IntEnable(ulBase);
+ }
+
+ //
+ // Register an interrupt handler for timer B if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulBase + 1, pfnHandler);
+
+ //
+ // Enable the interrupt.
+ //
+ IntEnable(ulBase + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the timer interrupt.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function will clear the handler to be called when a timer interrupt
+//! occurs. This will also mask off the interrupt in the interrupt controller
+//! so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Get the interrupt number for this timer module.
+ //
+ ulBase = ((ulBase == TIMER0_BASE) ? INT_TIMER0A :
+ ((ulBase == TIMER1_BASE) ? INT_TIMER1A :
+ ((ulBase == TIMER2_BASE) ? INT_TIMER2A : INT_TIMER3A)));
+
+ //
+ // Unregister the interrupt handler for timer A if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulBase);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulBase);
+ }
+
+ //
+ // Unregister the interrupt handler for timer B if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulBase + 1);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulBase + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables individual timer interrupt sources.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated timer interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter must be the logical OR of any combination of
+//! the following:
+//!
+//! - \b TIMER_CAPB_EVENT - Capture B event interrupt
+//! - \b TIMER_CAPB_MATCH - Capture B match interrupt
+//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt
+//! - \b TIMER_RTC_MATCH - RTC interrupt mask
+//! - \b TIMER_CAPA_EVENT - Capture A event interrupt
+//! - \b TIMER_CAPA_MATCH - Capture A match interrupt
+//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual timer interrupt sources.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated timer interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to TimerIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the timer module. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! values described in TimerIntEnable().
+//
+//*****************************************************************************
+unsigned long
+TimerIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ return(bMasked ? HWREG(ulBase + TIMER_O_MIS) :
+ HWREG(ulBase + TIMER_O_RIS));
+}
+
+//*****************************************************************************
+//
+//! Clears timer interrupt sources.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified timer interrupt sources are cleared, so that they no longer
+//! assert. This must be done in the interrupt handler to keep it from being
+//! called again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to TimerIntEnable().
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + TIMER_O_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+// Puts the timer into its reset state.
+//
+// \param ulBase is the base address of the timer module.
+//
+// The specified timer is disabled, and all its interrupts are disabled,
+// cleared, and unregistered. Then the timer registers are set to their reset
+// value.
+//
+// \return None.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+void
+TimerQuiesce(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Disable the timer.
+ //
+ HWREG(ulBase + TIMER_O_CTL) = TIMER_RV_CTL;
+
+ //
+ // Disable all the timer interrupts.
+ //
+ HWREG(ulBase + TIMER_O_IMR) = TIMER_RV_IMR;
+
+ //
+ // Clear all the timer interrupts.
+ //
+ HWREG(ulBase + TIMER_O_ICR) = 0xFFFFFFFF;
+
+ //
+ // Unregister the interrupt handler. This also disables interrupts to the
+ // core.
+ //
+ TimerIntUnregister(ulBase, TIMER_BOTH);
+
+ //
+ // Set all the registers to their reset value.
+ //
+ HWREG(ulBase + TIMER_O_CFG) = TIMER_RV_CFG;
+ HWREG(ulBase + TIMER_O_TAMR) = TIMER_RV_TAMR;
+ HWREG(ulBase + TIMER_O_TBMR) = TIMER_RV_TBMR;
+ HWREG(ulBase + TIMER_O_RIS) = TIMER_RV_RIS;
+ HWREG(ulBase + TIMER_O_MIS) = TIMER_RV_MIS;
+ HWREG(ulBase + TIMER_O_TAILR) = TIMER_RV_TAILR;
+ HWREG(ulBase + TIMER_O_TBILR) = TIMER_RV_TBILR;
+ HWREG(ulBase + TIMER_O_TAMATCHR) = TIMER_RV_TAMATCHR;
+ HWREG(ulBase + TIMER_O_TBMATCHR) = TIMER_RV_TBMATCHR;
+ HWREG(ulBase + TIMER_O_TAPR) = TIMER_RV_TAPR;
+ HWREG(ulBase + TIMER_O_TBPR) = TIMER_RV_TBPR;
+ HWREG(ulBase + TIMER_O_TAPMR) = TIMER_RV_TAPMR;
+ HWREG(ulBase + TIMER_O_TBPMR) = TIMER_RV_TBPMR;
+ HWREG(ulBase + TIMER_O_TAR) = TIMER_RV_TAR;
+ HWREG(ulBase + TIMER_O_TBR) = TIMER_RV_TBR;
+}
+#endif // DEPRECATED
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/timer.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/timer.h
new file mode 100644
index 00000000..e59b1e9e
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/timer.h
@@ -0,0 +1,165 @@
+//*****************************************************************************
+//
+// timer.h - Prototypes for the timer module
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerConfigure as the ulConfig parameter.
+//
+//*****************************************************************************
+#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer
+#define TIMER_CFG_32_BIT_OS_UP 0x00000011 // 32-bit one-shot up-count timer
+#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer
+#define TIMER_CFG_32_BIT_PER_UP 0x00000012 // 32-bit periodic up-count timer
+#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
+#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
+#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer
+#define TIMER_CFG_A_ONE_SHOT_UP 0x00000011 // Timer A one-shot up-count timer
+#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer
+#define TIMER_CFG_A_PERIODIC_UP 0x00000012 // Timer A periodic up-count timer
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
+#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer
+#define TIMER_CFG_B_ONE_SHOT_UP 0x00001100 // Timer B one-shot up-count timer
+#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer
+#define TIMER_CFG_B_PERIODIC_UP 0x00001200 // Timer B periodic up-count timer
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
+//
+//*****************************************************************************
+#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
+#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
+#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.
+//
+//*****************************************************************************
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
+
+//*****************************************************************************
+//
+// Values that can be passed to most of the timer APIs as the ulTimer
+// parameter.
+//
+//*****************************************************************************
+#define TIMER_A 0x000000ff // Timer A
+#define TIMER_B 0x0000ff00 // Timer B
+#define TIMER_BOTH 0x0000ffff // Timer Both
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bInvert);
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bEnable);
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulEvent);
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bStall);
+extern void TimerControlWaitOnTrigger(unsigned long ulBase,
+ unsigned long ulTimer,
+ tBoolean bWait);
+extern void TimerRTCEnable(unsigned long ulBase);
+extern void TimerRTCDisable(unsigned long ulBase);
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
+extern unsigned long TimerValueGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerMatchGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
+ void (*pfnHandler)(void));
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+
+//*****************************************************************************
+//
+// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used
+// instead to return the timer to its reset state.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+extern void TimerQuiesce(unsigned long ulBase);
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __TIMER_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/uart.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/uart.c
new file mode 100644
index 00000000..51f8ab81
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/uart.c
@@ -0,0 +1,1611 @@
+//*****************************************************************************
+//
+// uart.c - Driver for the UART.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup uart_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_sysctl.h"
+#include "inc/hw_types.h"
+#include "inc/hw_uart.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/uart.h"
+
+//*****************************************************************************
+//
+// The system clock divider defining the maximum baud rate supported by the
+// UART.
+//
+//*****************************************************************************
+#define UART_CLK_DIVIDER ((CLASS_IS_SANDSTORM || \
+ (CLASS_IS_FURY && REVISION_IS_A2) || \
+ (CLASS_IS_DUSTDEVIL && REVISION_IS_A0)) ? \
+ 16 : 8)
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a UART base address.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function determines if a UART port base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+UARTBaseValid(unsigned long ulBase)
+{
+ return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) ||
+ (ulBase == UART2_BASE));
+}
+#endif
+
+//*****************************************************************************
+//
+//! Sets the type of parity.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulParity specifies the type of parity to use.
+//!
+//! Sets the type of parity to use for transmitting and expect when receiving.
+//! The \e ulParity parameter must be one of \b UART_CONFIG_PAR_NONE,
+//! \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE,
+//! or \b UART_CONFIG_PAR_ZERO. The last two allow direct control of the
+//! parity bit; it is always either one or zero based on the mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT((ulParity == UART_CONFIG_PAR_NONE) ||
+ (ulParity == UART_CONFIG_PAR_EVEN) ||
+ (ulParity == UART_CONFIG_PAR_ODD) ||
+ (ulParity == UART_CONFIG_PAR_ONE) ||
+ (ulParity == UART_CONFIG_PAR_ZERO));
+
+ //
+ // Set the parity mode.
+ //
+ HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) &
+ ~(UART_LCRH_SPS | UART_LCRH_EPS |
+ UART_LCRH_PEN)) | ulParity);
+}
+
+//*****************************************************************************
+//
+//! Gets the type of parity currently being used.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function gets the type of parity used for transmitting data and
+//! expected when receiving data.
+//!
+//! \return Returns the current parity settings, specified as one of
+//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
+//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
+//
+//*****************************************************************************
+unsigned long
+UARTParityModeGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the current parity setting.
+ //
+ return(HWREG(ulBase + UART_O_LCRH) &
+ (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO level at which interrupts are generated.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of
+//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8,
+//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
+//! \param ulRxLevel is the receive FIFO interrupt level, specified as one of
+//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
+//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
+//!
+//! This function sets the FIFO level at which transmit and receive interrupts
+//! are generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulRxLevel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT((ulTxLevel == UART_FIFO_TX1_8) ||
+ (ulTxLevel == UART_FIFO_TX2_8) ||
+ (ulTxLevel == UART_FIFO_TX4_8) ||
+ (ulTxLevel == UART_FIFO_TX6_8) ||
+ (ulTxLevel == UART_FIFO_TX7_8));
+ ASSERT((ulRxLevel == UART_FIFO_RX1_8) ||
+ (ulRxLevel == UART_FIFO_RX2_8) ||
+ (ulRxLevel == UART_FIFO_RX4_8) ||
+ (ulRxLevel == UART_FIFO_RX6_8) ||
+ (ulRxLevel == UART_FIFO_RX7_8));
+
+ //
+ // Set the FIFO interrupt levels.
+ //
+ HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel;
+}
+
+//*****************************************************************************
+//
+//! Gets the FIFO level at which interrupts are generated.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param pulTxLevel is a pointer to storage for the transmit FIFO level,
+//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
+//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
+//! \param pulRxLevel is a pointer to storage for the receive FIFO level,
+//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
+//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
+//!
+//! This function gets the FIFO level at which transmit and receive interrupts
+//! are generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
+ unsigned long *pulRxLevel)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Read the FIFO level register.
+ //
+ ulTemp = HWREG(ulBase + UART_O_IFLS);
+
+ //
+ // Extract the transmit and receive FIFO levels.
+ //
+ *pulTxLevel = ulTemp & UART_IFLS_TX_M;
+ *pulRxLevel = ulTemp & UART_IFLS_RX_M;
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration of a UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulUARTClk is the rate of the clock supplied to the UART module.
+//! \param ulBaud is the desired baud rate.
+//! \param ulConfig is the data format for the port (number of data bits,
+//! number of stop bits, and parity).
+//!
+//! This function configures the UART for operation in the specified data
+//! format. The baud rate is provided in the \e ulBaud parameter and the data
+//! format in the \e ulConfig parameter.
+//!
+//! The \e ulConfig parameter is the logical OR of three values: the number of
+//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8,
+//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5
+//! select from eight to five data bits per byte (respectively).
+//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop
+//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,
+//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO
+//! select the parity mode (no parity bit, even parity bit, odd parity bit,
+//! parity bit always one, and parity bit always zero, respectively).
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original UARTConfigSet() API and performs the
+//! same actions. A macro is provided in uart.h to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long ulBaud, unsigned long ulConfig)
+{
+ unsigned long ulDiv;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT(ulBaud != 0);
+ ASSERT(ulUARTClk >= (ulBaud * UART_CLK_DIVIDER));
+
+ //
+ // Stop the UART.
+ //
+ UARTDisable(ulBase);
+
+ //
+ // Is the required baud rate greater than the maximum rate supported
+ // without the use of high speed mode?
+ //
+ if((ulBaud * 16) > ulUARTClk)
+ {
+ //
+ // Enable high speed mode.
+ //
+ HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE;
+
+ //
+ // Half the supplied baud rate to compensate for enabling high speed
+ // mode. This allows the following code to be common to both cases.
+ //
+ ulBaud /= 2;
+ }
+ else
+ {
+ //
+ // Disable high speed mode.
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE);
+ }
+
+ //
+ // Compute the fractional baud rate divider.
+ //
+ ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2;
+
+ //
+ // Set the baud rate.
+ //
+ HWREG(ulBase + UART_O_IBRD) = ulDiv / 64;
+ HWREG(ulBase + UART_O_FBRD) = ulDiv % 64;
+
+ //
+ // Set parity, data length, and number of stop bits.
+ //
+ HWREG(ulBase + UART_O_LCRH) = ulConfig;
+
+ //
+ // Clear the flags register.
+ //
+ HWREG(ulBase + UART_O_FR) = 0;
+
+ //
+ // Start the UART.
+ //
+ UARTEnable(ulBase);
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration of a UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulUARTClk is the rate of the clock supplied to the UART module.
+//! \param pulBaud is a pointer to storage for the baud rate.
+//! \param pulConfig is a pointer to storage for the data format.
+//!
+//! The baud rate and data format for the UART is determined, given an
+//! explicitly provided peripheral clock (hence the ExpClk suffix). The
+//! returned baud rate is the actual baud rate; it may not be the exact baud
+//! rate requested or an ``official'' baud rate. The data format returned in
+//! \e pulConfig is enumerated the same as the \e ulConfig parameter of
+//! UARTConfigSetExpClk().
+//!
+//! The peripheral clock will be the same as the processor clock. This will be
+//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
+//! if it is constant and known (to save the code/execution overhead of a call
+//! to SysCtlClockGet()).
+//!
+//! This function replaces the original UARTConfigGet() API and performs the
+//! same actions. A macro is provided in uart.h to map the original
+//! API to this API.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long *pulBaud, unsigned long *pulConfig)
+{
+ unsigned long ulInt, ulFrac;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Compute the baud rate.
+ //
+ ulInt = HWREG(ulBase + UART_O_IBRD);
+ ulFrac = HWREG(ulBase + UART_O_FBRD);
+ *pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac);
+
+ //
+ // See if high speed mode enabled.
+ //
+ if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE)
+ {
+ //
+ // High speed mode is enabled so the actual baud rate is actually
+ // double what was just calculated.
+ //
+ *pulBaud *= 2;
+ }
+
+ //
+ // Get the parity, data length, and number of stop bits.
+ //
+ *pulConfig = (HWREG(ulBase + UART_O_LCRH) &
+ (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 |
+ UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! Enables transmitting and receiving.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Sets the UARTEN, TXE, and RXE bits, and enables the transmit and receive
+//! FIFOs.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
+
+ //
+ // Enable RX, TX, and the UART.
+ //
+ HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
+ UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! Disables transmitting and receiving.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Clears the UARTEN, TXE, and RXE bits, then waits for the end of
+//! transmission of the current character, and flushes the transmit FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Wait for end of TX.
+ //
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY)
+ {
+ }
+
+ //
+ // Disable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+
+ //
+ // Disable the UART.
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
+ UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! Enables the transmit and receive FIFOs.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This functions enables the transmit and receive FIFOs in the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the transmit and receive FIFOs.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This functions disables the transmit and receive FIFOs in the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFODisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Disable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+}
+
+//*****************************************************************************
+//
+//! Enables SIR (IrDA) mode on the specified UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param bLowPower indicates if SIR Low Power Mode is to be used.
+//!
+//! Enables the SIREN control bit for IrDA mode on the UART. If the
+//! \e bLowPower flag is set, then SIRLP bit will also be set.
+//!
+//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable SIR and SIRLP (if appropriate).
+ //
+ if(bLowPower)
+ {
+ HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN | UART_CTL_SIRLP);
+ }
+ else
+ {
+ HWREG(ulBase + UART_O_CTL) |= (UART_CTL_SIREN);
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables SIR (IrDA) mode on the specified UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Clears the SIREN (IrDA) and SIRLP (Low Power) bits.
+//!
+//! \note SIR (IrDA) operation is not supported on Sandstorm-class devices.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDisableSIR(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Disable SIR and SIRLP (if appropriate).
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_SIREN | UART_CTL_SIRLP);
+}
+
+//*****************************************************************************
+//
+//! Enables ISO 7816 smart card mode on the specified UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Enables the SMART control bit for ISO 7816 smart card mode on the UART.
+//! This call also sets 8 bit word length and even parity as required by ISO
+//! 7816.
+//!
+//! \note The availability of ISO 7816 smart card mode varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTSmartCardEnable(unsigned long ulBase)
+{
+ unsigned long ulVal;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Set 8 bit word length, even parity, 2 stop bits (even though the STP2
+ // bit is ignored when in smartcard mode, this lets the caller read back
+ // the actual setting in use).
+ //
+ ulVal = HWREG(ulBase + UART_O_LCRH);
+ ulVal &= ~(UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN |
+ UART_LCRH_WLEN_M);
+ ulVal |= UART_LCRH_WLEN_8 | UART_LCRH_PEN | UART_LCRH_EPS | UART_LCRH_STP2;
+ HWREG(ulBase + UART_O_LCRH) = ulVal;
+
+ //
+ // Enable SMART mode.
+ //
+ HWREG(ulBase + UART_O_CTL) |= UART_CTL_SMART;
+}
+
+//*****************************************************************************
+//
+//! Disables ISO 7816 smart card mode on the specified UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Clears the SMART (ISO 7816 smart card) bits in the UART control register.
+//!
+//! \note The availability of ISO 7816 smart card mode varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTSmartCardDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Disable the SMART bit.
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~UART_CTL_SMART;
+}
+
+//*****************************************************************************
+//
+//! Sets the states of the DTR and/or RTS modem control signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulControl is a bit-mapped flag indicating which modem control bits
+//! should be set.
+//!
+//! Sets the states of the DTR or RTS modem handshake outputs from the UART.
+//!
+//! The \e ulControl parameter is the logical OR of any of the following:
+//!
+//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
+//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTModemControlSet(unsigned long ulBase, unsigned long ulControl)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(ulBase == UART1_BASE);
+ ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
+
+ //
+ // Set the appropriate modem control output bits.
+ //
+ ulTemp = HWREG(ulBase + UART_O_CTL);
+ ulTemp |= (ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+ HWREG(ulBase + UART_O_CTL) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Clears the states of the DTR and/or RTS modem control signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulControl is a bit-mapped flag indicating which modem control bits
+//! should be set.
+//!
+//! Clears the states of the DTR or RTS modem handshake outputs from the UART.
+//!
+//! The \e ulControl parameter is the logical OR of any of the following:
+//!
+//! - \b UART_OUTPUT_DTR - The Modem Control DTR signal
+//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTModemControlClear(unsigned long ulBase, unsigned long ulControl)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(ulBase == UART1_BASE);
+ ASSERT((ulControl & ~(UART_OUTPUT_RTS | UART_OUTPUT_DTR)) == 0);
+
+ //
+ // Set the appropriate modem control output bits.
+ //
+ ulTemp = HWREG(ulBase + UART_O_CTL);
+ ulTemp &= ~(ulControl & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+ HWREG(ulBase + UART_O_CTL) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the states of the DTR and RTS modem control signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Returns the current states of each of the two UART modem control signals,
+//! DTR and RTS.
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return Returns the states of the handshake output signals. This will be a
+//! logical logical OR combination of values \b UART_OUTPUT_RTS and
+//! \b UART_OUTPUT_DTR where the presence of each flag indicates that the
+//! associated signal is asserted.
+//
+//*****************************************************************************
+unsigned long
+UARTModemControlGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(ulBase == UART1_BASE);
+
+ return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS | UART_OUTPUT_DTR));
+}
+
+//*****************************************************************************
+//
+//! Gets the states of the RI, DCD, DSR and CTS modem status signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Returns the current states of each of the four UART modem status signals,
+//! RI, DCD, DSR and CTS.
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! Stellaris part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return Returns the states of the handshake output signals. This will be a
+//! logical logical OR combination of values \b UART_INPUT_RI, \b
+//! UART_INPUT_DCD, \b UART_INPUT_CTS and \b UART_INPUT_DSR where the
+//! presence of each flag indicates that the associated signal is asserted.
+//
+//*****************************************************************************
+unsigned long
+UARTModemStatusGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(ulBase == UART1_BASE);
+
+ return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_RI | UART_INPUT_DCD |
+ UART_INPUT_CTS | UART_INPUT_DSR));
+}
+
+//*****************************************************************************
+//
+//! Sets the UART hardware flow control mode to be used.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulMode indicates the flow control modes to be used. This is a
+//! logical OR combination of values \b UART_FLOWCONTROL_TX and \b
+//! UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
+//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control.
+//!
+//! Sets the required hardware flow control modes. If \e ulMode contains
+//! flag \b UART_FLOWCONTROL_TX, data is only transmitted if the incoming CTS
+//! signal is asserted. If \e ulMode contains flag \b UART_FLOWCONTROL_RX,
+//! the RTS output is controlled by the hardware and is asserted only when
+//! there is space available in the receive FIFO. If no hardware flow control
+//! is required, UART_FLOWCONTROL_NONE should be passed.
+//!
+//! \note The availability of hardware flow control varies with the Stellaris
+//! part and UART in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0);
+
+ //
+ // Set the flow control mode as requested.
+ //
+ HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
+ ~(UART_FLOWCONTROL_TX |
+ UART_FLOWCONTROL_RX)) | ulMode);
+}
+
+//*****************************************************************************
+//
+//! Returns the UART hardware flow control mode currently in use.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Returns the current hardware flow control mode.
+//!
+//! \note The availability of hardware flow control varies with the Stellaris
+//! part and UART in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns the current flow control mode in use. This is a
+//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit
+//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS)
+//! flow control is in use. If hardware flow control is disabled, \b
+//! UART_FLOWCONTROL_NONE will be returned.
+//
+//*****************************************************************************
+unsigned long
+UARTFlowControlGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(!CLASS_IS_SANDSTORM && !CLASS_IS_FURY && !CLASS_IS_DUSTDEVIL);
+ ASSERT(UARTBaseValid(ulBase));
+
+ return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX |
+ UART_FLOWCONTROL_RX));
+}
+
+//*****************************************************************************
+//
+//! Sets the operating mode for the UART transmit interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulMode is the operating mode for the transmit interrupt. It may be
+//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle
+//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO
+//! level.
+//!
+//! This function allows the mode of the UART transmit interrupt to be set. By
+//! default, the transmit interrupt is asserted when the FIFO level falls past
+//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this
+//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the
+//! transmit interrupt will only be asserted once the transmitter is completely
+//! idle - the transmit FIFO is empty and all bits, including any stop bits,
+//! have cleared the transmitter.
+//!
+//! \note The availability of end-of-transmission mode varies with the
+//! Stellaris part in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT((ulMode == UART_TXINT_MODE_EOT) ||
+ (ulMode == UART_TXINT_MODE_FIFO));
+
+ //
+ // Set or clear the EOT bit of the UART control register as appropriate.
+ //
+ HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
+ ~(UART_TXINT_MODE_EOT |
+ UART_TXINT_MODE_FIFO)) | ulMode);
+}
+
+//*****************************************************************************
+//
+//! Returns the current operating mode for the UART transmit interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns the current operating mode for the UART transmit
+//! interrupt. The return value will be \b UART_TXINT_MODE_EOT if the
+//! transmit interrupt is currently set to be asserted once the transmitter is
+//! completely idle - the transmit FIFO is empty and all bits, including any
+//! stop bits, have cleared the transmitter. The return value will be \b
+//! UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon the
+//! level of the transmit FIFO.
+//!
+//! \note The availability of end-of-transmission mode varies with the
+//! Stellaris part in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT.
+//
+//*****************************************************************************
+unsigned long
+UARTTxIntModeGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the current transmit interrupt mode.
+ //
+ return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT |
+ UART_TXINT_MODE_FIFO));
+}
+
+//*****************************************************************************
+//
+//! Determines if there are any characters in the receive FIFO.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns a flag indicating whether or not there is data
+//! available in the receive FIFO.
+//!
+//! \return Returns \b true if there is data in the receive FIFO or \b false
+//! if there is no data in the receive FIFO.
+//
+//*****************************************************************************
+tBoolean
+UARTCharsAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the availability of characters.
+ //
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! Determines if there is any space in the transmit FIFO.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns a flag indicating whether or not there is space
+//! available in the transmit FIFO.
+//!
+//! \return Returns \b true if there is space available in the transmit FIFO
+//! or \b false if there is no space available in the transmit FIFO.
+//
+//*****************************************************************************
+tBoolean
+UARTSpaceAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the availability of space.
+ //
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! Receives a character from the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Gets a character from the receive FIFO for the specified port.
+//!
+//! This function replaces the original UARTCharNonBlockingGet() API and
+//! performs the same actions. A macro is provided in uart.h to map
+//! the original API to this API.
+//!
+//! \return Returns the character read from the specified port, cast as a
+//! \e long. A \b -1 is returned if there are no characters present in the
+//! receive FIFO. The UARTCharsAvail() function should be called before
+//! attempting to call this function.
+//
+//*****************************************************************************
+long
+UARTCharGetNonBlocking(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // See if there are any characters in the receive FIFO.
+ //
+ if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE))
+ {
+ //
+ // Read and return the next character.
+ //
+ return(HWREG(ulBase + UART_O_DR));
+ }
+ else
+ {
+ //
+ // There are no characters, so return a failure.
+ //
+ return(-1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Waits for a character from the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Gets a character from the receive FIFO for the specified port. If there
+//! are no characters available, this function waits until a character is
+//! received before returning.
+//!
+//! \return Returns the character read from the specified port, cast as a
+//! \e long.
+//
+//*****************************************************************************
+long
+UARTCharGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Wait until a char is available.
+ //
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)
+ {
+ }
+
+ //
+ // Now get the char.
+ //
+ return(HWREG(ulBase + UART_O_DR));
+}
+
+//*****************************************************************************
+//
+//! Sends a character to the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ucData is the character to be transmitted.
+//!
+//! Writes the character \e ucData to the transmit FIFO for the specified port.
+//! This function does not block, so if there is no space available, then a
+//! \b false is returned, and the application must retry the function later.
+//!
+//! This function replaces the original UARTCharNonBlockingPut() API and
+//! performs the same actions. A macro is provided in uart.h to map
+//! the original API to this API.
+//!
+//! \return Returns \b true if the character was successfully placed in the
+//! transmit FIFO or \b false if there was no space available in the transmit
+//! FIFO.
+//
+//*****************************************************************************
+tBoolean
+UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // See if there is space in the transmit FIFO.
+ //
+ if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF))
+ {
+ //
+ // Write this character to the transmit FIFO.
+ //
+ HWREG(ulBase + UART_O_DR) = ucData;
+
+ //
+ // Success.
+ //
+ return(true);
+ }
+ else
+ {
+ //
+ // There is no space in the transmit FIFO, so return a failure.
+ //
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Waits to send a character from the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ucData is the character to be transmitted.
+//!
+//! Sends the character \e ucData to the transmit FIFO for the specified port.
+//! If there is no space available in the transmit FIFO, this function waits
+//! until there is space available before returning.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTCharPut(unsigned long ulBase, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Wait until space is available.
+ //
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)
+ {
+ }
+
+ //
+ // Send the char.
+ //
+ HWREG(ulBase + UART_O_DR) = ucData;
+}
+
+//*****************************************************************************
+//
+//! Causes a BREAK to be sent.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param bBreakState controls the output level.
+//!
+//! Calling this function with \e bBreakState set to \b true asserts a break
+//! condition on the UART. Calling this function with \e bBreakState set to
+//! \b false removes the break condition. For proper transmission of a break
+//! command, the break must be asserted for at least two complete frames.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Set the break condition as requested.
+ //
+ HWREG(ulBase + UART_O_LCRH) =
+ (bBreakState ?
+ (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) :
+ (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK)));
+}
+
+//*****************************************************************************
+//
+//! Determines whether the UART transmitter is busy or not.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Allows the caller to determine whether all transmitted bytes have cleared
+//! the transmitter hardware. If \b false is returned, the transmit FIFO is
+//! empty and all bits of the last transmitted character, including all stop
+//! bits, have left the hardware shift register.
+//!
+//! \return Returns \b true if the UART is transmitting or \b false if all
+//! transmissions are complete.
+//
+//*****************************************************************************
+tBoolean
+UARTBusy(unsigned long ulBase)
+{
+ //
+ // Check the argument.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Determine if the UART is busy.
+ //
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a UART interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! UART interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! will enable the global interrupt in the interrupt controller; specific UART
+//! interrupts must be enabled via UARTIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Determine the interrupt number based on the UART port.
+ //
+ ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
+ ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the UART interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for a UART interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! will clear the handler to be called when a UART interrupt occurs. This
+//! will also mask off the interrupt in the interrupt controller so that the
+//! interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Determine the interrupt number based on the UART port.
+ //
+ ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
+ ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Enables individual UART interrupt sources.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated UART interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b UART_INT_OE - Overrun Error interrupt
+//! - \b UART_INT_BE - Break Error interrupt
+//! - \b UART_INT_PE - Parity Error interrupt
+//! - \b UART_INT_FE - Framing Error interrupt
+//! - \b UART_INT_RT - Receive Timeout interrupt
+//! - \b UART_INT_TX - Transmit interrupt
+//! - \b UART_INT_RX - Receive interrupt
+//! - \b UART_INT_DSR - DSR interrupt
+//! - \b UART_INT_DCD - DCD interrupt
+//! - \b UART_INT_CTS - CTS interrupt
+//! - \b UART_INT_RI - RI interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + UART_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual UART interrupt sources.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated UART interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to UARTIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the specified UART. Either the raw
+//! interrupt status or the status of interrupts that are allowed to reflect to
+//! the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in UARTIntEnable().
+//
+//*****************************************************************************
+unsigned long
+UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + UART_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + UART_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears UART interrupt sources.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified UART interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to UARTIntEnable().
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + UART_O_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Enable UART DMA operation.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulDMAFlags is a bit mask of the DMA features to enable.
+//!
+//! The specified UART DMA features are enabled. The UART can be
+//! configured to use DMA for transmit or receive, and to disable
+//! receive if an error occurs. The \e ulDMAFlags parameter is the
+//! logical OR of any of the following values:
+//!
+//! - UART_DMA_RX - enable DMA for receive
+//! - UART_DMA_TX - enable DMA for transmit
+//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Set the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Disable UART DMA operation.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulDMAFlags is a bit mask of the DMA features to disable.
+//!
+//! This function is used to disable UART DMA features that were enabled
+//! by UARTDMAEnable(). The specified UART DMA features are disabled. The
+//! \e ulDMAFlags parameter is the logical OR of any of the following values:
+//!
+//! - UART_DMA_RX - disable DMA for receive
+//! - UART_DMA_TX - disable DMA for transmit
+//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Clear the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets current receiver errors.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns the current state of each of the 4 receiver error
+//! sources. The returned errors are equivalent to the four error bits
+//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
+//! with the exception that the overrun error is set immediately the overrun
+//! occurs rather than when a character is next read.
+//!
+//! \return Returns a logical OR combination of the receiver error flags,
+//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
+//! and \b UART_RXERROR_OVERRUN.
+//
+//*****************************************************************************
+unsigned long
+UARTRxErrorGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the current value of the receive status register.
+ //
+ return(HWREG(ulBase + UART_O_RSR) & 0x0000000F);
+}
+
+//*****************************************************************************
+//
+//! Clears all reported receiver errors.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function is used to clear all receiver error conditions reported via
+//! UARTRxErrorGet(). If using the overrun, framing error, parity error or
+//! break interrupts, this function must be called after clearing the interrupt
+//! to ensure that later errors of the same type trigger another interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTRxErrorClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Any write to the Error Clear Register will clear all bits which are
+ // currently set.
+ //
+ HWREG(ulBase + UART_O_ECR) = 0;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/uart.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/uart.h
new file mode 100644
index 00000000..2a23fa63
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/uart.h
@@ -0,0 +1,243 @@
+//*****************************************************************************
+//
+// uart.h - Defines and Macros for the UART.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __UART_H__
+#define __UART_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
+// as the ulIntFlags parameter, and returned from UARTIntStatus.
+//
+//*****************************************************************************
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask
+#define UART_INT_RX 0x010 // Receive Interrupt Mask
+#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask
+#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask
+#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
+#define UART_INT_RI 0x001 // RI Modem Interrupt Mask
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
+// and returned by UARTConfigGetExpClk in the pulConfig parameter.
+// Additionally, the UART_CONFIG_PAR_* subset can be passed to
+// UARTParityModeSet as the ulParity parameter, and are returned by
+// UARTParityModeGet.
+//
+//*****************************************************************************
+#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
+#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
+#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
+#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
+#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
+// returned by UARTFIFOLevelGet in the pulTxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
+#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
+#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
+#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
+#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
+// returned by UARTFIFOLevelGet in the pulRxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
+#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
+#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
+#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
+#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
+//
+//*****************************************************************************
+#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
+#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
+#define UART_DMA_RX 0x00000001 // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Values returned from UARTRxErrorGet().
+//
+//*****************************************************************************
+#define UART_RXERROR_OVERRUN 0x00000008
+#define UART_RXERROR_BREAK 0x00000004
+#define UART_RXERROR_PARITY 0x00000002
+#define UART_RXERROR_FRAMING 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTHandshakeOutputsSet() or returned from
+// UARTHandshakeOutputGet().
+//
+//*****************************************************************************
+#define UART_OUTPUT_RTS 0x00000800
+#define UART_OUTPUT_DTR 0x00000400
+
+//*****************************************************************************
+//
+// Values that can be returned from UARTHandshakeInputsGet().
+//
+//*****************************************************************************
+#define UART_INPUT_RI 0x00000100
+#define UART_INPUT_DCD 0x00000004
+#define UART_INPUT_DSR 0x00000002
+#define UART_INPUT_CTS 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFlowControl() or returned from
+// UARTFlowControlGet().
+//
+//*****************************************************************************
+#define UART_FLOWCONTROL_TX 0x00008000
+#define UART_FLOWCONTROL_RX 0x00004000
+#define UART_FLOWCONTROL_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTTxIntModeSet() or returned from
+// UARTTxIntModeGet().
+//
+//*****************************************************************************
+#define UART_TXINT_MODE_FIFO 0x00000000
+#define UART_TXINT_MODE_EOT 0x00000010
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
+extern unsigned long UARTParityModeGet(unsigned long ulBase);
+extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulRxLevel);
+extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
+ unsigned long *pulRxLevel);
+extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long ulBaud, unsigned long ulConfig);
+extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long *pulBaud,
+ unsigned long *pulConfig);
+extern void UARTEnable(unsigned long ulBase);
+extern void UARTDisable(unsigned long ulBase);
+extern void UARTFIFOEnable(unsigned long ulBase);
+extern void UARTFIFODisable(unsigned long ulBase);
+extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
+extern void UARTDisableSIR(unsigned long ulBase);
+extern tBoolean UARTCharsAvail(unsigned long ulBase);
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);
+extern long UARTCharGetNonBlocking(unsigned long ulBase);
+extern long UARTCharGet(unsigned long ulBase);
+extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
+ unsigned char ucData);
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
+extern tBoolean UARTBusy(unsigned long ulBase);
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void UARTIntUnregister(unsigned long ulBase);
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern unsigned long UARTRxErrorGet(unsigned long ulBase);
+extern void UARTRxErrorClear(unsigned long ulBase);
+extern void UARTSmartCardEnable(unsigned long ulBase);
+extern void UARTSmartCardDisable(unsigned long ulBase);
+extern void UARTModemControlSet(unsigned long ulBase,
+ unsigned long ulControl);
+extern void UARTModemControlClear(unsigned long ulBase,
+ unsigned long ulControl);
+extern unsigned long UARTModemControlGet(unsigned long ulBase);
+extern unsigned long UARTModemStatusGet(unsigned long ulBase);
+extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
+extern unsigned long UARTFlowControlGet(unsigned long ulBase);
+extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
+extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several UART APIs have been renamed, with the original function name being
+// deprecated. These defines provide backward compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#include "driverlib/sysctl.h"
+#define UARTConfigSet(a, b, c) \
+ UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
+#define UARTConfigGet(a, b, c) \
+ UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
+#define UARTCharNonBlockingGet(a) \
+ UARTCharGetNonBlocking(a)
+#define UARTCharNonBlockingPut(a, b) \
+ UARTCharPutNonBlocking(a, b)
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __UART_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/udma.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/udma.c
new file mode 100644
index 00000000..a9596641
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/udma.c
@@ -0,0 +1,1178 @@
+//*****************************************************************************
+//
+// udma.c - Driver for the micro-DMA controller.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup udma_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "inc/hw_udma.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/udma.h"
+
+//*****************************************************************************
+//
+//! Enables the uDMA controller for use.
+//!
+//! This function enables the uDMA controller. The uDMA controller must be
+//! enabled before it can be configured and used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAEnable(void)
+{
+ //
+ // Set the master enable bit in the config register.
+ //
+ HWREG(UDMA_CFG) = UDMA_CFG_MASTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the uDMA controller for use.
+//!
+//! This function disables the uDMA controller. Once disabled, the uDMA
+//! controller will not operate until re-enabled with uDMAEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMADisable(void)
+{
+ //
+ // Clear the master enable bit in the config register.
+ //
+ HWREG(UDMA_CFG) = 0;
+}
+
+//*****************************************************************************
+//
+//! Gets the uDMA error status.
+//!
+//! This function returns the uDMA error status. It should be called from
+//! within the uDMA error interrupt handler to determine if a uDMA error
+//! occurred.
+//!
+//! \return Returns non-zero if a uDMA error is pending.
+//
+//*****************************************************************************
+unsigned long
+uDMAErrorStatusGet(void)
+{
+ //
+ // Return the uDMA error status.
+ //
+ return(HWREG(UDMA_ERRCLR));
+}
+
+//*****************************************************************************
+//
+//! Clears the uDMA error interrupt.
+//!
+//! This function clears a pending uDMA error interrupt. It should be called
+//! from within the uDMA error interrupt handler to clear the interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAErrorStatusClear(void)
+{
+ //
+ // Clear the uDMA error interrupt.
+ //
+ HWREG(UDMA_ERRCLR) = 1;
+}
+
+//*****************************************************************************
+//
+//! Enables a uDMA channel for operation.
+//!
+//! \param ulChannelNum is the channel number to enable.
+//!
+//! This function enables a specific uDMA channel for use. This function must
+//! be used to enable a channel before it can be used to perform a uDMA
+//! transfer.
+//!
+//! When a uDMA transfer is completed, the channel will be automatically
+//! disabled by the uDMA controller. Therefore, this function should be called
+//! prior to starting up any new transfer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelEnable(unsigned long ulChannelNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannelNum < 32);
+
+ //
+ // Set the bit for this channel in the enable set register.
+ //
+ HWREG(UDMA_ENASET) = 1 << ulChannelNum;
+}
+
+//*****************************************************************************
+//
+//! Disables a uDMA channel for operation.
+//!
+//! \param ulChannelNum is the channel number to disable.
+//!
+//! This function disables a specific uDMA channel. Once disabled, a channel
+//! will not respond to uDMA transfer requests until re-enabled via
+//! uDMAChannelEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelDisable(unsigned long ulChannelNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannelNum < 32);
+
+ //
+ // Set the bit for this channel in the enable clear register.
+ //
+ HWREG(UDMA_ENACLR) = 1 << ulChannelNum;
+}
+
+//*****************************************************************************
+//
+//! Checks if a uDMA channel is enabled for operation.
+//!
+//! \param ulChannelNum is the channel number to check.
+//!
+//! This function checks to see if a specific uDMA channel is enabled. This
+//! can be used to check the status of a transfer, since the channel will
+//! be automatically disabled at the end of a transfer.
+//!
+//! \return Returns \b true if the channel is enabled, \b false if disabled.
+//
+//*****************************************************************************
+tBoolean
+uDMAChannelIsEnabled(unsigned long ulChannelNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannelNum < 32);
+
+ //
+ // AND the specified channel bit with the enable register, and return the
+ // result.
+ //
+ return((HWREG(UDMA_ENASET) & (1 << ulChannelNum)) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Sets the base address for the channel control table.
+//!
+//! \param pControlTable is a pointer to the 1024 byte aligned base address
+//! of the uDMA channel control table.
+//!
+//! This function sets the base address of the channel control table. This
+//! table resides in system memory and holds control information for each uDMA
+//! channel. The table must be aligned on a 1024 byte boundary. The base
+//! address must be set before any of the channel functions can be used.
+//!
+//! The size of the channel control table depends on the number of uDMA
+//! channels, and which transfer modes are used. Refer to the introductory
+//! text and the microcontroller datasheet for more information about the
+//! channel control table.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAControlBaseSet(void *pControlTable)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(((unsigned long)pControlTable & ~0x3FF) ==
+ (unsigned long)pControlTable);
+ ASSERT((unsigned long)pControlTable >= 0x20000000);
+
+ //
+ // Program the base address into the register.
+ //
+ HWREG(UDMA_CTLBASE) = (unsigned long)pControlTable;
+}
+
+//*****************************************************************************
+//
+//! Gets the base address for the channel control table.
+//!
+//! This function gets the base address of the channel control table. This
+//! table resides in system memory and holds control information for each uDMA
+//! channel.
+//!
+//! \return Returns a pointer to the base address of the channel control table.
+//
+//*****************************************************************************
+void *
+uDMAControlBaseGet(void)
+{
+ //
+ // Read the current value of the control base register, and return it to
+ // the caller.
+ //
+ return((void *)HWREG(UDMA_CTLBASE));
+}
+
+//*****************************************************************************
+//
+//! Gets the base address for the channel control table alternate structures.
+//!
+//! This function gets the base address of the second half of the channel
+//! control table that holds the alternate control structures for each channel.
+//!
+//! \return Returns a pointer to the base address of the second half of the
+//! channel control table.
+//
+//*****************************************************************************
+void *
+uDMAControlAlternateBaseGet(void)
+{
+ //
+ // Read the current value of the control base register, and return it to
+ // the caller.
+ //
+ return((void *)HWREG(UDMA_ALTBASE));
+}
+
+//*****************************************************************************
+//
+//! Requests a uDMA channel to start a transfer.
+//!
+//! \param ulChannelNum is the channel number on which to request a uDMA
+//! transfer.
+//!
+//! This function allows software to request a uDMA channel to begin a
+//! transfer. This could be used for performing a memory to memory transfer,
+//! or if for some reason a transfer needs to be initiated by software instead
+//! of the peripheral associated with that channel.
+//!
+//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then
+//! the completion will be signaled on the uDMA dedicated interrupt. If a
+//! peripheral channel is used, then the completion will be signaled on the
+//! peripheral's interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelRequest(unsigned long ulChannelNum)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannelNum < 32);
+
+ //
+ // Set the bit for this channel in the software uDMA request register.
+ //
+ HWREG(UDMA_SWREQ) = 1 << ulChannelNum;
+}
+
+//*****************************************************************************
+//
+//! Enables attributes of a uDMA channel.
+//!
+//! \param ulChannelNum is the channel to configure.
+//! \param ulAttr is a combination of attributes for the channel.
+//!
+//! The \e ulAttr parameter is the logical OR of any of the following:
+//!
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst
+//! mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//! for this channel (it is very unlikely that this flag should be used)
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//! peripheral for this channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelAttributeEnable(unsigned long ulChannelNum, unsigned long ulAttr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannelNum < 32);
+ ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
+ UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0);
+
+ //
+ // Set the useburst bit for this channel if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_USEBURST)
+ {
+ HWREG(UDMA_USEBURSTSET) = 1 << ulChannelNum;
+ }
+
+ //
+ // Set the alternate control select bit for this channel,
+ // if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_ALTSELECT)
+ {
+ HWREG(UDMA_ALTSET) = 1 << ulChannelNum;
+ }
+
+ //
+ // Set the high priority bit for this channel, if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_HIGH_PRIORITY)
+ {
+ HWREG(UDMA_PRIOSET) = 1 << ulChannelNum;
+ }
+
+ //
+ // Set the request mask bit for this channel, if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_REQMASK)
+ {
+ HWREG(UDMA_REQMASKSET) = 1 << ulChannelNum;
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables attributes of a uDMA channel.
+//!
+//! \param ulChannelNum is the channel to configure.
+//! \param ulAttr is a combination of attributes for the channel.
+//!
+//! This function is used to disable attributes of a uDMA channel.
+//!
+//! The \e ulAttr parameter is the logical OR of any of the following:
+//!
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst
+//! mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//! for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//! peripheral for this channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelAttributeDisable(unsigned long ulChannelNum, unsigned long ulAttr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannelNum < 32);
+ ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
+ UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0);
+
+ //
+ // Clear the useburst bit for this channel if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_USEBURST)
+ {
+ HWREG(UDMA_USEBURSTCLR) = 1 << ulChannelNum;
+ }
+
+ //
+ // Clear the alternate control select bit for this channel, if set in
+ // ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_ALTSELECT)
+ {
+ HWREG(UDMA_ALTCLR) = 1 << ulChannelNum;
+ }
+
+ //
+ // Clear the high priority bit for this channel, if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_HIGH_PRIORITY)
+ {
+ HWREG(UDMA_PRIOCLR) = 1 << ulChannelNum;
+ }
+
+ //
+ // Clear the request mask bit for this channel, if set in ulConfig.
+ //
+ if(ulAttr & UDMA_ATTR_REQMASK)
+ {
+ HWREG(UDMA_REQMASKCLR) = 1 << ulChannelNum;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the enabled attributes of a uDMA channel.
+//!
+//! \param ulChannelNum is the channel to configure.
+//!
+//! This function returns a combination of flags representing the attributes of
+//! the uDMA channel.
+//!
+//! \return Returns the logical OR of the attributes of the uDMA channel, which
+//! can be any of the following:
+//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst
+//! mode.
+//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure
+//! for this channel.
+//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority.
+//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the
+//! peripheral for this channel.
+//
+//*****************************************************************************
+unsigned long
+uDMAChannelAttributeGet(unsigned long ulChannelNum)
+{
+ unsigned long ulAttr = 0;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannelNum < 32);
+
+ //
+ // Check to see if useburst bit is set for this channel.
+ //
+ if(HWREG(UDMA_USEBURSTSET) & (1 << ulChannelNum))
+ {
+ ulAttr |= UDMA_ATTR_USEBURST;
+ }
+
+ //
+ // Check to see if the alternate control bit is set for this channel.
+ //
+ if(HWREG(UDMA_ALTSET) & (1 << ulChannelNum))
+ {
+ ulAttr |= UDMA_ATTR_ALTSELECT;
+ }
+
+ //
+ // Check to see if the high priority bit is set for this channel.
+ //
+ if(HWREG(UDMA_PRIOSET) & (1 << ulChannelNum))
+ {
+ ulAttr |= UDMA_ATTR_HIGH_PRIORITY;
+ }
+
+ //
+ // Check to see if the request mask bit is set for this channel.
+ //
+ if(HWREG(UDMA_REQMASKSET) & (1 << ulChannelNum))
+ {
+ ulAttr |= UDMA_ATTR_REQMASK;
+ }
+
+ //
+ // Return the configuration flags.
+ //
+ return(ulAttr);
+}
+
+//*****************************************************************************
+//
+//! Sets the control parameters for a uDMA channel control structure.
+//!
+//! \param ulChannelStructIndex is the logical OR of the uDMA channel number
+//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//! \param ulControl is logical OR of several control values to set the control
+//! parameters for the channel.
+//!
+//! This function is used to set control parameters for a uDMA transfer. These
+//! are typically parameters that are not changed often.
+//!
+//! The \e ulChannelStructIndex parameter should be the logical OR of the
+//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to
+//! choose whether the primary or alternate data structure is used.
+//!
+//! The \e ulControl parameter is the logical OR of five values: the data size,
+//! the source address increment, the destination address increment, the
+//! arbitration size, and the use burst flag. The choices available for each
+//! of these values is described below.
+//!
+//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or
+//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits.
+//!
+//! Choose the source address increment from one of \b UDMA_SRC_INC_8,
+//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select
+//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or
+//! to select non-incrementing.
+//!
+//! Choose the destination address increment from one of \b UDMA_DST_INC_8,
+//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select
+//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or
+//! to select non-incrementing.
+//!
+//! The arbitration size determines how many items are transferred before
+//! the uDMA controller re-arbitrates for the bus. Choose the arbitration size
+//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8,
+//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024
+//! items, in powers of 2.
+//!
+//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only
+//! respond to burst requests at the tail end of a scatter-gather transfer.
+//!
+//! \note The address increment cannot be smaller than the data size.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelControlSet(unsigned long ulChannelStructIndex,
+ unsigned long ulControl)
+{
+ tDMAControlTable *pCtl;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannelStructIndex < 64);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+ //
+ // Get the base address of the control table.
+ //
+ pCtl = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get the current control word value and mask off the fields to be
+ // changed, then OR in the new settings.
+ //
+ pCtl[ulChannelStructIndex].ulControl =
+ ((pCtl[ulChannelStructIndex].ulControl &
+ ~(UDMA_CHCTL_DSTINC_M |
+ UDMA_CHCTL_DSTSIZE_M |
+ UDMA_CHCTL_SRCINC_M |
+ UDMA_CHCTL_SRCSIZE_M |
+ UDMA_CHCTL_ARBSIZE_M |
+ UDMA_CHCTL_NXTUSEBURST)) |
+ ulControl);
+}
+
+//*****************************************************************************
+//
+//! Sets the transfer parameters for a uDMA channel control structure.
+//!
+//! \param ulChannelStructIndex is the logical OR of the uDMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//! \param ulMode is the type of uDMA transfer.
+//! \param pvSrcAddr is the source address for the transfer.
+//! \param pvDstAddr is the destination address for the transfer.
+//! \param ulTransferSize is the number of data items to transfer.
+//!
+//! This function is used to set the parameters for a uDMA transfer. These are
+//! typically parameters that are changed often. The function
+//! uDMAChannelControlSet() MUST be called at least once for this channel prior
+//! to calling this function.
+//!
+//! The \e ulChannelStructIndex parameter should be the logical OR of the
+//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to
+//! choose whether the primary or alternate data structure is used.
+//!
+//! The \e ulMode parameter should be one of the following values:
+//!
+//! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode
+//! to this value at the end of a transfer.
+//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request.
+//! - \b UDMA_MODE_AUTO to perform a transfer that will always complete once
+//! started even if request is removed.
+//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the
+//! primary and alternate control structures for the channel. This allows
+//! use of ping-pong buffering for uDMA transfers.
+//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather
+//! transfer.
+//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather
+//! transfer.
+//!
+//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first
+//! location of the data to be transferred. These addresses should be aligned
+//! according to the item size. The compiler will take care of this if the
+//! pointers are pointing to storage of the appropriate data type.
+//!
+//! The \e ulTransferSize parameter is the number of data items, not the number
+//! of bytes.
+//!
+//! The two scatter/gather modes, memory and peripheral, are actually different
+//! depending on whether the primary or alternate control structure is
+//! selected. This function will look for the \b UDMA_PRI_SELECT and
+//! \b UDMA_ALT_SELECT flag along with the channel number and will set the
+//! scatter/gather mode as appropriate for the primary or alternate control
+//! structure.
+//!
+//! The channel must also be enabled using uDMAChannelEnable() after calling
+//! this function. The transfer will not begin until the channel has been set
+//! up and enabled. Note that the channel is automatically disabled after the
+//! transfer is completed, meaning that uDMAChannelEnable() must be called
+//! again after setting up the next transfer.
+//!
+//! \note Great care must be taken to not modify a channel control structure
+//! that is in use or else the results will be unpredictable, including the
+//! possibility of undesired data transfers to or from memory or peripherals.
+//! For BASIC and AUTO modes, it is safe to make changes when the channel is
+//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For
+//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the
+//! primary or alternate control structure only when the other is being used.
+//! The uDMAChannelModeGet() function will return \b UDMA_MODE_STOP when a
+//! channel control structure is inactive and safe to modify.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelTransferSet(unsigned long ulChannelStructIndex,
+ unsigned long ulMode, void *pvSrcAddr, void *pvDstAddr,
+ unsigned long ulTransferSize)
+{
+ tDMAControlTable *pControlTable;
+ unsigned long ulControl;
+ unsigned long ulInc;
+ unsigned long ulBufferBytes;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannelStructIndex < 64);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+ ASSERT(ulMode <= UDMA_MODE_PER_SCATTER_GATHER);
+ ASSERT((unsigned long)pvSrcAddr >= 0x20000000);
+ ASSERT((unsigned long)pvDstAddr >= 0x20000000);
+ ASSERT((ulTransferSize != 0) && (ulTransferSize <= 1024));
+
+ //
+ // Get the base address of the control table.
+ //
+ pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get the current control word value and mask off the mode and size
+ // fields.
+ //
+ ulControl = (pControlTable[ulChannelStructIndex].ulControl &
+ ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+ //
+ // Adjust the mode if the alt control structure is selected.
+ //
+ if(ulChannelStructIndex & UDMA_ALT_SELECT)
+ {
+ if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) ||
+ (ulMode == UDMA_MODE_PER_SCATTER_GATHER))
+ {
+ ulMode |= UDMA_MODE_ALT_SELECT;
+ }
+ }
+
+ //
+ // Set the transfer size and mode in the control word (but don't write the
+ // control word yet as it could kick off a transfer).
+ //
+ ulControl |= ulMode | ((ulTransferSize - 1) << 4);
+
+ //
+ // Get the address increment value for the source, from the control word.
+ //
+ ulInc = (ulControl & UDMA_CHCTL_SRCINC_M);
+
+ //
+ // Compute the ending source address of the transfer. If the source
+ // increment is set to none, then the ending address is the same as the
+ // beginning.
+ //
+ if(ulInc != UDMA_SRC_INC_NONE)
+ {
+ ulInc = ulInc >> 26;
+ ulBufferBytes = ulTransferSize << ulInc;
+ pvSrcAddr = (void *)((unsigned long)pvSrcAddr + ulBufferBytes - 1);
+ }
+
+ //
+ // Load the source ending address into the control block.
+ //
+ pControlTable[ulChannelStructIndex].pvSrcEndAddr = pvSrcAddr;
+
+ //
+ // Get the address increment value for the destination, from the control
+ // word.
+ //
+ ulInc = ulControl & UDMA_CHCTL_DSTINC_M;
+
+ //
+ // Compute the ending destination address of the transfer. If the
+ // destination increment is set to none, then the ending address is the
+ // same as the beginning.
+ //
+ if(ulInc != UDMA_DST_INC_NONE)
+ {
+ //
+ // There is a special case if this is setting up a scatter-gather
+ // transfer. The destination pointer needs to point to the end of
+ // the alternate structure for this channel instead of calculating
+ // the end of the buffer in the normal way.
+ //
+ if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) ||
+ (ulMode == UDMA_MODE_PER_SCATTER_GATHER))
+ {
+ pvDstAddr =
+ (void *)&pControlTable[ulChannelStructIndex |
+ UDMA_ALT_SELECT].ulSpare;
+ }
+ //
+ // Not a scatter-gather transfer, calculate end pointer normally.
+ //
+ else
+ {
+ ulInc = ulInc >> 30;
+ ulBufferBytes = ulTransferSize << ulInc;
+ pvDstAddr = (void *)((unsigned long)pvDstAddr + ulBufferBytes - 1);
+ }
+ }
+
+ //
+ // Load the destination ending address into the control block.
+ //
+ pControlTable[ulChannelStructIndex].pvDstEndAddr = pvDstAddr;
+
+ //
+ // Write the new control word value.
+ //
+ pControlTable[ulChannelStructIndex].ulControl = ulControl;
+}
+
+//*****************************************************************************
+//
+//! Configures a uDMA channel for scatter-gather mode.
+//!
+//! \param ulChannelNum is the uDMA channel number.
+//! \param ulTaskCount is the number of scatter-gather tasks to execute.
+//! \param pvTaskList is a pointer to the beginning of the scatter-gather
+//! task list.
+//! \param ulIsPeriphSG is a flag to indicate it is a peripheral scatter-gather
+//! transfer (else it will be memory scatter-gather transfer)
+//!
+//! This function is used to configure a channel for scatter-gather mode.
+//! The caller must have already set up a task list, and pass a pointer to
+//! the start of the task list as the \e pvTaskList parameter. The
+//! \e ulTaskCount parameter is the count of tasks in the task list, not the
+//! size of the task list. The flag \e bIsPeriphSG should be used to indicate
+//! if the scatter-gather should be configured for a peripheral or memory
+//! scatter-gather operation.
+//!
+//! \sa uDMATaskStructEntry
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelScatterGatherSet(unsigned long ulChannelNum, unsigned ulTaskCount,
+ void *pvTaskList, unsigned long ulIsPeriphSG)
+{
+ tDMAControlTable *pControlTable;
+ tDMAControlTable *pTaskTable;
+
+ //
+ // Check the parameters
+ //
+ ASSERT(ulChannelNum < 32);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+ ASSERT(pvTaskList != 0);
+ ASSERT(ulTaskCount <= 1024);
+ ASSERT(ulTaskCount != 0);
+
+ //
+ // Get the base address of the control table.
+ //
+ pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get a handy pointer to the task list
+ //
+ pTaskTable = (tDMAControlTable *)pvTaskList;
+
+ //
+ // Compute the ending address for the source pointer. This will be the
+ // last element of the last task in the task table
+ //
+ pControlTable[ulChannelNum].pvSrcEndAddr =
+ &pTaskTable[ulTaskCount - 1].ulSpare;
+
+ //
+ // Compute the ending address for the destination pointer. This will be
+ // the end of the alternate structure for this channel.
+ //
+ pControlTable[ulChannelNum].pvDstEndAddr =
+ &pControlTable[ulChannelNum | UDMA_ALT_SELECT].ulSpare;
+
+ //
+ // Compute the control word. Most configurable items are fixed for
+ // scatter-gather. Item and increment sizes are all 32-bit and arb
+ // size must be 4. The count is the number of items in the task list
+ // times 4 (4 words per task).
+ //
+ pControlTable[ulChannelNum].ulControl =
+ (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 |
+ UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 |
+ UDMA_CHCTL_ARBSIZE_4 |
+ (((ulTaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) |
+ (ulIsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG :
+ UDMA_CHCTL_XFERMODE_MEM_SG));
+}
+
+//*****************************************************************************
+//
+//! Gets the current transfer size for a uDMA channel control structure.
+//!
+//! \param ulChannelStructIndex is the logical OR of the uDMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//!
+//! This function is used to get the uDMA transfer size for a channel. The
+//! transfer size is the number of items to transfer, where the size of an item
+//! might be 8, 16, or 32 bits. If a partial transfer has already occurred,
+//! then the number of remaining items will be returned. If the transfer is
+//! complete, then 0 will be returned.
+//!
+//! \return Returns the number of items remaining to transfer.
+//
+//*****************************************************************************
+unsigned long
+uDMAChannelSizeGet(unsigned long ulChannelStructIndex)
+{
+ tDMAControlTable *pControlTable;
+ unsigned long ulControl;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannelStructIndex < 64);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+ //
+ // Get the base address of the control table.
+ //
+ pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get the current control word value and mask off all but the size field
+ // and the mode field.
+ //
+ ulControl = (pControlTable[ulChannelStructIndex].ulControl &
+ (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M));
+
+ //
+ // If the size field and mode field are 0 then the transfer is finished
+ // and there are no more items to transfer
+ //
+ if(ulControl == 0)
+ {
+ return(0);
+ }
+
+ //
+ // Otherwise, if either the size field or more field is non-zero, then
+ // not all the items have been transferred.
+ //
+ else
+ {
+ //
+ // Shift the size field and add one, then return to user.
+ //
+ return((ulControl >> 4) + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the transfer mode for a uDMA channel control structure.
+//!
+//! \param ulChannelStructIndex is the logical OR of the uDMA channel number
+//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT.
+//!
+//! This function is used to get the transfer mode for the uDMA channel. It
+//! can be used to query the status of a transfer on a channel. When the
+//! transfer is complete the mode will be \b UDMA_MODE_STOP.
+//!
+//! \return Returns the transfer mode of the specified channel and control
+//! structure, which will be one of the following values: \b UDMA_MODE_STOP,
+//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG,
+//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER.
+//
+//*****************************************************************************
+unsigned long
+uDMAChannelModeGet(unsigned long ulChannelStructIndex)
+{
+ tDMAControlTable *pControlTable;
+ unsigned long ulControl;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulChannelStructIndex < 64);
+ ASSERT(HWREG(UDMA_CTLBASE) != 0);
+
+ //
+ // Get the base address of the control table.
+ //
+ pControlTable = (tDMAControlTable *)HWREG(UDMA_CTLBASE);
+
+ //
+ // Get the current control word value and mask off all but the mode field.
+ //
+ ulControl = (pControlTable[ulChannelStructIndex].ulControl &
+ UDMA_CHCTL_XFERMODE_M);
+
+ //
+ // Check if scatter/gather mode, and if so, mask off the alt bit.
+ //
+ if(((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) ||
+ ((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER))
+ {
+ ulControl &= ~UDMA_MODE_ALT_SELECT;
+ }
+
+ //
+ // Return the mode to the caller.
+ //
+ return(ulControl);
+}
+
+//*****************************************************************************
+//
+//! Selects the secondary peripheral for a set of uDMA channels.
+//!
+//! \param ulSecPeriphs is the logical or of the uDMA channels for which to
+//! use the secondary peripheral, instead of the default peripheral.
+//!
+//! This function is used to select the secondary peripheral assignment for
+//! a set of uDMA channels. By selecting the secondary peripheral assignment
+//! for a channel, the default peripheral assignment is no longer available
+//! for that channel.
+//!
+//! The parameter \e ulSecPeriphs can be the logical OR of any of the
+//! following macros. If one of the macros below is in the list passed
+//! to this function, then the secondary peripheral (marked as \b _SEC_)
+//! will be selected.
+//!
+//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX
+//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX
+//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A
+//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B
+//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A
+//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B
+//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A
+//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B
+//! - \b UDMA_DEF_UART0RX_SEC_UART1RX
+//! - \b UDMA_DEF_UART0TX_SEC_UART1TX
+//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX
+//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2RX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2TX
+//! - \b UDMA_DEF_ADC00_SEC_TMR2A
+//! - \b UDMA_DEF_ADC01_SEC_TMR2B
+//! - \b UDMA_DEF_ADC02_SEC_RESERVED
+//! - \b UDMA_DEF_ADC03_SEC_RESERVED
+//! - \b UDMA_DEF_TMR0A_SEC_TMR1A
+//! - \b UDMA_DEF_TMR0B_SEC_TMR1B
+//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX
+//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX
+//! - \b UDMA_DEF_UART1RX_SEC_RESERVED
+//! - \b UDMA_DEF_UART1TX_SEC_RESERVED
+//! - \b UDMA_DEF_SSI1RX_SEC_ADC10
+//! - \b UDMA_DEF_SSI1TX_SEC_ADC11
+//! - \b UDMA_DEF_RESERVED_SEC_ADC12
+//! - \b UDMA_DEF_RESERVED_SEC_ADC13
+//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED
+//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelSelectSecondary(unsigned long ulSecPeriphs)
+{
+ //
+ // Select the secondary peripheral for the specified channels.
+ //
+ HWREG(UDMA_CHASGN) |= ulSecPeriphs;
+}
+
+//*****************************************************************************
+//
+//! Selects the default peripheral for a set of uDMA channels.
+//!
+//! \param ulDefPeriphs is the logical or of the uDMA channels for which to
+//! use the default peripheral, instead of the secondary peripheral.
+//!
+//! This function is used to select the default peripheral assignment for
+//! a set of uDMA channels.
+//!
+//! The parameter \e ulDefPeriphs can be the logical OR of any of the
+//! following macros. If one of the macros below is in the list passed
+//! to this function, then the default peripheral (marked as \b _DEF_)
+//! will be selected.
+//!
+//! - \b UDMA_DEF_USBEP1RX_SEC_UART2RX
+//! - \b UDMA_DEF_USBEP1TX_SEC_UART2TX
+//! - \b UDMA_DEF_USBEP2RX_SEC_TMR3A
+//! - \b UDMA_DEF_USBEP2TX_SEC_TMR3B
+//! - \b UDMA_DEF_USBEP3RX_SEC_TMR2A
+//! - \b UDMA_DEF_USBEP3TX_SEC_TMR2B
+//! - \b UDMA_DEF_ETH0RX_SEC_TMR2A
+//! - \b UDMA_DEF_ETH0TX_SEC_TMR2B
+//! - \b UDMA_DEF_UART0RX_SEC_UART1RX
+//! - \b UDMA_DEF_UART0TX_SEC_UART1TX
+//! - \b UDMA_DEF_SSI0RX_SEC_SSI1RX
+//! - \b UDMA_DEF_SSI0TX_SEC_SSI1TX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2RX
+//! - \b UDMA_DEF_RESERVED_SEC_UART2TX
+//! - \b UDMA_DEF_ADC00_SEC_TMR2A
+//! - \b UDMA_DEF_ADC01_SEC_TMR2B
+//! - \b UDMA_DEF_ADC02_SEC_RESERVED
+//! - \b UDMA_DEF_ADC03_SEC_RESERVED
+//! - \b UDMA_DEF_TMR0A_SEC_TMR1A
+//! - \b UDMA_DEF_TMR0B_SEC_TMR1B
+//! - \b UDMA_DEF_TMR1A_SEC_EPI0RX
+//! - \b UDMA_DEF_TMR1B_SEC_EPI0TX
+//! - \b UDMA_DEF_UART1RX_SEC_RESERVED
+//! - \b UDMA_DEF_UART1TX_SEC_RESERVED
+//! - \b UDMA_DEF_SSI1RX_SEC_ADC10
+//! - \b UDMA_DEF_SSI1TX_SEC_ADC11
+//! - \b UDMA_DEF_RESERVED_SEC_ADC12
+//! - \b UDMA_DEF_RESERVED_SEC_ADC13
+//! - \b UDMA_DEF_I2S0RX_SEC_RESERVED
+//! - \b UDMA_DEF_I2S0TX_SEC_RESERVED
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAChannelSelectDefault(unsigned long ulDefPeriphs)
+{
+ //
+ // Select the default peripheral for the specified channels.
+ //
+ HWREG(UDMA_CHASGN) &= ~ulDefPeriphs;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the uDMA controller.
+//!
+//! \param ulIntChannel identifies which uDMA interrupt is to be registered.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! This sets and enables the handler to be called when the uDMA controller
+//! generates an interrupt. The \e ulIntChannel parameter should be one of the
+//! following:
+//!
+//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts
+//! from the uDMA software channel (UDMA_CHANNEL_SW)
+//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error
+//! interrupts
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note The interrupt handler for uDMA is for transfer completion when the
+//! channel UDMA_CHANNEL_SW is used, and for error interrupts. The
+//! interrupts for each peripheral channel are handled through the individual
+//! peripheral interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(pfnHandler);
+ ASSERT((ulIntChannel == UDMA_INT_SW) || (ulIntChannel == UDMA_INT_ERR));
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulIntChannel, pfnHandler);
+
+ //
+ // Enable the memory management fault.
+ //
+ IntEnable(ulIntChannel);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the uDMA controller.
+//!
+//! \param ulIntChannel identifies which uDMA interrupt to unregister.
+//!
+//! This function will disable and clear the handler to be called for the
+//! specified uDMA interrupt. The \e ulIntChannel parameter should be one of
+//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function
+//! uDMAIntRegister().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+uDMAIntUnregister(unsigned long ulIntChannel)
+{
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulIntChannel);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulIntChannel);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/udma.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/udma.h
new file mode 100644
index 00000000..5a876fdb
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/udma.h
@@ -0,0 +1,442 @@
+//*****************************************************************************
+//
+// udma.h - Prototypes and macros for the uDMA controller.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __UDMA_H__
+#define __UDMA_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! \addtogroup udma_api
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// A structure that defines an entry in the channel control table. These
+// fields are used by the uDMA controller and normally it is not necessary for
+// software to directly read or write fields in the table.
+//
+//*****************************************************************************
+typedef struct
+{
+ //
+ // The ending source address of the data transfer.
+ //
+ volatile void *pvSrcEndAddr;
+
+ //
+ // The ending destination address of the data transfer.
+ //
+ volatile void *pvDstEndAddr;
+
+ //
+ // The channel control mode.
+ //
+ volatile unsigned long ulControl;
+
+ //
+ // An unused location.
+ //
+ volatile unsigned long ulSpare;
+}
+tDMAControlTable;
+
+//*****************************************************************************
+//
+//! A helper macro for building scatter-gather task table entries.
+//!
+//! \param ulTransferCount is the count of items to transfer for this task.
+//! \param ulItemSize is the bit size of the items to transfer for this task.
+//! \param ulSrcIncrement is the bit size increment for source data.
+//! \param pvSrcAddr is the starting address of the data to transfer.
+//! \param ulDstIncrement is the bit size increment for destination data.
+//! \param pvDstAddr is the starting address of the destination data.
+//! \param ulArbSize is the arbitration size to use for the transfer task.
+//! \param ulMode is the transfer mode for this task.
+//!
+//! This macro is intended to be used to help populate a table of uDMA tasks
+//! for a scatter-gather transfer. This macro will calculate the values for
+//! the fields of a task structure entry based on the input parameters.
+//!
+//! There are specific requirements for the values of each parameter. No
+//! checking is done so it is up to the caller to ensure that correct values
+//! are used for the parameters.
+//!
+//! The \e ulTransferCount parameter is the number of items that will be
+//! transferred by this task. It must be in the range 1-1024.
+//!
+//! The \e ulItemSize parameter is the bit size of the transfer data. It must
+//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
+//!
+//! The \e ulSrcIncrement parameter is the increment size for the source data.
+//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
+//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
+//!
+//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source
+//! data.
+//!
+//! The \e ulDstIncrement parameter is the increment size for the destination
+//! data. It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
+//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
+//!
+//! The \e pvDstAddr parameter is a void pointer to the beginning of the
+//! location where the data will be transferred.
+//!
+//! The \e ulArbSize parameter is the arbitration size for the transfer, and
+//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
+//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in
+//! powers of 2, from 1 to 1024.
+//!
+//! The \e ulMode parameter is the mode to use for this transfer task. It
+//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
+//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note
+//! that normally all tasks will be one of the scatter-gather modes while the
+//! last task is a task list will be AUTO or BASIC.
+//!
+//! This macro is intended to be used to initialize individual entries of
+//! a structure of tDMAControlTable type, like this:
+//!
+//! \verbatim
+//! tDMAControlTable MyTaskList[] =
+//! {
+//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
+//! UDMA_SRC_INC_8, MySourceBuf,
+//! UDMA_DST_INC_8, MyDestBuf,
+//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
+//! uDMATaskStructEntry(Task2Count, ... ),
+//! }
+//! \endverbatim
+//!
+//! \return Nothing; this is not a function.
+//
+//*****************************************************************************
+#define uDMATaskStructEntry(ulTransferCount, \
+ ulItemSize, \
+ ulSrcIncrement, \
+ pvSrcAddr, \
+ ulDstIncrement, \
+ pvDstAddr, \
+ ulArbSize, \
+ ulMode) \
+ { \
+ (((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \
+ ((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \
+ ((ulSrcIncrement) >> 26)) - 1]))), \
+ (((ulDstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \
+ ((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \
+ ((ulDstIncrement) >> 30)) - 1]))), \
+ (ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \
+ (((ulTransferCount) - 1) << 4) | \
+ ((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
+ ((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
+ (ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \
+ }
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Flags that can be passed to uDMAChannelAttributeEnable(),
+// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
+//
+//*****************************************************************************
+#define UDMA_ATTR_USEBURST 0x00000001
+#define UDMA_ATTR_ALTSELECT 0x00000002
+#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
+#define UDMA_ATTR_REQMASK 0x00000008
+#define UDMA_ATTR_ALL 0x0000000F
+
+//*****************************************************************************
+//
+// DMA control modes that can be passed to uDMAModeSet() and returned
+// uDMAModeGet().
+//
+//*****************************************************************************
+#define UDMA_MODE_STOP 0x00000000
+#define UDMA_MODE_BASIC 0x00000001
+#define UDMA_MODE_AUTO 0x00000002
+#define UDMA_MODE_PINGPONG 0x00000003
+#define UDMA_MODE_MEM_SCATTER_GATHER \
+ 0x00000004
+#define UDMA_MODE_PER_SCATTER_GATHER \
+ 0x00000006
+#define UDMA_MODE_ALT_SELECT 0x00000001
+
+//*****************************************************************************
+//
+// Channel configuration values that can be passed to uDMAControlSet().
+//
+//*****************************************************************************
+#define UDMA_DST_INC_8 0x00000000
+#define UDMA_DST_INC_16 0x40000000
+#define UDMA_DST_INC_32 0x80000000
+#define UDMA_DST_INC_NONE 0xc0000000
+#define UDMA_SRC_INC_8 0x00000000
+#define UDMA_SRC_INC_16 0x04000000
+#define UDMA_SRC_INC_32 0x08000000
+#define UDMA_SRC_INC_NONE 0x0c000000
+#define UDMA_SIZE_8 0x00000000
+#define UDMA_SIZE_16 0x11000000
+#define UDMA_SIZE_32 0x22000000
+#define UDMA_ARB_1 0x00000000
+#define UDMA_ARB_2 0x00004000
+#define UDMA_ARB_4 0x00008000
+#define UDMA_ARB_8 0x0000c000
+#define UDMA_ARB_16 0x00010000
+#define UDMA_ARB_32 0x00014000
+#define UDMA_ARB_64 0x00018000
+#define UDMA_ARB_128 0x0001c000
+#define UDMA_ARB_256 0x00020000
+#define UDMA_ARB_512 0x00024000
+#define UDMA_ARB_1024 0x00028000
+#define UDMA_NEXT_USEBURST 0x00000008
+
+//*****************************************************************************
+//
+// Channel numbers to be passed to API functions that require a channel number
+// ID.
+//
+//*****************************************************************************
+#define UDMA_CHANNEL_USBEP1RX 0
+#define UDMA_CHANNEL_USBEP1TX 1
+#define UDMA_CHANNEL_USBEP2RX 2
+#define UDMA_CHANNEL_USBEP2TX 3
+#define UDMA_CHANNEL_USBEP3RX 4
+#define UDMA_CHANNEL_USBEP3TX 5
+#define UDMA_CHANNEL_ETH0RX 6
+#define UDMA_CHANNEL_ETH0TX 7
+#define UDMA_CHANNEL_UART0RX 8
+#define UDMA_CHANNEL_UART0TX 9
+#define UDMA_CHANNEL_SSI0RX 10
+#define UDMA_CHANNEL_SSI0TX 11
+#define UDMA_CHANNEL_ADC0 14
+#define UDMA_CHANNEL_ADC1 15
+#define UDMA_CHANNEL_ADC2 16
+#define UDMA_CHANNEL_ADC3 17
+#define UDMA_CHANNEL_TMR0A 18
+#define UDMA_CHANNEL_TMR0B 19
+#define UDMA_CHANNEL_TMR1A 20
+#define UDMA_CHANNEL_TMR1B 21
+#define UDMA_CHANNEL_UART1RX 22
+#define UDMA_CHANNEL_UART1TX 23
+#define UDMA_CHANNEL_SSI1RX 24
+#define UDMA_CHANNEL_SSI1TX 25
+#define UDMA_CHANNEL_I2S0RX 28
+#define UDMA_CHANNEL_I2S0TX 29
+#define UDMA_CHANNEL_SW 30
+
+//*****************************************************************************
+//
+// Flags to be OR'd with the channel ID to indicate if the primary or alternate
+// control structure should be used.
+//
+//*****************************************************************************
+#define UDMA_PRI_SELECT 0x00000000
+#define UDMA_ALT_SELECT 0x00000020
+
+//*****************************************************************************
+//
+// uDMA interrupt sources, to be passed to uDMAIntRegister() and
+// uDMAIntUnregister().
+//
+//*****************************************************************************
+#define UDMA_INT_SW 62
+#define UDMA_INT_ERR 63
+
+//*****************************************************************************
+//
+// Channel numbers to be passed to API functions that require a channel number
+// ID. These are for secondary peripheral assignments.
+//
+//*****************************************************************************
+#define UDMA_SEC_CHANNEL_UART2RX_0 \
+ 0
+#define UDMA_SEC_CHANNEL_UART2TX_1 \
+ 1
+#define UDMA_SEC_CHANNEL_TMR3A 2
+#define UDMA_SEC_CHANNEL_TMR3B 3
+#define UDMA_SEC_CHANNEL_TMR2A_4 \
+ 4
+#define UDMA_SEC_CHANNEL_TMR2B_5 \
+ 5
+#define UDMA_SEC_CHANNEL_TMR2A_6 \
+ 6
+#define UDMA_SEC_CHANNEL_TMR2B_7 \
+ 7
+#define UDMA_SEC_CHANNEL_UART1RX \
+ 8
+#define UDMA_SEC_CHANNEL_UART1TX \
+ 9
+#define UDMA_SEC_CHANNEL_SSI1RX 10
+#define UDMA_SEC_CHANNEL_SSI1TX 11
+#define UDMA_SEC_CHANNEL_UART2RX_12 \
+ 12
+#define UDMA_SEC_CHANNEL_UART2TX_13 \
+ 13
+#define UDMA_SEC_CHANNEL_TMR2A_14 \
+ 14
+#define UDMA_SEC_CHANNEL_TMR2B_15 \
+ 15
+#define UDMA_SEC_CHANNEL_TMR1A 18
+#define UDMA_SEC_CHANNEL_TMR1B 19
+#define UDMA_SEC_CHANNEL_EPI0RX 20
+#define UDMA_SEC_CHANNEL_EPI0TX 21
+#define UDMA_SEC_CHANNEL_ADC10 24
+#define UDMA_SEC_CHANNEL_ADC11 25
+#define UDMA_SEC_CHANNEL_ADC12 26
+#define UDMA_SEC_CHANNEL_ADC13 27
+#define UDMA_SEC_CHANNEL_SW 30
+
+//*****************************************************************************
+//
+// uDMA default/secondary peripheral selections, to be passed to
+// uDMAChannelSelectSecondary() and uDMAChannelSelectDefault().
+//
+//*****************************************************************************
+#define UDMA_DEF_USBEP1RX_SEC_UART2RX \
+ 0x00000001
+#define UDMA_DEF_USBEP1TX_SEC_UART2TX \
+ 0x00000002
+#define UDMA_DEF_USBEP2RX_SEC_TMR3A \
+ 0x00000004
+#define UDMA_DEF_USBEP2TX_SEC_TMR3B \
+ 0x00000008
+#define UDMA_DEF_USBEP3RX_SEC_TMR2A \
+ 0x00000010
+#define UDMA_DEF_USBEP3TX_SEC_TMR2B \
+ 0x00000020
+#define UDMA_DEF_ETH0RX_SEC_TMR2A \
+ 0x00000040
+#define UDMA_DEF_ETH0TX_SEC_TMR2B \
+ 0x00000080
+#define UDMA_DEF_UART0RX_SEC_UART1RX \
+ 0x00000100
+#define UDMA_DEF_UART0TX_SEC_UART1TX \
+ 0x00000200
+#define UDMA_DEF_SSI0RX_SEC_SSI1RX \
+ 0x00000400
+#define UDMA_DEF_SSI0TX_SEC_SSI1TX \
+ 0x00000800
+#define UDMA_DEF_RESERVED_SEC_UART2RX \
+ 0x00001000
+#define UDMA_DEF_RESERVED_SEC_UART2TX \
+ 0x00002000
+#define UDMA_DEF_ADC00_SEC_TMR2A \
+ 0x00004000
+#define UDMA_DEF_ADC01_SEC_TMR2B \
+ 0x00008000
+#define UDMA_DEF_ADC02_SEC_RESERVED \
+ 0x00010000
+#define UDMA_DEF_ADC03_SEC_RESERVED \
+ 0x00020000
+#define UDMA_DEF_TMR0A_SEC_TMR1A \
+ 0x00040000
+#define UDMA_DEF_TMR0B_SEC_TMR1B \
+ 0x00080000
+#define UDMA_DEF_TMR1A_SEC_EPI0RX \
+ 0x00100000
+#define UDMA_DEF_TMR1B_SEC_EPI0TX \
+ 0x00200000
+#define UDMA_DEF_UART1RX_SEC_RESERVED \
+ 0x00400000
+#define UDMA_DEF_UART1TX_SEC_RESERVED \
+ 0x00800000
+#define UDMA_DEF_SSI1RX_SEC_ADC10 \
+ 0x01000000
+#define UDMA_DEF_SSI1TX_SEC_ADC11 \
+ 0x02000000
+#define UDMA_DEF_RESERVED_SEC_ADC12 \
+ 0x04000000
+#define UDMA_DEF_RESERVED_SEC_ADC13 \
+ 0x08000000
+#define UDMA_DEF_I2S0RX_SEC_RESERVED \
+ 0x10000000
+#define UDMA_DEF_I2S0TX_SEC_RESERVED \
+ 0x20000000
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void uDMAEnable(void);
+extern void uDMADisable(void);
+extern unsigned long uDMAErrorStatusGet(void);
+extern void uDMAErrorStatusClear(void);
+extern void uDMAChannelEnable(unsigned long ulChannelNum);
+extern void uDMAChannelDisable(unsigned long ulChannelNum);
+extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum);
+extern void uDMAControlBaseSet(void *pControlTable);
+extern void *uDMAControlBaseGet(void);
+extern void *uDMAControlAlternateBaseGet(void);
+extern void uDMAChannelRequest(unsigned long ulChannelNum);
+extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum,
+ unsigned long ulAttr);
+extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum,
+ unsigned long ulAttr);
+extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum);
+extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex,
+ unsigned long ulControl);
+extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex,
+ unsigned long ulMode, void *pvSrcAddr,
+ void *pvDstAddr,
+ unsigned long ulTransferSize);
+extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum,
+ unsigned ulTaskCount, void *pvTaskList,
+ unsigned long ulIsPeriphSG);
+extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex);
+extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex);
+extern void uDMAIntRegister(unsigned long ulIntChannel,
+ void (*pfnHandler)(void));
+extern void uDMAIntUnregister(unsigned long ulIntChannel);
+extern void uDMAChannelSelectDefault(unsigned long ulDefPeriphs);
+extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __UDMA_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/usb.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/usb.c
new file mode 100644
index 00000000..e8511711
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/usb.c
@@ -0,0 +1,3871 @@
+//*****************************************************************************
+//
+// usb.c - Driver for the USB Interface.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup usb_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_usb.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/udma.h"
+#include "driverlib/usb.h"
+
+//*****************************************************************************
+//
+// Amount to shift the RX interrupt sources by in the flags used in the
+// interrupt calls.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define USB_INT_RX_SHIFT 8
+#endif
+#define USB_INTEP_RX_SHIFT 16
+
+//*****************************************************************************
+//
+// Amount to shift the status interrupt sources by in the flags used in the
+// interrupt calls.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define USB_INT_STATUS_SHIFT 24
+#endif
+
+//*****************************************************************************
+//
+// Amount to shift the RX endpoint status sources by in the flags used in the
+// calls.
+//
+//*****************************************************************************
+#define USB_RX_EPSTATUS_SHIFT 16
+
+//*****************************************************************************
+//
+// Converts from an endpoint specifier to the offset of the endpoint's
+// control/status registers.
+//
+//*****************************************************************************
+#define EP_OFFSET(Endpoint) (Endpoint - 0x10)
+
+//*****************************************************************************
+//
+// Sets one of the indexed registers.
+//
+// \param ulBase specifies the USB module base address.
+// \param ulEndpoint is the endpoint index to target for this write.
+// \param ulIndexedReg is the indexed register to write to.
+// \param ucValue is the value to write to the register.
+//
+// This function is used to access the indexed registers for each endpoint.
+// The only registers that are indexed are the FIFO configuration registers
+// which are not used after configuration.
+//
+// \return None.
+//
+//*****************************************************************************
+static void
+USBIndexWrite(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulIndexedReg, unsigned long ulValue,
+ unsigned long ulSize)
+{
+ unsigned long ulIndex;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == 0) || (ulEndpoint == 1) || (ulEndpoint == 2) ||
+ (ulEndpoint == 3));
+ ASSERT((ulSize == 1) || (ulSize == 2));
+
+ //
+ // Save the old index in case it was in use.
+ //
+ ulIndex = HWREGB(ulBase + USB_O_EPIDX);
+
+ //
+ // Set the index.
+ //
+ HWREGB(ulBase + USB_O_EPIDX) = ulEndpoint;
+
+ //
+ // Determine the size of the register value.
+ //
+ if(ulSize == 1)
+ {
+ //
+ // Set the value.
+ //
+ HWREGB(ulBase + ulIndexedReg) = ulValue;
+ }
+ else
+ {
+ //
+ // Set the value.
+ //
+ HWREGH(ulBase + ulIndexedReg) = ulValue;
+ }
+
+ //
+ // Restore the old index in case it was in use.
+ //
+ HWREGB(ulBase + USB_O_EPIDX) = ulIndex;
+}
+
+//*****************************************************************************
+//
+// Reads one of the indexed registers.
+//
+// \param ulBase specifies the USB module base address.
+// \param ulEndpoint is the endpoint index to target for this write.
+// \param ulIndexedReg is the indexed register to write to.
+//
+// This function is used internally to access the indexed registers for each
+// endpoint. The only registers that are indexed are the FIFO configuration
+// registers which are not used after configuration.
+//
+// \return The value in the register requested.
+//
+//*****************************************************************************
+static unsigned long
+USBIndexRead(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulIndexedReg, unsigned long ulSize)
+{
+ unsigned char ulIndex;
+ unsigned char ulValue;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == 0) || (ulEndpoint == 1) || (ulEndpoint == 2) ||
+ (ulEndpoint == 3));
+ ASSERT((ulSize == 1) || (ulSize == 2));
+
+ //
+ // Save the old index in case it was in use.
+ //
+ ulIndex = HWREGB(ulBase + USB_O_EPIDX);
+
+ //
+ // Set the index.
+ //
+ HWREGB(ulBase + USB_O_EPIDX) = ulEndpoint;
+
+ //
+ // Determine the size of the register value.
+ //
+ if(ulSize == 1)
+ {
+ //
+ // Get the value.
+ //
+ ulValue = HWREGB(ulBase + ulIndexedReg);
+ }
+ else
+ {
+ //
+ // Get the value.
+ //
+ ulValue = HWREGH(ulBase + ulIndexedReg);
+ }
+
+ //
+ // Restore the old index in case it was in use.
+ //
+ HWREGB(ulBase + USB_O_EPIDX) = ulIndex;
+
+ //
+ // Return the register's value.
+ //
+ return(ulValue);
+}
+
+//*****************************************************************************
+//
+//! Puts the USB bus in a suspended state.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! When used in host mode, this function will put the USB bus in the suspended
+//! state.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostSuspend(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Send the suspend signaling to the USB bus.
+ //
+ HWREGB(ulBase + USB_O_POWER) |= USB_POWER_SUSPEND;
+}
+
+//*****************************************************************************
+//
+//! Handles the USB bus reset condition.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param bStart specifies whether to start or stop signaling reset on the USB
+//! bus.
+//!
+//! When this function is called with the \e bStart parameter set to \b true,
+//! this function will cause the start of a reset condition on the USB bus.
+//! The caller should then delay at least 20ms before calling this function
+//! again with the \e bStart parameter set to \b false.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostReset(unsigned long ulBase, tBoolean bStart)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Send a reset signal to the bus.
+ //
+ if(bStart)
+ {
+ HWREGB(ulBase + USB_O_POWER) |= USB_POWER_RESET;
+ }
+ else
+ {
+ HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_RESET;
+ }
+}
+
+//*****************************************************************************
+//
+//! Handles the USB bus resume condition.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param bStart specifies if the USB controller is entering or leaving the
+//! resume signaling state.
+//!
+//! When in device mode this function will bring the USB controller out of the
+//! suspend state. This call should first be made with the \e bStart parameter
+//! set to \b true to start resume signaling. The device application should
+//! then delay at least 10ms but not more than 15ms before calling this
+//! function with the \e bStart parameter set to \b false.
+//!
+//! When in host mode this function will signal devices to leave the suspend
+//! state. This call should first be made with the \e bStart parameter set to
+//! \b true to start resume signaling. The host application should then delay
+//! at least 20ms before calling this function with the \e bStart parameter set
+//! to \b false. This will cause the controller to complete the resume
+//! signaling on the USB bus.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostResume(unsigned long ulBase, tBoolean bStart)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Send a resume signal to the bus.
+ //
+ if(bStart)
+ {
+ HWREGB(ulBase + USB_O_POWER) |= USB_POWER_RESUME;
+ }
+ else
+ {
+ HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_RESUME;
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the current speed of the USB device connected.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will return the current speed of the USB bus.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return Returns either \b USB_LOW_SPEED, \b USB_FULL_SPEED, or
+//! \b USB_UNDEF_SPEED.
+//
+//*****************************************************************************
+unsigned long
+USBHostSpeedGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // If the Full Speed device bit is set, then this is a full speed device.
+ //
+ if(HWREGB(ulBase + USB_O_DEVCTL) & USB_DEVCTL_FSDEV)
+ {
+ return(USB_FULL_SPEED);
+ }
+
+ //
+ // If the Low Speed device bit is set, then this is a low speed device.
+ //
+ if(HWREGB(ulBase + USB_O_DEVCTL) & USB_DEVCTL_LSDEV)
+ {
+ return(USB_LOW_SPEED);
+ }
+
+ //
+ // The device speed is not known.
+ //
+ return(USB_UNDEF_SPEED);
+}
+
+//*****************************************************************************
+//
+//! Returns the status of the USB interrupts.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will read the source of the interrupt for the USB controller.
+//! There are three groups of interrupt sources, IN Endpoints, OUT Endpoints,
+//! and general status changes. This call will return the current status for
+//! all of these interrupts. The bit values returned should be compared
+//! against the \b USB_HOST_IN, \b USB_HOST_OUT, \b USB_HOST_EP0,
+//! \b USB_DEV_IN, \b USB_DEV_OUT, and \b USB_DEV_EP0 values.
+//!
+//! \note This call will clear the source of all of the general status
+//! interrupts.
+//!
+//! \note WARNING: This API cannot be used on endpoint numbers greater than
+//! endpoint 3 so USBIntStatusControl() or USBIntStatusEndpoint() should be
+//! used instead.
+//!
+//! \return Returns the status of the sources for the USB controller's
+//! interrupt.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+unsigned long
+USBIntStatus(unsigned long ulBase)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Get the transmit interrupt status.
+ //
+ ulStatus = (HWREGB(ulBase + USB_O_TXIS));
+
+ //
+ // Get the receive interrupt status, these bits go into the second byte of
+ // the returned value.
+ //
+ ulStatus |= (HWREGB(ulBase + USB_O_RXIS) << USB_INT_RX_SHIFT);
+
+ //
+ // Get the general interrupt status, these bits go into the upper 8 bits
+ // of the returned value.
+ //
+ ulStatus |= (HWREGB(ulBase + USB_O_IS) << USB_INT_STATUS_SHIFT);
+
+ //
+ // Add the power fault status.
+ //
+ if(HWREG(ulBase + USB_O_EPCISC) & USB_EPCISC_PF)
+ {
+ //
+ // Indicate a power fault was detected.
+ //
+ ulStatus |= USB_INT_POWER_FAULT;
+
+ //
+ // Clear the power fault interrupt.
+ //
+ HWREGB(ulBase + USB_O_EPCISC) |= USB_EPCISC_PF;
+ }
+
+ if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID)
+ {
+ //
+ // Indicate a id detection was detected.
+ //
+ ulStatus |= USB_INT_MODE_DETECT;
+
+ //
+ // Clear the id detection interrupt.
+ //
+ HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID;
+ }
+
+ //
+ // Return the combined interrupt status.
+ //
+ return(ulStatus);
+}
+#endif
+
+//*****************************************************************************
+//
+//! Disables the sources for USB interrupts.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which interrupts to disable.
+//!
+//! This function will disable the USB controller from generating the
+//! interrupts indicated by the \e ulFlags parameter. There are three groups
+//! of interrupt sources, IN Endpoints, OUT Endpoints, and general status
+//! changes, specified by \b USB_INT_HOST_IN, \b USB_INT_HOST_OUT,
+//! \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and \b USB_INT_STATUS. If
+//! \b USB_INT_ALL is specified then all interrupts will be disabled.
+//!
+//! \note WARNING: This API cannot be used on endpoint numbers greater than
+//! endpoint 3 so USBIntDisableControl() or USBIntDisableEndpoint() should be
+//! used instead.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+void
+USBIntDisable(unsigned long ulBase, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulFlags & ~(USB_INT_ALL)) == 0);
+
+ //
+ // If any transmit interrupts were disabled then write the transmit
+ // interrupt settings out to the hardware.
+ //
+ if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0))
+ {
+ HWREGH(ulBase + USB_O_TXIE) &=
+ ~(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0));
+ }
+
+ //
+ // If any receive interrupts were disabled then write the receive interrupt
+ // settings out to the hardware.
+ //
+ if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT))
+ {
+ HWREGH(ulBase + USB_O_RXIE) &=
+ ~((ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) >>
+ USB_INT_RX_SHIFT);
+ }
+
+ //
+ // If any general interrupts were disabled then write the general interrupt
+ // settings out to the hardware.
+ //
+ if(ulFlags & USB_INT_STATUS)
+ {
+ HWREGB(ulBase + USB_O_IE) &=
+ ~((ulFlags & USB_INT_STATUS) >> USB_INT_STATUS_SHIFT);
+ }
+
+ //
+ // Disable the power fault interrupt.
+ //
+ if(ulFlags & USB_INT_POWER_FAULT)
+ {
+ HWREG(ulBase + USB_O_EPCIM) = 0;
+ }
+
+ //
+ // Disable the ID pin detect interrupt.
+ //
+ if(ulFlags & USB_INT_MODE_DETECT)
+ {
+ HWREG(USB0_BASE + USB_O_IDVIM) = 0;
+ }
+}
+#endif
+
+//*****************************************************************************
+//
+//! Enables the sources for USB interrupts.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which interrupts to enable.
+//!
+//! This function will enable the USB controller's ability to generate the
+//! interrupts indicated by the \e ulFlags parameter. There are three
+//! groups of interrupt sources, IN Endpoints, OUT Endpoints, and
+//! general status changes, specified by \b USB_INT_HOST_IN,
+//! \b USB_INT_HOST_OUT, \b USB_INT_DEV_IN, \b USB_INT_DEV_OUT, and
+//! \b USB_STATUS. If \b USB_INT_ALL is specified then all interrupts will be
+//! enabled.
+//!
+//! \note A call must be made to enable the interrupt in the main interrupt
+//! controller to receive interrupts. The USBIntRegister() API performs this
+//! controller level interrupt enable. However if static interrupt handlers
+//! are used then then a call to IntEnable() must be made in order to allow any
+//! USB interrupts to occur.
+//!
+//! \note WARNING: This API cannot be used on endpoint numbers greater than
+//! endpoint 3 so USBIntEnableControl() or USBIntEnableEndpoint() should be
+//! used instead.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+void
+USBIntEnable(unsigned long ulBase, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulFlags & (~USB_INT_ALL)) == 0);
+
+ //
+ // If any transmit interrupts were enabled then write the transmit
+ // interrupt settings out to the hardware.
+ //
+ if(ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0))
+ {
+ HWREGH(ulBase + USB_O_TXIE) |=
+ ulFlags & (USB_INT_HOST_OUT | USB_INT_DEV_IN | USB_INT_EP0);
+ }
+
+ //
+ // If any receive interrupts were enabled then write the receive interrupt
+ // settings out to the hardware.
+ //
+ if(ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT))
+ {
+ HWREGH(ulBase + USB_O_RXIE) |=
+ ((ulFlags & (USB_INT_HOST_IN | USB_INT_DEV_OUT)) >>
+ USB_INT_RX_SHIFT);
+ }
+
+ //
+ // If any general interrupts were enabled then write the general interrupt
+ // settings out to the hardware.
+ //
+ if(ulFlags & USB_INT_STATUS)
+ {
+ HWREGB(ulBase + USB_O_IE) |=
+ (ulFlags & USB_INT_STATUS) >> USB_INT_STATUS_SHIFT;
+ }
+
+ //
+ // Enable the power fault interrupt.
+ //
+ if(ulFlags & USB_INT_POWER_FAULT)
+ {
+ HWREG(ulBase + USB_O_EPCIM) = USB_EPCIM_PF;
+ }
+
+ //
+ // Enable the ID pin detect interrupt.
+ //
+ if(ulFlags & USB_INT_MODE_DETECT)
+ {
+ HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID;
+ }
+}
+#endif
+
+//*****************************************************************************
+//
+//! Disable control interrupts on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which control interrupts to disable.
+//!
+//! This function will disable the control interrupts for the USB controller
+//! specified by the \e ulBase parameter. The \e ulFlags parameter specifies
+//! which control interrupts to disable. The flags passed in the \e ulFlags
+//! parameters should be the definitions that start with \b USB_INTCTRL_* and
+//! not any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntDisableControl(unsigned long ulBase, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulFlags & ~(USB_INTCTRL_ALL)) == 0);
+
+ //
+ // If any general interrupts were disabled then write the general interrupt
+ // settings out to the hardware.
+ //
+ if(ulFlags & USB_INTCTRL_STATUS)
+ {
+ HWREGB(ulBase + USB_O_IE) &= ~(ulFlags & USB_INTCTRL_STATUS);
+ }
+
+ //
+ // Disable the power fault interrupt.
+ //
+ if(ulFlags & USB_INTCTRL_POWER_FAULT)
+ {
+ HWREG(ulBase + USB_O_EPCIM) = 0;
+ }
+
+ //
+ // Disable the ID pin detect interrupt.
+ //
+ if(ulFlags & USB_INTCTRL_MODE_DETECT)
+ {
+ HWREG(USB0_BASE + USB_O_IDVIM) = 0;
+ }
+}
+
+//*****************************************************************************
+//
+//! Enable control interrupts on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which control interrupts to enable.
+//!
+//! This function will enable the control interrupts for the USB controller
+//! specified by the \e ulBase parameter. The \e ulFlags parameter specifies
+//! which control interrupts to enable. The flags passed in the \e ulFlags
+//! parameters should be the definitions that start with \b USB_INTCTRL_* and
+//! not any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntEnableControl(unsigned long ulBase, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulFlags & (~USB_INTCTRL_ALL)) == 0);
+
+ //
+ // If any general interrupts were enabled then write the general interrupt
+ // settings out to the hardware.
+ //
+ if(ulFlags & USB_INTCTRL_STATUS)
+ {
+ HWREGB(ulBase + USB_O_IE) |= ulFlags;
+ }
+
+ //
+ // Enable the power fault interrupt.
+ //
+ if(ulFlags & USB_INTCTRL_POWER_FAULT)
+ {
+ HWREG(ulBase + USB_O_EPCIM) = USB_EPCIM_PF;
+ }
+
+ //
+ // Enable the ID pin detect interrupt.
+ //
+ if(ulFlags & USB_INTCTRL_MODE_DETECT)
+ {
+ HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID;
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the control interrupt status on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will read control interrupt status for a USB controller.
+//! This call will return the current status for control interrupts only, the
+//! endpoint interrupt status is retrieved by calling USBIntStatusEndpoint().
+//! The bit values returned should be compared against the \b USB_INTCTRL_*
+//! values.
+//!
+//! The following are the meanings of all \b USB_INCTRL_ flags and the modes
+//! for which they are valid. These values apply to any calls to
+//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableConrol().
+//! Some of these flags are only valid in the following modes as indicated in
+//! the parenthesis: Host, Device, and OTG.
+//!
+//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources.
+//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only).
+//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable
+//! (OTG Only).
+//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only)
+//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only)
+//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only)
+//! - \b USB_INTCTRL_SOF - Start of Frame Detected.
+//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past
+//! the end of a frame. (Host Only)
+//! - \b USB_INTCTRL_RESET - Reset signaling detected by device. (Device Only)
+//! - \b USB_INTCTRL_RESUME - Resume signaling detected.
+//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device
+//! Only)
+//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed
+//! (OTG Only)
+//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected. (Host Only)
+//!
+//! \note This call will clear the source of all of the control status
+//! interrupts.
+//!
+//! \return Returns the status of the control interrupts for a USB controller.
+//
+//*****************************************************************************
+unsigned long
+USBIntStatusControl(unsigned long ulBase)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Get the general interrupt status, these bits go into the upper 8 bits
+ // of the returned value.
+ //
+ ulStatus = HWREGB(ulBase + USB_O_IS);
+
+ //
+ // Add the power fault status.
+ //
+ if(HWREG(ulBase + USB_O_EPCISC) & USB_EPCISC_PF)
+ {
+ //
+ // Indicate a power fault was detected.
+ //
+ ulStatus |= USB_INTCTRL_POWER_FAULT;
+
+ //
+ // Clear the power fault interrupt.
+ //
+ HWREGB(ulBase + USB_O_EPCISC) |= USB_EPCISC_PF;
+ }
+
+ if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID)
+ {
+ //
+ // Indicate a id detection was detected.
+ //
+ ulStatus |= USB_INTCTRL_MODE_DETECT;
+
+ //
+ // Clear the id detection interrupt.
+ //
+ HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID;
+ }
+
+ //
+ // Return the combined interrupt status.
+ //
+ return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Disable endpoint interrupts on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which endpoint interrupts to disable.
+//!
+//! This function will disable endpoint interrupts for the USB controller
+//! specified by the \e ulBase parameter. The \e ulFlags parameter specifies
+//! which endpoint interrupts to disable. The flags passed in the \e ulFlags
+//! parameters should be the definitions that start with \b USB_INTEP_* and not
+//! any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntDisableEndpoint(unsigned long ulBase, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // If any transmit interrupts were disabled then write the transmit
+ // interrupt settings out to the hardware.
+ //
+ HWREGH(ulBase + USB_O_TXIE) &=
+ ~(ulFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0));
+
+ //
+ // If any receive interrupts were disabled then write the receive interrupt
+ // settings out to the hardware.
+ //
+ HWREGH(ulBase + USB_O_RXIE) &=
+ ~((ulFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >>
+ USB_INTEP_RX_SHIFT);
+}
+
+//*****************************************************************************
+//
+//! Enable endpoint interrupts on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies which endpoint interrupts to enable.
+//!
+//! This function will enable endpoint interrupts for the USB controller
+//! specified by the \e ulBase parameter. The \e ulFlags parameter specifies
+//! which endpoint interrupts to enable. The flags passed in the \e ulFlags
+//! parameters should be the definitions that start with \b USB_INTEP_* and not
+//! any other \b USB_INT flags.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntEnableEndpoint(unsigned long ulBase, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Enable any transmit endpoint interrupts.
+ //
+ HWREGH(ulBase + USB_O_TXIE) |=
+ ulFlags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0);
+
+ //
+ // Enable any receive endpoint interrupts.
+ //
+ HWREGH(ulBase + USB_O_RXIE) |=
+ ((ulFlags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >>
+ USB_INTEP_RX_SHIFT);
+}
+
+//*****************************************************************************
+//
+//! Returns the endpoint interrupt status on a given USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will read endpoint interrupt status for a USB controller.
+//! This call will return the current status for endpoint interrupts only, the
+//! control interrupt status is retrieved by calling USBIntStatusControl().
+//! The bit values returned should be compared against the \b USB_INTEP_*
+//! values. These are grouped into classes for \b USB_INTEP_HOST_* and
+//! \b USB_INTEP_DEV_* values to handle both host and device modes with all
+//! endpoints.
+//!
+//! \note This call will clear the source of all of the endpoint interrupts.
+//!
+//! \return Returns the status of the endpoint interrupts for a USB controller.
+//
+//*****************************************************************************
+unsigned long
+USBIntStatusEndpoint(unsigned long ulBase)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Get the transmit interrupt status.
+ //
+ ulStatus = HWREGH(ulBase + USB_O_TXIS);
+
+ ulStatus |= (HWREGH(ulBase + USB_O_RXIS) << USB_INTEP_RX_SHIFT);
+
+ //
+ // Return the combined interrupt status.
+ //
+ return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param pfnHandler is a pointer to the function to be called when a USB
+//! interrupt occurs.
+//!
+//! This sets the handler to be called when a USB interrupt occurs. This will
+//! also enable the global USB interrupt in the interrupt controller. The
+//! specific desired USB interrupts must be enabled via a separate call to
+//! USBIntEnable(). It is the interrupt handler's responsibility to clear the
+//! interrupt sources via a calls to USBIntStatusControl() and
+//! USBIntStatusEndpoint().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_USB0, pfnHandler);
+
+ //
+ // Enable the USB interrupt.
+ //
+ IntEnable(INT_USB0);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the USB controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function unregister the interrupt handler. This function will also
+//! disable the USB interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering or
+//! unregistering interrupt handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_USB0);
+
+ //
+ // Disable the CAN interrupt.
+ //
+ IntDisable(INT_USB0);
+}
+
+//*****************************************************************************
+//
+//! Returns the current status of an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//!
+//! This function will return the status of a given endpoint. If any of these
+//! status bits need to be cleared, then these these values must be cleared by
+//! calling the USBDevEndpointStatusClear() or USBHostEndpointStatusClear()
+//! functions.
+//!
+//! The following are the status flags for host mode:
+//!
+//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint.
+//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request.
+//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint.
+//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN
+//! endpoint in Isochronous mode.
+//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than
+//! the specified timeout period.
+//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN
+//! endpoint.
+//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full.
+//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint.
+//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than
+//! the specified timeout period.
+//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT
+//! request.
+//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint.
+//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this
+//! OUT endpoint.
+//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty.
+//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not
+//! completed.
+//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the
+//! specified timeout period.
+//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on
+//! endpoint zero.
+//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an
+//! IN transaction.
+//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN
+//! transaction.
+//!
+//! The following are the status flags for device mode:
+//!
+//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint.
+//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT
+//! endpoint.
+//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO.
+//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full.
+//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT
+//! endpoint's FIFO.
+//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come.
+//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint.
+//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no
+//! data was ready.
+//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty.
+//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not
+//! completed.
+//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End
+//! condition was sent.
+//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero.
+//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not
+//! completed.
+//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint
+//! zero's OUT FIFO.
+//!
+//! \return The current status flags for the endpoint depending on mode.
+//
+//*****************************************************************************
+unsigned long
+USBEndpointStatus(unsigned long ulBase, unsigned long ulEndpoint)
+{
+ unsigned long ulStatus;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Get the TX portion of the endpoint status.
+ //
+ ulStatus = HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRL1);
+
+ //
+ // Get the RX portion of the endpoint status.
+ //
+ ulStatus |= ((HWREGH(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRL1)) <<
+ USB_RX_EPSTATUS_SHIFT);
+
+ //
+ // Return the endpoint status.
+ //
+ return(ulStatus);
+}
+
+//*****************************************************************************
+//
+//! Clears the status bits in this endpoint in host mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags are the status bits that will be cleared.
+//!
+//! This function will clear the status of any bits that are passed in the
+//! \e ulFlags parameter. The \e ulFlags parameter can take the value returned
+//! from the USBEndpointStatus() call.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Clear the specified flags for the endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ HWREGB(ulBase + USB_O_CSRL0) &= ~ulFlags;
+ }
+ else
+ {
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &= ~ulFlags;
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~(ulFlags >> USB_RX_EPSTATUS_SHIFT);
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the status bits in this endpoint in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags are the status bits that will be cleared.
+//!
+//! This function will clear the status of any bits that are passed in the
+//! \e ulFlags parameter. The \e ulFlags parameter can take the value returned
+//! from the USBEndpointStatus() call.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStatusClear(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // If this is endpoint 0 then the bits have different meaning and map into
+ // the TX memory location.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Set the Serviced RxPktRdy bit to clear the RxPktRdy.
+ //
+ if(ulFlags & USB_DEV_EP0_OUT_PKTRDY)
+ {
+ HWREGB(ulBase + USB_O_CSRL0) |= USB_CSRL0_RXRDYC;
+ }
+
+ //
+ // Set the serviced Setup End bit to clear the SetupEnd status.
+ //
+ if(ulFlags & USB_DEV_EP0_SETUP_END)
+ {
+ HWREGB(ulBase + USB_O_CSRL0) |= USB_CSRL0_SETENDC;
+ }
+
+ //
+ // Clear the Sent Stall status flag.
+ //
+ if(ulFlags & USB_DEV_EP0_SENT_STALL)
+ {
+ HWREGB(ulBase + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL);
+ }
+ }
+ else
+ {
+ //
+ // Clear out any TX flags that were passed in. Only
+ // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN should be cleared.
+ //
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~(ulFlags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN));
+
+ //
+ // Clear out valid RX flags that were passed in. Only
+ // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN
+ // should be cleared.
+ //
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~((ulFlags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR |
+ USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT);
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the value data toggle on an endpoint in host mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies the endpoint to reset the data toggle.
+//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1.
+//! \param ulFlags specifies whether to set the IN or OUT endpoint.
+//!
+//! This function is used to force the state of the data toggle in host mode.
+//! If the value passed in the \e bDataToggle parameter is \b false, then the
+//! data toggle will be set to the DATA0 state, and if it is \b true it will be
+//! set to the DATA1 state. The \e ulFlags parameter can be \b USB_EP_HOST_IN
+//! or \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The
+//! \e ulFlags parameter is ignored for endpoint zero.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointDataToggle(unsigned long ulBase, unsigned long ulEndpoint,
+ tBoolean bDataToggle, unsigned long ulFlags)
+{
+ unsigned long ulDataToggle;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // The data toggle defaults to DATA0.
+ //
+ ulDataToggle = 0;
+
+ //
+ // See if the data toggle should be set to DATA1.
+ //
+ if(bDataToggle)
+ {
+ //
+ // Select the data toggle bit based on the endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ ulDataToggle = USB_CSRH0_DT;
+ }
+ else if(ulFlags == USB_EP_HOST_IN)
+ {
+ ulDataToggle = USB_RXCSRH1_DT;
+ }
+ else
+ {
+ ulDataToggle = USB_TXCSRH1_DT;
+ }
+ }
+
+ //
+ // Set the data toggle based on the endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Set the write enable and the bit value for endpoint zero.
+ //
+ HWREGB(ulBase + USB_O_CSRH0) =
+ ((HWREGB(ulBase + USB_O_CSRH0) &
+ ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) |
+ (ulDataToggle | USB_CSRH0_DTWE));
+ }
+ else if(ulFlags == USB_EP_HOST_IN)
+ {
+ //
+ // Set the Write enable and the bit value for an IN endpoint.
+ //
+ HWREGB(ulBase + USB_O_RXCSRH1 + EP_OFFSET(ulEndpoint)) =
+ ((HWREGB(ulBase + USB_O_RXCSRH1 + EP_OFFSET(ulEndpoint)) &
+ ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) |
+ (ulDataToggle | USB_RXCSRH1_DTWE));
+ }
+ else
+ {
+ //
+ // Set the Write enable and the bit value for an OUT endpoint.
+ //
+ HWREGB(ulBase + USB_O_TXCSRH1 + EP_OFFSET(ulEndpoint)) =
+ ((HWREGB(ulBase + USB_O_TXCSRH1 + EP_OFFSET(ulEndpoint)) &
+ ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) |
+ (ulDataToggle | USB_TXCSRH1_DTWE));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the Data toggle on an endpoint to zero.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies the endpoint to reset the data toggle.
+//! \param ulFlags specifies whether to access the IN or OUT endpoint.
+//!
+//! This function will cause the controller to clear the data toggle for an
+//! endpoint. This call is not valid for endpoint zero and can be made with
+//! host or device controllers.
+//!
+//! The \e ulFlags parameter should be one of \b USB_EP_HOST_OUT,
+//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDataToggleClear(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+ (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+ (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+ (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+ (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+ (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+ (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+ (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the transmit or receive data toggle should be cleared.
+ //
+ if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+ {
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_TXCSRL1_CLRDT;
+ }
+ else
+ {
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_RXCSRL1_CLRDT;
+ }
+}
+
+//*****************************************************************************
+//
+//! Stalls the specified endpoint in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies the endpoint to stall.
+//! \param ulFlags specifies whether to stall the IN or OUT endpoint.
+//!
+//! This function will cause to endpoint number passed in to go into a stall
+//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall
+//! will be issued on the IN portion of this endpoint. If the \e ulFlags
+//! parameter is \b USB_EP_DEV_OUT then the stall will be issued on the OUT
+//! portion of this endpoint.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulFlags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0)
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Determine how to stall this endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Perform a stall on endpoint zero.
+ //
+ HWREGB(ulBase + USB_O_CSRL0) |=
+ (USB_CSRL0_STALL | USB_CSRL0_RXRDYC);
+ }
+ else if(ulFlags == USB_EP_DEV_IN)
+ {
+ //
+ // Perform a stall on an IN endpoint.
+ //
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_TXCSRL1_STALL;
+ }
+ else
+ {
+ //
+ // Perform a stall on an OUT endpoint.
+ //
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_RXCSRL1_STALL;
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the stall condition on the specified endpoint in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies which endpoint to remove the stall condition.
+//! \param ulFlags specifies whether to remove the stall condition from the IN
+//! or the OUT portion of this endpoint.
+//!
+//! This function will cause the endpoint number passed in to exit the stall
+//! condition. If the \e ulFlags parameter is \b USB_EP_DEV_IN then the stall
+//! will be cleared on the IN portion of this endpoint. If the \e ulFlags
+//! parameter is \b USB_EP_DEV_OUT then the stall will be cleared on the OUT
+//! portion of this endpoint.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointStallClear(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+ ASSERT((ulFlags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0)
+
+ //
+ // Determine how to clear the stall on this endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Clear the stall on endpoint zero.
+ //
+ HWREGB(ulBase + USB_O_CSRL0) &= ~USB_CSRL0_STALLED;
+ }
+ else if(ulFlags == USB_EP_DEV_IN)
+ {
+ //
+ // Clear the stall on an IN endpoint.
+ //
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED);
+
+ //
+ // Reset the data toggle.
+ //
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_TXCSRL1_CLRDT;
+ }
+ else
+ {
+ //
+ // Clear the stall on an OUT endpoint.
+ //
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);
+
+ //
+ // Reset the data toggle.
+ //
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_RXCSRL1_CLRDT;
+ }
+}
+
+//*****************************************************************************
+//
+//! Connects the USB controller to the bus in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will cause the soft connect feature of the USB controller to
+//! be enabled. Call USBDisconnect() to remove the USB device from the bus.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevConnect(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Enable connection to the USB bus.
+ //
+ HWREGB(ulBase + USB_O_POWER) |= USB_POWER_SOFTCONN;
+}
+
+//*****************************************************************************
+//
+//! Removes the USB controller from the bus in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will cause the soft connect feature of the USB controller to
+//! remove the device from the USB bus. A call to USBDevConnect() is needed to
+//! reconnect to the bus.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevDisconnect(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Disable connection to the USB bus.
+ //
+ HWREGB(ulBase + USB_O_POWER) &= (~USB_POWER_SOFTCONN);
+}
+
+//*****************************************************************************
+//
+//! Sets the address in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulAddress is the address to use for a device.
+//!
+//! This function will set the device address on the USB bus. This address was
+//! likely received via a SET ADDRESS command from the host controller.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Set the function address in the correct location.
+ //
+ HWREGB(ulBase + USB_O_FADDR) = (unsigned char)ulAddress;
+}
+
+//*****************************************************************************
+//
+//! Returns the current device address in device mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will return the current device address. This address was set
+//! by a call to USBDevAddrSet().
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return The current device address.
+//
+//*****************************************************************************
+unsigned long
+USBDevAddrGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Return the function address.
+ //
+ return(HWREGB(ulBase + USB_O_FADDR));
+}
+
+//*****************************************************************************
+//
+//! Sets the base configuration for a host endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulMaxPayload is the maximum payload for this endpoint.
+//! \param ulNAKPollInterval is the either the NAK timeout limit or the polling
+//! interval depending on the type of endpoint.
+//! \param ulTargetEndpoint is the endpoint that the host endpoint is
+//! targeting.
+//! \param ulFlags are used to configure other endpoint settings.
+//!
+//! This function will set the basic configuration for the transmit or receive
+//! portion of an endpoint in host mode. The \e ulFlags parameter determines
+//! some of the configuration while the other parameters provide the rest. The
+//! \e ulFlags parameter determines whether this is an IN endpoint
+//! (USB_EP_HOST_IN or USB_EP_DEV_IN) or an OUT endpoint (USB_EP_HOST_OUT or
+//! USB_EP_DEV_OUT), whether this is a Full speed endpoint (USB_EP_SPEED_FULL)
+//! or a Low speed endpoint (USB_EP_SPEED_LOW).
+//!
+//! The \b USB_EP_MODE_ flags control the type of the endpoint.
+//! - \b USB_EP_MODE_CTRL is a control endpoint.
+//! - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+//! - \b USB_EP_MODE_BULK is a bulk endpoint.
+//! - \b USB_EP_MODE_INT is an interrupt endpoint.
+//!
+//! The \e ulNAKPollInterval parameter has different meanings based on the
+//! \b USB_EP_MODE value and whether or not this call is being made for
+//! endpoint zero or another endpoint. For endpoint zero or any Bulk
+//! endpoints, this value always indicates the number of frames to allow a
+//! device to NAK before considering it a timeout. If this endpoint is an
+//! isochronous or interrupt endpoint, this value is the polling interval for
+//! this endpoint.
+//!
+//! For interrupt endpoints the polling interval is simply the number of
+//! frames between polling an interrupt endpoint. For isochronous endpoints
+//! this value represents a polling interval of 2 ^ (\e ulNAKPollInterval - 1)
+//! frames. When used as a NAK timeout, the \e ulNAKPollInterval value
+//! specifies 2 ^ (\e ulNAKPollInterval - 1) frames before issuing a time out.
+//! There are two special time out values that can be specified when setting
+//! the \e ulNAKPollInterval value. The first is \b MAX_NAK_LIMIT which is the
+//! maximum value that can be passed in this variable. The other is
+//! \b DISABLE_NAK_LIMIT which indicates that there should be no limit on the
+//! number of NAKs.
+//!
+//! The \b USB_EP_DMA_MODE_ flags enables the type of DMA used to access the
+//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA
+//! controller is configured and how it is being used. See the ``Using USB
+//! with the uDMA Controller'' section for more information on DMA
+//! configuration.
+//!
+//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit
+//! is specified to cause the transmission of data on the USB bus to start
+//! as soon as the number of bytes specified by \e ulMaxPayload have been
+//! written into the OUT FIFO for this endpoint.
+//!
+//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST
+//! bit can be specified to trigger the request for more data once the FIFO has
+//! been drained enough to fit \e ulMaxPayload bytes. The \b USB_EP_AUTO_CLEAR
+//! bit can be used to clear the data packet ready flag automatically once the
+//! data has been read from the FIFO. If this is not used, this flag must be
+//! manually cleared via a call to USBDevEndpointStatusClear() or
+//! USBHostEndpointStatusClear().
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointConfig(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulMaxPayload,
+ unsigned long ulNAKPollInterval,
+ unsigned long ulTargetEndpoint, unsigned long ulFlags)
+{
+ unsigned long ulRegister;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+ ASSERT(ulNAKPollInterval <= MAX_NAK_LIMIT);
+
+ //
+ // Endpoint zero is configured differently than the other endpoints, so see
+ // if this is endpoint zero.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Set the NAK timeout.
+ //
+ HWREGB(ulBase + USB_O_NAKLMT) = ulNAKPollInterval;
+
+ //
+ // Set the transfer type information.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TYPE0) =
+ ((ulFlags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL :
+ USB_TYPE0_SPEED_LOW);
+ }
+ else
+ {
+ //
+ // Start with the target endpoint.
+ //
+ ulRegister = ulTargetEndpoint;
+
+ //
+ // Set the speed for the device using this endpoint.
+ //
+ if(ulFlags & USB_EP_SPEED_FULL)
+ {
+ ulRegister |= USB_TXTYPE1_SPEED_FULL;
+ }
+ else
+ {
+ ulRegister |= USB_TXTYPE1_SPEED_LOW;
+ }
+
+ //
+ // Set the protocol for the device using this endpoint.
+ //
+ switch(ulFlags & USB_EP_MODE_MASK)
+ {
+ //
+ // The bulk protocol is being used.
+ //
+ case USB_EP_MODE_BULK:
+ {
+ ulRegister |= USB_TXTYPE1_PROTO_BULK;
+ break;
+ }
+
+ //
+ // The isochronous protocol is being used.
+ //
+ case USB_EP_MODE_ISOC:
+ {
+ ulRegister |= USB_TXTYPE1_PROTO_ISOC;
+ break;
+ }
+
+ //
+ // The interrupt protocol is being used.
+ //
+ case USB_EP_MODE_INT:
+ {
+ ulRegister |= USB_TXTYPE1_PROTO_INT;
+ break;
+ }
+
+ //
+ // The control protocol is being used.
+ //
+ case USB_EP_MODE_CTRL:
+ {
+ ulRegister |= USB_TXTYPE1_PROTO_CTRL;
+ break;
+ }
+ }
+
+ //
+ // See if the transmit or receive endpoint is being configured.
+ //
+ if(ulFlags & USB_EP_HOST_OUT)
+ {
+ //
+ // Set the transfer type information.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXTYPE1) =
+ ulRegister;
+
+ //
+ // Set the NAK timeout or polling interval.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXINTERVAL1) =
+ ulNAKPollInterval;
+
+ //
+ // Set the Maximum Payload per transaction.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXMAXP1) =
+ ulMaxPayload;
+
+ //
+ // Set the transmit control value to zero.
+ //
+ ulRegister = 0;
+
+ //
+ // Allow auto setting of TxPktRdy when max packet size has been
+ // loaded into the FIFO.
+ //
+ if(ulFlags & USB_EP_AUTO_SET)
+ {
+ ulRegister |= USB_TXCSRH1_AUTOSET;
+ }
+
+ //
+ // Configure the DMA Mode.
+ //
+ if(ulFlags & USB_EP_DMA_MODE_1)
+ {
+ ulRegister |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
+ }
+ else if(ulFlags & USB_EP_DMA_MODE_0)
+ {
+ ulRegister |= USB_TXCSRH1_DMAEN;
+ }
+
+ //
+ // Write out the transmit control value.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) =
+ (unsigned char)ulRegister;
+ }
+ else
+ {
+ //
+ // Set the transfer type information.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXTYPE1) =
+ ulRegister;
+
+ //
+ // Set the NAK timeout or polling interval.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXINTERVAL1) =
+ ulNAKPollInterval;
+
+ //
+ // Set the receive control value to zero.
+ //
+ ulRegister = 0;
+
+ //
+ // Allow auto clearing of RxPktRdy when packet of size max packet
+ // has been unloaded from the FIFO.
+ //
+ if(ulFlags & USB_EP_AUTO_CLEAR)
+ {
+ ulRegister |= USB_RXCSRH1_AUTOCL;
+ }
+
+ //
+ // Configure the DMA Mode.
+ //
+ if(ulFlags & USB_EP_DMA_MODE_1)
+ {
+ ulRegister |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
+ }
+ else if(ulFlags & USB_EP_DMA_MODE_0)
+ {
+ ulRegister |= USB_RXCSRH1_DMAEN;
+ }
+
+ //
+ // Write out the receive control value.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) =
+ (unsigned char)ulRegister;
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulMaxPacketSize is the maximum packet size for this endpoint.
+//! \param ulFlags are used to configure other endpoint settings.
+//!
+//! This function will set the basic configuration for an endpoint in device
+//! mode. Endpoint zero does not have a dynamic configuration, so this
+//! function should not be called for endpoint zero. The \e ulFlags parameter
+//! determines some of the configuration while the other parameters provide the
+//! rest.
+//!
+//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint.
+//!
+//! - \b USB_EP_MODE_CTRL is a control endpoint.
+//! - \b USB_EP_MODE_ISOC is an isochronous endpoint.
+//! - \b USB_EP_MODE_BULK is a bulk endpoint.
+//! - \b USB_EP_MODE_INT is an interrupt endpoint.
+//!
+//! The \b USB_EP_DMA_MODE_ flags determines the type of DMA access to the
+//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA
+//! controller is configured and how it is being used. See the ``Using USB
+//! with the uDMA Controller'' section for more information on DMA
+//! configuration.
+//!
+//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be
+//! specified to cause the automatic transmission of data on the USB bus as
+//! soon as \e ulMaxPacketSize bytes of data are written into the FIFO for
+//! this endpoint. This is commonly used with DMA as no interaction is
+//! required to start the transmission of data.
+//!
+//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is
+//! specified to trigger the request for more data once the FIFO has been
+//! drained enough to receive \e ulMaxPacketSize more bytes of data. Also for
+//! OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the data
+//! packet ready flag automatically once the data has been read from the FIFO.
+//! If this is not used, this flag must be manually cleared via a call to
+//! USBDevEndpointStatusClear(). Both of these settings can be used to remove
+//! the need for extra calls when using the controller in DMA mode.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointConfigSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulMaxPacketSize, unsigned long ulFlags)
+{
+ unsigned long ulRegister;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+ (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+ (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+ (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+ (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+ (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+ (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+ (ulEndpoint == USB_EP_15));
+
+ //
+ // Determine if a transmit or receive endpoint is being configured.
+ //
+ if(ulFlags & USB_EP_DEV_IN)
+ {
+ //
+ // Set the maximum packet size.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXMAXP1) =
+ ulMaxPacketSize;
+
+ //
+ // The transmit control value is zero unless options are enabled.
+ //
+ ulRegister = 0;
+
+ //
+ // Allow auto setting of TxPktRdy when max packet size has been loaded
+ // into the FIFO.
+ //
+ if(ulFlags & USB_EP_AUTO_SET)
+ {
+ ulRegister |= USB_TXCSRH1_AUTOSET;
+ }
+
+ //
+ // Configure the DMA mode.
+ //
+ if(ulFlags & USB_EP_DMA_MODE_1)
+ {
+ ulRegister |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
+ }
+ else if(ulFlags & USB_EP_DMA_MODE_0)
+ {
+ ulRegister |= USB_TXCSRH1_DMAEN;
+ }
+
+ //
+ // Enable isochronous mode if requested.
+ //
+ if((ulFlags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
+ {
+ ulRegister |= USB_TXCSRH1_ISO;
+ }
+
+ //
+ // Write the transmit control value.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) =
+ (unsigned char)ulRegister;
+
+ //
+ // Reset the Data toggle to zero.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRL1) =
+ USB_TXCSRL1_CLRDT;
+ }
+ else
+ {
+ //
+ // Set the MaxPacketSize.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXMAXP1) =
+ ulMaxPacketSize;
+
+ //
+ // The receive control value is zero unless options are enabled.
+ //
+ ulRegister = 0;
+
+ //
+ // Allow auto clearing of RxPktRdy when packet of size max packet
+ // has been unloaded from the FIFO.
+ //
+ if(ulFlags & USB_EP_AUTO_CLEAR)
+ {
+ ulRegister = USB_RXCSRH1_AUTOCL;
+ }
+
+ //
+ // Configure the DMA mode.
+ //
+ if(ulFlags & USB_EP_DMA_MODE_1)
+ {
+ ulRegister |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
+ }
+ else if(ulFlags & USB_EP_DMA_MODE_0)
+ {
+ ulRegister |= USB_RXCSRH1_DMAEN;
+ }
+
+ //
+ // Enable isochronous mode if requested.
+ //
+ if((ulFlags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
+ {
+ ulRegister |= USB_RXCSRH1_ISO;
+ }
+
+ //
+ // Write the receive control value.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) =
+ (unsigned char)ulRegister;
+
+ //
+ // Reset the Data toggle to zero.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRL1) =
+ USB_RXCSRL1_CLRDT;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param pulMaxPacketSize is a pointer which will be written with the
+//! maximum packet size for this endpoint.
+//! \param pulFlags is a pointer which will be written with the current
+//! endpoint settings. On entry to the function, this pointer must contain
+//! either \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or
+//! OUT endpoint is to be queried.
+//!
+//! This function will return the basic configuration for an endpoint in device
+//! mode. The values returned in \e *pulMaxPacketSize and \e *pulFlags are
+//! equivalent to the \e ulMaxPacketSize and \e ulFlags previously passed to
+//! USBDevEndpointConfigSet() for this endpoint.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long *pulMaxPacketSize,
+ unsigned long *pulFlags)
+{
+ unsigned long ulRegister;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT(pulMaxPacketSize && pulFlags);
+ ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+ (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+ (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+ (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+ (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+ (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+ (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+ (ulEndpoint == USB_EP_15));
+
+ //
+ // Determine if a transmit or receive endpoint is being queried.
+ //
+ if(*pulFlags & USB_EP_DEV_IN)
+ {
+ //
+ // Clear the flags other than the direction bit.
+ //
+ *pulFlags = USB_EP_DEV_IN;
+
+ //
+ // Get the maximum packet size.
+ //
+ *pulMaxPacketSize = (unsigned long)HWREGB(ulBase +
+ EP_OFFSET(ulEndpoint) +
+ USB_O_TXMAXP1);
+
+ //
+ // Get the current transmit control register value.
+ //
+ ulRegister = (unsigned long)HWREGB(ulBase + EP_OFFSET(ulEndpoint) +
+ USB_O_TXCSRH1);
+
+ //
+ // Are we allowing auto setting of TxPktRdy when max packet size has
+ // been loaded into the FIFO?
+ //
+ if(ulRegister & USB_TXCSRH1_AUTOSET)
+ {
+ *pulFlags |= USB_EP_AUTO_SET;
+ }
+
+ //
+ // Get the DMA mode.
+ //
+ if(ulRegister & USB_TXCSRH1_DMAEN)
+ {
+ if(ulRegister & USB_TXCSRH1_DMAMOD)
+ {
+ *pulFlags |= USB_EP_DMA_MODE_1;
+ }
+ else
+ {
+ *pulFlags |= USB_EP_DMA_MODE_0;
+ }
+ }
+
+ //
+ // Are we in isochronous mode?
+ //
+ if(ulRegister & USB_TXCSRH1_ISO)
+ {
+ *pulFlags |= USB_EP_MODE_ISOC;
+ }
+ else
+ {
+ //
+ // The hardware doesn't differentiate between bulk, interrupt
+ // and control mode for the endpoint so we just set something
+ // that isn't isochronous. This ensures that anyone modifying
+ // the returned flags in preparation for a call to
+ // USBDevEndpointConfigSet will not see an unexpected mode change.
+ // If they decode the returned mode, however, they may be in for
+ // a surprise.
+ //
+ *pulFlags |= USB_EP_MODE_BULK;
+ }
+ }
+ else
+ {
+ //
+ // Clear the flags other than the direction bit.
+ //
+ *pulFlags = USB_EP_DEV_OUT;
+
+ //
+ // Get the MaxPacketSize.
+ //
+ *pulMaxPacketSize = (unsigned long)HWREGB(ulBase +
+ EP_OFFSET(ulEndpoint) +
+ USB_O_RXMAXP1);
+
+ //
+ // Get the current receive control register value.
+ //
+ ulRegister = (unsigned long)HWREGB(ulBase + EP_OFFSET(ulEndpoint) +
+ USB_O_RXCSRH1);
+
+ //
+ // Are we allowing auto clearing of RxPktRdy when packet of size max
+ // packet has been unloaded from the FIFO?
+ //
+ if(ulRegister & USB_RXCSRH1_AUTOCL)
+ {
+ *pulFlags |= USB_EP_AUTO_CLEAR;
+ }
+
+ //
+ // Get the DMA mode.
+ //
+ if(ulRegister & USB_RXCSRH1_DMAEN)
+ {
+ if(ulRegister & USB_RXCSRH1_DMAMOD)
+ {
+ *pulFlags |= USB_EP_DMA_MODE_1;
+ }
+ else
+ {
+ *pulFlags |= USB_EP_DMA_MODE_0;
+ }
+ }
+
+ //
+ // Are we in isochronous mode?
+ //
+ if(ulRegister & USB_RXCSRH1_ISO)
+ {
+ *pulFlags |= USB_EP_MODE_ISOC;
+ }
+ else
+ {
+ //
+ // The hardware doesn't differentiate between bulk, interrupt
+ // and control mode for the endpoint so we just set something
+ // that isn't isochronous. This ensures that anyone modifying
+ // the returned flags in preparation for a call to
+ // USBDevEndpointConfigSet will not see an unexpected mode change.
+ // If they decode the returned mode, however, they may be in for
+ // a surprise.
+ //
+ *pulFlags |= USB_EP_MODE_BULK;
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFIFOAddress is the starting address for the FIFO.
+//! \param ulFIFOSize is the size of the FIFO in bytes.
+//! \param ulFlags specifies what information to set in the FIFO configuration.
+//!
+//! This function will set the starting FIFO RAM address and size of the FIFO
+//! for a given endpoint. Endpoint zero does not have a dynamically
+//! configurable FIFO so this function should not be called for endpoint zero.
+//! The \e ulFIFOSize parameter should be one of the values in the
+//! \b USB_FIFO_SZ_ values. If the endpoint is going to use double buffering
+//! it should use the values with the \b _DB at the end of the value. For
+//! example, use \b USB_FIFO_SZ_16_DB to configure an endpoint to have a 16
+//! byte double buffered FIFO. If a double buffered FIFO is used, then the
+//! actual size of the FIFO will be twice the size indicated by the
+//! \e ulFIFOSize parameter. This means that the \b USB_FIFO_SZ_16_DB value
+//! will use 32 bytes of the USB controller's FIFO memory.
+//!
+//! The \e ulFIFOAddress value should be a multiple of 8 bytes and directly
+//! indicates the starting address in the USB controller's FIFO RAM. For
+//! example, a value of 64 indicates that the FIFO should start 64 bytes into
+//! the USB controller's FIFO memory. The \e ulFlags value specifies whether
+//! the endpoint's OUT or IN FIFO should be configured. If in host mode, use
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode use
+//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFIFOAddress, unsigned long ulFIFOSize,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+ (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+ (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+ (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+ (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+ (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+ (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+ (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the transmit or receive FIFO is being configured.
+ //
+ if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+ {
+ //
+ // Set the transmit FIFO location and size for this endpoint.
+ //
+ USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_TXFIFOSZ, ulFIFOSize, 1);
+ USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_TXFIFOADD,
+ ulFIFOAddress >> 3, 2);
+ }
+ else
+ {
+ //
+ // Set the receive FIFO location and size for this endpoint.
+ //
+ USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_RXFIFOSZ, ulFIFOSize, 1);
+ USBIndexWrite(ulBase, ulEndpoint >> 4, USB_O_RXFIFOADD,
+ ulFIFOAddress >> 3, 2);
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the FIFO configuration for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param pulFIFOAddress is the starting address for the FIFO.
+//! \param pulFIFOSize is the size of the FIFO in bytes.
+//! \param ulFlags specifies what information to retrieve from the FIFO
+//! configuration.
+//!
+//! This function will return the starting address and size of the FIFO for a
+//! given endpoint. Endpoint zero does not have a dynamically configurable
+//! FIFO so this function should not be called for endpoint zero. The
+//! \e ulFlags parameter specifies whether the endpoint's OUT or IN FIFO should
+//! be read. If in host mode, the \e ulFlags parameter should be
+//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode the
+//! \e ulFlags parameter should be either \b USB_EP_DEV_OUT or
+//! \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long *pulFIFOAddress, unsigned long *pulFIFOSize,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+ (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+ (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+ (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+ (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+ (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+ (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+ (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the transmit or receive FIFO is being configured.
+ //
+ if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+ {
+ //
+ // Get the transmit FIFO location and size for this endpoint.
+ //
+ *pulFIFOAddress = (USBIndexRead(ulBase, ulEndpoint >> 4,
+ (unsigned long)USB_O_TXFIFOADD,
+ 2)) << 3;
+ *pulFIFOSize = USBIndexRead(ulBase, ulEndpoint >> 4,
+ (unsigned long)USB_O_TXFIFOSZ, 1);
+
+ }
+ else
+ {
+ //
+ // Get the receive FIFO location and size for this endpoint.
+ //
+ *pulFIFOAddress = (USBIndexRead(ulBase, ulEndpoint >> 4,
+ (unsigned long)USB_O_RXFIFOADD,
+ 2)) << 3;
+ *pulFIFOSize = USBIndexRead(ulBase, ulEndpoint >> 4,
+ (unsigned long)USB_O_RXFIFOSZ, 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enable DMA on a given endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags specifies which direction and what mode to use when enabling
+//! DMA.
+//!
+//! This function will enable DMA on a given endpoint and set the mode according
+//! to the values in the \e ulFlags parameter. The \e ulFlags parameter should
+//! have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // See if the transmit DMA is being enabled.
+ //
+ if(ulFlags & USB_EP_DEV_IN)
+ {
+ //
+ // Enable DMA on the transmit end point.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) |=
+ USB_TXCSRH1_DMAEN;
+ }
+ else
+ {
+ //
+ // Enable DMA on the receive end point.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) |=
+ USB_RXCSRH1_DMAEN;
+ }
+}
+
+//*****************************************************************************
+//
+//! Disable DMA on a given endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags specifies which direction to disable.
+//!
+//! This function will disable DMA on a given end point to allow non-DMA
+//! USB transactions to generate interrupts normally. The ulFlags should be
+//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT all other bits are ignored.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBEndpointDMADisable(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // If this was a request to disable DMA on the IN portion of the end point
+ // then handle it.
+ //
+ if(ulFlags & USB_EP_DEV_IN)
+ {
+ //
+ // Just disable DMA leave the mode setting.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_TXCSRH1) &=
+ ~USB_TXCSRH1_DMAEN;
+ }
+ else
+ {
+ //
+ // Just disable DMA leave the mode setting.
+ //
+ HWREGB(ulBase + EP_OFFSET(ulEndpoint) + USB_O_RXCSRH1) &=
+ ~USB_RXCSRH1_DMAEN;
+ }
+}
+
+//*****************************************************************************
+//
+//! Determine the number of bytes of data available in a given endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//!
+//! This function will return the number of bytes of data currently available
+//! in the FIFO for the given receive (OUT) endpoint. It may be used prior to
+//! calling USBEndpointDataGet() to determine the size of buffer required to
+//! hold the newly-received packet.
+//!
+//! \return This call will return the number of bytes available in a given
+//! endpoint FIFO.
+//
+//*****************************************************************************
+unsigned long
+USBEndpointDataAvail(unsigned long ulBase, unsigned long ulEndpoint)
+{
+ unsigned long ulRegister;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Get the address of the receive status register to use, based on the
+ // endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ ulRegister = USB_O_CSRL0;
+ }
+ else
+ {
+ ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint);
+ }
+
+ //
+ // Is there a packet ready in the FIFO?
+ //
+ if((HWREGH(ulBase + ulRegister) & USB_CSRL0_RXRDY) == 0)
+ {
+ return(0);
+ }
+
+ //
+ // Return the byte count in the FIFO.
+ //
+ return(HWREGH(ulBase + USB_O_COUNT0 + ulEndpoint));
+}
+
+//*****************************************************************************
+//
+//! Retrieves data from the given endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param pucData is a pointer to the data area used to return the data from
+//! the FIFO.
+//! \param pulSize is initially the size of the buffer passed into this call
+//! via the \e pucData parameter. It will be set to the amount of data
+//! returned in the buffer.
+//!
+//! This function will return the data from the FIFO for the given endpoint.
+//! The \e pulSize parameter should indicate the size of the buffer passed in
+//! the \e pulData parameter. The data in the \e pulSize parameter will be
+//! changed to match the amount of data returned in the \e pucData parameter.
+//! If a zero byte packet was received this call will not return a error but
+//! will instead just return a zero in the \e pulSize parameter. The only
+//! error case occurs when there is no data packet available.
+//!
+//! \return This call will return 0, or -1 if no packet was received.
+//
+//*****************************************************************************
+long
+USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned char *pucData, unsigned long *pulSize)
+{
+ unsigned long ulRegister, ulByteCount, ulFIFO;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Get the address of the receive status register to use, based on the
+ // endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ ulRegister = USB_O_CSRL0;
+ }
+ else
+ {
+ ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint);
+ }
+
+ //
+ // Don't allow reading of data if the RxPktRdy bit is not set.
+ //
+ if((HWREGH(ulBase + ulRegister) & USB_CSRL0_RXRDY) == 0)
+ {
+ //
+ // Can't read the data because none is available.
+ //
+ *pulSize = 0;
+
+ //
+ // Return a failure since there is no data to read.
+ //
+ return(-1);
+ }
+
+ //
+ // Get the byte count in the FIFO.
+ //
+ ulByteCount = HWREGH(ulBase + USB_O_COUNT0 + ulEndpoint);
+
+ //
+ // Determine how many bytes we will actually copy.
+ //
+ ulByteCount = (ulByteCount < *pulSize) ? ulByteCount : *pulSize;
+
+ //
+ // Return the number of bytes we are going to read.
+ //
+ *pulSize = ulByteCount;
+
+ //
+ // Calculate the FIFO address.
+ //
+ ulFIFO = ulBase + USB_O_FIFO0 + (ulEndpoint >> 2);
+
+ //
+ // Read the data out of the FIFO.
+ //
+ for(; ulByteCount > 0; ulByteCount--)
+ {
+ //
+ // Read a byte at a time from the FIFO.
+ //
+ *pucData++ = HWREGB(ulFIFO);
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Acknowledge that data was read from the given endpoint's FIFO in device
+//! mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param bIsLastPacket indicates if this is the last packet.
+//!
+//! This function acknowledges that the data was read from the endpoint's FIFO.
+//! The \e bIsLastPacket parameter is set to a \b true value if this is the
+//! last in a series of data packets on endpoint zero. The \e bIsLastPacket
+//! parameter is not used for endpoints other than endpoint zero. This call
+//! can be used if processing is required between reading the data and
+//! acknowledging that the data has been read.
+//!
+//! \note This function should only be called in device mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevEndpointDataAck(unsigned long ulBase, unsigned long ulEndpoint,
+ tBoolean bIsLastPacket)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Determine which endpoint is being acked.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Clear RxPktRdy, and optionally DataEnd, on endpoint zero.
+ //
+ HWREGB(ulBase + USB_O_CSRL0) =
+ USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0);
+ }
+ else
+ {
+ //
+ // Clear RxPktRdy on all other endpoints.
+ //
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~(USB_RXCSRL1_RXRDY);
+ }
+}
+
+//*****************************************************************************
+//
+//! Acknowledge that data was read from the given endpoint's FIFO in host
+//! mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//!
+//! This function acknowledges that the data was read from the endpoint's FIFO.
+//! This call is used if processing is required between reading the data and
+//! acknowledging that the data has been read.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostEndpointDataAck(unsigned long ulBase, unsigned long ulEndpoint)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Clear RxPktRdy.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ HWREGB(ulBase + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY;
+ }
+ else
+ {
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &=
+ ~(USB_RXCSRL1_RXRDY);
+ }
+}
+
+//*****************************************************************************
+//
+//! Puts data into the given endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param pucData is a pointer to the data area used as the source for the
+//! data to put into the FIFO.
+//! \param ulSize is the amount of data to put into the FIFO.
+//!
+//! This function will put the data from the \e pucData parameter into the FIFO
+//! for this endpoint. If a packet is already pending for transmission then
+//! this call will not put any of the data into the FIFO and will return -1.
+//! Care should be taken to not write more data than can fit into the FIFO
+//! allocated by the call to USBFIFOConfig().
+//!
+//! \return This call will return 0 on success, or -1 to indicate that the FIFO
+//! is in use and cannot be written.
+//
+//*****************************************************************************
+long
+USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned char *pucData, unsigned long ulSize)
+{
+ unsigned long ulFIFO;
+ unsigned char ucTxPktRdy;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Get the bit position of TxPktRdy based on the endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ ucTxPktRdy = USB_CSRL0_TXRDY;
+ }
+ else
+ {
+ ucTxPktRdy = USB_TXCSRL1_TXRDY;
+ }
+
+ //
+ // Don't allow transmit of data if the TxPktRdy bit is already set.
+ //
+ if(HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) & ucTxPktRdy)
+ {
+ return(-1);
+ }
+
+ //
+ // Calculate the FIFO address.
+ //
+ ulFIFO = ulBase + USB_O_FIFO0 + (ulEndpoint >> 2);
+
+ //
+ // Write the data to the FIFO.
+ //
+ for(; ulSize > 0; ulSize--)
+ {
+ HWREGB(ulFIFO) = *pucData++;
+ }
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Starts the transfer of data from an endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulTransType is set to indicate what type of data is being sent.
+//!
+//! This function will start the transfer of data from the FIFO for a given
+//! endpoint. This is necessary if the \b USB_EP_AUTO_SET bit was not enabled
+//! for the endpoint. Setting the \e ulTransType parameter will allow the
+//! appropriate signaling on the USB bus for the type of transaction being
+//! requested. The \e ulTransType parameter should be one of the following:
+//!
+//! - USB_TRANS_OUT for OUT transaction on any endpoint in host mode.
+//! - USB_TRANS_IN for IN transaction on any endpoint in device mode.
+//! - USB_TRANS_IN_LAST for the last IN transactions on endpoint zero in a
+//! sequence of IN transactions.
+//! - USB_TRANS_SETUP for setup transactions on endpoint zero.
+//! - USB_TRANS_STATUS for status results on endpoint zero.
+//!
+//! \return This call will return 0 on success, or -1 if a transmission is
+//! already in progress.
+//
+//*****************************************************************************
+long
+USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulTransType)
+{
+ unsigned long ulTxPktRdy;
+
+ //
+ // CHeck the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Get the bit position of TxPktRdy based on the endpoint.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ ulTxPktRdy = ulTransType & 0xff;
+ }
+ else
+ {
+ ulTxPktRdy = (ulTransType >> 8) & 0xff;
+ }
+
+ //
+ // Don't allow transmit of data if the TxPktRdy bit is already set.
+ //
+ if(HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) & USB_CSRL0_TXRDY)
+ {
+ return(-1);
+ }
+
+ //
+ // Set TxPktRdy in order to send the data.
+ //
+ HWREGB(ulBase + USB_O_CSRL0 + ulEndpoint) = ulTxPktRdy;
+
+ //
+ // Success.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Forces a flush of an endpoint's FIFO.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags specifies if the IN or OUT endpoint should be accessed.
+//!
+//! This function will force the controller to flush out the data in the FIFO.
+//! The function can be called with either host or device controllers and
+//! requires the \e ulFlags parameter be one of \b USB_EP_HOST_OUT,
+//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Endpoint zero has a different register set for FIFO flushing.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ //
+ // Nothing in the FIFO if neither of these bits are set.
+ //
+ if((HWREGB(ulBase + USB_O_CSRL0) &
+ (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0)
+ {
+ //
+ // Hit the Flush FIFO bit.
+ //
+ HWREGB(ulBase + USB_O_CSRH0) = USB_CSRH0_FLUSH;
+ }
+ }
+ else
+ {
+ //
+ // Only reset the IN or OUT FIFO.
+ //
+ if(ulFlags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
+ {
+ //
+ // Make sure the FIFO is not empty.
+ //
+ if(HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) &
+ USB_TXCSRL1_TXRDY)
+ {
+ //
+ // Hit the Flush FIFO bit.
+ //
+ HWREGB(ulBase + USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_TXCSRL1_FLUSH;
+ }
+ }
+ else
+ {
+ //
+ // Make sure that the FIFO is not empty.
+ //
+ if(HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) &
+ USB_RXCSRL1_RXRDY)
+ {
+ //
+ // Hit the Flush FIFO bit.
+ //
+ HWREGB(ulBase + USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint)) |=
+ USB_RXCSRL1_FLUSH;
+ }
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Schedules a request for an IN transaction on an endpoint in host mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//!
+//! This function will schedule a request for an IN transaction. When the USB
+//! device being communicated with responds the data, the data can be retrieved
+//! by calling USBEndpointDataGet() or via a DMA transfer.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint)
+{
+ unsigned long ulRegister;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // Endpoint zero uses a different offset than the other endpoints.
+ //
+ if(ulEndpoint == USB_EP_0)
+ {
+ ulRegister = USB_O_CSRL0;
+ }
+ else
+ {
+ ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint);
+ }
+
+ //
+ // Set the request for an IN transaction.
+ //
+ HWREGB(ulBase + ulRegister) = USB_RXCSRL1_REQPKT;
+}
+
+//*****************************************************************************
+//
+//! Issues a request for a status IN transaction on endpoint zero.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function is used to cause a request for an status IN transaction from
+//! a device on endpoint zero. This function can only be used with endpoint
+//! zero as that is the only control endpoint that supports this ability. This
+//! is used to complete the last phase of a control transaction to a device and
+//! an interrupt will be signaled when the status packet has been received.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostRequestStatus(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Set the request for a status IN transaction.
+ //
+ HWREGB(ulBase + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS;
+}
+
+//*****************************************************************************
+//
+//! Sets the functional address for the device that is connected to an
+//! endpoint in host mode.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulAddr is the functional address for the controller to use for this
+//! endpoint.
+//! \param ulFlags determines if this is an IN or an OUT endpoint.
+//!
+//! This function will set the functional address for a device that is using
+//! this endpoint for communication. This \e ulAddr parameter is the address
+//! of the target device that this endpoint will be used to communicate with.
+//! The \e ulFlags parameter indicates if the IN or OUT endpoint should be set.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulAddr, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the transmit or receive address should be set.
+ //
+ if(ulFlags & USB_EP_HOST_OUT)
+ {
+ //
+ // Set the transmit address.
+ //
+ HWREGB(ulBase + USB_O_TXFUNCADDR0 + (ulEndpoint >> 1)) = ulAddr;
+ }
+ else
+ {
+ //
+ // Set the receive address.
+ //
+ HWREGB(ulBase + USB_O_TXFUNCADDR0 + 4 + (ulEndpoint >> 1)) = ulAddr;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current functional device address for an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags determines if this is an IN or an OUT endpoint.
+//!
+//! This function returns the current functional address that an endpoint is
+//! using to communicate with a device. The \e ulFlags parameter determines if
+//! the IN or OUT endpoint's device address is returned.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return Returns the current function address being used by an endpoint.
+//
+//*****************************************************************************
+unsigned long
+USBHostAddrGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the transmit or receive address should be returned.
+ //
+ if(ulFlags & USB_EP_HOST_OUT)
+ {
+ //
+ // Return this endpoint's transmit address.
+ //
+ return(HWREGB(ulBase + USB_O_TXFUNCADDR0 + (ulEndpoint >> 1)));
+ }
+ else
+ {
+ //
+ // Return this endpoint's receive address.
+ //
+ return(HWREGB(ulBase + USB_O_TXFUNCADDR0 + 4 + (ulEndpoint >> 1)));
+ }
+}
+
+//*****************************************************************************
+//
+//! Set the hub address for the device that is connected to an endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulAddr is the hub address for the device using this endpoint.
+//! \param ulFlags determines if this is an IN or an OUT endpoint.
+//!
+//! This function will set the hub address for a device that is using this
+//! endpoint for communication. The \e ulFlags parameter determines if the
+//! device address for the IN or the OUT endpoint is set by this call.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulAddr, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the hub transmit or receive address is being set.
+ //
+ if(ulFlags & USB_EP_HOST_OUT)
+ {
+ //
+ // Set the hub transmit address for this endpoint.
+ //
+ HWREGB(ulBase + USB_O_TXHUBADDR0 + (ulEndpoint >> 1)) = ulAddr;
+ }
+ else
+ {
+ //
+ // Set the hub receive address for this endpoint.
+ //
+ HWREGB(ulBase + USB_O_TXHUBADDR0 + 4 + (ulEndpoint >> 1)) = ulAddr;
+ }
+}
+
+//*****************************************************************************
+//
+//! Get the current device hub address for this endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint is the endpoint to access.
+//! \param ulFlags determines if this is an IN or an OUT endpoint.
+//!
+//! This function will return the current hub address that an endpoint is using
+//! to communicate with a device. The \e ulFlags parameter determines if the
+//! device address for the IN or OUT endpoint is returned.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return This function returns the current hub address being used by an
+//! endpoint.
+//
+//*****************************************************************************
+unsigned long
+USBHostHubAddrGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_0) || (ulEndpoint == USB_EP_1) ||
+ (ulEndpoint == USB_EP_2) || (ulEndpoint == USB_EP_3) ||
+ (ulEndpoint == USB_EP_4) || (ulEndpoint == USB_EP_5) ||
+ (ulEndpoint == USB_EP_6) || (ulEndpoint == USB_EP_7) ||
+ (ulEndpoint == USB_EP_8) || (ulEndpoint == USB_EP_9) ||
+ (ulEndpoint == USB_EP_10) || (ulEndpoint == USB_EP_11) ||
+ (ulEndpoint == USB_EP_12) || (ulEndpoint == USB_EP_13) ||
+ (ulEndpoint == USB_EP_14) || (ulEndpoint == USB_EP_15));
+
+ //
+ // See if the hub transmit or receive address should be returned.
+ //
+ if(ulFlags & USB_EP_HOST_OUT)
+ {
+ //
+ // Return the hub transmit address for this endpoint.
+ //
+ return(HWREGB(ulBase + USB_O_TXHUBADDR0 + (ulEndpoint >> 1)));
+ }
+ else
+ {
+ //
+ // Return the hub receive address for this endpoint.
+ //
+ return(HWREGB(ulBase + USB_O_TXHUBADDR0 + 4 + (ulEndpoint >> 1)));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration for USB power fault.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulFlags specifies the configuration of the power fault.
+//!
+//! This function controls how the USB controller uses its external power
+//! control pins(USBnPFTL and USBnEPEN). The flags specify the power
+//! fault level sensitivity, the power fault action, and the power enable level
+//! and source.
+//!
+//! One of the following can be selected as the power fault level
+//! sensitivity:
+//!
+//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin
+//! being driven low.
+//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin
+//! being driven high.
+//!
+//! One of the following can be selected as the power fault action:
+//!
+//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault
+//! detected.
+//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically Tri-state the USBnEPEN pin on a
+//! power fault.
+//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a
+//! power fault.
+//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a
+//! power fault.
+//!
+//! One of the following can be selected as the power enable level and source:
+//!
+//! - \b USB_HOST_PWREN_MAN_LOW - USBEPEN is driven low by the USB controller
+//! when USBHostPwrEnable() is called.
+//! - \b USB_HOST_PWREN_MAN_HIGH - USBEPEN is driven high by the USB controller
+//! when USBHostPwrEnable() is called.
+//! - \b USB_HOST_PWREN_AUTOLOW - USBEPEN is driven low by the USB controller
+//! automatically if USBOTGSessionRequest() has
+//! enabled a session.
+//! - \b USB_HOST_PWREN_AUTOHIGH - USBEPEN is driven high by the USB controller
+//! automatically if USBOTGSessionRequest() has
+//! enabled a session.
+//!
+//! On devices that support the VBUS glitch filter, the
+//! \b USB_HOST_PWREN_FILTER can be added to ignore small short drops in VBUS
+//! level caused by high power consumption. This is mainly used to avoid
+//! causing VBUS errors caused by devices with high in-rush current.
+//!
+//! \note The following values have been deprecated and should no longer be
+//! used.
+//! - \b USB_HOST_PWREN_LOW - Automatically drive USBnEPEN low when power is
+//! enabled.
+//! - \b USB_HOST_PWREN_HIGH - Automatically drive USBnEPEN high when power is
+//! enabled.
+//! - \b USB_HOST_PWREN_VBLOW - Automatically drive USBnEPEN low when power is
+//! enabled.
+//! - \b USB_HOST_PWREN_VBHIGH - Automatically drive USBnEPEN high when power is
+//! enabled.
+//!
+//! \note This function should only be called on microcontrollers that support
+//! host mode or OTG operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulFlags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M |
+ USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH |
+ USB_EPC_EPEN_M)) == 0);
+
+ //
+ // If requested, enable VBUS droop detection on parts that support this
+ // feature.
+ //
+ HWREG(ulBase + USB_O_VDC) = ulFlags >> 16;
+
+ //
+ // Set the power fault configuration as specified. This will not change
+ // whether fault detection is enabled or not.
+ //
+ HWREGH(ulBase + USB_O_EPC) =
+ (ulFlags | (HWREGH(ulBase + USB_O_EPC) &
+ ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN |
+ USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M)));
+}
+
+//*****************************************************************************
+//
+//! Enables power fault detection.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function enables power fault detection in the USB controller. If the
+//! USBPFLT pin is not in use this function should not be used.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrFaultEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Enable power fault input.
+ //
+ HWREGH(ulBase + USB_O_EPC) |= USB_EPC_PFLTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables power fault detection.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function disables power fault detection in the USB controller.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrFaultDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Enable power fault input.
+ //
+ HWREGH(ulBase + USB_O_EPC) &= ~USB_EPC_PFLTEN;
+}
+
+//*****************************************************************************
+//
+//! Enables the external power pin.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function enables the USBEPEN signal to enable an external power supply
+//! in host mode operation.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Enable the external power supply enable signal.
+ //
+ HWREGH(ulBase + USB_O_EPC) |= USB_EPC_EPENDE;
+}
+
+//*****************************************************************************
+//
+//! Disables the external power pin.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function disables the USBEPEN signal to disable an external power
+//! supply in host mode operation.
+//!
+//! \note This function should only be called in host mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostPwrDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Disable the external power supply enable signal.
+ //
+ HWREGH(ulBase + USB_O_EPC) &= ~USB_EPC_EPENDE;
+}
+
+//*****************************************************************************
+//
+//! Get the current frame number.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function returns the last frame number received.
+//!
+//! \return The last frame number received.
+//
+//*****************************************************************************
+unsigned long
+USBFrameNumberGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Return the most recent frame number.
+ //
+ return(HWREGH(ulBase + USB_O_FRAME));
+}
+
+//*****************************************************************************
+//
+//! Starts or ends a session.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param bStart specifies if this call starts or ends a session.
+//!
+//! This function is used in OTG mode to start a session request or end a
+//! session. If the \e bStart parameter is set to \b true, then this function
+//! start a session and if it is \b false it will end a session.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Start or end the session as directed.
+ //
+ if(bStart)
+ {
+ HWREGB(ulBase + USB_O_DEVCTL) |= USB_DEVCTL_SESSION;
+ }
+ else
+ {
+ HWREGB(ulBase + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION;
+ }
+}
+
+//*****************************************************************************
+//
+//! Returns the absolute FIFO address for a given endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies which endpoint's FIFO address to return.
+//!
+//! This function returns the actual physical address of the FIFO. This is
+//! needed when the USB is going to be used with the uDMA controller and the
+//! source or destination address needs to be set to the physical FIFO address
+//! for a given endpoint.
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long
+USBFIFOAddrGet(unsigned long ulBase, unsigned long ulEndpoint)
+{
+ //
+ // Return the FIFO address for this endpoint.
+ //
+ return(ulBase + USB_O_FIFO0 + (ulEndpoint >> 2));
+}
+
+//*****************************************************************************
+//
+//! Returns the current operating mode of the controller.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function returns the current operating mode on USB controllers with
+//! OTG or Dual mode functionality.
+//!
+//! For OTG controllers:
+//!
+//! The function will return on of the following values on OTG controllers:
+//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV,
+//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV,
+//! \b USB_OTG_MODE_NONE.
+//!
+//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode
+//! on the A-side of the cable.
+//!
+//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode
+//! on the A-side of the cable.
+//!
+//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode
+//! on the B-side of the cable.
+//!
+//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode
+//! on the B-side of the cable. If and OTG session request is started with no
+//! cable in place this is the default mode for the controller.
+//!
+//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to
+//! determine its role in the system.
+//!
+//! For Dual Mode controllers:
+//!
+//! The function will return on of the following values:
+//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or
+//! \b USB_DUAL_MODE_NONE.
+//!
+//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host.
+//!
+//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device.
+//!
+//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as
+//! either a host or device.
+//!
+//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV,
+//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV,
+//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or
+//! \b USB_DUAL_MODE_NONE.
+//
+//*****************************************************************************
+unsigned long
+USBModeGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Checks the current mode in the USB_O_DEVCTL and returns the current
+ // mode.
+ //
+ // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION
+ // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION
+ // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION |
+ // USB_DEVCTL_HOST
+ // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION
+ // USB_OTG_MODE_NONE: USB_DEVCTL_DEV
+ //
+ return(HWREGB(ulBase + USB_O_DEVCTL) &
+ (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION |
+ USB_DEVCTL_VBUS_M));
+}
+
+//*****************************************************************************
+//
+//! Sets the DMA channel to use for a given endpoint.
+//!
+//! \param ulBase specifies the USB module base address.
+//! \param ulEndpoint specifies which endpoint's FIFO address to return.
+//! \param ulChannel specifies which DMA channel to use for which endpoint.
+//!
+//! This function is used to configure which DMA channel to use with a given
+//! endpoint. Receive DMA channels can only be used with receive endpoints
+//! and transmit DMA channels can only be used with transmit endpoints. This
+//! allows the 3 receive and 3 transmit DMA channels to be mapped to any
+//! endpoint other than 0. The values that should be passed into the \e
+//! ulChannel value are the UDMA_CHANNEL_USBEP* values defined in udma.h.
+//!
+//! \note This function only has an effect on microcontrollers that have the
+//! ability to change the DMA channel for an endpoint. Calling this function
+//! on other devices will have no effect.
+//!
+//! \return None.
+//!
+//*****************************************************************************
+void
+USBEndpointDMAChannel(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulChannel)
+{
+ unsigned long ulMask;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+ ASSERT((ulEndpoint == USB_EP_1) || (ulEndpoint == USB_EP_2) ||
+ (ulEndpoint == USB_EP_3) || (ulEndpoint == USB_EP_4) ||
+ (ulEndpoint == USB_EP_5) || (ulEndpoint == USB_EP_6) ||
+ (ulEndpoint == USB_EP_7) || (ulEndpoint == USB_EP_8) ||
+ (ulEndpoint == USB_EP_9) || (ulEndpoint == USB_EP_10) ||
+ (ulEndpoint == USB_EP_11) || (ulEndpoint == USB_EP_12) ||
+ (ulEndpoint == USB_EP_13) || (ulEndpoint == USB_EP_14) ||
+ (ulEndpoint == USB_EP_15));
+ ASSERT(ulChannel <= UDMA_CHANNEL_USBEP3TX);
+
+ //
+ // The input select mask needs to be shifted into the correct position
+ // based on the channel.
+ //
+ ulMask = 0xf << (ulChannel * 4);
+
+ //
+ // Clear out the current selection for the channel.
+ //
+ ulMask = HWREG(ulBase + USB_O_DMASEL) & (~ulMask);
+
+ //
+ // The input select is now shifted into the correct position based on the
+ // channel.
+ //
+ ulMask |= (USB_EP_TO_INDEX(ulEndpoint)) << (ulChannel * 4);
+
+ //
+ // Write the value out to the register.
+ //
+ HWREG(ulBase + USB_O_DMASEL) = ulMask;
+}
+
+//*****************************************************************************
+//
+//! Change the mode of the USB controller to host.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to host mode. This
+//! is only valid on microcontrollers that have the host and device
+//! capabilities and not the OTG capabilities.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBHostMode(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Force mode in OTG parts that support forcing USB controller mode.
+ // This bit is not writable in USB controllers that do not support
+ // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a
+ // force of host mode.
+ //
+ HWREGB(ulBase + USB_O_GPCS) = USB_GPCS_DEVMODOTG;
+}
+
+//*****************************************************************************
+//
+//! Change the mode of the USB controller to device.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function changes the mode of the USB controller to device mode. This
+//! is only valid on microcontrollers that have the host and device
+//! capabilities and not the OTG capabilities.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBDevMode(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == USB0_BASE);
+
+ //
+ // Set the USB controller mode to device.
+ //
+ HWREGB(ulBase + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD;
+}
+
+//*****************************************************************************
+//
+//! Powers off the USB PHY.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will power off the USB PHY, reducing the current consuption
+//! of the device. While in the powered off state, the USB controller will be
+//! unable to operate.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBPHYPowerOff(unsigned long ulBase)
+{
+ //
+ // Set the PWRDNPHY bit in the PHY, putting it into its low power mode.
+ //
+ HWREGB(ulBase + USB_O_POWER) |= USB_POWER_PWRDNPHY;
+}
+
+//*****************************************************************************
+//
+//! Powers on the USB PHY.
+//!
+//! \param ulBase specifies the USB module base address.
+//!
+//! This function will power on the USB PHY, enabling it return to normal
+//! operation. By default, the PHY is powered on, so this function only needs
+//! to be called if USBPHYPowerOff() has previously been called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+USBPHYPowerOn(unsigned long ulBase)
+{
+ //
+ // Clear the PWRDNPHY bit in the PHY, putting it into normal operating
+ // mode.
+ //
+ HWREGB(ulBase + USB_O_POWER) &= ~USB_POWER_PWRDNPHY;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/usb.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/usb.h
new file mode 100644
index 00000000..c5b3b7f2
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/usb.h
@@ -0,0 +1,567 @@
+//*****************************************************************************
+//
+// usb.h - Prototypes for the USB Interface Driver.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __USB_H__
+#define __USB_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBIntEnableControl() and
+// USBIntDisableControl() as the ulFlags parameter, and are returned from
+// USBIntStatusControl().
+//
+//*****************************************************************************
+#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources
+#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts
+#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error
+#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected
+#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected
+#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected
+#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected
+#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected
+#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled
+#define USB_INTCTRL_RESET 0x00000004 // Reset signaled
+#define USB_INTCTRL_RESUME 0x00000002 // Resume detected
+#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected
+#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid
+#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBIntEnableEndpoint() and
+// USBIntDisableEndpoint() as the ulFlags parameter, and are returned from
+// USBIntStatusEndpoint().
+//
+//*****************************************************************************
+#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts
+#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts
+#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt
+#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt
+#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt
+#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt
+#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt
+#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt
+#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt
+#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt
+#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt
+#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt
+#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt
+#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt
+#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt
+#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt
+#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt
+
+#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts
+#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt
+#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt
+
+#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts
+#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt
+#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt
+
+#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts
+#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt
+#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt
+#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt
+#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt
+#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt
+#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt
+#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt
+#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt
+#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt
+#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt
+#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt
+#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt
+#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt
+#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt
+#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt
+
+#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are values that are returned from USBSpeedGet().
+//
+//*****************************************************************************
+#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined
+#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed
+#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed
+
+//*****************************************************************************
+//
+// The following are values that are returned from USBEndpointStatus(). The
+// USB_HOST_* values are used when the USB controller is in host mode and the
+// USB_DEV_* values are used when the USB controller is in device mode.
+//
+//*****************************************************************************
+#define USB_HOST_IN_PID_ERROR 0x01000000 // Stall on this endpoint received
+#define USB_HOST_IN_NOT_COMP 0x00100000 // Device failed to respond
+#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received
+#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error
+ // (ISOC Mode)
+#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the
+ // specified timeout period
+#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a
+ // device
+#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full
+#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready
+#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the
+ // specified timeout period
+#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device
+ // (ISOC mode)
+#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received
+#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a
+ // device
+#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty
+#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted
+#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the
+ // specified timeout period
+#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet
+#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a
+ // device
+#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received
+#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready
+#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint
+#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data
+#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to
+ // a full FIFO
+#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full
+#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready
+#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data
+ // to come
+#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint
+#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready
+#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty
+#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted
+#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before
+ // Data End seen
+#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint
+#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending
+#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBHostEndpointConfig() and
+// USBDevEndpointConfigSet() as the ulFlags parameter.
+//
+//*****************************************************************************
+#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled
+#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled
+#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled
+#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0
+#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1
+#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint
+#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint
+#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint
+#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint
+#define USB_EP_MODE_MASK 0x00000300 // Mode Mask
+#define USB_EP_SPEED_LOW 0x00000000 // Low Speed
+#define USB_EP_SPEED_FULL 0x00001000 // Full Speed
+#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint
+#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint
+#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint
+#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBHostPwrConfig() as
+// the ulFlags parameter.
+//
+//*****************************************************************************
+#define USB_HOST_PWRFLT_LOW 0x00000010
+#define USB_HOST_PWRFLT_HIGH 0x00000030
+#define USB_HOST_PWRFLT_EP_NONE 0x00000000
+#define USB_HOST_PWRFLT_EP_TRI 0x00000140
+#define USB_HOST_PWRFLT_EP_LOW 0x00000240
+#define USB_HOST_PWRFLT_EP_HIGH 0x00000340
+#ifndef DEPRECATED
+#define USB_HOST_PWREN_LOW 0x00000002
+#define USB_HOST_PWREN_HIGH 0x00000003
+#define USB_HOST_PWREN_VBLOW 0x00000002
+#define USB_HOST_PWREN_VBHIGH 0x00000003
+#endif
+#define USB_HOST_PWREN_MAN_LOW 0x00000000
+#define USB_HOST_PWREN_MAN_HIGH 0x00000001
+#define USB_HOST_PWREN_AUTOLOW 0x00000002
+#define USB_HOST_PWREN_AUTOHIGH 0x00000003
+#define USB_HOST_PWREN_FILTER 0x00010000
+
+//*****************************************************************************
+//
+// The following are special values that can be passed to
+// USBHostEndpointConfig() as the ulNAKPollInterval parameter.
+//
+//*****************************************************************************
+#define MAX_NAK_LIMIT 31 // Maximum NAK interval
+#define DISABLE_NAK_LIMIT 0 // No NAK timeouts
+
+//*****************************************************************************
+//
+// This value specifies the maximum size of transfers on endpoint 0 as 64
+// bytes. This value is fixed in hardware as the FIFO size for endpoint 0.
+//
+//*****************************************************************************
+#define MAX_PACKET_SIZE_EP0 64
+
+//*****************************************************************************
+//
+// These values are used to indicate which endpoint to access.
+//
+//*****************************************************************************
+#define USB_EP_0 0x00000000 // Endpoint 0
+#define USB_EP_1 0x00000010 // Endpoint 1
+#define USB_EP_2 0x00000020 // Endpoint 2
+#define USB_EP_3 0x00000030 // Endpoint 3
+#define USB_EP_4 0x00000040 // Endpoint 4
+#define USB_EP_5 0x00000050 // Endpoint 5
+#define USB_EP_6 0x00000060 // Endpoint 6
+#define USB_EP_7 0x00000070 // Endpoint 7
+#define USB_EP_8 0x00000080 // Endpoint 8
+#define USB_EP_9 0x00000090 // Endpoint 9
+#define USB_EP_10 0x000000A0 // Endpoint 10
+#define USB_EP_11 0x000000B0 // Endpoint 11
+#define USB_EP_12 0x000000C0 // Endpoint 12
+#define USB_EP_13 0x000000D0 // Endpoint 13
+#define USB_EP_14 0x000000E0 // Endpoint 14
+#define USB_EP_15 0x000000F0 // Endpoint 15
+#define NUM_USB_EP 16 // Number of supported endpoints
+
+//*****************************************************************************
+//
+// These macros allow conversion between 0-based endpoint indices and the
+// USB_EP_x values required when calling various USB APIs.
+//
+//*****************************************************************************
+#define INDEX_TO_USB_EP(x) ((x) << 4)
+#define USB_EP_TO_INDEX(x) ((x) >> 4)
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBFIFOConfigSet() as the
+// ulFIFOSize parameter.
+//
+//*****************************************************************************
+#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO
+#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO
+#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO
+#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO
+#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO
+#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO
+#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO
+#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO
+#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO
+#define USB_FIFO_SZ_4096 0x00000009 // 4096 byte FIFO
+#define USB_FIFO_SZ_8_DB 0x00000010 // 8 byte double buffered FIFO
+ // (occupying 16 bytes)
+#define USB_FIFO_SZ_16_DB 0x00000011 // 16 byte double buffered FIFO
+ // (occupying 32 bytes)
+#define USB_FIFO_SZ_32_DB 0x00000012 // 32 byte double buffered FIFO
+ // (occupying 64 bytes)
+#define USB_FIFO_SZ_64_DB 0x00000013 // 64 byte double buffered FIFO
+ // (occupying 128 bytes)
+#define USB_FIFO_SZ_128_DB 0x00000014 // 128 byte double buffered FIFO
+ // (occupying 256 bytes)
+#define USB_FIFO_SZ_256_DB 0x00000015 // 256 byte double buffered FIFO
+ // (occupying 512 bytes)
+#define USB_FIFO_SZ_512_DB 0x00000016 // 512 byte double buffered FIFO
+ // (occupying 1024 bytes)
+#define USB_FIFO_SZ_1024_DB 0x00000017 // 1024 byte double buffered FIFO
+ // (occupying 2048 bytes)
+#define USB_FIFO_SZ_2048_DB 0x00000018 // 2048 byte double buffered FIFO
+ // (occupying 4096 bytes)
+
+//*****************************************************************************
+//
+// This macro allow conversion from a FIFO size label as defined above to
+// a number of bytes
+//
+//*****************************************************************************
+#define USB_FIFO_SIZE_DB_FLAG 0x00000010
+#define USB_FIFO_SZ_TO_BYTES(x) ((8 << ((x) & ~ USB_FIFO_SIZE_DB_FLAG)) * \
+ (((x) & USB_FIFO_SIZE_DB_FLAG) ? 2 : 1))
+
+//*****************************************************************************
+//
+// The following are values that can be passed to USBEndpointDataSend() as the
+// ulTransType parameter.
+//
+//*****************************************************************************
+#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction
+#define USB_TRANS_IN 0x00000102 // Normal IN transaction
+#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for
+ // endpoint 0 in device mode)
+#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint
+ // 0)
+#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint
+ // 0)
+
+//*****************************************************************************
+//
+// The following are values are returned by the USBModeGet function.
+//
+//*****************************************************************************
+#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host
+ // mode.
+#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in
+ // Device mode.
+#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not
+ // set.
+#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of
+ // the cable.
+#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of
+ // the cable.
+#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of
+ // the cable Session Valid.
+#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of
+ // the cable A valid.
+#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of
+ // the cable.
+#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of
+ // the cable.
+#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of
+ // the cable.
+#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of
+ // the cable.
+#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set.
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern unsigned long USBDevAddrGet(unsigned long ulBase);
+extern void USBDevAddrSet(unsigned long ulBase, unsigned long ulAddress);
+extern void USBDevConnect(unsigned long ulBase);
+extern void USBDevDisconnect(unsigned long ulBase);
+extern void USBDevEndpointConfigSet(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulMaxPacketSize,
+ unsigned long ulFlags);
+extern void USBDevEndpointConfigGet(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long *pulMaxPacketSize,
+ unsigned long *pulFlags);
+extern void USBDevEndpointDataAck(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ tBoolean bIsLastPacket);
+extern void USBDevEndpointStall(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern void USBDevEndpointStallClear(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern void USBDevEndpointStatusClear(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern unsigned long USBEndpointDataAvail(unsigned long ulBase,
+ unsigned long ulEndpoint);
+extern void USBEndpointDMAEnable(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern void USBEndpointDMADisable(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern long USBEndpointDataGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned char *pucData, unsigned long *pulSize);
+extern long USBEndpointDataPut(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned char *pucData, unsigned long ulSize);
+extern long USBEndpointDataSend(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulTransType);
+extern void USBEndpointDataToggleClear(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern unsigned long USBEndpointStatus(unsigned long ulBase,
+ unsigned long ulEndpoint);
+extern unsigned long USBFIFOAddrGet(unsigned long ulBase,
+ unsigned long ulEndpoint);
+extern void USBFIFOConfigGet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long *pulFIFOAddress,
+ unsigned long *pulFIFOSize,
+ unsigned long ulFlags);
+extern void USBFIFOConfigSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFIFOAddress,
+ unsigned long ulFIFOSize, unsigned long ulFlags);
+extern void USBFIFOFlush(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern unsigned long USBFrameNumberGet(unsigned long ulBase);
+extern unsigned long USBHostAddrGet(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern void USBHostAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulAddr, unsigned long ulFlags);
+extern void USBHostEndpointConfig(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulMaxPacketSize,
+ unsigned long ulNAKPollInterval,
+ unsigned long ulTargetEndpoint,
+ unsigned long ulFlags);
+extern void USBHostEndpointDataAck(unsigned long ulBase,
+ unsigned long ulEndpoint);
+extern void USBHostEndpointDataToggle(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ tBoolean bDataToggle,
+ unsigned long ulFlags);
+extern void USBHostEndpointStatusClear(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern unsigned long USBHostHubAddrGet(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulFlags);
+extern void USBHostHubAddrSet(unsigned long ulBase, unsigned long ulEndpoint,
+ unsigned long ulAddr, unsigned long ulFlags);
+extern void USBHostPwrDisable(unsigned long ulBase);
+extern void USBHostPwrEnable(unsigned long ulBase);
+extern void USBHostPwrConfig(unsigned long ulBase, unsigned long ulFlags);
+#ifndef DEPRECATED
+#define USBHostPwrFaultConfig USBHostPwrConfig
+#endif
+extern void USBHostPwrFaultDisable(unsigned long ulBase);
+extern void USBHostPwrFaultEnable(unsigned long ulBase);
+extern void USBHostRequestIN(unsigned long ulBase, unsigned long ulEndpoint);
+extern void USBHostRequestStatus(unsigned long ulBase);
+extern void USBHostReset(unsigned long ulBase, tBoolean bStart);
+extern void USBHostResume(unsigned long ulBase, tBoolean bStart);
+extern unsigned long USBHostSpeedGet(unsigned long ulBase);
+extern void USBHostSuspend(unsigned long ulBase);
+extern void USBIntDisableControl(unsigned long ulBase,
+ unsigned long ulIntFlags);
+extern void USBIntEnableControl(unsigned long ulBase,
+ unsigned long ulIntFlags);
+extern unsigned long USBIntStatusControl(unsigned long ulBase);
+extern void USBIntDisableEndpoint(unsigned long ulBase,
+ unsigned long ulIntFlags);
+extern void USBIntEnableEndpoint(unsigned long ulBase,
+ unsigned long ulIntFlags);
+extern unsigned long USBIntStatusEndpoint(unsigned long ulBase);
+extern void USBIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void USBIntUnregister(unsigned long ulBase);
+extern void USBOTGSessionRequest(unsigned long ulBase, tBoolean bStart);
+extern unsigned long USBModeGet(unsigned long ulBase);
+extern void USBEndpointDMAChannel(unsigned long ulBase,
+ unsigned long ulEndpoint,
+ unsigned long ulChannel);
+extern void USBHostMode(unsigned long ulBase);
+extern void USBHostMode(unsigned long ulBase);
+extern void USBDevMode(unsigned long ulBase);
+extern void USBPHYPowerOff(unsigned long ulBase);
+extern void USBPHYPowerOn(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Several USB APIs have been renamed, with the original function name being
+// deprecated. These defines and function protypes provide backward
+// compatibility.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+//*****************************************************************************
+//
+// The following are values that can be passed to USBIntEnable() and
+// USBIntDisable() as the ulIntFlags parameter, and are returned from
+// USBIntStatus().
+//
+//*****************************************************************************
+#define USB_INT_ALL 0xFF030E0F // All Interrupt sources
+#define USB_INT_STATUS 0xFF000000 // Status Interrupts
+#define USB_INT_VBUS_ERR 0x80000000 // VBUS Error
+#define USB_INT_SESSION_START 0x40000000 // Session Start Detected
+#define USB_INT_SESSION_END 0x20000000 // Session End Detected
+#define USB_INT_DISCONNECT 0x20000000 // Disconnect Detected
+#define USB_INT_CONNECT 0x10000000 // Device Connect Detected
+#define USB_INT_SOF 0x08000000 // Start of Frame Detected
+#define USB_INT_BABBLE 0x04000000 // Babble signaled
+#define USB_INT_RESET 0x04000000 // Reset signaled
+#define USB_INT_RESUME 0x02000000 // Resume detected
+#define USB_INT_SUSPEND 0x01000000 // Suspend detected
+#define USB_INT_MODE_DETECT 0x00020000 // Mode value valid
+#define USB_INT_POWER_FAULT 0x00010000 // Power Fault detected
+#define USB_INT_HOST_IN 0x00000E00 // Host IN Interrupts
+#define USB_INT_DEV_OUT 0x00000E00 // Device OUT Interrupts
+#define USB_INT_HOST_IN_EP3 0x00000800 // Endpoint 3 Host IN Interrupt
+#define USB_INT_HOST_IN_EP2 0x00000400 // Endpoint 2 Host IN Interrupt
+#define USB_INT_HOST_IN_EP1 0x00000200 // Endpoint 1 Host IN Interrupt
+#define USB_INT_DEV_OUT_EP3 0x00000800 // Endpoint 3 Device OUT Interrupt
+#define USB_INT_DEV_OUT_EP2 0x00000400 // Endpoint 2 Device OUT Interrupt
+#define USB_INT_DEV_OUT_EP1 0x00000200 // Endpoint 1 Device OUT Interrupt
+#define USB_INT_HOST_OUT 0x0000000E // Host OUT Interrupts
+#define USB_INT_DEV_IN 0x0000000E // Device IN Interrupts
+#define USB_INT_HOST_OUT_EP3 0x00000008 // Endpoint 3 HOST_OUT Interrupt
+#define USB_INT_HOST_OUT_EP2 0x00000004 // Endpoint 2 HOST_OUT Interrupt
+#define USB_INT_HOST_OUT_EP1 0x00000002 // Endpoint 1 HOST_OUT Interrupt
+#define USB_INT_DEV_IN_EP3 0x00000008 // Endpoint 3 DEV_IN Interrupt
+#define USB_INT_DEV_IN_EP2 0x00000004 // Endpoint 2 DEV_IN Interrupt
+#define USB_INT_DEV_IN_EP1 0x00000002 // Endpoint 1 DEV_IN Interrupt
+#define USB_INT_EP0 0x00000001 // Endpoint 0 Interrupt
+
+#define USBDevEndpointConfig USBDevEndpointConfigSet
+extern void USBIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void USBIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long USBIntStatus(unsigned long ulBase);
+#endif
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USB_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/watchdog.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/watchdog.c
new file mode 100644
index 00000000..e9d66c9d
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/watchdog.c
@@ -0,0 +1,564 @@
+//*****************************************************************************
+//
+// watchdog.c - Driver for the Watchdog Timer Module.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup watchdog_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_watchdog.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/watchdog.h"
+
+//*****************************************************************************
+//
+//! Determines if the watchdog timer is enabled.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This will check to see if the watchdog timer is enabled.
+//!
+//! \return Returns \b true if the watchdog timer is enabled, and \b false
+//! if it is not.
+//
+//*****************************************************************************
+tBoolean
+WatchdogRunning(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // See if the watchdog timer module is enabled, and return.
+ //
+ return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This will enable the watchdog timer counter and interrupt.
+//!
+//! \note This function will have no effect if the watchdog timer has
+//! been locked.
+//!
+//! \sa WatchdogLock(), WatchdogUnlock()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Enable the watchdog timer module.
+ //
+ HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer reset.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Enables the capability of the watchdog timer to issue a reset to the
+//! processor upon a second timeout condition.
+//!
+//! \note This function will have no effect if the watchdog timer has
+//! been locked.
+//!
+//! \sa WatchdogLock(), WatchdogUnlock()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogResetEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Enable the watchdog reset.
+ //
+ HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the watchdog timer reset.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Disables the capability of the watchdog timer to issue a reset to the
+//! processor upon a second timeout condition.
+//!
+//! \note This function will have no effect if the watchdog timer has
+//! been locked.
+//!
+//! \sa WatchdogLock(), WatchdogUnlock()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogResetDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Disable the watchdog reset.
+ //
+ HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer lock mechanism.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Locks out write access to the watchdog timer configuration registers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogLock(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
+ // register causes the lock to go into effect.
+ //
+ HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
+}
+
+//*****************************************************************************
+//
+//! Disables the watchdog timer lock mechanism.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Enables write access to the watchdog timer configuration registers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogUnlock(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Unlock watchdog register writes.
+ //
+ HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
+}
+
+//*****************************************************************************
+//
+//! Gets the state of the watchdog timer lock mechanism.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Returns the lock state of the watchdog timer registers.
+//!
+//! \return Returns \b true if the watchdog timer registers are locked, and
+//! \b false if they are not locked.
+//
+//*****************************************************************************
+tBoolean
+WatchdogLockState(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Get the lock state.
+ //
+ return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Sets the watchdog timer reload value.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//! \param ulLoadVal is the load value for the watchdog timer.
+//!
+//! This function sets the value to load into the watchdog timer when the count
+//! reaches zero for the first time; if the watchdog timer is running when this
+//! function is called, then the value will be immediately loaded into the
+//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an
+//! interrupt is immediately generated.
+//!
+//! \note This function will have no effect if the watchdog timer has
+//! been locked.
+//!
+//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Set the load register.
+ //
+ HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
+}
+
+//*****************************************************************************
+//
+//! Gets the watchdog timer reload value.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function gets the value that is loaded into the watchdog timer when
+//! the count reaches zero for the first time.
+//!
+//! \sa WatchdogReloadSet()
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long
+WatchdogReloadGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Get the load register.
+ //
+ return(HWREG(ulBase + WDT_O_LOAD));
+}
+
+//*****************************************************************************
+//
+//! Gets the current watchdog timer value.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function reads the current value of the watchdog timer.
+//!
+//! \return Returns the current value of the watchdog timer.
+//
+//*****************************************************************************
+unsigned long
+WatchdogValueGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Get the current watchdog timer register value.
+ //
+ return(HWREG(ulBase + WDT_O_VALUE));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for watchdog timer interrupt.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! watchdog timer interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! will enable the global interrupt in the interrupt controller; the watchdog
+//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source via
+//! WatchdogIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_WATCHDOG, pfnHandler);
+
+ //
+ // Enable the watchdog timer interrupt.
+ //
+ IntEnable(INT_WATCHDOG);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the watchdog timer interrupt.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function does the actual unregistering of the interrupt handler. This
+//! function will clear the handler to be called when a watchdog timer
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_WATCHDOG);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_WATCHDOG);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer interrupt.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Enables the watchdog timer interrupt.
+//!
+//! \note This function will have no effect if the watchdog timer has
+//! been locked.
+//!
+//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Enable the watchdog interrupt.
+ //
+ HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Gets the current watchdog timer interrupt status.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the watchdog timer module. Either
+//! the raw interrupt status or the status of interrupt that is allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, where a 1 indicates that the
+//! watchdog interrupt is active, and a 0 indicates that it is not active.
+//
+//*****************************************************************************
+unsigned long
+WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + WDT_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + WDT_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the watchdog timer interrupt.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! The watchdog timer interrupt source is cleared, so that it no longer
+//! asserts.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Clear the interrupt source.
+ //
+ HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
+}
+
+//*****************************************************************************
+//
+//! Enables stalling of the watchdog timer during debug events.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function allows the watchdog timer to stop counting when the processor
+//! is stopped by the debugger. By doing so, the watchdog is prevented from
+//! expiring (typically almost immediately from a human time perspective) and
+//! resetting the system (if reset is enabled). The watchdog will instead
+//! expired after the appropriate number of processor cycles have been executed
+//! while debugging (or at the appropriate time after the processor has been
+//! restarted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogStallEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Enable timer stalling.
+ //
+ HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
+}
+
+//*****************************************************************************
+//
+//! Disables stalling of the watchdog timer during debug events.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function disables the debug mode stall of the watchdog timer. By
+//! doing so, the watchdog timer continues to count regardless of the processor
+//! debug state.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogStallDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
+
+ //
+ // Disable timer stalling.
+ //
+ HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/watchdog.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/watchdog.h
new file mode 100644
index 00000000..93b38879
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/driverlib/watchdog.h
@@ -0,0 +1,71 @@
+//*****************************************************************************
+//
+// watchdog.h - Prototypes for the Watchdog Timer API
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __WATCHDOG_H__
+#define __WATCHDOG_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern tBoolean WatchdogRunning(unsigned long ulBase);
+extern void WatchdogEnable(unsigned long ulBase);
+extern void WatchdogResetEnable(unsigned long ulBase);
+extern void WatchdogResetDisable(unsigned long ulBase);
+extern void WatchdogLock(unsigned long ulBase);
+extern void WatchdogUnlock(unsigned long ulBase);
+extern tBoolean WatchdogLockState(unsigned long ulBase);
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);
+extern unsigned long WatchdogValueGet(unsigned long ulBase);
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void WatchdogIntUnregister(unsigned long ulBase);
+extern void WatchdogIntEnable(unsigned long ulBase);
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void WatchdogIntClear(unsigned long ulBase);
+extern void WatchdogStallEnable(unsigned long ulBase);
+extern void WatchdogStallDisable(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __WATCHDOG_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/asmdefs.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/asmdefs.h
new file mode 100644
index 00000000..6a134fd1
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/asmdefs.h
@@ -0,0 +1,212 @@
+//*****************************************************************************
+//
+// asmdefs.h - Macros to allow assembly code be portable among toolchains.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __ASMDEFS_H__
+#define __ASMDEFS_H__
+
+//*****************************************************************************
+//
+// The defines required for code_red.
+//
+//*****************************************************************************
+#ifdef codered
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // codered
+
+//*****************************************************************************
+//
+// The defines required for EW-ARM.
+//
+//*****************************************************************************
+#ifdef ewarm
+
+//
+// Section headers.
+//
+#define __LIBRARY__ module
+#define __TEXT__ rseg CODE:CODE(2)
+#define __DATA__ rseg DATA:DATA(2)
+#define __BSS__ rseg DATA:DATA(2)
+#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ alignrom 2
+#define __END__ end
+#define __EXPORT__ export
+#define __IMPORT__ import
+#define __LABEL__
+#define __STR__ dcb
+#define __THUMB_LABEL__ thumb
+#define __WORD__ dcd
+#define __INLINE_DATA__ data
+
+#endif // ewarm
+
+//*****************************************************************************
+//
+// The defines required for GCC.
+//
+//*****************************************************************************
+#if defined(gcc)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // gcc
+
+//*****************************************************************************
+//
+// The defines required for RV-MDK.
+//
+//*****************************************************************************
+#ifdef rvmdk
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ thumb
+ require8
+ preserve8
+
+//
+// Section headers.
+//
+#define __LIBRARY__ ;
+#define __TEXT__ area ||.text||, code, readonly, align=2
+#define __DATA__ area ||.data||, data, align=2
+#define __BSS__ area ||.bss||, noinit, align=2
+#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ align 4
+#define __END__ end
+#define __EXPORT__ export
+#define __IMPORT__ import
+#define __LABEL__
+#define __STR__ dcb
+#define __THUMB_LABEL__
+#define __WORD__ dcd
+#define __INLINE_DATA__
+
+#endif // rvmdk
+
+//*****************************************************************************
+//
+// The defines required for Sourcery G++.
+//
+//*****************************************************************************
+#if defined(sourcerygxx)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // sourcerygxx
+
+#endif // __ASMDEF_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_adc.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_adc.h
new file mode 100644
index 00000000..872ad6f5
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_adc.h
@@ -0,0 +1,1193 @@
+//*****************************************************************************
+//
+// hw_adc.h - Macros used when accessing the ADC hardware.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ADC_H__
+#define __HW_ADC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_O_ACTSS 0x00000000 // ADC Active Sample Sequencer
+#define ADC_O_RIS 0x00000004 // ADC Raw Interrupt Status
+#define ADC_O_IM 0x00000008 // ADC Interrupt Mask
+#define ADC_O_ISC 0x0000000C // ADC Interrupt Status and Clear
+#define ADC_O_OSTAT 0x00000010 // ADC Overflow Status
+#define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select
+#define ADC_O_USTAT 0x00000018 // ADC Underflow Status
+#define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority
+#define ADC_O_SPC 0x00000024 // ADC Sample Phase Control
+#define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence
+ // Initiate
+#define ADC_O_SAC 0x00000030 // ADC Sample Averaging Control
+#define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt
+ // Status and Clear
+#define ADC_O_CTL 0x00000038 // ADC Control
+#define ADC_O_SSMUX0 0x00000040 // ADC Sample Sequence Input
+ // Multiplexer Select 0
+#define ADC_O_SSCTL0 0x00000044 // ADC Sample Sequence Control 0
+#define ADC_O_SSFIFO0 0x00000048 // ADC Sample Sequence Result FIFO
+ // 0
+#define ADC_O_SSFSTAT0 0x0000004C // ADC Sample Sequence FIFO 0
+ // Status
+#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation
+#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital
+ // Comparator Select
+#define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input
+ // Multiplexer Select 1
+#define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1
+#define ADC_O_SSFIFO1 0x00000068 // ADC Sample Sequence Result FIFO
+ // 1
+#define ADC_O_SSFSTAT1 0x0000006C // ADC Sample Sequence FIFO 1
+ // Status
+#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation
+#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital
+ // Comparator Select
+#define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input
+ // Multiplexer Select 2
+#define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2
+#define ADC_O_SSFIFO2 0x00000088 // ADC Sample Sequence Result FIFO
+ // 2
+#define ADC_O_SSFSTAT2 0x0000008C // ADC Sample Sequence FIFO 2
+ // Status
+#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation
+#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital
+ // Comparator Select
+#define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input
+ // Multiplexer Select 3
+#define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3
+#define ADC_O_SSFIFO3 0x000000A8 // ADC Sample Sequence Result FIFO
+ // 3
+#define ADC_O_SSFSTAT3 0x000000AC // ADC Sample Sequence FIFO 3
+ // Status
+#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation
+#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital
+ // Comparator Select
+#define ADC_O_TMLB 0x00000100 // ADC Test Mode Loopback
+#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset
+ // Initial Conditions
+#define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0
+#define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1
+#define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2
+#define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3
+#define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4
+#define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5
+#define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6
+#define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7
+#define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0
+#define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1
+#define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2
+#define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3
+#define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4
+#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5
+#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6
+#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt
+ // Status
+#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on
+ // SS3
+#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on
+ // SS2
+#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on
+ // SS1
+#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on
+ // SS0
+#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask
+#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask
+#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask
+#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt
+ // Status on SS3
+#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt
+ // Status on SS2
+#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt
+ // Status on SS1
+#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt
+ // Status on SS0
+#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2
+#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM3
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
+#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2
+#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM3
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
+#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2
+#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM3
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
+#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2
+#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM3
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow
+#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow
+#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow
+#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
+#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
+#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
+#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SPC register.
+//
+//*****************************************************************************
+#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference
+#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize
+#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait
+#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate
+#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate
+#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate
+#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt
+ // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CTL register.
+//
+//*****************************************************************************
+#define ADC_CTL_VREF 0x00000001 // Voltage Reference Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S 28
+#define ADC_SSMUX0_MUX6_S 24
+#define ADC_SSMUX0_MUX5_S 20
+#define ADC_SSMUX0_MUX4_S 16
+#define ADC_SSMUX0_MUX3_S 12
+#define ADC_SSMUX0_MUX2_S 8
+#define ADC_SSMUX0_MUX1_S 4
+#define ADC_SSMUX0_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S 4
+#define ADC_SSFSTAT0_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator
+ // Select
+#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator
+ // Select
+#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator
+ // Select
+#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator
+ // Select
+#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC0_S6DCSEL_S 24
+#define ADC_SSDC0_S5DCSEL_S 20
+#define ADC_SSDC0_S4DCSEL_S 16
+#define ADC_SSDC0_S3DCSEL_S 12
+#define ADC_SSDC0_S2DCSEL_S 8
+#define ADC_SSDC0_S1DCSEL_S 4
+#define ADC_SSDC0_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S 12
+#define ADC_SSMUX1_MUX2_S 8
+#define ADC_SSMUX1_MUX1_S 4
+#define ADC_SSMUX1_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S 4
+#define ADC_SSFSTAT1_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC1_S2DCSEL_S 8
+#define ADC_SSDC1_S1DCSEL_S 4
+#define ADC_SSDC1_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S 12
+#define ADC_SSMUX2_MUX2_S 8
+#define ADC_SSMUX2_MUX1_S 4
+#define ADC_SSMUX2_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S 4
+#define ADC_SSFSTAT2_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC2_S2DCSEL_S 8
+#define ADC_SSDC2_S1DCSEL_S 4
+#define ADC_SSDC2_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S 4
+#define ADC_SSFSTAT3_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TMLB register.
+//
+//*****************************************************************************
+#define ADC_TMLB_LB 0x00000001 // Loopback Mode Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M 0x03FF0000 // Compare 1
+#define ADC_DCCMP0_COMP0_M 0x000003FF // Compare 0
+#define ADC_DCCMP0_COMP1_S 16
+#define ADC_DCCMP0_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M 0x03FF0000 // Compare 1
+#define ADC_DCCMP1_COMP0_M 0x000003FF // Compare 0
+#define ADC_DCCMP1_COMP1_S 16
+#define ADC_DCCMP1_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M 0x03FF0000 // Compare 1
+#define ADC_DCCMP2_COMP0_M 0x000003FF // Compare 0
+#define ADC_DCCMP2_COMP1_S 16
+#define ADC_DCCMP2_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M 0x03FF0000 // Compare 1
+#define ADC_DCCMP3_COMP0_M 0x000003FF // Compare 0
+#define ADC_DCCMP3_COMP1_S 16
+#define ADC_DCCMP3_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M 0x03FF0000 // Compare 1
+#define ADC_DCCMP4_COMP0_M 0x000003FF // Compare 0
+#define ADC_DCCMP4_COMP1_S 16
+#define ADC_DCCMP4_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M 0x03FF0000 // Compare 1
+#define ADC_DCCMP5_COMP0_M 0x000003FF // Compare 0
+#define ADC_DCCMP5_COMP1_S 16
+#define ADC_DCCMP5_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M 0x03FF0000 // Compare 1
+#define ADC_DCCMP6_COMP0_M 0x000003FF // Compare 0
+#define ADC_DCCMP6_COMP1_S 16
+#define ADC_DCCMP6_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M 0x03FF0000 // Compare 1
+#define ADC_DCCMP7_COMP0_M 0x000003FF // Compare 0
+#define ADC_DCCMP7_COMP1_S 16
+#define ADC_DCCMP7_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter
+#define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator
+#define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator
+#define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator
+#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator
+#define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_O_EMUX
+// register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask
+#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask
+#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask
+#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask
+#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event
+#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event
+#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event
+#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_O_SSPRI
+// register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask
+#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask
+#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask
+#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the ADC sequence register offsets..
+//
+//*****************************************************************************
+#define ADC_O_SEQ 0x00000040 // Offset to the first sequence
+#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence
+#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register
+#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register
+#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register
+#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSMUX0,
+// ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present
+// in all registers..
+//
+//*****************************************************************************
+#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask
+#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask
+#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask
+#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask
+#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask
+#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask
+#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask
+#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask
+#define ADC_SSMUX_MUX7_SHIFT 28
+#define ADC_SSMUX_MUX6_SHIFT 24
+#define ADC_SSMUX_MUX5_SHIFT 20
+#define ADC_SSMUX_MUX4_SHIFT 16
+#define ADC_SSMUX_MUX3_SHIFT 12
+#define ADC_SSMUX_MUX2_SHIFT 8
+#define ADC_SSMUX_MUX1_SHIFT 4
+#define ADC_SSMUX_MUX0_SHIFT 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSCTL0,
+// ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present
+// in all registers.
+//
+//*****************************************************************************
+#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select
+#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable
+#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select
+#define ADC_SSCTL_D7 0x10000000 // 8th differential select
+#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select
+#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable
+#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select
+#define ADC_SSCTL_D6 0x01000000 // 7th differential select
+#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select
+#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable
+#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select
+#define ADC_SSCTL_D5 0x00100000 // 6th differential select
+#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select
+#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable
+#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select
+#define ADC_SSCTL_D4 0x00010000 // 5th differential select
+#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select
+#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable
+#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select
+#define ADC_SSCTL_D3 0x00001000 // 4th differential select
+#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select
+#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable
+#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select
+#define ADC_SSCTL_D2 0x00000100 // 3rd differential select
+#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select
+#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable
+#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select
+#define ADC_SSCTL_D1 0x00000010 // 2nd differential select
+#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select
+#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable
+#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select
+#define ADC_SSCTL_D0 0x00000001 // 1st differential select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSFIFO0,
+// ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data
+#define ADC_SSFIFO_DATA_SHIFT 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSFSTAT0,
+// ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full
+#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty
+#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer
+#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the the interpretation of the data
+// in the SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter
+#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator
+#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator
+#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator
+#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator
+#define ADC_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the loopback ADC
+// data.
+//
+//*****************************************************************************
+#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask
+#define ADC_LB_CONT 0x00000020 // Continuation sample
+#define ADC_LB_DIFF 0x00000010 // Differential sample
+#define ADC_LB_TS 0x00000008 // Temperature sensor sample
+#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask
+#define ADC_LB_CNT_SHIFT 6 // Sample counter shift
+#define ADC_LB_MUX_SHIFT 0 // Input channel number shift
+
+#endif
+
+#endif // __HW_ADC_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_comp.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_comp.h
new file mode 100644
index 00000000..4b58bbf5
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_comp.h
@@ -0,0 +1,277 @@
+//*****************************************************************************
+//
+// hw_comp.h - Macros used when accessing the comparator hardware.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_COMP_H__
+#define __HW_COMP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Comparator register offsets.
+//
+//*****************************************************************************
+#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked
+ // Interrupt Status
+#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt
+ // Status
+#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt
+ // Enable
+#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference
+ // Voltage Control
+#define COMP_O_ACSTAT0 0x00000020 // Analog Comparator Status 0
+#define COMP_O_ACCTL0 0x00000024 // Analog Comparator Control 0
+#define COMP_O_ACSTAT1 0x00000040 // Analog Comparator Status 1
+#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1
+#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2
+#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
+ // Status
+#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
+ // Status
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status
+#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable
+#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Comparator register offsets.
+//
+//*****************************************************************************
+#define COMP_O_MIS 0x00000000 // Interrupt status register
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_O_REFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable
+#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range
+#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask
+#define COMP_REFCTL_VREF_SHIFT 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_MIS,
+// COMP_RIS, and COMP_INTEN registers.
+//
+//*****************************************************************************
+#define COMP_INT_2 0x00000004 // Comp2 interrupt
+#define COMP_INT_1 0x00000002 // Comp1 interrupt
+#define COMP_INT_0 0x00000001 // Comp0 interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_ACSTAT0,
+// COMP_ACSTAT1, and COMP_ACSTAT2 registers.
+//
+//*****************************************************************************
+#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_ACCTL0,
+// COMP_ACCTL1, and COMP_ACCTL2 registers.
+//
+//*****************************************************************************
+#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable
+#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask
+#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
+#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin
+#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved
+#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable
+#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select
+#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask
+#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense
+#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge
+#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge
+#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges
+#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select
+#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask
+#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense
+#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge
+#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge
+#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges
+#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the comparator
+// registers.
+//
+//*****************************************************************************
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register
+#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register
+#define COMP_RV_RIS 0x00000000 // Raw interrupt status register
+#define COMP_RV_INTEN 0x00000000 // Interrupt enable register
+#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register
+#define COMP_RV_MIS 0x00000000 // Interrupt status register
+#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register
+#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg
+
+#endif
+
+#endif // __HW_COMP_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_epi.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_epi.h
new file mode 100644
index 00000000..8ed9d165
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_epi.h
@@ -0,0 +1,499 @@
+//*****************************************************************************
+//
+// hw_epi.h - Macros for use in accessing the EPI registers.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EPI_H__
+#define __HW_EPI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the External Peripheral Interface register
+// offsets.
+//
+//*****************************************************************************
+#define EPI_O_CFG 0x00000000 // EPI Configuration
+#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate
+#define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration
+#define EPI_O_GPCFG 0x00000010 // EPI General-Purpose
+ // Configuration
+#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration
+#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration
+#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2
+#define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2
+#define EPI_O_GPCFG2 0x00000014 // EPI General-Purpose
+ // Configuration 2
+#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map
+#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0
+#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0
+#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0
+#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1
+#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1
+#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1
+#define EPI_O_STAT 0x00000060 // EPI Status
+#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count
+#define EPI_O_READFIFO 0x00000070 // EPI Read FIFO
+#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1
+#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2
+#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3
+#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4
+#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5
+#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6
+#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7
+#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects
+#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count
+#define EPI_O_IM 0x00000210 // EPI Interrupt Mask
+#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status
+#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status
+#define EPI_O_EISC 0x0000021C // EPI Error Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_CFG register.
+//
+//*****************************************************************************
+#define EPI_CFG_BLKEN 0x00000010 // Block Enable
+#define EPI_CFG_MODE_M 0x0000000F // Mode Select
+#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose
+#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM
+#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8)
+#define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1
+#define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0
+#define EPI_BAUD_COUNT1_S 16
+#define EPI_BAUD_COUNT0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable
+#define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable
+#define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity
+#define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity
+#define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
+#define EPI_HB16CFG_WRWS_M 0x000000C0 // CS0n Write Wait States
+#define EPI_HB16CFG_WRWS_0 0x00000000 // No wait states
+#define EPI_HB16CFG_WRWS_1 0x00000040 // 1 wait state
+#define EPI_HB16CFG_WRWS_2 0x00000080 // 2 wait states
+#define EPI_HB16CFG_WRWS_3 0x000000C0 // 3 wait states
+#define EPI_HB16CFG_RDWS_M 0x00000030 // CS0n Read Wait States
+#define EPI_HB16CFG_RDWS_0 0x00000000 // No wait states
+#define EPI_HB16CFG_RDWS_1 0x00000010 // 1 wait state
+#define EPI_HB16CFG_RDWS_2 0x00000020 // 2 wait states
+#define EPI_HB16CFG_RDWS_3 0x00000030 // 3 wait states
+#define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration
+#define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode
+#define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
+#define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0]
+#define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0]
+#define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0]
+#define EPI_HB16CFG_MAXWAIT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG register.
+//
+//*****************************************************************************
+#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin
+#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated
+#define EPI_GPCFG_RDYEN 0x10000000 // Ready Enable
+#define EPI_GPCFG_FRMPIN 0x08000000 // Framing Pin
+#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame
+#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count
+#define EPI_GPCFG_RW 0x00200000 // Read and Write
+#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes
+#define EPI_GPCFG_RD2CYC 0x00040000 // 2-Cycle Reads
+#define EPI_GPCFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
+#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size
+#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address
+#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide
+#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size
+ // cannot be used with 24-bit data
+#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size
+ // cannot be used with data sizes
+ // other than 8
+#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus
+#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7)
+#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15)
+#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23)
+#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31)
+#define EPI_GPCFG_FRMCNT_S 22
+#define EPI_GPCFG_MAXWAIT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // Frequency Range
+#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz
+#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz
+#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz
+#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000 // 50 - 100 MHz
+#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter
+#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode
+#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM
+#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB)
+#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB)
+#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB)
+#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB)
+#define EPI_SDRAMCFG_RFSH_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable
+#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable
+#define EPI_HB8CFG_WRHIGH 0x00200000 // CS0n WRITE Strobe Polarity
+#define EPI_HB8CFG_RDHIGH 0x00100000 // CS0n READ Strobe Polarity
+#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
+#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States
+#define EPI_HB8CFG_WRWS_0 0x00000000 // No wait states
+#define EPI_HB8CFG_WRWS_1 0x00000040 // 1 wait state
+#define EPI_HB8CFG_WRWS_2 0x00000080 // 2 wait states
+#define EPI_HB8CFG_WRWS_3 0x000000C0 // 3 wait states
+#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States
+#define EPI_HB8CFG_RDWS_0 0x00000000 // No wait states
+#define EPI_HB8CFG_RDWS_1 0x00000010 // 1 wait state
+#define EPI_HB8CFG_RDWS_2 0x00000020 // 2 wait states
+#define EPI_HB8CFG_RDWS_3 0x00000030 // 3 wait states
+#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode
+#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0]
+#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0]
+#define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0]
+#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0]
+#define EPI_HB8CFG_MAXWAIT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG2_WORD 0x80000000 // Word Access Mode
+#define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate
+#define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration
+#define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration
+#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration
+#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
+#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG2_WORD 0x80000000 // Word Access Mode
+#define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate
+#define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration
+#define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration
+#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration
+#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
+#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG2 register.
+//
+//*****************************************************************************
+#define EPI_GPCFG2_WORD 0x80000000 // Word Access Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
+//
+//*****************************************************************************
+#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size
+#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range:
+ // 0x00 to 0xFF
+#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range:
+ // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range:
+ // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range:
+ // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address
+#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped
+#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000
+#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000
+#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size
+#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range:
+ // 0x00 to 0xFF
+#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range:
+ // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range:
+ // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range:
+ // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address
+#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped
+#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000
+#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size
+#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits)
+#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits)
+#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR0 register.
+//
+//*****************************************************************************
+#define EPI_RADDR0_ADDR_M 0x1FFFFFFF // Current Address
+#define EPI_RADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count
+#define EPI_RPSTD0_POSTCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size
+#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits)
+#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits)
+#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR1 register.
+//
+//*****************************************************************************
+#define EPI_RADDR1_ADDR_M 0x1FFFFFFF // Current Address
+#define EPI_RADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count
+#define EPI_RPSTD1_POSTCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_STAT register.
+//
+//*****************************************************************************
+#define EPI_STAT_CELOW 0x00000200 // Clock Enable Low
+#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full
+#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty
+#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence
+#define EPI_STAT_WBUSY 0x00000020 // Write Busy
+#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy
+#define EPI_STAT_ACTIVE 0x00000001 // Register Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_RFIFOCNT_COUNT_M 0x00000007 // FIFO Count
+#define EPI_RFIFOCNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO register.
+//
+//*****************************************************************************
+#define EPI_READFIFO_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO1
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO2
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO3
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO4
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO4_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO5
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO5_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO6
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO6_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO7
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO7_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
+//
+//*****************************************************************************
+#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error
+#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error
+#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO
+#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Trigger when there are 1 to 4
+ // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are 1 to 3
+ // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are 1 to 2
+ // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space
+ // available in the WFIFO
+#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO
+#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty
+#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries
+ // in the NBRFIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions
+#define EPI_WFIFOCNT_WTAV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_IM register.
+//
+//*****************************************************************************
+#define EPI_IM_WRIM 0x00000004 // Write Interrupt Mask
+#define EPI_IM_RDIM 0x00000002 // Read Interrupt Mask
+#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RIS register.
+//
+//*****************************************************************************
+#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status
+#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status
+#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_MIS register.
+//
+//*****************************************************************************
+#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status
+#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status
+#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_EISC register.
+//
+//*****************************************************************************
+#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error
+#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error
+#define EPI_EISC_TOUT 0x00000001 // Timeout Error
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the EPI_O_BAUD
+// register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT_M 0x0000FFFF // Baud Rate Counter
+#define EPI_BAUD_COUNT_S 0
+
+#endif
+
+#endif // __HW_EPI_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_ethernet.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_ethernet.h
new file mode 100644
index 00000000..742db3ff
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_ethernet.h
@@ -0,0 +1,679 @@
+//*****************************************************************************
+//
+// hw_ethernet.h - Macros used when accessing the Ethernet hardware.
+//
+// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ETHERNET_H__
+#define __HW_ETHERNET_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Ethernet MAC register offsets.
+//
+//*****************************************************************************
+#define MAC_O_RIS 0x00000000 // Ethernet MAC Raw Interrupt
+ // Status/Acknowledge
+#define MAC_O_IACK 0x00000000 // Ethernet MAC Raw Interrupt
+ // Status/Acknowledge
+#define MAC_O_IM 0x00000004 // Ethernet MAC Interrupt Mask
+#define MAC_O_RCTL 0x00000008 // Ethernet MAC Receive Control
+#define MAC_O_TCTL 0x0000000C // Ethernet MAC Transmit Control
+#define MAC_O_DATA 0x00000010 // Ethernet MAC Data
+#define MAC_O_IA0 0x00000014 // Ethernet MAC Individual Address
+ // 0
+#define MAC_O_IA1 0x00000018 // Ethernet MAC Individual Address
+ // 1
+#define MAC_O_THR 0x0000001C // Ethernet MAC Threshold
+#define MAC_O_MCTL 0x00000020 // Ethernet MAC Management Control
+#define MAC_O_MDV 0x00000024 // Ethernet MAC Management Divider
+#define MAC_O_MTXD 0x0000002C // Ethernet MAC Management Transmit
+ // Data
+#define MAC_O_MRXD 0x00000030 // Ethernet MAC Management Receive
+ // Data
+#define MAC_O_NP 0x00000034 // Ethernet MAC Number of Packets
+#define MAC_O_TR 0x00000038 // Ethernet MAC Transmission
+ // Request
+#define MAC_O_TS 0x0000003C // Ethernet MAC Timer Support
+#define MAC_O_LED 0x00000040 // Ethernet MAC LED Encoding
+#define MAC_O_MDIX 0x00000044 // Ethernet PHY MDIX
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt
+#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete
+#define MAC_RIS_RXER 0x00000010 // Receive Error
+#define MAC_RIS_FOV 0x00000008 // FIFO Overrun
+#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty
+#define MAC_RIS_TXER 0x00000002 // Transmit Error
+#define MAC_RIS_RXINT 0x00000001 // Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IACK register.
+//
+//*****************************************************************************
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt
+#define MAC_IACK_MDINT 0x00000020 // Clear MII Transaction Complete
+#define MAC_IACK_RXER 0x00000010 // Clear Receive Error
+#define MAC_IACK_FOV 0x00000008 // Clear FIFO Overrun
+#define MAC_IACK_TXEMP 0x00000004 // Clear Transmit FIFO Empty
+#define MAC_IACK_TXER 0x00000002 // Clear Transmit Error
+#define MAC_IACK_RXINT 0x00000001 // Clear Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IM register.
+//
+//*****************************************************************************
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt
+#define MAC_IM_MDINTM 0x00000020 // Mask MII Transaction Complete
+#define MAC_IM_RXERM 0x00000010 // Mask Receive Error
+#define MAC_IM_FOVM 0x00000008 // Mask FIFO Overrun
+#define MAC_IM_TXEMPM 0x00000004 // Mask Transmit FIFO Empty
+#define MAC_IM_TXERM 0x00000002 // Mask Transmit Error
+#define MAC_IM_RXINTM 0x00000001 // Mask Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RCTL register.
+//
+//*****************************************************************************
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear Receive FIFO
+#define MAC_RCTL_BADCRC 0x00000008 // Enable Reject Bad CRC
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Frames
+#define MAC_RCTL_RXEN 0x00000001 // Enable Receiver
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex Mode
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation
+#define MAC_TCTL_PADEN 0x00000002 // Enable Packet Padding
+#define MAC_TCTL_TXEN 0x00000001 // Enable Transmitter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data
+#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data
+#define MAC_DATA_RXDATA_S 0
+#define MAC_DATA_TXDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4
+#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3
+#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2
+#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1
+#define MAC_IA0_MACOCT4_S 24
+#define MAC_IA0_MACOCT3_S 16
+#define MAC_IA0_MACOCT2_S 8
+#define MAC_IA0_MACOCT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6
+#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5
+#define MAC_IA1_MACOCT6_S 8
+#define MAC_IA1_MACOCT5_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_THR register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M 0x0000003F // Threshold Value
+#define MAC_THR_THRESH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address
+#define MAC_MCTL_WRITE 0x00000002 // MII Register Transaction Type
+#define MAC_MCTL_START 0x00000001 // MII Register Transaction Enable
+#define MAC_MCTL_REGADR_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M 0x000000FF // Clock Divider
+#define MAC_MDV_DIV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data
+#define MAC_MTXD_MDTX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data
+#define MAC_MRXD_MDRX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive
+ // FIFO
+#define MAC_NP_NPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TR register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX 0x00000001 // New Transmission
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TS register.
+//
+//*****************************************************************************
+#define MAC_TS_TSEN 0x00000001 // Time Stamp Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_LED register.
+//
+//*****************************************************************************
+#define MAC_LED_LED1_M 0x00000F00 // LED1 Source
+#define MAC_LED_LED1_LINK 0x00000000 // Link OK
+#define MAC_LED_LED1_RXTX 0x00000100 // RX or TX Activity (Default LED1)
+#define MAC_LED_LED1_100 0x00000500 // 100BASE-TX mode
+#define MAC_LED_LED1_10 0x00000600 // 10BASE-T mode
+#define MAC_LED_LED1_DUPLEX 0x00000700 // Full-Duplex
+#define MAC_LED_LED1_LINKACT 0x00000800 // Link OK & Blink=RX or TX
+ // Activity
+#define MAC_LED_LED0_M 0x0000000F // LED0 Source
+#define MAC_LED_LED0_LINK 0x00000000 // Link OK (Default LED0)
+#define MAC_LED_LED0_RXTX 0x00000001 // RX or TX Activity
+#define MAC_LED_LED0_100 0x00000005 // 100BASE-TX mode
+#define MAC_LED_LED0_10 0x00000006 // 10BASE-T mode
+#define MAC_LED_LED0_DUPLEX 0x00000007 // Full-Duplex
+#define MAC_LED_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
+ // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDIX register.
+//
+//*****************************************************************************
+#define MAC_MDIX_EN 0x00000001 // MDI/MDI-X Enable
+
+//*****************************************************************************
+//
+// The following are defines for the Ethernet Controller PHY registers.
+//
+//*****************************************************************************
+#define PHY_MR0 0x00000000 // Ethernet PHY Management Register
+ // 0 - Control
+#define PHY_MR1 0x00000001 // Ethernet PHY Management Register
+ // 1 - Status
+#define PHY_MR2 0x00000002 // Ethernet PHY Management Register
+ // 2 - PHY Identifier 1
+#define PHY_MR3 0x00000003 // Ethernet PHY Management Register
+ // 3 - PHY Identifier 2
+#define PHY_MR4 0x00000004 // Ethernet PHY Management Register
+ // 4 - Auto-Negotiation
+ // Advertisement
+#define PHY_MR5 0x00000005 // Ethernet PHY Management Register
+ // 5 - Auto-Negotiation Link
+ // Partner Base Page Ability
+#define PHY_MR6 0x00000006 // Ethernet PHY Management Register
+ // 6 - Auto-Negotiation Expansion
+#define PHY_MR16 0x00000010 // Ethernet PHY Management Register
+ // 16 - Vendor-Specific
+#define PHY_MR17 0x00000011 // Ethernet PHY Management Register
+ // 17 - Mode Control/Status
+#define PHY_MR18 0x00000012 // Ethernet PHY Management Register
+ // 18 - Diagnostic
+#define PHY_MR19 0x00000013 // Ethernet PHY Management Register
+ // 19 - Transceiver Control
+#define PHY_MR23 0x00000017 // Ethernet PHY Management Register
+ // 23 - LED Configuration
+#define PHY_MR24 0x00000018 // Ethernet PHY Management Register
+ // 24 -MDI/MDIX Control
+#define PHY_MR27 0x0000001B // Ethernet PHY Management Register
+ // 27 - Special Control/Status
+#define PHY_MR29 0x0000001D // Ethernet PHY Management Register
+ // 29 - Interrupt Status
+#define PHY_MR30 0x0000001E // Ethernet PHY Management Register
+ // 30 - Interrupt Mask
+#define PHY_MR31 0x0000001F // Ethernet PHY Management Register
+ // 31 - PHY Special Control/Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET 0x00008000 // Reset Registers
+#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode
+#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select
+#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable
+#define PHY_MR0_PWRDN 0x00000800 // Power Down
+#define PHY_MR0_ISO 0x00000400 // Isolate
+#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation
+#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode
+#define PHY_MR0_COLT 0x00000080 // Collision Test
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode
+#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode
+#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode
+#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode
+#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble
+ // Suppressed
+#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete
+#define PHY_MR1_RFAULT 0x00000010 // Remote Fault
+#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation
+#define PHY_MR1_LINK 0x00000004 // Link Made
+#define PHY_MR1_JAB 0x00000002 // Jabber Condition
+#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
+ // Identifier[21:6]
+#define PHY_MR2_OUI_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
+ // Identifier[5:0]
+#define PHY_MR3_MN_M 0x000003F0 // Model Number
+#define PHY_MR3_RN_M 0x0000000F // Revision Number
+#define PHY_MR3_OUI_S 10
+#define PHY_MR3_MN_S 4
+#define PHY_MR3_RN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP 0x00008000 // Next Page
+#define PHY_MR4_RF 0x00002000 // Remote Fault
+#define PHY_MR4_A3 0x00000100 // Technology Ability Field [3]
+#define PHY_MR4_A2 0x00000080 // Technology Ability Field [2]
+#define PHY_MR4_A1 0x00000040 // Technology Ability Field [1]
+#define PHY_MR4_A0 0x00000020 // Technology Ability Field [0]
+#define PHY_MR4_S_M 0x0000001F // Selector Field
+#define PHY_MR4_S_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR5 register.
+//
+//*****************************************************************************
+#define PHY_MR5_NP 0x00008000 // Next Page
+#define PHY_MR5_ACK 0x00004000 // Acknowledge
+#define PHY_MR5_RF 0x00002000 // Remote Fault
+#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field
+#define PHY_MR5_S_M 0x0000001F // Selector Field
+#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
+#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
+#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
+#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
+#define PHY_MR5_A_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR6 register.
+//
+//*****************************************************************************
+#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault
+#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able
+#define PHY_MR6_PRX 0x00000002 // New Page Received
+#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
+ // Able
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR16 register.
+//
+//*****************************************************************************
+#define PHY_MR16_RPTR 0x00008000 // Repeater Mode
+#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity
+#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode
+#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing
+#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode
+#define PHY_MR16_SR_M 0x000003C0 // Silicon Revision Identifier
+#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable
+#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity
+#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass
+#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control
+#define PHY_MR16_SR_S 6
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR17 register.
+//
+//*****************************************************************************
+#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable
+#define PHY_MR17_FASTRIP 0x00004000 // 10-BASE-T Fast Mode Enable
+#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable
+#define PHY_MR17_EDPD 0x00002000 // Enable Energy Detect Power Down
+#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable
+#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
+ // Interrupt Enable
+#define PHY_MR17_LSQE 0x00000800 // Low Squelch Enable
+#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable
+#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
+ // Enable
+#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable
+#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
+ // Interrupt Enable
+#define PHY_MR17_FASTEST 0x00000100 // Auto-Negotiation Test Mode
+#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt
+#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt
+#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt
+#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
+ // Interrupt
+#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt
+#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt
+#define PHY_MR17_FGLS 0x00000004 // Force Good Link Status
+#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt
+#define PHY_MR17_ENON 0x00000002 // Energy On
+#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR18 register.
+//
+//*****************************************************************************
+#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure
+#define PHY_MR18_DPLX 0x00000800 // Duplex Mode
+#define PHY_MR18_RATE 0x00000400 // Rate
+#define PHY_MR18_RXSD 0x00000200 // Receive Detection
+#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR19 register.
+//
+//*****************************************************************************
+#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection
+#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
+ // loss
+#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
+ // loss
+#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
+ // loss
+#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion
+ // loss
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR23 register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source
+#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
+#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
+#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
+#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
+#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
+#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
+ // Activity
+#define PHY_MR23_LED0_M 0x0000000F // LED0 Source
+#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
+#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
+#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
+#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
+#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
+#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
+ // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR24 register.
+//
+//*****************************************************************************
+#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode
+#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable
+#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration
+#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete
+#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed
+#define PHY_MR24_MDIX_SD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR27 register.
+//
+//*****************************************************************************
+#define PHY_MR27_XPOL 0x00000010 // Polarity State of 10 BASE-T
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR29 register.
+//
+//*****************************************************************************
+#define PHY_MR29_EONIS 0x00000080 // ENERGYON Interrupt
+#define PHY_MR29_ANCOMPIS 0x00000040 // Auto-Negotiation Complete
+ // Interrupt
+#define PHY_MR29_RFLTIS 0x00000020 // Remote Fault Interrupt
+#define PHY_MR29_LDIS 0x00000010 // Link Down Interrupt
+#define PHY_MR29_LPACKIS 0x00000008 // Auto-Negotiation LP Acknowledge
+#define PHY_MR29_PDFIS 0x00000004 // Parallel Detection Fault
+#define PHY_MR29_PRXIS 0x00000002 // Auto Negotiation Page Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR30 register.
+//
+//*****************************************************************************
+#define PHY_MR30_EONIM 0x00000080 // ENERGYON Interrupt Enabled
+#define PHY_MR30_ANCOMPIM 0x00000040 // Auto-Negotiation Complete
+ // Interrupt Enabled
+#define PHY_MR30_RFLTIM 0x00000020 // Remote Fault Interrupt Enabled
+#define PHY_MR30_LDIM 0x00000010 // Link Down Interrupt Enabled
+#define PHY_MR30_LPACKIM 0x00000008 // Auto-Negotiation LP Acknowledge
+ // Enabled
+#define PHY_MR30_PDFIM 0x00000004 // Parallel Detection Fault Enabled
+#define PHY_MR30_PRXIM 0x00000002 // Auto Negotiation Page Received
+ // Enabled
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR31 register.
+//
+//*****************************************************************************
+#define PHY_MR31_AUTODONE 0x00001000 // Auto Negotiation Done
+#define PHY_MR31_SPEED_M 0x0000001C // HCD Speed Value
+#define PHY_MR31_SPEED_10HD 0x00000004 // 10BASE-T half duplex
+#define PHY_MR31_SPEED_100HD 0x00000008 // 100BASE-T half duplex
+#define PHY_MR31_SPEED_10FD 0x00000014 // 10BASE-T full duplex
+#define PHY_MR31_SPEED_100FD 0x00000018 // 100BASE-T full duplex
+#define PHY_MR31_SCRDIS 0x00000001 // Scramble Disable
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Ethernet MAC register offsets.
+//
+//*****************************************************************************
+#define MAC_O_IS 0x00000000 // Interrupt Status Register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_IS
+// register.
+//
+//*****************************************************************************
+#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt
+#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete
+#define MAC_IS_RXER 0x00000010 // RX Error
+#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun
+#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy
+#define MAC_IS_TXER 0x00000002 // TX Error
+#define MAC_IS_RXINT 0x00000001 // RX Packet Available
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_IA0
+// register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address
+#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address
+#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address
+#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_IA1
+// register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address
+#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_THR
+// register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_MCTL
+// register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_MDV
+// register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_MTXD
+// register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_MRXD
+// register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_NP
+// register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PHY_MR23
+// register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_TX 0x00000020 // TX Activity
+#define PHY_MR23_LED1_RX 0x00000030 // RX Activity
+#define PHY_MR23_LED1_COL 0x00000040 // Collision
+#define PHY_MR23_LED0_TX 0x00000002 // TX Activity
+#define PHY_MR23_LED0_RX 0x00000003 // RX Activity
+#define PHY_MR23_LED0_COL 0x00000004 // Collision
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the MAC
+// registers.
+//
+//*****************************************************************************
+#define MAC_RV_MDV 0x00000080
+#define MAC_RV_IM 0x0000007F
+#define MAC_RV_THR 0x0000003F
+#define MAC_RV_RCTL 0x00000008
+#define MAC_RV_IA0 0x00000000
+#define MAC_RV_TCTL 0x00000000
+#define MAC_RV_DATA 0x00000000
+#define MAC_RV_MRXD 0x00000000
+#define MAC_RV_TR 0x00000000
+#define MAC_RV_IS 0x00000000
+#define MAC_RV_NP 0x00000000
+#define MAC_RV_MCTL 0x00000000
+#define MAC_RV_MTXD 0x00000000
+#define MAC_RV_IA1 0x00000000
+#define MAC_RV_IACK 0x00000000
+#define MAC_RV_MADD 0x00000000
+
+#endif
+
+#endif // __HW_ETHERNET_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_flash.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_flash.h
new file mode 100644
index 00000000..13a013e5
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_flash.h
@@ -0,0 +1,381 @@
+//*****************************************************************************
+//
+// hw_flash.h - Macros used when accessing the flash controller.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FLASH_H__
+#define __HW_FLASH_H__
+
+//*****************************************************************************
+//
+// The following are defines for the FLASH register offsets.
+//
+//*****************************************************************************
+#define FLASH_FMA 0x400FD000 // Flash Memory Address
+#define FLASH_FMD 0x400FD004 // Flash Memory Data
+#define FLASH_FMC 0x400FD008 // Flash Memory Control
+#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt
+ // Status
+#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask
+#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked
+ // Interrupt Status and Clear
+#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2
+#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
+#define FLASH_FCTL 0x400FD0F8 // Flash Control
+#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n
+#define FLASH_RMCTL 0x400FE0F0 // ROM Control
+#define FLASH_FMPRE 0x400FE130 // Flash Memory Protection Read
+ // Enable
+#define FLASH_FMPPE 0x400FE134 // Flash Memory Protection Program
+ // Enable
+#define FLASH_USECRL 0x400FE140 // USec Reload
+#define FLASH_USERDBG 0x400FE1D0 // User Debug
+#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration
+#define FLASH_USERREG0 0x400FE1E0 // User Register 0
+#define FLASH_USERREG1 0x400FE1E4 // User Register 1
+#define FLASH_USERREG2 0x400FE1E8 // User Register 2
+#define FLASH_USERREG3 0x400FE1EC // User Register 3
+#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read
+ // Enable 0
+#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read
+ // Enable 1
+#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read
+ // Enable 2
+#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
+ // Enable 3
+#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
+ // Enable 0
+#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
+ // Enable 1
+#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program
+ // Enable 2
+#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
+ // Enable 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset
+#define FLASH_FMA_OFFSET_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
+#define FLASH_FMD_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
+#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCTL register.
+//
+//*****************************************************************************
+#define FLASH_FCTL_USDACK 0x00000002 // User Shut Down Acknowledge
+#define FLASH_FCTL_USDREQ 0x00000001 // User Shut Down Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USECRL register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value
+#define FLASH_USECRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERDBG register.
+//
+//*****************************************************************************
+#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written
+#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data
+#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1
+#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0
+#define FLASH_USERDBG_DATA_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
+#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
+#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
+#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
+#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
+#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
+#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
+#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
+#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
+#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
+#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1
+#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2
+#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
+#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4
+#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5
+#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6
+#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
+#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
+#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
+#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_NW 0x80000000 // Not Written
+#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data
+#define FLASH_USERREG0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_NW 0x80000000 // Not Written
+#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data
+#define FLASH_USERREG1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_NW 0x80000000 // Not Written
+#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data
+#define FLASH_USERREG2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_NW 0x80000000 // Not Written
+#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data
+#define FLASH_USERREG3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE and
+// FLASH_FMPPE registers.
+//
+//*****************************************************************************
+#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
+#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
+#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
+#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
+#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
+#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
+#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
+#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
+#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
+#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
+#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
+#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
+#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
+#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
+#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
+#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
+#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
+#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
+#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
+#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
+#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
+#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
+#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
+#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
+#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
+#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
+#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
+#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
+#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
+#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
+#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE 0x00000800
+#define FLASH_ERASE_SIZE 0x00000400
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the FLASH register offsets.
+//
+//*****************************************************************************
+#define FLASH_RMVER 0x400FE0F4 // ROM Version Register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FMC
+// register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
+#define FLASH_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key
+#define FLASH_FMC_WRKEY_S 16
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FCRIS
+// register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FCIM
+// register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FCMISC
+// register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_RMVER
+// register.
+//
+//*****************************************************************************
+#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents
+#define FLASH_RMVER_CONT_LM 0x00000000 // Stellaris Boot Loader &
+ // DriverLib
+#define FLASH_RMVER_CONT_LM_AES 0x02000000 // Stellaris Boot Loader &
+ // DriverLib with AES
+#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \
+ 0x03000000 // Stellaris Boot Loader &
+ // DriverLib with AES and SAFERTOS
+#define FLASH_RMVER_CONT_LM_AES2 \
+ 0x05000000 // Stellaris Boot Loader &
+ // DriverLib with AES
+#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version
+#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision
+#define FLASH_RMVER_VER_S 8
+#define FLASH_RMVER_REV_S 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_USECRL
+// register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
+#define FLASH_USECRL_SHIFT 0
+
+#endif
+
+#endif // __HW_FLASH_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_gpio.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_gpio.h
new file mode 100644
index 00000000..acdb2984
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_gpio.h
@@ -0,0 +1,592 @@
+//*****************************************************************************
+//
+// hw_gpio.h - Defines and Macros for GPIO hardware.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_GPIO_H__
+#define __HW_GPIO_H__
+
+//*****************************************************************************
+//
+// The following are defines for the GPIO register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_DATA 0x00000000 // GPIO Data
+#define GPIO_O_DIR 0x00000400 // GPIO Direction
+#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
+#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
+#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
+#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
+#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
+#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
+#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
+#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
+#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
+#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
+#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
+#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
+#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
+#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
+#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
+#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
+#define GPIO_O_LOCK 0x00000520 // GPIO Lock
+#define GPIO_O_CR 0x00000524 // GPIO Commit
+#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
+#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
+#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
+ // and may be modified
+#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
+ // and may not be modified
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
+#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on
+ // DustDevil-class devices and
+ // later
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port A.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask
+#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0
+#define GPIO_PCTL_PA0_I2C1SCL 0x00000008 // I2C1SCL on PA0
+#define GPIO_PCTL_PA0_U1RX 0x00000009 // U1RX on PA0
+#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 mask
+#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1
+#define GPIO_PCTL_PA1_I2C1SDA 0x00000080 // I2C1SDA on PA1
+#define GPIO_PCTL_PA1_U1TX 0x00000090 // U1TX on PA1
+#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 mask
+#define GPIO_PCTL_PA2_SSI0CLK 0x00000100 // SSI0CLK on PA2
+#define GPIO_PCTL_PA2_PWM4 0x00000400 // PWM4 on PA2
+#define GPIO_PCTL_PA2_I2S0RXSD 0x00000900 // I2S0RXSD on PA2
+#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 mask
+#define GPIO_PCTL_PA3_SSI0FSS 0x00001000 // SSI0FSS on PA3
+#define GPIO_PCTL_PA3_PWM5 0x00004000 // PWM5 on PA3
+#define GPIO_PCTL_PA3_I2S0RXMCLK \
+ 0x00009000 // I2S0RXMCLK on PA3
+#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 mask
+#define GPIO_PCTL_PA4_SSI0RX 0x00010000 // SSI0RX on PA4
+#define GPIO_PCTL_PA4_PWM6 0x00040000 // PWM6 on PA4
+#define GPIO_PCTL_PA4_CAN0RX 0x00050000 // CAN0RX on PA4
+#define GPIO_PCTL_PA4_I2S0TXSCK 0x00090000 // I2S0TXSCK on PA4
+#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 mask
+#define GPIO_PCTL_PA5_SSI0TX 0x00100000 // SSI0TX on PA5
+#define GPIO_PCTL_PA5_PWM7 0x00400000 // PWM7 on PA5
+#define GPIO_PCTL_PA5_CAN0TX 0x00500000 // CAN0TX on PA5
+#define GPIO_PCTL_PA5_I2S0TXWS 0x00900000 // I2S0TXWS on PA5
+#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask
+#define GPIO_PCTL_PA6_I2C1SCL 0x01000000 // I2C1SCL on PA6
+#define GPIO_PCTL_PA6_CCP1 0x02000000 // CCP1 on PA6
+#define GPIO_PCTL_PA6_PWM0 0x04000000 // PWM0 on PA6
+#define GPIO_PCTL_PA6_PWM4 0x05000000 // PWM4 on PA6
+#define GPIO_PCTL_PA6_CAN0RX 0x06000000 // CAN0RX on PA6
+#define GPIO_PCTL_PA6_USB0EPEN 0x08000000 // USB0EPEN on PA6
+#define GPIO_PCTL_PA6_U1CTS 0x09000000 // U1CTS on PA6
+#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask
+#define GPIO_PCTL_PA7_I2C1SDA 0x10000000 // I2C1SDA on PA7
+#define GPIO_PCTL_PA7_CCP4 0x20000000 // CCP4 on PA7
+#define GPIO_PCTL_PA7_PWM1 0x40000000 // PWM1 on PA7
+#define GPIO_PCTL_PA7_PWM5 0x50000000 // PWM5 on PA7
+#define GPIO_PCTL_PA7_CAN0TX 0x60000000 // CAN0TX on PA7
+#define GPIO_PCTL_PA7_CCP3 0x70000000 // CCP3 on PA7
+#define GPIO_PCTL_PA7_USB0PFLT 0x80000000 // USB0PFLT on PA7
+#define GPIO_PCTL_PA7_U1DCD 0x90000000 // U1DCD on PA7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port B.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask
+#define GPIO_PCTL_PB0_CCP0 0x00000001 // CCP0 on PB0
+#define GPIO_PCTL_PB0_PWM2 0x00000002 // PWM2 on PB0
+#define GPIO_PCTL_PB0_U1RX 0x00000005 // U1RX on PB0
+#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 mask
+#define GPIO_PCTL_PB1_CCP2 0x00000010 // CCP2 on PB1
+#define GPIO_PCTL_PB1_PWM3 0x00000020 // PWM3 on PB1
+#define GPIO_PCTL_PB1_CCP1 0x00000040 // CCP1 on PB1
+#define GPIO_PCTL_PB1_U1TX 0x00000050 // U1TX on PB1
+#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 mask
+#define GPIO_PCTL_PB2_I2C0SCL 0x00000100 // I2C0SCL on PB2
+#define GPIO_PCTL_PB2_IDX0 0x00000200 // IDX0 on PB2
+#define GPIO_PCTL_PB2_CCP3 0x00000400 // CCP3 on PB2
+#define GPIO_PCTL_PB2_CCP0 0x00000500 // CCP0 on PB2
+#define GPIO_PCTL_PB2_USB0EPEN 0x00000800 // USB0EPEN on PB2
+#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 mask
+#define GPIO_PCTL_PB3_I2C0SDA 0x00001000 // I2C0SDA on PB3
+#define GPIO_PCTL_PB3_FAULT0 0x00002000 // FAULT0 on PB3
+#define GPIO_PCTL_PB3_FAULT3 0x00004000 // FAULT3 on PB3
+#define GPIO_PCTL_PB3_USB0PFLT 0x00008000 // USB0PFLT on PB3
+#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 mask
+#define GPIO_PCTL_PB4_U2RX 0x00040000 // U2RX on PB4
+#define GPIO_PCTL_PB4_CAN0RX 0x00050000 // CAN0RX on PB4
+#define GPIO_PCTL_PB4_IDX0 0x00060000 // IDX0 on PB4
+#define GPIO_PCTL_PB4_U1RX 0x00070000 // U1RX on PB4
+#define GPIO_PCTL_PB4_EPI0S23 0x00080000 // EPI0S23 on PB4
+#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 mask
+#define GPIO_PCTL_PB5_C0O 0x00100000 // C0O on PB5
+#define GPIO_PCTL_PB5_CCP5 0x00200000 // CCP5 on PB5
+#define GPIO_PCTL_PB5_CCP6 0x00300000 // CCP6 on PB5
+#define GPIO_PCTL_PB5_CCP0 0x00400000 // CCP0 on PB5
+#define GPIO_PCTL_PB5_CAN0TX 0x00500000 // CAN0TX on PB5
+#define GPIO_PCTL_PB5_CCP2 0x00600000 // CCP2 on PB5
+#define GPIO_PCTL_PB5_U1TX 0x00700000 // U1TX on PB5
+#define GPIO_PCTL_PB5_EPI0S22 0x00800000 // EPI0S22 on PB5
+#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 mask
+#define GPIO_PCTL_PB6_CCP1 0x01000000 // CCP1 on PB6
+#define GPIO_PCTL_PB6_CCP7 0x02000000 // CCP7 on PB6
+#define GPIO_PCTL_PB6_C0O 0x03000000 // C0O on PB6
+#define GPIO_PCTL_PB6_FAULT1 0x04000000 // FAULT1 on PB6
+#define GPIO_PCTL_PB6_IDX0 0x05000000 // IDX0 on PB6
+#define GPIO_PCTL_PB6_CCP5 0x06000000 // CCP5 on PB6
+#define GPIO_PCTL_PB6_I2S0TXSCK 0x09000000 // I2S0TXSCK on PB6
+#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 mask
+#define GPIO_PCTL_PB7_NMI 0x40000000 // NMI on PB7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port C.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask
+#define GPIO_PCTL_PC0_TCK 0x00000003 // TCK on PC0
+#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 mask
+#define GPIO_PCTL_PC1_TMS 0x00000030 // TMS on PC1
+#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 mask
+#define GPIO_PCTL_PC2_TDI 0x00000300 // TDI on PC2
+#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 mask
+#define GPIO_PCTL_PC3_TDO 0x00003000 // TDO on PC3
+#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 mask
+#define GPIO_PCTL_PC4_CCP5 0x00010000 // CCP5 on PC4
+#define GPIO_PCTL_PC4_PHA0 0x00020000 // PHA0 on PC4
+#define GPIO_PCTL_PC4_PWM6 0x00040000 // PWM6 on PC4
+#define GPIO_PCTL_PC4_CCP2 0x00050000 // CCP2 on PC4
+#define GPIO_PCTL_PC4_CCP4 0x00060000 // CCP4 on PC4
+#define GPIO_PCTL_PC4_EPI0S2 0x00080000 // EPI0S2 on PC4
+#define GPIO_PCTL_PC4_CCP1 0x00090000 // CCP1 on PC4
+#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 mask
+#define GPIO_PCTL_PC5_CCP1 0x00100000 // CCP1 on PC5
+#define GPIO_PCTL_PC5_C1O 0x00200000 // C1O on PC5
+#define GPIO_PCTL_PC5_C0O 0x00300000 // C0O on PC5
+#define GPIO_PCTL_PC5_FAULT2 0x00400000 // FAULT2 on PC5
+#define GPIO_PCTL_PC5_CCP3 0x00500000 // CCP3 on PC5
+#define GPIO_PCTL_PC5_USB0EPEN 0x00600000 // USB0EPEN on PC5
+#define GPIO_PCTL_PC5_EPI0S3 0x00800000 // EPI0S3 on PC5
+#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask
+#define GPIO_PCTL_PC6_CCP3 0x01000000 // CCP3 on PC6
+#define GPIO_PCTL_PC6_PHB0 0x02000000 // PHB0 on PC6
+#define GPIO_PCTL_PC6_C2O 0x03000000 // C2O on PC6
+#define GPIO_PCTL_PC6_PWM7 0x04000000 // PWM7 on PC6
+#define GPIO_PCTL_PC6_U1RX 0x05000000 // U1RX on PC6
+#define GPIO_PCTL_PC6_CCP0 0x06000000 // CCP0 on PC6
+#define GPIO_PCTL_PC6_USB0PFLT 0x07000000 // USB0PFLT on PC6
+#define GPIO_PCTL_PC6_EPI0S4 0x08000000 // EPI0S4 on PC6
+#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask
+#define GPIO_PCTL_PC7_CCP4 0x10000000 // CCP4 on PC7
+#define GPIO_PCTL_PC7_PHB0 0x20000000 // PHB0 on PC7
+#define GPIO_PCTL_PC7_CCP0 0x40000000 // CCP0 on PC7
+#define GPIO_PCTL_PC7_U1TX 0x50000000 // U1TX on PC7
+#define GPIO_PCTL_PC7_USB0PFLT 0x60000000 // USB0PFLT on PC7
+#define GPIO_PCTL_PC7_C1O 0x70000000 // C1O on PC7
+#define GPIO_PCTL_PC7_EPI0S5 0x80000000 // EPI0S5 on PC7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port D.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask
+#define GPIO_PCTL_PD0_PWM0 0x00000001 // PWM0 on PD0
+#define GPIO_PCTL_PD0_CAN0RX 0x00000002 // CAN0RX on PD0
+#define GPIO_PCTL_PD0_IDX0 0x00000003 // IDX0 on PD0
+#define GPIO_PCTL_PD0_U2RX 0x00000004 // U2RX on PD0
+#define GPIO_PCTL_PD0_U1RX 0x00000005 // U1RX on PD0
+#define GPIO_PCTL_PD0_CCP6 0x00000006 // CCP6 on PD0
+#define GPIO_PCTL_PD0_I2S0RXSCK 0x00000008 // I2S0RXSCK on PD0
+#define GPIO_PCTL_PD0_U1CTS 0x00000009 // U1CTS on PD0
+#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 mask
+#define GPIO_PCTL_PD1_PWM1 0x00000010 // PWM1 on PD1
+#define GPIO_PCTL_PD1_CAN0TX 0x00000020 // CAN0TX on PD1
+#define GPIO_PCTL_PD1_PHA0 0x00000030 // PHA0 on PD1
+#define GPIO_PCTL_PD1_U2TX 0x00000040 // U2TX on PD1
+#define GPIO_PCTL_PD1_U1TX 0x00000050 // U1TX on PD1
+#define GPIO_PCTL_PD1_CCP7 0x00000060 // CCP7 on PD1
+#define GPIO_PCTL_PD1_I2S0RXWS 0x00000080 // I2S0RXWS on PD1
+#define GPIO_PCTL_PD1_U1DCD 0x00000090 // U1DCD on PD1
+#define GPIO_PCTL_PD1_CCP2 0x000000A0 // CCP2 on PD1
+#define GPIO_PCTL_PD1_PHB1 0x000000B0 // PHB1 on PD1
+#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 mask
+#define GPIO_PCTL_PD2_U1RX 0x00000100 // U1RX on PD2
+#define GPIO_PCTL_PD2_CCP6 0x00000200 // CCP6 on PD2
+#define GPIO_PCTL_PD2_PWM2 0x00000300 // PWM2 on PD2
+#define GPIO_PCTL_PD2_CCP5 0x00000400 // CCP5 on PD2
+#define GPIO_PCTL_PD2_EPI0S20 0x00000800 // EPI0S20 on PD2
+#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 mask
+#define GPIO_PCTL_PD3_U1TX 0x00001000 // U1TX on PD3
+#define GPIO_PCTL_PD3_CCP7 0x00002000 // CCP7 on PD3
+#define GPIO_PCTL_PD3_PWM3 0x00003000 // PWM3 on PD3
+#define GPIO_PCTL_PD3_CCP0 0x00004000 // CCP0 on PD3
+#define GPIO_PCTL_PD3_EPI0S21 0x00008000 // EPI0S21 on PD3
+#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 mask
+#define GPIO_PCTL_PD4_CCP0 0x00010000 // CCP0 on PD4
+#define GPIO_PCTL_PD4_CCP3 0x00020000 // CCP3 on PD4
+#define GPIO_PCTL_PD4_I2S0RXSD 0x00080000 // I2S0RXSD on PD4
+#define GPIO_PCTL_PD4_U1RI 0x00090000 // U1RI on PD4
+#define GPIO_PCTL_PD4_EPI0S19 0x000A0000 // EPI0S19 on PD4
+#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 mask
+#define GPIO_PCTL_PD5_CCP2 0x00100000 // CCP2 on PD5
+#define GPIO_PCTL_PD5_CCP4 0x00200000 // CCP4 on PD5
+#define GPIO_PCTL_PD5_I2S0RXMCLK \
+ 0x00800000 // I2S0RXMCLK on PD5
+#define GPIO_PCTL_PD5_U2RX 0x00900000 // U2RX on PD5
+#define GPIO_PCTL_PD5_EPI0S28 0x00A00000 // EPI0S28 on PD5
+#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask
+#define GPIO_PCTL_PD6_FAULT0 0x01000000 // FAULT0 on PD6
+#define GPIO_PCTL_PD6_I2S0TXSCK 0x08000000 // I2S0TXSCK on PD6
+#define GPIO_PCTL_PD6_U2TX 0x09000000 // U2TX on PD6
+#define GPIO_PCTL_PD6_EPI0S29 0x0A000000 // EPI0S29 on PD6
+#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask
+#define GPIO_PCTL_PD7_IDX0 0x10000000 // IDX0 on PD7
+#define GPIO_PCTL_PD7_C0O 0x20000000 // C0O on PD7
+#define GPIO_PCTL_PD7_CCP1 0x30000000 // CCP1 on PD7
+#define GPIO_PCTL_PD7_I2S0TXWS 0x80000000 // I2S0TXWS on PD7
+#define GPIO_PCTL_PD7_U1DTR 0x90000000 // U1DTR on PD7
+#define GPIO_PCTL_PD7_EPI0S30 0xA0000000 // EPI0S30 on PD7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port E.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask
+#define GPIO_PCTL_PE0_PWM4 0x00000001 // PWM4 on PE0
+#define GPIO_PCTL_PE0_SSI1CLK 0x00000002 // SSI1CLK on PE0
+#define GPIO_PCTL_PE0_CCP3 0x00000003 // CCP3 on PE0
+#define GPIO_PCTL_PE0_EPI0S8 0x00000008 // EPI0S8 on PE0
+#define GPIO_PCTL_PE0_USB0PFLT 0x00000009 // USB0PFLT on PE0
+#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 mask
+#define GPIO_PCTL_PE1_PWM5 0x00000010 // PWM5 on PE1
+#define GPIO_PCTL_PE1_SSI1FSS 0x00000020 // SSI1FSS on PE1
+#define GPIO_PCTL_PE1_FAULT0 0x00000030 // FAULT0 on PE1
+#define GPIO_PCTL_PE1_CCP2 0x00000040 // CCP2 on PE1
+#define GPIO_PCTL_PE1_CCP6 0x00000050 // CCP6 on PE1
+#define GPIO_PCTL_PE1_EPI0S9 0x00000080 // EPI0S9 on PE1
+#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 mask
+#define GPIO_PCTL_PE2_CCP4 0x00000100 // CCP4 on PE2
+#define GPIO_PCTL_PE2_SSI1RX 0x00000200 // SSI1RX on PE2
+#define GPIO_PCTL_PE2_PHB1 0x00000300 // PHB1 on PE2
+#define GPIO_PCTL_PE2_PHA0 0x00000400 // PHA0 on PE2
+#define GPIO_PCTL_PE2_CCP2 0x00000500 // CCP2 on PE2
+#define GPIO_PCTL_PE2_EPI0S24 0x00000800 // EPI0S24 on PE2
+#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 mask
+#define GPIO_PCTL_PE3_CCP1 0x00001000 // CCP1 on PE3
+#define GPIO_PCTL_PE3_SSI1TX 0x00002000 // SSI1TX on PE3
+#define GPIO_PCTL_PE3_PHA1 0x00003000 // PHA1 on PE3
+#define GPIO_PCTL_PE3_PHB0 0x00004000 // PHB0 on PE3
+#define GPIO_PCTL_PE3_CCP7 0x00005000 // CCP7 on PE3
+#define GPIO_PCTL_PE3_EPI0S25 0x00008000 // EPI0S25 on PE3
+#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 mask
+#define GPIO_PCTL_PE4_CCP3 0x00010000 // CCP3 on PE4
+#define GPIO_PCTL_PE4_FAULT0 0x00040000 // FAULT0 on PE4
+#define GPIO_PCTL_PE4_U2TX 0x00050000 // U2TX on PE4
+#define GPIO_PCTL_PE4_CCP2 0x00060000 // CCP2 on PE4
+#define GPIO_PCTL_PE4_I2S0TXWS 0x00090000 // I2S0TXWS on PE4
+#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 mask
+#define GPIO_PCTL_PE5_CCP5 0x00100000 // CCP5 on PE5
+#define GPIO_PCTL_PE5_I2S0TXSD 0x00900000 // I2S0TXSD on PE5
+#define GPIO_PCTL_PE6_M 0x0F000000 // PE6 mask
+#define GPIO_PCTL_PE6_PWM4 0x01000000 // PWM4 on PE6
+#define GPIO_PCTL_PE6_C1O 0x02000000 // C1O on PE6
+#define GPIO_PCTL_PE6_U1CTS 0x09000000 // U1CTS on PE6
+#define GPIO_PCTL_PE7_M 0xF0000000 // PE7 mask
+#define GPIO_PCTL_PE7_PWM5 0x10000000 // PWM5 on PE7
+#define GPIO_PCTL_PE7_C2O 0x20000000 // C2O on PE7
+#define GPIO_PCTL_PE7_U1DCD 0x90000000 // U1DCD on PE7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port F.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask
+#define GPIO_PCTL_PF0_CAN1RX 0x00000001 // CAN1RX on PF0
+#define GPIO_PCTL_PF0_PHB0 0x00000002 // PHB0 on PF0
+#define GPIO_PCTL_PF0_PWM0 0x00000003 // PWM0 on PF0
+#define GPIO_PCTL_PF0_I2S0TXSD 0x00000008 // I2S0TXSD on PF0
+#define GPIO_PCTL_PF0_U1DSR 0x00000009 // U1DSR on PF0
+#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 mask
+#define GPIO_PCTL_PF1_CAN1TX 0x00000010 // CAN1TX on PF1
+#define GPIO_PCTL_PF1_IDX1 0x00000020 // IDX1 on PF1
+#define GPIO_PCTL_PF1_PWM1 0x00000030 // PWM1 on PF1
+#define GPIO_PCTL_PF1_I2S0TXMCLK \
+ 0x00000080 // I2S0TXMCLK on PF1
+#define GPIO_PCTL_PF1_U1RTS 0x00000090 // U1RTS on PF1
+#define GPIO_PCTL_PF1_CCP3 0x000000A0 // CCP3 on PF1
+#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 mask
+#define GPIO_PCTL_PF2_LED1 0x00000100 // LED1 on PF2
+#define GPIO_PCTL_PF2_PWM4 0x00000200 // PWM4 on PF2
+#define GPIO_PCTL_PF2_PWM2 0x00000400 // PWM2 on PF2
+#define GPIO_PCTL_PF2_SSI1CLK 0x00000900 // SSI1CLK on PF2
+#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 mask
+#define GPIO_PCTL_PF3_LED0 0x00001000 // LED0 on PF3
+#define GPIO_PCTL_PF3_PWM5 0x00002000 // PWM5 on PF3
+#define GPIO_PCTL_PF3_PWM3 0x00004000 // PWM3 on PF3
+#define GPIO_PCTL_PF3_SSI1FSS 0x00009000 // SSI1FSS on PF3
+#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 mask
+#define GPIO_PCTL_PF4_CCP0 0x00010000 // CCP0 on PF4
+#define GPIO_PCTL_PF4_C0O 0x00020000 // C0O on PF4
+#define GPIO_PCTL_PF4_FAULT0 0x00040000 // FAULT0 on PF4
+#define GPIO_PCTL_PF4_EPI0S12 0x00080000 // EPI0S12 on PF4
+#define GPIO_PCTL_PF4_SSI1RX 0x00090000 // SSI1RX on PF4
+#define GPIO_PCTL_PF5_M 0x00F00000 // PF5 mask
+#define GPIO_PCTL_PF5_CCP2 0x00100000 // CCP2 on PF5
+#define GPIO_PCTL_PF5_C1O 0x00200000 // C1O on PF5
+#define GPIO_PCTL_PF5_EPI0S15 0x00800000 // EPI0S15 on PF5
+#define GPIO_PCTL_PF5_SSI1TX 0x00900000 // SSI1TX on PF5
+#define GPIO_PCTL_PF6_M 0x0F000000 // PF6 mask
+#define GPIO_PCTL_PF6_CCP1 0x01000000 // CCP1 on PF6
+#define GPIO_PCTL_PF6_C2O 0x02000000 // C2O on PF6
+#define GPIO_PCTL_PF6_PHA0 0x04000000 // PHA0 on PF6
+#define GPIO_PCTL_PF6_I2S0TXMCLK \
+ 0x09000000 // I2S0TXMCLK on PF6
+#define GPIO_PCTL_PF6_U1RTS 0x0A000000 // U1RTS on PF6
+#define GPIO_PCTL_PF7_M 0xF0000000 // PF7 mask
+#define GPIO_PCTL_PF7_CCP4 0x10000000 // CCP4 on PF7
+#define GPIO_PCTL_PF7_PHB0 0x40000000 // PHB0 on PF7
+#define GPIO_PCTL_PF7_EPI0S12 0x80000000 // EPI0S12 on PF7
+#define GPIO_PCTL_PF7_FAULT1 0x90000000 // FAULT1 on PF7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port G.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PG0_M 0x0000000F // PG0 mask
+#define GPIO_PCTL_PG0_U2RX 0x00000001 // U2RX on PG0
+#define GPIO_PCTL_PG0_PWM0 0x00000002 // PWM0 on PG0
+#define GPIO_PCTL_PG0_I2C1SCL 0x00000003 // I2C1SCL on PG0
+#define GPIO_PCTL_PG0_PWM4 0x00000004 // PWM4 on PG0
+#define GPIO_PCTL_PG0_USB0EPEN 0x00000007 // USB0EPEN on PG0
+#define GPIO_PCTL_PG0_EPI0S13 0x00000008 // EPI0S13 on PG0
+#define GPIO_PCTL_PG1_M 0x000000F0 // PG1 mask
+#define GPIO_PCTL_PG1_U2TX 0x00000010 // U2TX on PG1
+#define GPIO_PCTL_PG1_PWM1 0x00000020 // PWM1 on PG1
+#define GPIO_PCTL_PG1_I2C1SDA 0x00000030 // I2C1SDA on PG1
+#define GPIO_PCTL_PG1_PWM5 0x00000040 // PWM5 on PG1
+#define GPIO_PCTL_PG1_EPI0S14 0x00000080 // EPI0S14 on PG1
+#define GPIO_PCTL_PG2_M 0x00000F00 // PG2 mask
+#define GPIO_PCTL_PG2_PWM0 0x00000100 // PWM0 on PG2
+#define GPIO_PCTL_PG2_FAULT0 0x00000400 // FAULT0 on PG2
+#define GPIO_PCTL_PG2_IDX1 0x00000800 // IDX1 on PG2
+#define GPIO_PCTL_PG2_I2S0RXSD 0x00000900 // I2S0RXSD on PG2
+#define GPIO_PCTL_PG3_M 0x0000F000 // PG3 mask
+#define GPIO_PCTL_PG3_PWM1 0x00001000 // PWM1 on PG3
+#define GPIO_PCTL_PG3_FAULT2 0x00004000 // FAULT2 on PG3
+#define GPIO_PCTL_PG3_FAULT0 0x00008000 // FAULT0 on PG3
+#define GPIO_PCTL_PG3_I2S0RXMCLK \
+ 0x00009000 // I2S0RXMCLK on PG3
+#define GPIO_PCTL_PG4_M 0x000F0000 // PG4 mask
+#define GPIO_PCTL_PG4_CCP3 0x00010000 // CCP3 on PG4
+#define GPIO_PCTL_PG4_FAULT1 0x00040000 // FAULT1 on PG4
+#define GPIO_PCTL_PG4_EPI0S15 0x00080000 // EPI0S15 on PG4
+#define GPIO_PCTL_PG4_PWM6 0x00090000 // PWM6 on PG4
+#define GPIO_PCTL_PG4_U1RI 0x000A0000 // U1RI on PG4
+#define GPIO_PCTL_PG5_M 0x00F00000 // PG5 mask
+#define GPIO_PCTL_PG5_CCP5 0x00100000 // CCP5 on PG5
+#define GPIO_PCTL_PG5_IDX0 0x00400000 // IDX0 on PG5
+#define GPIO_PCTL_PG5_FAULT1 0x00500000 // FAULT1 on PG5
+#define GPIO_PCTL_PG5_PWM7 0x00800000 // PWM7 on PG5
+#define GPIO_PCTL_PG5_I2S0RXSCK 0x00900000 // I2S0RXSCK on PG5
+#define GPIO_PCTL_PG5_U1DTR 0x00A00000 // U1DTR on PG5
+#define GPIO_PCTL_PG6_M 0x0F000000 // PG6 mask
+#define GPIO_PCTL_PG6_PHA1 0x01000000 // PHA1 on PG6
+#define GPIO_PCTL_PG6_PWM6 0x04000000 // PWM6 on PG6
+#define GPIO_PCTL_PG6_FAULT1 0x08000000 // FAULT1 on PG6
+#define GPIO_PCTL_PG6_I2S0RXWS 0x09000000 // I2S0RXWS on PG6
+#define GPIO_PCTL_PG6_U1RI 0x0A000000 // U1RI on PG6
+#define GPIO_PCTL_PG7_M 0xF0000000 // PG7 mask
+#define GPIO_PCTL_PG7_PHB1 0x10000000 // PHB1 on PG7
+#define GPIO_PCTL_PG7_PWM7 0x40000000 // PWM7 on PG7
+#define GPIO_PCTL_PG7_CCP5 0x80000000 // CCP5 on PG7
+#define GPIO_PCTL_PG7_EPI0S31 0x90000000 // EPI0S31 on PG7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port H.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PH0_M 0x0000000F // PH0 mask
+#define GPIO_PCTL_PH0_CCP6 0x00000001 // CCP6 on PH0
+#define GPIO_PCTL_PH0_PWM2 0x00000002 // PWM2 on PH0
+#define GPIO_PCTL_PH0_EPI0S6 0x00000008 // EPI0S6 on PH0
+#define GPIO_PCTL_PH0_PWM4 0x00000009 // PWM4 on PH0
+#define GPIO_PCTL_PH1_M 0x000000F0 // PH1 mask
+#define GPIO_PCTL_PH1_CCP7 0x00000010 // CCP7 on PH1
+#define GPIO_PCTL_PH1_PWM3 0x00000020 // PWM3 on PH1
+#define GPIO_PCTL_PH1_EPI0S7 0x00000080 // EPI0S7 on PH1
+#define GPIO_PCTL_PH1_PWM5 0x00000090 // PWM5 on PH1
+#define GPIO_PCTL_PH2_M 0x00000F00 // PH2 mask
+#define GPIO_PCTL_PH2_IDX1 0x00000100 // IDX1 on PH2
+#define GPIO_PCTL_PH2_C1O 0x00000200 // C1O on PH2
+#define GPIO_PCTL_PH2_FAULT3 0x00000400 // FAULT3 on PH2
+#define GPIO_PCTL_PH2_EPI0S1 0x00000800 // EPI0S1 on PH2
+#define GPIO_PCTL_PH3_M 0x0000F000 // PH3 mask
+#define GPIO_PCTL_PH3_PHB0 0x00001000 // PHB0 on PH3
+#define GPIO_PCTL_PH3_FAULT0 0x00002000 // FAULT0 on PH3
+#define GPIO_PCTL_PH3_USB0EPEN 0x00004000 // USB0EPEN on PH3
+#define GPIO_PCTL_PH3_EPI0S0 0x00008000 // EPI0S0 on PH3
+#define GPIO_PCTL_PH4_M 0x000F0000 // PH4 mask
+#define GPIO_PCTL_PH4_USB0PFLT 0x00040000 // USB0PFLT on PH4
+#define GPIO_PCTL_PH4_EPI0S10 0x00080000 // EPI0S10 on PH4
+#define GPIO_PCTL_PH4_SSI1CLK 0x000B0000 // SSI1CLK on PH4
+#define GPIO_PCTL_PH5_M 0x00F00000 // PH5 mask
+#define GPIO_PCTL_PH5_EPI0S11 0x00800000 // EPI0S11 on PH5
+#define GPIO_PCTL_PH5_FAULT2 0x00A00000 // FAULT2 on PH5
+#define GPIO_PCTL_PH5_SSI1FSS 0x00B00000 // SSI1FSS on PH5
+#define GPIO_PCTL_PH6_M 0x0F000000 // PH6 mask
+#define GPIO_PCTL_PH6_EPI0S26 0x08000000 // EPI0S26 on PH6
+#define GPIO_PCTL_PH6_PWM4 0x0A000000 // PWM4 on PH6
+#define GPIO_PCTL_PH6_SSI1RX 0x0B000000 // SSI1RX on PH6
+#define GPIO_PCTL_PH7_M 0xF0000000 // PH7 mask
+#define GPIO_PCTL_PH7_EPI0S27 0x80000000 // EPI0S27 on PH7
+#define GPIO_PCTL_PH7_PWM5 0xA0000000 // PWM5 on PH7
+#define GPIO_PCTL_PH7_SSI1TX 0xB0000000 // SSI1TX on PH7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port J.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PJ0_M 0x0000000F // PJ0 mask
+#define GPIO_PCTL_PJ0_EPI0S16 0x00000008 // EPI0S16 on PJ0
+#define GPIO_PCTL_PJ0_PWM0 0x0000000A // PWM0 on PJ0
+#define GPIO_PCTL_PJ0_I2C1SCL 0x0000000B // I2C1SCL on PJ0
+#define GPIO_PCTL_PJ1_M 0x000000F0 // PJ1 mask
+#define GPIO_PCTL_PJ1_EPI0S17 0x00000080 // EPI0S17 on PJ1
+#define GPIO_PCTL_PJ1_USB0PFLT 0x00000090 // USB0PFLT on PJ1
+#define GPIO_PCTL_PJ1_PWM1 0x000000A0 // PWM1 on PJ1
+#define GPIO_PCTL_PJ1_I2C1SDA 0x000000B0 // I2C1SDA on PJ1
+#define GPIO_PCTL_PJ2_M 0x00000F00 // PJ2 mask
+#define GPIO_PCTL_PJ2_EPI0S18 0x00000800 // EPI0S18 on PJ2
+#define GPIO_PCTL_PJ2_CCP0 0x00000900 // CCP0 on PJ2
+#define GPIO_PCTL_PJ2_FAULT0 0x00000A00 // FAULT0 on PJ2
+#define GPIO_PCTL_PJ3_M 0x0000F000 // PJ3 mask
+#define GPIO_PCTL_PJ3_EPI0S19 0x00008000 // EPI0S19 on PJ3
+#define GPIO_PCTL_PJ3_U1CTS 0x00009000 // U1CTS on PJ3
+#define GPIO_PCTL_PJ3_CCP6 0x0000A000 // CCP6 on PJ3
+#define GPIO_PCTL_PJ4_M 0x000F0000 // PJ4 mask
+#define GPIO_PCTL_PJ4_EPI0S28 0x00080000 // EPI0S28 on PJ4
+#define GPIO_PCTL_PJ4_U1DCD 0x00090000 // U1DCD on PJ4
+#define GPIO_PCTL_PJ4_CCP4 0x000A0000 // CCP4 on PJ4
+#define GPIO_PCTL_PJ5_M 0x00F00000 // PJ5 mask
+#define GPIO_PCTL_PJ5_EPI0S29 0x00800000 // EPI0S29 on PJ5
+#define GPIO_PCTL_PJ5_U1DSR 0x00900000 // U1DSR on PJ5
+#define GPIO_PCTL_PJ5_CCP2 0x00A00000 // CCP2 on PJ5
+#define GPIO_PCTL_PJ6_M 0x0F000000 // PJ6 mask
+#define GPIO_PCTL_PJ6_EPI0S30 0x08000000 // EPI0S30 on PJ6
+#define GPIO_PCTL_PJ6_U1RTS 0x09000000 // U1RTS on PJ6
+#define GPIO_PCTL_PJ6_CCP1 0x0A000000 // CCP1 on PJ6
+#define GPIO_PCTL_PJ7_M 0xF0000000 // PJ7 mask
+#define GPIO_PCTL_PJ7_U1DTR 0x90000000 // U1DTR on PJ7
+#define GPIO_PCTL_PJ7_CCP0 0xA0000000 // CCP0 on PJ7
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the GPIO register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_PeriphID4 0x00000FD0
+#define GPIO_O_PeriphID5 0x00000FD4
+#define GPIO_O_PeriphID6 0x00000FD8
+#define GPIO_O_PeriphID7 0x00000FDC
+#define GPIO_O_PeriphID0 0x00000FE0
+#define GPIO_O_PeriphID1 0x00000FE4
+#define GPIO_O_PeriphID2 0x00000FE8
+#define GPIO_O_PeriphID3 0x00000FEC
+#define GPIO_O_PCellID0 0x00000FF0
+#define GPIO_O_PCellID1 0x00000FF4
+#define GPIO_O_PCellID2 0x00000FF8
+#define GPIO_O_PCellID3 0x00000FFC
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the GPIO Register reset values.
+//
+//*****************************************************************************
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV
+#define GPIO_RV_PCellID1 0x000000F0
+#define GPIO_RV_PCellID3 0x000000B1
+#define GPIO_RV_PeriphID0 0x00000061
+#define GPIO_RV_PeriphID1 0x00000010
+#define GPIO_RV_PCellID0 0x0000000D
+#define GPIO_RV_PCellID2 0x00000005
+#define GPIO_RV_PeriphID2 0x00000004
+#define GPIO_RV_LOCK 0x00000001 // Lock register RV
+#define GPIO_RV_PeriphID7 0x00000000
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV
+#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV
+#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV
+#define GPIO_RV_PeriphID4 0x00000000
+#define GPIO_RV_PeriphID5 0x00000000
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV
+#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV
+#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV
+#define GPIO_RV_PeriphID6 0x00000000
+#define GPIO_RV_PeriphID3 0x00000000
+#define GPIO_RV_DATA 0x00000000 // Data register reset value
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV
+
+#endif
+
+#endif // __HW_GPIO_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_hibernate.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_hibernate.h
new file mode 100644
index 00000000..5c286da2
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_hibernate.h
@@ -0,0 +1,242 @@
+//*****************************************************************************
+//
+// hw_hibernate.h - Defines and Macros for the Hibernation module.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_HIBERNATE_H__
+#define __HW_HIBERNATE_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Hibernation module register addresses.
+//
+//*****************************************************************************
+#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
+#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
+#define HIB_RTCM1 0x400FC008 // Hibernation RTC Match 1
+#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
+#define HIB_CTL 0x400FC010 // Hibernation Control
+#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
+#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
+#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
+ // Status
+#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
+#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
+#define HIB_DATA 0x400FC030 // Hibernation Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
+#define HIB_RTCC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
+#define HIB_RTCM0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM1 register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1
+#define HIB_RTCM1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
+#define HIB_RTCLD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
+#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
+#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
+#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable
+#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
+#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
+#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select
+#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
+#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
+ // Mask
+#define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask
+#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
+ // Status
+#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
+ // Interrupt Status
+#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status
+#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Status
+#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Status
+#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt
+ // Status
+#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Clear
+#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Clear
+#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
+ // Clear
+#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
+#define HIB_RTCT_TRIM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
+#define HIB_DATA_RTD_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Hibernation module register
+// addresses.
+//
+//*****************************************************************************
+#define HIB_DATA_END 0x400FC130 // end of data area, exclusive
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_RTCC
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_RTCM0
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_RTCM1
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_RTCLD
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_RIS
+// register.
+//
+//*****************************************************************************
+#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_MIS
+// register.
+//
+//*****************************************************************************
+#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_RTCT
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_DATA
+// register.
+//
+//*****************************************************************************
+#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask
+
+#endif
+
+#endif // __HW_HIBERNATE_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_i2c.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_i2c.h
new file mode 100644
index 00000000..e956d376
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_i2c.h
@@ -0,0 +1,407 @@
+//*****************************************************************************
+//
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_I2C_H__
+#define __HW_I2C_H__
+
+//*****************************************************************************
+//
+// The following are defines for the I2C register offsets.
+//
+//*****************************************************************************
+#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
+#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address
+#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status
+#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
+#define I2C_O_SDR 0x00000008 // I2C Slave Data
+#define I2C_O_MDR 0x00000008 // I2C Master Data
+#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
+#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask
+#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status
+#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
+#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
+#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt
+ // Status
+#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear
+#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
+ // Status
+#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
+#define I2C_O_MCR 0x00000020 // I2C Master Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
+#define I2C_MSA_RS 0x00000001 // Receive not send
+#define I2C_MSA_SA_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
+#define I2C_SCSR_DA 0x00000001 // Device Active
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
+#define I2C_MCS_STOP 0x00000004 // Generate STOP
+#define I2C_MCS_START 0x00000002 // Generate START
+#define I2C_MCS_ERROR 0x00000002 // Error
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_IM 0x00000001 // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_IC 0x00000001 // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the I2C register offsets.
+//
+//*****************************************************************************
+#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SIMR
+// register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM 0x00000001 // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SRIS
+// register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SMIS
+// register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SICR
+// register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC 0x00000001 // Clear Interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the I2C master register offsets.
+//
+//*****************************************************************************
+#define I2C_MASTER_O_SA 0x00000000 // Slave address register
+#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
+#define I2C_MASTER_O_DR 0x00000008 // Data register
+#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
+#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
+#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
+#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
+#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register
+#define I2C_MASTER_O_CR 0x00000020 // Configuration register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the I2C slave register offsets.
+//
+//*****************************************************************************
+#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
+#define I2C_SLAVE_O_DR 0x00000008 // Data register
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C master
+// slave address register.
+//
+//*****************************************************************************
+#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
+#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
+#define I2C_MASTER_SA_SA_SHIFT 1
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Control and Status register.
+//
+//*****************************************************************************
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
+#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
+#define I2C_MASTER_CS_STOP 0x00000004 // Stop
+#define I2C_MASTER_CS_START 0x00000002 // Start
+#define I2C_MASTER_CS_RUN 0x00000001 // Run
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the values used in determining the
+// contents of the I2C Master Timer Period register.
+//
+//*****************************************************************************
+#define I2C_SCL_FAST 400000 // SCL fast frequency
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency
+#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
+#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Interrupt Mask register.
+//
+//*****************************************************************************
+#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Raw Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Masked Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Interrupt Clear register.
+//
+//*****************************************************************************
+#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Configuration register.
+//
+//*****************************************************************************
+#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
+#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
+#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave Own
+// Address register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Control/Status register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master
+#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
+#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Interrupt Mask register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave Raw
+// Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Masked Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Interrupt Clear register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
+
+#endif
+
+#endif // __HW_I2C_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_i2s.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_i2s.h
new file mode 100644
index 00000000..f02ce94c
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_i2s.h
@@ -0,0 +1,224 @@
+//*****************************************************************************
+//
+// hw_i2s.h - Macros for use in accessing the I2S registers.
+//
+// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_I2S_H__
+#define __HW_I2S_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Inter-Integrated Circuit Sound register
+// offsets.
+//
+//*****************************************************************************
+#define I2S_O_TXFIFO 0x00000000 // I2S Transmit FIFO Data
+#define I2S_O_TXFIFOCFG 0x00000004 // I2S Transmit FIFO Configuration
+#define I2S_O_TXCFG 0x00000008 // I2S Transmit Module
+ // Configuration
+#define I2S_O_TXLIMIT 0x0000000C // I2S Transmit FIFO Limit
+#define I2S_O_TXISM 0x00000010 // I2S Transmit Interrupt Status
+ // and Mask
+#define I2S_O_TXLEV 0x00000018 // I2S Transmit FIFO Level
+#define I2S_O_RXFIFO 0x00000800 // I2S Receive FIFO Data
+#define I2S_O_RXFIFOCFG 0x00000804 // I2S Receive FIFO Configuration
+#define I2S_O_RXCFG 0x00000808 // I2S Receive Module Configuration
+#define I2S_O_RXLIMIT 0x0000080C // I2S Receive FIFO Limit
+#define I2S_O_RXISM 0x00000810 // I2S Receive Interrupt Status and
+ // Mask
+#define I2S_O_RXLEV 0x00000818 // I2S Receive FIFO Level
+#define I2S_O_CFG 0x00000C00 // I2S Module Configuration
+#define I2S_O_IM 0x00000C10 // I2S Interrupt Mask
+#define I2S_O_RIS 0x00000C14 // I2S Raw Interrupt Status
+#define I2S_O_MIS 0x00000C18 // I2S Masked Interrupt Status
+#define I2S_O_IC 0x00000C1C // I2S Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXFIFO register.
+//
+//*****************************************************************************
+#define I2S_TXFIFO_M 0xFFFFFFFF // TX Data
+#define I2S_TXFIFO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXFIFOCFG
+// register.
+//
+//*****************************************************************************
+#define I2S_TXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size
+#define I2S_TXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXCFG register.
+//
+//*****************************************************************************
+#define I2S_TXCFG_JST 0x20000000 // Justification of Output Data
+#define I2S_TXCFG_DLY 0x10000000 // Data Delay
+#define I2S_TXCFG_SCP 0x08000000 // SCLK Polarity
+#define I2S_TXCFG_LRP 0x04000000 // Left/Right Clock Polarity
+#define I2S_TXCFG_WM_M 0x03000000 // Write Mode
+#define I2S_TXCFG_WM_DUAL 0x00000000 // Stereo mode
+#define I2S_TXCFG_WM_COMPACT 0x01000000 // Compact Stereo mode
+#define I2S_TXCFG_WM_MONO 0x02000000 // Mono mode
+#define I2S_TXCFG_FMT 0x00800000 // FIFO Empty
+#define I2S_TXCFG_MSL 0x00400000 // SCLK Master/Slave
+#define I2S_TXCFG_SSZ_M 0x0000FC00 // Sample Size
+#define I2S_TXCFG_SDSZ_M 0x000003F0 // System Data Size
+#define I2S_TXCFG_SSZ_S 10
+#define I2S_TXCFG_SDSZ_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXLIMIT register.
+//
+//*****************************************************************************
+#define I2S_TXLIMIT_LIMIT_M 0x0000001F // FIFO Limit
+#define I2S_TXLIMIT_LIMIT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXISM register.
+//
+//*****************************************************************************
+#define I2S_TXISM_FFI 0x00010000 // Transmit FIFO Service Request
+ // Interrupt
+#define I2S_TXISM_FFM 0x00000001 // FIFO Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXLEV register.
+//
+//*****************************************************************************
+#define I2S_TXLEV_LEVEL_M 0x0000001F // Number of Audio Samples
+#define I2S_TXLEV_LEVEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXFIFO register.
+//
+//*****************************************************************************
+#define I2S_RXFIFO_M 0xFFFFFFFF // RX Data
+#define I2S_RXFIFO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXFIFOCFG
+// register.
+//
+//*****************************************************************************
+#define I2S_RXFIFOCFG_FMM 0x00000004 // FIFO Mono Mode
+#define I2S_RXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size
+#define I2S_RXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXCFG register.
+//
+//*****************************************************************************
+#define I2S_RXCFG_JST 0x20000000 // Justification of Input Data
+#define I2S_RXCFG_DLY 0x10000000 // Data Delay
+#define I2S_RXCFG_SCP 0x08000000 // SCLK Polarity
+#define I2S_RXCFG_LRP 0x04000000 // Left/Right Clock Polarity
+#define I2S_RXCFG_RM 0x01000000 // Read Mode
+#define I2S_RXCFG_MSL 0x00400000 // SCLK Master/Slave
+#define I2S_RXCFG_SSZ_M 0x0000FC00 // Sample Size
+#define I2S_RXCFG_SDSZ_M 0x000003F0 // System Data Size
+#define I2S_RXCFG_SSZ_S 10
+#define I2S_RXCFG_SDSZ_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXLIMIT register.
+//
+//*****************************************************************************
+#define I2S_RXLIMIT_LIMIT_M 0x0000001F // FIFO Limit
+#define I2S_RXLIMIT_LIMIT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXISM register.
+//
+//*****************************************************************************
+#define I2S_RXISM_FFI 0x00010000 // Receive FIFO Service Request
+ // Interrupt
+#define I2S_RXISM_FFM 0x00000001 // FIFO Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXLEV register.
+//
+//*****************************************************************************
+#define I2S_RXLEV_LEVEL_M 0x0000001F // Number of Audio Samples
+#define I2S_RXLEV_LEVEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_CFG register.
+//
+//*****************************************************************************
+#define I2S_CFG_RXSLV 0x00000020 // Use External I2S0RXMCLK
+#define I2S_CFG_TXSLV 0x00000010 // Use External I2S0TXMCLK
+#define I2S_CFG_RXEN 0x00000002 // Serial Receive Engine Enable
+#define I2S_CFG_TXEN 0x00000001 // Serial Transmit Engine Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_IM register.
+//
+//*****************************************************************************
+#define I2S_IM_RXRE 0x00000020 // Receive FIFO Read Error
+#define I2S_IM_RXFSR 0x00000010 // Receive FIFO Service Request
+#define I2S_IM_TXWE 0x00000002 // Transmit FIFO Write Error
+#define I2S_IM_TXFSR 0x00000001 // Transmit FIFO Service Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RIS register.
+//
+//*****************************************************************************
+#define I2S_RIS_RXRE 0x00000020 // Receive FIFO Read Error
+#define I2S_RIS_RXFSR 0x00000010 // Receive FIFO Service Request
+#define I2S_RIS_TXWE 0x00000002 // Transmit FIFO Write Error
+#define I2S_RIS_TXFSR 0x00000001 // Transmit FIFO Service Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_MIS register.
+//
+//*****************************************************************************
+#define I2S_MIS_RXRE 0x00000020 // Receive FIFO Read Error
+#define I2S_MIS_RXFSR 0x00000010 // Receive FIFO Service Request
+#define I2S_MIS_TXWE 0x00000002 // Transmit FIFO Write Error
+#define I2S_MIS_TXFSR 0x00000001 // Transmit FIFO Service Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_IC register.
+//
+//*****************************************************************************
+#define I2S_IC_RXRE 0x00000020 // Receive FIFO Read Error
+#define I2S_IC_TXWE 0x00000002 // Transmit FIFO Write Error
+
+#endif // __HW_I2S_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_ints.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_ints.h
new file mode 100644
index 00000000..1eb1e34e
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_ints.h
@@ -0,0 +1,141 @@
+//*****************************************************************************
+//
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_INTS_H__
+#define __HW_INTS_H__
+
+//*****************************************************************************
+//
+// The following are defines for the fault assignments.
+//
+//*****************************************************************************
+#define FAULT_NMI 2 // NMI fault
+#define FAULT_HARD 3 // Hard fault
+#define FAULT_MPU 4 // MPU fault
+#define FAULT_BUS 5 // Bus fault
+#define FAULT_USAGE 6 // Usage fault
+#define FAULT_SVCALL 11 // SVCall
+#define FAULT_DEBUG 12 // Debug monitor
+#define FAULT_PENDSV 14 // PendSV
+#define FAULT_SYSTICK 15 // System Tick
+
+//*****************************************************************************
+//
+// The following are defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_GPIOA 16 // GPIO Port A
+#define INT_GPIOB 17 // GPIO Port B
+#define INT_GPIOC 18 // GPIO Port C
+#define INT_GPIOD 19 // GPIO Port D
+#define INT_GPIOE 20 // GPIO Port E
+#define INT_UART0 21 // UART0 Rx and Tx
+#define INT_UART1 22 // UART1 Rx and Tx
+#define INT_SSI0 23 // SSI0 Rx and Tx
+#define INT_I2C0 24 // I2C0 Master and Slave
+#define INT_PWM_FAULT 25 // PWM Fault
+#define INT_PWM0 26 // PWM Generator 0
+#define INT_PWM1 27 // PWM Generator 1
+#define INT_PWM2 28 // PWM Generator 2
+#define INT_QEI0 29 // Quadrature Encoder 0
+#define INT_ADC0SS0 30 // ADC0 Sequence 0
+#define INT_ADC0SS1 31 // ADC0 Sequence 1
+#define INT_ADC0SS2 32 // ADC0 Sequence 2
+#define INT_ADC0SS3 33 // ADC0 Sequence 3
+#define INT_WATCHDOG 34 // Watchdog timer
+#define INT_TIMER0A 35 // Timer 0 subtimer A
+#define INT_TIMER0B 36 // Timer 0 subtimer B
+#define INT_TIMER1A 37 // Timer 1 subtimer A
+#define INT_TIMER1B 38 // Timer 1 subtimer B
+#define INT_TIMER2A 39 // Timer 2 subtimer A
+#define INT_TIMER2B 40 // Timer 2 subtimer B
+#define INT_COMP0 41 // Analog Comparator 0
+#define INT_COMP1 42 // Analog Comparator 1
+#define INT_COMP2 43 // Analog Comparator 2
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
+#define INT_FLASH 45 // FLASH Control
+#define INT_GPIOF 46 // GPIO Port F
+#define INT_GPIOG 47 // GPIO Port G
+#define INT_GPIOH 48 // GPIO Port H
+#define INT_UART2 49 // UART2 Rx and Tx
+#define INT_SSI1 50 // SSI1 Rx and Tx
+#define INT_TIMER3A 51 // Timer 3 subtimer A
+#define INT_TIMER3B 52 // Timer 3 subtimer B
+#define INT_I2C1 53 // I2C1 Master and Slave
+#define INT_QEI1 54 // Quadrature Encoder 1
+#define INT_CAN0 55 // CAN0
+#define INT_CAN1 56 // CAN1
+#define INT_CAN2 57 // CAN2
+#define INT_ETH 58 // Ethernet
+#define INT_HIBERNATE 59 // Hibernation module
+#define INT_USB0 60 // USB 0 Controller
+#define INT_PWM3 61 // PWM Generator 3
+#define INT_UDMA 62 // uDMA controller
+#define INT_UDMAERR 63 // uDMA Error
+#define INT_ADC1SS0 64 // ADC1 Sequence 0
+#define INT_ADC1SS1 65 // ADC1 Sequence 1
+#define INT_ADC1SS2 66 // ADC1 Sequence 2
+#define INT_ADC1SS3 67 // ADC1 Sequence 3
+#define INT_I2S0 68 // I2S0
+#define INT_EPI0 69 // EPI0
+#define INT_GPIOJ 70 // GPIO Port J
+
+//*****************************************************************************
+//
+// The following are defines for the total number of interrupts.
+//
+//*****************************************************************************
+#define NUM_INTERRUPTS 71
+
+//*****************************************************************************
+//
+// The following are defines for the total number of priority levels.
+//
+//*****************************************************************************
+#define NUM_PRIORITY 8
+#define NUM_PRIORITY_BITS 3
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_SSI 23 // SSI Rx and Tx
+#define INT_I2C 24 // I2C Master and Slave
+#define INT_QEI 29 // Quadrature Encoder
+#define INT_ADC0 30 // ADC Sequence 0
+#define INT_ADC1 31 // ADC Sequence 1
+#define INT_ADC2 32 // ADC Sequence 2
+#define INT_ADC3 33 // ADC Sequence 3
+
+#endif
+
+#endif // __HW_INTS_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_memmap.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_memmap.h
new file mode 100644
index 00000000..144f9d25
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_memmap.h
@@ -0,0 +1,115 @@
+//*****************************************************************************
+//
+// hw_memmap.h - Macros defining the memory map of Stellaris.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_MEMMAP_H__
+#define __HW_MEMMAP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the base address of the memories and
+// peripherals.
+//
+//*****************************************************************************
+#define FLASH_BASE 0x00000000 // FLASH memory
+#define SRAM_BASE 0x20000000 // SRAM memory
+#define WATCHDOG0_BASE 0x40000000 // Watchdog0
+#define WATCHDOG1_BASE 0x40001000 // Watchdog1
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
+#define SSI0_BASE 0x40008000 // SSI0
+#define SSI1_BASE 0x40009000 // SSI1
+#define UART0_BASE 0x4000C000 // UART0
+#define UART1_BASE 0x4000D000 // UART1
+#define UART2_BASE 0x4000E000 // UART2
+#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
+#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
+#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
+#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
+#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
+#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
+#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
+#define PWM_BASE 0x40028000 // PWM
+#define QEI0_BASE 0x4002C000 // QEI0
+#define QEI1_BASE 0x4002D000 // QEI1
+#define TIMER0_BASE 0x40030000 // Timer0
+#define TIMER1_BASE 0x40031000 // Timer1
+#define TIMER2_BASE 0x40032000 // Timer2
+#define TIMER3_BASE 0x40033000 // Timer3
+#define ADC0_BASE 0x40038000 // ADC0
+#define ADC1_BASE 0x40039000 // ADC1
+#define COMP_BASE 0x4003C000 // Analog comparators
+#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
+#define CAN0_BASE 0x40040000 // CAN0
+#define CAN1_BASE 0x40041000 // CAN1
+#define CAN2_BASE 0x40042000 // CAN2
+#define ETH_BASE 0x40048000 // Ethernet
+#define MAC_BASE 0x40048000 // Ethernet
+#define USB0_BASE 0x40050000 // USB 0 Controller
+#define I2S0_BASE 0x40054000 // I2S0
+#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
+#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
+#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
+#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
+#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
+#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
+#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
+#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
+#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
+#define EPI0_BASE 0x400D0000 // EPI0
+#define HIB_BASE 0x400FC000 // Hibernation Module
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
+#define SYSCTL_BASE 0x400FE000 // System Control
+#define UDMA_BASE 0x400FF000 // uDMA Controller
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the base address of the memories
+// and peripherals.
+//
+//*****************************************************************************
+#define WATCHDOG_BASE 0x40000000 // Watchdog
+#define SSI_BASE 0x40008000 // SSI
+#define I2C_MASTER_BASE 0x40020000 // I2C Master
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
+#define QEI_BASE 0x4002C000 // QEI
+#define ADC_BASE 0x40038000 // ADC
+
+#endif
+
+#endif // __HW_MEMMAP_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_nvic.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_nvic.h
new file mode 100644
index 00000000..5ac7bafb
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_nvic.h
@@ -0,0 +1,1189 @@
+//*****************************************************************************
+//
+// hw_nvic.h - Macros used when accessing the NVIC hardware.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_NVIC_H__
+#define __HW_NVIC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg
+#define NVIC_ACTLR 0xE000E008 // Auxiliary Control
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status
+ // Register
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg
+#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable
+#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable
+#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable
+#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable
+#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending
+#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending
+#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending
+#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending
+#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit
+#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit
+#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority
+#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority
+#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority
+#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority
+#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority
+#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority
+#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority
+#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority
+#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority
+#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority
+#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority
+#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority
+#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority
+#define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority
+#define NVIC_CPUID 0xE000ED00 // CPU ID Base
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset
+#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset
+ // Control
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control
+#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1
+#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2
+#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
+#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size
+#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1
+#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size
+ // Alias 1
+#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2
+#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size
+ // Alias 2
+#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3
+#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size
+ // Alias 3
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple
+ // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M 0x00FFFFFF // Interrupt Disable
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M 0x00FFFFFF // Interrupt Set Pending
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M 0x00FFFFFF // Interrupt Clear Pending
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M 0x00FFFFFF // Interrupt Active
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S 29
+#define NVIC_PRI0_INT2_S 21
+#define NVIC_PRI0_INT1_S 13
+#define NVIC_PRI0_INT0_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S 29
+#define NVIC_PRI1_INT6_S 21
+#define NVIC_PRI1_INT5_S 13
+#define NVIC_PRI1_INT4_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S 29
+#define NVIC_PRI2_INT10_S 21
+#define NVIC_PRI2_INT9_S 13
+#define NVIC_PRI2_INT8_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S 29
+#define NVIC_PRI3_INT14_S 21
+#define NVIC_PRI3_INT13_S 13
+#define NVIC_PRI3_INT12_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S 29
+#define NVIC_PRI4_INT18_S 21
+#define NVIC_PRI4_INT17_S 13
+#define NVIC_PRI4_INT16_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S 29
+#define NVIC_PRI5_INT22_S 21
+#define NVIC_PRI5_INT21_S 13
+#define NVIC_PRI5_INT20_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S 29
+#define NVIC_PRI6_INT26_S 21
+#define NVIC_PRI6_INT25_S 13
+#define NVIC_PRI6_INT24_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S 29
+#define NVIC_PRI7_INT30_S 21
+#define NVIC_PRI7_INT29_S 13
+#define NVIC_PRI7_INT28_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S 29
+#define NVIC_PRI8_INT34_S 21
+#define NVIC_PRI8_INT33_S 13
+#define NVIC_PRI8_INT32_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S 29
+#define NVIC_PRI9_INT38_S 21
+#define NVIC_PRI9_INT37_S 13
+#define NVIC_PRI9_INT36_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S 29
+#define NVIC_PRI10_INT42_S 21
+#define NVIC_PRI10_INT41_S 13
+#define NVIC_PRI10_INT40_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S 29
+#define NVIC_PRI11_INT46_S 21
+#define NVIC_PRI11_INT45_S 13
+#define NVIC_PRI11_INT44_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S 29
+#define NVIC_PRI12_INT50_S 21
+#define NVIC_PRI12_INT49_S 13
+#define NVIC_PRI12_INT48_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S 29
+#define NVIC_PRI13_INT54_S 21
+#define NVIC_PRI13_INT53_S 13
+#define NVIC_PRI13_INT52_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code
+#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number
+#define NVIC_CPUID_CON_M 0x000F0000 // Constant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number
+#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor
+#define NVIC_CPUID_REV_M 0x0000000F // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+ 0x00002000 // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+ 0x00003000 // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+ 0x00004000 // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+ 0x00005000 // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+ 0x00006000 // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+ 0x0000B000 // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+ 0x0000E000 // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+ 0x0000F000 // SysTick
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S 9
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception
+ // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and
+ // Fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S 21
+#define NVIC_SYS_PRI1_BUS_S 13
+#define NVIC_SYS_PRI1_MEM_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S 29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S 29
+#define NVIC_SYS_PRI3_PENDSV_S 21
+#define NVIC_SYS_PRI3_DEBUG_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+ 0x00001000 // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage
+ // Fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address
+ // Register Valid
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE_ADDR_S 5
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes
+#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE1_ADDR_S 5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE2_ADDR_S 5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE3_ADDR_S 5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S 0
+
+#endif // __HW_NVIC_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_pwm.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_pwm.h
new file mode 100644
index 00000000..a59f3edb
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_pwm.h
@@ -0,0 +1,756 @@
+//*****************************************************************************
+//
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_PWM_H__
+#define __HW_PWM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the PWM register offsets.
+//
+//*****************************************************************************
+#define PWM_O_CTL 0x00000000 // PWM Master Control
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable
+#define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear
+#define PWM_O_STATUS 0x00000020 // PWM Status
+#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value
+#define PWM_O_ENUPD 0x00000028 // PWM Enable Update
+#define PWM_O_0_CTL 0x00000040 // PWM0 Control
+#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger
+ // Enable
+#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status
+#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear
+#define PWM_O_0_LOAD 0x00000050 // PWM0 Load
+#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter
+#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A
+#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B
+#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control
+#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control
+#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control
+#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay
+#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0
+#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1
+#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period
+#define PWM_O_1_CTL 0x00000080 // PWM1 Control
+#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger
+ // Enable
+#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status
+#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear
+#define PWM_O_1_LOAD 0x00000090 // PWM1 Load
+#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter
+#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A
+#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B
+#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control
+#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control
+#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control
+#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay
+#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0
+#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1
+#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period
+#define PWM_O_2_CTL 0x000000C0 // PWM2 Control
+#define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger
+ // Enable
+#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status
+#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear
+#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load
+#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter
+#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A
+#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B
+#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control
+#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control
+#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control
+#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay
+#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0
+#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1
+#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period
+#define PWM_O_3_CTL 0x00000100 // PWM3 Control
+#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger
+ // Enable
+#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status
+#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear
+#define PWM_O_3_LOAD 0x00000110 // PWM3 Load
+#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter
+#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A
+#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B
+#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control
+#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control
+#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control
+#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay
+#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0
+#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1
+#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period
+#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense
+#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0
+#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1
+#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense
+#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0
+#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1
+#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense
+#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0
+#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1
+#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense
+#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0
+#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 Output Enable
+#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 Output Enable
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV 0x00000080 // Invert PWM7 Signal
+#define PWM_INVERT_PWM6INV 0x00000040 // Invert PWM6 Signal
+#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal
+#define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal
+#define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal
+#define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal
+#define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal
+#define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7 0x00000080 // PWM7 Fault
+#define PWM_FAULT_FAULT6 0x00000040 // PWM6 Fault
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault
+#define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault
+#define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault
+#define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault
+#define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault
+#define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3
+#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2
+#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable
+#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3
+#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2
+#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0
+#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted
+#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted
+#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted
+#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted
+#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status
+#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status
+#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value
+#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value
+#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value
+#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value
+#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value
+#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value
+#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value
+#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
+//
+//*****************************************************************************
+#define PWM_ENUPD_ENUPD7_M 0x0000C000 // PWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M 0x00003000 // PWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M 0x00000C00 // PWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M 0x00000300 // PWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M 0x000000C0 // PWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M 0x00000030 // PWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M 0x0000000C // PWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M 0x00000003 // PWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
+#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_X_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
+ // Down
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
+ // Down
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
+ // Down
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
+ // Up
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
+ // Down
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
+ // Up
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_X_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_X_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_X_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_X_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_X_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_X_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_X_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_X_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_X_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_X_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_X_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_X_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
+#define PWM_X_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
+#define PWM_X_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
+#define PWM_X_MINFLTPER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator standard offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
+#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition
+#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition
+#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
+#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator extended offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense
+#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status
+#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status
+#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base
+#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base
+#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base
+#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PWM_O_CTL
+// register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
+#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
+#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PWM_O_STATUS
+// register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT 0x00000001 // Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM Interrupt Register bit
+// definitions.
+//
+//*****************************************************************************
+#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Interrupt Status Register
+// bit definitions.
+//
+//*****************************************************************************
+#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
+#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
+#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
+#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
+#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
+#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Generator A/B Control
+// Register bit definitions.
+//
+//*****************************************************************************
+#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
+#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
+#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
+#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
+#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
+#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Generator A/B Control
+// Register action definitions.
+//
+//*****************************************************************************
+#define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one
+#define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero
+#define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal
+#define PWM_GEN_ACT_NONE 0x00000000 // Do nothing
+#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
+#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
+#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
+#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
+#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
+#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Dead Band Control
+// Register bit definitions.
+//
+//*****************************************************************************
+#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM Register reset values.
+//
+//*****************************************************************************
+#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
+#define PWM_RV_STATUS 0x00000000 // Status
+#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
+#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
+#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
+ // generator block
+#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
+#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
+ // count
+#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
+#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
+#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
+#define PWM_RV_CTL 0x00000000 // Master control of the PWM module
+#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
+ // output pins
+#define PWM_RV_RIS 0x00000000 // Raw interrupt status
+#define PWM_RV_X_CMPA 0x00000000 // The comparator A value
+#define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output
+ // pins
+#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
+ // count
+#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output
+ // pins
+#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
+#define PWM_RV_X_CMPB 0x00000000 // The comparator B value
+#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
+#define PWM_RV_INTEN 0x00000000 // Interrupt enable
+#define PWM_RV_X_COUNT 0x00000000 // The current counter value
+
+#endif
+
+#endif // __HW_PWM_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_qei.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_qei.h
new file mode 100644
index 00000000..2b6dbd54
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_qei.h
@@ -0,0 +1,201 @@
+//*****************************************************************************
+//
+// hw_qei.h - Macros used when accessing the QEI hardware.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_QEI_H__
+#define __HW_QEI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the QEI register offsets.
+//
+//*****************************************************************************
+#define QEI_O_CTL 0x00000000 // QEI Control
+#define QEI_O_STAT 0x00000004 // QEI Status
+#define QEI_O_POS 0x00000008 // QEI Position
+#define QEI_O_MAXPOS 0x0000000C // QEI Maximum Position
+#define QEI_O_LOAD 0x00000010 // QEI Timer Load
+#define QEI_O_TIME 0x00000014 // QEI Timer
+#define QEI_O_COUNT 0x00000018 // QEI Velocity Counter
+#define QEI_O_SPEED 0x0000001C // QEI Velocity
+#define QEI_O_INTEN 0x00000020 // QEI Interrupt Enable
+#define QEI_O_RIS 0x00000024 // QEI Raw Interrupt Status
+#define QEI_O_ISC 0x00000028 // QEI Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count
+#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter
+#define QEI_CTL_STALLEN 0x00001000 // Stall QEI
+#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse
+#define QEI_CTL_INVB 0x00000400 // Invert PhB
+#define QEI_CTL_INVA 0x00000200 // Invert PhA
+#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity
+#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1
+#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2
+#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4
+#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8
+#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16
+#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32
+#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64
+#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128
+#define QEI_CTL_VELEN 0x00000020 // Capture Velocity
+#define QEI_CTL_RESMODE 0x00000010 // Reset Mode
+#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode
+#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode
+#define QEI_CTL_SWAP 0x00000002 // Swap Signals
+#define QEI_CTL_ENABLE 0x00000001 // Enable QEI
+#define QEI_CTL_FILTCNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation
+#define QEI_STAT_ERROR 0x00000001 // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
+ // Value
+#define QEI_POS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
+ // Value
+#define QEI_MAXPOS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value
+#define QEI_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value
+#define QEI_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count
+#define QEI_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M 0xFFFFFFFF // Velocity
+#define QEI_SPEED_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
+ // Enable
+#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected
+#define QEI_RIS_DIR 0x00000004 // Direction Change Detected
+#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired
+#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt
+#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt
+#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the QEI_ISC
+// register.
+//
+//*****************************************************************************
+#define QEI_INT_ERROR 0x00000008 // Phase error detected
+#define QEI_INT_DIR 0x00000004 // Direction change
+#define QEI_INT_TIMER 0x00000002 // Velocity timer expired
+#define QEI_INT_INDEX 0x00000001 // Index pulse detected
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the QEI
+// registers.
+//
+//*****************************************************************************
+#define QEI_RV_POS 0x00000000 // Current position register
+#define QEI_RV_LOAD 0x00000000 // Velocity timer load register
+#define QEI_RV_CTL 0x00000000 // Configuration and control reg
+#define QEI_RV_RIS 0x00000000 // Raw interrupt status register
+#define QEI_RV_ISC 0x00000000 // Interrupt status register
+#define QEI_RV_SPEED 0x00000000 // Velocity speed register
+#define QEI_RV_INTEN 0x00000000 // Interrupt enable register
+#define QEI_RV_STAT 0x00000000 // Status register
+#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register
+#define QEI_RV_MAXPOS 0x00000000 // Maximum position register
+#define QEI_RV_TIME 0x00000000 // Velocity timer register
+
+#endif
+
+#endif // __HW_QEI_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_ssi.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_ssi.h
new file mode 100644
index 00000000..22706961
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_ssi.h
@@ -0,0 +1,217 @@
+//*****************************************************************************
+//
+// hw_ssi.h - Macros used when accessing the SSI hardware.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SSI_H__
+#define __HW_SSI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the SSI register offsets.
+//
+//*****************************************************************************
+#define SSI_O_CR0 0x00000000 // SSI Control 0
+#define SSI_O_CR1 0x00000004 // SSI Control 1
+#define SSI_O_DR 0x00000008 // SSI Data
+#define SSI_O_SR 0x0000000C // SSI Status
+#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale
+#define SSI_O_IM 0x00000014 // SSI Interrupt Mask
+#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status
+#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status
+#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear
+#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
+#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
+#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
+ // Serial Frame Format
+#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
+#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
+#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
+#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
+#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
+#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
+#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
+#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
+#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
+#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
+#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
+#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
+#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
+#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
+#define SSI_CR0_SCR_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_EOT 0x00000010 // End of Transmission
+#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
+#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
+#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
+ // Enable
+#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
+#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
+#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
+ // Mask
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
+ // Interrupt Status
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
+ // Interrupt Status
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
+ // Clear
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SSI_O_CR0
+// register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
+#define SSI_CR0_DSS 0x0000000F // Data size select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SSI_O_CPSR
+// register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the SSI controller's FIFO size.
+//
+//*****************************************************************************
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the interrupt
+// mask set and clear, raw interrupt, masked interrupt, and interrupt clear
+// registers.
+//
+//*****************************************************************************
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
+
+#endif
+
+#endif // __HW_SSI_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_sysctl.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_sysctl.h
new file mode 100644
index 00000000..2bcd8c71
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_sysctl.h
@@ -0,0 +1,1687 @@
+//*****************************************************************************
+//
+// hw_sysctl.h - Macros used when accessing the system control hardware.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSCTL_H__
+#define __HW_SYSCTL_H__
+
+//*****************************************************************************
+//
+// The following are defines for the System Control register addresses.
+//
+//*****************************************************************************
+#define SYSCTL_DID0 0x400FE000 // Device Identification 0
+#define SYSCTL_DID1 0x400FE004 // Device Identification 1
+#define SYSCTL_DC0 0x400FE008 // Device Capabilities 0
+#define SYSCTL_DC1 0x400FE010 // Device Capabilities 1
+#define SYSCTL_DC2 0x400FE014 // Device Capabilities 2
+#define SYSCTL_DC3 0x400FE018 // Device Capabilities 3
+#define SYSCTL_DC4 0x400FE01C // Device Capabilities 4
+#define SYSCTL_DC5 0x400FE020 // Device Capabilities 5
+#define SYSCTL_DC6 0x400FE024 // Device Capabilities 6
+#define SYSCTL_DC7 0x400FE028 // Device Capabilities 7
+#define SYSCTL_DC8 0x400FE02C // Device Capabilities 8 ADC
+ // Channels
+#define SYSCTL_PBORCTL 0x400FE030 // Brown-Out Reset Control
+#define SYSCTL_LDOPCTL 0x400FE034 // LDO Power Control
+#define SYSCTL_SRCR0 0x400FE040 // Software Reset Control 0
+#define SYSCTL_SRCR1 0x400FE044 // Software Reset Control 1
+#define SYSCTL_SRCR2 0x400FE048 // Software Reset Control 2
+#define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status
+#define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control
+#define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and
+ // Clear
+#define SYSCTL_RESC 0x400FE05C // Reset Cause
+#define SYSCTL_RCC 0x400FE060 // Run-Mode Clock Configuration
+#define SYSCTL_PLLCFG 0x400FE064 // XTAL to PLL Translation
+#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO High-Performance Bus
+ // Control
+#define SYSCTL_RCC2 0x400FE070 // Run-Mode Clock Configuration 2
+#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control
+#define SYSCTL_RCGC0 0x400FE100 // Run Mode Clock Gating Control
+ // Register 0
+#define SYSCTL_RCGC1 0x400FE104 // Run Mode Clock Gating Control
+ // Register 1
+#define SYSCTL_RCGC2 0x400FE108 // Run Mode Clock Gating Control
+ // Register 2
+#define SYSCTL_SCGC0 0x400FE110 // Sleep Mode Clock Gating Control
+ // Register 0
+#define SYSCTL_SCGC1 0x400FE114 // Sleep Mode Clock Gating Control
+ // Register 1
+#define SYSCTL_SCGC2 0x400FE118 // Sleep Mode Clock Gating Control
+ // Register 2
+#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep Mode Clock Gating
+ // Control Register 0
+#define SYSCTL_DCGC1 0x400FE124 // Deep-Sleep Mode Clock Gating
+ // Control Register 1
+#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating
+ // Control Register 2
+#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration
+#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator
+ // Calibration
+#define SYSCTL_CLKVCLR 0x400FE150 // Clock Verification Clear
+#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator
+ // Statistics
+#define SYSCTL_LDOARST 0x400FE160 // Allow Unregulated LDO to Reset
+ // the Part
+#define SYSCTL_I2SMCLKCFG 0x400FE170 // I2S MCLK Configuration
+#define SYSCTL_DC9 0x400FE190 // Device Capabilities 9 ADC
+ // Digital Comparators
+#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version
+#define SYSCTL_DID0_VER_0 0x00000000 // Initial DID0 register format
+ // definition for Stellaris(R)
+ // Sandstorm-class devices
+#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
+ // register format
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
+#define SYSCTL_DID0_CLASS_SANDSTORM \
+ 0x00000000 // Sandstorm-class Device
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Stellaris(R) Fury-class devices
+#define SYSCTL_DID0_CLASS_DUSTDEVIL \
+ 0x00030000 // Stellaris(R) DustDevil-class
+ // devices
+#define SYSCTL_DID0_CLASS_TEMPEST \
+ 0x00040000 // Stellaris(R) Tempest-class
+ // microcontrollers
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
+ // revision)
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
+ // revision)
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision
+#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
+ // revision update
+#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change
+#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change
+#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3
+#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4
+#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version
+#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format
+ // definition, indicating a
+ // Stellaris LM3Snnn device
+#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1
+ // register format
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family
+#define SYSCTL_DID1_FAM_STELLARIS \
+ 0x00000000 // Stellaris family of
+ // microcontollers, that is, all
+ // devices with external part
+ // numbers starting with LM3S
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
+#define SYSCTL_DID1_PRTNO_300 0x00190000 // LM3S300
+#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301
+#define SYSCTL_DID1_PRTNO_308 0x001A0000 // LM3S308
+#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310
+#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315
+#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316
+#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317
+#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328
+#define SYSCTL_DID1_PRTNO_600 0x002A0000 // LM3S600
+#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601
+#define SYSCTL_DID1_PRTNO_608 0x002B0000 // LM3S608
+#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610
+#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611
+#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612
+#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613
+#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615
+#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617
+#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618
+#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628
+#define SYSCTL_DID1_PRTNO_800 0x00380000 // LM3S800
+#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801
+#define SYSCTL_DID1_PRTNO_808 0x00390000 // LM3S808
+#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811
+#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812
+#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815
+#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817
+#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818
+#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828
+#define SYSCTL_DID1_PRTNO_1110 0x00BF0000 // LM3S1110
+#define SYSCTL_DID1_PRTNO_1133 0x00C30000 // LM3S1133
+#define SYSCTL_DID1_PRTNO_1138 0x00C50000 // LM3S1138
+#define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150
+#define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162
+#define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165
+#define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332
+#define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435
+#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439
+#define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512
+#define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538
+#define SYSCTL_DID1_PRTNO_1601 0x00DB0000 // LM3S1601
+#define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607
+#define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608
+#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620
+#define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625
+#define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626
+#define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627
+#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635
+#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637
+#define SYSCTL_DID1_PRTNO_1651 0x00B10000 // LM3S1651
+#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751
+#define SYSCTL_DID1_PRTNO_1776 0x00100000 // LM3S1776
+#define SYSCTL_DID1_PRTNO_1811 0x00160000 // LM3S1811
+#define SYSCTL_DID1_PRTNO_1816 0x003D0000 // LM3S1816
+#define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850
+#define SYSCTL_DID1_PRTNO_1911 0x00DD0000 // LM3S1911
+#define SYSCTL_DID1_PRTNO_1918 0x00DC0000 // LM3S1918
+#define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937
+#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958
+#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960
+#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968
+#define SYSCTL_DID1_PRTNO_1J11 0x000F0000 // LM3S1J11
+#define SYSCTL_DID1_PRTNO_1J16 0x003C0000 // LM3S1J16
+#define SYSCTL_DID1_PRTNO_1N11 0x000E0000 // LM3S1N11
+#define SYSCTL_DID1_PRTNO_1N16 0x003B0000 // LM3S1N16
+#define SYSCTL_DID1_PRTNO_1P51 0x00B20000 // LM3S1P51
+#define SYSCTL_DID1_PRTNO_1R21 0x009E0000 // LM3S1R21
+#define SYSCTL_DID1_PRTNO_1W16 0x00300000 // LM3S1W16
+#define SYSCTL_DID1_PRTNO_1Z16 0x002F0000 // LM3S1Z16
+#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110
+#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139
+#define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276
+#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410
+#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412
+#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432
+#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533
+#define SYSCTL_DID1_PRTNO_2601 0x00E10000 // LM3S2601
+#define SYSCTL_DID1_PRTNO_2608 0x00E00000 // LM3S2608
+#define SYSCTL_DID1_PRTNO_2616 0x00330000 // LM3S2616
+#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620
+#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637
+#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651
+#define SYSCTL_DID1_PRTNO_2671 0x00800000 // LM3S2671
+#define SYSCTL_DID1_PRTNO_2678 0x00500000 // LM3S2678
+#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730
+#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739
+#define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776
+#define SYSCTL_DID1_PRTNO_2793 0x006D0000 // LM3S2793
+#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911
+#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918
+#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939
+#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948
+#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950
+#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965
+#define SYSCTL_DID1_PRTNO_2B93 0x006C0000 // LM3S2B93
+#define SYSCTL_DID1_PRTNO_3634 0x00080000 // LM3S3634
+#define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651
+#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739
+#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748
+#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749
+#define SYSCTL_DID1_PRTNO_3826 0x00420000 // LM3S3826
+#define SYSCTL_DID1_PRTNO_3J26 0x00410000 // LM3S3J26
+#define SYSCTL_DID1_PRTNO_3N26 0x00400000 // LM3S3N26
+#define SYSCTL_DID1_PRTNO_3W26 0x003F0000 // LM3S3W26
+#define SYSCTL_DID1_PRTNO_3Z26 0x003E0000 // LM3S3Z26
+#define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632
+#define SYSCTL_DID1_PRTNO_5651 0x000C0000 // LM3S5651
+#define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652
+#define SYSCTL_DID1_PRTNO_5656 0x004D0000 // LM3S5656
+#define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662
+#define SYSCTL_DID1_PRTNO_5732 0x00960000 // LM3S5732
+#define SYSCTL_DID1_PRTNO_5737 0x00970000 // LM3S5737
+#define SYSCTL_DID1_PRTNO_5739 0x00A00000 // LM3S5739
+#define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747
+#define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749
+#define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752
+#define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762
+#define SYSCTL_DID1_PRTNO_5791 0x00690000 // LM3S5791
+#define SYSCTL_DID1_PRTNO_5951 0x000B0000 // LM3S5951
+#define SYSCTL_DID1_PRTNO_5956 0x004E0000 // LM3S5956
+#define SYSCTL_DID1_PRTNO_5B91 0x00680000 // LM3S5B91
+#define SYSCTL_DID1_PRTNO_5K31 0x00090000 // LM3S5K31
+#define SYSCTL_DID1_PRTNO_5K36 0x004A0000 // LM3S5K36
+#define SYSCTL_DID1_PRTNO_5P31 0x000A0000 // LM3S5P31
+#define SYSCTL_DID1_PRTNO_5P36 0x00480000 // LM3S5P36
+#define SYSCTL_DID1_PRTNO_5P51 0x000D0000 // LM3S5P51
+#define SYSCTL_DID1_PRTNO_5P56 0x004C0000 // LM3S5P56
+#define SYSCTL_DID1_PRTNO_5R31 0x00070000 // LM3S5R31
+#define SYSCTL_DID1_PRTNO_5R36 0x004B0000 // LM3S5R36
+#define SYSCTL_DID1_PRTNO_5T36 0x00470000 // LM3S5T36
+#define SYSCTL_DID1_PRTNO_5Y36 0x00460000 // LM3S5Y36
+#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100
+#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110
+#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420
+#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422
+#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432
+#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537
+#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610
+#define SYSCTL_DID1_PRTNO_6611 0x00E70000 // LM3S6611
+#define SYSCTL_DID1_PRTNO_6618 0x00E60000 // LM3S6618
+#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633
+#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637
+#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730
+#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753
+#define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911
+#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918
+#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938
+#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950
+#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952
+#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965
+#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530
+#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538
+#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630
+#define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730
+#define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733
+#define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738
+#define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930
+#define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933
+#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938
+#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962
+#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970
+#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971
+#define SYSCTL_DID1_PRTNO_9790 0x00670000 // LM3S9790
+#define SYSCTL_DID1_PRTNO_9792 0x006B0000 // LM3S9792
+#define SYSCTL_DID1_PRTNO_9997 0x00200000 // LM3S9997
+#define SYSCTL_DID1_PRTNO_9B90 0x00660000 // LM3S9B90
+#define SYSCTL_DID1_PRTNO_9B92 0x006A0000 // LM3S9B92
+#define SYSCTL_DID1_PRTNO_9B95 0x006E0000 // LM3S9B95
+#define SYSCTL_DID1_PRTNO_9B96 0x006F0000 // LM3S9B96
+#define SYSCTL_DID1_PRTNO_9L97 0x00180000 // LM3S9L97
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count
+#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package
+#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package
+#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C
+ // to 70C)
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
+ // (-40C to 85C)
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
+ // to 105C)
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type
+#define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
+#define SYSCTL_DID1_PKG_QFN 0x00000018 // QFN package
+#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
+#define SYSCTL_DID1_PRTNO_S 16 // Part number shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_96KB 0x017F0000 // 96 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
+#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
+#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present
+#define SYSCTL_DC1_CAN2 0x04000000 // CAN Module 2 Present
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present
+#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present
+#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present
+#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider
+#define SYSCTL_DC1_MINSYSDIV_100 \
+ 0x00001000 // Divide VCO (400MHZ) by 5 minimum
+#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Divide VCO (400MHZ) by 2*2 + 2 =
+ // 6 minimum
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
+ // with a PLL divider of 4
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
+ // PLL divider of 8
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
+ // PLL divider of 10
+#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // Max ADC Speed
+#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
+#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250K samples/second
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500K samples/second
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed
+#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed
+#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DC1_MPU 0x00000080 // MPU Present
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present
+#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present
+#define SYSCTL_DC1_PLL 0x00000010 // PLL Present
+#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present
+#define SYSCTL_DC1_SWD 0x00000002 // SWD Present
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present
+#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present
+#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present
+#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present
+#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 Pin Present
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 Pin Present
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present
+#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present
+#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present
+#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present
+#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present
+#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable
+#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate
+#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present
+#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present
+#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present
+#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present
+#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present
+#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present
+#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present
+#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present
+#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active
+#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active
+#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present
+#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present
+#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present
+#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present
+#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host
+#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_SW 0x40000000 // Software transfer on uDMA Ch30
+#define SYSCTL_DC7_DMACH30 0x40000000 // SW
+#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX / CAN1_TX
+#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX / CAN1_RX
+#define SYSCTL_DC7_DMACH27 0x08000000 // CAN1_TX / ADC1_SS3
+#define SYSCTL_DC7_DMACH26 0x04000000 // CAN1_RX / ADC1_SS2
+#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1
+#define SYSCTL_DC7_SSI1_TX 0x02000000 // SSI1 TX on uDMA Ch25
+#define SYSCTL_DC7_SSI1_RX 0x01000000 // SSI1 RX on uDMA Ch24
+#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0
+#define SYSCTL_DC7_UART1_TX 0x00800000 // UART1 TX on uDMA Ch23
+#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX / CAN2_TX
+#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX / CAN2_RX
+#define SYSCTL_DC7_UART1_RX 0x00400000 // UART1 RX on uDMA Ch22
+#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_WFIFO
+#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_NBRFIFO
+#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B
+#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A
+#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3
+#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2
+#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B
+#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A
+#define SYSCTL_DC7_DMACH13 0x00002000 // CAN0_TX / UART2_TX
+#define SYSCTL_DC7_DMACH12 0x00001000 // CAN0_RX / UART2_RX
+#define SYSCTL_DC7_SSI0_TX 0x00000800 // SSI0 TX on uDMA Ch11
+#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / SSI1_TX
+#define SYSCTL_DC7_SSI0_RX 0x00000400 // SSI0 RX on uDMA Ch10
+#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / SSI1_RX
+#define SYSCTL_DC7_UART0_TX 0x00000200 // UART0 TX on uDMA Ch9
+#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / UART1_TX
+#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / UART1_RX
+#define SYSCTL_DC7_UART0_RX 0x00000100 // UART0 RX on uDMA Ch8
+#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B
+#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A
+#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B
+#define SYSCTL_DC7_USB_EP3_TX 0x00000020 // USB EP3 TX on uDMA Ch5
+#define SYSCTL_DC7_USB_EP3_RX 0x00000010 // USB EP3 RX on uDMA Ch4
+#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A
+#define SYSCTL_DC7_USB_EP2_TX 0x00000008 // USB EP2 TX on uDMA Ch3
+#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B
+#define SYSCTL_DC7_USB_EP2_RX 0x00000004 // USB EP2 RX on uDMA Ch2
+#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A
+#define SYSCTL_DC7_USB_EP1_TX 0x00000002 // USB EP1 TX on uDMA Ch1
+#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX
+#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX
+#define SYSCTL_DC7_USB_EP1_RX 0x00000001 // USB EP1 RX on uDMA Ch0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present
+#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present
+#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present
+#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present
+#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present
+#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present
+#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present
+#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present
+#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present
+#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present
+#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present
+#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present
+#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present
+#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present
+#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present
+#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present
+#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present
+#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present
+#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present
+#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present
+#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present
+#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present
+#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present
+#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present
+#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC // BOR Time Delay
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR Wait and Check for Noise
+#define SYSCTL_PBORCTL_BORTIM_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // 2.50
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // 2.45
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // 2.40
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // 2.35
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // 2.30
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // 2.25
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // 2.75
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // 2.70
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // 2.65
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // 2.60
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // 2.55
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control
+#define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control
+#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control
+#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control
+#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control
+#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control
+#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_EPI0 0x40000000 // EPI0 Reset Control
+#define SYSCTL_SRCR1_I2S0 0x10000000 // I2S0 Reset Control
+#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control
+#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control
+#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control
+#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control
+#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control
+#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control
+#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
+ // Status
+#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt
+ // Status
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_CLRIS 0x00000020 // Current Limit Raw Interrupt
+ // Status
+#define SYSCTL_RIS_IOFRIS 0x00000010 // Internal Oscillator Fault Raw
+ // Interrupt Status
+#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw
+ // Interrupt Status
+#define SYSCTL_RIS_LDORIS 0x00000004 // LDO Power Unregulated Raw
+ // Interrupt Status
+#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
+ // Status
+#define SYSCTL_RIS_PLLFRIS 0x00000001 // PLL Fault Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_CLIM 0x00000020 // Current Limit Interrupt Mask
+#define SYSCTL_IMC_IOFIM 0x00000010 // Internal Oscillator Fault
+ // Interrupt Mask
+#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt
+ // Mask
+#define SYSCTL_IMC_LDOIM 0x00000004 // LDO Power Unregulated Interrupt
+ // Mask
+#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask
+#define SYSCTL_IMC_PLLFIM 0x00000001 // PLL Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
+ // Status
+#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt
+ // Status
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_CLMIS 0x00000020 // Current Limit Masked Interrupt
+ // Status
+#define SYSCTL_MISC_IOFMIS 0x00000010 // Internal Oscillator Fault Masked
+ // Interrupt Status
+#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked
+ // Interrupt Status
+#define SYSCTL_MISC_LDOMIS 0x00000004 // LDO Power Unregulated Masked
+ // Interrupt Status
+#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset
+#define SYSCTL_RESC_LDO 0x00000020 // LDO Reset
+#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW 0x00000010 // Software Reset
+#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset
+#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset
+#define SYSCTL_RESC_EXT 0x00000001 // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down
+#define SYSCTL_RCC_OEN 0x00001000 // PLL Output Enable
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass
+#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value
+#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // 1 MHz
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // 1.8432 MHz
+#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // 2 MHz
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // 2.4576 MHz
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // 3.579545 MHz
+#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // 3.6864 MHz
+#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
+#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz
+#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL Verification
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC_IOSCVER 0x00000008 // Internal Oscillator Verification
+ // Timer
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main Oscillator Verification
+ // Timer
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S 23
+#define SYSCTL_RCC_PWMDIV_S 17 // Shift to the PWMDIV field
+#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field
+#define SYSCTL_RCC_OSCSRC_S 4 // Shift to the OSCSRC field
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_OD_M 0x0000C000 // PLL OD Value
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Divide by 1
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Divide by 2
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Divide by 4
+#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value
+#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value
+#define SYSCTL_PLLCFG_F_S 5
+#define SYSCTL_PLLCFG_R_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance
+ // Bus
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
+#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200
+ // MHz
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
+#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2
+#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC2_OSCSRC2_419 0x00000060 // 4.194304 MHz
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz
+#define SYSCTL_RCC2_SYSDIV2_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control
+#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed
+#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed
+#define SYSCTL_RCGC0_ADC1SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_250K \
+ 0x00000400 // 250K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_500K \
+ 0x00000800 // 500K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed
+#define SYSCTL_RCGC0_ADC0SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_250K \
+ 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_500K \
+ 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_EPI0 0x40000000 // EPI0 Clock Gating
+#define SYSCTL_RCGC1_I2S0 0x10000000 // I2S0 Clock Gating
+#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control
+#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control
+#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control
+#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed
+#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second
+#define SYSCTL_SCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed
+#define SYSCTL_SCGC0_ADC1SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_250K \
+ 0x00000400 // 250K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_500K \
+ 0x00000800 // 500K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_SCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed
+#define SYSCTL_SCGC0_ADC0SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_250K \
+ 0x00000100 // 250K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_500K \
+ 0x00000200 // 500K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_EPI0 0x40000000 // EPI0 Clock Gating
+#define SYSCTL_SCGC1_I2S0 0x10000000 // I2S0 Clock Gating
+#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control
+#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control
+#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control
+#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_EPI0 0x40000000 // EPI0 Clock Gating
+#define SYSCTL_DCGC1_I2S0 0x10000000 // I2S0 Clock Gating
+#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control
+#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control
+#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_D_1 0x00000000 // System clock /1
+#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2
+#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3
+#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4
+#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5
+#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6
+#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7
+#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8
+#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9
+#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10
+#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11
+#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12
+#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13
+#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14
+#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15
+#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16
+#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17
+#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18
+#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19
+#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20
+#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21
+#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22
+#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23
+#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24
+#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25
+#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26
+#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27
+#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28
+#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29
+#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30
+#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31
+#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32
+#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33
+#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34
+#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35
+#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36
+#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37
+#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38
+#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39
+#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40
+#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41
+#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42
+#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43
+#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44
+#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45
+#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46
+#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47
+#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48
+#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49
+#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50
+#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51
+#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52
+#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53
+#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54
+#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55
+#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56
+#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57
+#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58
+#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59
+#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60
+#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61
+#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62
+#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63
+#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz
+#define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source
+#define SYSCTL_DSLPCLKCFG_D_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value
+#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration
+#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value
+#define SYSCTL_PIOSCCAL_UT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_CLKVCLR register.
+//
+//*****************************************************************************
+#define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value
+#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result
+#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been
+ // attempted
+#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation
+ // completed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation
+ // failed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value
+#define SYSCTL_PIOSCSTAT_DT_S 16
+#define SYSCTL_PIOSCSTAT_CT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOARST register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_I2SMCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_I2SMCLKCFG_RXEN 0x80000000 // RX Clock Enable
+#define SYSCTL_I2SMCLKCFG_RXI_M 0x3FF00000 // RX Clock Integer Input
+#define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000 // RX Clock Fractional Input
+#define SYSCTL_I2SMCLKCFG_TXEN 0x00008000 // TX Clock Enable
+#define SYSCTL_I2SMCLKCFG_TXI_M 0x00003FF0 // TX Clock Integer Input
+#define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F // TX Clock Fractional Input
+#define SYSCTL_I2SMCLKCFG_RXI_S 20
+#define SYSCTL_I2SMCLKCFG_RXF_S 16
+#define SYSCTL_I2SMCLKCFG_TXI_S 4
+#define SYSCTL_I2SMCLKCFG_TXF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC9 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present
+#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present
+#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present
+#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present
+#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present
+#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present
+#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present
+#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present
+#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present
+#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present
+#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present
+#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present
+#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present
+#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present
+#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present
+#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_TPSW 0x00000010 // Third Party Software Present
+#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer
+ // Active
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the System Control register
+// addresses.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High-Speed Control
+#define SYSCTL_USER0 0x400FE1E0 // NV User Register 0
+#define SYSCTL_USER1 0x400FE1E4 // NV User Register 1
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DID0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask
+#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
+#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DID1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
+#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // QFP package
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PRTNO_SHIFT 16
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_ADC 0x00010000 // ADC Module Present
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
+#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
+#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC2
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present
+#define SYSCTL_DC2_QEI 0x00000100 // QEI present
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC3
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 Pin Present
+#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 Pin Present
+#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 Pin Present
+#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 Pin Present
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 Pin Present
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 Pin Present
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 Pin Present
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 Pin Present
+#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer
+#define SYSCTL_PBORCTL_BOR_SH 2
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control
+#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RESC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
+#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider
+#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider
+#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864 MHz crystal
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4 MHz crystal
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field
+#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider
+#define SYSCTL_PLLCFG_F_SHIFT 5
+#define SYSCTL_PLLCFG_R_SHIFT 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_GPIOHSCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed
+#define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed
+#define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed
+#define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed
+#define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed
+#define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed
+#define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed
+#define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCC2
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USEFRACT 0x40000000 // Use fractional divider
+#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider
+#define SYSCTL_RCC2_FRACT 0x00400000 // Fractional divide
+#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCGC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SCGC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DCGC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_DSLPCLKCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000 // Deep sleep system clock override
+#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_CLKVCLR register.
+//
+//*****************************************************************************
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_LDOARST register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0,
+// SYSCTL_RCGC0, SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
+//
+//*****************************************************************************
+#define SYSCTL_SET0_CAN2 0x04000000 // CAN 2 module
+#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module
+#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module
+#define SYSCTL_SET0_PWM 0x00100000 // PWM module
+#define SYSCTL_SET0_ADC 0x00010000 // ADC module
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC
+#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC
+#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR1,
+// SYSCTL_RCGC1, SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
+//
+//*****************************************************************************
+#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0
+#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3
+#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0
+#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1
+#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module
+#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1
+#define SYSCTL_SET1_QEI 0x00000100 // QEI module
+#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0
+#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1
+#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module
+#define SYSCTL_SET1_UART2 0x00000004 // UART module 2
+#define SYSCTL_SET1_UART1 0x00000002 // UART module 1
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR2,
+// SYSCTL_RCGC2, SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
+//
+//*****************************************************************************
+#define SYSCTL_SET2_ETH 0x50000000 // ETH module
+#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module
+#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module
+#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module
+#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module
+#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RIS,
+// SYSCTL_IMC, and SYSCTL_IMS registers.
+//
+//*****************************************************************************
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
+
+#endif
+
+#endif // __HW_SYSCTL_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_timer.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_timer.h
new file mode 100644
index 00000000..2a2cac71
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_timer.h
@@ -0,0 +1,474 @@
+//*****************************************************************************
+//
+// hw_timer.h - Defines and macros used when accessing the timer.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TIMER_H__
+#define __HW_TIMER_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Timer register offsets.
+//
+//*****************************************************************************
+#define TIMER_O_CFG 0x00000000 // GPTM Configuration
+#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
+#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
+#define TIMER_O_CTL 0x0000000C // GPTM Control
+#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
+#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
+#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
+#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
+#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
+#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
+#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
+#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
+#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
+#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
+#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
+#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
+#define TIMER_O_TAR 0x00000048 // GPTM Timer A
+#define TIMER_O_TBR 0x0000004C // GPTM Timer B
+#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
+#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
+ // counter configuration
+#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
+ // function is controlled by bits
+ // 1:0 of GPTMTAMR and GPTMTBMR
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
+ // Enable
+#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
+ // Select
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
+ // Enable
+#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
+ // Select
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
+ // Enable
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
+#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
+ // Enable
+#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
+#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt
+ // Mask
+#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt
+ // Mask
+#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Mask
+#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt
+ // Mask
+#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt
+ // Mask
+#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw
+ // Interrupt
+#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw
+ // Interrupt
+#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw
+ // Interrupt
+#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
+ // Interrupt
+#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw
+ // Interrupt
+#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw
+ // Interrupt
+#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw
+ // Interrupt
+#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked
+ // Interrupt
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked
+ // Interrupt
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked
+ // Interrupt
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
+ // Interrupt
+#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked
+ // Interrupt
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked
+ // Interrupt
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked
+ // Interrupt
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt
+ // Clear
+#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt
+ // Clear
+#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Clear
+#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt
+ // Clear
+#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt
+ // Clear
+#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load
+ // Register High
+#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load
+ // Register Low
+#define TIMER_TAILR_TAILRH_S 16
+#define TIMER_TAILR_TAILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load
+ // Register
+#define TIMER_TBILR_TBILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High
+#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low
+#define TIMER_TAMATCHR_TAMRH_S 16
+#define TIMER_TAMATCHR_TAMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low
+#define TIMER_TBMATCHR_TBMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High
+#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low
+#define TIMER_TAR_TARH_S 16
+#define TIMER_TAR_TARL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B
+#define TIMER_TBR_TBRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High
+#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low
+#define TIMER_TAV_TAVH_S 16
+#define TIMER_TAV_TAVL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register
+#define TIMER_TBV_TBVL_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_CFG
+// register.
+//
+//*****************************************************************************
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_CTL
+// register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_RIS
+// register.
+//
+//*****************************************************************************
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TAILR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TBILR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// TIMER_O_TAMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// TIMER_O_TBMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TAR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TBR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the timer
+// registers.
+//
+//*****************************************************************************
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
+#define TIMER_RV_CTL 0x00000000 // Control register RV
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnMR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnPR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnPMR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
+
+#endif
+
+#endif // __HW_TIMER_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_types.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_types.h
new file mode 100644
index 00000000..c62428aa
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_types.h
@@ -0,0 +1,185 @@
+//*****************************************************************************
+//
+// hw_types.h - Common types and macros.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TYPES_H__
+#define __HW_TYPES_H__
+
+//*****************************************************************************
+//
+// Define a boolean type, and values for true and false.
+//
+//*****************************************************************************
+typedef unsigned char tBoolean;
+
+#ifndef true
+#define true 1
+#endif
+
+#ifndef false
+#define false 0
+#endif
+
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x) \
+ (*((volatile unsigned long *)(x)))
+#define HWREGH(x) \
+ (*((volatile unsigned short *)(x)))
+#define HWREGB(x) \
+ (*((volatile unsigned char *)(x)))
+#define HWREGBITW(x, b) \
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITH(x, b) \
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITB(x, b) \
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+//*****************************************************************************
+//
+// Helper Macros for determining silicon revisions, etc.
+//
+// These macros will be used by Driverlib at "run-time" to create necessary
+// conditional code blocks that will allow a single version of the Driverlib
+// "binary" code to support multiple(all) Stellaris silicon revisions.
+//
+// It is expected that these macros will be used inside of a standard 'C'
+// conditional block of code, e.g.
+//
+// if(CLASS_IS_SANDSTORM)
+// {
+// do some Sandstorm-class specific code here.
+// }
+//
+// By default, these macros will be defined as run-time checks of the
+// appropriate register(s) to allow creation of run-time conditional code
+// blocks for a common DriverLib across the entire Stellaris family.
+//
+// However, if code-space optimization is required, these macros can be "hard-
+// coded" for a specific version of Stellaris silicon. Many compilers will
+// then detect the "hard-coded" conditionals, and appropriately optimize the
+// code blocks, eliminating any "unreachable" code. This would result in
+// a smaller Driverlib, thus producing a smaller final application size, but
+// at the cost of limiting the Driverlib binary to a specific Stellaris
+// silicon revision.
+//
+//*****************************************************************************
+#ifndef CLASS_IS_SANDSTORM
+#define CLASS_IS_SANDSTORM \
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM)))
+#endif
+
+#ifndef CLASS_IS_FURY
+#define CLASS_IS_FURY \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY))
+#endif
+
+#ifndef CLASS_IS_DUSTDEVIL
+#define CLASS_IS_DUSTDEVIL \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))
+#endif
+
+#ifndef CLASS_IS_TEMPEST
+#define CLASS_IS_TEMPEST \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST))
+#endif
+
+#ifndef REVISION_IS_A0
+#define REVISION_IS_A0 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A1
+#define REVISION_IS_A1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A2
+#define REVISION_IS_A2 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
+#endif
+
+#ifndef REVISION_IS_B0
+#define REVISION_IS_B0 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_B1
+#define REVISION_IS_B1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
+#endif
+
+#ifndef REVISION_IS_C0
+#define REVISION_IS_C0 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_C1
+#define REVISION_IS_C1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1))
+#endif
+
+#ifndef REVISION_IS_C2
+#define REVISION_IS_C2 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
+#endif
+
+#ifndef REVISION_IS_C3
+#define REVISION_IS_C3 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3))
+#endif
+
+//*****************************************************************************
+//
+// Deprecated silicon class and revision detection macros.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM
+#define DEVICE_IS_FURY CLASS_IS_FURY
+#define DEVICE_IS_REVA2 REVISION_IS_A2
+#define DEVICE_IS_REVC1 REVISION_IS_C1
+#define DEVICE_IS_REVC2 REVISION_IS_C2
+#endif
+
+#endif // __HW_TYPES_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_uart.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_uart.h
new file mode 100644
index 00000000..b6613861
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_uart.h
@@ -0,0 +1,458 @@
+//*****************************************************************************
+//
+// hw_uart.h - Macros and defines used when accessing the UART hardware.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UART_H__
+#define __HW_UART_H__
+
+//*****************************************************************************
+//
+// The following are defines for the UART register offsets.
+//
+//*****************************************************************************
+#define UART_O_DR 0x00000000 // UART Data
+#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear
+#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear
+#define UART_O_FR 0x00000018 // UART Flag
+#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
+#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor
+#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate
+ // Divisor
+#define UART_O_LCRH 0x0000002C // UART Line Control
+#define UART_O_CTL 0x00000030 // UART Control
+#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select
+#define UART_O_IM 0x00000038 // UART Interrupt Mask
+#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status
+#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status
+#define UART_O_ICR 0x00000044 // UART Interrupt Clear
+#define UART_O_DMACTL 0x00000048 // UART DMA Control
+#define UART_O_LCTL 0x00000090 // UART LIN Control
+#define UART_O_LSS 0x00000094 // UART LIN Snap Shot
+#define UART_O_LTIM 0x00000098 // UART LIN Timer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE 0x00000800 // UART Overrun Error
+#define UART_DR_BE 0x00000400 // UART Break Error
+#define UART_DR_PE 0x00000200 // UART Parity Error
+#define UART_DR_FE 0x00000100 // UART Framing Error
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE 0x00000008 // UART Overrun Error
+#define UART_RSR_BE 0x00000004 // UART Break Error
+#define UART_RSR_PE 0x00000002 // UART Parity Error
+#define UART_RSR_FE 0x00000001 // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear
+#define UART_ECR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_RI 0x00000100 // Ring Indicator
+#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
+#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
+#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
+#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
+#define UART_FR_BUSY 0x00000008 // UART Busy
+#define UART_FR_DCD 0x00000004 // Data Carrier Detect
+#define UART_FR_DSR 0x00000002 // Data Set Ready
+#define UART_FR_CTS 0x00000001 // Clear To Send
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
+#define UART_LCRH_BRK 0x00000001 // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
+#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
+#define UART_CTL_RTS 0x00000800 // Request to Send
+#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
+#define UART_CTL_RXE 0x00000200 // UART Receive Enable
+#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
+#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
+#define UART_CTL_LIN 0x00000040 // LIN Mode Enable
+#define UART_CTL_HSE 0x00000020 // High-Speed Enable
+#define UART_CTL_EOT 0x00000010 // End of Transmission
+#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
+#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
+#define UART_CTL_UARTEN 0x00000001 // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
+ // Level Select
+#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
+ // Level Select
+#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
+#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
+#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
+ // Mask
+#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
+ // Mask
+#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
+#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
+ // Mask
+#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
+ // Mask
+#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
+#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
+#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Mask
+#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Mask
+#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
+ // Interrupt Mask
+#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
+ // Status
+#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
+ // Status
+#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
+ // Interrupt Status
+#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
+ // Status
+#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
+ // Status
+#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
+ // Status
+#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
+ // Status
+#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
+ // Interrupt Status
+#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
+ // Status
+#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
+ // Status
+#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
+ // Interrupt Status
+#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
+ // Raw Interrupt Status
+#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
+ // Interrupt Status
+#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
+ // Status
+#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
+ // Status
+#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
+ // Interrupt Status
+#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
+ // Interrupt Status
+#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
+ // Interrupt Status
+#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
+ // Interrupt Status
+#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
+ // Interrupt Status
+#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
+ // Interrupt Status
+#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
+ // Status
+#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
+ // Status
+#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
+ // Interrupt Status
+#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
+ // Masked Interrupt Status
+#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
+ // Interrupt Status
+#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
+#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
+#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
+ // Clear
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
+#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
+#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Clear
+#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Clear
+#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
+ // Interrupt Clear
+#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
+#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCTL register.
+//
+//*****************************************************************************
+#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length
+#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits
+ // (default)
+#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits
+#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits
+#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits
+#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LSS register.
+//
+//*****************************************************************************
+#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
+#define UART_LSS_TSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LTIM register.
+//
+//*****************************************************************************
+#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
+#define UART_LTIM_TIMER_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the UART register offsets.
+//
+//*****************************************************************************
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
+#define UART_O_PeriphID4 0x00000FD0
+#define UART_O_PeriphID5 0x00000FD4
+#define UART_O_PeriphID6 0x00000FD8
+#define UART_O_PeriphID7 0x00000FDC
+#define UART_O_PeriphID0 0x00000FE0
+#define UART_O_PeriphID1 0x00000FE4
+#define UART_O_PeriphID2 0x00000FE8
+#define UART_O_PeriphID3 0x00000FEC
+#define UART_O_PCellID0 0x00000FF0
+#define UART_O_PCellID1 0x00000FF4
+#define UART_O_PCellID2 0x00000FF8
+#define UART_O_PCellID3 0x00000FFC
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UART_O_DR
+// register.
+//
+//*****************************************************************************
+#define UART_DR_DATA_MASK 0x000000FF // UART data
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UART_O_IBRD
+// register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UART_O_FBRD
+// register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UART_O_LCR_H
+// register.
+//
+//*****************************************************************************
+#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
+#define UART_LCR_H_WLEN 0x00000060 // Word length
+#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
+#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
+#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
+#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
+#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
+#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
+#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
+#define UART_LCR_H_PEN 0x00000002 // Parity Enable
+#define UART_LCR_H_BRK 0x00000001 // Send Break
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UART_O_IFLS
+// register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask
+#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UART_O_ICR
+// register.
+//
+//*****************************************************************************
+#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
+ UART_RSR_FE)
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Reset Values for UART
+// Registers.
+//
+//*****************************************************************************
+#define UART_RV_CTL 0x00000300
+#define UART_RV_PCellID1 0x000000F0
+#define UART_RV_PCellID3 0x000000B1
+#define UART_RV_FR 0x00000090
+#define UART_RV_PeriphID2 0x00000018
+#define UART_RV_IFLS 0x00000012
+#define UART_RV_PeriphID0 0x00000011
+#define UART_RV_PCellID0 0x0000000D
+#define UART_RV_PCellID2 0x00000005
+#define UART_RV_PeriphID3 0x00000001
+#define UART_RV_PeriphID4 0x00000000
+#define UART_RV_LCR_H 0x00000000
+#define UART_RV_PeriphID6 0x00000000
+#define UART_RV_DR 0x00000000
+#define UART_RV_RSR 0x00000000
+#define UART_RV_ECR 0x00000000
+#define UART_RV_PeriphID5 0x00000000
+#define UART_RV_RIS 0x00000000
+#define UART_RV_FBRD 0x00000000
+#define UART_RV_IM 0x00000000
+#define UART_RV_MIS 0x00000000
+#define UART_RV_ICR 0x00000000
+#define UART_RV_PeriphID1 0x00000000
+#define UART_RV_PeriphID7 0x00000000
+#define UART_RV_IBRD 0x00000000
+
+#endif
+
+#endif // __HW_UART_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_udma.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_udma.h
new file mode 100644
index 00000000..6f6270b1
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_udma.h
@@ -0,0 +1,331 @@
+//*****************************************************************************
+//
+// hw_udma.h - Macros for use in accessing the UDMA registers.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UDMA_H__
+#define __HW_UDMA_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access register
+// addresses.
+//
+//*****************************************************************************
+#define UDMA_STAT 0x400FF000 // DMA Status
+#define UDMA_CFG 0x400FF004 // DMA Configuration
+#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer
+#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control
+ // Base Pointer
+#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request
+ // Status
+#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request
+#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set
+#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear
+#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set
+#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear
+#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set
+#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear
+#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate
+ // Set
+#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate
+ // Clear
+#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
+#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
+#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
+#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP \
+ 0x00000020 // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP \
+ 0x00000030 // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT \
+ 0x00000040 // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT \
+ 0x00000050 // Writing destination data
+#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to
+ // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
+#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
+#define UDMA_STAT_STATE_DONE 0x00000090 // Done
+#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
+#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
+#define UDMA_STAT_DMACHANS_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
+ // Pointer
+#define UDMA_ALTBASE_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel
+ // assignment
+#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel
+ // assignment
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
+//
+//*****************************************************************************
+#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
+ // Pointer
+#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
+ // End Pointer
+#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
+#define UDMA_SRCENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
+#define UDMA_DSTENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
+#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
+#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
+#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
+#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
+#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
+#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
+#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
+#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
+#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
+#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
+#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
+#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
+#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
+#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
+#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
+#define UDMA_CHCTL_XFERMODE_STOP \
+ 0x00000000 // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC \
+ 0x00000001 // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO \
+ 0x00000002 // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG \
+ 0x00000003 // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG \
+ 0x00000004 // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA \
+ 0x00000005 // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG \
+ 0x00000006 // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA \
+ 0x00000007 // Alternate Peripheral
+ // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S 4
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Micro Direct Memory Access
+// register addresses.
+//
+//*****************************************************************************
+#define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UDMA_ENASET
+// register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UDMA_CHALT
+// register.
+//
+//*****************************************************************************
+#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment
+ // Select
+
+#endif
+
+#endif // __HW_UDMA_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_usb.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_usb.h
new file mode 100644
index 00000000..0dda4a4c
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_usb.h
@@ -0,0 +1,4620 @@
+//*****************************************************************************
+//
+// hw_usb.h - Macros for use in accessing the USB registers.
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_USB_H__
+#define __HW_USB_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Univeral Serial Bus register offsets.
+//
+//*****************************************************************************
+#define USB_O_FADDR 0x00000000 // USB Device Functional Address
+#define USB_O_POWER 0x00000001 // USB Power
+#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status
+#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status
+#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable
+#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable
+#define USB_O_IS 0x0000000A // USB General Interrupt Status
+#define USB_O_IE 0x0000000B // USB Interrupt Enable
+#define USB_O_FRAME 0x0000000C // USB Frame Value
+#define USB_O_EPIDX 0x0000000E // USB Endpoint Index
+#define USB_O_TEST 0x0000000F // USB Test Mode
+#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0
+#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1
+#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2
+#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3
+#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4
+#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5
+#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6
+#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7
+#define USB_O_FIFO8 0x00000040 // USB FIFO Endpoint 8
+#define USB_O_FIFO9 0x00000044 // USB FIFO Endpoint 9
+#define USB_O_FIFO10 0x00000048 // USB FIFO Endpoint 10
+#define USB_O_FIFO11 0x0000004C // USB FIFO Endpoint 11
+#define USB_O_FIFO12 0x00000050 // USB FIFO Endpoint 12
+#define USB_O_FIFO13 0x00000054 // USB FIFO Endpoint 13
+#define USB_O_FIFO14 0x00000058 // USB FIFO Endpoint 14
+#define USB_O_FIFO15 0x0000005C // USB FIFO Endpoint 15
+#define USB_O_DEVCTL 0x00000060 // USB Device Control
+#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing
+#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing
+#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address
+#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address
+#define USB_O_CONTIM 0x0000007A // USB Connect Timing
+#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing
+#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction
+ // to End of Frame Timing
+#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction
+ // to End of Frame Timing
+#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address
+ // Endpoint 0
+#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address
+ // Endpoint 0
+#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0
+#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address
+ // Endpoint 1
+#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address
+ // Endpoint 1
+#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1
+#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address
+ // Endpoint 1
+#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint
+ // 1
+#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1
+#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address
+ // Endpoint 2
+#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address
+ // Endpoint 2
+#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2
+#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address
+ // Endpoint 2
+#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint
+ // 2
+#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2
+#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address
+ // Endpoint 3
+#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address
+ // Endpoint 3
+#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3
+#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address
+ // Endpoint 3
+#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint
+ // 3
+#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3
+#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address
+ // Endpoint 4
+#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address
+ // Endpoint 4
+#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4
+#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address
+ // Endpoint 4
+#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint
+ // 4
+#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4
+#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address
+ // Endpoint 5
+#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address
+ // Endpoint 5
+#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5
+#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address
+ // Endpoint 5
+#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint
+ // 5
+#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5
+#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address
+ // Endpoint 6
+#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address
+ // Endpoint 6
+#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6
+#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address
+ // Endpoint 6
+#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint
+ // 6
+#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6
+#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address
+ // Endpoint 7
+#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address
+ // Endpoint 7
+#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7
+#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address
+ // Endpoint 7
+#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint
+ // 7
+#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7
+#define USB_O_TXFUNCADDR8 0x000000C0 // USB Transmit Functional Address
+ // Endpoint 8
+#define USB_O_TXHUBADDR8 0x000000C2 // USB Transmit Hub Address
+ // Endpoint 8
+#define USB_O_TXHUBPORT8 0x000000C3 // USB Transmit Hub Port Endpoint 8
+#define USB_O_RXFUNCADDR8 0x000000C4 // USB Receive Functional Address
+ // Endpoint 8
+#define USB_O_RXHUBADDR8 0x000000C6 // USB Receive Hub Address Endpoint
+ // 8
+#define USB_O_RXHUBPORT8 0x000000C7 // USB Receive Hub Port Endpoint 8
+#define USB_O_TXFUNCADDR9 0x000000C8 // USB Transmit Functional Address
+ // Endpoint 9
+#define USB_O_TXHUBADDR9 0x000000CA // USB Transmit Hub Address
+ // Endpoint 9
+#define USB_O_TXHUBPORT9 0x000000CB // USB Transmit Hub Port Endpoint 9
+#define USB_O_RXFUNCADDR9 0x000000CC // USB Receive Functional Address
+ // Endpoint 9
+#define USB_O_RXHUBADDR9 0x000000CE // USB Receive Hub Address Endpoint
+ // 9
+#define USB_O_RXHUBPORT9 0x000000CF // USB Receive Hub Port Endpoint 9
+#define USB_O_TXFUNCADDR10 0x000000D0 // USB Transmit Functional Address
+ // Endpoint 10
+#define USB_O_TXHUBADDR10 0x000000D2 // USB Transmit Hub Address
+ // Endpoint 10
+#define USB_O_TXHUBPORT10 0x000000D3 // USB Transmit Hub Port Endpoint
+ // 10
+#define USB_O_RXFUNCADDR10 0x000000D4 // USB Receive Functional Address
+ // Endpoint 10
+#define USB_O_RXHUBADDR10 0x000000D6 // USB Receive Hub Address Endpoint
+ // 10
+#define USB_O_RXHUBPORT10 0x000000D7 // USB Receive Hub Port Endpoint 10
+#define USB_O_TXFUNCADDR11 0x000000D8 // USB Transmit Functional Address
+ // Endpoint 11
+#define USB_O_TXHUBADDR11 0x000000DA // USB Transmit Hub Address
+ // Endpoint 11
+#define USB_O_TXHUBPORT11 0x000000DB // USB Transmit Hub Port Endpoint
+ // 11
+#define USB_O_RXFUNCADDR11 0x000000DC // USB Receive Functional Address
+ // Endpoint 11
+#define USB_O_RXHUBADDR11 0x000000DE // USB Receive Hub Address Endpoint
+ // 11
+#define USB_O_RXHUBPORT11 0x000000DF // USB Receive Hub Port Endpoint 11
+#define USB_O_TXFUNCADDR12 0x000000E0 // USB Transmit Functional Address
+ // Endpoint 12
+#define USB_O_TXHUBADDR12 0x000000E2 // USB Transmit Hub Address
+ // Endpoint 12
+#define USB_O_TXHUBPORT12 0x000000E3 // USB Transmit Hub Port Endpoint
+ // 12
+#define USB_O_RXFUNCADDR12 0x000000E4 // USB Receive Functional Address
+ // Endpoint 12
+#define USB_O_RXHUBADDR12 0x000000E6 // USB Receive Hub Address Endpoint
+ // 12
+#define USB_O_RXHUBPORT12 0x000000E7 // USB Receive Hub Port Endpoint 12
+#define USB_O_TXFUNCADDR13 0x000000E8 // USB Transmit Functional Address
+ // Endpoint 13
+#define USB_O_TXHUBADDR13 0x000000EA // USB Transmit Hub Address
+ // Endpoint 13
+#define USB_O_TXHUBPORT13 0x000000EB // USB Transmit Hub Port Endpoint
+ // 13
+#define USB_O_RXFUNCADDR13 0x000000EC // USB Receive Functional Address
+ // Endpoint 13
+#define USB_O_RXHUBADDR13 0x000000EE // USB Receive Hub Address Endpoint
+ // 13
+#define USB_O_RXHUBPORT13 0x000000EF // USB Receive Hub Port Endpoint 13
+#define USB_O_TXFUNCADDR14 0x000000F0 // USB Transmit Functional Address
+ // Endpoint 14
+#define USB_O_TXHUBADDR14 0x000000F2 // USB Transmit Hub Address
+ // Endpoint 14
+#define USB_O_TXHUBPORT14 0x000000F3 // USB Transmit Hub Port Endpoint
+ // 14
+#define USB_O_RXFUNCADDR14 0x000000F4 // USB Receive Functional Address
+ // Endpoint 14
+#define USB_O_RXHUBADDR14 0x000000F6 // USB Receive Hub Address Endpoint
+ // 14
+#define USB_O_RXHUBPORT14 0x000000F7 // USB Receive Hub Port Endpoint 14
+#define USB_O_TXFUNCADDR15 0x000000F8 // USB Transmit Functional Address
+ // Endpoint 15
+#define USB_O_TXHUBADDR15 0x000000FA // USB Transmit Hub Address
+ // Endpoint 15
+#define USB_O_TXHUBPORT15 0x000000FB // USB Transmit Hub Port Endpoint
+ // 15
+#define USB_O_RXFUNCADDR15 0x000000FC // USB Receive Functional Address
+ // Endpoint 15
+#define USB_O_RXHUBADDR15 0x000000FE // USB Receive Hub Address Endpoint
+ // 15
+#define USB_O_RXHUBPORT15 0x000000FF // USB Receive Hub Port Endpoint 15
+#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint
+ // 0 Low
+#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint
+ // 0 High
+#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint
+ // 0
+#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0
+#define USB_O_NAKLMT 0x0000010B // USB NAK Limit
+#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data
+ // Endpoint 1
+#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status
+ // Endpoint 1 Low
+#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status
+ // Endpoint 1 High
+#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data
+ // Endpoint 1
+#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status
+ // Endpoint 1 Low
+#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status
+ // Endpoint 1 High
+#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint
+ // 1
+#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type
+ // Endpoint 1
+#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval
+ // Endpoint 1
+#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type
+ // Endpoint 1
+#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling
+ // Interval Endpoint 1
+#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data
+ // Endpoint 2
+#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status
+ // Endpoint 2 Low
+#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status
+ // Endpoint 2 High
+#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data
+ // Endpoint 2
+#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status
+ // Endpoint 2 Low
+#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status
+ // Endpoint 2 High
+#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint
+ // 2
+#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type
+ // Endpoint 2
+#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval
+ // Endpoint 2
+#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type
+ // Endpoint 2
+#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling
+ // Interval Endpoint 2
+#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data
+ // Endpoint 3
+#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status
+ // Endpoint 3 Low
+#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status
+ // Endpoint 3 High
+#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data
+ // Endpoint 3
+#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status
+ // Endpoint 3 Low
+#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status
+ // Endpoint 3 High
+#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint
+ // 3
+#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type
+ // Endpoint 3
+#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval
+ // Endpoint 3
+#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type
+ // Endpoint 3
+#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling
+ // Interval Endpoint 3
+#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data
+ // Endpoint 4
+#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status
+ // Endpoint 4 Low
+#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status
+ // Endpoint 4 High
+#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data
+ // Endpoint 4
+#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status
+ // Endpoint 4 Low
+#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status
+ // Endpoint 4 High
+#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint
+ // 4
+#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type
+ // Endpoint 4
+#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval
+ // Endpoint 4
+#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type
+ // Endpoint 4
+#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling
+ // Interval Endpoint 4
+#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data
+ // Endpoint 5
+#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status
+ // Endpoint 5 Low
+#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status
+ // Endpoint 5 High
+#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data
+ // Endpoint 5
+#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status
+ // Endpoint 5 Low
+#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status
+ // Endpoint 5 High
+#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint
+ // 5
+#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type
+ // Endpoint 5
+#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval
+ // Endpoint 5
+#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type
+ // Endpoint 5
+#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling
+ // Interval Endpoint 5
+#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data
+ // Endpoint 6
+#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status
+ // Endpoint 6 Low
+#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status
+ // Endpoint 6 High
+#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data
+ // Endpoint 6
+#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status
+ // Endpoint 6 Low
+#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status
+ // Endpoint 6 High
+#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint
+ // 6
+#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type
+ // Endpoint 6
+#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval
+ // Endpoint 6
+#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type
+ // Endpoint 6
+#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling
+ // Interval Endpoint 6
+#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data
+ // Endpoint 7
+#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status
+ // Endpoint 7 Low
+#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status
+ // Endpoint 7 High
+#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data
+ // Endpoint 7
+#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status
+ // Endpoint 7 Low
+#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status
+ // Endpoint 7 High
+#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint
+ // 7
+#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type
+ // Endpoint 7
+#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval
+ // Endpoint 7
+#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type
+ // Endpoint 7
+#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling
+ // Interval Endpoint 7
+#define USB_O_TXMAXP8 0x00000180 // USB Maximum Transmit Data
+ // Endpoint 8
+#define USB_O_TXCSRL8 0x00000182 // USB Transmit Control and Status
+ // Endpoint 8 Low
+#define USB_O_TXCSRH8 0x00000183 // USB Transmit Control and Status
+ // Endpoint 8 High
+#define USB_O_RXMAXP8 0x00000184 // USB Maximum Receive Data
+ // Endpoint 8
+#define USB_O_RXCSRL8 0x00000186 // USB Receive Control and Status
+ // Endpoint 8 Low
+#define USB_O_RXCSRH8 0x00000187 // USB Receive Control and Status
+ // Endpoint 8 High
+#define USB_O_RXCOUNT8 0x00000188 // USB Receive Byte Count Endpoint
+ // 8
+#define USB_O_TXTYPE8 0x0000018A // USB Host Transmit Configure Type
+ // Endpoint 8
+#define USB_O_TXINTERVAL8 0x0000018B // USB Host Transmit Interval
+ // Endpoint 8
+#define USB_O_RXTYPE8 0x0000018C // USB Host Configure Receive Type
+ // Endpoint 8
+#define USB_O_RXINTERVAL8 0x0000018D // USB Host Receive Polling
+ // Interval Endpoint 8
+#define USB_O_TXMAXP9 0x00000190 // USB Maximum Transmit Data
+ // Endpoint 9
+#define USB_O_TXCSRL9 0x00000192 // USB Transmit Control and Status
+ // Endpoint 9 Low
+#define USB_O_TXCSRH9 0x00000193 // USB Transmit Control and Status
+ // Endpoint 9 High
+#define USB_O_RXMAXP9 0x00000194 // USB Maximum Receive Data
+ // Endpoint 9
+#define USB_O_RXCSRL9 0x00000196 // USB Receive Control and Status
+ // Endpoint 9 Low
+#define USB_O_RXCSRH9 0x00000197 // USB Receive Control and Status
+ // Endpoint 9 High
+#define USB_O_RXCOUNT9 0x00000198 // USB Receive Byte Count Endpoint
+ // 9
+#define USB_O_TXTYPE9 0x0000019A // USB Host Transmit Configure Type
+ // Endpoint 9
+#define USB_O_TXINTERVAL9 0x0000019B // USB Host Transmit Interval
+ // Endpoint 9
+#define USB_O_RXTYPE9 0x0000019C // USB Host Configure Receive Type
+ // Endpoint 9
+#define USB_O_RXINTERVAL9 0x0000019D // USB Host Receive Polling
+ // Interval Endpoint 9
+#define USB_O_TXMAXP10 0x000001A0 // USB Maximum Transmit Data
+ // Endpoint 10
+#define USB_O_TXCSRL10 0x000001A2 // USB Transmit Control and Status
+ // Endpoint 10 Low
+#define USB_O_TXCSRH10 0x000001A3 // USB Transmit Control and Status
+ // Endpoint 10 High
+#define USB_O_RXMAXP10 0x000001A4 // USB Maximum Receive Data
+ // Endpoint 10
+#define USB_O_RXCSRL10 0x000001A6 // USB Receive Control and Status
+ // Endpoint 10 Low
+#define USB_O_RXCSRH10 0x000001A7 // USB Receive Control and Status
+ // Endpoint 10 High
+#define USB_O_RXCOUNT10 0x000001A8 // USB Receive Byte Count Endpoint
+ // 10
+#define USB_O_TXTYPE10 0x000001AA // USB Host Transmit Configure Type
+ // Endpoint 10
+#define USB_O_TXINTERVAL10 0x000001AB // USB Host Transmit Interval
+ // Endpoint 10
+#define USB_O_RXTYPE10 0x000001AC // USB Host Configure Receive Type
+ // Endpoint 10
+#define USB_O_RXINTERVAL10 0x000001AD // USB Host Receive Polling
+ // Interval Endpoint 10
+#define USB_O_TXMAXP11 0x000001B0 // USB Maximum Transmit Data
+ // Endpoint 11
+#define USB_O_TXCSRL11 0x000001B2 // USB Transmit Control and Status
+ // Endpoint 11 Low
+#define USB_O_TXCSRH11 0x000001B3 // USB Transmit Control and Status
+ // Endpoint 11 High
+#define USB_O_RXMAXP11 0x000001B4 // USB Maximum Receive Data
+ // Endpoint 11
+#define USB_O_RXCSRL11 0x000001B6 // USB Receive Control and Status
+ // Endpoint 11 Low
+#define USB_O_RXCSRH11 0x000001B7 // USB Receive Control and Status
+ // Endpoint 11 High
+#define USB_O_RXCOUNT11 0x000001B8 // USB Receive Byte Count Endpoint
+ // 11
+#define USB_O_TXTYPE11 0x000001BA // USB Host Transmit Configure Type
+ // Endpoint 11
+#define USB_O_TXINTERVAL11 0x000001BB // USB Host Transmit Interval
+ // Endpoint 11
+#define USB_O_RXTYPE11 0x000001BC // USB Host Configure Receive Type
+ // Endpoint 11
+#define USB_O_RXINTERVAL11 0x000001BD // USB Host Receive Polling
+ // Interval Endpoint 11
+#define USB_O_TXMAXP12 0x000001C0 // USB Maximum Transmit Data
+ // Endpoint 12
+#define USB_O_TXCSRL12 0x000001C2 // USB Transmit Control and Status
+ // Endpoint 12 Low
+#define USB_O_TXCSRH12 0x000001C3 // USB Transmit Control and Status
+ // Endpoint 12 High
+#define USB_O_RXMAXP12 0x000001C4 // USB Maximum Receive Data
+ // Endpoint 12
+#define USB_O_RXCSRL12 0x000001C6 // USB Receive Control and Status
+ // Endpoint 12 Low
+#define USB_O_RXCSRH12 0x000001C7 // USB Receive Control and Status
+ // Endpoint 12 High
+#define USB_O_RXCOUNT12 0x000001C8 // USB Receive Byte Count Endpoint
+ // 12
+#define USB_O_TXTYPE12 0x000001CA // USB Host Transmit Configure Type
+ // Endpoint 12
+#define USB_O_TXINTERVAL12 0x000001CB // USB Host Transmit Interval
+ // Endpoint 12
+#define USB_O_RXTYPE12 0x000001CC // USB Host Configure Receive Type
+ // Endpoint 12
+#define USB_O_RXINTERVAL12 0x000001CD // USB Host Receive Polling
+ // Interval Endpoint 12
+#define USB_O_TXMAXP13 0x000001D0 // USB Maximum Transmit Data
+ // Endpoint 13
+#define USB_O_TXCSRL13 0x000001D2 // USB Transmit Control and Status
+ // Endpoint 13 Low
+#define USB_O_TXCSRH13 0x000001D3 // USB Transmit Control and Status
+ // Endpoint 13 High
+#define USB_O_RXMAXP13 0x000001D4 // USB Maximum Receive Data
+ // Endpoint 13
+#define USB_O_RXCSRL13 0x000001D6 // USB Receive Control and Status
+ // Endpoint 13 Low
+#define USB_O_RXCSRH13 0x000001D7 // USB Receive Control and Status
+ // Endpoint 13 High
+#define USB_O_RXCOUNT13 0x000001D8 // USB Receive Byte Count Endpoint
+ // 13
+#define USB_O_TXTYPE13 0x000001DA // USB Host Transmit Configure Type
+ // Endpoint 13
+#define USB_O_TXINTERVAL13 0x000001DB // USB Host Transmit Interval
+ // Endpoint 13
+#define USB_O_RXTYPE13 0x000001DC // USB Host Configure Receive Type
+ // Endpoint 13
+#define USB_O_RXINTERVAL13 0x000001DD // USB Host Receive Polling
+ // Interval Endpoint 13
+#define USB_O_TXMAXP14 0x000001E0 // USB Maximum Transmit Data
+ // Endpoint 14
+#define USB_O_TXCSRL14 0x000001E2 // USB Transmit Control and Status
+ // Endpoint 14 Low
+#define USB_O_TXCSRH14 0x000001E3 // USB Transmit Control and Status
+ // Endpoint 14 High
+#define USB_O_RXMAXP14 0x000001E4 // USB Maximum Receive Data
+ // Endpoint 14
+#define USB_O_RXCSRL14 0x000001E6 // USB Receive Control and Status
+ // Endpoint 14 Low
+#define USB_O_RXCSRH14 0x000001E7 // USB Receive Control and Status
+ // Endpoint 14 High
+#define USB_O_RXCOUNT14 0x000001E8 // USB Receive Byte Count Endpoint
+ // 14
+#define USB_O_TXTYPE14 0x000001EA // USB Host Transmit Configure Type
+ // Endpoint 14
+#define USB_O_TXINTERVAL14 0x000001EB // USB Host Transmit Interval
+ // Endpoint 14
+#define USB_O_RXTYPE14 0x000001EC // USB Host Configure Receive Type
+ // Endpoint 14
+#define USB_O_RXINTERVAL14 0x000001ED // USB Host Receive Polling
+ // Interval Endpoint 14
+#define USB_O_TXMAXP15 0x000001F0 // USB Maximum Transmit Data
+ // Endpoint 15
+#define USB_O_TXCSRL15 0x000001F2 // USB Transmit Control and Status
+ // Endpoint 15 Low
+#define USB_O_TXCSRH15 0x000001F3 // USB Transmit Control and Status
+ // Endpoint 15 High
+#define USB_O_RXMAXP15 0x000001F4 // USB Maximum Receive Data
+ // Endpoint 15
+#define USB_O_RXCSRL15 0x000001F6 // USB Receive Control and Status
+ // Endpoint 15 Low
+#define USB_O_RXCSRH15 0x000001F7 // USB Receive Control and Status
+ // Endpoint 15 High
+#define USB_O_RXCOUNT15 0x000001F8 // USB Receive Byte Count Endpoint
+ // 15
+#define USB_O_TXTYPE15 0x000001FA // USB Host Transmit Configure Type
+ // Endpoint 15
+#define USB_O_TXINTERVAL15 0x000001FB // USB Host Transmit Interval
+ // Endpoint 15
+#define USB_O_RXTYPE15 0x000001FC // USB Host Configure Receive Type
+ // Endpoint 15
+#define USB_O_RXINTERVAL15 0x000001FD // USB Host Receive Polling
+ // Interval Endpoint 15
+#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in
+ // Block Transfer Endpoint 1
+#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in
+ // Block Transfer Endpoint 2
+#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in
+ // Block Transfer Endpoint 3
+#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in
+ // Block Transfer Endpoint 4
+#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in
+ // Block Transfer Endpoint 5
+#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in
+ // Block Transfer Endpoint 6
+#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in
+ // Block Transfer Endpoint 7
+#define USB_O_RQPKTCOUNT8 0x00000320 // USB Request Packet Count in
+ // Block Transfer Endpoint 8
+#define USB_O_RQPKTCOUNT9 0x00000324 // USB Request Packet Count in
+ // Block Transfer Endpoint 9
+#define USB_O_RQPKTCOUNT10 0x00000328 // USB Request Packet Count in
+ // Block Transfer Endpoint 10
+#define USB_O_RQPKTCOUNT11 0x0000032C // USB Request Packet Count in
+ // Block Transfer Endpoint 11
+#define USB_O_RQPKTCOUNT12 0x00000330 // USB Request Packet Count in
+ // Block Transfer Endpoint 12
+#define USB_O_RQPKTCOUNT13 0x00000334 // USB Request Packet Count in
+ // Block Transfer Endpoint 13
+#define USB_O_RQPKTCOUNT14 0x00000338 // USB Request Packet Count in
+ // Block Transfer Endpoint 14
+#define USB_O_RQPKTCOUNT15 0x0000033C // USB Request Packet Count in
+ // Block Transfer Endpoint 15
+#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer
+ // Disable
+#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet
+ // Buffer Disable
+#define USB_O_EPC 0x00000400 // USB External Power Control
+#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw
+ // Interrupt Status
+#define USB_O_EPCIM 0x00000408 // USB External Power Control
+ // Interrupt Mask
+#define USB_O_EPCISC 0x0000040C // USB External Power Control
+ // Interrupt Status and Clear
+#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt
+ // Status
+#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask
+#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt
+ // Status and Clear
+#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and
+ // Status
+#define USB_O_VDC 0x00000430 // USB VBUS Droop Control
+#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw
+ // Interrupt Status
+#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt
+ // Mask
+#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt
+ // Status and Clear
+#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw
+ // Interrupt Status
+#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt
+ // Mask
+#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt
+ // Status and Clear
+#define USB_O_DMASEL 0x00000450 // USB DMA Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M 0x0000007F // Function Address
+#define USB_FADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP 0x00000080 // Isochronous Update
+#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect
+#define USB_POWER_RESET 0x00000008 // RESET Signaling
+#define USB_POWER_RESUME 0x00000004 // RESUME Signaling
+#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode
+#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP15 0x00008000 // TX Endpoint 15 Interrupt
+#define USB_TXIS_EP14 0x00004000 // TX Endpoint 14 Interrupt
+#define USB_TXIS_EP13 0x00002000 // TX Endpoint 13 Interrupt
+#define USB_TXIS_EP12 0x00001000 // TX Endpoint 12 Interrupt
+#define USB_TXIS_EP11 0x00000800 // TX Endpoint 11 Interrupt
+#define USB_TXIS_EP10 0x00000400 // TX Endpoint 10 Interrupt
+#define USB_TXIS_EP9 0x00000200 // TX Endpoint 9 Interrupt
+#define USB_TXIS_EP8 0x00000100 // TX Endpoint 8 Interrupt
+#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP15 0x00008000 // RX Endpoint 15 Interrupt
+#define USB_RXIS_EP14 0x00004000 // RX Endpoint 14 Interrupt
+#define USB_RXIS_EP13 0x00002000 // RX Endpoint 13 Interrupt
+#define USB_RXIS_EP12 0x00001000 // RX Endpoint 12 Interrupt
+#define USB_RXIS_EP11 0x00000800 // RX Endpoint 11 Interrupt
+#define USB_RXIS_EP10 0x00000400 // RX Endpoint 10 Interrupt
+#define USB_RXIS_EP9 0x00000200 // RX Endpoint 9 Interrupt
+#define USB_RXIS_EP8 0x00000100 // RX Endpoint 8 Interrupt
+#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP15 0x00008000 // TX Endpoint 15 Interrupt Enable
+#define USB_TXIE_EP14 0x00004000 // TX Endpoint 14 Interrupt Enable
+#define USB_TXIE_EP13 0x00002000 // TX Endpoint 13 Interrupt Enable
+#define USB_TXIE_EP12 0x00001000 // TX Endpoint 12 Interrupt Enable
+#define USB_TXIE_EP11 0x00000800 // TX Endpoint 11 Interrupt Enable
+#define USB_TXIE_EP10 0x00000400 // TX Endpoint 10 Interrupt Enable
+#define USB_TXIE_EP9 0x00000200 // TX Endpoint 9 Interrupt Enable
+#define USB_TXIE_EP8 0x00000100 // TX Endpoint 8 Interrupt Enable
+#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable
+#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP15 0x00008000 // RX Endpoint 15 Interrupt Enable
+#define USB_RXIE_EP14 0x00004000 // RX Endpoint 14 Interrupt Enable
+#define USB_RXIE_EP13 0x00002000 // RX Endpoint 13 Interrupt Enable
+#define USB_RXIE_EP12 0x00001000 // RX Endpoint 12 Interrupt Enable
+#define USB_RXIE_EP11 0x00000800 // RX Endpoint 11 Interrupt Enable
+#define USB_RXIE_EP10 0x00000400 // RX Endpoint 10 Interrupt Enable
+#define USB_RXIE_EP9 0x00000200 // RX Endpoint 9 Interrupt Enable
+#define USB_RXIE_EP8 0x00000100 // RX Endpoint 8 Interrupt Enable
+#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR 0x00000080 // VBUS Error
+#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST
+#define USB_IS_DISCON 0x00000020 // Session Disconnect
+#define USB_IS_CONN 0x00000010 // Session Connect
+#define USB_IS_SOF 0x00000008 // Start of Frame
+#define USB_IS_BABBLE 0x00000004 // Babble Detected
+#define USB_IS_RESET 0x00000004 // RESET Signaling Detected
+#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected
+#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt
+#define USB_IE_SESREQ 0x00000040 // Enable Session Request
+#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt
+#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt
+#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt
+#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt
+#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt
+#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M 0x000007FF // Frame Number
+#define USB_FRAME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index
+#define USB_EPIDX_EPIDX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH 0x00000080 // Force Host Mode
+#define USB_TEST_FIFOACC 0x00000040 // FIFO Access
+#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO0_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO1_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO2_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO3_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO4_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO5_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO6_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO7_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO8 register.
+//
+//*****************************************************************************
+#define USB_FIFO8_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO8_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO9 register.
+//
+//*****************************************************************************
+#define USB_FIFO9_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO9_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO10 register.
+//
+//*****************************************************************************
+#define USB_FIFO10_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO10_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO11 register.
+//
+//*****************************************************************************
+#define USB_FIFO11_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO11_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO12 register.
+//
+//*****************************************************************************
+#define USB_FIFO12_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO12_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO13 register.
+//
+//*****************************************************************************
+#define USB_FIFO13_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO13_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO14 register.
+//
+//*****************************************************************************
+#define USB_FIFO14_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO14_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO15 register.
+//
+//*****************************************************************************
+#define USB_FIFO15_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO15_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV 0x00000080 // Device Mode
+#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level
+#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid
+#define USB_DEVCTL_HOST 0x00000004 // Host Mode
+#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request
+#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
+#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
+#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait
+#define USB_CONTIM_WTID_M 0x0000000F // Wait ID
+#define USB_CONTIM_WTCON_S 4
+#define USB_CONTIM_WTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length
+#define USB_VPLEN_VPLEN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap
+#define USB_FSEOF_FSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap
+#define USB_LSEOF_LSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT0_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR8_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR8_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR8_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT8
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT8_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT8_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR8_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR8_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR8_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT8
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT8_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT8_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR9_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR9_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR9_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT9
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT9_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT9_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR9_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR9_MULTTRAN 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR9_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT9
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT9_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT9_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR10_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR10_MULTTRAN \
+ 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR10_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT10
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT10_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT10_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR10_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR10_MULTTRAN \
+ 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR10_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT10
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT10_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT10_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR11_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR11_MULTTRAN \
+ 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR11_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT11
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT11_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT11_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR11_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR11_MULTTRAN \
+ 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR11_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT11
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT11_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT11_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR12_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR12_MULTTRAN \
+ 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR12_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT12
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT12_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT12_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR12_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR12_MULTTRAN \
+ 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR12_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT12
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT12_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT12_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR13_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR13_MULTTRAN \
+ 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR13_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT13
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT13_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT13_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR13_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR13_MULTTRAN \
+ 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR13_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT13
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT13_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT13_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR14_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR14_MULTTRAN \
+ 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR14_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT14
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT14_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT14_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR14_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR14_MULTTRAN \
+ 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR14_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT14
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT14_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT14_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR15_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR15_MULTTRAN \
+ 0x00000080 // Multiple Translators
+#define USB_TXHUBADDR15_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT15
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT15_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT15_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR15_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR15_MULTTRAN \
+ 0x00000080 // Multiple Translators
+#define USB_RXHUBADDR15_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT15
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT15_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT15_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout
+#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear
+#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet
+#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear
+#define USB_CSRL0_REQPKT 0x00000020 // Request Packet
+#define USB_CSRL0_STALL 0x00000020 // Send Stall
+#define USB_CSRL0_SETEND 0x00000010 // Setup End
+#define USB_CSRL0_ERROR 0x00000010 // Error
+#define USB_CSRL0_DATAEND 0x00000008 // Data End
+#define USB_CSRL0_SETUP 0x00000008 // Setup Packet
+#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled
+#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready
+#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_CSRH0_DT 0x00000002 // Data Toggle
+#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count
+#define USB_COUNT0_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TYPE0_SPEED_FULL 0x00000080 // Full
+#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit
+#define USB_NAKLMT_NAKLMT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL1_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL1_ERROR 0x00000004 // Error
+#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH1_MODE 0x00000020 // Mode
+#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH1_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL1_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL1_OVER 0x00000004 // Overrun
+#define USB_RXCSRL1_ERROR 0x00000004 // Error
+#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH1_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT1_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL1_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL2_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL2_ERROR 0x00000004 // Error
+#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH2_MODE 0x00000020 // Mode
+#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH2_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL2_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL2_ERROR 0x00000004 // Error
+#define USB_RXCSRL2_OVER 0x00000004 // Overrun
+#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH2_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT2_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL2_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL2_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL2_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL2_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL3_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL3_ERROR 0x00000004 // Error
+#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH3_MODE 0x00000020 // Mode
+#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH3_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL3_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL3_ERROR 0x00000004 // Error
+#define USB_RXCSRL3_OVER 0x00000004 // Overrun
+#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH3_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT3_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL4_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL4_ERROR 0x00000004 // Error
+#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH4_MODE 0x00000020 // Mode
+#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH4_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL4_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL4_OVER 0x00000004 // Overrun
+#define USB_RXCSRL4_ERROR 0x00000004 // Error
+#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH4_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL5_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL5_ERROR 0x00000004 // Error
+#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH5_MODE 0x00000020 // Mode
+#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH5_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL5_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL5_ERROR 0x00000004 // Error
+#define USB_RXCSRL5_OVER 0x00000004 // Overrun
+#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH5_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL5_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL5_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL5_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL5_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL6_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL6_ERROR 0x00000004 // Error
+#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH6_MODE 0x00000020 // Mode
+#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH6_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL6_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL6_ERROR 0x00000004 // Error
+#define USB_RXCSRL6_OVER 0x00000004 // Overrun
+#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH6_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL6_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL6_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL6_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL6_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL7_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL7_ERROR 0x00000004 // Error
+#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH7_MODE 0x00000020 // Mode
+#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH7_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL7_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL7_ERROR 0x00000004 // Error
+#define USB_RXCSRL7_OVER 0x00000004 // Overrun
+#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH7_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP8 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP8_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL8 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL8_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL8_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL8_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL8_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL8_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL8_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL8_ERROR 0x00000004 // Error
+#define USB_TXCSRL8_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL8_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL8_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH8 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH8_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH8_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH8_MODE 0x00000020 // Mode
+#define USB_TXCSRH8_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH8_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH8_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH8_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH8_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP8 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP8_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL8 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL8_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL8_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL8_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL8_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL8_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL8_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL8_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL8_OVER 0x00000004 // Overrun
+#define USB_RXCSRL8_ERROR 0x00000004 // Error
+#define USB_RXCSRL8_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL8_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH8 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH8_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH8_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH8_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH8_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH8_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH8_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH8_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH8_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH8_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT8 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT8_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT8_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE8 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE8_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE8_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE8_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE8_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE8_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE8_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE8_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE8_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE8_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE8_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE8_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL8
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL8_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL8_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL8_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL8_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE8 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE8_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE8_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE8_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE8_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE8_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE8_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE8_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE8_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE8_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE8_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE8_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL8
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL8_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL8_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL8_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL8_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP9 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP9_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL9 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL9_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL9_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL9_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL9_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL9_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL9_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL9_ERROR 0x00000004 // Error
+#define USB_TXCSRL9_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL9_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL9_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH9 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH9_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH9_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH9_MODE 0x00000020 // Mode
+#define USB_TXCSRH9_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH9_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH9_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH9_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH9_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP9 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP9_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL9 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL9_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL9_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL9_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL9_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL9_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL9_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL9_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL9_ERROR 0x00000004 // Error
+#define USB_RXCSRL9_OVER 0x00000004 // Overrun
+#define USB_RXCSRL9_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL9_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH9 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH9_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH9_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH9_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH9_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH9_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH9_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH9_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH9_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH9_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT9 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT9_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT9_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE9 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE9_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE9_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE9_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE9_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE9_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE9_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE9_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE9_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE9_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE9_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE9_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL9
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL9_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL9_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL9_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL9_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE9 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE9_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE9_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE9_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE9_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE9_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE9_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE9_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE9_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE9_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE9_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE9_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL9
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL9_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL9_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL9_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL9_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP10 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP10_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL10 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL10_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL10_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL10_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL10_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL10_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL10_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL10_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL10_ERROR 0x00000004 // Error
+#define USB_TXCSRL10_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL10_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH10 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH10_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH10_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH10_MODE 0x00000020 // Mode
+#define USB_TXCSRH10_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH10_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH10_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH10_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH10_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP10 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP10_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL10 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL10_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL10_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL10_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL10_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL10_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL10_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL10_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL10_OVER 0x00000004 // Overrun
+#define USB_RXCSRL10_ERROR 0x00000004 // Error
+#define USB_RXCSRL10_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL10_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH10 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH10_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH10_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH10_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH10_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH10_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH10_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH10_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH10_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH10_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT10
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT10_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT10_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE10 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE10_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE10_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE10_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE10_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE10_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE10_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE10_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE10_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE10_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE10_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE10_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL10
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL10_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL10_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL10_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL10_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE10 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE10_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE10_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE10_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE10_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE10_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE10_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE10_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE10_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE10_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE10_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE10_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL10
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL10_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL10_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL10_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL10_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP11 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP11_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL11 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL11_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL11_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL11_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL11_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL11_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL11_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL11_ERROR 0x00000004 // Error
+#define USB_TXCSRL11_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL11_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL11_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH11 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH11_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH11_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH11_MODE 0x00000020 // Mode
+#define USB_TXCSRH11_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH11_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH11_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH11_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH11_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP11 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP11_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL11 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL11_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL11_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL11_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL11_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL11_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL11_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL11_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL11_OVER 0x00000004 // Overrun
+#define USB_RXCSRL11_ERROR 0x00000004 // Error
+#define USB_RXCSRL11_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL11_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH11 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH11_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH11_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH11_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH11_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH11_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH11_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH11_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH11_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH11_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT11
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT11_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT11_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE11 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE11_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE11_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE11_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE11_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE11_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE11_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE11_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE11_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE11_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE11_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE11_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL11
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL11_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL11_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL11_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL11_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE11 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE11_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE11_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE11_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE11_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE11_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE11_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE11_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE11_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE11_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE11_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE11_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL11
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL11_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL11_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL11_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL11_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP12 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP12_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL12 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL12_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL12_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL12_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL12_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL12_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL12_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL12_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL12_ERROR 0x00000004 // Error
+#define USB_TXCSRL12_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL12_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH12 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH12_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH12_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH12_MODE 0x00000020 // Mode
+#define USB_TXCSRH12_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH12_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH12_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH12_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH12_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP12 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP12_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL12 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL12_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL12_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL12_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL12_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL12_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL12_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL12_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL12_ERROR 0x00000004 // Error
+#define USB_RXCSRL12_OVER 0x00000004 // Overrun
+#define USB_RXCSRL12_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL12_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH12 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH12_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH12_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH12_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH12_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH12_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH12_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH12_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH12_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH12_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT12
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT12_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT12_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE12 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE12_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE12_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE12_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE12_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE12_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE12_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE12_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE12_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE12_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE12_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE12_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL12
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL12_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL12_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL12_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL12_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE12 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE12_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE12_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE12_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE12_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE12_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE12_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE12_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE12_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE12_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE12_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE12_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL12
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL12_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL12_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL12_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL12_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP13 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP13_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL13 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL13_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL13_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL13_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL13_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL13_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL13_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL13_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL13_ERROR 0x00000004 // Error
+#define USB_TXCSRL13_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL13_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH13 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH13_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH13_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH13_MODE 0x00000020 // Mode
+#define USB_TXCSRH13_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH13_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH13_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH13_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH13_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP13 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP13_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL13 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL13_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL13_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL13_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL13_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL13_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL13_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL13_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL13_OVER 0x00000004 // Overrun
+#define USB_RXCSRL13_ERROR 0x00000004 // Error
+#define USB_RXCSRL13_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL13_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH13 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH13_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH13_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH13_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH13_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH13_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH13_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH13_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH13_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH13_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT13
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT13_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT13_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE13 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE13_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE13_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE13_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE13_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE13_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE13_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE13_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE13_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE13_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE13_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE13_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL13
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL13_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL13_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL13_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL13_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE13 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE13_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE13_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE13_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE13_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE13_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE13_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE13_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE13_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE13_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE13_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE13_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL13
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL13_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL13_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL13_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL13_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP14 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP14_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL14 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL14_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL14_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL14_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL14_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL14_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL14_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL14_ERROR 0x00000004 // Error
+#define USB_TXCSRL14_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL14_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL14_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH14 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH14_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH14_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH14_MODE 0x00000020 // Mode
+#define USB_TXCSRH14_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH14_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH14_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH14_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH14_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP14 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP14_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL14 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL14_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL14_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL14_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL14_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL14_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL14_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL14_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL14_OVER 0x00000004 // Overrun
+#define USB_RXCSRL14_ERROR 0x00000004 // Error
+#define USB_RXCSRL14_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL14_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH14 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH14_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH14_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH14_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH14_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH14_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH14_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH14_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH14_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH14_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT14
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT14_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT14_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE14 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE14_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE14_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE14_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE14_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE14_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE14_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE14_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE14_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE14_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE14_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE14_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL14
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL14_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL14_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL14_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL14_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE14 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE14_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE14_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE14_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE14_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE14_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE14_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE14_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE14_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE14_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE14_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE14_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL14
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL14_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL14_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL14_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL14_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP15 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP15_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL15 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL15_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL15_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL15_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL15_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL15_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL15_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL15_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL15_ERROR 0x00000004 // Error
+#define USB_TXCSRL15_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL15_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH15 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH15_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH15_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH15_MODE 0x00000020 // Mode
+#define USB_TXCSRH15_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH15_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH15_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH15_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH15_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP15 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP15_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL15 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL15_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL15_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL15_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL15_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL15_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL15_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL15_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL15_ERROR 0x00000004 // Error
+#define USB_RXCSRL15_OVER 0x00000004 // Overrun
+#define USB_RXCSRL15_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL15_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH15 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH15_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH15_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH15_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH15_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH15_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH15_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH15_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH15_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH15_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT15
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT15_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT15_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE15 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE15_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE15_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE15_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE15_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE15_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE15_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE15_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE15_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE15_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE15_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE15_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL15
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL15_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL15_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL15_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL15_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE15 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE15_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE15_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE15_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE15_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE15_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE15_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE15_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE15_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE15_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE15_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE15_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL15
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL15_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL15_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL15_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL15_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT2_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT3_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT8_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT9_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT10_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT10_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT11_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT11_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT12_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT12_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT13_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT13_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT14_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT14_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT15_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT15_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP15 0x00008000 // EP15 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP14 0x00004000 // EP14 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP13 0x00002000 // EP13 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP12 0x00001000 // EP12 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP11 0x00000800 // EP11 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP10 0x00000400 // EP10 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP9 0x00000200 // EP9 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP8 0x00000100 // EP8 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
+ // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP15 0x00008000 // EP15 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP14 0x00004000 // EP14 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP13 0x00002000 // EP13 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP12 0x00001000 // EP12 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP11 0x00000800 // EP11 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP10 0x00000400 // EP10 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP9 0x00000200 // EP9 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP8 0x00000100 // EP8 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
+ // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action
+#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged
+#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate
+#define USB_EPC_PFLTACT_LOW 0x00000200 // Low
+#define USB_EPC_PFLTACT_HIGH 0x00000300 // High
+#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense
+#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable
+#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable
+#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable
+ // Configuration
+#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low
+#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode
+#define USB_GPCS_DEVMOD 0x00000001 // Device Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVRIS register.
+//
+//*****************************************************************************
+#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVIM register.
+//
+//*****************************************************************************
+#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVISC register.
+//
+//*****************************************************************************
+#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMASEL register.
+//
+//*****************************************************************************
+#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select
+#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select
+#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select
+#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select
+#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select
+#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select
+#define USB_DMASEL_DMABTX_S 12
+#define USB_DMASEL_DMABRX_S 8
+#define USB_DMASEL_DMAATX_S 4
+#define USB_DMASEL_DMAARX_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// USB_O_TXFIFOADD register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048
+#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024
+#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512
+#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256
+#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128
+#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64
+#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32
+#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16
+#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8
+#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// USB_O_RXFIFOADD register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048
+#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024
+#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512
+#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256
+#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128
+#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64
+#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32
+#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16
+#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8
+#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0
+
+#endif
+
+#endif // __HW_USB_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_watchdog.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_watchdog.h
new file mode 100644
index 00000000..b8aeb7a8
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/hw_watchdog.h
@@ -0,0 +1,175 @@
+//*****************************************************************************
+//
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
+//
+// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_WATCHDOG_H__
+#define __HW_WATCHDOG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Watchdog Timer register offsets.
+//
+//*****************************************************************************
+#define WDT_O_LOAD 0x00000000 // Watchdog Load
+#define WDT_O_VALUE 0x00000004 // Watchdog Value
+#define WDT_O_CTL 0x00000008 // Watchdog Control
+#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear
+#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status
+#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status
+#define WDT_O_TEST 0x00000418 // Watchdog Test
+#define WDT_O_LOCK 0x00000C00 // Watchdog Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
+#define WDT_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
+#define WDT_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC 0x80000000 // Write Complete
+#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
+#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
+#define WDT_ICR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
+#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WDT_LOCK_LOCKED 0x00000001 // Locked
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
+// WDT_MIS registers.
+//
+//*****************************************************************************
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Watchdog Timer register
+// offsets.
+//
+//*****************************************************************************
+#define WDT_O_PeriphID4 0x00000FD0
+#define WDT_O_PeriphID5 0x00000FD4
+#define WDT_O_PeriphID6 0x00000FD8
+#define WDT_O_PeriphID7 0x00000FDC
+#define WDT_O_PeriphID0 0x00000FE0
+#define WDT_O_PeriphID1 0x00000FE4
+#define WDT_O_PeriphID2 0x00000FE8
+#define WDT_O_PeriphID3 0x00000FEC
+#define WDT_O_PCellID0 0x00000FF0
+#define WDT_O_PCellID1 0x00000FF4
+#define WDT_O_PCellID2 0x00000FF8
+#define WDT_O_PCellID3 0x00000FFC
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the WDT_O_TEST
+// register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the WDT
+// registers.
+//
+//*****************************************************************************
+#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register
+#define WDT_RV_PCellID1 0x000000F0
+#define WDT_RV_PCellID3 0x000000B1
+#define WDT_RV_PeriphID1 0x00000018
+#define WDT_RV_PeriphID2 0x00000018
+#define WDT_RV_PCellID0 0x0000000D
+#define WDT_RV_PCellID2 0x00000005
+#define WDT_RV_PeriphID0 0x00000005
+#define WDT_RV_PeriphID3 0x00000001
+#define WDT_RV_PeriphID5 0x00000000
+#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
+#define WDT_RV_CTL 0x00000000 // Control register
+#define WDT_RV_PeriphID4 0x00000000
+#define WDT_RV_PeriphID6 0x00000000
+#define WDT_RV_PeriphID7 0x00000000
+#define WDT_RV_LOCK 0x00000000 // Lock register
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
+
+#endif
+
+#endif // __HW_WATCHDOG_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/lm3s6965.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/lm3s6965.h
new file mode 100644
index 00000000..b52248cd
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/lib/inc/lm3s6965.h
@@ -0,0 +1,4795 @@
+//*****************************************************************************
+//
+// lm3s6965.h - LM3S6965 Register Definitions
+//
+// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Texas Instruments (TI) is supplying this software for use solely and
+// exclusively on TI's microcontroller products. The software is owned by
+// TI and/or its suppliers, and is protected under applicable copyright
+// laws. You may not combine this software with "viral" open-source
+// software in order to form a larger program.
+//
+// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+// DAMAGES, FOR ANY REASON WHATSOEVER.
+//
+// This is part of revision 6852 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __LM3S6965_H__
+#define __LM3S6965_H__
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG0)
+//
+//*****************************************************************************
+#define WATCHDOG0_LOAD_R (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG0_VALUE_R (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG0_CTL_R (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG0_ICR_R (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG0_RIS_R (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG0_MIS_R (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG0_TEST_R (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG0_LOCK_R (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTA)
+//
+//*****************************************************************************
+#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000)
+#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC))
+#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400))
+#define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404))
+#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408))
+#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C))
+#define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410))
+#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414))
+#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418))
+#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C))
+#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420))
+#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500))
+#define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504))
+#define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508))
+#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C))
+#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510))
+#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514))
+#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518))
+#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C))
+#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520))
+#define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000)
+#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC))
+#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400))
+#define GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404))
+#define GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408))
+#define GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C))
+#define GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410))
+#define GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414))
+#define GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418))
+#define GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C))
+#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420))
+#define GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500))
+#define GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504))
+#define GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508))
+#define GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C))
+#define GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510))
+#define GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514))
+#define GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518))
+#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C))
+#define GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520))
+#define GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTC)
+//
+//*****************************************************************************
+#define GPIO_PORTC_DATA_BITS_R ((volatile unsigned long *)0x40006000)
+#define GPIO_PORTC_DATA_R (*((volatile unsigned long *)0x400063FC))
+#define GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400))
+#define GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404))
+#define GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408))
+#define GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C))
+#define GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410))
+#define GPIO_PORTC_RIS_R (*((volatile unsigned long *)0x40006414))
+#define GPIO_PORTC_MIS_R (*((volatile unsigned long *)0x40006418))
+#define GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C))
+#define GPIO_PORTC_AFSEL_R (*((volatile unsigned long *)0x40006420))
+#define GPIO_PORTC_DR2R_R (*((volatile unsigned long *)0x40006500))
+#define GPIO_PORTC_DR4R_R (*((volatile unsigned long *)0x40006504))
+#define GPIO_PORTC_DR8R_R (*((volatile unsigned long *)0x40006508))
+#define GPIO_PORTC_ODR_R (*((volatile unsigned long *)0x4000650C))
+#define GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510))
+#define GPIO_PORTC_PDR_R (*((volatile unsigned long *)0x40006514))
+#define GPIO_PORTC_SLR_R (*((volatile unsigned long *)0x40006518))
+#define GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C))
+#define GPIO_PORTC_LOCK_R (*((volatile unsigned long *)0x40006520))
+#define GPIO_PORTC_CR_R (*((volatile unsigned long *)0x40006524))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTD)
+//
+//*****************************************************************************
+#define GPIO_PORTD_DATA_BITS_R ((volatile unsigned long *)0x40007000)
+#define GPIO_PORTD_DATA_R (*((volatile unsigned long *)0x400073FC))
+#define GPIO_PORTD_DIR_R (*((volatile unsigned long *)0x40007400))
+#define GPIO_PORTD_IS_R (*((volatile unsigned long *)0x40007404))
+#define GPIO_PORTD_IBE_R (*((volatile unsigned long *)0x40007408))
+#define GPIO_PORTD_IEV_R (*((volatile unsigned long *)0x4000740C))
+#define GPIO_PORTD_IM_R (*((volatile unsigned long *)0x40007410))
+#define GPIO_PORTD_RIS_R (*((volatile unsigned long *)0x40007414))
+#define GPIO_PORTD_MIS_R (*((volatile unsigned long *)0x40007418))
+#define GPIO_PORTD_ICR_R (*((volatile unsigned long *)0x4000741C))
+#define GPIO_PORTD_AFSEL_R (*((volatile unsigned long *)0x40007420))
+#define GPIO_PORTD_DR2R_R (*((volatile unsigned long *)0x40007500))
+#define GPIO_PORTD_DR4R_R (*((volatile unsigned long *)0x40007504))
+#define GPIO_PORTD_DR8R_R (*((volatile unsigned long *)0x40007508))
+#define GPIO_PORTD_ODR_R (*((volatile unsigned long *)0x4000750C))
+#define GPIO_PORTD_PUR_R (*((volatile unsigned long *)0x40007510))
+#define GPIO_PORTD_PDR_R (*((volatile unsigned long *)0x40007514))
+#define GPIO_PORTD_SLR_R (*((volatile unsigned long *)0x40007518))
+#define GPIO_PORTD_DEN_R (*((volatile unsigned long *)0x4000751C))
+#define GPIO_PORTD_LOCK_R (*((volatile unsigned long *)0x40007520))
+#define GPIO_PORTD_CR_R (*((volatile unsigned long *)0x40007524))
+
+//*****************************************************************************
+//
+// SSI registers (SSI0)
+//
+//*****************************************************************************
+#define SSI0_CR0_R (*((volatile unsigned long *)0x40008000))
+#define SSI0_CR1_R (*((volatile unsigned long *)0x40008004))
+#define SSI0_DR_R (*((volatile unsigned long *)0x40008008))
+#define SSI0_SR_R (*((volatile unsigned long *)0x4000800C))
+#define SSI0_CPSR_R (*((volatile unsigned long *)0x40008010))
+#define SSI0_IM_R (*((volatile unsigned long *)0x40008014))
+#define SSI0_RIS_R (*((volatile unsigned long *)0x40008018))
+#define SSI0_MIS_R (*((volatile unsigned long *)0x4000801C))
+#define SSI0_ICR_R (*((volatile unsigned long *)0x40008020))
+
+//*****************************************************************************
+//
+// UART registers (UART0)
+//
+//*****************************************************************************
+#define UART0_DR_R (*((volatile unsigned long *)0x4000C000))
+#define UART0_RSR_R (*((volatile unsigned long *)0x4000C004))
+#define UART0_ECR_R (*((volatile unsigned long *)0x4000C004))
+#define UART0_FR_R (*((volatile unsigned long *)0x4000C018))
+#define UART0_ILPR_R (*((volatile unsigned long *)0x4000C020))
+#define UART0_IBRD_R (*((volatile unsigned long *)0x4000C024))
+#define UART0_FBRD_R (*((volatile unsigned long *)0x4000C028))
+#define UART0_LCRH_R (*((volatile unsigned long *)0x4000C02C))
+#define UART0_CTL_R (*((volatile unsigned long *)0x4000C030))
+#define UART0_IFLS_R (*((volatile unsigned long *)0x4000C034))
+#define UART0_IM_R (*((volatile unsigned long *)0x4000C038))
+#define UART0_RIS_R (*((volatile unsigned long *)0x4000C03C))
+#define UART0_MIS_R (*((volatile unsigned long *)0x4000C040))
+#define UART0_ICR_R (*((volatile unsigned long *)0x4000C044))
+
+//*****************************************************************************
+//
+// UART registers (UART1)
+//
+//*****************************************************************************
+#define UART1_DR_R (*((volatile unsigned long *)0x4000D000))
+#define UART1_RSR_R (*((volatile unsigned long *)0x4000D004))
+#define UART1_ECR_R (*((volatile unsigned long *)0x4000D004))
+#define UART1_FR_R (*((volatile unsigned long *)0x4000D018))
+#define UART1_ILPR_R (*((volatile unsigned long *)0x4000D020))
+#define UART1_IBRD_R (*((volatile unsigned long *)0x4000D024))
+#define UART1_FBRD_R (*((volatile unsigned long *)0x4000D028))
+#define UART1_LCRH_R (*((volatile unsigned long *)0x4000D02C))
+#define UART1_CTL_R (*((volatile unsigned long *)0x4000D030))
+#define UART1_IFLS_R (*((volatile unsigned long *)0x4000D034))
+#define UART1_IM_R (*((volatile unsigned long *)0x4000D038))
+#define UART1_RIS_R (*((volatile unsigned long *)0x4000D03C))
+#define UART1_MIS_R (*((volatile unsigned long *)0x4000D040))
+#define UART1_ICR_R (*((volatile unsigned long *)0x4000D044))
+
+//*****************************************************************************
+//
+// UART registers (UART2)
+//
+//*****************************************************************************
+#define UART2_DR_R (*((volatile unsigned long *)0x4000E000))
+#define UART2_RSR_R (*((volatile unsigned long *)0x4000E004))
+#define UART2_ECR_R (*((volatile unsigned long *)0x4000E004))
+#define UART2_FR_R (*((volatile unsigned long *)0x4000E018))
+#define UART2_ILPR_R (*((volatile unsigned long *)0x4000E020))
+#define UART2_IBRD_R (*((volatile unsigned long *)0x4000E024))
+#define UART2_FBRD_R (*((volatile unsigned long *)0x4000E028))
+#define UART2_LCRH_R (*((volatile unsigned long *)0x4000E02C))
+#define UART2_CTL_R (*((volatile unsigned long *)0x4000E030))
+#define UART2_IFLS_R (*((volatile unsigned long *)0x4000E034))
+#define UART2_IM_R (*((volatile unsigned long *)0x4000E038))
+#define UART2_RIS_R (*((volatile unsigned long *)0x4000E03C))
+#define UART2_MIS_R (*((volatile unsigned long *)0x4000E040))
+#define UART2_ICR_R (*((volatile unsigned long *)0x4000E044))
+
+//*****************************************************************************
+//
+// I2C registers (I2C0 MASTER)
+//
+//*****************************************************************************
+#define I2C0_MASTER_MSA_R (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_MCS_R (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_MDR_R (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MTPR_R (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_MIMR_R (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MRIS_R (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_MMIS_R (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MICR_R (*((volatile unsigned long *)0x4002001C))
+#define I2C0_MASTER_MCR_R (*((volatile unsigned long *)0x40020020))
+
+//*****************************************************************************
+//
+// I2C registers (I2C0 SLAVE)
+//
+//*****************************************************************************
+#define I2C0_SLAVE_SOAR_R (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SCSR_R (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_SDR_R (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SRIS_R (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_SMIS_R (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SICR_R (*((volatile unsigned long *)0x40020818))
+
+//*****************************************************************************
+//
+// I2C registers (I2C1 MASTER)
+//
+//*****************************************************************************
+#define I2C1_MASTER_MSA_R (*((volatile unsigned long *)0x40021000))
+#define I2C1_MASTER_MCS_R (*((volatile unsigned long *)0x40021004))
+#define I2C1_MASTER_MDR_R (*((volatile unsigned long *)0x40021008))
+#define I2C1_MASTER_MTPR_R (*((volatile unsigned long *)0x4002100C))
+#define I2C1_MASTER_MIMR_R (*((volatile unsigned long *)0x40021010))
+#define I2C1_MASTER_MRIS_R (*((volatile unsigned long *)0x40021014))
+#define I2C1_MASTER_MMIS_R (*((volatile unsigned long *)0x40021018))
+#define I2C1_MASTER_MICR_R (*((volatile unsigned long *)0x4002101C))
+#define I2C1_MASTER_MCR_R (*((volatile unsigned long *)0x40021020))
+
+//*****************************************************************************
+//
+// I2C registers (I2C1 SLAVE)
+//
+//*****************************************************************************
+#define I2C1_SLAVE_SOAR_R (*((volatile unsigned long *)0x40021800))
+#define I2C1_SLAVE_SCSR_R (*((volatile unsigned long *)0x40021804))
+#define I2C1_SLAVE_SDR_R (*((volatile unsigned long *)0x40021808))
+#define I2C1_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002180C))
+#define I2C1_SLAVE_SRIS_R (*((volatile unsigned long *)0x40021810))
+#define I2C1_SLAVE_SMIS_R (*((volatile unsigned long *)0x40021814))
+#define I2C1_SLAVE_SICR_R (*((volatile unsigned long *)0x40021818))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTE)
+//
+//*****************************************************************************
+#define GPIO_PORTE_DATA_BITS_R ((volatile unsigned long *)0x40024000)
+#define GPIO_PORTE_DATA_R (*((volatile unsigned long *)0x400243FC))
+#define GPIO_PORTE_DIR_R (*((volatile unsigned long *)0x40024400))
+#define GPIO_PORTE_IS_R (*((volatile unsigned long *)0x40024404))
+#define GPIO_PORTE_IBE_R (*((volatile unsigned long *)0x40024408))
+#define GPIO_PORTE_IEV_R (*((volatile unsigned long *)0x4002440C))
+#define GPIO_PORTE_IM_R (*((volatile unsigned long *)0x40024410))
+#define GPIO_PORTE_RIS_R (*((volatile unsigned long *)0x40024414))
+#define GPIO_PORTE_MIS_R (*((volatile unsigned long *)0x40024418))
+#define GPIO_PORTE_ICR_R (*((volatile unsigned long *)0x4002441C))
+#define GPIO_PORTE_AFSEL_R (*((volatile unsigned long *)0x40024420))
+#define GPIO_PORTE_DR2R_R (*((volatile unsigned long *)0x40024500))
+#define GPIO_PORTE_DR4R_R (*((volatile unsigned long *)0x40024504))
+#define GPIO_PORTE_DR8R_R (*((volatile unsigned long *)0x40024508))
+#define GPIO_PORTE_ODR_R (*((volatile unsigned long *)0x4002450C))
+#define GPIO_PORTE_PUR_R (*((volatile unsigned long *)0x40024510))
+#define GPIO_PORTE_PDR_R (*((volatile unsigned long *)0x40024514))
+#define GPIO_PORTE_SLR_R (*((volatile unsigned long *)0x40024518))
+#define GPIO_PORTE_DEN_R (*((volatile unsigned long *)0x4002451C))
+#define GPIO_PORTE_LOCK_R (*((volatile unsigned long *)0x40024520))
+#define GPIO_PORTE_CR_R (*((volatile unsigned long *)0x40024524))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTF)
+//
+//*****************************************************************************
+#define GPIO_PORTF_DATA_BITS_R ((volatile unsigned long *)0x40025000)
+#define GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC))
+#define GPIO_PORTF_DIR_R (*((volatile unsigned long *)0x40025400))
+#define GPIO_PORTF_IS_R (*((volatile unsigned long *)0x40025404))
+#define GPIO_PORTF_IBE_R (*((volatile unsigned long *)0x40025408))
+#define GPIO_PORTF_IEV_R (*((volatile unsigned long *)0x4002540C))
+#define GPIO_PORTF_IM_R (*((volatile unsigned long *)0x40025410))
+#define GPIO_PORTF_RIS_R (*((volatile unsigned long *)0x40025414))
+#define GPIO_PORTF_MIS_R (*((volatile unsigned long *)0x40025418))
+#define GPIO_PORTF_ICR_R (*((volatile unsigned long *)0x4002541C))
+#define GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420))
+#define GPIO_PORTF_DR2R_R (*((volatile unsigned long *)0x40025500))
+#define GPIO_PORTF_DR4R_R (*((volatile unsigned long *)0x40025504))
+#define GPIO_PORTF_DR8R_R (*((volatile unsigned long *)0x40025508))
+#define GPIO_PORTF_ODR_R (*((volatile unsigned long *)0x4002550C))
+#define GPIO_PORTF_PUR_R (*((volatile unsigned long *)0x40025510))
+#define GPIO_PORTF_PDR_R (*((volatile unsigned long *)0x40025514))
+#define GPIO_PORTF_SLR_R (*((volatile unsigned long *)0x40025518))
+#define GPIO_PORTF_DEN_R (*((volatile unsigned long *)0x4002551C))
+#define GPIO_PORTF_LOCK_R (*((volatile unsigned long *)0x40025520))
+#define GPIO_PORTF_CR_R (*((volatile unsigned long *)0x40025524))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTG)
+//
+//*****************************************************************************
+#define GPIO_PORTG_DATA_BITS_R ((volatile unsigned long *)0x40026000)
+#define GPIO_PORTG_DATA_R (*((volatile unsigned long *)0x400263FC))
+#define GPIO_PORTG_DIR_R (*((volatile unsigned long *)0x40026400))
+#define GPIO_PORTG_IS_R (*((volatile unsigned long *)0x40026404))
+#define GPIO_PORTG_IBE_R (*((volatile unsigned long *)0x40026408))
+#define GPIO_PORTG_IEV_R (*((volatile unsigned long *)0x4002640C))
+#define GPIO_PORTG_IM_R (*((volatile unsigned long *)0x40026410))
+#define GPIO_PORTG_RIS_R (*((volatile unsigned long *)0x40026414))
+#define GPIO_PORTG_MIS_R (*((volatile unsigned long *)0x40026418))
+#define GPIO_PORTG_ICR_R (*((volatile unsigned long *)0x4002641C))
+#define GPIO_PORTG_AFSEL_R (*((volatile unsigned long *)0x40026420))
+#define GPIO_PORTG_DR2R_R (*((volatile unsigned long *)0x40026500))
+#define GPIO_PORTG_DR4R_R (*((volatile unsigned long *)0x40026504))
+#define GPIO_PORTG_DR8R_R (*((volatile unsigned long *)0x40026508))
+#define GPIO_PORTG_ODR_R (*((volatile unsigned long *)0x4002650C))
+#define GPIO_PORTG_PUR_R (*((volatile unsigned long *)0x40026510))
+#define GPIO_PORTG_PDR_R (*((volatile unsigned long *)0x40026514))
+#define GPIO_PORTG_SLR_R (*((volatile unsigned long *)0x40026518))
+#define GPIO_PORTG_DEN_R (*((volatile unsigned long *)0x4002651C))
+#define GPIO_PORTG_LOCK_R (*((volatile unsigned long *)0x40026520))
+#define GPIO_PORTG_CR_R (*((volatile unsigned long *)0x40026524))
+
+//*****************************************************************************
+//
+// PWM registers (PWM)
+//
+//*****************************************************************************
+#define PWM_CTL_R (*((volatile unsigned long *)0x40028000))
+#define PWM_SYNC_R (*((volatile unsigned long *)0x40028004))
+#define PWM_ENABLE_R (*((volatile unsigned long *)0x40028008))
+#define PWM_INVERT_R (*((volatile unsigned long *)0x4002800C))
+#define PWM_FAULT_R (*((volatile unsigned long *)0x40028010))
+#define PWM_INTEN_R (*((volatile unsigned long *)0x40028014))
+#define PWM_RIS_R (*((volatile unsigned long *)0x40028018))
+#define PWM_ISC_R (*((volatile unsigned long *)0x4002801C))
+#define PWM_STATUS_R (*((volatile unsigned long *)0x40028020))
+#define PWM_0_CTL_R (*((volatile unsigned long *)0x40028040))
+#define PWM_0_INTEN_R (*((volatile unsigned long *)0x40028044))
+#define PWM_0_RIS_R (*((volatile unsigned long *)0x40028048))
+#define PWM_0_ISC_R (*((volatile unsigned long *)0x4002804C))
+#define PWM_0_LOAD_R (*((volatile unsigned long *)0x40028050))
+#define PWM_0_COUNT_R (*((volatile unsigned long *)0x40028054))
+#define PWM_0_CMPA_R (*((volatile unsigned long *)0x40028058))
+#define PWM_0_CMPB_R (*((volatile unsigned long *)0x4002805C))
+#define PWM_0_GENA_R (*((volatile unsigned long *)0x40028060))
+#define PWM_0_GENB_R (*((volatile unsigned long *)0x40028064))
+#define PWM_0_DBCTL_R (*((volatile unsigned long *)0x40028068))
+#define PWM_0_DBRISE_R (*((volatile unsigned long *)0x4002806C))
+#define PWM_0_DBFALL_R (*((volatile unsigned long *)0x40028070))
+#define PWM_1_CTL_R (*((volatile unsigned long *)0x40028080))
+#define PWM_1_INTEN_R (*((volatile unsigned long *)0x40028084))
+#define PWM_1_RIS_R (*((volatile unsigned long *)0x40028088))
+#define PWM_1_ISC_R (*((volatile unsigned long *)0x4002808C))
+#define PWM_1_LOAD_R (*((volatile unsigned long *)0x40028090))
+#define PWM_1_COUNT_R (*((volatile unsigned long *)0x40028094))
+#define PWM_1_CMPA_R (*((volatile unsigned long *)0x40028098))
+#define PWM_1_CMPB_R (*((volatile unsigned long *)0x4002809C))
+#define PWM_1_GENA_R (*((volatile unsigned long *)0x400280A0))
+#define PWM_1_GENB_R (*((volatile unsigned long *)0x400280A4))
+#define PWM_1_DBCTL_R (*((volatile unsigned long *)0x400280A8))
+#define PWM_1_DBRISE_R (*((volatile unsigned long *)0x400280AC))
+#define PWM_1_DBFALL_R (*((volatile unsigned long *)0x400280B0))
+#define PWM_2_CTL_R (*((volatile unsigned long *)0x400280C0))
+#define PWM_2_INTEN_R (*((volatile unsigned long *)0x400280C4))
+#define PWM_2_RIS_R (*((volatile unsigned long *)0x400280C8))
+#define PWM_2_ISC_R (*((volatile unsigned long *)0x400280CC))
+#define PWM_2_LOAD_R (*((volatile unsigned long *)0x400280D0))
+#define PWM_2_COUNT_R (*((volatile unsigned long *)0x400280D4))
+#define PWM_2_CMPA_R (*((volatile unsigned long *)0x400280D8))
+#define PWM_2_CMPB_R (*((volatile unsigned long *)0x400280DC))
+#define PWM_2_GENA_R (*((volatile unsigned long *)0x400280E0))
+#define PWM_2_GENB_R (*((volatile unsigned long *)0x400280E4))
+#define PWM_2_DBCTL_R (*((volatile unsigned long *)0x400280E8))
+#define PWM_2_DBRISE_R (*((volatile unsigned long *)0x400280EC))
+#define PWM_2_DBFALL_R (*((volatile unsigned long *)0x400280F0))
+
+//*****************************************************************************
+//
+// QEI registers (QEI0)
+//
+//*****************************************************************************
+#define QEI0_CTL_R (*((volatile unsigned long *)0x4002C000))
+#define QEI0_STAT_R (*((volatile unsigned long *)0x4002C004))
+#define QEI0_POS_R (*((volatile unsigned long *)0x4002C008))
+#define QEI0_MAXPOS_R (*((volatile unsigned long *)0x4002C00C))
+#define QEI0_LOAD_R (*((volatile unsigned long *)0x4002C010))
+#define QEI0_TIME_R (*((volatile unsigned long *)0x4002C014))
+#define QEI0_COUNT_R (*((volatile unsigned long *)0x4002C018))
+#define QEI0_SPEED_R (*((volatile unsigned long *)0x4002C01C))
+#define QEI0_INTEN_R (*((volatile unsigned long *)0x4002C020))
+#define QEI0_RIS_R (*((volatile unsigned long *)0x4002C024))
+#define QEI0_ISC_R (*((volatile unsigned long *)0x4002C028))
+
+//*****************************************************************************
+//
+// QEI registers (QEI1)
+//
+//*****************************************************************************
+#define QEI1_CTL_R (*((volatile unsigned long *)0x4002D000))
+#define QEI1_STAT_R (*((volatile unsigned long *)0x4002D004))
+#define QEI1_POS_R (*((volatile unsigned long *)0x4002D008))
+#define QEI1_MAXPOS_R (*((volatile unsigned long *)0x4002D00C))
+#define QEI1_LOAD_R (*((volatile unsigned long *)0x4002D010))
+#define QEI1_TIME_R (*((volatile unsigned long *)0x4002D014))
+#define QEI1_COUNT_R (*((volatile unsigned long *)0x4002D018))
+#define QEI1_SPEED_R (*((volatile unsigned long *)0x4002D01C))
+#define QEI1_INTEN_R (*((volatile unsigned long *)0x4002D020))
+#define QEI1_RIS_R (*((volatile unsigned long *)0x4002D024))
+#define QEI1_ISC_R (*((volatile unsigned long *)0x4002D028))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER0)
+//
+//*****************************************************************************
+#define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000))
+#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004))
+#define TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008))
+#define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C))
+#define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018))
+#define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C))
+#define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020))
+#define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024))
+#define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028))
+#define TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C))
+#define TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030))
+#define TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034))
+#define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038))
+#define TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C))
+#define TIMER0_TAPMR_R (*((volatile unsigned long *)0x40030040))
+#define TIMER0_TBPMR_R (*((volatile unsigned long *)0x40030044))
+#define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048))
+#define TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER1)
+//
+//*****************************************************************************
+#define TIMER1_CFG_R (*((volatile unsigned long *)0x40031000))
+#define TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004))
+#define TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008))
+#define TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C))
+#define TIMER1_IMR_R (*((volatile unsigned long *)0x40031018))
+#define TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C))
+#define TIMER1_MIS_R (*((volatile unsigned long *)0x40031020))
+#define TIMER1_ICR_R (*((volatile unsigned long *)0x40031024))
+#define TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028))
+#define TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C))
+#define TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030))
+#define TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034))
+#define TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038))
+#define TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C))
+#define TIMER1_TAPMR_R (*((volatile unsigned long *)0x40031040))
+#define TIMER1_TBPMR_R (*((volatile unsigned long *)0x40031044))
+#define TIMER1_TAR_R (*((volatile unsigned long *)0x40031048))
+#define TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER2)
+//
+//*****************************************************************************
+#define TIMER2_CFG_R (*((volatile unsigned long *)0x40032000))
+#define TIMER2_TAMR_R (*((volatile unsigned long *)0x40032004))
+#define TIMER2_TBMR_R (*((volatile unsigned long *)0x40032008))
+#define TIMER2_CTL_R (*((volatile unsigned long *)0x4003200C))
+#define TIMER2_IMR_R (*((volatile unsigned long *)0x40032018))
+#define TIMER2_RIS_R (*((volatile unsigned long *)0x4003201C))
+#define TIMER2_MIS_R (*((volatile unsigned long *)0x40032020))
+#define TIMER2_ICR_R (*((volatile unsigned long *)0x40032024))
+#define TIMER2_TAILR_R (*((volatile unsigned long *)0x40032028))
+#define TIMER2_TBILR_R (*((volatile unsigned long *)0x4003202C))
+#define TIMER2_TAMATCHR_R (*((volatile unsigned long *)0x40032030))
+#define TIMER2_TBMATCHR_R (*((volatile unsigned long *)0x40032034))
+#define TIMER2_TAPR_R (*((volatile unsigned long *)0x40032038))
+#define TIMER2_TBPR_R (*((volatile unsigned long *)0x4003203C))
+#define TIMER2_TAPMR_R (*((volatile unsigned long *)0x40032040))
+#define TIMER2_TBPMR_R (*((volatile unsigned long *)0x40032044))
+#define TIMER2_TAR_R (*((volatile unsigned long *)0x40032048))
+#define TIMER2_TBR_R (*((volatile unsigned long *)0x4003204C))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER3)
+//
+//*****************************************************************************
+#define TIMER3_CFG_R (*((volatile unsigned long *)0x40033000))
+#define TIMER3_TAMR_R (*((volatile unsigned long *)0x40033004))
+#define TIMER3_TBMR_R (*((volatile unsigned long *)0x40033008))
+#define TIMER3_CTL_R (*((volatile unsigned long *)0x4003300C))
+#define TIMER3_IMR_R (*((volatile unsigned long *)0x40033018))
+#define TIMER3_RIS_R (*((volatile unsigned long *)0x4003301C))
+#define TIMER3_MIS_R (*((volatile unsigned long *)0x40033020))
+#define TIMER3_ICR_R (*((volatile unsigned long *)0x40033024))
+#define TIMER3_TAILR_R (*((volatile unsigned long *)0x40033028))
+#define TIMER3_TBILR_R (*((volatile unsigned long *)0x4003302C))
+#define TIMER3_TAMATCHR_R (*((volatile unsigned long *)0x40033030))
+#define TIMER3_TBMATCHR_R (*((volatile unsigned long *)0x40033034))
+#define TIMER3_TAPR_R (*((volatile unsigned long *)0x40033038))
+#define TIMER3_TBPR_R (*((volatile unsigned long *)0x4003303C))
+#define TIMER3_TAPMR_R (*((volatile unsigned long *)0x40033040))
+#define TIMER3_TBPMR_R (*((volatile unsigned long *)0x40033044))
+#define TIMER3_TAR_R (*((volatile unsigned long *)0x40033048))
+#define TIMER3_TBR_R (*((volatile unsigned long *)0x4003304C))
+
+//*****************************************************************************
+//
+// ADC registers (ADC0)
+//
+//*****************************************************************************
+#define ADC0_ACTSS_R (*((volatile unsigned long *)0x40038000))
+#define ADC0_RIS_R (*((volatile unsigned long *)0x40038004))
+#define ADC0_IM_R (*((volatile unsigned long *)0x40038008))
+#define ADC0_ISC_R (*((volatile unsigned long *)0x4003800C))
+#define ADC0_OSTAT_R (*((volatile unsigned long *)0x40038010))
+#define ADC0_EMUX_R (*((volatile unsigned long *)0x40038014))
+#define ADC0_USTAT_R (*((volatile unsigned long *)0x40038018))
+#define ADC0_SSPRI_R (*((volatile unsigned long *)0x40038020))
+#define ADC0_PSSI_R (*((volatile unsigned long *)0x40038028))
+#define ADC0_SAC_R (*((volatile unsigned long *)0x40038030))
+#define ADC0_SSMUX0_R (*((volatile unsigned long *)0x40038040))
+#define ADC0_SSCTL0_R (*((volatile unsigned long *)0x40038044))
+#define ADC0_SSFIFO0_R (*((volatile unsigned long *)0x40038048))
+#define ADC0_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C))
+#define ADC0_SSMUX1_R (*((volatile unsigned long *)0x40038060))
+#define ADC0_SSCTL1_R (*((volatile unsigned long *)0x40038064))
+#define ADC0_SSFIFO1_R (*((volatile unsigned long *)0x40038068))
+#define ADC0_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C))
+#define ADC0_SSMUX2_R (*((volatile unsigned long *)0x40038080))
+#define ADC0_SSCTL2_R (*((volatile unsigned long *)0x40038084))
+#define ADC0_SSFIFO2_R (*((volatile unsigned long *)0x40038088))
+#define ADC0_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C))
+#define ADC0_SSMUX3_R (*((volatile unsigned long *)0x400380A0))
+#define ADC0_SSCTL3_R (*((volatile unsigned long *)0x400380A4))
+#define ADC0_SSFIFO3_R (*((volatile unsigned long *)0x400380A8))
+#define ADC0_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC))
+#define ADC0_TMLB_R (*((volatile unsigned long *)0x40038100))
+
+//*****************************************************************************
+//
+// Comparator registers (COMP)
+//
+//*****************************************************************************
+#define COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000))
+#define COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004))
+#define COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008))
+#define COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010))
+#define COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020))
+#define COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024))
+#define COMP_ACSTAT1_R (*((volatile unsigned long *)0x4003C040))
+#define COMP_ACCTL1_R (*((volatile unsigned long *)0x4003C044))
+
+//*****************************************************************************
+//
+// Ethernet MAC registers (MAC)
+//
+//*****************************************************************************
+#define MAC_RIS_R (*((volatile unsigned long *)0x40048000))
+#define MAC_IACK_R (*((volatile unsigned long *)0x40048000))
+#define MAC_IM_R (*((volatile unsigned long *)0x40048004))
+#define MAC_RCTL_R (*((volatile unsigned long *)0x40048008))
+#define MAC_TCTL_R (*((volatile unsigned long *)0x4004800C))
+#define MAC_DATA_R (*((volatile unsigned long *)0x40048010))
+#define MAC_IA0_R (*((volatile unsigned long *)0x40048014))
+#define MAC_IA1_R (*((volatile unsigned long *)0x40048018))
+#define MAC_THR_R (*((volatile unsigned long *)0x4004801C))
+#define MAC_MCTL_R (*((volatile unsigned long *)0x40048020))
+#define MAC_MDV_R (*((volatile unsigned long *)0x40048024))
+#define MAC_MTXD_R (*((volatile unsigned long *)0x4004802C))
+#define MAC_MRXD_R (*((volatile unsigned long *)0x40048030))
+#define MAC_NP_R (*((volatile unsigned long *)0x40048034))
+#define MAC_TR_R (*((volatile unsigned long *)0x40048038))
+
+//*****************************************************************************
+//
+// Ethernet Controller PHY registers (MAC)
+//
+//*****************************************************************************
+#define PHY_MR0 0x00000000 // Ethernet PHY Management Register
+ // 0 - Control
+#define PHY_MR1 0x00000001 // Ethernet PHY Management Register
+ // 1 - Status
+#define PHY_MR2 0x00000002 // Ethernet PHY Management Register
+ // 2 - PHY Identifier 1
+#define PHY_MR3 0x00000003 // Ethernet PHY Management Register
+ // 3 - PHY Identifier 2
+#define PHY_MR4 0x00000004 // Ethernet PHY Management Register
+ // 4 - Auto-Negotiation
+ // Advertisement
+#define PHY_MR5 0x00000005 // Ethernet PHY Management Register
+ // 5 - Auto-Negotiation Link
+ // Partner Base Page Ability
+#define PHY_MR6 0x00000006 // Ethernet PHY Management Register
+ // 6 - Auto-Negotiation Expansion
+#define PHY_MR16 0x00000010 // Ethernet PHY Management Register
+ // 16 - Vendor-Specific
+#define PHY_MR17 0x00000011 // Ethernet PHY Management Register
+ // 17 - Mode Control/Status
+#define PHY_MR18 0x00000012 // Ethernet PHY Management Register
+ // 18 - Diagnostic
+#define PHY_MR19 0x00000013 // Ethernet PHY Management Register
+ // 19 - Transceiver Control
+#define PHY_MR23 0x00000017 // Ethernet PHY Management Register
+ // 23 - LED Configuration
+#define PHY_MR24 0x00000018 // Ethernet PHY Management Register
+ // 24 -MDI/MDIX Control
+
+//*****************************************************************************
+//
+// Hibernation module registers (HIB)
+//
+//*****************************************************************************
+#define HIB_RTCC_R (*((volatile unsigned long *)0x400FC000))
+#define HIB_RTCM0_R (*((volatile unsigned long *)0x400FC004))
+#define HIB_RTCM1_R (*((volatile unsigned long *)0x400FC008))
+#define HIB_RTCLD_R (*((volatile unsigned long *)0x400FC00C))
+#define HIB_CTL_R (*((volatile unsigned long *)0x400FC010))
+#define HIB_IM_R (*((volatile unsigned long *)0x400FC014))
+#define HIB_RIS_R (*((volatile unsigned long *)0x400FC018))
+#define HIB_MIS_R (*((volatile unsigned long *)0x400FC01C))
+#define HIB_IC_R (*((volatile unsigned long *)0x400FC020))
+#define HIB_RTCT_R (*((volatile unsigned long *)0x400FC024))
+#define HIB_DATA_R (*((volatile unsigned long *)0x400FC030))
+
+//*****************************************************************************
+//
+// FLASH registers (FLASH CTRL)
+//
+//*****************************************************************************
+#define FLASH_FMA_R (*((volatile unsigned long *)0x400FD000))
+#define FLASH_FMD_R (*((volatile unsigned long *)0x400FD004))
+#define FLASH_FMC_R (*((volatile unsigned long *)0x400FD008))
+#define FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C))
+#define FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010))
+#define FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014))
+#define FLASH_USECRL_R (*((volatile unsigned long *)0x400FE140))
+#define FLASH_USERDBG_R (*((volatile unsigned long *)0x400FE1D0))
+#define FLASH_USERREG0_R (*((volatile unsigned long *)0x400FE1E0))
+#define FLASH_USERREG1_R (*((volatile unsigned long *)0x400FE1E4))
+#define FLASH_FMPRE0_R (*((volatile unsigned long *)0x400FE200))
+#define FLASH_FMPRE1_R (*((volatile unsigned long *)0x400FE204))
+#define FLASH_FMPRE2_R (*((volatile unsigned long *)0x400FE208))
+#define FLASH_FMPRE3_R (*((volatile unsigned long *)0x400FE20C))
+#define FLASH_FMPPE0_R (*((volatile unsigned long *)0x400FE400))
+#define FLASH_FMPPE1_R (*((volatile unsigned long *)0x400FE404))
+#define FLASH_FMPPE2_R (*((volatile unsigned long *)0x400FE408))
+#define FLASH_FMPPE3_R (*((volatile unsigned long *)0x400FE40C))
+
+//*****************************************************************************
+//
+// System Control registers (SYSCTL)
+//
+//*****************************************************************************
+#define SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000))
+#define SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004))
+#define SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008))
+#define SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010))
+#define SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014))
+#define SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018))
+#define SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C))
+#define SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030))
+#define SYSCTL_LDOPCTL_R (*((volatile unsigned long *)0x400FE034))
+#define SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040))
+#define SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044))
+#define SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048))
+#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))
+#define SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054))
+#define SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058))
+#define SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C))
+#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))
+#define SYSCTL_PLLCFG_R (*((volatile unsigned long *)0x400FE064))
+#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))
+#define SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100))
+#define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104))
+#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108))
+#define SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110))
+#define SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114))
+#define SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118))
+#define SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120))
+#define SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124))
+#define SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128))
+#define SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144))
+
+//*****************************************************************************
+//
+// NVIC registers (NVIC)
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004))
+#define NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010))
+#define NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014))
+#define NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018))
+#define NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C))
+#define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100))
+#define NVIC_EN1_R (*((volatile unsigned long *)0xE000E104))
+#define NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180))
+#define NVIC_DIS1_R (*((volatile unsigned long *)0xE000E184))
+#define NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200))
+#define NVIC_PEND1_R (*((volatile unsigned long *)0xE000E204))
+#define NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280))
+#define NVIC_UNPEND1_R (*((volatile unsigned long *)0xE000E284))
+#define NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300))
+#define NVIC_ACTIVE1_R (*((volatile unsigned long *)0xE000E304))
+#define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400))
+#define NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404))
+#define NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408))
+#define NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C))
+#define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410))
+#define NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414))
+#define NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418))
+#define NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C))
+#define NVIC_PRI8_R (*((volatile unsigned long *)0xE000E420))
+#define NVIC_PRI9_R (*((volatile unsigned long *)0xE000E424))
+#define NVIC_PRI10_R (*((volatile unsigned long *)0xE000E428))
+#define NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00))
+#define NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04))
+#define NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08))
+#define NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C))
+#define NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10))
+#define NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14))
+#define NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18))
+#define NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C))
+#define NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20))
+#define NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24))
+#define NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28))
+#define NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C))
+#define NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30))
+#define NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34))
+#define NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38))
+#define NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90))
+#define NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94))
+#define NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98))
+#define NVIC_MPU_BASE_R (*((volatile unsigned long *)0xE000ED9C))
+#define NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0))
+#define NVIC_MPU_BASE1_R (*((volatile unsigned long *)0xE000EDA4))
+#define NVIC_MPU_ATTR1_R (*((volatile unsigned long *)0xE000EDA8))
+#define NVIC_MPU_BASE2_R (*((volatile unsigned long *)0xE000EDAC))
+#define NVIC_MPU_ATTR2_R (*((volatile unsigned long *)0xE000EDB0))
+#define NVIC_MPU_BASE3_R (*((volatile unsigned long *)0xE000EDB4))
+#define NVIC_MPU_ATTR3_R (*((volatile unsigned long *)0xE000EDB8))
+#define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0))
+#define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4))
+#define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8))
+#define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC))
+#define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00))
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
+#define WDT_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
+#define WDT_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
+#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
+#define WDT_ICR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
+#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WDT_LOCK_LOCKED 0x00000001 // Locked
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
+#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
+ // and may be modified
+#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
+ // and may not be modified
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
+#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
+#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
+ // Serial Frame Format
+#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
+#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
+#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
+#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
+#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
+#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
+#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
+#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
+#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
+#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
+#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
+#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
+#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
+#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
+#define SSI_CR0_SCR_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
+#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
+#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
+ // Enable
+#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
+#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
+#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
+ // Mask
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
+ // Interrupt Status
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
+ // Interrupt Status
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
+ // Clear
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE 0x00000800 // UART Overrun Error
+#define UART_DR_BE 0x00000400 // UART Break Error
+#define UART_DR_PE 0x00000200 // UART Parity Error
+#define UART_DR_FE 0x00000100 // UART Framing Error
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE 0x00000008 // UART Overrun Error
+#define UART_RSR_BE 0x00000004 // UART Break Error
+#define UART_RSR_PE 0x00000002 // UART Parity Error
+#define UART_RSR_FE 0x00000001 // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear
+#define UART_ECR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
+#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
+#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
+#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
+#define UART_FR_BUSY 0x00000008 // UART Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
+#define UART_LCRH_BRK 0x00000001 // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_RXE 0x00000200 // UART Receive Enable
+#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
+#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
+#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
+#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
+#define UART_CTL_UARTEN 0x00000001 // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
+ // Level Select
+#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
+ // Level Select
+#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
+ // Mask
+#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
+#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
+ // Mask
+#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
+ // Mask
+#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
+#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
+ // Status
+#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
+ // Status
+#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
+ // Status
+#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
+ // Status
+#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
+ // Interrupt Status
+#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
+ // Status
+#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
+ // Interrupt Status
+#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
+ // Interrupt Status
+#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
+ // Interrupt Status
+#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
+ // Interrupt Status
+#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
+ // Interrupt Status
+#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
+ // Status
+#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
+#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
+#define I2C_MSA_RS 0x00000001 // Receive not send
+#define I2C_MSA_SA_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
+#define I2C_SCSR_DA 0x00000001 // Device Active
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
+#define I2C_MCS_STOP 0x00000004 // Generate STOP
+#define I2C_MCS_START 0x00000002 // Generate START
+#define I2C_MCS_ERROR 0x00000002 // Error
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_IM 0x00000001 // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_IC 0x00000001 // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal
+#define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal
+#define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal
+#define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal
+#define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal
+#define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault
+#define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault
+#define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault
+#define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault
+#define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault
+#define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable
+#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted
+#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted
+#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT 0x00000001 // Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
+//
+//*****************************************************************************
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_X_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
+ // Down
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
+ // Down
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
+ // Down
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
+ // Up
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
+ // Down
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
+ // Up
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_X_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_X_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_X_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_X_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_X_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_X_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_X_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_X_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_X_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_X_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_X_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_X_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
+#define PWM_X_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
+#define PWM_X_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_STALLEN 0x00001000 // Stall QEI
+#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse
+#define QEI_CTL_INVB 0x00000400 // Invert PhB
+#define QEI_CTL_INVA 0x00000200 // Invert PhA
+#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity
+#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1
+#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2
+#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4
+#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8
+#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16
+#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32
+#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64
+#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128
+#define QEI_CTL_VELEN 0x00000020 // Capture Velocity
+#define QEI_CTL_RESMODE 0x00000010 // Reset Mode
+#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode
+#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode
+#define QEI_CTL_SWAP 0x00000002 // Swap Signals
+#define QEI_CTL_ENABLE 0x00000001 // Enable QEI
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation
+#define QEI_STAT_ERROR 0x00000001 // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
+ // Value
+#define QEI_POS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
+ // Value
+#define QEI_MAXPOS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value
+#define QEI_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value
+#define QEI_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count
+#define QEI_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M 0xFFFFFFFF // Velocity
+#define QEI_SPEED_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
+ // Enable
+#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected
+#define QEI_RIS_DIR 0x00000004 // Direction Change Detected
+#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired
+#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt
+#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt
+#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
+ // counter configuration
+#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
+ // function is controlled by bits
+ // 1:0 of GPTMTAMR and GPTMTBMR
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
+ // Select
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
+ // Select
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
+ // Enable
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
+#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
+ // Enable
+#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
+#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt
+ // Mask
+#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt
+ // Mask
+#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Mask
+#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt
+ // Mask
+#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt
+ // Mask
+#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw
+ // Interrupt
+#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw
+ // Interrupt
+#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
+ // Interrupt
+#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw
+ // Interrupt
+#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw
+ // Interrupt
+#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked
+ // Interrupt
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked
+ // Interrupt
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
+ // Interrupt
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked
+ // Interrupt
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked
+ // Interrupt
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt
+ // Clear
+#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt
+ // Clear
+#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Clear
+#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt
+ // Clear
+#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt
+ // Clear
+#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load
+ // Register High
+#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load
+ // Register Low
+#define TIMER_TAILR_TAILRH_S 16
+#define TIMER_TAILR_TAILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load
+ // Register
+#define TIMER_TBILR_TBILRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High
+#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low
+#define TIMER_TAMATCHR_TAMRH_S 16
+#define TIMER_TAMATCHR_TAMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low
+#define TIMER_TBMATCHR_TBMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High
+#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low
+#define TIMER_TAR_TARH_S 16
+#define TIMER_TAR_TARL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM Timer B
+#define TIMER_TBR_TBRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask
+#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask
+#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask
+#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
+#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
+#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
+#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow
+#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow
+#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow
+#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
+#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
+#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
+#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate
+#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate
+#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate
+#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M 0x30000000 // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M 0x03000000 // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M 0x00300000 // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M 0x00030000 // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M 0x00003000 // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M 0x00000300 // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M 0x00000030 // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M 0x00000003 // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S 28
+#define ADC_SSMUX0_MUX6_S 24
+#define ADC_SSMUX0_MUX5_S 20
+#define ADC_SSMUX0_MUX4_S 16
+#define ADC_SSMUX0_MUX3_S 12
+#define ADC_SSMUX0_MUX2_S 8
+#define ADC_SSMUX0_MUX1_S 4
+#define ADC_SSMUX0_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S 4
+#define ADC_SSFSTAT0_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M 0x00003000 // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M 0x00000300 // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M 0x00000030 // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M 0x00000003 // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S 12
+#define ADC_SSMUX1_MUX2_S 8
+#define ADC_SSMUX1_MUX1_S 4
+#define ADC_SSMUX1_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S 4
+#define ADC_SSFSTAT1_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M 0x00003000 // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M 0x00000300 // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M 0x00000030 // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M 0x00000003 // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S 12
+#define ADC_SSMUX2_MUX2_S 8
+#define ADC_SSMUX2_MUX1_S 4
+#define ADC_SSMUX2_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S 4
+#define ADC_SSFSTAT2_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M 0x00000003 // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S 4
+#define ADC_SSFSTAT3_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TMLB register.
+//
+//*****************************************************************************
+#define ADC_TMLB_LB 0x00000001 // Loopback Mode Enable
+
+//*****************************************************************************
+//
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter
+#define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator
+#define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator
+#define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator
+#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator
+#define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
+ // Status
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt
+#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete
+#define MAC_RIS_RXER 0x00000010 // Receive Error
+#define MAC_RIS_FOV 0x00000008 // FIFO Overrun
+#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty
+#define MAC_RIS_TXER 0x00000002 // Transmit Error
+#define MAC_RIS_RXINT 0x00000001 // Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IACK register.
+//
+//*****************************************************************************
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt
+#define MAC_IACK_MDINT 0x00000020 // Clear MII Transaction Complete
+#define MAC_IACK_RXER 0x00000010 // Clear Receive Error
+#define MAC_IACK_FOV 0x00000008 // Clear FIFO Overrun
+#define MAC_IACK_TXEMP 0x00000004 // Clear Transmit FIFO Empty
+#define MAC_IACK_TXER 0x00000002 // Clear Transmit Error
+#define MAC_IACK_RXINT 0x00000001 // Clear Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IM register.
+//
+//*****************************************************************************
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt
+#define MAC_IM_MDINTM 0x00000020 // Mask MII Transaction Complete
+#define MAC_IM_RXERM 0x00000010 // Mask Receive Error
+#define MAC_IM_FOVM 0x00000008 // Mask FIFO Overrun
+#define MAC_IM_TXEMPM 0x00000004 // Mask Transmit FIFO Empty
+#define MAC_IM_TXERM 0x00000002 // Mask Transmit Error
+#define MAC_IM_RXINTM 0x00000001 // Mask Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RCTL register.
+//
+//*****************************************************************************
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear Receive FIFO
+#define MAC_RCTL_BADCRC 0x00000008 // Enable Reject Bad CRC
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Frames
+#define MAC_RCTL_RXEN 0x00000001 // Enable Receiver
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex Mode
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation
+#define MAC_TCTL_PADEN 0x00000002 // Enable Packet Padding
+#define MAC_TCTL_TXEN 0x00000001 // Enable Transmitter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data
+#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data
+#define MAC_DATA_RXDATA_S 0
+#define MAC_DATA_TXDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4
+#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3
+#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2
+#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1
+#define MAC_IA0_MACOCT4_S 24
+#define MAC_IA0_MACOCT3_S 16
+#define MAC_IA0_MACOCT2_S 8
+#define MAC_IA0_MACOCT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6
+#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5
+#define MAC_IA1_MACOCT6_S 8
+#define MAC_IA1_MACOCT5_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_THR register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M 0x0000003F // Threshold Value
+#define MAC_THR_THRESH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address
+#define MAC_MCTL_WRITE 0x00000002 // MII Register Transaction Type
+#define MAC_MCTL_START 0x00000001 // MII Register Transaction Enable
+#define MAC_MCTL_REGADR_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M 0x000000FF // Clock Divider
+#define MAC_MDV_DIV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data
+#define MAC_MTXD_MDTX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data
+#define MAC_MRXD_MDRX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive
+ // FIFO
+#define MAC_NP_NPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TR register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX 0x00000001 // New Transmission
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET 0x00008000 // Reset Registers
+#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode
+#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select
+#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable
+#define PHY_MR0_PWRDN 0x00000800 // Power Down
+#define PHY_MR0_ISO 0x00000400 // Isolate
+#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation
+#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode
+#define PHY_MR0_COLT 0x00000080 // Collision Test
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode
+#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode
+#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode
+#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode
+#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble
+ // Suppressed
+#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete
+#define PHY_MR1_RFAULT 0x00000010 // Remote Fault
+#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation
+#define PHY_MR1_LINK 0x00000004 // Link Made
+#define PHY_MR1_JAB 0x00000002 // Jabber Condition
+#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
+ // Identifier[21:6]
+#define PHY_MR2_OUI_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
+ // Identifier[5:0]
+#define PHY_MR3_MN_M 0x000003F0 // Model Number
+#define PHY_MR3_RN_M 0x0000000F // Revision Number
+#define PHY_MR3_OUI_S 10
+#define PHY_MR3_MN_S 4
+#define PHY_MR3_RN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP 0x00008000 // Next Page
+#define PHY_MR4_RF 0x00002000 // Remote Fault
+#define PHY_MR4_A3 0x00000100 // Technology Ability Field [3]
+#define PHY_MR4_A2 0x00000080 // Technology Ability Field [2]
+#define PHY_MR4_A1 0x00000040 // Technology Ability Field [1]
+#define PHY_MR4_A0 0x00000020 // Technology Ability Field [0]
+#define PHY_MR4_S_M 0x0000001F // Selector Field
+#define PHY_MR4_S_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR5 register.
+//
+//*****************************************************************************
+#define PHY_MR5_NP 0x00008000 // Next Page
+#define PHY_MR5_ACK 0x00004000 // Acknowledge
+#define PHY_MR5_RF 0x00002000 // Remote Fault
+#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field
+#define PHY_MR5_S_M 0x0000001F // Selector Field
+#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
+#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
+#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
+#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
+#define PHY_MR5_A_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR6 register.
+//
+//*****************************************************************************
+#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault
+#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able
+#define PHY_MR6_PRX 0x00000002 // New Page Received
+#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
+ // Able
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR16 register.
+//
+//*****************************************************************************
+#define PHY_MR16_RPTR 0x00008000 // Repeater Mode
+#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity
+#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode
+#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing
+#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode
+#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable
+#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity
+#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass
+#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR17 register.
+//
+//*****************************************************************************
+#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable
+#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable
+#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable
+#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
+ // Interrupt Enable
+#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable
+#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
+ // Enable
+#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable
+#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
+ // Interrupt Enable
+#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt
+#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt
+#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt
+#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
+ // Interrupt
+#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt
+#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt
+#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt
+#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR18 register.
+//
+//*****************************************************************************
+#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure
+#define PHY_MR18_DPLX 0x00000800 // Duplex Mode
+#define PHY_MR18_RATE 0x00000400 // Rate
+#define PHY_MR18_RXSD 0x00000200 // Receive Detection
+#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR19 register.
+//
+//*****************************************************************************
+#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection
+#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
+ // loss
+#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
+ // loss
+#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
+ // loss
+#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion
+ // loss
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR23 register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source
+#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
+#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
+#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
+#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
+#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
+#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
+ // Activity
+#define PHY_MR23_LED0_M 0x0000000F // LED0 Source
+#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
+#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
+#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
+#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
+#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
+#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
+ // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR24 register.
+//
+//*****************************************************************************
+#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode
+#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable
+#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration
+#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete
+#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed
+#define PHY_MR24_MDIX_SD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
+#define HIB_RTCC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
+#define HIB_RTCM0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM1 register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1
+#define HIB_RTCM1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
+#define HIB_RTCLD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
+#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable
+#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
+#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
+#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select
+#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
+#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
+ // Mask
+#define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask
+#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
+ // Status
+#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
+ // Interrupt Status
+#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status
+#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Status
+#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Status
+#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt
+ // Status
+#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Clear
+#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Clear
+#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
+ // Clear
+#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
+#define HIB_RTCT_TRIM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
+#define HIB_DATA_RTD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset
+#define FLASH_FMA_OFFSET_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
+#define FLASH_FMD_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
+#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USECRL register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value
+#define FLASH_USECRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERDBG register.
+//
+//*****************************************************************************
+#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written
+#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data
+#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1
+#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0
+#define FLASH_USERDBG_DATA_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_NW 0x80000000 // Not Written
+#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data
+#define FLASH_USERREG0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_NW 0x80000000 // Not Written
+#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data
+#define FLASH_USERREG1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE 0x00000800
+#define FLASH_ERASE_SIZE 0x00000400
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version
+#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
+ // register format
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Stellaris(R) Fury-class devices
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
+ // revision)
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
+ // revision)
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision
+#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
+ // revision update
+#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change
+#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version
+#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1
+ // register format
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family
+#define SYSCTL_DID1_FAM_STELLARIS \
+ 0x00000000 // Stellaris family of
+ // microcontollers, that is, all
+ // devices with external part
+ // numbers starting with LM3S
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number
+#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C
+ // to 70C)
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
+ // (-40C to 85C)
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
+ // to 105C)
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type
+#define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
+#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
+#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
+#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present
+#define SYSCTL_DC1_ADC 0x00010000 // ADC Module Present
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
+ // with a PLL divider of 4
+#define SYSCTL_DC1_ADCSPD_M 0x00000300 // Max ADC Speed
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DC1_MPU 0x00000080 // MPU Present
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present
+#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present
+#define SYSCTL_DC1_PLL 0x00000010 // PLL Present
+#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present
+#define SYSCTL_DC1_SWD 0x00000002 // SWD Present
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present
+#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present
+#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present
+#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 Pin Present
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 Pin Present
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 Pin Present
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 Pin Present
+#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present
+#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // 2.50
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // 2.45
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // 2.40
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // 2.35
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // 2.30
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // 2.25
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // 2.75
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // 2.70
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // 2.65
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // 2.60
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // 2.55
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control
+#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control
+#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control
+#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_SW 0x00000010 // Software Reset
+#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset
+#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset
+#define SYSCTL_RESC_EXT 0x00000001 // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass
+#define SYSCTL_RCC_XTAL_M 0x000003C0 // Crystal Value
+#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // 1 MHz
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // 1.8432 MHz
+#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // 2 MHz
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // 2.4576 MHz
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // 3.579545 MHz
+#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // 3.6864 MHz
+#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value
+#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value
+#define SYSCTL_PLLCFG_F_S 5
+#define SYSCTL_PLLCFG_R_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz
+#define SYSCTL_RCC2_SYSDIV2_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed
+#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control
+#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADCSPD_M 0x00000300 // ADC Sample Speed
+#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second
+#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control
+#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control
+#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_D_1 0x00000000 // System clock /1
+#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2
+#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3
+#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4
+#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5
+#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6
+#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7
+#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8
+#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9
+#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10
+#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11
+#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12
+#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13
+#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14
+#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15
+#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16
+#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17
+#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18
+#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19
+#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20
+#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21
+#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22
+#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23
+#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24
+#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25
+#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26
+#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27
+#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28
+#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29
+#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30
+#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31
+#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32
+#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33
+#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34
+#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35
+#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36
+#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37
+#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38
+#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39
+#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40
+#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41
+#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42
+#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43
+#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44
+#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45
+#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46
+#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47
+#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48
+#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49
+#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50
+#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51
+#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52
+#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53
+#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54
+#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55
+#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56
+#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57
+#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58
+#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59
+#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60
+#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61
+#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62
+#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63
+#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz
+#define SYSCTL_DSLPCLKCFG_D_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M 0x00000FFF // Interrupt Enable
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M 0x00000FFF // Interrupt Disable
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M 0x00000FFF // Interrupt Set Pending
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M 0x00000FFF // Interrupt Clear Pending
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M 0x00000FFF // Interrupt Active
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S 29
+#define NVIC_PRI0_INT2_S 21
+#define NVIC_PRI0_INT1_S 13
+#define NVIC_PRI0_INT0_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S 29
+#define NVIC_PRI1_INT6_S 21
+#define NVIC_PRI1_INT5_S 13
+#define NVIC_PRI1_INT4_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S 29
+#define NVIC_PRI2_INT10_S 21
+#define NVIC_PRI2_INT9_S 13
+#define NVIC_PRI2_INT8_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S 29
+#define NVIC_PRI3_INT14_S 21
+#define NVIC_PRI3_INT13_S 13
+#define NVIC_PRI3_INT12_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S 29
+#define NVIC_PRI4_INT18_S 21
+#define NVIC_PRI4_INT17_S 13
+#define NVIC_PRI4_INT16_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S 29
+#define NVIC_PRI5_INT22_S 21
+#define NVIC_PRI5_INT21_S 13
+#define NVIC_PRI5_INT20_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S 29
+#define NVIC_PRI6_INT26_S 21
+#define NVIC_PRI6_INT25_S 13
+#define NVIC_PRI6_INT24_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S 29
+#define NVIC_PRI7_INT30_S 21
+#define NVIC_PRI7_INT29_S 13
+#define NVIC_PRI7_INT28_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S 29
+#define NVIC_PRI8_INT34_S 21
+#define NVIC_PRI8_INT33_S 13
+#define NVIC_PRI8_INT32_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S 29
+#define NVIC_PRI9_INT38_S 21
+#define NVIC_PRI9_INT37_S 13
+#define NVIC_PRI9_INT36_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S 29
+#define NVIC_PRI10_INT42_S 21
+#define NVIC_PRI10_INT41_S 13
+#define NVIC_PRI10_INT40_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code
+#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number
+#define NVIC_CPUID_CON_M 0x000F0000 // Constant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number
+#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor
+#define NVIC_CPUID_REV_M 0x0000000F // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x0003F000 // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+ 0x00002000 // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+ 0x00003000 // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+ 0x00004000 // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+ 0x00005000 // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+ 0x00006000 // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+ 0x0000B000 // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+ 0x0000E000 // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+ 0x0000F000 // SysTick
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x0000003F // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception
+ // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and
+ // Fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S 21
+#define NVIC_SYS_PRI1_BUS_S 13
+#define NVIC_SYS_PRI1_MEM_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S 29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S 29
+#define NVIC_SYS_PRI3_PENDSV_S 21
+#define NVIC_SYS_PRI3_DEBUG_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+ 0x00001000 // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage
+ // Fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address
+ // Register Valid
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE_ADDR_S 5
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes
+#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE1_ADDR_S 5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE2_ADDR_S 5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE3_ADDR_S 5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// Deprecated defines for the Watchdog
+//
+//*****************************************************************************
+#define WATCHDOG_LOAD_R (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG_VALUE_R (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG_CTL_R (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG_ICR_R (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG_RIS_R (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG_MIS_R (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG_TEST_R (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG_LOCK_R (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC 0x00000001 // Clear Interrupt
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM 0x00000001 // Interrupt Mask
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the the interpretation of the data
+// in the SSFIFOx when the ADC TMLB is enabled. register.
+//
+//*****************************************************************************
+#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter
+#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator
+#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator
+#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator
+#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator
+#define ADC_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// Deprecated defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_ACTSS_R (*((volatile unsigned long *)0x40038000))
+#define ADC_RIS_R (*((volatile unsigned long *)0x40038004))
+#define ADC_IM_R (*((volatile unsigned long *)0x40038008))
+#define ADC_ISC_R (*((volatile unsigned long *)0x4003800C))
+#define ADC_OSTAT_R (*((volatile unsigned long *)0x40038010))
+#define ADC_EMUX_R (*((volatile unsigned long *)0x40038014))
+#define ADC_USTAT_R (*((volatile unsigned long *)0x40038018))
+#define ADC_SSPRI_R (*((volatile unsigned long *)0x40038020))
+#define ADC_PSSI_R (*((volatile unsigned long *)0x40038028))
+#define ADC_SAC_R (*((volatile unsigned long *)0x40038030))
+#define ADC_SSMUX0_R (*((volatile unsigned long *)0x40038040))
+#define ADC_SSCTL0_R (*((volatile unsigned long *)0x40038044))
+#define ADC_SSFIFO0_R (*((volatile unsigned long *)0x40038048))
+#define ADC_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C))
+#define ADC_SSMUX1_R (*((volatile unsigned long *)0x40038060))
+#define ADC_SSCTL1_R (*((volatile unsigned long *)0x40038064))
+#define ADC_SSFIFO1_R (*((volatile unsigned long *)0x40038068))
+#define ADC_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C))
+#define ADC_SSMUX2_R (*((volatile unsigned long *)0x40038080))
+#define ADC_SSCTL2_R (*((volatile unsigned long *)0x40038084))
+#define ADC_SSFIFO2_R (*((volatile unsigned long *)0x40038088))
+#define ADC_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C))
+#define ADC_SSMUX3_R (*((volatile unsigned long *)0x400380A0))
+#define ADC_SSCTL3_R (*((volatile unsigned long *)0x400380A4))
+#define ADC_SSFIFO3_R (*((volatile unsigned long *)0x400380A8))
+#define ADC_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC))
+#define ADC_TMLB_R (*((volatile unsigned long *)0x40038100))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key
+#define FLASH_FMC_WRKEY_S 16
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // QFP package
+
+//*****************************************************************************
+//
+// Deprecated defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_MPU_R (*((volatile unsigned long *)0xE000ED9C))
+
+#endif
+
+#endif // __LM3S6965_H__
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/main.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/main.c
new file mode 100644
index 00000000..871181a4
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/main.c
@@ -0,0 +1,120 @@
+/****************************************************************************************
+| Description: demo program application source file
+| File Name: main.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h" /* generic header */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static void Init(void);
+
+
+/****************************************************************************************
+** NAME: main
+** PARAMETER: none
+** RETURN VALUE: program return code
+** DESCRIPTION: This is the entry point for the bootloader application and is called
+** by the reset interrupt vector after the C-startup routines executed.
+**
+****************************************************************************************/
+int main(void)
+{
+ /* initialize the microcontroller */
+ Init();
+ /* initialize the bootloader interface */
+ BootComInit();
+
+ /* start the infinite program loop */
+ while (1)
+ {
+ /* toggle LED with a fixed frequency */
+ LedToggle();
+ /* check for bootloader activation request */
+ BootComCheckActivationRequest();
+ }
+
+ /* program should never get here */
+ return 0;
+} /*** end of main ***/
+
+
+/****************************************************************************************
+** NAME: Init
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the microcontroller.
+**
+****************************************************************************************/
+static void Init(void)
+{
+ /* set the clocking to run at 50MHz from the PLL */
+ SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_8MHZ);
+ /* init the led driver */
+ LedInit();
+ /* init the timer driver */
+ TimeInit();
+ /* enable IRQ's, because they were initially disabled by the bootloader */
+ IrqInterruptEnable();
+} /*** end of Init ***/
+
+
+/****************************************************************************************
+** NAME: __error__
+** PARAMETER: pcFilename name of the source file where the assertion occurred.
+** ulLine linenumber in the source file where the assertion occurred.
+** RETURN VALUE: none
+** DESCRIPTION: Called when a runtime assertion failed. It stores information about
+** where the assertion occurred and halts the software program.
+**
+****************************************************************************************/
+#ifdef DEBUG
+void __error__(char *pcFilename, unsigned long ulLine)
+{
+ static volatile char *assert_failure_file;
+ static volatile unsigned long assert_failure_line;
+
+ /* store the file string and line number so that it can be read on a breakpoint*/
+ assert_failure_file = pcFilename;
+ assert_failure_line = ulLine;
+
+ /* hang the software so that it requires a hard reset */
+ for(;;)
+ {
+ }
+} /*** end of __error__ ***/
+#endif
+
+
+/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/memory.x b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/memory.x
new file mode 100644
index 00000000..b42de017
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/memory.x
@@ -0,0 +1,281 @@
+MEMORY
+{
+ UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0
+ CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000
+ Peripherals (wx) : ORIGIN = 0x40020000, LENGTH = 0x00100000
+ FiRM_Peripherals (wx) : ORIGIN = 0x40000000, LENGTH = 0x00010000
+ SRAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00010000
+ FLASH (rx) : ORIGIN = 0x00004000, LENGTH = 0x00040000 - 0x4000
+}
+
+
+SECTIONS
+{
+ __CM3_System_Control_Space_segment_start__ = 0xe000e000;
+ __CM3_System_Control_Space_segment_end__ = 0xe000f000;
+ __Peripherals_segment_start__ = 0x40020000;
+ __Peripherals_segment_end__ = 0x40120000;
+ __FiRM_Peripherals_segment_start__ = 0x40000000;
+ __FiRM_Peripherals_segment_end__ = 0x40010000;
+ __SRAM_segment_start__ = 0x20000000;
+ __SRAM_segment_end__ = 0x20010000;
+ __FLASH_segment_start__ = 0x00004000;
+ __FLASH_segment_end__ = 0x00040000;
+
+ __STACKSIZE__ = 256;
+ __STACKSIZE_PROCESS__ = 0;
+ __STACKSIZE_IRQ__ = 0;
+ __STACKSIZE_FIQ__ = 0;
+ __STACKSIZE_SVC__ = 0;
+ __STACKSIZE_ABT__ = 0;
+ __STACKSIZE_UND__ = 0;
+ __HEAPSIZE__ = 128;
+
+ __vectors_ram_load_start__ = ALIGN(__SRAM_segment_start__ , 256);
+ .vectors_ram ALIGN(__SRAM_segment_start__ , 256) (NOLOAD) : AT(ALIGN(__SRAM_segment_start__ , 256))
+ {
+ __vectors_ram_start__ = .;
+ *(.vectors_ram .vectors_ram.*)
+ }
+ __vectors_ram_end__ = __vectors_ram_start__ + SIZEOF(.vectors_ram);
+
+ __vectors_ram_load_end__ = __vectors_ram_end__;
+
+ . = ASSERT(__vectors_ram_end__ >= __SRAM_segment_start__ && __vectors_ram_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .vectors_ram is too large to fit in SRAM memory segment");
+
+ __vectors_load_start__ = ALIGN(__FLASH_segment_start__ , 256);
+ .vectors ALIGN(__FLASH_segment_start__ , 256) : AT(ALIGN(__FLASH_segment_start__ , 256))
+ {
+ __vectors_start__ = .;
+ *(.vectors .vectors.*)
+ }
+ __vectors_end__ = __vectors_start__ + SIZEOF(.vectors);
+
+ __vectors_load_end__ = __vectors_end__;
+
+ . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .vectors is too large to fit in FLASH memory segment");
+
+ __init_load_start__ = ALIGN(__vectors_end__ , 4);
+ .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4))
+ {
+ __init_start__ = .;
+ *(.init .init.*)
+ }
+ __init_end__ = __init_start__ + SIZEOF(.init);
+
+ __init_load_end__ = __init_end__;
+
+ . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .init is too large to fit in FLASH memory segment");
+
+ __text_load_start__ = ALIGN(__init_end__ , 4);
+ .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4))
+ {
+ __text_start__ = .;
+ *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*)
+ }
+ __text_end__ = __text_start__ + SIZEOF(.text);
+
+ __text_load_end__ = __text_end__;
+
+ . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .text is too large to fit in FLASH memory segment");
+
+ __dtors_load_start__ = ALIGN(__text_end__ , 4);
+ .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4))
+ {
+ __dtors_start__ = .;
+ KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) KEEP (*(.fini_array .fini_array.*))
+ }
+ __dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
+
+ __dtors_load_end__ = __dtors_end__;
+
+ . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .dtors is too large to fit in FLASH memory segment");
+
+ __ctors_load_start__ = ALIGN(__dtors_end__ , 4);
+ .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
+ {
+ __ctors_start__ = .;
+ KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) KEEP (*(.init_array .init_array.*))
+ }
+ __ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
+
+ __ctors_load_end__ = __ctors_end__;
+
+ . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .ctors is too large to fit in FLASH memory segment");
+
+ __rodata_load_start__ = ALIGN(__ctors_end__ , 4);
+ .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
+ {
+ __rodata_start__ = .;
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ }
+ __rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
+
+ __rodata_load_end__ = __rodata_end__;
+
+ . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .rodata is too large to fit in FLASH memory segment");
+
+ __ARM.exidx_load_start__ = ALIGN(__rodata_end__ , 4);
+ .ARM.exidx ALIGN(__rodata_end__ , 4) : AT(ALIGN(__rodata_end__ , 4))
+ {
+ __ARM.exidx_start__ = .;
+ __exidx_start = __ARM.exidx_start__;
+ *(.ARM.exidx .ARM.exidx.*)
+ }
+ __ARM.exidx_end__ = __ARM.exidx_start__ + SIZEOF(.ARM.exidx);
+
+ __exidx_end = __ARM.exidx_end__;
+ __ARM.exidx_load_end__ = __ARM.exidx_end__;
+
+ . = ASSERT(__ARM.exidx_end__ >= __FLASH_segment_start__ && __ARM.exidx_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .ARM.exidx is too large to fit in FLASH memory segment");
+
+ __fast_load_start__ = ALIGN(__ARM.exidx_end__ , 4);
+ .fast ALIGN(__vectors_ram_end__ , 4) : AT(ALIGN(__ARM.exidx_end__ , 4))
+ {
+ __fast_start__ = .;
+ *(.fast .fast.*)
+ }
+ __fast_end__ = __fast_start__ + SIZEOF(.fast);
+
+ __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
+
+ . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .fast is too large to fit in FLASH memory segment");
+
+ .fast_run ALIGN(__vectors_ram_end__ , 4) (NOLOAD) :
+ {
+ __fast_run_start__ = .;
+ . = MAX(__fast_run_start__ + SIZEOF(.fast), .);
+ }
+ __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
+
+ __fast_run_load_end__ = __fast_run_end__;
+
+ . = ASSERT(__fast_run_end__ >= __SRAM_segment_start__ && __fast_run_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .fast_run is too large to fit in SRAM memory segment");
+
+ __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4);
+ .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4))
+ {
+ __data_start__ = .;
+ *(.data .data.* .gnu.linkonce.d.*)
+ }
+ __data_end__ = __data_start__ + SIZEOF(.data);
+
+ __data_load_end__ = __data_load_start__ + SIZEOF(.data);
+
+ . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .data is too large to fit in FLASH memory segment");
+
+ .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) :
+ {
+ __data_run_start__ = .;
+ . = MAX(__data_run_start__ + SIZEOF(.data), .);
+ }
+ __data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
+
+ __data_run_load_end__ = __data_run_end__;
+
+ . = ASSERT(__data_run_end__ >= __SRAM_segment_start__ && __data_run_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .data_run is too large to fit in SRAM memory segment");
+
+ __bss_load_start__ = ALIGN(__data_run_end__ , 4);
+ .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
+ {
+ __bss_start__ = .;
+ *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
+ }
+ __bss_end__ = __bss_start__ + SIZEOF(.bss);
+
+ __bss_load_end__ = __bss_end__;
+
+ . = ASSERT(__bss_end__ >= __SRAM_segment_start__ && __bss_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .bss is too large to fit in SRAM memory segment");
+
+ __non_init_load_start__ = ALIGN(__bss_end__ , 4);
+ .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
+ {
+ __non_init_start__ = .;
+ *(.non_init .non_init.*)
+ }
+ __non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
+
+ __non_init_load_end__ = __non_init_end__;
+
+ . = ASSERT(__non_init_end__ >= __SRAM_segment_start__ && __non_init_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .non_init is too large to fit in SRAM memory segment");
+
+ __heap_load_start__ = ALIGN(__non_init_end__ , 4);
+ .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
+ {
+ __heap_start__ = .;
+ *(.heap .heap.*)
+ . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
+ }
+ __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+ __heap_load_end__ = __heap_end__;
+
+ . = ASSERT(__heap_end__ >= __SRAM_segment_start__ && __heap_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .heap is too large to fit in SRAM memory segment");
+
+ __stack_load_start__ = ALIGN(__heap_end__ , 4);
+ .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4))
+ {
+ __stack_start__ = .;
+ *(.stack .stack.*)
+ . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4);
+ }
+ __stack_end__ = __stack_start__ + SIZEOF(.stack);
+
+ __stack_load_end__ = __stack_end__;
+
+ . = ASSERT(__stack_end__ >= __SRAM_segment_start__ && __stack_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .stack is too large to fit in SRAM memory segment");
+
+ __stack_process_load_start__ = ALIGN(__stack_end__ , 4);
+ .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4))
+ {
+ __stack_process_start__ = .;
+ *(.stack_process .stack_process.*)
+ . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4);
+ }
+ __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process);
+
+ __stack_process_load_end__ = __stack_process_end__;
+
+ . = ASSERT(__stack_process_end__ >= __SRAM_segment_start__ && __stack_process_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .stack_process is too large to fit in SRAM memory segment");
+
+ __tbss_load_start__ = ALIGN(__stack_process_end__ , 4);
+ .tbss ALIGN(__stack_process_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_process_end__ , 4))
+ {
+ __tbss_start__ = .;
+ *(.tbss .tbss.*)
+ }
+ __tbss_end__ = __tbss_start__ + SIZEOF(.tbss);
+
+ __tbss_load_end__ = __tbss_end__;
+
+ . = ASSERT(__tbss_end__ >= __SRAM_segment_start__ && __tbss_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .tbss is too large to fit in SRAM memory segment");
+
+ __tdata_load_start__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4);
+ .tdata ALIGN(__tbss_end__ , 4) : AT(ALIGN(__data_load_start__ + SIZEOF(.data) , 4))
+ {
+ __tdata_start__ = .;
+ *(.tdata .tdata.*)
+ }
+ __tdata_end__ = __tdata_start__ + SIZEOF(.tdata);
+
+ __tdata_load_end__ = __tdata_load_start__ + SIZEOF(.tdata);
+
+ __FLASH_segment_used_end__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4) + SIZEOF(.tdata);
+
+ . = ASSERT((__tdata_load_start__ + SIZEOF(.tdata)) >= __FLASH_segment_start__ && (__tdata_load_start__ + SIZEOF(.tdata)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .tdata is too large to fit in FLASH memory segment");
+
+ .tdata_run ALIGN(__tbss_end__ , 4) (NOLOAD) :
+ {
+ __tdata_run_start__ = .;
+ . = MAX(__tdata_run_start__ + SIZEOF(.tdata), .);
+ }
+ __tdata_run_end__ = __tdata_run_start__ + SIZEOF(.tdata_run);
+
+ __tdata_run_load_end__ = __tdata_run_end__;
+
+ __SRAM_segment_used_end__ = ALIGN(__tbss_end__ , 4) + SIZEOF(.tdata_run);
+
+ . = ASSERT(__tdata_run_end__ >= __SRAM_segment_start__ && __tdata_run_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .tdata_run is too large to fit in SRAM memory segment");
+
+}
+
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/time.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/time.c
new file mode 100644
index 00000000..ef3e5bd2
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/time.c
@@ -0,0 +1,118 @@
+/****************************************************************************************
+| Description: Timer driver source file
+| File Name: time.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h" /* generic header */
+
+
+/****************************************************************************************
+* Local data declarations
+****************************************************************************************/
+static unsigned long millisecond_counter;
+
+
+/****************************************************************************************
+** NAME: TimeInit
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the timer.
+**
+****************************************************************************************/
+void TimeInit(void)
+{
+ /* configure the SysTick timer for 1 ms period */
+ SysTickPeriodSet((unsigned long)SysCtlClockGet() / 1000);
+ SysTickEnable();
+ SysTickIntEnable();
+ /* reset the millisecond counter */
+ TimeSet(0);
+} /*** end of TimeInit ***/
+
+
+/****************************************************************************************
+** NAME: TimeDeinit
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Stops and disables the timer.
+**
+****************************************************************************************/
+void TimeDeinit(void)
+{
+ SysTickIntDisable();
+ SysTickDisable();
+} /*** end of TimeDeinit ***/
+
+
+/****************************************************************************************
+** NAME: TimeSet
+** PARAMETER: timer_value initialize value of the millisecond timer.
+** RETURN VALUE: none
+** DESCRIPTION: Sets the initial counter value of the millisecond timer.
+**
+****************************************************************************************/
+void TimeSet(unsigned long timer_value)
+{
+ /* set the millisecond counter */
+ millisecond_counter = timer_value;
+} /*** end of TimeSet ***/
+
+
+/****************************************************************************************
+** NAME: TimeGet
+** PARAMETER: none
+** RETURN VALUE: current value of the millisecond timer
+** DESCRIPTION: Obtains the counter value of the millisecond timer.
+**
+****************************************************************************************/
+unsigned long TimeGet(void)
+{
+ /* read and return the millisecond counter value */
+ return millisecond_counter;
+} /*** end of TimeGet ***/
+
+
+/****************************************************************************************
+** NAME: TimeISRHandler
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Interrupt service routine of the timer.
+**
+****************************************************************************************/
+void TimeISRHandler(void)
+{
+ /* increment the millisecond counter */
+ millisecond_counter++;
+} /*** end of TimeISRHandler ***/
+
+
+/*********************************** end of time.c *************************************/
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/time.h b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/time.h
new file mode 100644
index 00000000..a01f7e58
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/time.h
@@ -0,0 +1,44 @@
+/****************************************************************************************
+| Description: Timer driver header file
+| File Name: time.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef TIME_H
+#define TIME_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void TimeInit(void);
+void TimeDeinit(void);
+void TimeSet(unsigned long timer_value);
+unsigned long TimeGet(void);
+void TimeISRHandler(void);
+
+#endif /* TIME_H */
+/*********************************** end of time.h *************************************/
diff --git a/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/vectors.c b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/vectors.c
new file mode 100644
index 00000000..494467ab
--- /dev/null
+++ b/Target/Demo/ARMCM3_LM3S_EK_LM3S6965_Crossworks/Prog/vectors.c
@@ -0,0 +1,142 @@
+/****************************************************************************************
+| Description: bootloader interrupt vector table source file
+| File Name: vectors.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h" /* generic header */
+
+
+/****************************************************************************************
+* External functions
+****************************************************************************************/
+extern void reset_handler(void); /* implemented in cstart.s */
+
+
+/****************************************************************************************
+* External data declarations
+****************************************************************************************/
+extern unsigned long __stack_end__; /* stack end address (memory.x) */
+
+
+/****************************************************************************************
+** NAME: UnusedISR
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Catch-all for unused interrrupt service routines.
+**
+****************************************************************************************/
+void UnusedISR(void)
+{
+ /* unexpected interrupt occured, so halt the system */
+ while (1) { ; }
+} /*** end of UnusedISR ***/
+
+
+/****************************************************************************************
+* I N T E R R U P T V E C T O R T A B L E
+****************************************************************************************/
+typedef union
+{
+ void (*func)(void); /* for ISR function pointers */
+ unsigned long ptr; /* for stack pointer entry */
+}tIsrFunc; /* type for vector table entries */
+
+__attribute__ ((section(".vectors")))
+const tIsrFunc _vectors[] =
+{
+ { .ptr = (unsigned long)&__stack_end__ }, /* the initial stack pointer */
+ { reset_handler }, /* the reset handler */
+ { UnusedISR }, /* NMI Handler */
+ { UnusedISR }, /* Hard Fault Handler */
+ { UnusedISR }, /* MPU Fault Handler */
+ { UnusedISR }, /* Bus Fault Handler */
+ { UnusedISR }, /* Usage Fault Handler */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* SVCall Handler */
+ { UnusedISR }, /* Debug Monitor Handler */
+ { UnusedISR }, /* Reserved */
+ { UnusedISR }, /* PendSV Handler */
+ { TimeISRHandler }, /* SysTick Handler */
+ { UnusedISR }, /* GPIO Port A */
+ { UnusedISR }, /* GPIO Port B */
+ { UnusedISR }, /* GPIO Port C */
+ { UnusedISR }, /* GPIO Port D */
+ { UnusedISR }, /* GPIO Port E */
+ { UnusedISR }, /* UART0 Rx and Tx */
+ { UnusedISR }, /* UART1 Rx and Tx */
+ { UnusedISR }, /* SSI Rx and Tx */
+ { UnusedISR }, /* I2C Master and Slave */
+ { UnusedISR }, /* PWM Fault */
+ { UnusedISR }, /* PWM Generator 0 */
+ { UnusedISR }, /* PWM Generator 1 */
+ { UnusedISR }, /* PWM Generator 2 */
+ { UnusedISR }, /* Quadrature Encoder */
+ { UnusedISR }, /* ADC Sequence 0 */
+ { UnusedISR }, /* ADC Sequence 1 */
+ { UnusedISR }, /* ADC Sequence 2 */
+ { UnusedISR }, /* ADC Sequence 3 */
+ { UnusedISR }, /* Watchdog timer */
+ { UnusedISR }, /* Timer 0 subtimer A */
+ { UnusedISR }, /* Timer 0 subtimer B */
+ { UnusedISR }, /* Timer 1 subtimer A */
+ { UnusedISR }, /* Timer 1 subtimer B */
+ { UnusedISR }, /* Timer 2 subtimer A */
+ { UnusedISR }, /* Timer 2 subtimer B */
+ { UnusedISR }, /* Analog Comparator 0 */
+ { UnusedISR }, /* Analog Comparator 1 */
+ { UnusedISR }, /* Analog Comparator 2 */
+ { UnusedISR }, /* System Control (PLL, OSC, BO) */
+ { UnusedISR }, /* FLASH Control */
+ { UnusedISR }, /* GPIO Port F */
+ { UnusedISR }, /* GPIO Port G */
+ { UnusedISR }, /* GPIO Port H */
+ { UnusedISR }, /* UART2 Rx and Tx */
+ { UnusedISR }, /* SSI1 Rx and Tx */
+ { UnusedISR }, /* Timer 3 subtimer A */
+ { UnusedISR }, /* Timer 3 subtimer B */
+ { UnusedISR }, /* I2C1 Master and Slave */
+ { UnusedISR }, /* Quadrature Encoder 1 */
+ { UnusedISR }, /* CAN0 */
+ { UnusedISR }, /* CAN1 */
+ { UnusedISR }, /* CAN2 */
+ { UnusedISR }, /* Ethernet */
+ { UnusedISR }, /* Hibernate */
+ { (void*)0x55AA11EE } /* Reserved for OpenBLT checksum */
+};
+
+
+/************************************ end of hw.c **************************************/
+
+
diff --git a/Target/Source/ARMCM3_LM3S/Crossworks/cstart.s b/Target/Source/ARMCM3_LM3S/Crossworks/cstart.s
new file mode 100644
index 00000000..326f8c77
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/Crossworks/cstart.s
@@ -0,0 +1,434 @@
+/*****************************************************************************
+ * Copyright (c) 2009 Rowley Associates Limited. *
+ * *
+ * This file may be distributed under the terms of the License Agreement *
+ * provided with this software. *
+ * *
+ * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
+ *****************************************************************************/
+
+/*****************************************************************************
+ * Preprocessor Definitions
+ * ------------------------
+ * APP_ENTRY_POINT
+ *
+ * Defines the application entry point function, if undefined this setting
+ * defaults to "main".
+ *
+ * USE_PROCESS_STACK
+ *
+ * If defined, thread mode will be configured to use the process stack if
+ * the size of the process stack is greater than zero bytes in length.
+ *
+ * INITIALIZE_STACK
+ *
+ * If defined, the contents of the stack will be initialized to a the
+ * value 0xCC.
+ *
+ * INITIALIZE_SECONDARY_SECTIONS
+ *
+ * If defined, the .data2, .text2, .rodata2 and .bss2 sections will be initialized.
+ *
+ * FULL_LIBRARY
+ *
+ * If defined then
+ * - argc, argv are setup by the debug_getargs.
+ * - the exit symbol is defined and executes on return from main.
+ * - the exit symbol calls destructors, atexit functions and then debug_exit.
+ *
+ * If not defined then
+ * - argc and argv are zero.
+ * - the exit symbol is defined, executes on return from main and loops
+ *****************************************************************************/
+
+#ifndef APP_ENTRY_POINT
+#define APP_ENTRY_POINT main
+#endif
+
+#ifndef ARGSSPACE
+#define ARGSSPACE 128
+#endif
+
+ .extern APP_ENTRY_POINT
+ .global exit
+ .global reset_handler
+ .global EntryFromProg
+ .extern ComSetConnectEntryState
+
+ .section .init, "ax"
+ .code 16
+ .align 2
+
+ .thumb_func
+/****************************************************************************************
+** NAME: EntryFromProg
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Called by the user program to activate the bootloader. Do not place
+** any assembly code before this function and the end of the vector
+** table. This guarantees that this function is located at address
+** 0x08000150. The user program can call this function from C in the
+** following way:
+** void ActivateBootloader(void)
+** {
+** void (*pEntryFromProgFnc)(void);
+**
+** pEntryFromProgFnc = (void*)0x08000150 + 1;
+** pEntryFromProgFnc();
+** }
+** Note that the + 1 added to the function address is neccassary to
+** enable a switch from Thumb2 to Thumb mode.
+**
+****************************************************************************************/
+EntryFromProg:
+ /* disable interrupts first */
+ cpsid i
+ /* configure vector table offset register to use bootloader's vector table*/
+ ldr r0, =0xE000ED08
+ ldr r1, =_vectors
+ str r1, [r0]
+ /* initialize stack pointer */
+ ldr r1, =__stack_end__
+#ifdef __ARM_EABI__
+ mov r2, #0x7
+ bic r1, r2
+#endif
+ mov sp, r1
+#ifdef INITIALIZE_STACK
+ mov r2, #0xCC
+ ldr r0, =__stack_start__
+ bl memory_set
+#endif
+
+#ifdef USE_PROCESS_STACK
+ /* Set up process stack if size > 0 */
+ ldr r1, =__stack_process_end__
+ ldr r0, =__stack_process_start__
+ sub r2, r1, r0
+ beq 1f
+#ifdef __ARM_EABI__
+ mov r2, #0x7
+ bic r1, r2
+#endif
+ msr psp, r1
+ mov r2, #2
+ msr control, r2
+#ifdef INITIALIZE_STACK
+ mov r2, #0xCC
+ bl memory_set
+#endif
+1:
+#endif
+ /* Copy initialised memory sections into RAM (if necessary). */
+ ldr r0, =__data_load_start__
+ ldr r1, =__data_start__
+ ldr r2, =__data_end__
+ bl memory_copy
+ ldr r0, =__text_load_start__
+ ldr r1, =__text_start__
+ ldr r2, =__text_end__
+ bl memory_copy
+ ldr r0, =__fast_load_start__
+ ldr r1, =__fast_start__
+ ldr r2, =__fast_end__
+ bl memory_copy
+ ldr r0, =__ctors_load_start__
+ ldr r1, =__ctors_start__
+ ldr r2, =__ctors_end__
+ bl memory_copy
+ ldr r0, =__dtors_load_start__
+ ldr r1, =__dtors_start__
+ ldr r2, =__dtors_end__
+ bl memory_copy
+ ldr r0, =__rodata_load_start__
+ ldr r1, =__rodata_start__
+ ldr r2, =__rodata_end__
+ bl memory_copy
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+ ldr r0, =__data2_load_start__
+ ldr r1, =__data2_start__
+ ldr r2, =__data2_end__
+ bl memory_copy
+ ldr r0, =__text2_load_start__
+ ldr r1, =__text2_start__
+ ldr r2, =__text2_end__
+ bl memory_copy
+ ldr r0, =__rodata2_load_start__
+ ldr r1, =__rodata2_start__
+ ldr r2, =__rodata2_end__
+ bl memory_copy
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+
+ /* Zero the bss. */
+ ldr r0, =__bss_start__
+ ldr r1, =__bss_end__
+ mov r2, #0
+ bl memory_set
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+ ldr r0, =__bss2_start__
+ ldr r1, =__bss2_end__
+ mov r2, #0
+ bl memory_set
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+
+ /* Initialise the heap */
+ ldr r0, = __heap_start__
+ ldr r1, = __heap_end__
+ sub r1, r1, r0
+ cmp r1, #8
+ blt 1f
+ mov r2, #0
+ str r2, [r0]
+ add r0, r0, #4
+ str r1, [r0]
+1:
+
+ /* Call constructors */
+ ldr r0, =__ctors_start__
+ ldr r1, =__ctors_end__
+ctor_loop:
+ cmp r0, r1
+ beq ctor_end
+ ldr r2, [r0]
+ add r0, #4
+ push {r0-r1}
+ blx r2
+ pop {r0-r1}
+ b ctor_loop
+ctor_end:
+
+ /* Setup initial call frame */
+ mov r0, #0
+ mov lr, r0
+ mov r12, sp
+
+start:
+ /* this part makes the difference with the normal reset_handler */
+ bl ComSetConnectEntryState
+ /* Jump to application entry point */
+#ifdef FULL_LIBRARY
+ mov r0, #ARGSSPACE
+ ldr r1, =args
+ ldr r2, =debug_getargs
+ blx r2
+ ldr r1, =args
+#else
+ mov r0, #0
+ mov r1, #0
+#endif
+ ldr r2, =APP_ENTRY_POINT
+ blx r2
+
+ .thumb_func
+/****************************************************************************************
+** NAME: reset_handler
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Reset interrupt service routine. Configures the stack, initializes
+** RAM and jumps to function main.
+**
+****************************************************************************************/
+reset_handler:
+ /* disable interrupts first */
+ cpsid i
+ ldr r1, =__stack_end__
+#ifdef __ARM_EABI__
+ mov r2, #0x7
+ bic r1, r2
+#endif
+ mov sp, r1
+#ifdef INITIALIZE_STACK
+ mov r2, #0xCC
+ ldr r0, =__stack_start__
+ bl memory_set
+#endif
+
+#ifdef USE_PROCESS_STACK
+ /* Set up process stack if size > 0 */
+ ldr r1, =__stack_process_end__
+ ldr r0, =__stack_process_start__
+ sub r2, r1, r0
+ beq 1f
+#ifdef __ARM_EABI__
+ mov r2, #0x7
+ bic r1, r2
+#endif
+ msr psp, r1
+ mov r2, #2
+ msr control, r2
+#ifdef INITIALIZE_STACK
+ mov r2, #0xCC
+ bl memory_set
+#endif
+1:
+#endif
+ /* Copy initialised memory sections into RAM (if necessary). */
+ ldr r0, =__data_load_start__
+ ldr r1, =__data_start__
+ ldr r2, =__data_end__
+ bl memory_copy
+ ldr r0, =__text_load_start__
+ ldr r1, =__text_start__
+ ldr r2, =__text_end__
+ bl memory_copy
+ ldr r0, =__fast_load_start__
+ ldr r1, =__fast_start__
+ ldr r2, =__fast_end__
+ bl memory_copy
+ ldr r0, =__ctors_load_start__
+ ldr r1, =__ctors_start__
+ ldr r2, =__ctors_end__
+ bl memory_copy
+ ldr r0, =__dtors_load_start__
+ ldr r1, =__dtors_start__
+ ldr r2, =__dtors_end__
+ bl memory_copy
+ ldr r0, =__rodata_load_start__
+ ldr r1, =__rodata_start__
+ ldr r2, =__rodata_end__
+ bl memory_copy
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+ ldr r0, =__data2_load_start__
+ ldr r1, =__data2_start__
+ ldr r2, =__data2_end__
+ bl memory_copy
+ ldr r0, =__text2_load_start__
+ ldr r1, =__text2_start__
+ ldr r2, =__text2_end__
+ bl memory_copy
+ ldr r0, =__rodata2_load_start__
+ ldr r1, =__rodata2_start__
+ ldr r2, =__rodata2_end__
+ bl memory_copy
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+
+ /* Zero the bss. */
+ ldr r0, =__bss_start__
+ ldr r1, =__bss_end__
+ mov r2, #0
+ bl memory_set
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+ ldr r0, =__bss2_start__
+ ldr r1, =__bss2_end__
+ mov r2, #0
+ bl memory_set
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+
+ /* Initialise the heap */
+ ldr r0, = __heap_start__
+ ldr r1, = __heap_end__
+ sub r1, r1, r0
+ cmp r1, #8
+ blt 1f
+ mov r2, #0
+ str r2, [r0]
+ add r0, r0, #4
+ str r1, [r0]
+1:
+
+ /* Call constructors */
+ ldr r0, =__ctors_start__
+ ldr r1, =__ctors_end__
+ctor_loop2:
+ cmp r0, r1
+ beq ctor_end2
+ ldr r2, [r0]
+ add r0, #4
+ push {r0-r1}
+ blx r2
+ pop {r0-r1}
+ b ctor_loop2
+ctor_end2:
+
+ /* Setup initial call frame */
+ mov r0, #0
+ mov lr, r0
+ mov r12, sp
+
+start2:
+ /* Jump to application entry point */
+#ifdef FULL_LIBRARY
+ mov r0, #ARGSSPACE
+ ldr r1, =args
+ ldr r2, =debug_getargs
+ blx r2
+ ldr r1, =args
+#else
+ mov r0, #0
+ mov r1, #0
+#endif
+ ldr r2, =APP_ENTRY_POINT
+ blx r2
+
+ .thumb_func
+exit:
+#ifdef FULL_LIBRARY
+ mov r5, r0 // save the exit parameter/return result
+
+ /* Call destructors */
+ ldr r0, =__dtors_start__
+ ldr r1, =__dtors_end__
+dtor_loop:
+ cmp r0, r1
+ beq dtor_end
+ ldr r2, [r0]
+ add r0, #4
+ push {r0-r1}
+ blx r2
+ pop {r0-r1}
+ b dtor_loop
+dtor_end:
+
+ /* Call atexit functions */
+ ldr r2, =_execute_at_exit_fns
+ blx r2
+
+ /* Call debug_exit with return result/exit parameter */
+ mov r0, r5
+ ldr r2, =debug_exit
+ blx r2
+#endif
+
+ /* Returned from application entry point, loop forever. */
+exit_loop:
+ b exit_loop
+
+ .thumb_func
+memory_copy:
+ cmp r0, r1
+ beq 2f
+ sub r2, r2, r1
+ beq 2f
+1:
+ ldrb r3, [r0]
+ add r0, r0, #1
+ strb r3, [r1]
+ add r1, r1, #1
+ sub r2, r2, #1
+ bne 1b
+2:
+ bx lr
+
+ .thumb_func
+memory_set:
+ cmp r0, r1
+ beq 1f
+ strb r2, [r0]
+ add r0, r0, #1
+ b memory_set
+1:
+ bx lr
+
+
+#ifdef FULL_LIBRARY
+ .bss
+args:
+ .space ARGSSPACE
+#endif
+
+ /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
+ .section .stack, "wa", %nobits
+ .section .stack_process, "wa", %nobits
+ .section .heap, "wa", %nobits
+
diff --git a/Target/Source/ARMCM3_LM3S/Crossworks/memory.x b/Target/Source/ARMCM3_LM3S/Crossworks/memory.x
new file mode 100644
index 00000000..10672fa0
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/Crossworks/memory.x
@@ -0,0 +1,281 @@
+MEMORY
+{
+ UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0
+ CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000
+ Peripherals (wx) : ORIGIN = 0x40020000, LENGTH = 0x00100000
+ FiRM_Peripherals (wx) : ORIGIN = 0x40000000, LENGTH = 0x00010000
+ SRAM (wx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00004000
+}
+
+
+SECTIONS
+{
+ __CM3_System_Control_Space_segment_start__ = 0xe000e000;
+ __CM3_System_Control_Space_segment_end__ = 0xe000f000;
+ __Peripherals_segment_start__ = 0x40020000;
+ __Peripherals_segment_end__ = 0x40120000;
+ __FiRM_Peripherals_segment_start__ = 0x40000000;
+ __FiRM_Peripherals_segment_end__ = 0x40010000;
+ __SRAM_segment_start__ = 0x20000000;
+ __SRAM_segment_end__ = 0x20001000;
+ __FLASH_segment_start__ = 0x00000000;
+ __FLASH_segment_end__ = 0x00004000;
+
+ __STACKSIZE__ = 256;
+ __STACKSIZE_PROCESS__ = 0;
+ __STACKSIZE_IRQ__ = 0;
+ __STACKSIZE_FIQ__ = 0;
+ __STACKSIZE_SVC__ = 0;
+ __STACKSIZE_ABT__ = 0;
+ __STACKSIZE_UND__ = 0;
+ __HEAPSIZE__ = 128;
+
+ __vectors_ram_load_start__ = ALIGN(__SRAM_segment_start__ , 256);
+ .vectors_ram ALIGN(__SRAM_segment_start__ , 256) (NOLOAD) : AT(ALIGN(__SRAM_segment_start__ , 256))
+ {
+ __vectors_ram_start__ = .;
+ *(.vectors_ram .vectors_ram.*)
+ }
+ __vectors_ram_end__ = __vectors_ram_start__ + SIZEOF(.vectors_ram);
+
+ __vectors_ram_load_end__ = __vectors_ram_end__;
+
+ . = ASSERT(__vectors_ram_end__ >= __SRAM_segment_start__ && __vectors_ram_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .vectors_ram is too large to fit in SRAM memory segment");
+
+ __vectors_load_start__ = ALIGN(__FLASH_segment_start__ , 256);
+ .vectors ALIGN(__FLASH_segment_start__ , 256) : AT(ALIGN(__FLASH_segment_start__ , 256))
+ {
+ __vectors_start__ = .;
+ *(.vectors .vectors.*)
+ }
+ __vectors_end__ = __vectors_start__ + SIZEOF(.vectors);
+
+ __vectors_load_end__ = __vectors_end__;
+
+ . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .vectors is too large to fit in FLASH memory segment");
+
+ __init_load_start__ = ALIGN(__vectors_end__ , 4);
+ .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4))
+ {
+ __init_start__ = .;
+ *(.init .init.*)
+ }
+ __init_end__ = __init_start__ + SIZEOF(.init);
+
+ __init_load_end__ = __init_end__;
+
+ . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .init is too large to fit in FLASH memory segment");
+
+ __text_load_start__ = ALIGN(__init_end__ , 4);
+ .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4))
+ {
+ __text_start__ = .;
+ *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table .ARM.extab* .gnu.linkonce.armextab.*)
+ }
+ __text_end__ = __text_start__ + SIZEOF(.text);
+
+ __text_load_end__ = __text_end__;
+
+ . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .text is too large to fit in FLASH memory segment");
+
+ __dtors_load_start__ = ALIGN(__text_end__ , 4);
+ .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4))
+ {
+ __dtors_start__ = .;
+ KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) KEEP (*(.fini_array .fini_array.*))
+ }
+ __dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
+
+ __dtors_load_end__ = __dtors_end__;
+
+ . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .dtors is too large to fit in FLASH memory segment");
+
+ __ctors_load_start__ = ALIGN(__dtors_end__ , 4);
+ .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
+ {
+ __ctors_start__ = .;
+ KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) KEEP (*(.init_array .init_array.*))
+ }
+ __ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
+
+ __ctors_load_end__ = __ctors_end__;
+
+ . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .ctors is too large to fit in FLASH memory segment");
+
+ __rodata_load_start__ = ALIGN(__ctors_end__ , 4);
+ .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
+ {
+ __rodata_start__ = .;
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ }
+ __rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
+
+ __rodata_load_end__ = __rodata_end__;
+
+ . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .rodata is too large to fit in FLASH memory segment");
+
+ __ARM.exidx_load_start__ = ALIGN(__rodata_end__ , 4);
+ .ARM.exidx ALIGN(__rodata_end__ , 4) : AT(ALIGN(__rodata_end__ , 4))
+ {
+ __ARM.exidx_start__ = .;
+ __exidx_start = __ARM.exidx_start__;
+ *(.ARM.exidx .ARM.exidx.*)
+ }
+ __ARM.exidx_end__ = __ARM.exidx_start__ + SIZEOF(.ARM.exidx);
+
+ __exidx_end = __ARM.exidx_end__;
+ __ARM.exidx_load_end__ = __ARM.exidx_end__;
+
+ . = ASSERT(__ARM.exidx_end__ >= __FLASH_segment_start__ && __ARM.exidx_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .ARM.exidx is too large to fit in FLASH memory segment");
+
+ __fast_load_start__ = ALIGN(__ARM.exidx_end__ , 4);
+ .fast ALIGN(__vectors_ram_end__ , 4) : AT(ALIGN(__ARM.exidx_end__ , 4))
+ {
+ __fast_start__ = .;
+ *(.fast .fast.*)
+ }
+ __fast_end__ = __fast_start__ + SIZEOF(.fast);
+
+ __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
+
+ . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .fast is too large to fit in FLASH memory segment");
+
+ .fast_run ALIGN(__vectors_ram_end__ , 4) (NOLOAD) :
+ {
+ __fast_run_start__ = .;
+ . = MAX(__fast_run_start__ + SIZEOF(.fast), .);
+ }
+ __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
+
+ __fast_run_load_end__ = __fast_run_end__;
+
+ . = ASSERT(__fast_run_end__ >= __SRAM_segment_start__ && __fast_run_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .fast_run is too large to fit in SRAM memory segment");
+
+ __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4);
+ .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4))
+ {
+ __data_start__ = .;
+ *(.data .data.* .gnu.linkonce.d.*)
+ }
+ __data_end__ = __data_start__ + SIZEOF(.data);
+
+ __data_load_end__ = __data_load_start__ + SIZEOF(.data);
+
+ . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .data is too large to fit in FLASH memory segment");
+
+ .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) :
+ {
+ __data_run_start__ = .;
+ . = MAX(__data_run_start__ + SIZEOF(.data), .);
+ }
+ __data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
+
+ __data_run_load_end__ = __data_run_end__;
+
+ . = ASSERT(__data_run_end__ >= __SRAM_segment_start__ && __data_run_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .data_run is too large to fit in SRAM memory segment");
+
+ __bss_load_start__ = ALIGN(__data_run_end__ , 4);
+ .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
+ {
+ __bss_start__ = .;
+ *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
+ }
+ __bss_end__ = __bss_start__ + SIZEOF(.bss);
+
+ __bss_load_end__ = __bss_end__;
+
+ . = ASSERT(__bss_end__ >= __SRAM_segment_start__ && __bss_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .bss is too large to fit in SRAM memory segment");
+
+ __non_init_load_start__ = ALIGN(__bss_end__ , 4);
+ .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
+ {
+ __non_init_start__ = .;
+ *(.non_init .non_init.*)
+ }
+ __non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
+
+ __non_init_load_end__ = __non_init_end__;
+
+ . = ASSERT(__non_init_end__ >= __SRAM_segment_start__ && __non_init_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .non_init is too large to fit in SRAM memory segment");
+
+ __heap_load_start__ = ALIGN(__non_init_end__ , 4);
+ .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
+ {
+ __heap_start__ = .;
+ *(.heap .heap.*)
+ . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
+ }
+ __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+ __heap_load_end__ = __heap_end__;
+
+ . = ASSERT(__heap_end__ >= __SRAM_segment_start__ && __heap_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .heap is too large to fit in SRAM memory segment");
+
+ __stack_load_start__ = ALIGN(__heap_end__ , 4);
+ .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4))
+ {
+ __stack_start__ = .;
+ *(.stack .stack.*)
+ . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4);
+ }
+ __stack_end__ = __stack_start__ + SIZEOF(.stack);
+
+ __stack_load_end__ = __stack_end__;
+
+ . = ASSERT(__stack_end__ >= __SRAM_segment_start__ && __stack_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .stack is too large to fit in SRAM memory segment");
+
+ __stack_process_load_start__ = ALIGN(__stack_end__ , 4);
+ .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4))
+ {
+ __stack_process_start__ = .;
+ *(.stack_process .stack_process.*)
+ . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4);
+ }
+ __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process);
+
+ __stack_process_load_end__ = __stack_process_end__;
+
+ . = ASSERT(__stack_process_end__ >= __SRAM_segment_start__ && __stack_process_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .stack_process is too large to fit in SRAM memory segment");
+
+ __tbss_load_start__ = ALIGN(__stack_process_end__ , 4);
+ .tbss ALIGN(__stack_process_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_process_end__ , 4))
+ {
+ __tbss_start__ = .;
+ *(.tbss .tbss.*)
+ }
+ __tbss_end__ = __tbss_start__ + SIZEOF(.tbss);
+
+ __tbss_load_end__ = __tbss_end__;
+
+ . = ASSERT(__tbss_end__ >= __SRAM_segment_start__ && __tbss_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .tbss is too large to fit in SRAM memory segment");
+
+ __tdata_load_start__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4);
+ .tdata ALIGN(__tbss_end__ , 4) : AT(ALIGN(__data_load_start__ + SIZEOF(.data) , 4))
+ {
+ __tdata_start__ = .;
+ *(.tdata .tdata.*)
+ }
+ __tdata_end__ = __tdata_start__ + SIZEOF(.tdata);
+
+ __tdata_load_end__ = __tdata_load_start__ + SIZEOF(.tdata);
+
+ __FLASH_segment_used_end__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4) + SIZEOF(.tdata);
+
+ . = ASSERT((__tdata_load_start__ + SIZEOF(.tdata)) >= __FLASH_segment_start__ && (__tdata_load_start__ + SIZEOF(.tdata)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .tdata is too large to fit in FLASH memory segment");
+
+ .tdata_run ALIGN(__tbss_end__ , 4) (NOLOAD) :
+ {
+ __tdata_run_start__ = .;
+ . = MAX(__tdata_run_start__ + SIZEOF(.tdata), .);
+ }
+ __tdata_run_end__ = __tdata_run_start__ + SIZEOF(.tdata_run);
+
+ __tdata_run_load_end__ = __tdata_run_end__;
+
+ __SRAM_segment_used_end__ = ALIGN(__tbss_end__ , 4) + SIZEOF(.tdata_run);
+
+ . = ASSERT(__tdata_run_end__ >= __SRAM_segment_start__ && __tdata_run_end__ <= (__SRAM_segment_start__ + 0x00010000) , "error: .tdata_run is too large to fit in SRAM memory segment");
+
+}
+
diff --git a/Target/Source/ARMCM3_LM3S/Crossworks/vectors.c b/Target/Source/ARMCM3_LM3S/Crossworks/vectors.c
new file mode 100644
index 00000000..08ab66a0
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/Crossworks/vectors.c
@@ -0,0 +1,141 @@
+/****************************************************************************************
+| Description: bootloader interrupt vector table source file
+| File Name: vectors.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h" /* bootloader generic header */
+
+
+/****************************************************************************************
+* External functions
+****************************************************************************************/
+extern void reset_handler(void); /* implemented in cstart.s */
+
+
+/****************************************************************************************
+* External data declarations
+****************************************************************************************/
+extern blt_int32u __stack_end__; /* stack end address (memory.x) */
+
+
+/****************************************************************************************
+** NAME: UnusedISR
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Catch-all for unused interrrupt service routines.
+**
+****************************************************************************************/
+void UnusedISR(void)
+{
+ /* unexpected interrupt occured, so trigger an assertion to halt the system */
+ ASSERT_RT(BLT_FALSE);
+} /*** end of UnusedISR ***/
+
+
+/****************************************************************************************
+* I N T E R R U P T V E C T O R T A B L E
+****************************************************************************************/
+typedef union
+{
+ void (*func)(void); /* for ISR function pointers */
+ blt_int32u ptr; /* for stack pointer entry */
+}tIsrFunc; /* type for vector table entries */
+
+__attribute__ ((section(".vectors")))
+const tIsrFunc _vectors[] =
+{
+ { .ptr = (blt_int32u)&__stack_end__ }, /* the initial stack pointer */
+ reset_handler, /* the reset handler */
+ UnusedISR, /* NMI Handler */
+ UnusedISR, /* Hard Fault Handler */
+ UnusedISR, /* MPU Fault Handler */
+ UnusedISR, /* Bus Fault Handler */
+ UnusedISR, /* Usage Fault Handler */
+ UnusedISR, /* Reserved */
+ UnusedISR, /* Reserved */
+ UnusedISR, /* Reserved */
+ UnusedISR, /* Reserved */
+ UnusedISR, /* SVCall Handler */
+ UnusedISR, /* Debug Monitor Handler */
+ UnusedISR, /* Reserved */
+ UnusedISR, /* PendSV Handler */
+ UnusedISR, /* SysTick Handler */
+ UnusedISR, /* GPIO Port A */
+ UnusedISR, /* GPIO Port B */
+ UnusedISR, /* GPIO Port C */
+ UnusedISR, /* GPIO Port D */
+ UnusedISR, /* GPIO Port E */
+ UnusedISR, /* UART0 Rx and Tx */
+ UnusedISR, /* UART1 Rx and Tx */
+ UnusedISR, /* SSI Rx and Tx */
+ UnusedISR, /* I2C Master and Slave */
+ UnusedISR, /* PWM Fault */
+ UnusedISR, /* PWM Generator 0 */
+ UnusedISR, /* PWM Generator 1 */
+ UnusedISR, /* PWM Generator 2 */
+ UnusedISR, /* Quadrature Encoder */
+ UnusedISR, /* ADC Sequence 0 */
+ UnusedISR, /* ADC Sequence 1 */
+ UnusedISR, /* ADC Sequence 2 */
+ UnusedISR, /* ADC Sequence 3 */
+ UnusedISR, /* Watchdog timer */
+ UnusedISR, /* Timer 0 subtimer A */
+ UnusedISR, /* Timer 0 subtimer B */
+ UnusedISR, /* Timer 1 subtimer A */
+ UnusedISR, /* Timer 1 subtimer B */
+ UnusedISR, /* Timer 2 subtimer A */
+ UnusedISR, /* Timer 2 subtimer B */
+ UnusedISR, /* Analog Comparator 0 */
+ UnusedISR, /* Analog Comparator 1 */
+ UnusedISR, /* Analog Comparator 2 */
+ UnusedISR, /* System Control (PLL, OSC, BO) */
+ UnusedISR, /* FLASH Control */
+ UnusedISR, /* GPIO Port F */
+ UnusedISR, /* GPIO Port G */
+ UnusedISR, /* GPIO Port H */
+ UnusedISR, /* UART2 Rx and Tx */
+ UnusedISR, /* SSI1 Rx and Tx */
+ UnusedISR, /* Timer 3 subtimer A */
+ UnusedISR, /* Timer 3 subtimer B */
+ UnusedISR, /* I2C1 Master and Slave */
+ UnusedISR, /* Quadrature Encoder 1 */
+ UnusedISR, /* CAN0 */
+ UnusedISR, /* CAN1 */
+ UnusedISR, /* CAN2 */
+ UnusedISR, /* Ethernet */
+ UnusedISR /* Hibernate */
+};
+
+
+/************************************ end of vectors.c *********************************/
+
+
diff --git a/Target/Source/ARMCM3_LM3S/cpu.c b/Target/Source/ARMCM3_LM3S/cpu.c
new file mode 100644
index 00000000..30c35b18
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/cpu.c
@@ -0,0 +1,133 @@
+/****************************************************************************************
+| Description: bootloader cpu module source file
+| File Name: cpu.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h" /* bootloader generic header */
+
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+#define CPU_USER_PROGRAM_STARTADDR_PTR ((blt_addr) 0x00004004)
+#define CPU_USER_PROGRAM_VECTABLE_OFFSET ((blt_int32u)0x00004000)
+
+
+/****************************************************************************************
+* Register definitions
+****************************************************************************************/
+/* vector table offset register */
+#define SCB_VTOR (*((volatile blt_int32u *) 0xE000ED08))
+
+
+/****************************************************************************************
+* External functions
+****************************************************************************************/
+extern void reset_handler(void); /* implemented in cstart.s */
+
+
+/****************************************************************************************
+** NAME: CpuStartUserProgram
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Starts the user program, if one is present. In this case this function
+** does not return.
+**
+****************************************************************************************/
+void CpuStartUserProgram(void)
+{
+ void (*pProgResetHandler)(void);
+
+ /* check if a user program is present by verifying the checksum */
+ if (NvmVerifyChecksum() == BLT_FALSE)
+ {
+ /* not a valid user program so it cannot be started */
+ return;
+ }
+ /* release the communication interface */
+ ComFree();
+ /* remap user program's vector table */
+ SCB_VTOR = CPU_USER_PROGRAM_VECTABLE_OFFSET & (blt_int32u)0x1FFFFF80;
+ /* set the address where the bootloader needs to jump to. this is the address of
+ * the 2nd entry in the user program's vector table. this address points to the
+ * user program's reset handler.
+ */
+ pProgResetHandler = (void(*)(void))(*((blt_addr*)CPU_USER_PROGRAM_STARTADDR_PTR));
+ /* start the user program by activating its reset interrupt service routine */
+ pProgResetHandler();
+} /*** end of CpuStartUserProgram ***/
+
+
+/****************************************************************************************
+** NAME: CpuMemCopy
+** PARAMETER: dest destination address for the data.
+** src source address of the data.
+** len length of the data in bytes.
+** RETURN VALUE: none
+** DESCRIPTION: Copies data from the source to the destination address.
+**
+****************************************************************************************/
+void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len)
+{
+ blt_int8u *from, *to;
+
+ /* set casted pointers */
+ from = (blt_int8u *)src;
+ to = (blt_int8u *)dest;
+
+ /* copy all bytes from source address to destination address */
+ while(len-- > 0)
+ {
+ /* store byte value from source to destination */
+ *to++ = *from++;
+ /* keep the watchdog happy */
+ CopService();
+ }
+} /*** end of CpuMemCopy ***/
+
+
+/****************************************************************************************
+** NAME: CpuReset
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Perform a soft reset of the microcontroller by starting from the reset
+** ISR.
+**
+****************************************************************************************/
+void CpuReset(void)
+{
+ /* perform a software reset by calling the reset ISR routine */
+ reset_handler();
+} /*** end of CpuReset ***/
+
+
+/*********************************** end of cpu.c **************************************/
diff --git a/Target/Source/ARMCM3_LM3S/cpu.h b/Target/Source/ARMCM3_LM3S/cpu.h
new file mode 100644
index 00000000..e8722991
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/cpu.h
@@ -0,0 +1,44 @@
+/****************************************************************************************
+| Description: bootloader cpu module header file
+| File Name: cpu.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef CPU_H
+#define CPU_H
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void CpuStartUserProgram(void);
+void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len);
+void CpuReset(void);
+
+
+#endif /* CPU_H */
+/*********************************** end of cpu.h **************************************/
diff --git a/Target/Source/ARMCM3_LM3S/flash.c b/Target/Source/ARMCM3_LM3S/flash.c
new file mode 100644
index 00000000..9a59633c
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/flash.c
@@ -0,0 +1,707 @@
+/****************************************************************************************
+| Description: bootloader flash driver source file
+| File Name: flash.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h" /* bootloader generic header */
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "driverlib/flashlib.h"
+
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+#define FLASH_INVALID_SECTOR (0xff)
+#define FLASH_INVALID_ADDRESS (0xffffffff)
+#define FLASH_WRITE_BLOCK_SIZE (512)
+#define FLASH_TOTAL_SECTORS (sizeof(flashLayout)/sizeof(flashLayout[0]))
+#define FLASH_ERASE_BLOCK_SIZE (0x400)
+#define FLASH_VECTOR_TABLE_CS_OFFSET (0xF0)
+
+
+/****************************************************************************************
+* Type definitions
+****************************************************************************************/
+/* flash sector descriptor type */
+typedef struct
+{
+ blt_addr sector_start; /* sector start address */
+ blt_int32u sector_size; /* sector size in bytes */
+ blt_int8u sector_num; /* sector number */
+} tFlashSector; /* flash sector description */
+
+/* programming is done per block of max FLASH_WRITE_BLOCK_SIZE. for this a flash block
+ * manager is implemented in this driver. this flash block manager depends on this
+ * flash block info structure. It holds the base address of the flash block and the
+ * data that should be programmed into the flash block. The .base_addr must be a multiple
+ * of FLASH_WRITE_BLOCK_SIZE.
+ */
+typedef struct
+{
+ blt_addr base_addr;
+ blt_int8u data[FLASH_WRITE_BLOCK_SIZE];
+} tFlashBlockInfo;
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address);
+static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr);
+static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
+ blt_int8u *data, blt_int16u len);
+static blt_bool FlashWriteBlock(tFlashBlockInfo *block);
+static blt_bool FlashEraseSectors(blt_int8u first_sector, blt_int8u last_sector);
+static blt_int8u FlashGetSector(blt_addr address);
+static blt_addr FlashGetSectorBaseAddr(blt_int8u sector);
+static blt_addr FlashGetSectorSize(blt_int8u sector);
+
+
+/****************************************************************************************
+* Local constant declarations
+****************************************************************************************/
+/* The current flash layout does not reflect the minimum sector size of the physical
+ * flash (1 - 2kb), because this would make the table quit long and a waste of ROM. The
+ * minumum sector size is only really needed when erasing the flash. This can still be
+ * done in combination with macro FLASH_ERASE_BLOCK_SIZE.
+ */
+static const tFlashSector flashLayout[] =
+{
+ /* { 0x08000000, 0x02000, 0}, flash sector 0 - reserved for bootloader */
+ /* { 0x08002000, 0x02000, 1}, flash sector 1 - reserved for bootloader */
+ { 0x00004000, 0x02000, 2}, /* flash sector 2 - 8kb */
+ { 0x00006000, 0x02000, 3}, /* flash sector 3 - 8kb */
+#if (BOOT_NVM_SIZE_KB > 32)
+ { 0x00008000, 0x02000, 4}, /* flash sector 4 - 8kb */
+ { 0x0000A000, 0x02000, 5}, /* flash sector 5 - 8kb */
+ { 0x0000C000, 0x02000, 6}, /* flash sector 6 - 8kb */
+ { 0x0000E000, 0x02000, 7}, /* flash sector 7 - 8kb */
+#endif
+#if (BOOT_NVM_SIZE_KB > 64)
+ { 0x00010000, 0x02000, 8}, /* flash sector 8 - 8kb */
+ { 0x00012000, 0x02000, 9}, /* flash sector 9 - 8kb */
+ { 0x00014000, 0x02000, 10}, /* flash sector 10 - 8kb */
+ { 0x00016000, 0x02000, 11}, /* flash sector 11 - 8kb */
+ { 0x00018000, 0x02000, 12}, /* flash sector 12 - 8kb */
+ { 0x0001A000, 0x02000, 13}, /* flash sector 13 - 8kb */
+ { 0x0001C000, 0x02000, 14}, /* flash sector 14 - 8kb */
+ { 0x0001E000, 0x02000, 15}, /* flash sector 15 - 8kb */
+#endif
+#if (BOOT_NVM_SIZE_KB > 128)
+ { 0x00020000, 0x08000, 16}, /* flash sector 16 - 32kb */
+ { 0x00028000, 0x08000, 17}, /* flash sector 17 - 32kb */
+ { 0x00030000, 0x08000, 18}, /* flash sector 18 - 32kb */
+ { 0x00038000, 0x08000, 19}, /* flash sector 19 - 32kb */
+#endif
+#if (BOOT_NVM_SIZE_KB > 256)
+ { 0x00040000, 0x08000, 20}, /* flash sector 20 - 32kb */
+ { 0x00048000, 0x08000, 21}, /* flash sector 21 - 32kb */
+ { 0x00050000, 0x08000, 22}, /* flash sector 22 - 32kb */
+ { 0x00058000, 0x08000, 23}, /* flash sector 23 - 32kb */
+ { 0x00060000, 0x08000, 24}, /* flash sector 24 - 32kb */
+ { 0x00068000, 0x08000, 25}, /* flash sector 25 - 32kb */
+ { 0x00070000, 0x08000, 26}, /* flash sector 26 - 32kb */
+ { 0x00078000, 0x08000, 27}, /* flash sector 27 - 32kb */
+#endif
+#if (BOOT_NVM_SIZE_KB > 512)
+#error "BOOT_NVM_SIZE_KB > 512 is currently not supported."
+#endif
+};
+
+
+/****************************************************************************************
+* Local data declarations
+****************************************************************************************/
+/* The smallest amount of flash that can be programmed is FLASH_WRITE_BLOCK_SIZE. A flash
+ * block manager is implemented in this driver and stores info in this variable. Whenever
+ * new data should be flashed, it is first added to a RAM buffer, which is part of this
+ * variable. Whenever the RAM buffer, which has the size of a flash block, is full or
+ * data needs to be written to a different block, the contents of the RAM buffer are
+ * programmed to flash. The flash block manager requires some software overhead, yet
+ * results is faster flash programming because data is first harvested, ideally until
+ * there is enough to program an entire flash block, before the flash device is actually
+ * operated on.
+ */
+static tFlashBlockInfo blockInfo;
+
+/* The first block of the user program holds the vector table, which on the STM32 is
+ * also the where the checksum is written to. Is it likely that the vector table is
+ * first flashed and then, at the end of the programming sequence, the checksum. This
+ * means that this flash block need to be written to twice. Normally this is not a
+ * problem with flash memory, as long as you write the same values to those bytes that
+ * are not supposed to be changed and the locations where you do write to are still in
+ * the erased 0xFF state. Unfortunately, writing twice to flash this way, does not work
+ * reliably on all micros. This is why we need to have an extra block, the bootblock,
+ * placed under the management of the block manager. This way is it possible to implement
+ * functionality so that the bootblock is only written to once at the end of the
+ * programming sequency.
+ */
+static tFlashBlockInfo bootBlockInfo;
+
+
+/****************************************************************************************
+** NAME: FlashInit
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the flash driver.
+**
+****************************************************************************************/
+void FlashInit(void)
+{
+ /* init the flash block info structs by setting the address to an invalid address */
+ blockInfo.base_addr = FLASH_INVALID_ADDRESS;
+ bootBlockInfo.base_addr = FLASH_INVALID_ADDRESS;
+} /*** end of FlashInit ***/
+
+
+/****************************************************************************************
+** NAME: FlashWrite
+** PARAMETER: addr start address
+** len length in bytes
+** data pointer to the data buffer.
+** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
+** DESCRIPTION: Writes the data to flash through a flash block manager. Note that this
+** function also checks that no data is programmed outside the flash
+** memory region, so the bootloader can never be overwritten.
+**
+****************************************************************************************/
+blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
+{
+ blt_addr base_addr;
+
+ /* make sure the addresses are within the flash device */
+ if ( (FlashGetSector(addr) == FLASH_INVALID_SECTOR) || \
+ (FlashGetSector(addr+len-1) == FLASH_INVALID_SECTOR) )
+ {
+ return BLT_FALSE;
+ }
+
+ /* if this is the bootblock, then let the boot block manager handle it */
+ base_addr = (addr/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
+ if (base_addr == flashLayout[0].sector_start)
+ {
+ /* let the boot block manager handle it */
+ return FlashAddToBlock(&bootBlockInfo, addr, data, len);
+ }
+ /* let the block manager handle it */
+ return FlashAddToBlock(&blockInfo, addr, data, len);
+} /*** end of FlashWrite ***/
+
+
+/****************************************************************************************
+** NAME: FlashErase
+** PARAMETER: addr start address
+** len length in bytes
+** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
+** DESCRIPTION: Erases the flash memory. Note that this function also checks that no
+** data is erased outside the flash memory region, so the bootloader can
+** never be erased.
+**
+****************************************************************************************/
+blt_bool FlashErase(blt_addr addr, blt_int32u len)
+{
+ blt_int8u first_sector;
+ blt_int8u last_sector;
+
+ /* obtain the first and last sector number */
+ first_sector = FlashGetSector(addr);
+ last_sector = FlashGetSector(addr+len-1);
+ /* check them */
+ if ( (first_sector == FLASH_INVALID_SECTOR) || (last_sector == FLASH_INVALID_SECTOR) )
+ {
+ return BLT_FALSE;
+ }
+ /* erase the sectors */
+ return FlashEraseSectors(first_sector, last_sector);
+} /*** end of FlashErase ***/
+
+
+/****************************************************************************************
+** NAME: FlashWriteChecksum
+** PARAMETER: none
+** RETURN VALUE: BLT_TRUE is successful, BTL_FALSE otherwise.
+** DESCRIPTION: Writes a checksum of the user program to non-volatile memory. This is
+** performed once the entire user program has been programmed. Through
+** the checksum, the bootloader can check if the programming session
+** was completed, which indicates that a valid user programming is
+** present and can be started.
+**
+****************************************************************************************/
+blt_bool FlashWriteChecksum(void)
+{
+ blt_int32u signature_checksum = 0;
+
+ /* for the STM32 target we defined the checksum as the Two's complement value of the
+ * sum of the first 7 exception addresses.
+ *
+ * Layout of the vector table:
+ * 0x08000000 Initial stack pointer
+ * 0x08000004 Reset Handler
+ * 0x08000008 NMI Handler
+ * 0x0800000C Hard Fault Handler
+ * 0x08000010 MPU Fault Handler
+ * 0x08000014 Bus Fault Handler
+ * 0x08000018 Usage Fault Handler
+ *
+ * signature_checksum = Two's complement of (SUM(exception address values))
+ *
+ * the bootloader writes this 32-bit checksum value right after the vector table
+ * of the user program. note that this means one extra dummy entry must be added
+ * at the end of the user program's vector table to reserve storage space for the
+ * checksum.
+ */
+
+ /* first check that the bootblock contains valid data. if not, this means the
+ * bootblock is not part of the reprogramming this time and therefore no
+ * new checksum needs to be written
+ */
+ if (bootBlockInfo.base_addr == FLASH_INVALID_ADDRESS)
+ {
+ return BLT_TRUE;
+ }
+
+ /* compute the checksum. note that the user program's vectors are not yet written
+ * to flash but are present in the bootblock data structure at this point.
+ */
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x00]));
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x04]));
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x08]));
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x0C]));
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x10]));
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x14]));
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x18]));
+ signature_checksum = ~signature_checksum; /* one's complement */
+ signature_checksum += 1; /* two's complement */
+
+ /* write the checksum */
+ return FlashWrite(flashLayout[0].sector_start+FLASH_VECTOR_TABLE_CS_OFFSET,
+ sizeof(blt_addr), (blt_int8u*)&signature_checksum);
+} /*** end of FlashWriteChecksum ***/
+
+
+/****************************************************************************************
+** NAME: FlashVerifyChecksum
+** PARAMETER: none
+** RETURN VALUE: BLT_TRUE is successful, BTL_FALSE otherwise.
+** DESCRIPTION: Verifies the checksum, which indicates that a valid user program is
+** present and can be started.
+**
+****************************************************************************************/
+blt_bool FlashVerifyChecksum(void)
+{
+ blt_int32u signature_checksum = 0;
+
+ /* verify the checksum based on how it was written by CpuWriteChecksum() */
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x04));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x08));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x0C));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x10));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x14));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x18));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+FLASH_VECTOR_TABLE_CS_OFFSET));
+ /* sum should add up to an unsigned 32-bit value of 0 */
+ if (signature_checksum == 0)
+ {
+ /* checksum okay */
+ return BLT_TRUE;
+ }
+ /* checksum incorrect */
+ return BLT_FALSE;
+} /*** end of FlashVerifyChecksum ***/
+
+
+/****************************************************************************************
+** NAME: FlashDone
+** PARAMETER: none
+** RETURN VALUE: BLT_TRUE is succesful, BLT_FALSE otherwise.
+** DESCRIPTION: Finilizes the flash driver operations. There could still be data in
+** the currently active block that needs to be flashed.
+**
+****************************************************************************************/
+blt_bool FlashDone(void)
+{
+ /* check if there is still data waiting to be programmed in the boot block */
+ if (bootBlockInfo.base_addr != FLASH_INVALID_ADDRESS)
+ {
+ if (FlashWriteBlock(&bootBlockInfo) == BLT_FALSE)
+ {
+ return BLT_FALSE;
+ }
+ }
+
+ /* check if there is still data waiting to be programmed */
+ if (blockInfo.base_addr != FLASH_INVALID_ADDRESS)
+ {
+ if (FlashWriteBlock(&blockInfo) == BLT_FALSE)
+ {
+ return BLT_FALSE;
+ }
+ }
+ /* still here so all is okay */
+ return BLT_TRUE;
+} /*** end of FlashDone ***/
+
+
+/****************************************************************************************
+** NAME: FlashInitBlock
+** PARAMETER: block pointer to flash block info structure to operate on.
+** address base address of the block data.
+** RETURN VALUE: BLT_TRUE is succesful, BLT_FALSE otherwise.
+** DESCRIPTION: Copies data currently in flash to the block->data and sets the
+** base address.
+**
+****************************************************************************************/
+static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address)
+{
+ /* check address alignment */
+ if ((address % FLASH_WRITE_BLOCK_SIZE) != 0)
+ {
+ return BLT_FALSE;
+ }
+ /* make sure that we are initializing a new block and not the same one */
+ if (block->base_addr == address)
+ {
+ /* block already initialized, so nothing to do */
+ return BLT_TRUE;
+ }
+ /* set the base address and copies the current data from flash */
+ block->base_addr = address;
+ CpuMemCopy((blt_addr)block->data, address, FLASH_WRITE_BLOCK_SIZE);
+ return BLT_TRUE;
+} /*** end of FlashInitBlock ***/
+
+
+/****************************************************************************************
+** NAME: FlashSwitchBlock
+** PARAMETER: block pointer to flash block info structure to operate on.
+** base_addr base address for the next block
+** RETURN VALUE: the pointer of the block info struct that is no being used, or a NULL
+** pointer in case of error.
+** DESCRIPTION: Switches blocks by programming the current one and initializing the
+** next.
+**
+****************************************************************************************/
+static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr)
+{
+ /* check if a switch needs to be made away from the boot block. in this case the boot
+ * block shouldn't be written yet, because this is done at the end of the programming
+ * session by FlashDone(), this is right after the checksum was written.
+ */
+ if (block == &bootBlockInfo)
+ {
+ /* switch from the boot block to the generic block info structure */
+ block = &blockInfo;
+ }
+ /* check if a switch back into the bootblock is needed. in this case the generic block
+ * doesn't need to be written here yet.
+ */
+ else if (base_addr == flashLayout[0].sector_start)
+ {
+ /* switch from the generic block to the boot block info structure */
+ block = &bootBlockInfo;
+ base_addr = flashLayout[0].sector_start;
+ }
+ else
+ {
+ /* need to switch to a new block, so program the current one and init the next */
+ if (FlashWriteBlock(block) == BLT_FALSE)
+ {
+ return BLT_NULL;
+ }
+ }
+
+ /* initialize tne new block when necessary */
+ if (FlashInitBlock(block, base_addr) == BLT_FALSE)
+ {
+ return BLT_NULL;
+ }
+
+ /* still here to all is okay */
+ return block;
+} /*** end of FlashSwitchBlock ***/
+
+
+/****************************************************************************************
+** NAME: FlashAddToBlock
+** PARAMETER: block pointer to flash block info structure to operate on.
+** address flash destination address
+** data pointer to the byte array with data
+** len number of bytes to add to the block
+** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
+** DESCRIPTION: Programming is done per block. This function adds data to the block
+** that is currently collecting data to be written to flash. If the
+** address is outside of the current block, the current block is written
+** to flash an a new block is initialized.
+**
+****************************************************************************************/
+static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
+ blt_int8u *data, blt_int16u len)
+{
+ blt_addr current_base_addr;
+ blt_int8u *dst;
+ blt_int8u *src;
+
+ /* determine the current base address */
+ current_base_addr = (address/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
+
+ /* make sure the blockInfo is not uninitialized */
+ if (block->base_addr == FLASH_INVALID_ADDRESS)
+ {
+ /* initialize the blockInfo struct for the current block */
+ if (FlashInitBlock(block, current_base_addr) == BLT_FALSE)
+ {
+ return BLT_FALSE;
+ }
+ }
+
+ /* check if the new data fits in the current block */
+ if (block->base_addr != current_base_addr)
+ {
+ /* need to switch to a new block, so program the current one and init the next */
+ block = FlashSwitchBlock(block, current_base_addr);
+ if (block == BLT_NULL)
+ {
+ return BLT_FALSE;
+ }
+ }
+
+ /* add the data to the current block, but check for block overflow */
+ dst = &(block->data[address - block->base_addr]);
+ src = data;
+ do
+ {
+ /* keep the watchdog happy */
+ CopService();
+ /* buffer overflow? */
+ if ((blt_addr)(dst-&(block->data[0])) >= FLASH_WRITE_BLOCK_SIZE)
+ {
+ /* need to switch to a new block, so program the current one and init the next */
+ block = FlashSwitchBlock(block, current_base_addr+FLASH_WRITE_BLOCK_SIZE);
+ if (block == BLT_NULL)
+ {
+ return BLT_FALSE;
+ }
+ /* reset destination pointer */
+ dst = &(block->data[0]);
+ }
+ /* write the data to the buffer */
+ *dst = *src;
+ /* update pointers */
+ dst++;
+ src++;
+ /* decrement byte counter */
+ len--;
+ }
+ while (len > 0);
+ /* still here so all is good */
+ return BLT_TRUE;
+} /*** end of FlashAddToBlock ***/
+
+
+/****************************************************************************************
+** NAME: FlashWriteBlock
+** PARAMETER: block pointer to flash block info structure to operate on.
+** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
+** DESCRIPTION: Programs FLASH_WRITE_BLOCK_SIZE bytes to flash from the block->data
+** array.
+**
+****************************************************************************************/
+static blt_bool FlashWriteBlock(tFlashBlockInfo *block)
+{
+ blt_int8u sector_num;
+ blt_bool result = BLT_TRUE;
+ blt_addr prog_addr;
+ blt_int32u prog_data;
+ blt_int32u word_cnt;
+
+ /* check that address is actually within flash */
+ sector_num = FlashGetSector(block->base_addr);
+ if (sector_num == FLASH_INVALID_SECTOR)
+ {
+ return BLT_FALSE;
+ }
+ /* program all words in the block one by one */
+ for (word_cnt=0; word_cnt<(FLASH_WRITE_BLOCK_SIZE/sizeof(blt_int32u)); word_cnt++)
+ {
+ prog_addr = block->base_addr + (word_cnt * sizeof(blt_int32u));
+ prog_data = *(volatile blt_int32u*)(&block->data[word_cnt * sizeof(blt_int32u)]);
+ /* keep the watchdog happy */
+ CopService();
+ /* program the word to flash */
+ if (FlashProgram((unsigned long *)&prog_data, prog_addr, sizeof(blt_int32u)) != 0)
+ {
+ result = BLT_FALSE;
+ break;
+ }
+ /* verify that the written data is actually there */
+ if (*(volatile blt_int32u*)prog_addr != prog_data)
+ {
+ result = BLT_FALSE;
+ break;
+ }
+ }
+ /* still here so all is okay */
+ return result;
+} /*** end of FlashWriteBlock ***/
+
+
+/****************************************************************************************
+** NAME: FlashEraseSectors
+** PARAMETER: first_sector first flash sector number
+** last_sector last flash sector number
+** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
+** DESCRIPTION: Erases the flash sectors from first_sector up until last_sector
+**
+****************************************************************************************/
+static blt_bool FlashEraseSectors(blt_int8u first_sector, blt_int8u last_sector)
+{
+ blt_int16u nr_of_blocks;
+ blt_int16u block_cnt;
+ blt_addr start_addr;
+ blt_addr end_addr;
+
+ /* validate the sector numbers */
+ if (first_sector > last_sector)
+ {
+ return BLT_FALSE;
+ }
+ if ( (first_sector < flashLayout[0].sector_num) || \
+ (last_sector > flashLayout[FLASH_TOTAL_SECTORS-1].sector_num) )
+ {
+ return BLT_FALSE;
+ }
+ /* determine how many blocks need to be erased */
+ start_addr = FlashGetSectorBaseAddr(first_sector);
+ end_addr = FlashGetSectorBaseAddr(last_sector) + FlashGetSectorSize(last_sector) - 1;
+ nr_of_blocks = (end_addr - start_addr + 1) / FLASH_ERASE_BLOCK_SIZE;
+
+ /* erase all blocks one by one */
+ for (block_cnt=0; block_cnt= flashLayout[sectorIdx].sector_start) && \
+ (address < (flashLayout[sectorIdx].sector_start + \
+ flashLayout[sectorIdx].sector_size)) )
+ {
+ /* return the sector number */
+ return flashLayout[sectorIdx].sector_num;
+ }
+ }
+ /* still here so no valid sector found */
+ return FLASH_INVALID_SECTOR;
+} /*** end of FlashGetSector ***/
+
+
+/****************************************************************************************
+** NAME: FlashGetSectorBaseAddr
+** PARAMETER: sector sector to get the base address of.
+** RETURN VALUE: flash sector base address or FLASH_INVALID_ADDRESS
+** DESCRIPTION: Determines the flash sector base address.
+**
+****************************************************************************************/
+static blt_addr FlashGetSectorBaseAddr(blt_int8u sector)
+{
+ blt_int8u sectorIdx;
+
+ /* search through the sectors to find the right one */
+ for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++)
+ {
+ /* keep the watchdog happy */
+ CopService();
+ if (flashLayout[sectorIdx].sector_num == sector)
+ {
+ return flashLayout[sectorIdx].sector_start;
+ }
+ }
+ /* still here so no valid sector found */
+ return FLASH_INVALID_ADDRESS;
+} /*** end of FlashGetSectorBaseAddr ***/
+
+
+/****************************************************************************************
+** NAME: FlashGetSectorSize
+** PARAMETER: sector sector to get the size of.
+** RETURN VALUE: flash sector size or 0
+** DESCRIPTION: Determines the flash sector size.
+**
+****************************************************************************************/
+static blt_addr FlashGetSectorSize(blt_int8u sector)
+{
+ blt_int8u sectorIdx;
+
+ /* search through the sectors to find the right one */
+ for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++)
+ {
+ /* keep the watchdog happy */
+ CopService();
+ if (flashLayout[sectorIdx].sector_num == sector)
+ {
+ return flashLayout[sectorIdx].sector_size;
+ }
+ }
+ /* still here so no valid sector found */
+ return 0;
+} /*** end of FlashGetSectorSize ***/
+
+
+/*********************************** end of flash.c ************************************/
diff --git a/Target/Source/ARMCM3_LM3S/flash.h b/Target/Source/ARMCM3_LM3S/flash.h
new file mode 100644
index 00000000..ea81acfa
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/flash.h
@@ -0,0 +1,46 @@
+/****************************************************************************************
+| Description: bootloader flash driver header file
+| File Name: flash.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef FLASH_H
+#define FLASH_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void FlashInit(void);
+blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
+blt_bool FlashErase(blt_addr addr, blt_int32u len);
+blt_bool FlashWriteChecksum(void);
+blt_bool FlashVerifyChecksum(void);
+blt_bool FlashDone(void);
+
+
+#endif /* FLASH_H */
+/*********************************** end of flash.h ************************************/
diff --git a/Target/Source/ARMCM3_LM3S/nvm.c b/Target/Source/ARMCM3_LM3S/nvm.c
new file mode 100644
index 00000000..a84a5107
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/nvm.c
@@ -0,0 +1,201 @@
+/****************************************************************************************
+| Description: bootloader non-volatile memory driver source file
+| File Name: nvm.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h" /* bootloader generic header */
+
+
+/****************************************************************************************
+* Hook functions
+****************************************************************************************/
+#if (BOOT_NVM_HOOKS_ENABLE > 0)
+extern void NvmInitHook(void);
+extern blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data);
+extern blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len);
+extern blt_bool NvmDoneHook(void);
+#endif
+
+
+/****************************************************************************************
+** NAME: NvmInit
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the NVM driver.
+**
+****************************************************************************************/
+void NvmInit(void)
+{
+#if (BOOT_NVM_HOOKS_ENABLE > 0)
+ /* give the application a chance to initialize a driver for operating on NVM
+ * that is not by default supported by this driver.
+ */
+ NvmInitHook();
+#endif
+
+ /* init the internal driver */
+ FlashInit();
+} /*** end of NvmInit ***/
+
+
+/****************************************************************************************
+** NAME: NvmWrite
+** PARAMETER: addr start address
+** len length in bytes
+** data pointer to the data buffer.
+** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
+** DESCRIPTION: Programs the non-volatile memory.
+**
+****************************************************************************************/
+blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
+{
+#if (BOOT_NVM_HOOKS_ENABLE > 0)
+ blt_int8u result = BLT_NVM_NOT_IN_RANGE;
+#endif
+
+#if (BOOT_NVM_HOOKS_ENABLE > 0)
+ /* give the application a chance to operate on memory that is not by default supported
+ * by this driver.
+ */
+ result = NvmWriteHook(addr, len, data);
+
+ /* process the return code */
+ if (result == BLT_NVM_OKAY)
+ {
+ /* data was within range of the additionally supported memory and succesfully
+ * programmed, so we are all done.
+ */
+ return BLT_TRUE;
+ }
+ else if (result == BLT_NVM_ERROR)
+ {
+ /* data was within range of the additionally supported memory and attempted to be
+ * programmed, but an error occurred, so we can't continue.
+ */
+ return BLT_FALSE;
+ }
+#endif
+
+ /* still here so the internal driver should try and perform the program operation */
+ return FlashWrite(addr, len, data);
+} /*** end of NvmWrite ***/
+
+
+/****************************************************************************************
+** NAME: NvmErase
+** PARAMETER: addr start address
+** len length in bytes
+** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
+** DESCRIPTION: Erases the non-volatile memory.
+**
+****************************************************************************************/
+blt_bool NvmErase(blt_addr addr, blt_int32u len)
+{
+#if (BOOT_NVM_HOOKS_ENABLE > 0)
+ blt_int8u result = BLT_NVM_NOT_IN_RANGE;
+#endif
+
+#if (BOOT_NVM_HOOKS_ENABLE > 0)
+ /* give the application a chance to operate on memory that is not by default supported
+ * by this driver.
+ */
+ result = NvmEraseHook(addr, len);
+
+ /* process the return code */
+ if (result == BLT_NVM_OKAY)
+ {
+ /* address was within range of the additionally supported memory and succesfully
+ * erased, so we are all done.
+ */
+ return BLT_TRUE;
+ }
+ else if (result == BLT_NVM_ERROR)
+ {
+ /* address was within range of the additionally supported memory and attempted to be
+ * erased, but an error occurred, so we can't continue.
+ */
+ return BLT_FALSE;
+ }
+#endif
+
+ /* still here so the internal driver should try and perform the erase operation */
+ return FlashErase(addr, len);
+} /*** end of NvmErase ***/
+
+
+/****************************************************************************************
+** NAME: NvmVerifyChecksum
+** PARAMETER: none
+** RETURN VALUE: BLT_TRUE is successful, BTL_FALSE otherwise.
+** DESCRIPTION: Verifies the checksum, which indicates that a valid user program is
+** present and can be started.
+**
+****************************************************************************************/
+blt_bool NvmVerifyChecksum(void)
+{
+ /* check checksum */
+ return FlashVerifyChecksum();
+} /*** end of NvmVerifyChecksum ***/
+
+
+/****************************************************************************************
+** NAME: NvmDone
+** PARAMETER: none
+** RETURN VALUE: BLT_TRUE is successful, BLT_FALSE otherwise.
+** DESCRIPTION: Once all erase and programming operations are completed, this
+** function is called, so at the end of the programming session and
+** right before a software reset is performed. It is used to calculate
+** a checksum and program this into flash. This checksum is later used
+** to determine if a valid user program is present in flash.
+**
+****************************************************************************************/
+blt_bool NvmDone(void)
+{
+#if (BOOT_NVM_HOOKS_ENABLE > 0)
+ /* give the application's NVM driver a chance to finish up */
+ if (NvmDoneHook() == BLT_FALSE)
+ {
+ /* error so no need to continue */
+ return BLT_FALSE;
+ }
+#endif
+ /* compute and write checksum, which is programmed by the internal driver */
+ if (FlashWriteChecksum() == BLT_FALSE)
+ {
+ return BLT_FALSE;
+ }
+ /* finish up internal driver operations */
+ return FlashDone();
+} /*** end of NvmDone ***/
+
+
+/*********************************** end of nvm.c **************************************/
diff --git a/Target/Source/ARMCM3_LM3S/nvm.h b/Target/Source/ARMCM3_LM3S/nvm.h
new file mode 100644
index 00000000..4b58cd8c
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/nvm.h
@@ -0,0 +1,60 @@
+/****************************************************************************************
+| Description: bootloader non-volatile memory driver header file
+| File Name: nvm.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef NVM_H
+#define NVM_H
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "flash.h" /* LPC2xxx flash driver */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void NvmInit(void);
+blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
+blt_bool NvmErase(blt_addr addr, blt_int32u len);
+blt_bool NvmVerifyChecksum(void);
+blt_bool NvmDone(void);
+
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+/* return codes for hook function NvmWrite/Erase */
+#define BLT_NVM_ERROR (0x00) /* return code for success */
+#define BLT_NVM_OKAY (0x01) /* return code for error */
+#define BLT_NVM_NOT_IN_RANGE (0x02) /* return code for not in range */
+
+
+#endif /* NVM_H */
+/*********************************** end of nvm.h **************************************/
diff --git a/Target/Source/ARMCM3_LM3S/timer.c b/Target/Source/ARMCM3_LM3S/timer.c
new file mode 100644
index 00000000..0e5ac9d7
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/timer.c
@@ -0,0 +1,156 @@
+/****************************************************************************************
+| Description: bootloader timer driver source file
+| File Name: timer.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h" /* bootloader generic header */
+
+
+/****************************************************************************************
+* Type definitions
+****************************************************************************************/
+typedef struct
+{
+ volatile blt_int32u CTRL; /* SysTick Control and Status Register */
+ volatile blt_int32u LOAD; /* SysTick Reload Value Register */
+ volatile blt_int32u VAL; /* SysTick Current Value Register */
+} tSysTickRegs;
+
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+#define SYSTICK_BIT_CLKSOURCE ((blt_int32u)0x00000004)
+#define SYSTICK_BIT_ENABLE ((blt_int32u)0x00000001)
+#define SYSTICK_BIT_COUNTERFLAG ((blt_int32u)0x00010000)
+
+
+/****************************************************************************************
+* Local data declarations
+****************************************************************************************/
+static blt_int16u millisecond_counter;
+
+
+/****************************************************************************************
+* Register definitions
+****************************************************************************************/
+#define SYSTICK ((tSysTickRegs *) (blt_int32u)0xE000E010)
+
+
+/****************************************************************************************
+** NAME: TimerInit
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the polling based millisecond timer driver.
+**
+****************************************************************************************/
+void TimerInit(void)
+{
+ /* reset the timer configuration */
+ TimerReset();
+ /* configure the systick frequency as a 1 ms event generator */
+ SYSTICK->LOAD = BOOT_CPU_SYSTEM_SPEED_KHZ - 1;
+ /* reset the current counter value */
+ SYSTICK->VAL = 0;
+ /* select core clock as source and enable the timer */
+ SYSTICK->CTRL = SYSTICK_BIT_CLKSOURCE | SYSTICK_BIT_ENABLE;
+ /* reset the millisecond counter value */
+ TimerSet(0);
+} /*** end of TimerInit ***/
+
+
+/****************************************************************************************
+** NAME: TimerReset
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Reset the timer by placing the timer back into it's default reset
+** configuration.
+**
+****************************************************************************************/
+void TimerReset(void)
+{
+ /* set the systick's status and control register back into the default reset value */
+ SYSTICK->CTRL = 0;
+} /* end of TimerReset */
+
+
+/****************************************************************************************
+** NAME: TimerUpdate
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Updates the millisecond timer.
+**
+****************************************************************************************/
+void TimerUpdate(void)
+{
+ /* check if the milliseond event occurred */
+ if ((SYSTICK->CTRL & SYSTICK_BIT_COUNTERFLAG) != 0)
+ {
+ /* increment the millisecond counter */
+ millisecond_counter++;
+ }
+} /*** end of TimerUpdate ***/
+
+
+/****************************************************************************************
+** NAME: TimerSet
+** PARAMETER: timer_value initialize value of the millisecond timer.
+** RETURN VALUE: none
+** DESCRIPTION: Sets the initial counter value of the millisecond timer.
+**
+****************************************************************************************/
+void TimerSet(blt_int32u timer_value)
+{
+ /* set the millisecond counter value */
+ millisecond_counter = timer_value;
+} /*** end of TimerSet ***/
+
+
+/****************************************************************************************
+** NAME: TimerGet
+** PARAMETER: none
+** RETURN VALUE: current value of the millisecond timer
+** DESCRIPTION: Obtains the counter value of the millisecond timer.
+**
+****************************************************************************************/
+blt_int32u TimerGet(void)
+{
+ /* updating timer here allows this function to be called in a loop with timeout
+ * detection.
+ */
+ TimerUpdate();
+ /* read and return the amount of milliseconds that passed since initialization */
+ return millisecond_counter;
+} /*** end of TimerGet ***/
+
+
+/*********************************** end of timer.c ************************************/
diff --git a/Target/Source/ARMCM3_LM3S/timer.h b/Target/Source/ARMCM3_LM3S/timer.h
new file mode 100644
index 00000000..a0fa926b
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/timer.h
@@ -0,0 +1,45 @@
+/****************************************************************************************
+| Description: bootloader timer driver header file
+| File Name: timer.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef TIMER_H
+#define TIMER_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void TimerInit(void);
+void TimerUpdate(void);
+void TimerSet(blt_int32u timer_value);
+blt_int32u TimerGet(void);
+void TimerReset(void);
+
+
+#endif /* TIMER_H */
+/*********************************** end of timer.h ************************************/
diff --git a/Target/Source/ARMCM3_LM3S/types.h b/Target/Source/ARMCM3_LM3S/types.h
new file mode 100644
index 00000000..97f7bcf5
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/types.h
@@ -0,0 +1,58 @@
+/****************************************************************************************
+| Description: bootloader types header file
+| File Name: types.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef TYPES_H
+#define TYPES_H
+
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+#define BLT_TRUE (1)
+#define BLT_FALSE (0)
+#define BLT_NULL ((void *)0)
+
+
+/****************************************************************************************
+* Type definitions
+****************************************************************************************/
+typedef unsigned char blt_bool; /* boolean type */
+typedef char blt_char; /* character type */
+typedef unsigned long blt_addr; /* memory address type */
+typedef unsigned char blt_int8u; /* 8-bit unsigned integer */
+typedef signed char blt_int8s; /* 8-bit signed integer */
+typedef unsigned short blt_int16u; /* 16-bit unsigned integer */
+typedef signed short blt_int16s; /* 16-bit signed integer */
+typedef unsigned int blt_int32u; /* 32-bit unsigned integer */
+typedef signed int blt_int32s; /* 32-bit signed integer */
+
+
+#endif /* TYPES_H */
+/*********************************** end of types.h ************************************/
diff --git a/Target/Source/ARMCM3_LM3S/uart.c b/Target/Source/ARMCM3_LM3S/uart.c
new file mode 100644
index 00000000..1d9d529d
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/uart.c
@@ -0,0 +1,207 @@
+/****************************************************************************************
+| Description: bootloader UART communication interface source file
+| File Name: uart.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h" /* bootloader generic header */
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#if (BOOT_COM_UART_ENABLE > 0)
+#include "driverlib/uartlib.h"
+#endif
+
+
+#if (BOOT_COM_UART_ENABLE > 0)
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static blt_bool UartReceiveByte(blt_int8u *data);
+static blt_bool UartTransmitByte(blt_int8u data);
+
+
+/****************************************************************************************
+** NAME: UartInit
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the UART communication interface
+**
+****************************************************************************************/
+void UartInit(void)
+{
+ /* the current implementation supports UART0. throw an assertion error in case a
+ * different UART channel is configured.
+ */
+ ASSERT_CT(BOOT_COM_UART_CHANNEL_INDEX == 0);
+ /* enable the UART0 peripheral */
+ SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
+ /* configure the UART0 baudrate and communication parameters */
+ UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(), BOOT_COM_UART_BAUDRATE,
+ (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
+ UART_CONFIG_PAR_NONE));
+} /*** end of UartInit ***/
+
+
+/****************************************************************************************
+** NAME: UartTransmitPacket
+** PARAMETER: data pointer to byte array with data that it to be transmitted.
+** len number of bytes that are to be transmitted.
+** RETURN VALUE: none
+** DESCRIPTION: Transmits a packet formatted for the communication interface.
+**
+****************************************************************************************/
+void UartTransmitPacket(blt_int8u *data, blt_int8u len)
+{
+ blt_int16u data_index;
+
+ /* verify validity of the len-paramenter */
+ ASSERT_RT(len <= BOOT_COM_TX_MAX_DATA);
+
+ /* first transmit the length of the packet */
+ ASSERT_RT(UartTransmitByte(len) == BLT_TRUE);
+
+ /* transmit all the packet bytes one-by-one */
+ for (data_index = 0; data_index < len; data_index++)
+ {
+ /* keep the watchdog happy */
+ CopService();
+ /* write byte */
+ ASSERT_RT(UartTransmitByte(data[data_index]) == BLT_TRUE);
+ }
+} /*** end of UartTransmitPacket ***/
+
+
+/****************************************************************************************
+** NAME: UartReceivePacket
+** PARAMETER: data pointer to byte array where the data is to be stored.
+** RETURN VALUE: BLT_TRUE if a packet was received, BLT_FALSE otherwise.
+** DESCRIPTION: Receives a communication interface packet if one is present.
+**
+****************************************************************************************/
+blt_bool UartReceivePacket(blt_int8u *data)
+{
+ static blt_int8u xcpCtoReqPacket[XCP_CTO_PACKET_LEN+1]; /* one extra for length */
+ static blt_int8u xcpCtoRxLength;
+ static blt_bool xcpCtoRxInProgress = BLT_FALSE;
+
+ /* start of cto packet received? */
+ if (xcpCtoRxInProgress == BLT_FALSE)
+ {
+ /* store the message length when received */
+ if (UartReceiveByte(&xcpCtoReqPacket[0]) == BLT_TRUE)
+ {
+ /* indicate that a cto packet is being received */
+ xcpCtoRxInProgress = BLT_TRUE;
+
+ /* reset packet data count */
+ xcpCtoRxLength = 0;
+ }
+ }
+ else
+ {
+ /* store the next packet byte */
+ if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == BLT_TRUE)
+ {
+ /* increment the packet data count */
+ xcpCtoRxLength++;
+
+ /* check to see if the entire packet was received */
+ if (xcpCtoRxLength == xcpCtoReqPacket[0])
+ {
+ /* copy the packet data */
+ CpuMemCopy((blt_int32u)data, (blt_int32u)&xcpCtoReqPacket[1], xcpCtoRxLength);
+ /* done with cto packet reception */
+ xcpCtoRxInProgress = BLT_FALSE;
+
+ /* packet reception complete */
+ return BLT_TRUE;
+ }
+ }
+ }
+ /* packet reception not yet complete */
+ return BLT_FALSE;
+} /*** end of UartReceivePacket ***/
+
+
+/****************************************************************************************
+** NAME: UartReceiveByte
+** PARAMETER: data pointer to byte where the data is to be stored.
+** RETURN VALUE: BLT_TRUE if a byte was received, BLT_FALSE otherwise.
+** DESCRIPTION: Receives a communication interface byte if one is present.
+**
+****************************************************************************************/
+static blt_bool UartReceiveByte(blt_int8u *data)
+{
+ blt_int32s result;
+
+ /* try to read a newly received byte */
+ result = UARTCharGetNonBlocking(UART0_BASE);
+ /* check if a new byte was received */
+ if(result != -1)
+ {
+ /* store the received byte */
+ data[0] = (blt_int8u)result;
+ /* inform caller of the newly received byte */
+ return BLT_TRUE;
+ }
+ /* inform caller that no new data was received */
+ return BLT_FALSE;
+} /*** end of UartReceiveByte ***/
+
+
+/****************************************************************************************
+** NAME: UartTransmitByte
+** PARAMETER: data value of byte that is to be transmitted.
+** RETURN VALUE: BLT_TRUE if the byte was transmitted, BLT_FALSE otherwise.
+** DESCRIPTION: Transmits a communication interface byte.
+**
+****************************************************************************************/
+static blt_bool UartTransmitByte(blt_int8u data)
+{
+ /* write byte to transmit holding register */
+ if (UARTCharPutNonBlocking(UART0_BASE, data) == false)
+ {
+ /* tx holding register can accept new data */
+ return BLT_FALSE;
+ }
+ /* wait for tx holding register to be empty */
+ while(UARTSpaceAvail(UART0_BASE) == false)
+ {
+ /* keep the watchdog happy */
+ CopService();
+ }
+ /* byte transmitted */
+ return BLT_TRUE;
+} /*** end of UartTransmitByte ***/
+#endif /* BOOT_COM_UART_ENABLE > 0 */
+
+
+/*********************************** end of uart.c *************************************/
diff --git a/Target/Source/ARMCM3_LM3S/uart.h b/Target/Source/ARMCM3_LM3S/uart.h
new file mode 100644
index 00000000..f4b9b5d9
--- /dev/null
+++ b/Target/Source/ARMCM3_LM3S/uart.h
@@ -0,0 +1,45 @@
+/****************************************************************************************
+| Description: bootloader UART communication interface header file
+| File Name: uart.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2012 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef UART_H
+#define UART_H
+
+#if (BOOT_COM_UART_ENABLE > 0)
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void UartInit(void);
+void UartTransmitPacket(blt_int8u *data, blt_int8u len);
+blt_bool UartReceivePacket(blt_int8u *data);
+#endif /* BOOT_COM_UART_ENABLE > 0 */
+
+
+#endif /* UART_H */
+/*********************************** end of uart.h *************************************/