From adb4e6e943c72e8376526ea2b6edeb74bd409140 Mon Sep 17 00:00:00 2001 From: Frank Voorburg Date: Wed, 18 Sep 2013 10:39:57 +0000 Subject: [PATCH] Added Freescale HCS12 port including a Dragon12plus demo. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@60 5dc33758-31d5-4daf-9ae8-b24bf3d40d73 --- Host/openblt_uart.ini | 2 +- .../Boot/bin/openblt_evbplus_dragon12p.abs | Bin 0 -> 245432 bytes .../bin/openblt_evbplus_dragon12p.abs.phy | 142 + .../bin/openblt_evbplus_dragon12p.abs.s19 | 142 + .../Boot/bin/openblt_evbplus_dragon12p.map | 2801 +++ .../Boot/blt_conf.h | 168 + .../Boot/boot.dox | 7 + ...P&E_Multilink_USB_Erase_unsecure_hcs12.cmd | 78 + .../Boot/cmd/P&E_Multilink_USB_Postload.cmd | 1 + .../Boot/cmd/P&E_Multilink_USB_Preload.cmd | 1 + .../Boot/cmd/P&E_Multilink_USB_Reset.cmd | 1 + .../Boot/cmd/P&E_Multilink_USB_Startup.cmd | 1 + .../Boot/cmd/P&E_Multilink_USB_Vppoff.cmd | 1 + .../Boot/cmd/P&E_Multilink_USB_Vppon.cmd | 1 + .../Boot/cmd/burner.bbl | 157 + .../Boot/hooks.c | 217 + .../Boot/ide/C_Layout.hwl | 20 + .../Boot/ide/Default.mem | Bin 0 -> 161 bytes .../Boot/ide/P&E_Multilink_USB.ini | 95 + .../Boot/ide/hcs12.mcp | Bin 0 -> 60518 bytes .../Boot/ide/hcs12_Data/CWSettingsWindows.stg | Bin 0 -> 4179 bytes .../hcs12_Data/Standard/TargetDataWindows.tdt | Bin 0 -> 548025 bytes .../Boot/lib/datapage.c | 1981 ++ .../Boot/lib/derivative.h | 10 + .../Boot/lib/mc9s12dg256.c | 366 + .../Boot/lib/mc9s12dg256.h | 16197 ++++++++++++++++ .../Boot/main.c | 136 + .../Prog/bin/demoprog_evbplus_dragon12p.abs | Bin 0 -> 207573 bytes .../bin/demoprog_evbplus_dragon12p.abs.sx | 21 + .../Prog/bin/demoprog_evbplus_dragon12p.map | 1998 ++ .../Prog/boot.c | 169 + .../Prog/boot.h | 44 + ...P&E_Multilink_USB_Erase_unsecure_hcs12.cmd | 78 + .../Prog/cmd/P&E_Multilink_USB_Postload.cmd | 1 + .../Prog/cmd/P&E_Multilink_USB_Preload.cmd | 1 + .../Prog/cmd/P&E_Multilink_USB_Reset.cmd | 1 + .../Prog/cmd/P&E_Multilink_USB_Startup.cmd | 1 + .../Prog/cmd/P&E_Multilink_USB_Vppoff.cmd | 1 + .../Prog/cmd/P&E_Multilink_USB_Vppon.cmd | 1 + .../Prog/cmd/burner.bbl | 115 + .../Prog/header.h | 49 + .../Prog/ide/C_Layout.hwl | 20 + .../Prog/ide/Default.mem | Bin 0 -> 161 bytes .../Prog/ide/P&E_Multilink_USB.ini | 84 + .../Prog/ide/hcs12.mcp | Bin 0 -> 58710 bytes .../Prog/ide/hcs12_Data/CWSettingsWindows.stg | Bin 0 -> 4179 bytes .../hcs12_Data/Standard/TargetDataWindows.tdt | Bin 0 -> 517682 bytes .../Prog/irq.c | 106 + .../Prog/irq.h | 45 + .../Prog/led.c | 104 + .../Prog/led.h | 44 + .../Prog/lib/datapage.c | 1981 ++ .../Prog/lib/derivative.h | 10 + .../Prog/lib/mc9s12dg256.c | 366 + .../Prog/lib/mc9s12dg256.h | 16197 ++++++++++++++++ .../Prog/main.c | 86 + .../Prog/memory.x | 65 + .../Prog/prog.dox | 7 + .../Prog/start12.c | 475 + .../Prog/time.c | 144 + .../Prog/time.h | 46 + .../Prog/vectors.c | 150 + .../demo.dox | 8 + Target/Source/HCS12/CodeWarrior/memory.x | 37 + Target/Source/HCS12/CodeWarrior/start12.c | 485 + Target/Source/HCS12/CodeWarrior/vectors.c | 1770 ++ Target/Source/HCS12/cpu.c | 144 + Target/Source/HCS12/cpu.h | 46 + Target/Source/HCS12/flash.c | 975 + Target/Source/HCS12/flash.h | 48 + Target/Source/HCS12/nvm.c | 216 + Target/Source/HCS12/nvm.h | 65 + Target/Source/HCS12/target.dox | 8 + Target/Source/HCS12/timer.c | 178 + Target/Source/HCS12/timer.h | 46 + Target/Source/HCS12/types.h | 63 + Target/Source/HCS12/uart.c | 252 + Target/Source/HCS12/uart.h | 47 + 78 files changed, 49322 insertions(+), 1 deletion(-) create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/bin/openblt_evbplus_dragon12p.abs create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/bin/openblt_evbplus_dragon12p.abs.phy create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/bin/openblt_evbplus_dragon12p.abs.s19 create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/bin/openblt_evbplus_dragon12p.map create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/blt_conf.h create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/boot.dox create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Erase_unsecure_hcs12.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Postload.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Preload.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Reset.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Startup.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Vppoff.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Vppon.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/burner.bbl create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/hooks.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/C_Layout.hwl create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/Default.mem create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/P&E_Multilink_USB.ini create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/hcs12.mcp create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/hcs12_Data/CWSettingsWindows.stg create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/hcs12_Data/Standard/TargetDataWindows.tdt create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/datapage.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/derivative.h create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/mc9s12dg256.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/mc9s12dg256.h create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/main.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/bin/demoprog_evbplus_dragon12p.abs create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/bin/demoprog_evbplus_dragon12p.abs.sx create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/bin/demoprog_evbplus_dragon12p.map create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/boot.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/boot.h create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Erase_unsecure_hcs12.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Postload.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Preload.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Reset.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Startup.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Vppoff.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Vppon.cmd create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/burner.bbl create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/header.h create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/C_Layout.hwl create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/Default.mem create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/P&E_Multilink_USB.ini create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/hcs12.mcp create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/hcs12_Data/CWSettingsWindows.stg create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/hcs12_Data/Standard/TargetDataWindows.tdt create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/irq.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/irq.h create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/led.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/led.h create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/datapage.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/derivative.h create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/mc9s12dg256.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/mc9s12dg256.h create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/main.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/memory.x create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/prog.dox create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/start12.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/time.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/time.h create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/vectors.c create mode 100644 Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/demo.dox create mode 100644 Target/Source/HCS12/CodeWarrior/memory.x create mode 100644 Target/Source/HCS12/CodeWarrior/start12.c create mode 100644 Target/Source/HCS12/CodeWarrior/vectors.c create mode 100644 Target/Source/HCS12/cpu.c create mode 100644 Target/Source/HCS12/cpu.h create mode 100644 Target/Source/HCS12/flash.c create mode 100644 Target/Source/HCS12/flash.h create mode 100644 Target/Source/HCS12/nvm.c create mode 100644 Target/Source/HCS12/nvm.h create mode 100644 Target/Source/HCS12/target.dox create mode 100644 Target/Source/HCS12/timer.c create mode 100644 Target/Source/HCS12/timer.h create mode 100644 Target/Source/HCS12/types.h create mode 100644 Target/Source/HCS12/uart.c create mode 100644 Target/Source/HCS12/uart.h diff --git a/Host/openblt_uart.ini b/Host/openblt_uart.ini index 56b278d5..164dac50 100644 --- a/Host/openblt_uart.ini +++ b/Host/openblt_uart.ini @@ -1,5 +1,5 @@ [sci] -port=3 +port=5 baudrate=8 [xcp] seedkey= diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/bin/openblt_evbplus_dragon12p.abs b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/bin/openblt_evbplus_dragon12p.abs new file mode 100644 index 0000000000000000000000000000000000000000..5686e7c82532fe981ea259d432b48b43e95ce4e9 GIT binary patch literal 245432 zcmeEv30zgx`u5&upTnRiDu@G`n5kK*fS?|Ulu=P8563AjL?k5<46rh-5EalInr_)V zSltGj2ddkknRqMH=DL-YdUL=7qQZg7tKajk{qA!XTPdyk|Nh_i`)TdHp67kvwbr}d zHSD$bKAdxNQfjhlQ5DZWixLeC!GS@F_WJdTcJq3ni&DarNaaGcK%IBuz_9-uh#1&0 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+S123FFE0F735F73BF741F747F74DF753F759F75FF765F76BF771F777F77DF783F789F60CF1 +S9030000FC diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/bin/openblt_evbplus_dragon12p.map b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/bin/openblt_evbplus_dragon12p.map new file mode 100644 index 00000000..4d988fef --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/bin/openblt_evbplus_dragon12p.map @@ -0,0 +1,2801 @@ +*** EVALUATION *** +PROGRAM "C:\Work\software\OpenBLT\Target\Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Boot\bin\openblt_evbplus_dragon12p.abs" + +********************************************************************************************* +TARGET SECTION +--------------------------------------------------------------------------------------------- +Processor : Freescale HC12 +Memory Model: SMALL +File Format : ELF\DWARF 2.0 +Linker : SmartLinker V-5.0.40 Build 10203, Jul 23 2010 + +********************************************************************************************* +FILE SECTION +--------------------------------------------------------------------------------------------- +rtshc12.c.o (ansisi.lib) Model: SMALL, Lang: ANSI-C +mc9s12dg256.c.o Model: SMALL, Lang: ANSI-C +main.c.o Model: SMALL, Lang: ANSI-C +backdoor.c.o Model: SMALL, Lang: ANSI-C +boot.c.o Model: SMALL, Lang: ANSI-C +com.c.o Model: SMALL, Lang: ANSI-C +cop.c.o Model: SMALL, Lang: ANSI-C +xcp.c.o Model: SMALL, Lang: ANSI-C +cpu.c.o Model: SMALL, Lang: ANSI-C +flash.c.o Model: SMALL, Lang: ANSI-C +nvm.c.o Model: SMALL, Lang: ANSI-C +timer.c.o Model: SMALL, Lang: ANSI-C +uart.c.o Model: SMALL, Lang: ANSI-C +start12.c.o Model: SMALL, Lang: ANSI-C +vectors.c.o Model: SMALL, Lang: ANSI-C +assert.c.o Model: SMALL, Lang: ANSI-C + +********************************************************************************************* +STARTUP SECTION +--------------------------------------------------------------------------------------------- +Entry point: 0xE829 (_Startup) +_startupData is allocated at 0xE831 and uses 6 Bytes +extern struct _tagStartup { + unsigned nofZeroOut 1 + _Range pZeroOut 0x3900 1276 + _Copy *toCopyDownBeg 0xF8C3 +} _startupData; + +********************************************************************************************* +SECTION-ALLOCATION SECTION +Section Name Size Type From To Segment +--------------------------------------------------------------------------------------------- +.init 49 R 0xE800 0xE830 ROM_C000 +.startData 10 R 0xE831 0xE83A ROM_C000 +.rodata 190 R 0xE83B 0xE8F8 ROM_C000 +.rodata1 190 R 0xE8F9 0xE9B6 ROM_C000 +.text 3564 R 0xE9B7 0xF7A2 ROM_C000 +.copy 2 R 0xF8C3 0xF8C4 ROM_C000 +ENTRY 12 R 0xFEF0 0xFEFB ENTRY_SEG +.stack 256 R/W 0x3800 0x38FF RAM +.abs_section_8 1 N/I 0x8 0x8 .absSeg0 +.abs_section_9 1 N/I 0x9 0x9 .absSeg1 +.abs_section_a 1 N/I 0xA 0xA .absSeg2 +.abs_section_b 1 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+.abs_section_295 1 N/I 0x295 0x295 .absSeg244 +.abs_section_296 1 N/I 0x296 0x296 .absSeg245 +.abs_section_297 1 N/I 0x297 0x297 .absSeg246 +.abs_section_298 1 N/I 0x298 0x298 .absSeg247 +.abs_section_299 1 N/I 0x299 0x299 .absSeg248 +.abs_section_29a 1 N/I 0x29A 0x29A .absSeg249 +.abs_section_29b 1 N/I 0x29B 0x29B .absSeg250 +.abs_section_29c 1 N/I 0x29C 0x29C .absSeg251 +.abs_section_29d 1 N/I 0x29D 0x29D .absSeg252 +.abs_section_29e 1 N/I 0x29E 0x29E .absSeg253 +.abs_section_29f 1 N/I 0x29F 0x29F .absSeg254 +.abs_section_2a0 1 N/I 0x2A0 0x2A0 .absSeg255 +.abs_section_2a1 1 N/I 0x2A1 0x2A1 .absSeg256 +.abs_section_2a2 1 N/I 0x2A2 0x2A2 .absSeg257 +.abs_section_2a3 1 N/I 0x2A3 0x2A3 .absSeg258 +.abs_section_2a4 1 N/I 0x2A4 0x2A4 .absSeg259 +.abs_section_2a5 1 N/I 0x2A5 0x2A5 .absSeg260 +.abs_section_2a6 1 N/I 0x2A6 0x2A6 .absSeg261 +.abs_section_2a7 1 N/I 0x2A7 0x2A7 .absSeg262 +.abs_section_2a8 1 N/I 0x2A8 0x2A8 .absSeg263 +.abs_section_2a9 1 N/I 0x2A9 0x2A9 .absSeg264 +.abs_section_2aa 1 N/I 0x2AA 0x2AA .absSeg265 +.abs_section_2ab 1 N/I 0x2AB 0x2AB .absSeg266 +.abs_section_2ac 1 N/I 0x2AC 0x2AC .absSeg267 +.abs_section_2b0 1 N/I 0x2B0 0x2B0 .absSeg268 +.abs_section_2b1 1 N/I 0x2B1 0x2B1 .absSeg269 +.abs_section_2b2 1 N/I 0x2B2 0x2B2 .absSeg270 +.abs_section_2b3 1 N/I 0x2B3 0x2B3 .absSeg271 +.abs_section_2b4 1 N/I 0x2B4 0x2B4 .absSeg272 +.abs_section_2b5 1 N/I 0x2B5 0x2B5 .absSeg273 +.abs_section_2b6 1 N/I 0x2B6 0x2B6 .absSeg274 +.abs_section_2b7 1 N/I 0x2B7 0x2B7 .absSeg275 +.abs_section_2b8 1 N/I 0x2B8 0x2B8 .absSeg276 +.abs_section_2b9 1 N/I 0x2B9 0x2B9 .absSeg277 +.abs_section_2ba 1 N/I 0x2BA 0x2BA .absSeg278 +.abs_section_2bb 1 N/I 0x2BB 0x2BB .absSeg279 +.abs_section_2bc 1 N/I 0x2BC 0x2BC .absSeg280 +.abs_section_2bd 1 N/I 0x2BD 0x2BD .absSeg281 +.abs_section_0 2 N/I 0x0 0x1 .absSeg282 +.abs_section_2 2 N/I 0x2 0x3 .absSeg283 +.abs_section_1a 2 N/I 0x1A 0x1B .absSeg284 +.abs_section_44 2 N/I 0x44 0x45 .absSeg285 +.abs_section_50 2 N/I 0x50 0x51 .absSeg286 +.abs_section_52 2 N/I 0x52 0x53 .absSeg287 +.abs_section_54 2 N/I 0x54 0x55 .absSeg288 +.abs_section_56 2 N/I 0x56 0x57 .absSeg289 +.abs_section_58 2 N/I 0x58 0x59 .absSeg290 +.abs_section_5a 2 N/I 0x5A 0x5B .absSeg291 +.abs_section_5c 2 N/I 0x5C 0x5D .absSeg292 +.abs_section_5e 2 N/I 0x5E 0x5F .absSeg293 +.abs_section_62 2 N/I 0x62 0x63 .absSeg294 +.abs_section_64 2 N/I 0x64 0x65 .absSeg295 +.abs_section_72 2 N/I 0x72 0x73 .absSeg296 +.abs_section_74 2 N/I 0x74 0x75 .absSeg297 +.abs_section_76 2 N/I 0x76 0x77 .absSeg298 +.abs_section_78 2 N/I 0x78 0x79 .absSeg299 +.abs_section_7a 2 N/I 0x7A 0x7B .absSeg300 +.abs_section_7c 2 N/I 0x7C 0x7D .absSeg301 +.abs_section_7e 2 N/I 0x7E 0x7F .absSeg302 +.abs_section_82 2 N/I 0x82 0x83 .absSeg303 +.abs_section_84 2 N/I 0x84 0x85 .absSeg304 +.abs_section_90 2 N/I 0x90 0x91 .absSeg305 +.abs_section_92 2 N/I 0x92 0x93 .absSeg306 +.abs_section_94 2 N/I 0x94 0x95 .absSeg307 +.abs_section_96 2 N/I 0x96 0x97 .absSeg308 +.abs_section_98 2 N/I 0x98 0x99 .absSeg309 +.abs_section_9a 2 N/I 0x9A 0x9B .absSeg310 +.abs_section_9c 2 N/I 0x9C 0x9D .absSeg311 +.abs_section_9e 2 N/I 0x9E 0x9F .absSeg312 +.abs_section_ac 2 N/I 0xAC 0xAD .absSeg313 +.abs_section_ae 2 N/I 0xAE 0xAF .absSeg314 +.abs_section_b0 2 N/I 0xB0 0xB1 .absSeg315 +.abs_section_b2 2 N/I 0xB2 0xB3 .absSeg316 +.abs_section_b4 2 N/I 0xB4 0xB5 .absSeg317 +.abs_section_b6 2 N/I 0xB6 0xB7 .absSeg318 +.abs_section_b8 2 N/I 0xB8 0xB9 .absSeg319 +.abs_section_ba 2 N/I 0xBA 0xBB .absSeg320 +.abs_section_bc 2 N/I 0xBC 0xBD .absSeg321 +.abs_section_be 2 N/I 0xBE 0xBF .absSeg322 +.abs_section_c0 2 N/I 0xC0 0xC1 .absSeg323 +.abs_section_c2 2 N/I 0xC2 0xC3 .absSeg324 +.abs_section_c8 2 N/I 0xC8 0xC9 .absSeg325 +.abs_section_d0 2 N/I 0xD0 0xD1 .absSeg326 +.abs_section_122 2 N/I 0x122 0x123 .absSeg327 +.abs_section_124 2 N/I 0x124 0x125 .absSeg328 +.abs_section_130 2 N/I 0x130 0x131 .absSeg329 +.abs_section_132 2 N/I 0x132 0x133 .absSeg330 +.abs_section_134 2 N/I 0x134 0x135 .absSeg331 +.abs_section_136 2 N/I 0x136 0x137 .absSeg332 +.abs_section_138 2 N/I 0x138 0x139 .absSeg333 +.abs_section_13a 2 N/I 0x13A 0x13B .absSeg334 +.abs_section_13c 2 N/I 0x13C 0x13D .absSeg335 +.abs_section_13e 2 N/I 0x13E 0x13F .absSeg336 +.abs_section_16e 2 N/I 0x16E 0x16F .absSeg337 +.abs_section_17e 2 N/I 0x17E 0x17F .absSeg338 +.abs_section_2ae 2 N/I 0x2AE 0x2AF .absSeg339 +.abs_section_2be 2 N/I 0x2BE 0x2BF .absSeg340 +.abs_section_ff80 128 R 0xFF80 0xFFFF .absSeg341 +.bss 1276 R/W 0x3900 0x3DFB RAM +RUNTIME 288 R 0xF7A3 0xF8C2 ROM_C000 + +Summary of section sizes per section type: +READ_ONLY (R): 1151 (dec: 4433) +READ_WRITE (R/W): 5FC (dec: 1532) +NO_INIT (N/I): 190 (dec: 400) + +********************************************************************************************* +VECTOR-ALLOCATION SECTION + Address InitValue InitFunction +--------------------------------------------------------------------------------------------- + +********************************************************************************************* +OBJECT-ALLOCATION SECTION + Name Module Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- +MODULE: -- rtshc12.c.o (ansisi.lib) -- +- PROCEDURES: + _LSHL F7A3 11 17 3 RUNTIME + _LSHRU F7B4 11 17 5 RUNTIME + _LCMP F7C5 19 25 4 RUNTIME + _LINC F7DE 5 5 4 RUNTIME + _LDEC F7E3 8 8 6 RUNTIME + _lDivMod F7EB BE 190 1 RUNTIME + _LDIVU F8A9 E 14 1 RUNTIME + _ILSEXT F8B7 7 7 1 RUNTIME + _CASE_DIRECT_BYTE F8BE 5 5 3 RUNTIME +- VARIABLES: +MODULE: -- mc9s12dg256.c.o -- +- PROCEDURES: +- VARIABLES: + _PORTE 8 1 1 0 .abs_section_8 + _DDRE 9 1 1 0 .abs_section_9 + _PEAR A 1 1 0 .abs_section_a + _MODE B 1 1 0 .abs_section_b + _PUCR C 1 1 0 .abs_section_c + _RDRIV D 1 1 0 .abs_section_d + _EBICTL E 1 1 0 .abs_section_e + _INITRM 10 1 1 0 .abs_section_10 + _INITRG 11 1 1 0 .abs_section_11 + _INITEE 12 1 1 0 .abs_section_12 + _MISC 13 1 1 0 .abs_section_13 + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _INTCR 1E 1 1 0 .abs_section_1e + _HPRIO 1F 1 1 0 .abs_section_1f + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP1X 2D 1 1 0 .abs_section_2d + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _PPAGE 30 1 1 0 .abs_section_30 + _PORTK 32 1 1 0 .abs_section_32 + _DDRK 33 1 1 0 .abs_section_33 + _SYNR 34 1 1 1 .abs_section_34 + _REFDV 35 1 1 1 .abs_section_35 + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CLKSEL 39 1 1 2 .abs_section_39 + _PLLCTL 3A 1 1 0 .abs_section_3a + _RTICTL 3B 1 1 0 .abs_section_3b + _COPCTL 3C 1 1 0 .abs_section_3c + _ARMCOP 3F 1 1 0 .abs_section_3f + _TIOS 40 1 1 0 .abs_section_40 + _CFORC 41 1 1 0 .abs_section_41 + _OC7M 42 1 1 0 .abs_section_42 + _OC7D 43 1 1 0 .abs_section_43 + _TSCR1 46 1 1 0 .abs_section_46 + _TTOV 47 1 1 0 .abs_section_47 + _TCTL1 48 1 1 0 .abs_section_48 + _TCTL2 49 1 1 0 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TIE 4C 1 1 0 .abs_section_4c + _TSCR2 4D 1 1 0 .abs_section_4d + _TFLG1 4E 1 1 0 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _MCCTL 66 1 1 0 .abs_section_66 + _MCFLG 67 1 1 0 .abs_section_67 + _ICPAR 68 1 1 0 .abs_section_68 + _DLYCT 69 1 1 0 .abs_section_69 + _ICOVW 6A 1 1 0 .abs_section_6a + _ICSYS 6B 1 1 0 .abs_section_6b + _PBCTL 70 1 1 0 .abs_section_70 + _PBFLG 71 1 1 0 .abs_section_71 + _ATD0STAT0 86 1 1 0 .abs_section_86 + _ATD0TEST1 89 1 1 0 .abs_section_89 + _ATD0STAT1 8B 1 1 0 .abs_section_8b + _ATD0DIEN 8D 1 1 0 .abs_section_8d + _PORTAD0 8F 1 1 0 .abs_section_8f + _PWME A0 1 1 0 .abs_section_a0 + _PWMPOL A1 1 1 0 .abs_section_a1 + _PWMCLK A2 1 1 0 .abs_section_a2 + _PWMPRCLK A3 1 1 0 .abs_section_a3 + _PWMCAE A4 1 1 0 .abs_section_a4 + _PWMCTL A5 1 1 0 .abs_section_a5 + _PWMSCLA A8 1 1 0 .abs_section_a8 + _PWMSCLB A9 1 1 0 .abs_section_a9 + _PWMSDN C4 1 1 0 .abs_section_c4 + _SCI0CR1 CA 1 1 0 .abs_section_ca + _SCI0CR2 CB 1 1 0 .abs_section_cb + _SCI0SR1 CC 1 1 0 .abs_section_cc + _SCI0SR2 CD 1 1 0 .abs_section_cd + _SCI0DRH CE 1 1 0 .abs_section_ce + _SCI0DRL CF 1 1 0 .abs_section_cf + _SCI1CR1 D2 1 1 0 .abs_section_d2 + _SCI1CR2 D3 1 1 0 .abs_section_d3 + _SCI1SR1 D4 1 1 0 .abs_section_d4 + _SCI1SR2 D5 1 1 0 .abs_section_d5 + _SCI1DRH D6 1 1 0 .abs_section_d6 + _SCI1DRL D7 1 1 0 .abs_section_d7 + _SPI0CR1 D8 1 1 0 .abs_section_d8 + _SPI0CR2 D9 1 1 0 .abs_section_d9 + _SPI0BR DA 1 1 0 .abs_section_da + _SPI0SR DB 1 1 0 .abs_section_db + _SPI0DR DD 1 1 0 .abs_section_dd + _IBAD E0 1 1 0 .abs_section_e0 + _IBFD E1 1 1 0 .abs_section_e1 + _IBCR E2 1 1 0 .abs_section_e2 + _IBSR E3 1 1 0 .abs_section_e3 + _IBDR E4 1 1 0 .abs_section_e4 + _SPI1CR1 F0 1 1 0 .abs_section_f0 + _SPI1CR2 F1 1 1 0 .abs_section_f1 + _SPI1BR F2 1 1 0 .abs_section_f2 + _SPI1SR F3 1 1 0 .abs_section_f3 + _SPI1DR F5 1 1 0 .abs_section_f5 + _SPI2CR1 F8 1 1 0 .abs_section_f8 + _SPI2CR2 F9 1 1 0 .abs_section_f9 + _SPI2BR FA 1 1 0 .abs_section_fa + _SPI2SR FB 1 1 0 .abs_section_fb + _SPI2DR FD 1 1 0 .abs_section_fd + _FCLKDIV 100 1 1 0 .abs_section_100 + _FSEC 101 1 1 0 .abs_section_101 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSTAT 105 1 1 0 .abs_section_105 + _FCMD 106 1 1 0 .abs_section_106 + _ECLKDIV 110 1 1 0 .abs_section_110 + _ECNFG 113 1 1 0 .abs_section_113 + _EPROT 114 1 1 0 .abs_section_114 + _ESTAT 115 1 1 0 .abs_section_115 + _ECMD 116 1 1 0 .abs_section_116 + _ATD1STAT0 126 1 1 0 .abs_section_126 + _ATD1TEST1 129 1 1 0 .abs_section_129 + _ATD1STAT1 12B 1 1 0 .abs_section_12b + _ATD1DIEN 12D 1 1 0 .abs_section_12d + _PORTAD1 12F 1 1 0 .abs_section_12f + _CAN0CTL0 140 1 1 0 .abs_section_140 + _CAN0CTL1 141 1 1 0 .abs_section_141 + _CAN0BTR0 142 1 1 0 .abs_section_142 + _CAN0BTR1 143 1 1 0 .abs_section_143 + _CAN0RFLG 144 1 1 0 .abs_section_144 + _CAN0RIER 145 1 1 0 .abs_section_145 + _CAN0TFLG 146 1 1 0 .abs_section_146 + _CAN0TIER 147 1 1 0 .abs_section_147 + _CAN0TARQ 148 1 1 0 .abs_section_148 + _CAN0TAAK 149 1 1 0 .abs_section_149 + _CAN0TBSEL 14A 1 1 0 .abs_section_14a + _CAN0IDAC 14B 1 1 0 .abs_section_14b + _CAN0RXERR 14E 1 1 0 .abs_section_14e + _CAN0TXERR 14F 1 1 0 .abs_section_14f + _CAN0IDAR0 150 1 1 0 .abs_section_150 + _CAN0IDAR1 151 1 1 0 .abs_section_151 + _CAN0IDAR2 152 1 1 0 .abs_section_152 + _CAN0IDAR3 153 1 1 0 .abs_section_153 + _CAN0IDMR0 154 1 1 0 .abs_section_154 + _CAN0IDMR1 155 1 1 0 .abs_section_155 + _CAN0IDMR2 156 1 1 0 .abs_section_156 + _CAN0IDMR3 157 1 1 0 .abs_section_157 + _CAN0IDAR4 158 1 1 0 .abs_section_158 + _CAN0IDAR5 159 1 1 0 .abs_section_159 + _CAN0IDAR6 15A 1 1 0 .abs_section_15a + _CAN0IDAR7 15B 1 1 0 .abs_section_15b + _CAN0IDMR4 15C 1 1 0 .abs_section_15c + _CAN0IDMR5 15D 1 1 0 .abs_section_15d + _CAN0IDMR6 15E 1 1 0 .abs_section_15e + _CAN0IDMR7 15F 1 1 0 .abs_section_15f + _CAN0RXIDR0 160 1 1 0 .abs_section_160 + _CAN0RXIDR1 161 1 1 0 .abs_section_161 + _CAN0RXIDR2 162 1 1 0 .abs_section_162 + _CAN0RXIDR3 163 1 1 0 .abs_section_163 + _CAN0RXDSR0 164 1 1 0 .abs_section_164 + _CAN0RXDSR1 165 1 1 0 .abs_section_165 + _CAN0RXDSR2 166 1 1 0 .abs_section_166 + _CAN0RXDSR3 167 1 1 0 .abs_section_167 + _CAN0RXDSR4 168 1 1 0 .abs_section_168 + _CAN0RXDSR5 169 1 1 0 .abs_section_169 + _CAN0RXDSR6 16A 1 1 0 .abs_section_16a + _CAN0RXDSR7 16B 1 1 0 .abs_section_16b + _CAN0RXDLR 16C 1 1 0 .abs_section_16c + _CAN0TXIDR0 170 1 1 0 .abs_section_170 + _CAN0TXIDR1 171 1 1 0 .abs_section_171 + _CAN0TXIDR2 172 1 1 0 .abs_section_172 + _CAN0TXIDR3 173 1 1 0 .abs_section_173 + _CAN0TXDSR0 174 1 1 0 .abs_section_174 + _CAN0TXDSR1 175 1 1 0 .abs_section_175 + _CAN0TXDSR2 176 1 1 0 .abs_section_176 + _CAN0TXDSR3 177 1 1 0 .abs_section_177 + _CAN0TXDSR4 178 1 1 0 .abs_section_178 + _CAN0TXDSR5 179 1 1 0 .abs_section_179 + _CAN0TXDSR6 17A 1 1 0 .abs_section_17a + _CAN0TXDSR7 17B 1 1 0 .abs_section_17b + _CAN0TXDLR 17C 1 1 0 .abs_section_17c + _CAN0TXTBPR 17D 1 1 0 .abs_section_17d + _PTT 240 1 1 0 .abs_section_240 + _PTIT 241 1 1 0 .abs_section_241 + _DDRT 242 1 1 0 .abs_section_242 + _RDRT 243 1 1 0 .abs_section_243 + _PERT 244 1 1 0 .abs_section_244 + _PPST 245 1 1 0 .abs_section_245 + _PTS 248 1 1 0 .abs_section_248 + _PTIS 249 1 1 0 .abs_section_249 + _DDRS 24A 1 1 0 .abs_section_24a + _RDRS 24B 1 1 0 .abs_section_24b + _PERS 24C 1 1 0 .abs_section_24c + _PPSS 24D 1 1 0 .abs_section_24d + _WOMS 24E 1 1 0 .abs_section_24e + _PTM 250 1 1 0 .abs_section_250 + _PTIM 251 1 1 0 .abs_section_251 + _DDRM 252 1 1 0 .abs_section_252 + _RDRM 253 1 1 0 .abs_section_253 + _PERM 254 1 1 0 .abs_section_254 + _PPSM 255 1 1 0 .abs_section_255 + _WOMM 256 1 1 0 .abs_section_256 + _MODRR 257 1 1 0 .abs_section_257 + _PTP 258 1 1 0 .abs_section_258 + _PTIP 259 1 1 0 .abs_section_259 + _DDRP 25A 1 1 0 .abs_section_25a + _RDRP 25B 1 1 0 .abs_section_25b + _PERP 25C 1 1 0 .abs_section_25c + _PPSP 25D 1 1 0 .abs_section_25d + _PIEP 25E 1 1 0 .abs_section_25e + _PIFP 25F 1 1 0 .abs_section_25f + _PTH 260 1 1 0 .abs_section_260 + _PTIH 261 1 1 0 .abs_section_261 + _DDRH 262 1 1 0 .abs_section_262 + _RDRH 263 1 1 0 .abs_section_263 + _PERH 264 1 1 0 .abs_section_264 + _PPSH 265 1 1 0 .abs_section_265 + _PIEH 266 1 1 0 .abs_section_266 + _PIFH 267 1 1 0 .abs_section_267 + _PTJ 268 1 1 0 .abs_section_268 + _PTIJ 269 1 1 0 .abs_section_269 + _DDRJ 26A 1 1 0 .abs_section_26a + _RDRJ 26B 1 1 0 .abs_section_26b + _PERJ 26C 1 1 0 .abs_section_26c + _PPSJ 26D 1 1 0 .abs_section_26d + _PIEJ 26E 1 1 0 .abs_section_26e + _PIFJ 26F 1 1 0 .abs_section_26f + _CAN4CTL0 280 1 1 0 .abs_section_280 + _CAN4CTL1 281 1 1 0 .abs_section_281 + _CAN4BTR0 282 1 1 0 .abs_section_282 + _CAN4BTR1 283 1 1 0 .abs_section_283 + _CAN4RFLG 284 1 1 0 .abs_section_284 + _CAN4RIER 285 1 1 0 .abs_section_285 + _CAN4TFLG 286 1 1 0 .abs_section_286 + _CAN4TIER 287 1 1 0 .abs_section_287 + _CAN4TARQ 288 1 1 0 .abs_section_288 + _CAN4TAAK 289 1 1 0 .abs_section_289 + _CAN4TBSEL 28A 1 1 0 .abs_section_28a + _CAN4IDAC 28B 1 1 0 .abs_section_28b + _CAN4RXERR 28E 1 1 0 .abs_section_28e + _CAN4TXERR 28F 1 1 0 .abs_section_28f + _CAN4IDAR0 290 1 1 0 .abs_section_290 + _CAN4IDAR1 291 1 1 0 .abs_section_291 + _CAN4IDAR2 292 1 1 0 .abs_section_292 + _CAN4IDAR3 293 1 1 0 .abs_section_293 + _CAN4IDMR0 294 1 1 0 .abs_section_294 + _CAN4IDMR1 295 1 1 0 .abs_section_295 + _CAN4IDMR2 296 1 1 0 .abs_section_296 + _CAN4IDMR3 297 1 1 0 .abs_section_297 + _CAN4IDAR4 298 1 1 0 .abs_section_298 + _CAN4IDAR5 299 1 1 0 .abs_section_299 + _CAN4IDAR6 29A 1 1 0 .abs_section_29a + _CAN4IDAR7 29B 1 1 0 .abs_section_29b + _CAN4IDMR4 29C 1 1 0 .abs_section_29c + _CAN4IDMR5 29D 1 1 0 .abs_section_29d + _CAN4IDMR6 29E 1 1 0 .abs_section_29e + _CAN4IDMR7 29F 1 1 0 .abs_section_29f + _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 + _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 + _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 + _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 + _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 + _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 + _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 + _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 + _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 + _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 + _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa + _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab + _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac + _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 + _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 + _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 + _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 + _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 + _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 + _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 + _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 + _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 + _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 + _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba + _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb + _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc + _CAN4TXTBPR 2BD 1 1 0 .abs_section_2bd + _PORTAB 0 2 2 0 .abs_section_0 + _DDRAB 2 2 2 0 .abs_section_2 + _PARTID 1A 2 2 0 .abs_section_1a + _TCNT 44 2 2 0 .abs_section_44 + _TC0 50 2 2 0 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 0 .abs_section_5e + _PACN32 62 2 2 0 .abs_section_62 + _PACN10 64 2 2 0 .abs_section_64 + _PA32H 72 2 2 0 .abs_section_72 + _PA10H 74 2 2 0 .abs_section_74 + _MCCNT 76 2 2 0 .abs_section_76 + _TC0H 78 2 2 0 .abs_section_78 + _TC1H 7A 2 2 0 .abs_section_7a + _TC2H 7C 2 2 0 .abs_section_7c + _TC3H 7E 2 2 0 .abs_section_7e + _ATD0CTL23 82 2 2 0 .abs_section_82 + _ATD0CTL45 84 2 2 0 .abs_section_84 + _ATD0DR0 90 2 2 0 .abs_section_90 + _ATD0DR1 92 2 2 0 .abs_section_92 + _ATD0DR2 94 2 2 0 .abs_section_94 + _ATD0DR3 96 2 2 0 .abs_section_96 + _ATD0DR4 98 2 2 0 .abs_section_98 + _ATD0DR5 9A 2 2 0 .abs_section_9a + _ATD0DR6 9C 2 2 0 .abs_section_9c + _ATD0DR7 9E 2 2 0 .abs_section_9e + _PWMCNT01 AC 2 2 0 .abs_section_ac + _PWMCNT23 AE 2 2 0 .abs_section_ae + _PWMCNT45 B0 2 2 0 .abs_section_b0 + _PWMCNT67 B2 2 2 0 .abs_section_b2 + _PWMPER01 B4 2 2 0 .abs_section_b4 + _PWMPER23 B6 2 2 0 .abs_section_b6 + _PWMPER45 B8 2 2 0 .abs_section_b8 + _PWMPER67 BA 2 2 0 .abs_section_ba + _PWMDTY01 BC 2 2 0 .abs_section_bc + _PWMDTY23 BE 2 2 0 .abs_section_be + _PWMDTY45 C0 2 2 0 .abs_section_c0 + _PWMDTY67 C2 2 2 0 .abs_section_c2 + _SCI0BD C8 2 2 0 .abs_section_c8 + _SCI1BD D0 2 2 0 .abs_section_d0 + _ATD1CTL23 122 2 2 0 .abs_section_122 + _ATD1CTL45 124 2 2 0 .abs_section_124 + _ATD1DR0 130 2 2 0 .abs_section_130 + _ATD1DR1 132 2 2 0 .abs_section_132 + _ATD1DR2 134 2 2 0 .abs_section_134 + _ATD1DR3 136 2 2 0 .abs_section_136 + _ATD1DR4 138 2 2 0 .abs_section_138 + _ATD1DR5 13A 2 2 0 .abs_section_13a + _ATD1DR6 13C 2 2 0 .abs_section_13c + _ATD1DR7 13E 2 2 0 .abs_section_13e + _CAN0RXTSR 16E 2 2 0 .abs_section_16e + _CAN0TXTSR 17E 2 2 0 .abs_section_17e + _CAN4RXTSR 2AE 2 2 0 .abs_section_2ae + _CAN4TXTSR 2BE 2 2 0 .abs_section_2be +MODULE: -- main.c.o -- +- PROCEDURES: + main E9B7 B 11 3 .text + Init E9C2 79 121 1 .text +- VARIABLES: + STRING.C..Work.software.Ope.1 E8F9 55 85 1 .rodata1 +MODULE: -- backdoor.c.o -- +- PROCEDURES: + BackDoorInit EA3B 11 17 1 .text + BackDoorCheck EA4C 31 49 2 .text +- VARIABLES: + backdoorOpen 3900 1 1 3 .bss + backdoorOpenTime 3901 4 4 4 .bss +MODULE: -- boot.c.o -- +- PROCEDURES: + BootInit EA7D F 15 1 .text + BootTask EA8C C 12 1 .text +- VARIABLES: +MODULE: -- com.c.o -- +- PROCEDURES: + ComInit EA98 19 25 1 .text + ComTask EAB1 10 16 1 .text + ComFree EAC1 1 1 1 .text + ComTransmitPacket EAC2 F 15 1 .text + ComSetConnectEntryState EAD1 6 6 1 .text + ComIsConnected EAD7 4 4 1 .text +- VARIABLES: + comEntryStateConnect 3905 1 1 2 .bss + xcpCtoReqPacket.1 3906 40 64 2 .bss +MODULE: -- cop.c.o -- +- PROCEDURES: + CopInit EADB 1 1 1 .text + CopService EADC 1 1 8 .text +- VARIABLES: +MODULE: -- xcp.c.o -- +- PROCEDURES: + XcpInit EADD 15 21 1 .text + XcpIsConnected EAF2 9 9 1 .text + XcpPacketTransmitted EAFB 4 4 1 .text + XcpPacketReceived EAFF E7 231 2 .text + XcpTransmitPacket EBE6 C 12 1 .text + XcpComputeChecksum EBF2 43 67 1 .text + XcpProtectResources EC35 4 4 2 .text + XcpSetCtoError EC39 10 16 9 .text + XcpCmdConnect EC49 2A 42 1 .text + XcpCmdDisconnect EC73 10 16 1 .text + XcpCmdGetStatus EC83 1A 26 1 .text + XcpCmdSynch EC9D 4 4 1 .text + XcpCmdGetId ECA1 22 34 1 .text + XcpCmdSetMta ECC3 1A 26 1 .text + XcpCmdUpload ECDD 4E 78 1 .text + XcpCmdShortUpload ED2B 55 85 1 .text + XcpCmdBuildCheckSum ED80 2C 44 1 .text + XcpCmdProgramStart EDAC 19 25 1 .text + XcpCmdProgramMax EDC5 43 67 1 .text + XcpCmdProgram EE08 5B 91 1 .text + XcpCmdProgramClear EE63 2A 42 1 .text + XcpCmdProgramReset EE8D E 14 1 .text + XcpCmdProgramPrepare EE9B 5 5 1 .text +- VARIABLES: + xcpStationId E83B 8 8 1 .rodata + xcpInfo 3946 4A 74 102 .bss +MODULE: -- cpu.c.o -- +- PROCEDURES: + CpuStartUserProgram EEA0 18 24 1 .text + CpuMemCopy EEB8 27 39 4 .text + CpuReset EEDF 3 3 1 .text +- VARIABLES: +MODULE: -- flash.c.o -- +- PROCEDURES: + FlashInit EEE2 74 116 1 .text + FlashWrite EF56 B6 182 2 .text + FlashErase F00C DD 221 1 .text + FlashWriteChecksum F0E9 67 103 1 .text + FlashVerifyChecksum F150 8A 138 1 .text + FlashDone F1DA 35 53 1 .text + FlashInitBlock F20F 51 81 2 .text + FlashSwitchBlock F260 4E 78 2 .text + FlashAddToBlock F2AE BD 189 1 .text + FlashWriteBlock F36B 78 120 3 .text + FlashGetLinearAddrByte F3E3 1D 29 5 .text + FlashGetPhysPage F400 C 12 3 .text + FlashGetPhysAddr F40C 6 6 3 .text + FlashExecuteCommand F412 1F 31 1 .text + FlashOperate F431 54 84 2 .text +- VARIABLES: + flashLayout E843 A0 160 39 .rodata + flashExecCmd E8E3 16 22 1 .rodata + STRING.C..Work.software.Ope.1 E94E 35 53 1 .rodata1 + blockInfo 3990 204 516 7 .bss + bootBlockInfo 3B94 204 516 11 .bss + flashExecCmdRam 3D98 16 22 2 .bss + flashMaxNrBlocks 3DAE 1 1 1 .bss +MODULE: -- nvm.c.o -- +- PROCEDURES: + NvmInit F485 3 3 1 .text + NvmWrite F488 16 22 2 .text + NvmErase F49E 12 18 1 .text + NvmVerifyChecksum F4B0 4 4 1 .text + NvmDone F4B4 B 11 1 .text +- VARIABLES: +MODULE: -- timer.c.o -- +- PROCEDURES: + TimerInit F4BF 1D 29 1 .text + TimerReset F4DC 1C 28 2 .text + TimerUpdate F4F8 1F 31 2 .text + TimerGet F517 9 9 2 .text +- VARIABLES: + millisecond_counter 3DAF 4 4 8 .bss +MODULE: -- uart.c.o -- +- PROCEDURES: + UartInit F520 19 25 1 .text + UartTransmitPacket F539 5E 94 1 .text + UartReceivePacket F597 50 80 1 .text + UartReceiveByte F5E7 11 17 2 .text + UartTransmitByte F5F8 14 20 2 .text +- VARIABLES: + STRING.C..Work.software.Ope.1 E983 34 52 3 .rodata1 + xcpCtoRxInProgress.4 3DB3 1 1 3 .bss + xcpCtoReqPacket.2 3DB4 41 65 4 .bss + xcpCtoRxLength.3 3DF5 1 1 5 .bss +MODULE: -- start12.c.o -- +- PROCEDURES: + Init E800 29 41 1 .init + _Startup E829 8 8 2 .init +- VARIABLES: + _startupData E831 6 6 3 .startData +- LABELS: + __SEG_END_SSTACK 3900 0 0 3 +MODULE: -- vectors.c.o -- +- PROCEDURES: + reset_handler F60C 9 9 2 .text + Vector0_handler F615 6 6 1 .text + Vector1_handler F61B 6 6 1 .text + Vector2_handler F621 6 6 1 .text + Vector3_handler F627 6 6 1 .text + Vector4_handler F62D 6 6 1 .text + Vector5_handler F633 6 6 1 .text + Vector6_handler F639 6 6 1 .text + Vector7_handler F63F 6 6 1 .text + Vector8_handler F645 6 6 1 .text + Vector9_handler F64B 6 6 1 .text + Vector10_handler F651 6 6 1 .text + Vector11_handler F657 6 6 1 .text + Vector12_handler F65D 6 6 1 .text + Vector13_handler F663 6 6 1 .text + Vector14_handler F669 6 6 1 .text + Vector15_handler F66F 6 6 1 .text + Vector16_handler F675 6 6 1 .text + Vector17_handler F67B 6 6 1 .text + Vector18_handler F681 6 6 1 .text + Vector19_handler F687 6 6 1 .text + Vector20_handler F68D 6 6 1 .text + Vector21_handler F693 6 6 1 .text + Vector22_handler F699 6 6 1 .text + Vector23_handler F69F 6 6 1 .text + Vector24_handler F6A5 6 6 1 .text + Vector25_handler F6AB 6 6 1 .text + Vector26_handler F6B1 6 6 1 .text + Vector27_handler F6B7 6 6 1 .text + Vector28_handler F6BD 6 6 1 .text + Vector29_handler F6C3 6 6 1 .text + Vector30_handler F6C9 6 6 1 .text + Vector31_handler F6CF 6 6 1 .text + Vector32_handler F6D5 6 6 1 .text + Vector33_handler F6DB 6 6 1 .text + Vector34_handler F6E1 6 6 1 .text + Vector35_handler F6E7 6 6 1 .text + Vector36_handler F6ED 6 6 1 .text + Vector37_handler F6F3 6 6 1 .text + Vector38_handler F6F9 6 6 1 .text + Vector39_handler F6FF 6 6 1 .text + Vector40_handler F705 6 6 1 .text + Vector41_handler F70B 6 6 1 .text + Vector42_handler F711 6 6 1 .text + Vector43_handler F717 6 6 1 .text + Vector44_handler F71D 6 6 1 .text + Vector45_handler F723 6 6 1 .text + Vector46_handler F729 6 6 1 .text + Vector47_handler F72F 6 6 1 .text + Vector48_handler F735 6 6 1 .text + Vector49_handler F73B 6 6 1 .text + Vector50_handler F741 6 6 1 .text + Vector51_handler F747 6 6 1 .text + Vector52_handler F74D 6 6 1 .text + Vector53_handler F753 6 6 1 .text + Vector54_handler F759 6 6 1 .text + Vector55_handler F75F 6 6 1 .text + Vector56_handler F765 6 6 1 .text + Vector57_handler F76B 6 6 1 .text + Vector58_handler F771 6 6 1 .text + Vector59_handler F777 6 6 1 .text + Vector60_handler F77D 6 6 1 .text + Vector61_handler F783 6 6 1 .text + Vector62_handler F789 6 6 1 .text + reset_connected_handler FEF0 C 12 0 ENTRY +- VARIABLES: + _vectab FF80 80 128 0 .abs_section_ff80 +MODULE: -- assert.c.o -- +- PROCEDURES: + AssertFailure F78F 14 20 5 .text +- VARIABLES: + assert_failure_file 3DF6 2 2 1 .bss + assert_failure_line 3DF8 4 4 2 .bss + +********************************************************************************************* +MODULE STATISTIC + Name Data Code Const +--------------------------------------------------------------------------------------------- + rtshc12.c.o (ansisi.lib) 0 288 0 + mc9s12dg256.c.o 400 0 0 + main.c.o 0 132 85 + backdoor.c.o 5 66 0 + boot.c.o 0 27 0 + com.c.o 65 67 0 + cop.c.o 0 2 0 + xcp.c.o 74 963 8 + cpu.c.o 0 66 0 + flash.c.o 1055 1443 235 + nvm.c.o 0 58 0 + timer.c.o 4 97 0 + uart.c.o 67 236 52 + start12.c.o 0 49 0 + vectors.c.o 0 399 128 + assert.c.o 6 20 0 + other 256 10 2 + +********************************************************************************************* +SECTION USE IN OBJECT-ALLOCATION SECTION +--------------------------------------------------------------------------------------------- +SECTION: ".text" + main Init BackDoorInit BackDoorCheck BootInit BootTask ComInit ComTask + ComFree ComTransmitPacket ComSetConnectEntryState ComIsConnected CopInit + CopService XcpInit XcpIsConnected XcpPacketTransmitted XcpPacketReceived + XcpTransmitPacket XcpComputeChecksum XcpProtectResources XcpSetCtoError + XcpCmdConnect XcpCmdDisconnect XcpCmdGetStatus XcpCmdSynch XcpCmdGetId + XcpCmdSetMta XcpCmdUpload XcpCmdShortUpload XcpCmdBuildCheckSum + XcpCmdProgramStart XcpCmdProgramMax XcpCmdProgram XcpCmdProgramClear + XcpCmdProgramReset XcpCmdProgramPrepare CpuStartUserProgram CpuMemCopy + CpuReset FlashInit FlashWrite FlashErase FlashWriteChecksum + FlashVerifyChecksum FlashDone FlashInitBlock FlashSwitchBlock FlashAddToBlock + FlashWriteBlock FlashGetLinearAddrByte FlashGetPhysPage FlashGetPhysAddr + FlashExecuteCommand FlashOperate NvmInit NvmWrite NvmErase NvmVerifyChecksum + NvmDone TimerInit TimerReset TimerUpdate TimerGet UartInit UartTransmitPacket + UartReceivePacket UartReceiveByte UartTransmitByte reset_handler + Vector0_handler Vector1_handler Vector2_handler Vector3_handler + Vector4_handler Vector5_handler Vector6_handler Vector7_handler + Vector8_handler Vector9_handler Vector10_handler Vector11_handler + Vector12_handler Vector13_handler Vector14_handler Vector15_handler + Vector16_handler Vector17_handler Vector18_handler Vector19_handler + Vector20_handler Vector21_handler Vector22_handler Vector23_handler + Vector24_handler Vector25_handler Vector26_handler Vector27_handler + Vector28_handler Vector29_handler Vector30_handler Vector31_handler + Vector32_handler Vector33_handler Vector34_handler Vector35_handler + Vector36_handler Vector37_handler Vector38_handler Vector39_handler + Vector40_handler Vector41_handler Vector42_handler Vector43_handler + Vector44_handler Vector45_handler Vector46_handler Vector47_handler + Vector48_handler Vector49_handler Vector50_handler Vector51_handler + Vector52_handler Vector53_handler Vector54_handler Vector55_handler + Vector56_handler Vector57_handler Vector58_handler Vector59_handler + Vector60_handler Vector61_handler Vector62_handler AssertFailure +SECTION: ".bss" + backdoorOpen backdoorOpenTime comEntryStateConnect xcpCtoReqPacket.1 xcpInfo + blockInfo bootBlockInfo flashExecCmdRam flashMaxNrBlocks millisecond_counter + xcpCtoRxInProgress.4 xcpCtoReqPacket.2 xcpCtoRxLength.3 assert_failure_file + assert_failure_line +SECTION: ".init" + Init _Startup +SECTION: ".rodata" + xcpStationId flashLayout flashExecCmd +SECTION: ".rodata1" + STRING.C..Work.software.Ope.1 STRING.C..Work.software.Ope.1 + STRING.C..Work.software.Ope.1 +SECTION: "ENTRY" + reset_connected_handler +SECTION: "RUNTIME" + _LSHL _LSHRU _LCMP _LINC _LDEC _lDivMod _LDIVU _ILSEXT _CASE_DIRECT_BYTE +SECTION: ".abs_section_8" + _PORTE +SECTION: ".abs_section_9" + _DDRE +SECTION: ".abs_section_a" + _PEAR +SECTION: ".abs_section_b" + _MODE +SECTION: ".abs_section_c" + _PUCR +SECTION: ".abs_section_d" + _RDRIV +SECTION: ".abs_section_e" + _EBICTL +SECTION: ".abs_section_10" + _INITRM +SECTION: ".abs_section_11" + _INITRG +SECTION: ".abs_section_12" + _INITEE +SECTION: ".abs_section_13" + _MISC +SECTION: ".abs_section_15" + _ITCR +SECTION: ".abs_section_16" + _ITEST +SECTION: ".abs_section_1c" + _MEMSIZ0 +SECTION: ".abs_section_1d" + _MEMSIZ1 +SECTION: ".abs_section_1e" + _INTCR +SECTION: ".abs_section_1f" + _HPRIO +SECTION: ".abs_section_28" + _BKPCT0 +SECTION: ".abs_section_29" + _BKPCT1 +SECTION: ".abs_section_2a" + _BKP0X +SECTION: ".abs_section_2b" + _BKP0H +SECTION: ".abs_section_2c" + _BKP0L +SECTION: ".abs_section_2d" + _BKP1X +SECTION: ".abs_section_2e" + _BKP1H +SECTION: ".abs_section_2f" + _BKP1L +SECTION: ".abs_section_30" + _PPAGE +SECTION: ".abs_section_32" + _PORTK +SECTION: ".abs_section_33" + _DDRK +SECTION: ".abs_section_34" + _SYNR +SECTION: ".abs_section_35" + _REFDV +SECTION: ".abs_section_37" + _CRGFLG +SECTION: ".abs_section_38" + _CRGINT +SECTION: ".abs_section_39" + _CLKSEL +SECTION: ".abs_section_3a" + _PLLCTL +SECTION: ".abs_section_3b" + _RTICTL +SECTION: ".abs_section_3c" + _COPCTL +SECTION: ".abs_section_3f" + _ARMCOP +SECTION: ".abs_section_40" + _TIOS +SECTION: ".abs_section_41" + _CFORC +SECTION: ".abs_section_42" + _OC7M +SECTION: ".abs_section_43" + _OC7D +SECTION: ".abs_section_46" + _TSCR1 +SECTION: ".abs_section_47" + _TTOV +SECTION: ".abs_section_48" + _TCTL1 +SECTION: ".abs_section_49" + _TCTL2 +SECTION: ".abs_section_4a" + _TCTL3 +SECTION: ".abs_section_4b" + _TCTL4 +SECTION: ".abs_section_4c" + _TIE +SECTION: ".abs_section_4d" + _TSCR2 +SECTION: ".abs_section_4e" + _TFLG1 +SECTION: ".abs_section_4f" + _TFLG2 +SECTION: ".abs_section_60" + _PACTL +SECTION: ".abs_section_61" + _PAFLG +SECTION: ".abs_section_66" + _MCCTL +SECTION: ".abs_section_67" + _MCFLG +SECTION: ".abs_section_68" + _ICPAR +SECTION: ".abs_section_69" + _DLYCT +SECTION: ".abs_section_6a" + _ICOVW +SECTION: ".abs_section_6b" + _ICSYS +SECTION: ".abs_section_70" + _PBCTL +SECTION: ".abs_section_71" + _PBFLG +SECTION: ".abs_section_86" + _ATD0STAT0 +SECTION: ".abs_section_89" + _ATD0TEST1 +SECTION: ".abs_section_8b" + _ATD0STAT1 +SECTION: ".abs_section_8d" + _ATD0DIEN +SECTION: ".abs_section_8f" + _PORTAD0 +SECTION: ".abs_section_a0" + _PWME +SECTION: ".abs_section_a1" + _PWMPOL +SECTION: ".abs_section_a2" + _PWMCLK +SECTION: ".abs_section_a3" + _PWMPRCLK +SECTION: ".abs_section_a4" + _PWMCAE +SECTION: ".abs_section_a5" + _PWMCTL +SECTION: ".abs_section_a8" + _PWMSCLA +SECTION: ".abs_section_a9" + _PWMSCLB +SECTION: ".abs_section_c4" + _PWMSDN +SECTION: ".abs_section_ca" + _SCI0CR1 +SECTION: ".abs_section_cb" + _SCI0CR2 +SECTION: ".abs_section_cc" + _SCI0SR1 +SECTION: ".abs_section_cd" + _SCI0SR2 +SECTION: ".abs_section_ce" + _SCI0DRH +SECTION: ".abs_section_cf" + _SCI0DRL +SECTION: ".abs_section_d2" + _SCI1CR1 +SECTION: ".abs_section_d3" + _SCI1CR2 +SECTION: ".abs_section_d4" + _SCI1SR1 +SECTION: ".abs_section_d5" + _SCI1SR2 +SECTION: ".abs_section_d6" + _SCI1DRH +SECTION: ".abs_section_d7" + _SCI1DRL +SECTION: ".abs_section_d8" + _SPI0CR1 +SECTION: ".abs_section_d9" + _SPI0CR2 +SECTION: ".abs_section_da" + _SPI0BR +SECTION: ".abs_section_db" + _SPI0SR +SECTION: ".abs_section_dd" + _SPI0DR +SECTION: ".abs_section_e0" + _IBAD +SECTION: ".abs_section_e1" + _IBFD +SECTION: ".abs_section_e2" + _IBCR +SECTION: ".abs_section_e3" + _IBSR +SECTION: ".abs_section_e4" + _IBDR +SECTION: ".abs_section_f0" + _SPI1CR1 +SECTION: ".abs_section_f1" + _SPI1CR2 +SECTION: ".abs_section_f2" + _SPI1BR +SECTION: ".abs_section_f3" + _SPI1SR +SECTION: ".abs_section_f5" + _SPI1DR +SECTION: ".abs_section_f8" + _SPI2CR1 +SECTION: ".abs_section_f9" + _SPI2CR2 +SECTION: ".abs_section_fa" + _SPI2BR +SECTION: ".abs_section_fb" + _SPI2SR +SECTION: ".abs_section_fd" + _SPI2DR +SECTION: ".abs_section_100" + _FCLKDIV +SECTION: ".abs_section_101" + _FSEC +SECTION: ".abs_section_103" + _FCNFG +SECTION: ".abs_section_104" + _FPROT +SECTION: ".abs_section_105" + _FSTAT +SECTION: ".abs_section_106" + _FCMD +SECTION: ".abs_section_110" + _ECLKDIV +SECTION: ".abs_section_113" + _ECNFG +SECTION: ".abs_section_114" + _EPROT +SECTION: ".abs_section_115" + _ESTAT +SECTION: ".abs_section_116" + _ECMD +SECTION: ".abs_section_126" + _ATD1STAT0 +SECTION: ".abs_section_129" + _ATD1TEST1 +SECTION: ".abs_section_12b" + _ATD1STAT1 +SECTION: ".abs_section_12d" + _ATD1DIEN +SECTION: ".abs_section_12f" + _PORTAD1 +SECTION: ".abs_section_140" + _CAN0CTL0 +SECTION: ".abs_section_141" + _CAN0CTL1 +SECTION: ".abs_section_142" + _CAN0BTR0 +SECTION: ".abs_section_143" + _CAN0BTR1 +SECTION: ".abs_section_144" + _CAN0RFLG +SECTION: ".abs_section_145" + _CAN0RIER +SECTION: ".abs_section_146" + _CAN0TFLG +SECTION: ".abs_section_147" + _CAN0TIER +SECTION: ".abs_section_148" + _CAN0TARQ +SECTION: ".abs_section_149" + _CAN0TAAK +SECTION: ".abs_section_14a" + _CAN0TBSEL +SECTION: ".abs_section_14b" + _CAN0IDAC +SECTION: ".abs_section_14e" + _CAN0RXERR +SECTION: ".abs_section_14f" + _CAN0TXERR +SECTION: ".abs_section_150" + _CAN0IDAR0 +SECTION: ".abs_section_151" + _CAN0IDAR1 +SECTION: ".abs_section_152" + _CAN0IDAR2 +SECTION: ".abs_section_153" + _CAN0IDAR3 +SECTION: ".abs_section_154" + _CAN0IDMR0 +SECTION: ".abs_section_155" + _CAN0IDMR1 +SECTION: ".abs_section_156" + _CAN0IDMR2 +SECTION: ".abs_section_157" + _CAN0IDMR3 +SECTION: ".abs_section_158" + _CAN0IDAR4 +SECTION: ".abs_section_159" + _CAN0IDAR5 +SECTION: ".abs_section_15a" + _CAN0IDAR6 +SECTION: ".abs_section_15b" + _CAN0IDAR7 +SECTION: ".abs_section_15c" + _CAN0IDMR4 +SECTION: ".abs_section_15d" + _CAN0IDMR5 +SECTION: ".abs_section_15e" + _CAN0IDMR6 +SECTION: ".abs_section_15f" + _CAN0IDMR7 +SECTION: ".abs_section_160" + _CAN0RXIDR0 +SECTION: ".abs_section_161" + _CAN0RXIDR1 +SECTION: ".abs_section_162" + _CAN0RXIDR2 +SECTION: ".abs_section_163" + _CAN0RXIDR3 +SECTION: ".abs_section_164" + _CAN0RXDSR0 +SECTION: ".abs_section_165" + _CAN0RXDSR1 +SECTION: ".abs_section_166" + _CAN0RXDSR2 +SECTION: ".abs_section_167" + _CAN0RXDSR3 +SECTION: ".abs_section_168" + _CAN0RXDSR4 +SECTION: ".abs_section_169" + _CAN0RXDSR5 +SECTION: ".abs_section_16a" + _CAN0RXDSR6 +SECTION: ".abs_section_16b" + _CAN0RXDSR7 +SECTION: ".abs_section_16c" + _CAN0RXDLR +SECTION: ".abs_section_170" + _CAN0TXIDR0 +SECTION: ".abs_section_171" + _CAN0TXIDR1 +SECTION: ".abs_section_172" + _CAN0TXIDR2 +SECTION: ".abs_section_173" + _CAN0TXIDR3 +SECTION: ".abs_section_174" + _CAN0TXDSR0 +SECTION: ".abs_section_175" + _CAN0TXDSR1 +SECTION: ".abs_section_176" + _CAN0TXDSR2 +SECTION: ".abs_section_177" + _CAN0TXDSR3 +SECTION: ".abs_section_178" + _CAN0TXDSR4 +SECTION: ".abs_section_179" + _CAN0TXDSR5 +SECTION: ".abs_section_17a" + _CAN0TXDSR6 +SECTION: ".abs_section_17b" + _CAN0TXDSR7 +SECTION: ".abs_section_17c" + _CAN0TXDLR +SECTION: ".abs_section_17d" + _CAN0TXTBPR +SECTION: ".abs_section_240" + _PTT +SECTION: ".abs_section_241" + _PTIT +SECTION: ".abs_section_242" + _DDRT +SECTION: ".abs_section_243" + _RDRT +SECTION: ".abs_section_244" + _PERT +SECTION: ".abs_section_245" + _PPST +SECTION: ".abs_section_248" + _PTS +SECTION: ".abs_section_249" + _PTIS +SECTION: ".abs_section_24a" + _DDRS +SECTION: ".abs_section_24b" + _RDRS +SECTION: ".abs_section_24c" + _PERS +SECTION: ".abs_section_24d" + _PPSS +SECTION: ".abs_section_24e" + _WOMS +SECTION: ".abs_section_250" + _PTM +SECTION: ".abs_section_251" + _PTIM +SECTION: ".abs_section_252" + _DDRM +SECTION: ".abs_section_253" + _RDRM +SECTION: ".abs_section_254" + _PERM +SECTION: ".abs_section_255" + _PPSM +SECTION: ".abs_section_256" + _WOMM +SECTION: ".abs_section_257" + _MODRR +SECTION: ".abs_section_258" + _PTP +SECTION: ".abs_section_259" + _PTIP +SECTION: ".abs_section_25a" + _DDRP +SECTION: ".abs_section_25b" + _RDRP +SECTION: ".abs_section_25c" + _PERP +SECTION: ".abs_section_25d" + _PPSP +SECTION: ".abs_section_25e" + _PIEP +SECTION: ".abs_section_25f" + _PIFP +SECTION: ".abs_section_260" + _PTH +SECTION: ".abs_section_261" + _PTIH +SECTION: ".abs_section_262" + _DDRH +SECTION: ".abs_section_263" + _RDRH +SECTION: ".abs_section_264" + _PERH +SECTION: ".abs_section_265" + _PPSH +SECTION: ".abs_section_266" + _PIEH +SECTION: ".abs_section_267" + _PIFH +SECTION: ".abs_section_268" + _PTJ +SECTION: ".abs_section_269" + _PTIJ +SECTION: ".abs_section_26a" + _DDRJ +SECTION: ".abs_section_26b" + _RDRJ +SECTION: ".abs_section_26c" + _PERJ +SECTION: ".abs_section_26d" + _PPSJ +SECTION: ".abs_section_26e" + _PIEJ +SECTION: ".abs_section_26f" + _PIFJ +SECTION: ".abs_section_280" + _CAN4CTL0 +SECTION: ".abs_section_281" + _CAN4CTL1 +SECTION: ".abs_section_282" + _CAN4BTR0 +SECTION: ".abs_section_283" + _CAN4BTR1 +SECTION: ".abs_section_284" + _CAN4RFLG +SECTION: ".abs_section_285" + _CAN4RIER +SECTION: ".abs_section_286" + _CAN4TFLG +SECTION: ".abs_section_287" + _CAN4TIER +SECTION: ".abs_section_288" + _CAN4TARQ +SECTION: ".abs_section_289" + _CAN4TAAK +SECTION: ".abs_section_28a" + _CAN4TBSEL +SECTION: ".abs_section_28b" + _CAN4IDAC +SECTION: ".abs_section_28e" + _CAN4RXERR +SECTION: ".abs_section_28f" + _CAN4TXERR +SECTION: ".abs_section_290" + _CAN4IDAR0 +SECTION: ".abs_section_291" + _CAN4IDAR1 +SECTION: ".abs_section_292" + _CAN4IDAR2 +SECTION: ".abs_section_293" + _CAN4IDAR3 +SECTION: ".abs_section_294" + _CAN4IDMR0 +SECTION: ".abs_section_295" + _CAN4IDMR1 +SECTION: ".abs_section_296" + _CAN4IDMR2 +SECTION: ".abs_section_297" + _CAN4IDMR3 +SECTION: ".abs_section_298" + _CAN4IDAR4 +SECTION: ".abs_section_299" + _CAN4IDAR5 +SECTION: ".abs_section_29a" + _CAN4IDAR6 +SECTION: ".abs_section_29b" + _CAN4IDAR7 +SECTION: ".abs_section_29c" + _CAN4IDMR4 +SECTION: ".abs_section_29d" + _CAN4IDMR5 +SECTION: ".abs_section_29e" + _CAN4IDMR6 +SECTION: ".abs_section_29f" + _CAN4IDMR7 +SECTION: ".abs_section_2a0" + _CAN4RXIDR0 +SECTION: ".abs_section_2a1" + _CAN4RXIDR1 +SECTION: ".abs_section_2a2" + _CAN4RXIDR2 +SECTION: ".abs_section_2a3" + _CAN4RXIDR3 +SECTION: ".abs_section_2a4" + _CAN4RXDSR0 +SECTION: ".abs_section_2a5" + _CAN4RXDSR1 +SECTION: ".abs_section_2a6" + _CAN4RXDSR2 +SECTION: ".abs_section_2a7" + _CAN4RXDSR3 +SECTION: ".abs_section_2a8" + _CAN4RXDSR4 +SECTION: ".abs_section_2a9" + _CAN4RXDSR5 +SECTION: ".abs_section_2aa" + _CAN4RXDSR6 +SECTION: ".abs_section_2ab" + _CAN4RXDSR7 +SECTION: ".abs_section_2ac" + _CAN4RXDLR +SECTION: ".abs_section_2b0" + _CAN4TXIDR0 +SECTION: ".abs_section_2b1" + _CAN4TXIDR1 +SECTION: ".abs_section_2b2" + _CAN4TXIDR2 +SECTION: ".abs_section_2b3" + _CAN4TXIDR3 +SECTION: ".abs_section_2b4" + _CAN4TXDSR0 +SECTION: ".abs_section_2b5" + _CAN4TXDSR1 +SECTION: ".abs_section_2b6" + _CAN4TXDSR2 +SECTION: ".abs_section_2b7" + _CAN4TXDSR3 +SECTION: ".abs_section_2b8" + _CAN4TXDSR4 +SECTION: ".abs_section_2b9" + _CAN4TXDSR5 +SECTION: ".abs_section_2ba" + _CAN4TXDSR6 +SECTION: ".abs_section_2bb" + _CAN4TXDSR7 +SECTION: ".abs_section_2bc" + _CAN4TXDLR +SECTION: ".abs_section_2bd" + _CAN4TXTBPR +SECTION: ".abs_section_0" + _PORTAB +SECTION: ".abs_section_2" + _DDRAB +SECTION: ".abs_section_1a" + _PARTID +SECTION: ".abs_section_44" + _TCNT +SECTION: ".abs_section_50" + _TC0 +SECTION: ".abs_section_52" + _TC1 +SECTION: ".abs_section_54" + _TC2 +SECTION: ".abs_section_56" + _TC3 +SECTION: ".abs_section_58" + _TC4 +SECTION: ".abs_section_5a" + _TC5 +SECTION: ".abs_section_5c" + _TC6 +SECTION: ".abs_section_5e" + _TC7 +SECTION: ".abs_section_62" + _PACN32 +SECTION: ".abs_section_64" + _PACN10 +SECTION: ".abs_section_72" + _PA32H +SECTION: ".abs_section_74" + _PA10H +SECTION: ".abs_section_76" + _MCCNT +SECTION: ".abs_section_78" + _TC0H +SECTION: ".abs_section_7a" + _TC1H +SECTION: ".abs_section_7c" + _TC2H +SECTION: ".abs_section_7e" + _TC3H +SECTION: ".abs_section_82" + _ATD0CTL23 +SECTION: ".abs_section_84" + _ATD0CTL45 +SECTION: ".abs_section_90" + _ATD0DR0 +SECTION: ".abs_section_92" + _ATD0DR1 +SECTION: ".abs_section_94" + _ATD0DR2 +SECTION: ".abs_section_96" + _ATD0DR3 +SECTION: ".abs_section_98" + _ATD0DR4 +SECTION: ".abs_section_9a" + _ATD0DR5 +SECTION: ".abs_section_9c" + _ATD0DR6 +SECTION: ".abs_section_9e" + _ATD0DR7 +SECTION: ".abs_section_ac" + _PWMCNT01 +SECTION: ".abs_section_ae" + _PWMCNT23 +SECTION: ".abs_section_b0" + _PWMCNT45 +SECTION: ".abs_section_b2" + _PWMCNT67 +SECTION: ".abs_section_b4" + _PWMPER01 +SECTION: ".abs_section_b6" + _PWMPER23 +SECTION: ".abs_section_b8" + _PWMPER45 +SECTION: ".abs_section_ba" + _PWMPER67 +SECTION: ".abs_section_bc" + _PWMDTY01 +SECTION: ".abs_section_be" + _PWMDTY23 +SECTION: ".abs_section_c0" + _PWMDTY45 +SECTION: ".abs_section_c2" + _PWMDTY67 +SECTION: ".abs_section_c8" + _SCI0BD +SECTION: ".abs_section_d0" + _SCI1BD +SECTION: ".abs_section_122" + _ATD1CTL23 +SECTION: ".abs_section_124" + _ATD1CTL45 +SECTION: ".abs_section_130" + _ATD1DR0 +SECTION: ".abs_section_132" + _ATD1DR1 +SECTION: ".abs_section_134" + _ATD1DR2 +SECTION: ".abs_section_136" + _ATD1DR3 +SECTION: ".abs_section_138" + _ATD1DR4 +SECTION: ".abs_section_13a" + _ATD1DR5 +SECTION: ".abs_section_13c" + _ATD1DR6 +SECTION: ".abs_section_13e" + _ATD1DR7 +SECTION: ".abs_section_16e" + _CAN0RXTSR +SECTION: ".abs_section_17e" + _CAN0TXTSR +SECTION: ".abs_section_2ae" + _CAN4RXTSR +SECTION: ".abs_section_2be" + _CAN4TXTSR +SECTION: ".abs_section_ff80" + _vectab + +********************************************************************************************* +OBJECT LIST SORTED BY ADDRESS + Name Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- + _PORTAB 0 2 2 0 .abs_section_0 + _DDRAB 2 2 2 0 .abs_section_2 + _PORTE 8 1 1 0 .abs_section_8 + _DDRE 9 1 1 0 .abs_section_9 + _PEAR A 1 1 0 .abs_section_a + _MODE B 1 1 0 .abs_section_b + _PUCR C 1 1 0 .abs_section_c + _RDRIV D 1 1 0 .abs_section_d + _EBICTL E 1 1 0 .abs_section_e + _INITRM 10 1 1 0 .abs_section_10 + _INITRG 11 1 1 0 .abs_section_11 + _INITEE 12 1 1 0 .abs_section_12 + _MISC 13 1 1 0 .abs_section_13 + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _PARTID 1A 2 2 0 .abs_section_1a + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _INTCR 1E 1 1 0 .abs_section_1e + _HPRIO 1F 1 1 0 .abs_section_1f + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP1X 2D 1 1 0 .abs_section_2d + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _PPAGE 30 1 1 0 .abs_section_30 + _PORTK 32 1 1 0 .abs_section_32 + _DDRK 33 1 1 0 .abs_section_33 + _SYNR 34 1 1 1 .abs_section_34 + _REFDV 35 1 1 1 .abs_section_35 + _CRGFLG 37 1 1 1 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CLKSEL 39 1 1 2 .abs_section_39 + _PLLCTL 3A 1 1 0 .abs_section_3a + _RTICTL 3B 1 1 0 .abs_section_3b + _COPCTL 3C 1 1 0 .abs_section_3c + _ARMCOP 3F 1 1 0 .abs_section_3f + _TIOS 40 1 1 0 .abs_section_40 + _CFORC 41 1 1 0 .abs_section_41 + _OC7M 42 1 1 0 .abs_section_42 + _OC7D 43 1 1 0 .abs_section_43 + _TCNT 44 2 2 0 .abs_section_44 + _TSCR1 46 1 1 0 .abs_section_46 + _TTOV 47 1 1 0 .abs_section_47 + _TCTL1 48 1 1 0 .abs_section_48 + _TCTL2 49 1 1 0 .abs_section_49 + _TCTL3 4A 1 1 0 .abs_section_4a + _TCTL4 4B 1 1 0 .abs_section_4b + _TIE 4C 1 1 0 .abs_section_4c + _TSCR2 4D 1 1 0 .abs_section_4d + _TFLG1 4E 1 1 0 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TC0 50 2 2 0 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 0 .abs_section_5e + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PACN32 62 2 2 0 .abs_section_62 + _PACN10 64 2 2 0 .abs_section_64 + _MCCTL 66 1 1 0 .abs_section_66 + _MCFLG 67 1 1 0 .abs_section_67 + _ICPAR 68 1 1 0 .abs_section_68 + _DLYCT 69 1 1 0 .abs_section_69 + _ICOVW 6A 1 1 0 .abs_section_6a + _ICSYS 6B 1 1 0 .abs_section_6b + _PBCTL 70 1 1 0 .abs_section_70 + _PBFLG 71 1 1 0 .abs_section_71 + _PA32H 72 2 2 0 .abs_section_72 + _PA10H 74 2 2 0 .abs_section_74 + _MCCNT 76 2 2 0 .abs_section_76 + _TC0H 78 2 2 0 .abs_section_78 + _TC1H 7A 2 2 0 .abs_section_7a + _TC2H 7C 2 2 0 .abs_section_7c + _TC3H 7E 2 2 0 .abs_section_7e + _ATD0CTL23 82 2 2 0 .abs_section_82 + _ATD0CTL45 84 2 2 0 .abs_section_84 + _ATD0STAT0 86 1 1 0 .abs_section_86 + _ATD0TEST1 89 1 1 0 .abs_section_89 + _ATD0STAT1 8B 1 1 0 .abs_section_8b + _ATD0DIEN 8D 1 1 0 .abs_section_8d + _PORTAD0 8F 1 1 0 .abs_section_8f + _ATD0DR0 90 2 2 0 .abs_section_90 + _ATD0DR1 92 2 2 0 .abs_section_92 + _ATD0DR2 94 2 2 0 .abs_section_94 + _ATD0DR3 96 2 2 0 .abs_section_96 + _ATD0DR4 98 2 2 0 .abs_section_98 + _ATD0DR5 9A 2 2 0 .abs_section_9a + _ATD0DR6 9C 2 2 0 .abs_section_9c + _ATD0DR7 9E 2 2 0 .abs_section_9e + _PWME A0 1 1 0 .abs_section_a0 + _PWMPOL A1 1 1 0 .abs_section_a1 + _PWMCLK A2 1 1 0 .abs_section_a2 + _PWMPRCLK A3 1 1 0 .abs_section_a3 + _PWMCAE A4 1 1 0 .abs_section_a4 + _PWMCTL A5 1 1 0 .abs_section_a5 + _PWMSCLA A8 1 1 0 .abs_section_a8 + _PWMSCLB A9 1 1 0 .abs_section_a9 + _PWMCNT01 AC 2 2 0 .abs_section_ac + _PWMCNT23 AE 2 2 0 .abs_section_ae + _PWMCNT45 B0 2 2 0 .abs_section_b0 + _PWMCNT67 B2 2 2 0 .abs_section_b2 + _PWMPER01 B4 2 2 0 .abs_section_b4 + _PWMPER23 B6 2 2 0 .abs_section_b6 + _PWMPER45 B8 2 2 0 .abs_section_b8 + _PWMPER67 BA 2 2 0 .abs_section_ba + _PWMDTY01 BC 2 2 0 .abs_section_bc + _PWMDTY23 BE 2 2 0 .abs_section_be + _PWMDTY45 C0 2 2 0 .abs_section_c0 + _PWMDTY67 C2 2 2 0 .abs_section_c2 + _PWMSDN C4 1 1 0 .abs_section_c4 + _SCI0BD C8 2 2 0 .abs_section_c8 + _SCI0CR1 CA 1 1 0 .abs_section_ca + _SCI0CR2 CB 1 1 0 .abs_section_cb + _SCI0SR1 CC 1 1 0 .abs_section_cc + _SCI0SR2 CD 1 1 0 .abs_section_cd + _SCI0DRH CE 1 1 0 .abs_section_ce + _SCI0DRL CF 1 1 0 .abs_section_cf + _SCI1BD D0 2 2 0 .abs_section_d0 + _SCI1CR1 D2 1 1 0 .abs_section_d2 + _SCI1CR2 D3 1 1 0 .abs_section_d3 + _SCI1SR1 D4 1 1 0 .abs_section_d4 + _SCI1SR2 D5 1 1 0 .abs_section_d5 + _SCI1DRH D6 1 1 0 .abs_section_d6 + _SCI1DRL D7 1 1 0 .abs_section_d7 + _SPI0CR1 D8 1 1 0 .abs_section_d8 + _SPI0CR2 D9 1 1 0 .abs_section_d9 + _SPI0BR DA 1 1 0 .abs_section_da + _SPI0SR DB 1 1 0 .abs_section_db + _SPI0DR DD 1 1 0 .abs_section_dd + _IBAD E0 1 1 0 .abs_section_e0 + _IBFD E1 1 1 0 .abs_section_e1 + _IBCR E2 1 1 0 .abs_section_e2 + _IBSR E3 1 1 0 .abs_section_e3 + _IBDR E4 1 1 0 .abs_section_e4 + _SPI1CR1 F0 1 1 0 .abs_section_f0 + _SPI1CR2 F1 1 1 0 .abs_section_f1 + _SPI1BR F2 1 1 0 .abs_section_f2 + _SPI1SR F3 1 1 0 .abs_section_f3 + _SPI1DR F5 1 1 0 .abs_section_f5 + _SPI2CR1 F8 1 1 0 .abs_section_f8 + _SPI2CR2 F9 1 1 0 .abs_section_f9 + _SPI2BR FA 1 1 0 .abs_section_fa + _SPI2SR FB 1 1 0 .abs_section_fb + _SPI2DR FD 1 1 0 .abs_section_fd + _FCLKDIV 100 1 1 0 .abs_section_100 + _FSEC 101 1 1 0 .abs_section_101 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSTAT 105 1 1 0 .abs_section_105 + _FCMD 106 1 1 0 .abs_section_106 + _ECLKDIV 110 1 1 0 .abs_section_110 + _ECNFG 113 1 1 0 .abs_section_113 + _EPROT 114 1 1 0 .abs_section_114 + _ESTAT 115 1 1 0 .abs_section_115 + _ECMD 116 1 1 0 .abs_section_116 + _ATD1CTL23 122 2 2 0 .abs_section_122 + _ATD1CTL45 124 2 2 0 .abs_section_124 + _ATD1STAT0 126 1 1 0 .abs_section_126 + _ATD1TEST1 129 1 1 0 .abs_section_129 + _ATD1STAT1 12B 1 1 0 .abs_section_12b + _ATD1DIEN 12D 1 1 0 .abs_section_12d + _PORTAD1 12F 1 1 0 .abs_section_12f + _ATD1DR0 130 2 2 0 .abs_section_130 + _ATD1DR1 132 2 2 0 .abs_section_132 + _ATD1DR2 134 2 2 0 .abs_section_134 + _ATD1DR3 136 2 2 0 .abs_section_136 + _ATD1DR4 138 2 2 0 .abs_section_138 + _ATD1DR5 13A 2 2 0 .abs_section_13a + _ATD1DR6 13C 2 2 0 .abs_section_13c + _ATD1DR7 13E 2 2 0 .abs_section_13e + _CAN0CTL0 140 1 1 0 .abs_section_140 + _CAN0CTL1 141 1 1 0 .abs_section_141 + _CAN0BTR0 142 1 1 0 .abs_section_142 + _CAN0BTR1 143 1 1 0 .abs_section_143 + _CAN0RFLG 144 1 1 0 .abs_section_144 + _CAN0RIER 145 1 1 0 .abs_section_145 + _CAN0TFLG 146 1 1 0 .abs_section_146 + _CAN0TIER 147 1 1 0 .abs_section_147 + _CAN0TARQ 148 1 1 0 .abs_section_148 + _CAN0TAAK 149 1 1 0 .abs_section_149 + _CAN0TBSEL 14A 1 1 0 .abs_section_14a + _CAN0IDAC 14B 1 1 0 .abs_section_14b + _CAN0RXERR 14E 1 1 0 .abs_section_14e + _CAN0TXERR 14F 1 1 0 .abs_section_14f + _CAN0IDAR0 150 1 1 0 .abs_section_150 + _CAN0IDAR1 151 1 1 0 .abs_section_151 + _CAN0IDAR2 152 1 1 0 .abs_section_152 + _CAN0IDAR3 153 1 1 0 .abs_section_153 + _CAN0IDMR0 154 1 1 0 .abs_section_154 + _CAN0IDMR1 155 1 1 0 .abs_section_155 + _CAN0IDMR2 156 1 1 0 .abs_section_156 + _CAN0IDMR3 157 1 1 0 .abs_section_157 + _CAN0IDAR4 158 1 1 0 .abs_section_158 + _CAN0IDAR5 159 1 1 0 .abs_section_159 + _CAN0IDAR6 15A 1 1 0 .abs_section_15a + _CAN0IDAR7 15B 1 1 0 .abs_section_15b + _CAN0IDMR4 15C 1 1 0 .abs_section_15c + _CAN0IDMR5 15D 1 1 0 .abs_section_15d + _CAN0IDMR6 15E 1 1 0 .abs_section_15e + _CAN0IDMR7 15F 1 1 0 .abs_section_15f + _CAN0RXIDR0 160 1 1 0 .abs_section_160 + _CAN0RXIDR1 161 1 1 0 .abs_section_161 + _CAN0RXIDR2 162 1 1 0 .abs_section_162 + _CAN0RXIDR3 163 1 1 0 .abs_section_163 + _CAN0RXDSR0 164 1 1 0 .abs_section_164 + _CAN0RXDSR1 165 1 1 0 .abs_section_165 + _CAN0RXDSR2 166 1 1 0 .abs_section_166 + _CAN0RXDSR3 167 1 1 0 .abs_section_167 + _CAN0RXDSR4 168 1 1 0 .abs_section_168 + _CAN0RXDSR5 169 1 1 0 .abs_section_169 + _CAN0RXDSR6 16A 1 1 0 .abs_section_16a + _CAN0RXDSR7 16B 1 1 0 .abs_section_16b + _CAN0RXDLR 16C 1 1 0 .abs_section_16c + _CAN0RXTSR 16E 2 2 0 .abs_section_16e + _CAN0TXIDR0 170 1 1 0 .abs_section_170 + _CAN0TXIDR1 171 1 1 0 .abs_section_171 + _CAN0TXIDR2 172 1 1 0 .abs_section_172 + _CAN0TXIDR3 173 1 1 0 .abs_section_173 + _CAN0TXDSR0 174 1 1 0 .abs_section_174 + _CAN0TXDSR1 175 1 1 0 .abs_section_175 + _CAN0TXDSR2 176 1 1 0 .abs_section_176 + _CAN0TXDSR3 177 1 1 0 .abs_section_177 + _CAN0TXDSR4 178 1 1 0 .abs_section_178 + _CAN0TXDSR5 179 1 1 0 .abs_section_179 + _CAN0TXDSR6 17A 1 1 0 .abs_section_17a + _CAN0TXDSR7 17B 1 1 0 .abs_section_17b + _CAN0TXDLR 17C 1 1 0 .abs_section_17c + _CAN0TXTBPR 17D 1 1 0 .abs_section_17d + _CAN0TXTSR 17E 2 2 0 .abs_section_17e + _PTT 240 1 1 0 .abs_section_240 + _PTIT 241 1 1 0 .abs_section_241 + _DDRT 242 1 1 0 .abs_section_242 + _RDRT 243 1 1 0 .abs_section_243 + _PERT 244 1 1 0 .abs_section_244 + _PPST 245 1 1 0 .abs_section_245 + _PTS 248 1 1 0 .abs_section_248 + _PTIS 249 1 1 0 .abs_section_249 + _DDRS 24A 1 1 0 .abs_section_24a + _RDRS 24B 1 1 0 .abs_section_24b + _PERS 24C 1 1 0 .abs_section_24c + _PPSS 24D 1 1 0 .abs_section_24d + _WOMS 24E 1 1 0 .abs_section_24e + _PTM 250 1 1 0 .abs_section_250 + _PTIM 251 1 1 0 .abs_section_251 + _DDRM 252 1 1 0 .abs_section_252 + _RDRM 253 1 1 0 .abs_section_253 + _PERM 254 1 1 0 .abs_section_254 + _PPSM 255 1 1 0 .abs_section_255 + _WOMM 256 1 1 0 .abs_section_256 + _MODRR 257 1 1 0 .abs_section_257 + _PTP 258 1 1 0 .abs_section_258 + _PTIP 259 1 1 0 .abs_section_259 + _DDRP 25A 1 1 0 .abs_section_25a + _RDRP 25B 1 1 0 .abs_section_25b + _PERP 25C 1 1 0 .abs_section_25c + _PPSP 25D 1 1 0 .abs_section_25d + _PIEP 25E 1 1 0 .abs_section_25e + _PIFP 25F 1 1 0 .abs_section_25f + _PTH 260 1 1 0 .abs_section_260 + _PTIH 261 1 1 0 .abs_section_261 + _DDRH 262 1 1 0 .abs_section_262 + _RDRH 263 1 1 0 .abs_section_263 + _PERH 264 1 1 0 .abs_section_264 + _PPSH 265 1 1 0 .abs_section_265 + _PIEH 266 1 1 0 .abs_section_266 + _PIFH 267 1 1 0 .abs_section_267 + _PTJ 268 1 1 0 .abs_section_268 + _PTIJ 269 1 1 0 .abs_section_269 + _DDRJ 26A 1 1 0 .abs_section_26a + _RDRJ 26B 1 1 0 .abs_section_26b + _PERJ 26C 1 1 0 .abs_section_26c + _PPSJ 26D 1 1 0 .abs_section_26d + _PIEJ 26E 1 1 0 .abs_section_26e + _PIFJ 26F 1 1 0 .abs_section_26f + _CAN4CTL0 280 1 1 0 .abs_section_280 + _CAN4CTL1 281 1 1 0 .abs_section_281 + _CAN4BTR0 282 1 1 0 .abs_section_282 + _CAN4BTR1 283 1 1 0 .abs_section_283 + _CAN4RFLG 284 1 1 0 .abs_section_284 + _CAN4RIER 285 1 1 0 .abs_section_285 + _CAN4TFLG 286 1 1 0 .abs_section_286 + _CAN4TIER 287 1 1 0 .abs_section_287 + _CAN4TARQ 288 1 1 0 .abs_section_288 + _CAN4TAAK 289 1 1 0 .abs_section_289 + _CAN4TBSEL 28A 1 1 0 .abs_section_28a + _CAN4IDAC 28B 1 1 0 .abs_section_28b + _CAN4RXERR 28E 1 1 0 .abs_section_28e + _CAN4TXERR 28F 1 1 0 .abs_section_28f + _CAN4IDAR0 290 1 1 0 .abs_section_290 + _CAN4IDAR1 291 1 1 0 .abs_section_291 + _CAN4IDAR2 292 1 1 0 .abs_section_292 + _CAN4IDAR3 293 1 1 0 .abs_section_293 + _CAN4IDMR0 294 1 1 0 .abs_section_294 + _CAN4IDMR1 295 1 1 0 .abs_section_295 + _CAN4IDMR2 296 1 1 0 .abs_section_296 + _CAN4IDMR3 297 1 1 0 .abs_section_297 + _CAN4IDAR4 298 1 1 0 .abs_section_298 + _CAN4IDAR5 299 1 1 0 .abs_section_299 + _CAN4IDAR6 29A 1 1 0 .abs_section_29a + _CAN4IDAR7 29B 1 1 0 .abs_section_29b + _CAN4IDMR4 29C 1 1 0 .abs_section_29c + _CAN4IDMR5 29D 1 1 0 .abs_section_29d + _CAN4IDMR6 29E 1 1 0 .abs_section_29e + _CAN4IDMR7 29F 1 1 0 .abs_section_29f + _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 + _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 + _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 + _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 + _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 + _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 + _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 + _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 + _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 + _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 + _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa + _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab + _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac + _CAN4RXTSR 2AE 2 2 0 .abs_section_2ae + _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 + _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 + _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 + _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 + _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 + _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 + _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 + _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 + _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 + _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 + _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba + _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb + _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc + _CAN4TXTBPR 2BD 1 1 0 .abs_section_2bd + _CAN4TXTSR 2BE 2 2 0 .abs_section_2be + backdoorOpen 3900 1 1 3 .bss + backdoorOpenTime 3901 4 4 4 .bss + comEntryStateConnect 3905 1 1 2 .bss + xcpCtoReqPacket.1 3906 40 64 2 .bss + xcpInfo 3946 4A 74 102 .bss + blockInfo 3990 204 516 7 .bss + bootBlockInfo 3B94 204 516 11 .bss + flashExecCmdRam 3D98 16 22 2 .bss + flashMaxNrBlocks 3DAE 1 1 1 .bss + millisecond_counter 3DAF 4 4 8 .bss + xcpCtoRxInProgress.4 3DB3 1 1 3 .bss + xcpCtoReqPacket.2 3DB4 41 65 4 .bss + xcpCtoRxLength.3 3DF5 1 1 5 .bss + assert_failure_file 3DF6 2 2 1 .bss + assert_failure_line 3DF8 4 4 2 .bss + Init E800 29 41 1 .init + _Startup E829 8 8 2 .init + xcpStationId E83B 8 8 1 .rodata + flashLayout E843 A0 160 39 .rodata + flashExecCmd E8E3 16 22 1 .rodata + STRING.C..Work.software.Ope.1 E8F9 55 85 1 .rodata1 + STRING.C..Work.software.Ope.1 E94E 35 53 1 .rodata1 + STRING.C..Work.software.Ope.1 E983 34 52 3 .rodata1 + main E9B7 B 11 3 .text + Init E9C2 79 121 1 .text + BackDoorInit EA3B 11 17 1 .text + BackDoorCheck EA4C 31 49 2 .text + BootInit EA7D F 15 1 .text + BootTask EA8C C 12 1 .text + ComInit EA98 19 25 1 .text + ComTask EAB1 10 16 1 .text + ComFree EAC1 1 1 1 .text + ComTransmitPacket EAC2 F 15 1 .text + ComSetConnectEntryState EAD1 6 6 1 .text + ComIsConnected EAD7 4 4 1 .text + CopInit EADB 1 1 1 .text + CopService EADC 1 1 8 .text + XcpInit EADD 15 21 1 .text + XcpIsConnected EAF2 9 9 1 .text + XcpPacketTransmitted EAFB 4 4 1 .text + XcpPacketReceived EAFF E7 231 2 .text + XcpTransmitPacket EBE6 C 12 1 .text + XcpComputeChecksum EBF2 43 67 1 .text + XcpProtectResources EC35 4 4 2 .text + XcpSetCtoError EC39 10 16 9 .text + XcpCmdConnect EC49 2A 42 1 .text + XcpCmdDisconnect EC73 10 16 1 .text + XcpCmdGetStatus EC83 1A 26 1 .text + XcpCmdSynch EC9D 4 4 1 .text + XcpCmdGetId ECA1 22 34 1 .text + XcpCmdSetMta ECC3 1A 26 1 .text + XcpCmdUpload ECDD 4E 78 1 .text + XcpCmdShortUpload ED2B 55 85 1 .text + XcpCmdBuildCheckSum ED80 2C 44 1 .text + XcpCmdProgramStart EDAC 19 25 1 .text + XcpCmdProgramMax EDC5 43 67 1 .text + XcpCmdProgram EE08 5B 91 1 .text + XcpCmdProgramClear EE63 2A 42 1 .text + XcpCmdProgramReset EE8D E 14 1 .text + XcpCmdProgramPrepare EE9B 5 5 1 .text + CpuStartUserProgram EEA0 18 24 1 .text + CpuMemCopy EEB8 27 39 4 .text + CpuReset EEDF 3 3 1 .text + FlashInit EEE2 74 116 1 .text + FlashWrite EF56 B6 182 2 .text + FlashErase F00C DD 221 1 .text + FlashWriteChecksum F0E9 67 103 1 .text + FlashVerifyChecksum F150 8A 138 1 .text + FlashDone F1DA 35 53 1 .text + FlashInitBlock F20F 51 81 2 .text + FlashSwitchBlock F260 4E 78 2 .text + FlashAddToBlock F2AE BD 189 1 .text + FlashWriteBlock F36B 78 120 3 .text + FlashGetLinearAddrByte F3E3 1D 29 5 .text + FlashGetPhysPage F400 C 12 3 .text + FlashGetPhysAddr F40C 6 6 3 .text + FlashExecuteCommand F412 1F 31 1 .text + FlashOperate F431 54 84 2 .text + NvmInit F485 3 3 1 .text + NvmWrite F488 16 22 2 .text + NvmErase F49E 12 18 1 .text + NvmVerifyChecksum F4B0 4 4 1 .text + NvmDone F4B4 B 11 1 .text + TimerInit F4BF 1D 29 1 .text + TimerReset F4DC 1C 28 2 .text + TimerUpdate F4F8 1F 31 2 .text + TimerGet F517 9 9 2 .text + UartInit F520 19 25 1 .text + UartTransmitPacket F539 5E 94 1 .text + UartReceivePacket F597 50 80 1 .text + UartReceiveByte F5E7 11 17 2 .text + UartTransmitByte F5F8 14 20 2 .text + reset_handler F60C 9 9 2 .text + Vector0_handler F615 6 6 1 .text + Vector1_handler F61B 6 6 1 .text + Vector2_handler F621 6 6 1 .text + Vector3_handler F627 6 6 1 .text + Vector4_handler F62D 6 6 1 .text + Vector5_handler F633 6 6 1 .text + Vector6_handler F639 6 6 1 .text + Vector7_handler F63F 6 6 1 .text + Vector8_handler F645 6 6 1 .text + Vector9_handler F64B 6 6 1 .text + Vector10_handler F651 6 6 1 .text + Vector11_handler F657 6 6 1 .text + Vector12_handler F65D 6 6 1 .text + Vector13_handler F663 6 6 1 .text + Vector14_handler F669 6 6 1 .text + Vector15_handler F66F 6 6 1 .text + Vector16_handler F675 6 6 1 .text + Vector17_handler F67B 6 6 1 .text + Vector18_handler F681 6 6 1 .text + Vector19_handler F687 6 6 1 .text + Vector20_handler F68D 6 6 1 .text + Vector21_handler F693 6 6 1 .text + Vector22_handler F699 6 6 1 .text + Vector23_handler F69F 6 6 1 .text + Vector24_handler F6A5 6 6 1 .text + Vector25_handler F6AB 6 6 1 .text + Vector26_handler F6B1 6 6 1 .text + Vector27_handler F6B7 6 6 1 .text + Vector28_handler F6BD 6 6 1 .text + Vector29_handler F6C3 6 6 1 .text + Vector30_handler F6C9 6 6 1 .text + Vector31_handler F6CF 6 6 1 .text + Vector32_handler F6D5 6 6 1 .text + Vector33_handler F6DB 6 6 1 .text + Vector34_handler F6E1 6 6 1 .text + Vector35_handler F6E7 6 6 1 .text + Vector36_handler F6ED 6 6 1 .text + Vector37_handler F6F3 6 6 1 .text + Vector38_handler F6F9 6 6 1 .text + Vector39_handler F6FF 6 6 1 .text + Vector40_handler F705 6 6 1 .text + Vector41_handler F70B 6 6 1 .text + Vector42_handler F711 6 6 1 .text + Vector43_handler F717 6 6 1 .text + Vector44_handler F71D 6 6 1 .text + Vector45_handler F723 6 6 1 .text + Vector46_handler F729 6 6 1 .text + Vector47_handler F72F 6 6 1 .text + Vector48_handler F735 6 6 1 .text + Vector49_handler F73B 6 6 1 .text + Vector50_handler F741 6 6 1 .text + Vector51_handler F747 6 6 1 .text + Vector52_handler F74D 6 6 1 .text + Vector53_handler F753 6 6 1 .text + Vector54_handler F759 6 6 1 .text + Vector55_handler F75F 6 6 1 .text + Vector56_handler F765 6 6 1 .text + Vector57_handler F76B 6 6 1 .text + Vector58_handler F771 6 6 1 .text + Vector59_handler F777 6 6 1 .text + Vector60_handler F77D 6 6 1 .text + Vector61_handler F783 6 6 1 .text + Vector62_handler F789 6 6 1 .text + AssertFailure F78F 14 20 5 .text + _LSHL F7A3 11 17 3 RUNTIME + _LSHRU F7B4 11 17 5 RUNTIME + _LCMP F7C5 19 25 4 RUNTIME + _LINC F7DE 5 5 4 RUNTIME + _LDEC F7E3 8 8 6 RUNTIME + _lDivMod F7EB BE 190 1 RUNTIME + _LDIVU F8A9 E 14 1 RUNTIME + _ILSEXT F8B7 7 7 1 RUNTIME + _CASE_DIRECT_BYTE F8BE 5 5 3 RUNTIME + reset_connected_handler FEF0 C 12 0 ENTRY + _vectab FF80 80 128 0 .abs_section_ff80 + +********************************************************************************************* +UNUSED-OBJECTS SECTION +--------------------------------------------------------------------------------------------- +NOT USED PROCEDURES +rtshc12.c.o (ansisi.lib): + _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHRS _LADD + _LSUB _LAND _LOR _LXOR _LCMP_P _LCMP_PP _LNEG _LCOM _LMUL _LMULU16x32 + _LMULS16x32 _NEG_P _LDIVS _LMODU _LMODS _COPY _CASE_DIRECT _CASE_CHECKED + _CASE_CHECKED_BYTE _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 + _CASE_SEARCH_8_BYTE _FCALL _FPCMP +com.c.o: + ComSetDisconnectEntryState ComIsConnectEntryState +NOT USED VARIABLES +rtshc12.c.o (ansisi.lib): + _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 errno + +********************************************************************************************* +COPYDOWN SECTION +--------------------------------------------------------------------------------------------- +------- ROM-ADDRESS: 0xF8C3 ---- SIZE 2 --- +Filling bytes inserted + 0000 + +********************************************************************************************* +OBJECT-DEPENDENCIES SECTION +--------------------------------------------------------------------------------------------- +Init USES _startupData +_Startup USES __SEG_END_SSTACK Init main +main USES Init BootInit BootTask +Init USES _CLKSEL _ILSEXT _LDIVU + STRING.C..Work.software.Ope.1 AssertFailure _SYNR _REFDV _CRGFLG +BackDoorInit USES backdoorOpen TimerGet backdoorOpenTime + BackDoorCheck +BackDoorCheck USES ComIsConnected backdoorOpen TimerGet + backdoorOpenTime _LCMP CpuStartUserProgram +BootInit USES CopInit TimerInit NvmInit ComInit BackDoorInit +BootTask USES CopService TimerUpdate ComTask BackDoorCheck +ComInit USES XcpInit UartInit comEntryStateConnect + XcpPacketReceived +ComTask USES xcpCtoReqPacket.1 UartReceivePacket + XcpPacketReceived +ComTransmitPacket USES UartTransmitPacket XcpPacketTransmitted +ComSetConnectEntryState USES comEntryStateConnect +ComIsConnected USES XcpIsConnected +XcpInit USES xcpInfo +XcpIsConnected USES xcpInfo +XcpPacketTransmitted USES xcpInfo +XcpPacketReceived USES XcpCmdConnect xcpInfo _CASE_DIRECT_BYTE + XcpCmdUpload XcpCmdShortUpload XcpCmdSetMta + XcpCmdBuildCheckSum XcpCmdGetId XcpCmdSynch XcpCmdGetStatus + XcpCmdDisconnect XcpCmdProgramMax XcpCmdProgram + XcpCmdProgramStart XcpCmdProgramClear XcpCmdProgramReset + XcpCmdProgramPrepare XcpSetCtoError XcpTransmitPacket +XcpTransmitPacket USES ComTransmitPacket +XcpComputeChecksum USES _LINC _LDEC _LCMP +XcpProtectResources USES xcpInfo +XcpSetCtoError USES xcpInfo +XcpCmdConnect USES XcpProtectResources xcpInfo +XcpCmdDisconnect USES xcpInfo XcpProtectResources +XcpCmdGetStatus USES xcpInfo +XcpCmdSynch USES XcpSetCtoError +XcpCmdGetId USES xcpStationId xcpInfo +XcpCmdSetMta USES xcpInfo +XcpCmdUpload USES XcpSetCtoError xcpInfo CpuMemCopy +XcpCmdShortUpload USES XcpSetCtoError xcpInfo CpuMemCopy +XcpCmdBuildCheckSum USES xcpInfo XcpComputeChecksum +XcpCmdProgramStart USES xcpInfo +XcpCmdProgramMax USES xcpInfo NvmWrite XcpSetCtoError +XcpCmdProgram USES xcpInfo NvmDone NvmWrite XcpSetCtoError +XcpCmdProgramClear USES xcpInfo NvmErase XcpSetCtoError +XcpCmdProgramReset USES CpuReset xcpInfo +XcpCmdProgramPrepare USES XcpSetCtoError +CpuStartUserProgram USES NvmVerifyChecksum ComFree TimerReset +CpuMemCopy USES CopService +CpuReset USES reset_handler +FlashInit USES blockInfo bootBlockInfo flashMaxNrBlocks + STRING.C..Work.software.Ope.1 AssertFailure +FlashWrite USES flashLayout _LDEC _LCMP _LSHRU _LSHL + bootBlockInfo blockInfo FlashAddToBlock +FlashErase USES _LSHRU _LSHL flashLayout _LDEC _LCMP CopService + FlashOperate +FlashWriteChecksum USES bootBlockInfo flashLayout FlashWrite +FlashVerifyChecksum USES flashLayout FlashGetLinearAddrByte _LINC +FlashDone USES bootBlockInfo FlashWriteBlock blockInfo +FlashInitBlock USES FlashGetPhysPage FlashGetPhysAddr CpuMemCopy +FlashSwitchBlock USES bootBlockInfo blockInfo flashLayout + FlashWriteBlock FlashInitBlock +FlashAddToBlock USES _LSHRU _LSHL FlashInitBlock FlashSwitchBlock + CopService _LDEC +FlashWriteBlock USES CopService FlashOperate FlashGetLinearAddrByte + _LINC +FlashGetLinearAddrByte USES FlashGetPhysPage FlashGetPhysAddr +FlashGetPhysPage USES _LSHRU +FlashExecuteCommand USES flashExecCmd flashExecCmdRam +FlashOperate USES FlashGetPhysPage FlashGetPhysAddr + FlashExecuteCommand +NvmInit USES FlashInit +NvmWrite USES FlashWrite +NvmErase USES FlashErase +NvmVerifyChecksum USES FlashVerifyChecksum +NvmDone USES FlashWriteChecksum FlashDone +TimerInit USES TimerReset millisecond_counter +TimerUpdate USES millisecond_counter _LINC +TimerGet USES TimerUpdate millisecond_counter +UartTransmitPacket USES STRING.C..Work.software.Ope.1 AssertFailure + UartTransmitByte CopService +UartReceivePacket USES xcpCtoRxInProgress.4 xcpCtoReqPacket.2 + UartReceiveByte xcpCtoRxLength.3 CpuMemCopy +UartTransmitByte USES CopService +reset_handler USES __SEG_END_SSTACK _Startup main +AssertFailure USES assert_failure_file assert_failure_line + CopService +_LDIVU USES _lDivMod +reset_connected_handler USES __SEG_END_SSTACK _Startup + ComSetConnectEntryState main +_vectab USES Vector0_handler Vector1_handler Vector2_handler + Vector3_handler Vector4_handler Vector5_handler + Vector6_handler Vector7_handler Vector8_handler + Vector9_handler Vector10_handler Vector11_handler + Vector12_handler Vector13_handler Vector14_handler + Vector15_handler Vector16_handler Vector17_handler + Vector18_handler Vector19_handler Vector20_handler + Vector21_handler Vector22_handler Vector23_handler + Vector24_handler Vector25_handler Vector26_handler + Vector27_handler Vector28_handler Vector29_handler + Vector30_handler Vector31_handler Vector32_handler + Vector33_handler Vector34_handler Vector35_handler + Vector36_handler Vector37_handler Vector38_handler + Vector39_handler Vector40_handler Vector41_handler + Vector42_handler Vector43_handler Vector44_handler + Vector45_handler Vector46_handler Vector47_handler + Vector48_handler Vector49_handler Vector50_handler + Vector51_handler Vector52_handler Vector53_handler + Vector54_handler Vector55_handler Vector56_handler + Vector57_handler Vector58_handler Vector59_handler + Vector60_handler Vector61_handler Vector62_handler + reset_handler + +********************************************************************************************* +DEPENDENCY TREE +********************************************************************************************* + main and _Startup Group + | + +- main (recursive dependency) + | | + | +- Init + | | | + | | +- _ILSEXT + | | | + | | +- _LDIVU + | | | | + | | | +- _lDivMod + | | | + | | +- AssertFailure + | | | + | | +- CopService + | | + | +- BootInit (recursive dependency) + | | | + | | +- CopInit + | | | + | | +- TimerInit + | | | | + | | | +- TimerReset + | | | + | | +- NvmInit + | | | | + | | | +- FlashInit + | | | | + | | | +- AssertFailure (see above) + | | | + | | +- ComInit (recursive dependency) + | | | | + | | | +- XcpInit + | | | | + | | | +- UartInit + | | | | + | | | +- XcpPacketReceived (recursive dependency) + | | | | + | | | +- XcpCmdConnect + | | | | | + | | | | +- XcpProtectResources + | | | | + | | | +- _CASE_DIRECT_BYTE + | | | | + | | | +- XcpCmdUpload + | | | | | + | | | | +- XcpSetCtoError + | | | | | + | | | | +- CpuMemCopy + | | | | | + | | | | +- CopService (see above) + | | | | + | | | +- XcpCmdShortUpload + | | | | | + | | | | +- XcpSetCtoError (see above) + | | | | | + | | | | +- CpuMemCopy (see above) + | | | | + | | | +- XcpCmdSetMta + | | | | + | | | +- XcpCmdBuildCheckSum + | | | | | + | | | | +- XcpComputeChecksum + | | | | | + | | | | +- _LINC + | | | | | + | | | | +- _LDEC + | | | | | + | | | | +- _LCMP + | | | | + | | | +- XcpCmdGetId + | | | | + | | | +- XcpCmdSynch + | | | | | + | | | | +- XcpSetCtoError (see above) + | | | | + | | | +- XcpCmdGetStatus + | | | | + | | | +- XcpCmdDisconnect + | | | | | + | | | | +- XcpProtectResources (see above) + | | | | + | | | +- XcpCmdProgramMax + | | | | | + | | | | +- NvmWrite + | | | | | | + | | | | | +- FlashWrite + | | | | | | + | | | | | +- _LDEC (see above) + | | | | | | + | | | | | +- _LCMP (see above) + | | | | | | + | | | | | +- _LSHRU + | | | | | | + | | | | | +- _LSHL + | | | | | | + | | | | | +- FlashAddToBlock + | | | | | | + | | | | | +- _LSHRU (see above) + | | | | | | + | | | | | +- _LSHL (see above) + | | | | | | + | | | | | +- FlashInitBlock + | | | | | | | + | | | | | | +- FlashGetPhysPage + | | | | | | | | + | | | | | | | +- _LSHRU (see above) + | | | | | | | + | | | | | | +- FlashGetPhysAddr + | | | | | | | + | | | | | | +- CpuMemCopy (see above) + | | | | | | + | | | | | +- FlashSwitchBlock + | | | | | | | + | | | | | | +- FlashWriteBlock + | | | | | | | | + | | | | | | | +- CopService (see above) + | | | | | | | | + | | | | | | | +- FlashOperate + | | | | | | | | | + | | | | | | | | +- FlashGetPhysPage (see above) + | | | | | | | | | + | | | | | | | | +- FlashGetPhysAddr (see above) + | | | | | | | | | + | | | | | | | | +- FlashExecuteCommand + | | | | | | | | + | | | | | | | +- FlashGetLinearAddrByte + | | | | | | | | | + | | | | | | | | +- FlashGetPhysPage (see above) + | | | | | | | | | + | | | | | | | | +- FlashGetPhysAddr (see above) + | | | | | | | | + | | | | | | | +- _LINC (see above) + | | | | | | | + | | | | | | +- FlashInitBlock (see above) + | | | | | | + | | | | | +- CopService (see above) + | | | | | | + | | | | | +- _LDEC (see above) + | | | | | + | | | | +- XcpSetCtoError (see above) + | | | | + | | | +- XcpCmdProgram + | | | | | + | | | | +- NvmDone + | | | | | | + | | | | | +- FlashWriteChecksum + | | | | | | | + | | | | | | +- FlashWrite (see above) + | | | | | | + | | | | | +- FlashDone + | | | | | | + | | | | | +- FlashWriteBlock (see above) + | | | | | + | | | | +- NvmWrite (see above) + | | | | | + | | | | +- XcpSetCtoError (see above) + | | | | + | | | +- XcpCmdProgramStart + | | | | + | | | +- XcpCmdProgramClear + | | | | | + | | | | +- NvmErase + | | | | | | + | | | | | +- FlashErase + | | | | | | + | | | | | +- _LSHRU (see above) + | | | | | | + | | | | | +- _LSHL (see above) + | | | | | | + | | | | | +- _LDEC (see above) + | | | | | | + | | | | | +- _LCMP (see above) + | | | | | | + | | | | | +- CopService (see above) + | | | | | | + | | | | | +- FlashOperate (see above) + | | | | | + | | | | +- XcpSetCtoError (see above) + | | | | + | | | +- XcpCmdProgramReset (recursive dependency) + | | | | | + | | | | +- CpuReset (recursive dependency) + | | | | | + | | | | +- reset_handler (recursive dependency) + | | | | | + | | | | +- _Startup (recursive dependency) + | | | | | | + | | | | | +- Init + | | | | | | + | | | | | +- main (see above) (recursive dependency) + | | | | | + | | | | +- main (see above) (recursive dependency) + | | | | + | | | +- XcpCmdProgramPrepare + | | | | | + | | | | +- XcpSetCtoError (see above) + | | | | + | | | +- XcpSetCtoError (see above) + | | | | + | | | +- XcpTransmitPacket + | | | | + | | | +- ComTransmitPacket + | | | | + | | | +- UartTransmitPacket + | | | | | + | | | | +- AssertFailure (see above) + | | | | | + | | | | +- UartTransmitByte + | | | | | | + | | | | | +- CopService (see above) + | | | | | + | | | | +- CopService (see above) + | | | | + | | | +- XcpPacketTransmitted + | | | + | | +- BackDoorInit + | | | + | | +- TimerGet + | | | | + | | | +- TimerUpdate + | | | | + | | | +- _LINC (see above) + | | | + | | +- BackDoorCheck + | | | + | | +- ComIsConnected + | | | | + | | | +- XcpIsConnected + | | | + | | +- TimerGet (see above) + | | | + | | +- _LCMP (see above) + | | | + | | +- CpuStartUserProgram + | | | + | | +- NvmVerifyChecksum + | | | | + | | | +- FlashVerifyChecksum + | | | | + | | | +- FlashGetLinearAddrByte (see above) + | | | | + | | | +- _LINC (see above) + | | | + | | +- ComFree + | | | + | | +- TimerReset (see above) + | | + | +- BootTask + | | + | +- CopService (see above) + | | + | +- TimerUpdate (see above) + | | + | +- ComTask + | | | + | | +- UartReceivePacket + | | | | + | | | +- UartReceiveByte + | | | | + | | | +- CpuMemCopy (see above) + | | | + | | +- XcpPacketReceived (see above) (recursive dependency) + | | + | +- BackDoorCheck (see above) + | + +- _Startup (see above) (recursive dependency) + + _vectab + | + +- Vector0_handler + | + +- Vector1_handler + | + +- Vector2_handler + | + +- Vector3_handler + | + +- Vector4_handler + | + +- Vector5_handler + | + +- Vector6_handler + | + +- Vector7_handler + | + +- Vector8_handler + | + +- Vector9_handler + | + +- Vector10_handler + | + +- Vector11_handler + | + +- Vector12_handler + | + +- Vector13_handler + | + +- Vector14_handler + | + +- Vector15_handler + | + +- Vector16_handler + | + +- Vector17_handler + | + +- Vector18_handler + | + +- Vector19_handler + | + +- Vector20_handler + | + +- Vector21_handler + | + +- Vector22_handler + | + +- Vector23_handler + | + +- Vector24_handler + | + +- Vector25_handler + | + +- Vector26_handler + | + +- Vector27_handler + | + +- Vector28_handler + | + +- Vector29_handler + | + +- Vector30_handler + | + +- Vector31_handler + | + +- Vector32_handler + | + +- Vector33_handler + | + +- Vector34_handler + | + +- Vector35_handler + | + +- Vector36_handler + | + +- Vector37_handler + | + +- Vector38_handler + | + +- Vector39_handler + | + +- Vector40_handler + | + +- Vector41_handler + | + +- Vector42_handler + | + +- Vector43_handler + | + +- Vector44_handler + | + +- Vector45_handler + | + +- Vector46_handler + | + +- Vector47_handler + | + +- Vector48_handler + | + +- Vector49_handler + | + +- Vector50_handler + | + +- Vector51_handler + | + +- Vector52_handler + | + +- Vector53_handler + | + +- Vector54_handler + | + +- Vector55_handler + | + +- Vector56_handler + | + +- Vector57_handler + | + +- Vector58_handler + | + +- Vector59_handler + | + +- Vector60_handler + | + +- Vector61_handler + | + +- Vector62_handler + | + +- reset_handler (see above) (recursive dependency) + + reset_connected_handler + | + +- _Startup (see above) (recursive dependency) + | + +- ComSetConnectEntryState + | + +- main (see above) (recursive dependency) + +********************************************************************************************* +STATISTIC SECTION +--------------------------------------------------------------------------------------------- + +ExeFile: +-------- +Number of blocks to be downloaded: 7 +Total size of all blocks to be downloaded: 4433 + diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/blt_conf.h b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/blt_conf.h new file mode 100644 index 00000000..faa32ccd --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/blt_conf.h @@ -0,0 +1,168 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Boot\blt_conf.h +* \brief Bootloader configuration header file. +* \ingroup Boot_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef BLT_CONF_H +#define BLT_CONF_H + +/**************************************************************************************** +* C P U D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* To properly initialize the baudrate clocks of the communication interface, typically + * the speed of the crystal oscillator and/or the speed at which the system runs is + * needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and + * BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is + * not dependent on the targets architecture, the byte ordering needs to be known. + * Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects little endian mode and 0 selects + * big endian mode. + * + * Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be + * called the moment the user program is about to be started. This could be used to + * de-initialize application specific parts, for example to stop blinking an LED, etc. + */ +/** \brief Frequency of the external crystal oscillator. */ +#define BOOT_CPU_XTAL_SPEED_KHZ (8000) +/** \brief Desired system speed. */ +#define BOOT_CPU_SYSTEM_SPEED_KHZ (24000) +/** \brief Motorola or Intel style byte ordering. */ +#define BOOT_CPU_BYTE_ORDER_MOTOROLA (1) +/** \brief Enable/disable hook function call right before user program start. */ +#define BOOT_CPU_USER_PROGRAM_START_HOOK (0) + + +/**************************************************************************************** +* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N +****************************************************************************************/ +/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE + * configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed + * in bits/second. The maximum amount of data bytes in a message for data transmission + * and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA, + * respectively. It is common for a microcontroller to have more than 1 UART interface + * on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface. + * + */ +/** \brief Enable/disable UART transport layer. */ +#define BOOT_COM_UART_ENABLE (1) +/** \brief Configure the desired communication speed. */ +#define BOOT_COM_UART_BAUDRATE (57600) +/** \brief Configure number of bytes in the target->host data packet. */ +#define BOOT_COM_UART_TX_MAX_DATA (64) +/** \brief Configure number of bytes in the host->target data packet. */ +#define BOOT_COM_UART_RX_MAX_DATA (64) +/** \brief Select the desired UART peripheral as a zero based index. */ +#define BOOT_COM_UART_CHANNEL_INDEX (0) + + +/**************************************************************************************** +* F I L E S Y S T E M I N T E R F A C E C O N F I G U R A T I O N +****************************************************************************************/ +/* The file system interface is selected by setting the BOOT_FILE_SYS_ENABLE configurable + * to 1. This enables support for firmware updates from a file stored on a locally + * attached file system such as an SD-card. Note that this interface can be enabled + * together with one of the remote communication interfaces such as UART, CAN or USB. + * + * Set BOOT_FILE_LOGGING_ENABLE to 1 if you would like log messages to be created during + * a firmware update. The hook function FileFirmwareUpdateLogHook() will be called each + * time a new string formatted log entry is available. This could be used during testing + * by outputting the string on UART or to create a log file on the file system itself. + * + * Set BOOT_FILE_ERROR_HOOK_ENABLE to 1 if you would like to be informed in case an error + * occurs during the firmware update. This could for example be used to turn on an error + * LED to inform the user that something went wrong. Inspecting the log messages provides + * additional information on the error cause. + * + * Set BOOT_FILE_STARTED_HOOK_ENABLE to 1 if you would like to be informed when a new + * firmware update is started by the bootloader. + * + * Set BOOT_FILE_COMPLETED_HOOK_ENABLE to 1 if you would like to be informed when a + * firmware update is completed by the bootloader. + */ +/** \brief Enable/disable support for firmware updates from a locally attached storage.*/ +#define BOOT_FILE_SYS_ENABLE (0) +/** \brief Enable/disable logging messages during firmware updates. */ +#define BOOT_FILE_LOGGING_ENABLE (0) +/** \brief Enable/disable a hook function that is called upon detection of an error. */ +#define BOOT_FILE_ERROR_HOOK_ENABLE (0) +/** \brief Enable/disable a hook function that is called at the start of the update. */ +#define BOOT_FILE_STARTED_HOOK_ENABLE (0) +/** \brief Enable/disable a hook function that is called at the end of the update. */ +#define BOOT_FILE_COMPLETED_HOOK_ENABLE (0) + + +/**************************************************************************************** +* B A C K D O O R E N T R Y C O N F I G U R A T I O N +****************************************************************************************/ +/* It is possible to implement an application specific method to force the bootloader to + * stay active after a reset. Such a backdoor entry into the bootloader is desired in + * situations where the user program does not run properly and therefore cannot + * reactivate the bootloader. By enabling these hook functions, the application can + * implement the backdoor, which overrides the default backdoor entry that is programmed + * into the bootloader. When desired for security purposes, these hook functions can + * also be implemented in a way that disables the backdoor entry altogether. + */ +/** \brief Enable/disable the backdoor override hook functions. */ +#define BOOT_BACKDOOR_HOOKS_ENABLE (0) + + +/**************************************************************************************** +* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* The NVM driver typically supports erase and program operations of the internal memory + * present on the microcontroller. Through these hook functions the NVM driver can be + * extended to support additional memory types such as external flash memory and serial + * eeproms. The size of the internal memory in kilobytes is specified with configurable + * BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can + * be overridden with a application specific method by enabling configuration switch + * BOOT_NVM_CHECKSUM_HOOKS_ENABLE. + */ +/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */ +#define BOOT_NVM_HOOKS_ENABLE (0) +/** \brief Configure the size of the default memory device (typically flash EEPROM). */ +#define BOOT_NVM_SIZE_KB (256) +/** \brief Enable/disable hooks functions to override the user program checksum handling. */ +#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0) + + +/**************************************************************************************** +* W A T C H D O G D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* The COP driver cannot be configured internally in the bootloader, because its use + * and configuration is application specific. The bootloader does need to service the + * watchdog in case it is used. When the application requires the use of a watchdog, + * set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through + * hook functions. + */ +/** \brief Enable/disable the hook functions for controlling the watchdog. */ +#define BOOT_COP_HOOKS_ENABLE (0) + + +#endif /* BLT_CONF_H */ +/*********************************** end of blt_conf.h *********************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/boot.dox b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/boot.dox new file mode 100644 index 00000000..d6f092ba --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/boot.dox @@ -0,0 +1,7 @@ +/** +\defgroup Boot_HCS12_Evbplus_Dragon12p_CodeWarrior Bootloader +\brief Bootloader. +\ingroup HCS12_Evbplus_Dragon12p_CodeWarrior +*/ + + diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Erase_unsecure_hcs12.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Erase_unsecure_hcs12.cmd new file mode 100644 index 00000000..ca4f6c92 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Erase_unsecure_hcs12.cmd @@ -0,0 +1,78 @@ +// ver 1.1 (7/7/04) +// HCS12X Core erasing + unsecuring command file: +// These commands mass erase the chip then program the security byte to 0xFE (unsecured state). + +// Evaluate the clock divider to set in ECLKDIV/FCLKDIV registers: + +DEFINEVALUEDLG "Information required to unsecure the device" "CLKDIV" 0x49 "To unsecure the device, the command script needs \nthe correct value for ECLKDIV/FCLKDIV onchip\nregisters.\nIf the bus frequency is less than 10 MHz, the value\nto store in ECLKDIV/FCLKDIV is equal to:\n \"bus frequency (kHz) / 175\"\n\nIf the bus frequency is higher than 10 MHz, the value\nto store in ECLKDIV/FCLKDIV is equal to:\n \" bus frequency (kHz) / 1400 + 64\"\n(+64 (0x40) is to set PRDIV8 flag)\n\nDatasheet proposed values:\n\nbus frequency\t\tE/FCLKDIV value (decimal)\n\n 16 \tMHz\t\t73\n 8 \tMHz\t\t39\n 4 \tMHz\t\t19\n 2 \tMHz\t\t9\n 1 \tMHz\t\t4\n" + +// An average programming clock of 175 kHz is chosen. + +// If the oscillator frequency is less than 10 MHz, the value to store +// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 175 ". + +// If the oscillator frequency is higher than 10 MHz, the value to store +// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 1400 + 0x40 (to set PRDIV8 flag)". + +// Datasheet proposed values: +// +// oscillator frequency ECLKDIV/FCLKDIV value (hexadecimal) +// +// 16 MHz $49 +// 8 MHz $27 +// 4 MHz $13 +// 2 MHz $9 +// 1 MHz $4 + + +FLASH RELEASE // do not interact with regular flash programming monitor + +//mass erase flash +reset +wb 0x03c 0x00 //disable cop +wait 20 +wb 0x100 CLKDIV // set FCLKDIV clock divider +wb 0x104 0xFF // FPROT all protection disabled +wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register +wb 0x102 0x00 // clear the WRALL bit in FTSTMOD +wb 0x105 0x02 +wb 0x102 0x10 // set the WRALL bit in FTSTMOD to affect all blocks +ww 0x108 0xFFFE +ww 0x10A 0xFFFF +wb 0x106 0x41 // write MASS ERASE command in FCMD register +wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command +wait 20 // wait for command to complete + +//mass erase eeprom +wb 0x110 CLKDIV // set ECLKDV clock divider +wb 0x114 0xFF // EPROT all protection disabled +wb 0x115 0x30 // clear PVIOL and ACCERR in ESTAT register +wb 0x112 0x00 // clear the WRALL bit in FTSTMOD +wb 0x115 0x02 +ww 0x118 0x0C00 // write to EADDR eeprom address register +ww 0x11A 0x0000 // write to EDATA eeprom data register +wb 0x116 0x41 // write MASS ERASE command in ECMD register +wb 0x115 0x80 // clear CBEIF in ESTAT register to execute the command +wait 20 // wait for command to complete + +//reprogram Security byte to Unsecure state +reset +wb 0x03c 0x00 //disable cop +wait 20 +wb 0x102 0x00 // clear the WRALL bit in FTSTMOD +wb 0x105 0x02 +wb 0x100 CLKDIV // set FCLKDIV clock divider +wb 0x100 CLKDIV // set FCLKDIV clock divider +wb 0x104 0xFF // FPROT all protection disabled +wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register +wb 0x102 0x00 // clear the WRALL bit in FTSTMOD +wb 0x105 0x02 +ww 0xFF0E 0xFFFE // write security byte to "Unsecured" state +wb 0x106 0x20 // write MEMORY PROGRAM command in FCMD register +wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command +wait 20 // wait for command to complete + +reset + +undef CLKDIV // undefine variable + diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Postload.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Postload.cmd new file mode 100644 index 00000000..eb00f379 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Postload.cmd @@ -0,0 +1 @@ +// After load the commands written below will be executed diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Preload.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Preload.cmd new file mode 100644 index 00000000..691c5eed --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Preload.cmd @@ -0,0 +1 @@ +// Before load the commands written below will be executed diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Reset.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Reset.cmd new file mode 100644 index 00000000..f0fc8744 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Reset.cmd @@ -0,0 +1 @@ +// After reset the commands written below will be executed diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Startup.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Startup.cmd new file mode 100644 index 00000000..5f2b5a56 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Startup.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Vppoff.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Vppoff.cmd new file mode 100644 index 00000000..52e399a6 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Vppoff.cmd @@ -0,0 +1 @@ +// After programming the flash, the commands written below will be executed diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Vppon.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Vppon.cmd new file mode 100644 index 00000000..048a6d94 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/P&E_Multilink_USB_Vppon.cmd @@ -0,0 +1 @@ +// Before programming the flash, the commands written below will be executed diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/burner.bbl b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/burner.bbl new file mode 100644 index 00000000..42c21ed5 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/cmd/burner.bbl @@ -0,0 +1,157 @@ +/* logical s-record file */ +OPENFILE "%ABS_FILE%.s19" +format=motorola +busWidth=1 +origin=0 +len=0x1000000 +destination=0 +SRECORD=Sx +SENDBYTE 1 "%ABS_FILE%" +CLOSE + + +/* physical s-record file */ +OPENFILE "%ABS_FILE%.phy" +format = motorola +busWidth = 1 +len = 0x4000 + +/* logical non banked flash at $4000 and $C000 to physical */ +origin = 0x004000 +destination = 0x0F8000 +SENDBYTE 1 "%ABS_FILE%" + +origin = 0x00C000 +destination = 0x0FC000 +SENDBYTE 1 "%ABS_FILE%" + +/* physical FTS512K flash window to physical +origin = 0x008000 +destination = 0x080000 +SENDBYTE 1 "%ABS_FILE%" +*/ + +/* physical FTS256K parts flash window to physical +origin = 0x008000 +destination = 0x0C0000 +SENDBYTE 1 "%ABS_FILE%" +*/ + +/* physical FTS128K parts flash window to physical +origin = 0x008000 +destination = 0x0E0000 +SENDBYTE 1 "%ABS_FILE%" +*/ + +/* physical FTS64K parts flash window to physical +origin = 0x008000 +destination = 0x0F0000 +SENDBYTE 1 "%ABS_FILE%" +*/ + +/* physical FTS32K parts flash window to physical +origin = 0x008000 +destination = 0x0F8000 +SENDBYTE 1 "%ABS_FILE%" +*/ + +/* logical 512 kB banked flash to physical */ +origin = 0x208000 +destination = 0x080000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x218000 +destination = 0x084000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x228000 +destination = 0x088000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x238000 +destination = 0x08C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x248000 +destination = 0x090000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x258000 +destination = 0x094000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x268000 +destination = 0x098000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x278000 +destination = 0x09C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x288000 +destination = 0x0A0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x298000 +destination = 0x0A4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x2A8000 +destination = 0x0A8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x2B8000 +destination = 0x0AC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x2C8000 +destination = 0x0B0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x2D8000 +destination = 0x0B4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x2E8000 +destination = 0x0B8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x2F8000 +destination = 0x0BC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x308000 +destination = 0x0C0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x318000 +destination = 0x0C4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x328000 +destination = 0x0C8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x338000 +destination = 0x0CC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x348000 +destination = 0x0D0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x358000 +destination = 0x0D4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x368000 +destination = 0x0D8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x378000 +destination = 0x0DC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x388000 +destination = 0x0E0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x398000 +destination = 0x0E4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3A8000 +destination = 0x0E8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3B8000 +destination = 0x0EC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3C8000 +destination = 0x0F0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3D8000 +destination = 0x0F4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3E8000 +destination = 0x0F8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3F8000 +destination = 0x0FC000 +SENDBYTE 1 "%ABS_FILE%" + +CLOSE + diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/hooks.c b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/hooks.c new file mode 100644 index 00000000..b26a14af --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/hooks.c @@ -0,0 +1,217 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Boot\hooks.c +* \brief Bootloader callback source file. +* \ingroup Boot_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ + + +/**************************************************************************************** +* B A C K D O O R E N T R Y H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Initializes the backdoor entry option. +** \return none. +** +****************************************************************************************/ +void BackDoorInitHook(void) +{ +} /*** end of BackDoorInitHook ***/ + + +/************************************************************************************//** +** \brief Checks if a backdoor entry is requested. +** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool BackDoorEntryHook(void) +{ + /* default implementation always activates the bootloader after a reset */ + return BLT_TRUE; +} /*** end of BackDoorEntryHook ***/ +#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* C P U D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0) +/************************************************************************************//** +** \brief Callback that gets called when the bootloader is about to exit and +** hand over control to the user program. This is the last moment that +** some final checking can be performed and if necessary prevent the +** bootloader from activiting the user program. +** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep +** keep the bootloader active. +** +****************************************************************************************/ +blt_bool CpuUserProgramStartHook(void) +{ + /* okay to start the user program */ + return BLT_TRUE; +} /*** end of CpuUserProgramStartHook ***/ +#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */ + + +/**************************************************************************************** +* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_NVM_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Callback that gets called at the start of the internal NVM driver +** initialization routine. +** \return none. +** +****************************************************************************************/ +void NvmInitHook(void) +{ +} /*** end of NvmInitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of the NVM driver write +** routine. It allows additional memory to be operated on. If the address +** is not within the range of the additional memory, then +** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't +** been written yet. +** \param addr Start address. +** \param len Length in bytes. +** \param data Pointer to the data buffer. +** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is +** not within the supported memory range, or BLT_NVM_ERROR is the write +** operation failed. +** +****************************************************************************************/ +blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data) +{ + return BLT_NVM_NOT_IN_RANGE; +} /*** end of NvmWriteHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of the NVM driver erase +** routine. It allows additional memory to be operated on. If the address +** is not within the range of the additional memory, then +** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory +** hasn't been erased yet. +** \param addr Start address. +** \param len Length in bytes. +** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is +** not within the supported memory range, or BLT_NVM_ERROR is the erase +** operation failed. +** +****************************************************************************************/ +blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len) +{ + return BLT_NVM_NOT_IN_RANGE; +} /*** end of NvmEraseHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the end of the NVM programming session. +** \return BLT_TRUE is successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmDoneHook(void) +{ + return BLT_TRUE; +} /*** end of NvmDoneHook ***/ +#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */ + + +#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Verifies the checksum, which indicates that a valid user program is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmVerifyChecksumHook(void) +{ + return BLT_TRUE; +} /*** end of NvmVerifyChecksum ***/ + + +/************************************************************************************//** +** \brief Writes a checksum of the user program to non-volatile memory. This is +** performed once the entire user program has been programmed. Through +** the checksum, the bootloader can check if a valid user programming is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmWriteChecksumHook(void) +{ + return BLT_TRUE; +} +#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* W A T C H D O G D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_COP_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Callback that gets called at the end of the internal COP driver +** initialization routine. It can be used to configure and enable the +** watchdog. +** \return none. +** +****************************************************************************************/ +void CopInitHook(void) +{ +} /*** end of CopInitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the end of the internal COP driver +** service routine. This gets called upon initialization and during +** potential long lasting loops and routine. It can be used to service +** the watchdog to prevent a watchdog reset. +** \return none. +** +****************************************************************************************/ +void CopServiceHook(void) +{ +} /*** end of CopServiceHook ***/ +#endif /* BOOT_COP_HOOKS_ENABLE > 0 */ + + + +/*********************************** end of hooks.c ************************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/C_Layout.hwl b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/C_Layout.hwl new file mode 100644 index 00000000..3b16d98a --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/C_Layout.hwl @@ -0,0 +1,20 @@ +OPEN source 0 0 60 39 +Source < attributes MARKS off +OPEN assembly 60 0 40 31 +Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C +OPEN procedure 0 39 60 17 +Procedure < attributes VALUES on,TYPES off +OPEN register 60 31 40 25 +Register < attributes FORMAT AUTO,COMPLEMENT None +OPEN memory 60 56 40 22 +Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80 +OPEN data 0 56 60 22 +Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 +OPEN data 0 78 60 22 +Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 +OPEN command 60 78 40 22 +Command < attributes CACHESIZE 1000 +bckcolor 50331647 +font 'Courier New' 9 BLACK +AUTOSIZE on +ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/Default.mem b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/Default.mem new file mode 100644 index 0000000000000000000000000000000000000000..d0bbb2e4d27ec9e58f5004d60ac5c4b6e68fec3e GIT binary patch literal 161 zcmX>ckl4`d7#iZQ;Opwk5aj5~(9qB@0f_N}#>OtNo*;jq9v}uPCPGgSL=Vso;_c}M E0JXYCwEzGB literal 0 HcmV?d00001 diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/P&E_Multilink_USB.ini b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/P&E_Multilink_USB.ini new file mode 100644 index 00000000..afeb0cce --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/ide/P&E_Multilink_USB.ini @@ -0,0 +1,95 @@ +[STARTUP] +CPUTARGETTYPE=0 +USE_CYCLONEPRO_RELAYS=0 +PORT=21 +interface_selection=1 +SHOWDIALOG=0 +IO_DELAY_SET=1 +frequency_has_changed_old_io_delay_cnt=29 +CyclonePro_poweroffonexit=0 +CyclonePro_currentvoltage=255 +CyclonePro_PowerDownDelay=250 +CyclonePro_PowerUpDelay=250 +IO_DELAY_CNT=29 +PCI_DELAY=0 +RESET_DELAY=0 + + + + + + + + + + +[Environment Variables] +GENPATH={Project}..\src;{Compiler}lib\hc12c\src;{Compiler}lib\hc12c\include;{Compiler}lib\hc12c\lib;{Compiler}lib\xgatec\src;{Compiler}lib\xgatec\include;{Compiler}lib\xgatec\lib +LIBPATH={Compiler}lib\hc12c\include;{Compiler}lib\xgatec\include +OBJPATH={Project}..\bin +TEXTPATH={Project}..\bin +ABSPATH={Project}..\bin + +[HI-WAVE] +Target=icd12 +Layout=C_layout.hwl +LoadDialogOptions=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main" +CPU=HC12 +MainFrame=2,3,-1,-31,-1,-1,200,200,1640,967 +TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806 +AEFWarningDialog=FALSE + + + + +[HC12MultilinkCyclonePro_GDI_SETTINGS] +CMDFILE0=CMDFILE STARTUP ON ".\..\cmd\P&E_Multilink_USB_startup.cmd" +CMDFILE1=CMDFILE RESET ON ".\..\cmd\P&E_Multilink_USB_reset.cmd" +CMDFILE2=CMDFILE PRELOAD ON ".\..\cmd\P&E_Multilink_USB_preload.cmd" +CMDFILE3=CMDFILE POSTLOAD ON ".\..\cmd\P&E_Multilink_USB_postload.cmd" +CMDFILE4=CMDFILE VPPON ON ".\..\cmd\P&E_Multilink_USB_vppon.cmd" +CMDFILE5=CMDFILE VPPOFF ON ".\..\cmd\P&E_Multilink_USB_vppoff.cmd" +CMDFILE6=CMDFILE UNSECURE ON ".\..\cmd\P&E_Multilink_USB_erase_unsecure_hcs12.cmd" +MCUID=0x03D9 +NV_PARAMETER_FILE=C:\Program Files (x86)\Freescale\CWS12v5.1\prog\FPP\mcu03D9.fpp +NV_SAVE_WSP=0 +NV_AUTO_ID=1 +CHIPSECURE=CHIPSECURE SETUP 0xFF0F 0x3 0x2 +HWBPD_MCUID03D9_HWBPM0=HWBPM MODE AUTOMATIC BPM22BITS 0x28 SKIP_OFF +HWBPD_MCUID03D9_BKPT_REMAP0=HWBPM REMAP_22BITS RANGE 0x4000 0x7FFF 0x3E +HWBPD_MCUID03D9_BKPT_REMAP1=HWBPM REMAP_22BITS RANGE 0xC000 0xFFFF 0x3F +HWBPD_MCUID03D9_HWBPM1=HWBPM SET16BITS 0x0 0x0 0x0 0x0 +HWBPD_MCUID03D9_HWBPM2=HWBPM SET22BITS 0x0 0x0 0x0 0x0 + + + + + + + + + + +[ICD12] +COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL +SETCLKSW=0 +HOTPLUGGING=0 +DETECTRUNNING=0 +RESYNCONCOPRESET=0 +BDMAutoSpeed=0 +BDMClockSpeed=29 +HIGHIODELAYCONSTFORPLL=40 + +[PORT] +IP= + + +[Recent Applications File List] +File0=C:\Work\software\OpenBLT\Target\Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Boot\bin\openblt_evbplus_dragon12p.abs +File1=C:\Work\software\OpenBLT\Target\Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\bin\demoprog_evbplus_dragon12p.abs +File2= +File3= +LoadFlags0=NORUNAFTERLOAD +LoadFlags1=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main" +LoadFlags2= +LoadFlags3= diff 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See the text below at the #else // __HCS12X__ */ + +/* + According to the -Cp option of the compiler the + __DPAGE__, __PPAGE__ and __EPAGE__ macros are defined. + If none of them is given as argument, then no page accesses should occur and + this runtime routine should not be used ! + To be on the save side, the runtime routines are created anyway. +*/ + +/* Compile with option -DHCS12 to activate this code */ +#if defined(HCS12) || defined(_HCS12) || defined(__HCS12__) +#ifndef PPAGE_ADDR +#ifdef __PPAGE_ADR__ +#define PPAGE_ADDR __PPAGE_ADR__ +#else +#define PPAGE_ADDR (0x30 + REGISTER_BASE) +#endif +#endif +#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ +#define __PPAGE__ +#endif +/* Compile with option -DDG128 to activate this code */ +#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */ +#ifndef PPAGE_ADDR +#define PPAGE_ADDR (0xFF+REGISTER_BASE) +#endif +#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ +#define __PPAGE__ +#endif +#elif defined(HC812A4) +/* all setting default to A4 already */ +#endif + + +#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__) +/* as default use all page registers */ +#define __DPAGE__ +#define __EPAGE__ +#define __PPAGE__ +#endif + +/* modify the following defines to your memory configuration */ + +#define EPAGE_LOW_BOUND 0x400u +#define EPAGE_HIGH_BOUND 0x7ffu + +#define DPAGE_LOW_BOUND 0x7000u +#define DPAGE_HIGH_BOUND 0x7fffu + +#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1u) +#define PPAGE_HIGH_BOUND 0xBFFFu + +#ifndef REGISTER_BASE +#define REGISTER_BASE 0x0u +#endif + +#ifndef DPAGE_ADDR +#define DPAGE_ADDR (0x34u+REGISTER_BASE) +#endif +#ifndef EPAGE_ADDR +#define EPAGE_ADDR (0x36u+REGISTER_BASE) +#endif +#ifndef PPAGE_ADDR +#define PPAGE_ADDR (0x35u+REGISTER_BASE) +#endif + +/* + The following parts about the defines are assumed in the code of _GET_PAGE_REG : + - the memory region controlled by DPAGE is above the area controlled by the EPAGE and + below the area controlled by the PPAGE. + - the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1 +*/ +#if (EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND) || (EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND) || (DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND) || (DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND) || (PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND) +#error /* please adapt _GET_PAGE_REG for this non default page configuration */ +#endif + +#if (DPAGE_HIGH_BOUND+1u) != PPAGE_LOW_BOUND +#error /* please adapt _GET_PAGE_REG for this non default page configuration */ +#endif + + +/* this module does either control if any access is in the bounds of the specified page or */ +/* ,if only one page is specified, just use this page. */ +/* This behavior is controlled by the define USE_SEVERAL_PAGES. */ +/* If !USE_SEVERAL_PAGES does increase the performance significantly */ +/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */ +/* by this single page. But this is should not cause problems because the page is restored to the old value before any other access could occur */ + +#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__) +/* no page at all is specified */ +/* only specifying the right pages will speed up these functions a lot */ +#define USE_SEVERAL_PAGES 1 +#elif (defined(__DPAGE__) && defined(__EPAGE__)) || (defined(__DPAGE__) && defined(__PPAGE__)) || (defined(__EPAGE__) && defined(__PPAGE__)) +/* more than one page register is used */ +#define USE_SEVERAL_PAGES 1 +#else + +#define USE_SEVERAL_PAGES 0 + +#if defined(__DPAGE__) /* check which pages are used */ +#define PAGE_ADDR PPAGE_ADDR +#elif defined(__EPAGE__) +#define PAGE_ADDR EPAGE_ADDR +#elif defined(__PPAGE__) +#define PAGE_ADDR PPAGE_ADDR +#else /* we do not know which page, decide it at runtime */ +#error /* must not happen */ +#endif + +#endif + + +#if USE_SEVERAL_PAGES /* only needed for several pages support */ +/*--------------------------- _GET_PAGE_REG -------------------------------- + Runtime routine to detect the right register depending on the 16 bit offset part + of an address. + This function is only used by the functions below. + + Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced. + + Arguments : + - Y : offset part of an address + + Result : + if address Y is controlled by a page register : + - X : address of page register if Y is controlled by an page register + - Zero flag cleared + - all other registers remain unchanged + + if address Y is not controlled by a page register : + - Zero flag is set + - all registers remain unchanged + + --------------------------- _GET_PAGE_REG ----------------------------------*/ + +#if defined(__DPAGE__) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_DPAGE: + CPY #DPAGE_LOW_BOUND ;/* test of lower bound of DPAGE */ +#if defined(__EPAGE__) + BLO L_EPAGE ;/* EPAGE accesses are possible */ +#else + BLO L_NOPAGE ;/* no paged memory below accesses */ +#endif + CPY #DPAGE_HIGH_BOUND ;/* test of higher bound DPAGE/lower bound PPAGE */ +#if defined(__PPAGE__) + BHI L_PPAGE ;/* EPAGE accesses are possible */ +#else + BHI L_NOPAGE ;/* no paged memory above accesses */ +#endif +FOUND_DPAGE: + LDX #DPAGE_ADDR ;/* load page register address and clear zero flag */ + RTS + +#if defined(__PPAGE__) +L_PPAGE: + CPY #PPAGE_HIGH_BOUND ;/* test of higher bound of PPAGE */ + BHI L_NOPAGE +FOUND_PPAGE: + LDX #PPAGE_ADDR ;/* load page register address and clear zero flag */ + RTS +#endif + +#if defined(__EPAGE__) +L_EPAGE: + CPY #EPAGE_LOW_BOUND ;/* test of lower bound of EPAGE */ + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ;/* test of higher bound of EPAGE */ + BHI L_NOPAGE + +FOUND_EPAGE: + LDX #EPAGE_ADDR ;/* load page register address and clear zero flag */ + RTS +#endif + +L_NOPAGE: + ORCC #0x04 ;/* sets zero flag */ + RTS + } +} + +#else /* !defined(__DPAGE__) */ + +#if defined( __PPAGE__ ) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_PPAGE: + CPY #PPAGE_LOW_BOUND ;/* test of lower bound of PPAGE */ +#if defined( __EPAGE__ ) + BLO L_EPAGE +#else + BLO L_NOPAGE ;/* no paged memory below */ +#endif + CPY #PPAGE_HIGH_BOUND ;/* test of higher bound PPAGE */ + BHI L_NOPAGE +FOUND_PPAGE: + LDX #PPAGE_ADDR ;/* load page register address and clear zero flag */ + RTS +#if defined( __EPAGE__ ) +L_EPAGE: + CPY #EPAGE_LOW_BOUND ;/* test of lower bound of EPAGE */ + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ;/* test of higher bound of EPAGE */ + BHI L_NOPAGE +FOUND_EPAGE: + LDX #EPAGE_ADDR ;/* load page register address and clear zero flag */ + RTS +#endif + +L_NOPAGE: ;/* not in any allowed page area */ + ;/* its a far access to a non paged variable */ + ORCC #0x04 ;/* sets zero flag */ + RTS + } +} + +#else /* !defined(__DPAGE__ ) && !defined( __PPAGE__) */ +#if defined(__EPAGE__) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_EPAGE: + CPY #EPAGE_LOW_BOUND ;/* test of lower bound of EPAGE */ + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ;/* test of higher bound of EPAGE */ + BHI L_NOPAGE +FOUND_EPAGE: + LDX #EPAGE_ADDR ;/* load page register address and clear zero flag */ + RTS + +L_NOPAGE: ;/* not in any allowed page area */ + ;/* its a far access to a non paged variable */ + ORCC #0x04 ;/* sets zero flag */ + RTS + } +} + +#endif /* defined(__EPAGE__) */ +#endif /* defined(__PPAGE__) */ +#endif /* defined(__DPAGE__) */ + +#endif /* USE_SEVERAL_PAGES */ + +/*--------------------------- _SET_PAGE -------------------------------- + Runtime routine to set the right page register. This routine is used if the compiler + does not know the right page register, i.e. if the option -Cp is used for more than + one page register or if the runtime option is used for one of the -Cp options. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - page part written into the correct page register. + - the old page register content is destroyed + - all processor registers remains unchanged + --------------------------- _SET_PAGE ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _SET_PAGE(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + STAB 0,X ;/* set page register */ +L_NOPAGE: + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + STAB PAGE_ADDR ;/* set page register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _LOAD_FAR_8 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the B register + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_8 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_8(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ;/* save A register */ + LDAA 0,X ;/* save page register */ + STAB 0,X ;/* set page register */ + LDAB 0,Y ;/* actual load, overwrites page */ + STAA 0,X ;/* restore page register */ + PULA ;/* restore A register */ + PULX ;/* restore X register */ + RTS +L_NOPAGE: + LDAB 0,Y ;/* actual load, overwrites page */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ;/* save A register */ + LDAA PAGE_ADDR ;/* save page register */ + STAB PAGE_ADDR ;/* set page register */ + LDAB 0,Y ;/* actual load, overwrites page */ + STAA PAGE_ADDR ;/* restore page register */ + PULA ;/* restore A register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _LOAD_FAR_16 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the Y register + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_16 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_16(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ;/* save A register */ + LDAA 0,X ;/* save page register */ + STAB 0,X ;/* set page register */ + LDY 0,Y ;/* actual load, overwrites address */ + STAA 0,X ;/* restore page register */ + PULA ;/* restore A register */ + PULX ;/* restore X register */ + RTS +L_NOPAGE: + LDY 0,Y ;/* actual load, overwrites address */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ;/* save A register */ + LDAA PAGE_ADDR ;/* save page register */ + STAB PAGE_ADDR ;/* set page register */ + LDY 0,Y ;/* actual load, overwrites address */ + STAA PAGE_ADDR ;/* restore page register */ + PULA ;/* restore A register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _LOAD_FAR_24 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the Y:B registers + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_24 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_24(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ;/* save A register */ + LDAA 0,X ;/* save page register */ + STAB 0,X ;/* set page register */ + LDAB 0,Y ;/* actual load, overwrites page of address */ + LDY 1,Y ;/* actual load, overwrites offset of address */ + STAA 0,X ;/* restore page register */ + PULA ;/* restore A register */ + PULX ;/* restore X register */ + RTS +L_NOPAGE: + LDAB 0,Y ;/* actual load, overwrites page of address */ + LDY 1,Y ;/* actual load, overwrites offset of address */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ;/* save A register */ + LDAA PAGE_ADDR ;/* save page register */ + STAB PAGE_ADDR ;/* set page register */ + LDAB 0,Y ;/* actual load, overwrites page of address */ + LDY 1,Y ;/* actual load, overwrites offset of address */ + STAA PAGE_ADDR ;/* restore page register */ + PULA ;/* restore A register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ + +} + +/*--------------------------- _LOAD_FAR_32 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - low 16 bit of value to be read in the D registers + - high 16 bit of value to be read in the Y registers + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_32 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_32(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + LDAA 0,X ;/* save page register */ + PSHA ;/* put it onto the stack */ + STAB 0,X ;/* set page register */ + LDD 2,Y ;/* actual load, low word */ + LDY 0,Y ;/* actual load, high word */ + MOVB 1,SP+,0,X ;/* restore page register */ + PULX ;/* restore X register */ + RTS +L_NOPAGE: + LDD 2,Y ;/* actual load, low word */ + LDY 0,Y ;/* actual load, high word */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + LDAA PAGE_ADDR ;/* save page register */ + PSHA ;/* put it onto the stack */ + STAB PAGE_ADDR ;/* set page register */ + LDD 2,Y ;/* actual load, low word */ + LDY 0,Y ;/* actual load, high word */ + MOVB 1,SP+,PAGE_ADDR ;/* restore page register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _STORE_FAR_8 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the B register + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_8 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_8(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHB ;/* save B register */ + LDAB 0,X ;/* save page register */ + MOVB 0,SP, 0,X ;/* set page register */ + STAA 0,Y ;/* store the value passed in A */ + STAB 0,X ;/* restore page register */ + PULB ;/* restore B register */ + PULX ;/* restore X register */ + RTS +L_NOPAGE: + STAA 0,Y ;/* store the value passed in A */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHB ;/* save A register */ + LDAB PAGE_ADDR ;/* save page register */ + MOVB 0,SP,PAGE_ADDR ;/* set page register */ + STAA 0,Y ;/* store the value passed in A */ + STAB PAGE_ADDR ;/* restore page register */ + PULB ;/* restore B register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _STORE_FAR_16 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the X register + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_16 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_16(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHA + LDAA 0,X ;/* save page register */ + STAB 0,X ;/* set page register */ + MOVW 1,SP,0,Y ;/* store the value passed in X */ + STAA 0,X ;/* restore page register */ + PULA ;/* restore A register */ + PULX ;/* restore X register */ + RTS + +L_NOPAGE: + STX 0,Y ;/* store the value passed in X */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ;/* save A register */ + LDAA PAGE_ADDR ;/* save page register */ + STAB PAGE_ADDR ;/* set page register */ + STX 0,Y ;/* store the value passed in X */ + STAA PAGE_ADDR ;/* restore page register */ + PULA ;/* restore A register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _STORE_FAR_24 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the X:A registers (X : low 16 bit, A : high 8 bit) + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_24 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_24(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHA + LDAA 0,X ;/* save page register */ + STAB 0,X ;/* set page register */ + MOVW 1,SP, 1,Y ;/* store the value passed in X */ + MOVB 0,SP, 0,Y ;/* store the value passed in A */ + STAA 0,X ;/* restore page register */ + PULA ;/* restore A register */ + PULX ;/* restore X register */ + RTS + +L_NOPAGE: + STX 1,Y ;/* store the value passed in X */ + STAA 0,Y ;/* store the value passed in X */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ;/* save A register */ + LDAA PAGE_ADDR ;/* save page register */ + STAB PAGE_ADDR ;/* set page register */ + MOVB 0,SP, 0,Y ;/* store the value passed in A */ + STX 1,Y ;/* store the value passed in X */ + STAA PAGE_ADDR ;/* restore page register */ + PULA ;/* restore A register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _STORE_FAR_32 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address is on the stack at 3,SP (just below the return address) + - value to be stored in the X:D registers (D : low 16 bit, X : high 16 bit) + + Result : + - value stored at the address + - all registers remains unchanged + - the page part is removed from the stack + - all page register still contain the same value + --------------------------- _STORE_FAR_32 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_32(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHD + LDAA 0,X ;/* save page register */ + MOVB 6,SP, 0,X ;/* set page register */ + MOVW 2,SP, 0,Y ;/* store the value passed in X (high word) */ + MOVW 0,SP, 2,Y ;/* store the value passed in D (low word) */ + STAA 0,X ;/* restore page register */ + PULD ;/* restore A register */ + BRA done + +L_NOPAGE: + MOVW 0,SP, 0,Y ;/* store the value passed in X (high word) */ + STD 2,Y ;/* store the value passed in D (low word) */ +done: + PULX ;/* restore X register */ + MOVW 0,SP, 1,+SP ;/* move return address */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHD ;/* save D register */ + LDAA PAGE_ADDR ;/* save page register */ + LDAB 4,SP ;/* load page part of address */ + STAB PAGE_ADDR ;/* set page register */ + STX 0,Y ;/* store the value passed in X */ + MOVW 0,SP, 2,Y ;/* store the value passed in D (low word) */ + STAA PAGE_ADDR ;/* restore page register */ + PULD ;/* restore D register */ + MOVW 0,SP, 1,+SP ;/* move return address */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _FAR_COPY_RC -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of the source int the X register + - page part of the source in the A register + - offset part of the dest int the Y register + - page part of the dest in the B register + - number of bytes to be copied is defined by the next 2 bytes after the return address. + + Result : + - memory area copied + - no registers are saved, i.e. all registers may be destroyed + - all page register still contain the same value as before the call + - the function returns after the constant defining the number of bytes to be copied + + + stack-structure at the loop-label: + 0,SP : destination offset + 2,SP : source page + 3,SP : destination page + 4,SP : source offset + 6,SP : points to length to be copied. This function returns after the size + + A usual call to this function looks like: + + struct Huge src, dest; + ; ... + LDX #src + LDAA #PAGE(src) + LDY #dest + LDAB #PAGE(dest) + JSR _FAR_COPY_RC + DC.W sizeof(struct Huge) + ; ... + + --------------------------- _FAR_COPY_RC ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_RC(void) { +#if USE_SEVERAL_PAGES + asm { + DEX ;/* source addr-=1, because loop counter ends at 1 */ + PSHX ;/* save source offset */ + PSHD ;/* save both pages */ + DEY ;/* destination addr-=1, because loop counter ends at 1 */ + PSHY ;/* save destination offset */ + LDY 6,SP ;/* Load Return address */ + LDX 2,Y+ ;/* Load Size to copy */ + STY 6,SP ;/* Store adjusted return address */ +loop: + LDD 4,SP ;/* load source offset */ + LEAY D,X ;/* calculate actual source address */ + LDAB 2,SP ;/* load source page */ + __PIC_JSR(_LOAD_FAR_8) ;/* load 1 source byte */ + PSHB ;/* save value */ + LDD 0+1,SP ;/* load destination offset */ + LEAY D,X ;/* calculate actual destination address */ + PULA ;/* restore value */ + LDAB 3,SP ;/* load destination page */ + __PIC_JSR(_STORE_FAR_8) ;/* store one byte */ + DEX + BNE loop + LEAS 6,SP ;/* release stack */ + _SRET ;/* debug info only: This is the last instr of a function with a special return */ + RTS ;/* return */ + } +#else + asm { + PSHD ;/* store page registers */ + TFR X,D + PSHY ;/* temporary space */ + LDY 4,SP ;/* load return address */ + ADDD 2,Y+ ;/* calculate source end address. Increment return address */ + STY 4,SP + PULY + PSHD ;/* store src end address */ + LDAB 2,SP ;/* reload source page */ + LDAA PAGE_ADDR ;/* save page register */ + PSHA +loop: + STAB PAGE_ADDR ;/* set source page */ + LDAA 1,X+ ;/* load value */ + MOVB 4,SP, PAGE_ADDR ;/* set destination page */ + STAA 1,Y+ + CPX 1,SP + BNE loop + + LDAA 5,SP+ ;/* restore old page value and release stack */ + STAA PAGE_ADDR ;/* store it into page register */ + _SRET ;/* debug info only: This is the last instr of a function with a special return */ + RTS + } +#endif +} + +/*--------------------------- _FAR_COPY -------------------------------- + + The _FAR_COPY runtime routine was used to copied large memory blocks in previous compiler releases. + However this release now does use _FAR_COPY_RC instead. The only difference is how the size of + the area to be copied is passed into the function. For _FAR_COPY the size is passed on the stack just + above the return address. _FAR_COPY_RC does expect the return address just after the JSR _FAR_COPY_RC call + in the code of the caller. This allows for denser code calling _FAR_COPY_RC but does also need a slightly + larger runtime routine and it is slightly slower. + The _FAR_COPY routine is here now mainly for compatibility with previous releases. + The current compiler does not use it. + +--------------------------- _FAR_COPY ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY(void) { +#if USE_SEVERAL_PAGES + asm { + DEX ;/* source addr-=1, because loop counter ends at 1 */ + PSHX ;/* save source offset */ + PSHD ;/* save both pages */ + DEY ;/* destination addr-=1, because loop counter ends at 1 */ + PSHY ;/* save destination offset */ + LDX 8,SP ;/* load counter, assuming counter > 0 */ + +loop: + LDD 4,SP ;/* load source offset */ + LEAY D,X ;/* calculate actual source address */ + LDAB 2,SP ;/* load source page */ + __PIC_JSR(_LOAD_FAR_8) ;/* load 1 source byte */ + PSHB ;/* save value */ + LDD 0+1,SP ;/* load destination offset */ + LEAY D,X ;/* calculate actual destination address */ + PULA ;/* restore value */ + LDAB 3,SP ;/* load destination page */ + __PIC_JSR(_STORE_FAR_8) ;/* store one byte */ + DEX + BNE loop + LDX 6,SP ;/* load return address */ + LEAS 10,SP ;/* release stack */ + JMP 0,X ;/* return */ + } +#else + asm { + PSHD ;/* store page registers */ + TFR X,D + ADDD 4,SP ;/* calculate source end address */ + STD 4,SP + PULB ;/* reload source page */ + LDAA PAGE_ADDR ;/* save page register */ + PSHA +loop: + STAB PAGE_ADDR ;/* set source page */ + LDAA 1,X+ ;/* load value */ + MOVB 1,SP, PAGE_ADDR ;/* set destination page */ + STAA 1,Y+ + CPX 4,SP + BNE loop + + LDAA 2,SP+ ;/* restore old page value and release stack */ + STAA PAGE_ADDR ;/* store it into page register */ + LDX 4,SP+ ;/* release stack and load return address */ + JMP 0,X ;/* return */ + } +#endif +} + +#else /* __HCS12X__ */ + +/* + The HCS12X knows two different kind of addresses: + - Logical addresses. E.g. + MOVB #page(var),RPAGE + INC var + + - Global addresses E.g. + MOVB #page(var),GPAGE + GLDAA var + INCA + GSTAA var + + Global addresses are used with G-Load's and G-Store's, logical addresses are used for all the other instructions + and occasions. As HC12's or HCS12's do not have the G-Load and G-Store instructions, + global addresses are not used with these processor families. + They are only used with HCS12X chips (and maybe future ones deriving from a HCS12X). + + Logical and Global addresses can point to the same object, however the global and logical address of an object + are different for most objects (actually for all except the registers from 0 to 0x7FF). + Therefore the compiler needs to transform in between them. + + HCS12X Pointer types: + + The following are logical addresses: + - all 16 bit pointers + - "char* __near": always. + - "char *" in the small and banked memory model + - 24 bit dpage, epage, ppage or rpage pointers (*1) (note: the first HCS12X compilers may not support these pointer types) + - "char *__dpage": Note this type only exists for + orthogonality with the HC12 A4 chip which has a DPAGE reg. + It does not apply to the HCS12X. + - "char *__epage": 24 bit pointer using the EPAGE register + - "char *__ppage": 24 bit pointer using the PPAGE register. + As the PPAGE is also used for BANKED code, + using this pointer type is only legal from non banked code. + - "char *__rpage": 24 bit pointer using the RPAGE register + + + The following are global addresses: + "char*": in the large memory model (only HCS12X) + "char* __far": always for HCS12X. + + (*1): For the HC12 and HCS12 "char* __far" and "char*" in the large memory model are also logical. + + Some notes for the HC12/HCS12 programmers. + + The address of a far object for a HC12 and for a HCS12X is different, even if they are at the same place in the memory map. + For the HC12, a far address is using the logical addresses, for the HCS12X however, far addresses are using global addresses. + This does cause troubles for the unaware! + + The conversion routines implemented in this file support the special HCS12XE RAM mapping (when RAMHM is set). + To enable this mapping compile this file with the "-MapRAM" compiler option. + + HCS12X Logical Memory map + + Logical Addresses Used for shadowed at page register Global Address + + 0x000000 .. 0x0007FF Peripheral Registers Not Paged 0x000000 + 0x??0800 .. 0x??0BFF Paged EEPROM EPAGE (@0x17) 0x100000+EPAGE*0x0400 + 0x000C00 .. 0x000FFF Non Paged EEPROM 0xFF0800..0xFF0FFF Not Paged 0x13FC00 + 0x??1000 .. 0x??1FFF Paged RAM RPAGE (@0x16) 0x000000+RPAGE*0x1000 + 0x002000 .. 0x003FFF Non Paged RAM 0xFE1000..0xFF1FFF Not Paged 0x0FE000 + 0x004000 .. 0x007FFF Non Paged FLASH 0xFC8000..0xFCBFFF Not Paged 0x7F4000 + 0x??8000 .. 0x00BFFF Paged FLASH PPAGE (@0x30) 0x400000+PPAGE*0x4000 + 0x00C000 .. 0x00FFFF Non Paged FLASH 0xFF8000..0xFFBFFF Not Paged 0x7FC000 + + NA: Not Applicable + + HCS12X Global Memory map + + Global Addresses Used for Logical mapped at + + 0x000000 .. 0x0007FF Peripheral Registers 0x000000 .. 0x0007FF + 0x000800 .. 0x000FFF DMA registers Not mapped + 0x001000 .. 0x0FFFFF RAM 0x??1000 .. 0x??1FFF + 0x0FE000 .. 0x0FFFFF RAM, Log non paged 0x002000 .. 0x003FFF + 0x100000 .. 0x13FFFF EEPROM 0x??0800 .. 0x??0BFF + 0x13FC00 .. 0x13FFFF EEPROM non paged 0x000C00 .. 0x000FFF + 0x140000 .. 0x3FFFFF External Space Not mapped + 0x400000 .. 0x7FFFFF FLASH 0x??8000 .. 0x??BFFF + 0x7F4000 .. 0x7F7FFF FLASH, Log non paged 0x004000 .. 0x007FFF + 0x7FC000 .. 0x7FFFFF FLASH, Log non paged 0x00C000 .. 0x00FFFF + + HCS12XE Logical Memory map (with RAMHM set) + + Logical Addresses Used for shadowed at page register Global Address + + 0x000000 .. 0x0007FF Peripheral Registers Not Paged 0x000000 + 0x??0800 .. 0x??0BFF Paged EEPROM EPAGE 0x100000+EPAGE*0x0400 + 0x000C00 .. 0x000FFF Non Paged EEPROM 0xFF0800..0xFF0FFF Not Paged 0x13FC00 + 0x??1000 .. 0x??1FFF Paged RAM RPAGE 0x000000+RPAGE*0x1000 + 0x002000 .. 0x003FFF Non Paged RAM 0xFA1000..0xFB1FFF Not Paged 0x0FA000 + 0x004000 .. 0x007FFF Non Paged RAM 0xFC1000..0xFF1FFF Not Paged 0x0FC000 + 0x??8000 .. 0x00BFFF Paged FLASH PPAGE 0x400000+PPAGE*0x4000 + 0x00C000 .. 0x00FFFF Non Paged FLASH 0xFF8000..0xFFBFFF Not Paged 0x7FC000 + + NA: Not Applicable + + HCS12X Global Memory map (with RAMHM set) + + Global Addresses Used for Logical mapped at + + 0x000000 .. 0x0007FF Peripheral Registers 0x000000 .. 0x0007FF + 0x000800 .. 0x000FFF DMA registers Not mapped + 0x001000 .. 0x0FFFFF RAM 0x??1000 .. 0x??1FFF + 0x0FA000 .. 0x0FFFFF RAM, Log non paged 0x002000 .. 0x007FFF + 0x100000 .. 0x13FFFF EEPROM 0x??0800 .. 0x??0BFF + 0x13FC00 .. 0x13FFFF EEPROM non paged 0x000C00 .. 0x000FFF + 0x140000 .. 0x3FFFFF External Space Not mapped + 0x400000 .. 0x7FFFFF FLASH 0x??8000 .. 0x??BFFF + 0x7F4000 .. 0x7F7FFF FLASH, Log non paged Not mapped + 0x7FC000 .. 0x7FFFFF FLASH, Log non paged 0x00C000 .. 0x00FFFF + + + How to read this table: + For logical addresses, the lower 16 bits of the address do determine in which area the address is, + if this address is paged, then this entry also controls and which of the EPAGE, PPAGE or RPAGE + page register is controlling the bits 16 to 23 of the address. + For global addresses, the bits 16 to 23 have to be in the GPAGE register and the lower 16 bits + have to be used with the special G load or store instructions (e.g. GLDAA). + As example the logical address 0x123456 is invalid. Because its lower bits 0x3456 are in a + non paged area, so the page 0x12 does not exist. + The address 0xFE1020 however does exist. To access it, the RPAGE has to contain 0xFE and the + offset 0x1020 has to be used. + + ORG $7000 + MOVB #0xFE, 0x16 ; RPAGE + LDAA 0x1020 ; reads at the logical address 0xFE1020 + + Because the last two RAM pages are also accessible directly from 0x2000 to 0x3FFF, the + following shorter code does read the same memory location: + + ORG $7000 + LDAA 0x2020 ; reads at the logical address 0x2020 + ; which maps to the same memory as 0xFE1020 + + This memory location also has a global address. For logical 0xFE1020 the global address is 0x0FE020. + So the following code does once more access the same memory location: + + ORG $7000 + MOVB #0x0F, 0x10 ; GPAGE + GLDAA 0xE020 ; reads at the global address 0x0FE020 + ; which maps to the same memory as the logical addr. 0xFE1020 + + Therefore every memory location for the HCS12X has up to 3 different addresses. + Up to two logical and one global. + Notes. + - Not every address has a logical equivalent. The external space is only available in the global address space. + + - The PPAGE must only be set if the code is outside of the 0x8000 to 0xBFFF range. + If not, the next code fetch will be from the new wrong PPAGE value. + + - Inside of the paged area, the highest pages are allocated first. So all HCS12X's do have the FF pages + (if they have this memory type at all). + + - For RPAGE, the value 0 is illegal. Otherwise the global addresses would overlap with the registers. + +*/ + +/*lint -e10, -e106, -e30 */ +#if __OPTION_ACTIVE__("-MapRAM") +#define __HCS12XE_RAMHM_SET__ +#endif +/*lint +e10, +e106, +e30 */ + +/*--------------------------- pointer conversion operations -------------------------------*/ + +/*--------------------------- _CONV_GLOBAL_TO_LOGICAL -------------------------------- + Convert 24 bit logical to 24 bit global pointer + ("char*__far" to "char*__gpage") + + Arguments : + - B : page part of global address + - X : 16 offset part of global address + + Postcondition : + - B == page of returned logical address + - X == offset of returned logical address + - Y remains unchanged + - A remains unchanged +*/ +/*--------------------------- Convert 24 bit global to 24 bit logical pointer ----------------------------------*/ + +/* B:X = Logical(B:X) */ +#ifdef __cplusplus +extern "C" +#endif + +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +void NEAR _CONV_GLOBAL_TO_LOGICAL(void) { + asm { + CMPB #0x40 ;/* flash (0x400000..0x7FFFFF) or not? */ + BLO Below400000 +/* from 0x400000 to 0x7FFFFF */ + CMPB #0x7F ;/* check for Unpaged areas 0x7FC000..0x7FFFFF and 0x7F4000..0x7F7FFF */ + BNE PAGED_FLASH_AREA +#ifndef __HCS12XE_RAMHM_SET__ + BITX #0x4000 + BEQ PAGED_FLASH_AREA +#else + CPX #0xC000 + BLO PAGED_FLASH_AREA +#endif +/* from 0x7F4000 to 0x7F7FFF or 0x7FC000 to 0x7FFFFF */ + ;/* Note: offset in X is already OK. */ + CLRB ;/* logical page == 0 */ + RTS +PAGED_FLASH_AREA: ;/* paged flash. Map to 0x8000..0xBFFF */ +/* from 0x400000 to 0x7F3FFF or 0x7F8000 to 0x7FBFFF */ + LSLX ; /* shift 24 bit address 2 bits to the left to get correct page in B */ + ROLB + LSLX + ROLB + LSRX ; /* shift back to get offset from 0x8000 to 0xBFFF */ + SEC + RORX + RTS ;/* done */ + +Below400000: +/* from 0x000000 to 0x3FFFFF */ +#if 0 /* How should we handle mapping to External Space. There is no logical equivalent. This is an error case! */ + CMPB #0x14 ;/* check if above 0x140000. If so, its in the external space */ + BLO Below140000 + ERROR !!!! ;/* this mapping is not possible! What should we do? */ + RTS +Below140000: +/* from 0x000000 to 0x13FFFF */ +#endif + CMPB #0x10 ;/* if >= 0x100000 it's EEPROM */ + BLO Below100000 +/* from 0x100000 to 0x13FFFF (or 0x3FFFFF) */ + CMPB #0x13 ;/* check if its is in the non paged EEPROM area at 0x13FC00..0x13FFFF */ + BLO Below13FC00 + CPX #0xFC00 + BLO Below13FC00 +/* from 0x13FC00 to 0x13FFFF (or 0x3FFFFF) */ + LEAX 0x1000,X ;/* same as SUBX #0xF000 // map from 0xFC00 to 0x0C00 */ + CLRB + RTS +Below13FC00: +/* from 0x100000 to 0x13FBFF */ + PSHA + TFR XH,A ;/* calculate logical page */ + EXG A,B + LSRD + LSRD + PULA + ANDX #0x03FF + LEAX 0x0800,X ;/* same as ORX #0x0800 */ + RTS + +Below100000: +/* from 0x000000 to 0x0FFFFF */ + TSTB + BNE RAM_AREA + CPX #0x1000 + BLO Below001000 +RAM_AREA: +/* from 0x001000 to 0x0FFFFF */ + CMPB #0x0F + BNE PagedRAM_AREA +#ifndef __HCS12XE_RAMHM_SET__ + CPX #0xE000 + BLO PagedRAM_AREA +/* from 0x0FE000 to 0x0FFFFF */ + SUBX #(0xE000-0x2000) ;/* map 0xE000 to 0x2000 */ +#else + CPX #0xA000 + BLO PagedRAM_AREA +/* from 0x0FA000 to 0x0FFFFF */ + SUBX #(0xA000-0x2000) ;/* map 0xA000 to 0x2000 */ +#endif + CLRB ;/* Page is 0 */ + RTS +PagedRAM_AREA: +/* from 0x001000 to 0x0FDFFF */ + PSHA + TFR XH, A ;/* calculate logical page */ + EXG A,B + LSRD + LSRD + LSRD + LSRD + PULA + + ANDX #0x0FFF + LEAX 0x1000,X ;/* same as ORX #0x1000 */ + RTS + +Below001000: +/* from 0x000000 to 0x000FFF */ +#if 0 + CMPA #0x08 + BLO Below000800 +/* from 0x000800 to 0x000FFF */ + /* ??? DMA Regs? */ + RTS +Below000800: +/* from 0x000000 to 0x0007FF */ +#endif + CLRB + RTS + } +} + +/*--------------------------- _CONV_GLOBAL_TO_NEAR -------------------------------- + Convert 24 bit global to 16 bit logical pointer + ("char*__far" to "char*") + + Arguments : + - B : page part of global address + - X : 16 offset part of global address + + Postcondition : + - B is undefined + - A remains unchanged + - X == offset of returned logical address + - Y remains unchanged +*/ +/*--------------------------- Convert 24 bit global to 16 bit logical pointer ----------------------------------*/ + +/* X = Logical(B:X) */ + +#ifdef __cplusplus +extern "C" +#endif + +#define _REUSE_CONV_GLOBAL_TO_LOGICAL 1 + +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +void NEAR _CONV_GLOBAL_TO_NEAR(void){ +#if _REUSE_CONV_GLOBAL_TO_LOGICAL /* do we want an optimized version? */ + __asm JMP _CONV_GLOBAL_TO_LOGICAL; /* offset for NEAR is same as for LOGICAL. */ +#else + asm { + CMPB #0x40 ;/* flash (0x400000..0x7FFFFF) or not? */ + BLO Below400000 +/* from 0x400000 to 0x7FFFFF */ +#ifndef __HCS12XE_RAMHM_SET__ + CMPB #0x7F ;/* check for Unpaged areas 0x7FC000..0x7FFFFF and 0x7F4000..0x7F7FFF */ + BNE PAGED_FLASH_AREA + CPX #0x4000 + BLO PAGED_FLASH_AREA +/* from 0x7F4000 to 0x7FFFFF */ +#else + CMPB #0x7F ;/* check for Unpaged area 0x7FC000..0x7FFFFF */ + BNE PAGED_FLASH_AREA + CPX #0xC000 + BLO PAGED_FLASH_AREA +/* from 0x7FC000 to 0x7FFFFF */ +#endif + ;/* note non PAGED flash areas or paged area 0x7F8000..0x7FBFFF which are mapping all correctly */ + RTS +PAGED_FLASH_AREA: ;/* paged flash. Map to 0x8000..0xBFFF */ +/* from 0x400000 to 0x7F3FFF */ + ANDX #0x3F00 ;/* cut to 0.. 0x3FFF */ + LEAX 0x8000,X ;/* same as ORX #0x8000 ;// move to 0x8000..0xBFFF */ + RTS ;/* done */ + +Below400000: +/* from 0x000000 to 0x3FFFFF */ +#if 0 /* How should we handle mapping to External Space. There is no logical equivalent. This is an error case! */ + CMPB #0x14 ;/* check if above 0x140000. If so, its in the external space */ + BLO Below140000 + ERROR !!!! ;/* this mapping is not possible! What should we do? */ + RTS +Below140000: +/* from 0x000000 to 0x13FFFF */ +#endif + CMPB #0x10 ;/* if >= 0x100000 it's EEPROM */ + BLO Below100000 +/* from 0x100000 to 0x13FFFF (or 0x3FFFFF) */ + CMPB #0x13 ;/* check if its is in the non paged EEPROM area at 0x13FC00..0x13FFFF */ + BNE Below13FC00 + CPX #0xFC00 + BLO Below13FC00 +/* from 0x13FC00 to 0x13FFFF (or 0x3FFFFF) */ + SUBX #0xF000 ;/* map from 0xFC00 to 0x0C00 */ + RTS +Below13FC00: +/* from 0x100000 to 0x13FBFF */ + ANDX #0x03FF + LEAX 0x800,X ;/* same as ORX #0x0800 */ + RTS + +Below100000: +/* from 0x000000 to 0x0FFFFF */ + TBNE B,RAM_AREA + CPX #0x1000 + BLO Below001000 +RAM_AREA: +/* from 0x001000 to 0x0FFFFF */ + CMPB #0x0F + BNE PagedRAM_AREA +#ifndef __HCS12XE_RAMHM_SET__ + CPX #0xE000 + BLO PagedRAM_AREA +/* from 0x0FE000 to 0x0FFFFF */ + SUBX #(0xE000-0x2000) ;/* map 0xE000 to 0x2000 */ +#else + CPX #0xA000 + BLO PagedRAM_AREA +/* from 0x0FA000 to 0x0FFFFF */ + SUBX #(0xA000-0x2000) ;/* map 0xA000 to 0x2000 */ +#endif + RTS +PagedRAM_AREA: +/* from 0x001000 to 0x0FDFFF (0x001000 to 0x0F9FFF if HCS12XE RAM mapping is enabled) */ + ANDX #0x0FFF + LEAX 0x1000,X ;/* same as ORX #0x1000 */ + RTS + +Below001000: +/* from 0x000000 to 0x000FFF */ + RTS + } +#endif +} + +/*--------------------------- _CONV_NEAR_TO_GLOBAL -------------------------------- + Convert 16 bit logical to 24 bit global pointer + ("char*__near" to "char*__far") + + Arguments : + - X : 16 bit near pointer + + Postcondition : + - B == page of returned global address + - X == offset of returned global address + - Y remains unchanged + - A is unspecified +*/ +/*--------------------------- Convert 16 bit logical to 24 bit global pointer ----------------------------------*/ + +/* B:X = Global(X) */ + +#ifdef __cplusplus +extern "C" +#endif + +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +void NEAR _CONV_NEAR_TO_GLOBAL(void){ + asm { + /* syntax: */ + /* input 16 bit offset is bit15..bit0 */ + /* ppage values: ppage7..ppage0 */ + /* epage values: epage7..epage0 */ + /* dpage values: dpage7..dpage0 */ + /* rpage values: rpage7..rpage0 */ + PSHX ;/* D contains bit15..bit0 */ + TFR X,D ;/* D is cheaper to shift */ + LSLD ;/* D contains 0 bit14..bit0, C contains bit15 */ + BCC Below8000 ;/* bit15 == 0? */ + /* from 0x8000 to 0xFFFF */ + LSLD ;/* D contains 00 bit13..bit0, C contains bit14 */ + BCC BelowC000 + LDAB #0x7F + PULX + RTS ;/* returns 0b0111 1111 11 bit13...bit0 */ +BelowC000: ;/* from 0x8000 to 0xBFFF */ + TFR D,X + LDAB __PPAGE_ADR__ + SEC + RORB + RORX + LSRB + RORX + LEAS 2,SP + RTS ;/* returns 0b01 ppage7..ppage0 bit13...bit0 */ +Below8000: + LSLD ;/* D contains 00 bit13..bit0, C contains bit14 */ + BCC Below4000 + /* from 0x4000 to 0x7FFF */ + PULX +#ifndef __HCS12XE_RAMHM_SET__ + LDAB #0x7F +#else + LEAX (0xC000-0x4000),X + LDAB #0x0F +#endif + RTS ;/* returns 0b0111 1111 01 bit13...bit0 */ + +Below4000: + LSLD ;/* D contains 000 bit12..bit0, C contains bit13 */ + BCC Below2000 + /* from 0x2000 to 0x3FFF */ + PULX +#ifndef __HCS12XE_RAMHM_SET__ + LEAX (0xE000-0x2000),X +#else + LEAX (0xA000-0x2000),X +#endif + LDAB #0x0F + RTS ;/* returns 0b0000 1111 111 bit12...bit0 */ + +Below2000: + LSLD ;/* D contains 0000 bit11..bit0, C contains bit12 */ + BCC Below1000 + /* from 0x1000 to 0x1FFF */ + LDAB __RPAGE_ADR__ + LDAA #0x10 + MUL + EORB 0,SP + EORB #0x10 ;/* clear 1 bit */ + STAB 0,SP + TFR A,B + PULX + RTS + +Below1000: + LSLD ;/* D contains 0000 0 bit10..bit0, C contains bit11 */ + BCC Below0800 + /* from 0x0800 to 0x0FFF */ + LSLD ;/* D contains 0000 00 bit9..bit0, C contains bit10 */ + BCC Below0C00 + /* from 0x0C00 to 0x0FFF */ + LDAB #0x13 + PULX + LEAX 0xF000,X + RTS ;/* returns 0b0001 0011 1111 11 bit9...bit0 */ +Below0C00: + /* from 0x0800 to 0x0BFF */ + LDAB __EPAGE_ADR__ + LDAA #0x04 + MUL + EORB 0,SP + EORB #0x08 + STAB 0,SP + TFR A,B + ORAB #0b00010000 + PULX + RTS +Below0800: + PULX + CLRB + RTS + } +} + +/*--------------------------- _CONV_STACK_NEAR_TO_GLOBAL -------------------------------- + Convert 16 bit logical of address on the stack 24 bit global pointer + ("char*__near" to "char*__far") + + Arguments : + - X : 16 bit near pointer + + Postcondition : + - B == page of returned global address + - X == offset of returned global address + - Y remains unchanged + - A is unspecified +*/ +/*--------------------------- Convert 16 bit logical stack address to 24 bit global pointer ----------------------------------*/ + +/* B:X = Global(D) */ + +#ifdef __cplusplus +extern "C" +#endif + +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +void NEAR _CONV_STACK_NEAR_TO_GLOBAL(void){ + asm { + /* syntax: */ + /* input 16 bit offset is bit15..bit0 */ + /* ppage values: ppage7..ppage0 */ + /* epage values: epage7..epage0 */ + /* dpage values: dpage7..dpage0 */ + /* rpage values: rpage7..rpage0 */ + /* stack must be between $1000 and $3FFF. */ + /* actually placing the stack at $1000 implies that the RPAGE register is not set (and correctly initialized) */ + CPX #0x2000 + BLO PAGED_RAM + /* Map 0x2000 to 0x0FE000 (0x0FA000 for HCS12XE RAM mapping is enabled) */ + LDAB #0x0F +#ifndef __HCS12XE_RAMHM_SET__ + LEAX (0xE000-0x2000),X ;/* LEAX is one cycle faster than ADDX # */ +#else + LEAX (0xA000-0x2000),X ;/* LEAX is one cycle faster than ADDX # */ +#endif + RTS +PAGED_RAM: + PSHX + LDAB __RPAGE_ADR__ + LDAA #0x20 + MUL + EORB 0,SP + EORB #0x10 ;/* clear 1 bit */ + STAB 0,SP + TFR A,B + PULX + RTS + } +} + + + +/*--------------------------- _CONV_LOGICAL_TO_GLOBAL -------------------------------- + Convert 24 bit global to 24 bit logical pointer + ("char*__far" to "char*__gpage") + + Arguments : + - B : page part of logical address + - X : 16 offset part of logical address + + Postcondition : + - B == page of returned global address + - X == offset of returned global address + - Y remains unchanged + - A remains unchanged +*/ +/*--------------------------- Convert 24 bit logical to 24 bit global pointer ----------------------------------*/ + +/* B:X = Logical(B:X) */ + +#ifdef __cplusplus +extern "C" +#endif + +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +void NEAR _CONV_LOGICAL_TO_GLOBAL(void) { + + asm { + /* syntax: */ + /* input 16 bit offset is bit15..bit0 */ + /* ppage values: ppage7..ppage0 */ + /* epage values: epage7..epage0 */ + /* dpage values: dpage7..dpage0 */ + /* rpage values: rpage7..rpage0 */ + PSHA ;/* save A across this routine. */ + PSHX ;/* D contains bit15..bit0 */ + PSHB ;/* store page */ + TFR X,D ;/* D is cheaper to shift */ + LSLD ;/* D contains 0 bit14..bit0, C contains bit15 */ + BCC Below8000 ;/* bit15 == 0? */ + /* from 0x8000 to 0xFFFF */ + LSLD ;/* D contains 00 bit13..bit0, C contains bit14 */ + BCC BelowC000 + PULB ;/* cleanup stack */ + LDAB #0x7F + PULX + PULA + RTS ;/* returns 0b0111 1111 11 bit13...bit0 */ +BelowC000: ;/* from 0x8000 to 0xBFFF */ + TFR D,X + PULB ;/* cleanup stack */ + SEC + RORB + RORX + LSRB + RORX + LEAS 2,SP + PULA + RTS ;/* returns 0b01 ppage7..ppage0 bit13...bit0 */ +Below8000: + LSLD ;/* D contains 00 bit13..bit0, C contains bit14 */ + BCC Below4000 + ;/* from 0x4000 to 0x7FFF */ + PULB ;/* cleanup stack */ + PULX +#ifndef __HCS12XE_RAMHM_SET__ + LDAB #0x7F +#else + LEAX (0xC000-0x4000),X + LDAB #0x0F +#endif + PULA + RTS ;/* returns 0b0111 1111 01 bit13...bit0 */ + +Below4000: + LSLD ;/* D contains 000 bit12..bit0, C contains bit13 */ + BCC Below2000 + /* from 0x2000 to 0x3FFF */ + PULB ;/* cleanup stack */ + PULX +#ifndef __HCS12XE_RAMHM_SET__ + LEAX (0xE000-0x2000),X +#else + LEAX (0xA000-0x2000),X +#endif + LDAB #0x0F + PULA + RTS ;/* returns 0b0000 1111 111 bit12...bit0 */ + +Below2000: + LSLD ;/* D contains 0000 bit11..bit0, C contains bit12 */ + BCC Below1000 + /* from 0x1000 to 0x1FFF */ + PULB + LDAA #0x10 + MUL + EORB 0,SP + EORB #0x10 ;/* clear 1 bit */ + STAB 0,SP + TFR A,B + PULX + PULA + RTS + +Below1000: + LSLD ;/* D contains 0000 0 bit10..bit0, C contains bit11 */ + BCC Below0800 + /* from 0x0800 to 0x0FFF */ + LSLD ;/* D contains 0000 00 bit9..bit0, C contains bit10 */ + BCC Below0C00 + /* from 0x0C00 to 0x0FFF */ + PULB ;/* cleanup stack */ + LDAB #0x13 + PULX + LEAX 0xF000,X + PULA + RTS ;/* returns 0b0001 0011 1111 11 bit9...bit0 */ +Below0C00: + /* from 0x0800 to 0x0BFF */ + PULB + LDAA #0x04 + MUL + EORB 0,SP + EORB #0x08 + STAB 0,SP + TFR A,B + ORAB #0b00010000 + PULX + PULA + RTS +Below0800: + PULB + PULX + PULA + CLRB + RTS + } +} + +/*--------------------------- _FAR_COPY_RC HCS12X Routines -------------------------------- + copy larger far memory blocks + There are the following memory block copy routines: + _COPY : 16 bit logical copies. + Src and dest are both near. Note: implemented in rtshc12.c and not here. + _FAR_COPY_RC HC12/HCS12 struct copy routine. + Expects HC12/HCS12 logical 24 bit address. + Note: Does not exist for the HCS12X. + The HC12/HCS12 implementation is implemented above. + _FAR_COPY_GLOBAL_GLOBAL_RC: + _FAR_COPY_GLOBAL_LOGICAL_RC: + _FAR_COPY_LOGICAL_GLOBAL_RC: + _FAR_COPY_LOGICAL_LOGICAL_RC: + _FAR_COPY_NEAR_GLOBAL_RC: + _FAR_COPY_NEAR_LOGICAL_RC: + _FAR_COPY_GLOBAL_NEAR_RC: + _FAR_COPY_LOGICAL_NEAR_RC: HCS12X specific far copy routine. The name describes what the src/dest address format are. + All near src arguments are passed in X, all 24 bit src in X/B. + All near dest arguments are passed in Y, all 24 bit src in Y/A. + (Note: HC12 _FAR_COPY_RC is using X/A as src and Y/B as dest, so the register usage is not the same!) + + Arguments : + - B:X : src address (for NEAR/_COPY: only X) + - A:Y : dest address (for NEAR/_COPY: only Y) + - number of bytes to be copied behind return address (for _COPY: in D register). The number of bytes is always > 0 + + Result : + - memory area copied + - no registers are saved, i.e. all registers may be destroyed + - for _COPY: D contains 0. + - for HCS12X _FAR_COPY_... routines: GPAGE state is unknown +*/ + + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_GLOBAL_GLOBAL_RC(void) { + asm { + PSHD + PSHY + LDY 4,SP ;/* load return address */ + LDD 2,Y+ ;/* load size */ + STY 4,SP ;/* store return address */ + PULY + PSHD + LDAB 3,SP +Loop: + STAB __GPAGE_ADR__ + GLDAA 1,X+ + MOVB 2,SP,__GPAGE_ADR__ + GSTAA 1,Y+ + DECW 0,SP + BNE Loop + LEAS 4,SP + _SRET ;/* debug info only: This is the last instr of a function with a special return */ + RTS + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _SET_PAGE_REG_HCS12X(void) { + /* Sets the page contained in A to the register controlling the logical addr contained in X. */ + /* saves the old page before and returns it in A together with the page address just below the return address. */ + /* X/Y both remain valid. */ + asm { + PSHX + /* 0000..FFFF */ + CPX #0x8000 + BLO _LO8000 + LDX #__PPAGE_ADR__ + BRA Handle +_LO8000: + /* 0000..7FFF */ + CPX #0x1000 + BLO _LO1000 + LDX #__RPAGE_ADR__ + BRA Handle +_LO1000: + LDX #__EPAGE_ADR__ +Handle: + LDAA 0,X ;/* load old page register content */ + STAB 0,X ;/* set new page register */ + STX 4,SP + PULX + RTS + } +} + + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_GLOBAL_LOGICAL_RC(void) { + asm { + STAB __GPAGE_ADR__ + EXG X,Y + TFR A,B + PSHY ;/* space to store size */ + PSHX ;/* allocate some space where _SET_PAGE_REG_HCS12X can return the page */ + LDY 4,SP ;/* load return address */ + LDX 2,Y+ ;/* load size */ + STY 4,SP + LDY 2,SP ;/* restore dest pointer */ + STX 2,SP ;/* store size */ + LDX 0,SP ;/* reload src pointer */ + __PIC_JSR(_SET_PAGE_REG_HCS12X) + +Loop: GLDAB 1,Y+ + STAB 1,X+ + DECW 2,SP + BNE Loop + + PULX ;/* reload page register address */ + STAA 0,X ;/* restore old page content (necessary if it was PPAGE) */ + PULX ;/* clean up stack */ + _SRET ;/* debug info only: This is the last instr of a function with a special return */ + RTS + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_LOGICAL_GLOBAL_RC(void) { + asm { + STAA __GPAGE_ADR__ + PSHY ;/* space to store size */ + PSHX ;/* allocate some space where _SET_PAGE_REG_HCS12X can return the page */ + LDY 4,SP ;/* load return address */ + LDX 2,Y+ ;/* load size */ + STY 4,SP + LDY 2,SP ;/* restore dest pointer */ + STX 2,SP ;/* store size */ + LDX 0,SP ;/* reload src pointer */ + + __PIC_JSR(_SET_PAGE_REG_HCS12X) + +Loop: LDAB 1,X+ + GSTAB 1,Y+ + DECW 2,SP + BNE Loop + + PULX + STAA 0,X ;/* restore old page content (necessary if it was PPAGE) */ + PULX ;/* clean up stack */ + _SRET ;/* debug info only: This is the last instr of a function with a special return */ + RTS + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_LOGICAL_LOGICAL_RC(void) { + asm { + PSHA + __PIC_JSR(_CONV_LOGICAL_TO_GLOBAL); + PULA + __PIC_JMP(_FAR_COPY_GLOBAL_LOGICAL_RC); + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_NEAR_GLOBAL_RC(void) { + asm { + CLRB + __PIC_JMP(_FAR_COPY_LOGICAL_GLOBAL_RC); + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_NEAR_LOGICAL_RC(void) { + asm { + PSHA + __PIC_JSR(_CONV_NEAR_TO_GLOBAL); + PULA + __PIC_JMP(_FAR_COPY_GLOBAL_LOGICAL_RC); + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_GLOBAL_NEAR_RC(void) { + asm { + CLRA /* near to logical (we may have to use another runtime if this gets non trivial as well :-( */ + __PIC_JMP(_FAR_COPY_GLOBAL_LOGICAL_RC); + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_LOGICAL_NEAR_RC(void) { + asm { + EXG A,B + EXG X,Y + PSHA + __PIC_JSR(_CONV_NEAR_TO_GLOBAL); + PULA + EXG A,B + EXG X,Y + __PIC_JMP(_FAR_COPY_LOGICAL_GLOBAL_RC); + } +} + +/* _FAR_COPY_LOGICAL_GLOBAL: is used by some old wizard generated projects. Not used by current setup anymore */ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_LOGICAL_GLOBAL(void) { + asm { + STAA __GPAGE_ADR__ + PSHX ;/* allocate some space where _SET_PAGE_REG_HCS12X can return the page */ + __PIC_JSR(_SET_PAGE_REG_HCS12X) + +Loop: LDAB 1,X+ + GSTAB 1,Y+ + DECW 4,SP + BNE Loop + + PULX + STAA 0,X ;/* restore old page content (necessary if it was PPAGE) */ + + LDX 4,SP+ ;/* load return address and clean stack */ + JMP 0,X + } +} + + +#endif /* __HCS12X__ */ + + +/*----------------- end of code ------------------------------------------------*/ +/*lint --e{766} , runtime.sgm is not a regular header file, it contains a conditionally compiled CODE_SEG pragma */ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/derivative.h b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/derivative.h new file mode 100644 index 00000000..6e1bf282 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/derivative.h @@ -0,0 +1,10 @@ +/* + * Note: This file is recreated by the project wizard whenever the MCU is + * changed and should not be edited by hand + */ + +/* Include the derivative-specific header file */ +#include + +#pragma LINK_INFO DERIVATIVE "mc9s12dg256" + diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/mc9s12dg256.c b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/mc9s12dg256.c new file mode 100644 index 00000000..e3ef8a19 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/mc9s12dg256.c @@ -0,0 +1,366 @@ +/* Based on CPU DB MC9S12DG256_112, version 2.87.346 (RegistersPrg V2.28) */ +/* DataSheet : 9S12DT256DGV3/D V03.04 */ + +#include + +/*lint -save -esym(765, *) */ + + +/* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ +volatile PORTESTR _PORTE; /* Port E Register; 0x00000008 */ +volatile DDRESTR _DDRE; /* Port E Data Direction Register; 0x00000009 */ +volatile PEARSTR _PEAR; /* Port E Assignment Register; 0x0000000A */ +volatile MODESTR _MODE; /* Mode Register; 0x0000000B */ +volatile PUCRSTR _PUCR; /* Pull-Up Control Register; 0x0000000C */ +volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines; 0x0000000D */ +volatile EBICTLSTR _EBICTL; /* External Bus Interface Control; 0x0000000E */ +volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register; 0x00000010 */ +volatile INITRGSTR _INITRG; /* Initialization of Internal Registers Position Register; 0x00000011 */ +volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register; 0x00000012 */ +volatile MISCSTR _MISC; /* Miscellaneous System Control Register; 0x00000013 */ +volatile ITCRSTR _ITCR; /* Interrupt Test Control Register; 0x00000015 */ +volatile ITESTSTR _ITEST; /* Interrupt Test Register; 0x00000016 */ +volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero; 0x0000001C */ +volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One; 0x0000001D */ +volatile INTCRSTR _INTCR; /* Interrupt Control Register; 0x0000001E */ +volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt; 0x0000001F */ +volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0; 0x00000028 */ +volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1; 0x00000029 */ +volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register; 0x0000002A */ +volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register; 0x0000002B */ +volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register; 0x0000002C */ +volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register; 0x0000002D */ +volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register; 0x0000002E */ +volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register; 0x0000002F */ +volatile PPAGESTR _PPAGE; /* Page Index Register; 0x00000030 */ +volatile PORTKSTR _PORTK; /* Port K Data Register; 0x00000032 */ +volatile DDRKSTR _DDRK; /* Port K Data Direction Register; 0x00000033 */ +volatile SYNRSTR _SYNR; /* CRG Synthesizer Register; 0x00000034 */ +volatile REFDVSTR _REFDV; /* CRG Reference Divider Register; 0x00000035 */ +volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register; 0x00000037 */ +volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register; 0x00000038 */ +volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register; 0x00000039 */ +volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register; 0x0000003A */ +volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register; 0x0000003B */ +volatile COPCTLSTR _COPCTL; /* CRG COP Control Register; 0x0000003C */ +volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register; 0x0000003F */ +volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select; 0x00000040 */ +volatile CFORCSTR _CFORC; /* Timer Compare Force Register; 0x00000041 */ +volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register; 0x00000042 */ +volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register; 0x00000043 */ +volatile TSCR1STR _TSCR1; /* Timer System Control Register1; 0x00000046 */ +volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register; 0x00000047 */ +volatile TCTL1STR _TCTL1; /* Timer Control Register 1; 0x00000048 */ +volatile TCTL2STR _TCTL2; /* Timer Control Register 2; 0x00000049 */ +volatile TCTL3STR _TCTL3; /* Timer Control Register 3; 0x0000004A */ +volatile TCTL4STR _TCTL4; /* Timer Control Register 4; 0x0000004B */ +volatile TIESTR _TIE; /* Timer Interrupt Enable Register; 0x0000004C */ +volatile TSCR2STR _TSCR2; /* Timer System Control Register 2; 0x0000004D */ +volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1; 0x0000004E */ +volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2; 0x0000004F */ +volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register; 0x00000060 */ +volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register; 0x00000061 */ +volatile MCCTLSTR _MCCTL; /* Modulus Down Counter underflow; 0x00000066 */ +volatile MCFLGSTR _MCFLG; /* 16-Bit Modulus Down Counter Flag Register; 0x00000067 */ +volatile ICPARSTR _ICPAR; /* Input Control Pulse Accumulator Register; 0x00000068 */ +volatile DLYCTSTR _DLYCT; /* Delay Counter Control Register; 0x00000069 */ +volatile ICOVWSTR _ICOVW; /* Input Control Overwrite Register; 0x0000006A */ +volatile ICSYSSTR _ICSYS; /* Input Control System Control Register; 0x0000006B */ +volatile PBCTLSTR _PBCTL; /* 16-Bit Pulse Accumulator B Control Register; 0x00000070 */ +volatile PBFLGSTR _PBFLG; /* Pulse Accumulator B Flag Register; 0x00000071 */ +volatile ATD0STAT0STR _ATD0STAT0; /* ATD 0 Status Register 0; 0x00000086 */ +volatile ATD0TEST1STR _ATD0TEST1; /* ATD0 Test Register; 0x00000089 */ +volatile ATD0STAT1STR _ATD0STAT1; /* ATD 0 Status Register 1; 0x0000008B */ +volatile ATD0DIENSTR _ATD0DIEN; /* ATD 0 Input Enable Register; 0x0000008D */ +volatile PORTAD0STR _PORTAD0; /* Port AD0 Register; 0x0000008F */ +volatile PWMESTR _PWME; /* PWM Enable Register; 0x000000A0 */ +volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register; 0x000000A1 */ +volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register; 0x000000A2 */ +volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register; 0x000000A3 */ +volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register; 0x000000A4 */ +volatile PWMCTLSTR _PWMCTL; /* PWM Control Register; 0x000000A5 */ +volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register; 0x000000A8 */ +volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register; 0x000000A9 */ +volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register; 0x000000C4 */ +volatile SCI0CR1STR _SCI0CR1; /* SCI 0 Control Register 1; 0x000000CA */ +volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2; 0x000000CB */ +volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1; 0x000000CC */ +volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2; 0x000000CD */ +volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High; 0x000000CE */ +volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low; 0x000000CF */ +volatile SCI1CR1STR _SCI1CR1; /* SCI 1 Control Register 1; 0x000000D2 */ +volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2; 0x000000D3 */ +volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1; 0x000000D4 */ +volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2; 0x000000D5 */ +volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High; 0x000000D6 */ +volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low; 0x000000D7 */ +volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register; 0x000000D8 */ +volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2; 0x000000D9 */ +volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register; 0x000000DA */ +volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register; 0x000000DB */ +volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register; 0x000000DD */ +volatile IBADSTR _IBAD; /* IIC Address Register; 0x000000E0 */ +volatile IBFDSTR _IBFD; /* IIC Frequency Divider Register; 0x000000E1 */ +volatile IBCRSTR _IBCR; /* IIC Control Register; 0x000000E2 */ +volatile IBSRSTR _IBSR; /* IIC Status Register; 0x000000E3 */ +volatile IBDRSTR _IBDR; /* IIC Data I/O Register; 0x000000E4 */ +volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register; 0x000000F0 */ +volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2; 0x000000F1 */ +volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register; 0x000000F2 */ +volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register; 0x000000F3 */ +volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register; 0x000000F5 */ +volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register; 0x000000F8 */ +volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2; 0x000000F9 */ +volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register; 0x000000FA */ +volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register; 0x000000FB */ +volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register; 0x000000FD */ +volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register; 0x00000100 */ +volatile FSECSTR _FSEC; /* Flash Security Register; 0x00000101 */ +volatile FCNFGSTR _FCNFG; /* Flash Configuration Register; 0x00000103 */ +volatile FPROTSTR _FPROT; /* Flash Protection Register; 0x00000104 */ +volatile FSTATSTR _FSTAT; /* Flash Status Register; 0x00000105 */ +volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register; 0x00000106 */ +volatile ECLKDIVSTR _ECLKDIV; /* EEPROM Clock Divider Register; 0x00000110 */ +volatile ECNFGSTR _ECNFG; /* EEPROM Configuration Register; 0x00000113 */ +volatile EPROTSTR _EPROT; /* EEPROM Protection Register; 0x00000114 */ +volatile ESTATSTR _ESTAT; /* EEPROM Status Register; 0x00000115 */ +volatile ECMDSTR _ECMD; /* EEPROM Command Buffer and Register; 0x00000116 */ +volatile ATD1STAT0STR _ATD1STAT0; /* ATD 1 Status Register 0; 0x00000126 */ +volatile ATD1TEST1STR _ATD1TEST1; /* ATD1 Test Register; 0x00000129 */ +volatile ATD1STAT1STR _ATD1STAT1; /* ATD 1 Status Register 1; 0x0000012B */ +volatile ATD1DIENSTR _ATD1DIEN; /* ATD 1 Input Enable Register; 0x0000012D */ +volatile PORTAD1STR _PORTAD1; /* Port AD1 Register; 0x0000012F */ +volatile CAN0CTL0STR _CAN0CTL0; /* MSCAN 0 Control 0 Register; 0x00000140 */ +volatile CAN0CTL1STR _CAN0CTL1; /* MSCAN 0 Control 1 Register; 0x00000141 */ +volatile CAN0BTR0STR _CAN0BTR0; /* MSCAN 0 Bus Timing Register 0; 0x00000142 */ +volatile CAN0BTR1STR _CAN0BTR1; /* MSCAN 0 Bus Timing Register 1; 0x00000143 */ +volatile CAN0RFLGSTR _CAN0RFLG; /* MSCAN 0 Receiver Flag Register; 0x00000144 */ +volatile CAN0RIERSTR _CAN0RIER; /* MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 */ +volatile CAN0TFLGSTR _CAN0TFLG; /* MSCAN 0 Transmitter Flag Register; 0x00000146 */ +volatile CAN0TIERSTR _CAN0TIER; /* MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 */ +volatile CAN0TARQSTR _CAN0TARQ; /* MSCAN 0 Transmitter Message Abort Request; 0x00000148 */ +volatile CAN0TAAKSTR _CAN0TAAK; /* MSCAN 0 Transmitter Message Abort Control; 0x00000149 */ +volatile CAN0TBSELSTR _CAN0TBSEL; /* MSCAN 0 Transmit Buffer Selection; 0x0000014A */ +volatile CAN0IDACSTR _CAN0IDAC; /* MSCAN 0 Identifier Acceptance Control Register; 0x0000014B */ +volatile CAN0RXERRSTR _CAN0RXERR; /* MSCAN 0 Receive Error Counter Register; 0x0000014E */ +volatile CAN0TXERRSTR _CAN0TXERR; /* MSCAN 0 Transmit Error Counter Register; 0x0000014F */ +volatile CAN0IDAR0STR _CAN0IDAR0; /* MSCAN 0 Identifier Acceptance Register 0; 0x00000150 */ +volatile CAN0IDAR1STR _CAN0IDAR1; /* MSCAN 0 Identifier Acceptance Register 1; 0x00000151 */ +volatile CAN0IDAR2STR _CAN0IDAR2; /* MSCAN 0 Identifier Acceptance Register 2; 0x00000152 */ +volatile CAN0IDAR3STR _CAN0IDAR3; /* MSCAN 0 Identifier Acceptance Register 3; 0x00000153 */ +volatile CAN0IDMR0STR _CAN0IDMR0; /* MSCAN 0 Identifier Mask Register 0; 0x00000154 */ +volatile CAN0IDMR1STR _CAN0IDMR1; /* MSCAN 0 Identifier Mask Register 1; 0x00000155 */ +volatile CAN0IDMR2STR _CAN0IDMR2; /* MSCAN 0 Identifier Mask Register 2; 0x00000156 */ +volatile CAN0IDMR3STR _CAN0IDMR3; /* MSCAN 0 Identifier Mask Register 3; 0x00000157 */ +volatile CAN0IDAR4STR _CAN0IDAR4; /* MSCAN 0 Identifier Acceptance Register 4; 0x00000158 */ +volatile CAN0IDAR5STR _CAN0IDAR5; /* MSCAN 0 Identifier Acceptance Register 5; 0x00000159 */ +volatile CAN0IDAR6STR _CAN0IDAR6; /* MSCAN 0 Identifier Acceptance Register 6; 0x0000015A */ +volatile CAN0IDAR7STR _CAN0IDAR7; /* MSCAN 0 Identifier Acceptance Register 7; 0x0000015B */ +volatile CAN0IDMR4STR _CAN0IDMR4; /* MSCAN 0 Identifier Mask Register 4; 0x0000015C */ +volatile CAN0IDMR5STR _CAN0IDMR5; /* MSCAN 0 Identifier Mask Register 5; 0x0000015D */ +volatile CAN0IDMR6STR _CAN0IDMR6; /* MSCAN 0 Identifier Mask Register 6; 0x0000015E */ +volatile CAN0IDMR7STR _CAN0IDMR7; /* MSCAN 0 Identifier Mask Register 7; 0x0000015F */ +volatile CAN0RXIDR0STR _CAN0RXIDR0; /* MSCAN 0 Receive Identifier Register 0; 0x00000160 */ +volatile CAN0RXIDR1STR _CAN0RXIDR1; /* MSCAN 0 Receive Identifier Register 1; 0x00000161 */ +volatile CAN0RXIDR2STR _CAN0RXIDR2; /* MSCAN 0 Receive Identifier Register 2; 0x00000162 */ +volatile CAN0RXIDR3STR _CAN0RXIDR3; /* MSCAN 0 Receive Identifier Register 3; 0x00000163 */ +volatile CAN0RXDSR0STR _CAN0RXDSR0; /* MSCAN 0 Receive Data Segment Register 0; 0x00000164 */ +volatile CAN0RXDSR1STR _CAN0RXDSR1; /* MSCAN 0 Receive Data Segment Register 1; 0x00000165 */ +volatile CAN0RXDSR2STR _CAN0RXDSR2; /* MSCAN 0 Receive Data Segment Register 2; 0x00000166 */ +volatile CAN0RXDSR3STR _CAN0RXDSR3; /* MSCAN 0 Receive Data Segment Register 3; 0x00000167 */ +volatile CAN0RXDSR4STR _CAN0RXDSR4; /* MSCAN 0 Receive Data Segment Register 4; 0x00000168 */ +volatile CAN0RXDSR5STR _CAN0RXDSR5; /* MSCAN 0 Receive Data Segment Register 5; 0x00000169 */ +volatile CAN0RXDSR6STR _CAN0RXDSR6; /* MSCAN 0 Receive Data Segment Register 6; 0x0000016A */ +volatile CAN0RXDSR7STR _CAN0RXDSR7; /* MSCAN 0 Receive Data Segment Register 7; 0x0000016B */ +volatile CAN0RXDLRSTR _CAN0RXDLR; /* MSCAN 0 Receive Data Length Register; 0x0000016C */ +volatile CAN0TXIDR0STR _CAN0TXIDR0; /* MSCAN 0 Transmit Identifier Register 0; 0x00000170 */ +volatile CAN0TXIDR1STR _CAN0TXIDR1; /* MSCAN 0 Transmit Identifier Register 1; 0x00000171 */ +volatile CAN0TXIDR2STR _CAN0TXIDR2; /* MSCAN 0 Transmit Identifier Register 2; 0x00000172 */ +volatile CAN0TXIDR3STR _CAN0TXIDR3; /* MSCAN 0 Transmit Identifier Register 3; 0x00000173 */ +volatile CAN0TXDSR0STR _CAN0TXDSR0; /* MSCAN 0 Transmit Data Segment Register 0; 0x00000174 */ +volatile CAN0TXDSR1STR _CAN0TXDSR1; /* MSCAN 0 Transmit Data Segment Register 1; 0x00000175 */ +volatile CAN0TXDSR2STR _CAN0TXDSR2; /* MSCAN 0 Transmit Data Segment Register 2; 0x00000176 */ +volatile CAN0TXDSR3STR _CAN0TXDSR3; /* MSCAN 0 Transmit Data Segment Register 3; 0x00000177 */ +volatile CAN0TXDSR4STR _CAN0TXDSR4; /* MSCAN 0 Transmit Data Segment Register 4; 0x00000178 */ +volatile CAN0TXDSR5STR _CAN0TXDSR5; /* MSCAN 0 Transmit Data Segment Register 5; 0x00000179 */ +volatile CAN0TXDSR6STR _CAN0TXDSR6; /* MSCAN 0 Transmit Data Segment Register 6; 0x0000017A */ +volatile CAN0TXDSR7STR _CAN0TXDSR7; /* MSCAN 0 Transmit Data Segment Register 7; 0x0000017B */ +volatile CAN0TXDLRSTR _CAN0TXDLR; /* MSCAN 0 Transmit Data Length Register; 0x0000017C */ +volatile CAN0TXTBPRSTR _CAN0TXTBPR; /* MSCAN 0 Transmit Buffer Priority; 0x0000017D */ +volatile PTTSTR _PTT; /* Port T I/O Register; 0x00000240 */ +volatile PTITSTR _PTIT; /* Port T Input Register; 0x00000241 */ +volatile DDRTSTR _DDRT; /* Port T Data Direction Register; 0x00000242 */ +volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register; 0x00000243 */ +volatile PERTSTR _PERT; /* Port T Pull Device Enable Register; 0x00000244 */ +volatile PPSTSTR _PPST; /* Port T Polarity Select Register; 0x00000245 */ +volatile PTSSTR _PTS; /* Port S I/O Register; 0x00000248 */ +volatile PTISSTR _PTIS; /* Port S Input Register; 0x00000249 */ +volatile DDRSSTR _DDRS; /* Port S Data Direction Register; 0x0000024A */ +volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register; 0x0000024B */ +volatile PERSSTR _PERS; /* Port S Pull Device Enable Register; 0x0000024C */ +volatile PPSSSTR _PPSS; /* Port S Polarity Select Register; 0x0000024D */ +volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register; 0x0000024E */ +volatile PTMSTR _PTM; /* Port M I/O Register; 0x00000250 */ +volatile PTIMSTR _PTIM; /* Port M Input Register; 0x00000251 */ +volatile DDRMSTR _DDRM; /* Port M Data Direction Register; 0x00000252 */ +volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register; 0x00000253 */ +volatile PERMSTR _PERM; /* Port M Pull Device Enable Register; 0x00000254 */ +volatile PPSMSTR _PPSM; /* Port M Polarity Select Register; 0x00000255 */ +volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register; 0x00000256 */ +volatile MODRRSTR _MODRR; /* Module Routing Register; 0x00000257 */ +volatile PTPSTR _PTP; /* Port P I/O Register; 0x00000258 */ +volatile PTIPSTR _PTIP; /* Port P Input Register; 0x00000259 */ +volatile DDRPSTR _DDRP; /* Port P Data Direction Register; 0x0000025A */ +volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register; 0x0000025B */ +volatile PERPSTR _PERP; /* Port P Pull Device Enable Register; 0x0000025C */ +volatile PPSPSTR _PPSP; /* Port P Polarity Select Register; 0x0000025D */ +volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register; 0x0000025E */ +volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register; 0x0000025F */ +volatile PTHSTR _PTH; /* Port H I/O Register; 0x00000260 */ +volatile PTIHSTR _PTIH; /* Port H Input Register; 0x00000261 */ +volatile DDRHSTR _DDRH; /* Port H Data Direction Register; 0x00000262 */ +volatile RDRHSTR _RDRH; /* Port H Reduced Drive Register; 0x00000263 */ +volatile PERHSTR _PERH; /* Port H Pull Device Enable Register; 0x00000264 */ +volatile PPSHSTR _PPSH; /* Port H Polarity Select Register; 0x00000265 */ +volatile PIEHSTR _PIEH; /* Port H Interrupt Enable Register; 0x00000266 */ +volatile PIFHSTR _PIFH; /* Port H Interrupt Flag Register; 0x00000267 */ +volatile PTJSTR _PTJ; /* Port J I/O Register; 0x00000268 */ +volatile PTIJSTR _PTIJ; /* Port J Input Register; 0x00000269 */ +volatile DDRJSTR _DDRJ; /* Port J Data Direction Register; 0x0000026A */ +volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register; 0x0000026B */ +volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register; 0x0000026C */ +volatile PPSJSTR _PPSJ; /* Port J Polarity Select Register; 0x0000026D */ +volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register; 0x0000026E */ +volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register; 0x0000026F */ +volatile CAN4CTL0STR _CAN4CTL0; /* MSCAN4 Control 0 Register; 0x00000280 */ +volatile CAN4CTL1STR _CAN4CTL1; /* MSCAN4 Control 1 Register; 0x00000281 */ +volatile CAN4BTR0STR _CAN4BTR0; /* MSCAN4 Bus Timing Register 0; 0x00000282 */ +volatile CAN4BTR1STR _CAN4BTR1; /* MSCAN4 Bus Timing Register 1; 0x00000283 */ +volatile CAN4RFLGSTR _CAN4RFLG; /* MSCAN4 Receiver Flag Register; 0x00000284 */ +volatile CAN4RIERSTR _CAN4RIER; /* MSCAN4 Receiver Interrupt Enable Register; 0x00000285 */ +volatile CAN4TFLGSTR _CAN4TFLG; /* MSCAN4 Transmitter Flag Register; 0x00000286 */ +volatile CAN4TIERSTR _CAN4TIER; /* MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 */ +volatile CAN4TARQSTR _CAN4TARQ; /* MSCAN 4 Transmitter Message Abort Request; 0x00000288 */ +volatile CAN4TAAKSTR _CAN4TAAK; /* MSCAN4 Transmitter Message Abort Control; 0x00000289 */ +volatile CAN4TBSELSTR _CAN4TBSEL; /* MSCAN4 Transmit Buffer Selection; 0x0000028A */ +volatile CAN4IDACSTR _CAN4IDAC; /* MSCAN4 Identifier Acceptance Control Register; 0x0000028B */ +volatile CAN4RXERRSTR _CAN4RXERR; /* MSCAN4 Receive Error Counter Register; 0x0000028E */ +volatile CAN4TXERRSTR _CAN4TXERR; /* MSCAN4 Transmit Error Counter Register; 0x0000028F */ +volatile CAN4IDAR0STR _CAN4IDAR0; /* MSCAN4 Identifier Acceptance Register 0; 0x00000290 */ +volatile CAN4IDAR1STR _CAN4IDAR1; /* MSCAN4 Identifier Acceptance Register 1; 0x00000291 */ +volatile CAN4IDAR2STR _CAN4IDAR2; /* MSCAN4 Identifier Acceptance Register 2; 0x00000292 */ +volatile CAN4IDAR3STR _CAN4IDAR3; /* MSCAN4 Identifier Acceptance Register 3; 0x00000293 */ +volatile CAN4IDMR0STR _CAN4IDMR0; /* MSCAN4 Identifier Mask Register 0; 0x00000294 */ +volatile CAN4IDMR1STR _CAN4IDMR1; /* MSCAN4 Identifier Mask Register 1; 0x00000295 */ +volatile CAN4IDMR2STR _CAN4IDMR2; /* MSCAN4 Identifier Mask Register 2; 0x00000296 */ +volatile CAN4IDMR3STR _CAN4IDMR3; /* MSCAN4 Identifier Mask Register 3; 0x00000297 */ +volatile CAN4IDAR4STR _CAN4IDAR4; /* MSCAN4 Identifier Acceptance Register 4; 0x00000298 */ +volatile CAN4IDAR5STR _CAN4IDAR5; /* MSCAN4 Identifier Acceptance Register 5; 0x00000299 */ +volatile CAN4IDAR6STR _CAN4IDAR6; /* MSCAN4 Identifier Acceptance Register 6; 0x0000029A */ +volatile CAN4IDAR7STR _CAN4IDAR7; /* MSCAN4 Identifier Acceptance Register 7; 0x0000029B */ +volatile CAN4IDMR4STR _CAN4IDMR4; /* MSCAN4 Identifier Mask Register 4; 0x0000029C */ +volatile CAN4IDMR5STR _CAN4IDMR5; /* MSCAN4 Identifier Mask Register 5; 0x0000029D */ +volatile CAN4IDMR6STR _CAN4IDMR6; /* MSCAN4 Identifier Mask Register 6; 0x0000029E */ +volatile CAN4IDMR7STR _CAN4IDMR7; /* MSCAN4 Identifier Mask Register 7; 0x0000029F */ +volatile CAN4RXIDR0STR _CAN4RXIDR0; /* MSCAN4 Receive Identifier Register 0; 0x000002A0 */ +volatile CAN4RXIDR1STR _CAN4RXIDR1; /* MSCAN4 Receive Identifier Register 1; 0x000002A1 */ +volatile CAN4RXIDR2STR _CAN4RXIDR2; /* MSCAN4 Receive Identifier Register 2; 0x000002A2 */ +volatile CAN4RXIDR3STR _CAN4RXIDR3; /* MSCAN4 Receive Identifier Register 3; 0x000002A3 */ +volatile CAN4RXDSR0STR _CAN4RXDSR0; /* MSCAN4 Receive Data Segment Register 0; 0x000002A4 */ +volatile CAN4RXDSR1STR _CAN4RXDSR1; /* MSCAN4 Receive Data Segment Register 1; 0x000002A5 */ +volatile CAN4RXDSR2STR _CAN4RXDSR2; /* MSCAN4 Receive Data Segment Register 2; 0x000002A6 */ +volatile CAN4RXDSR3STR _CAN4RXDSR3; /* MSCAN4 Receive Data Segment Register 3; 0x000002A7 */ +volatile CAN4RXDSR4STR _CAN4RXDSR4; /* MSCAN4 Receive Data Segment Register 4; 0x000002A8 */ +volatile CAN4RXDSR5STR _CAN4RXDSR5; /* MSCAN4 Receive Data Segment Register 5; 0x000002A9 */ +volatile CAN4RXDSR6STR _CAN4RXDSR6; /* MSCAN4 Receive Data Segment Register 6; 0x000002AA */ +volatile CAN4RXDSR7STR _CAN4RXDSR7; /* MSCAN4 Receive Data Segment Register 7; 0x000002AB */ +volatile CAN4RXDLRSTR _CAN4RXDLR; /* MSCAN4 Receive Data Length Register; 0x000002AC */ +volatile CAN4TXIDR0STR _CAN4TXIDR0; /* MSCAN4 Transmit Identifier Register 0; 0x000002B0 */ +volatile CAN4TXIDR1STR _CAN4TXIDR1; /* MSCAN4 Transmit Identifier Register 1; 0x000002B1 */ +volatile CAN4TXIDR2STR _CAN4TXIDR2; /* MSCAN4 Transmit Identifier Register 2; 0x000002B2 */ +volatile CAN4TXIDR3STR _CAN4TXIDR3; /* MSCAN4 Transmit Identifier Register 3; 0x000002B3 */ +volatile CAN4TXDSR0STR _CAN4TXDSR0; /* MSCAN4 Transmit Data Segment Register 0; 0x000002B4 */ +volatile CAN4TXDSR1STR _CAN4TXDSR1; /* MSCAN4 Transmit Data Segment Register 1; 0x000002B5 */ +volatile CAN4TXDSR2STR _CAN4TXDSR2; /* MSCAN4 Transmit Data Segment Register 2; 0x000002B6 */ +volatile CAN4TXDSR3STR _CAN4TXDSR3; /* MSCAN4 Transmit Data Segment Register 3; 0x000002B7 */ +volatile CAN4TXDSR4STR _CAN4TXDSR4; /* MSCAN4 Transmit Data Segment Register 4; 0x000002B8 */ +volatile CAN4TXDSR5STR _CAN4TXDSR5; /* MSCAN4 Transmit Data Segment Register 5; 0x000002B9 */ +volatile CAN4TXDSR6STR _CAN4TXDSR6; /* MSCAN4 Transmit Data Segment Register 6; 0x000002BA */ +volatile CAN4TXDSR7STR _CAN4TXDSR7; /* MSCAN4 Transmit Data Segment Register 7; 0x000002BB */ +volatile CAN4TXDLRSTR _CAN4TXDLR; /* MSCAN4 Transmit Data Length Register; 0x000002BC */ +volatile CAN4TXTBPRSTR _CAN4TXTBPR; /* MSCAN4 Transmit Transmit Buffer Priority; 0x000002BD */ +/* NVFPROT3 - macro for reading non volatile register Non volatile Block 3 Flash Protection Register; 0x0000FF0A */ +/* NVFPROT2 - macro for reading non volatile register Non volatile Block 2 Flash Protection Register; 0x0000FF0B */ +/* NVFPROT1 - macro for reading non volatile register Non volatile Block 1 Flash Protection Register; 0x0000FF0C */ +/* NVFPROT0 - macro for reading non volatile register Non volatile Block 0 Flash Protection Register; 0x0000FF0D */ +/* NVFSEC - macro for reading non volatile register Non volatile Flash Security Register; 0x0000FF0F */ + + +/* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ +volatile PORTABSTR _PORTAB; /* Port AB Register; 0x00000000 */ +volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register; 0x00000002 */ +volatile PARTIDSTR _PARTID; /* Part ID Register; 0x0000001A */ +volatile TCNTSTR _TCNT; /* Timer Count Register; 0x00000044 */ +volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0; 0x00000050 */ +volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1; 0x00000052 */ +volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2; 0x00000054 */ +volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3; 0x00000056 */ +volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4; 0x00000058 */ +volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5; 0x0000005A */ +volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6; 0x0000005C */ +volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7; 0x0000005E */ +volatile PACN32STR _PACN32; /* Pulse Accumulators Count 32 Register; 0x00000062 */ +volatile PACN10STR _PACN10; /* Pulse Accumulators Count 10 Register; 0x00000064 */ +volatile PA32HSTR _PA32H; /* 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 */ +volatile PA10HSTR _PA10H; /* 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 */ +volatile MCCNTSTR _MCCNT; /* Modulus Down-Counter Count Register; 0x00000076 */ +volatile TC0HSTR _TC0H; /* Timer Input Capture Holding Registers 0; 0x00000078 */ +volatile TC1HSTR _TC1H; /* Timer Input Capture Holding Registers 1; 0x0000007A */ +volatile TC2HSTR _TC2H; /* Timer Input Capture Holding Registers 2; 0x0000007C */ +volatile TC3HSTR _TC3H; /* Timer Input Capture Holding Registers 3; 0x0000007E */ +volatile ATD0CTL23STR _ATD0CTL23; /* ATD 0 Control Register 23; 0x00000082 */ +volatile ATD0CTL45STR _ATD0CTL45; /* ATD 0 Control Register 45; 0x00000084 */ +volatile ATD0DR0STR _ATD0DR0; /* ATD 0 Conversion Result Register 0; 0x00000090 */ +volatile ATD0DR1STR _ATD0DR1; /* ATD 0 Conversion Result Register 1; 0x00000092 */ +volatile ATD0DR2STR _ATD0DR2; /* ATD 0 Conversion Result Register 2; 0x00000094 */ +volatile ATD0DR3STR _ATD0DR3; /* ATD 0 Conversion Result Register 3; 0x00000096 */ +volatile ATD0DR4STR _ATD0DR4; /* ATD 0 Conversion Result Register 4; 0x00000098 */ +volatile ATD0DR5STR _ATD0DR5; /* ATD 0 Conversion Result Register 5; 0x0000009A */ +volatile ATD0DR6STR _ATD0DR6; /* ATD 0 Conversion Result Register 6; 0x0000009C */ +volatile ATD0DR7STR _ATD0DR7; /* ATD 0 Conversion Result Register 7; 0x0000009E */ +volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register; 0x000000AC */ +volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register; 0x000000AE */ +volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register; 0x000000B0 */ +volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register; 0x000000B2 */ +volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register; 0x000000B4 */ +volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register; 0x000000B6 */ +volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register; 0x000000B8 */ +volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register; 0x000000BA */ +volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register; 0x000000BC */ +volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register; 0x000000BE */ +volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register; 0x000000C0 */ +volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register; 0x000000C2 */ +volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register; 0x000000C8 */ +volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register; 0x000000D0 */ +volatile ATD1CTL23STR _ATD1CTL23; /* ATD 1 Control Register 23; 0x00000122 */ +volatile ATD1CTL45STR _ATD1CTL45; /* ATD 1 Control Register 45; 0x00000124 */ +volatile ATD1DR0STR _ATD1DR0; /* ATD 1 Conversion Result Register 0; 0x00000130 */ +volatile ATD1DR1STR _ATD1DR1; /* ATD 1 Conversion Result Register 1; 0x00000132 */ +volatile ATD1DR2STR _ATD1DR2; /* ATD 1 Conversion Result Register 2; 0x00000134 */ +volatile ATD1DR3STR _ATD1DR3; /* ATD 1 Conversion Result Register 3; 0x00000136 */ +volatile ATD1DR4STR _ATD1DR4; /* ATD 1 Conversion Result Register 4; 0x00000138 */ +volatile ATD1DR5STR _ATD1DR5; /* ATD 1 Conversion Result Register 5; 0x0000013A */ +volatile ATD1DR6STR _ATD1DR6; /* ATD 1 Conversion Result Register 6; 0x0000013C */ +volatile ATD1DR7STR _ATD1DR7; /* ATD 1 Conversion Result Register 7; 0x0000013E */ +volatile CAN0RXTSRSTR _CAN0RXTSR; /* MSCAN 0 Receive Time Stamp Register; 0x0000016E */ +volatile CAN0TXTSRSTR _CAN0TXTSR; /* MSCAN 0 Transmit Time Stamp Register; 0x0000017E */ +volatile CAN4RXTSRSTR _CAN4RXTSR; /* MSCAN 4 Receive Time Stamp Register; 0x000002AE */ +volatile CAN4TXTSRSTR _CAN4TXTSR; /* MSCAN 4 Transmit Time Stamp Register; 0x000002BE */ +/* BAKEY0 - macro for reading non volatile register Backdoor Access Key 0; 0x0000FF00 */ +/* BAKEY1 - macro for reading non volatile register Backdoor Access Key 1; 0x0000FF02 */ +/* BAKEY2 - macro for reading non volatile register Backdoor Access Key 2; 0x0000FF04 */ +/* BAKEY3 - macro for reading non volatile register Backdoor Access Key 3; 0x0000FF06 */ + +/*lint -restore */ + +/* EOF */ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/mc9s12dg256.h b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/mc9s12dg256.h new file mode 100644 index 00000000..d62524d9 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/lib/mc9s12dg256.h @@ -0,0 +1,16197 @@ +/* Based on CPU DB MC9S12DG256_112, version 2.87.347 (RegistersPrg V2.32) */ +/* +** ################################################################### +** Filename : mc9s12dg256.h +** Processor : MC9S12DG256CPV +** FileFormat: V2.32 +** DataSheet : 9S12DT256DGV3/D V03.04 +** Compiler : CodeWarrior compiler +** Date/Time : 8.6.2010, 9:00 +** Abstract : +** This header implements the mapping of I/O devices. +** +** Copyright : 1997 - 2010 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http : www.freescale.com +** mail : support@freescale.com +** +** CPU Registers Revisions: +** - 24.05.2006, V2.87.285: +** - Removed bits MCCNTlo_BIT0..MCCNTlo_BIT7 and MCCNThi_BIT8.. MCCNThi_BIT15. REASON: Bug-fix (#3166 in Issue Manager) +** +** File-Format-Revisions: +** - 14.11.2005, V2.00 : +** - Deprecated symbols added for backward compatibility (section at the end of this file) +** - 15.11.2005, V2.01 : +** - Fixed invalid instruction in macro __RESET_WATCHDOG for HCS12 family. +** - 17.12.2005, V2.02 : +** - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778 +** - 16.01.2006, V2.03 : +** - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920. +** - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const") +** - 08.03.2006, V2.04 : +** - Support for bit(s) names duplicated with any register name in .h header files +** - 24.03.2006, V2.05 : +** - Fixed macro __RESET_WATCHDOG for HCS12 family - address and correct write order. +** - 26.04.2006, V2.06 : +** - Changes have not affected this file (because they are related to another family) +** - 27.04.2006, V2.07 : +** - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA). +** - 07.06.2006, V2.08 : +** - Changes have not affected this file (because they are related to another family) +** - 03.07.2006, V2.09 : +** - Changes have not affected this file (because they are related to another family) +** - 27.10.2006, V2.10 : +** - __RESET_WATCHDOG improved formating and re-definition +** - 23.11.2006, V2.11 : +** - Changes have not affected this file (because they are related to another family) +** - 22.01.2007, V2.12 : +** - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #4086. +** - 01.03.2007, V2.13 : +** - Flash commands constants values converted to HEX format +** - 02.03.2007, V2.14 : +** - Interrupt vector numbers added into .H, see VectorNumber_* +** - 26.03.2007, V2.15 : +** - Changes have not affected this file (because they are related to another family) +** - 10.05.2007, V2.16 : +** - Changes have not affected this file (because they are related to another family) +** - 05.06.2007, V2.17 : +** - Changes have not affected this file (because they are related to another family) +** - 19.07.2007, V2.18 : +** - Improved number of blanked lines inside register structures +** - 06.08.2007, V2.19 : +** - CPUDB revisions generated ahead of the file-format revisions. +** - 11.09.2007, V2.20 : +** - Added comment about initialization of unbonded pins. +** - 02.01.2008, V2.21 : +** - Changes have not affected this file (because they are related to another family) +** - 13.02.2008, V2.22 : +** - Changes have not affected this file (because they are related to another family) +** - 20.02.2008, V2.23 : +** - Termination of pragma V30toV31Compatible added, #5708 +** - 03.07.2008, V2.24 : +** - Added support for bits with name starting with number (like "1HZ") +** - 28.11.2008, V2.25 : +** - StandBy RAM array declaration for ANSI-C added +** - 1.12.2008, V2.26 : +** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. +** - 17.3.2009, V2.27 : +** - Merged bit-group is not generated, if the name matches with another bit name in the register +** - 6.4.2009, V2.28 : +** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB +** - 3.8.2009, V2.29 : +** - If there is just one bits group matching register name, single bits are not generated +** - 10.9.2009, V2.30 : +** - Fixed generation of registers arrays. +** - 15.10.2009, V2.31 : +** - Changes have not affected this file (because they are related to another family) +** - 18.05.2010, V2.32 : +** - MISRA compliance: U/UL suffixes added to all numbers (_MASK,_BITNUM and addresses) +** +** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific +** derivative device. To avoid extra current drain from floating input pins, the user’s reset +** initialization routine in the application program must either enable on-chip pull-up devices +** or change the direction of unconnected pins to outputs so the pins do not float. +** ################################################################### +*/ + +#ifndef _MC9S12DG256_H +#define _MC9S12DG256_H + +/*lint -save -e950 -esym(960,18.4) -e46 -esym(961,19.7) Disable MISRA rule (1.1,18.4,6.4,19.7) checking. */ +/* Types definition */ +typedef unsigned char byte; +typedef unsigned int word; +typedef unsigned long dword; +typedef unsigned long dlong[2]; + +#define REG_BASE 0x0000 /* Base address for the I/O register block */ + + +#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ +#pragma OPTION ADD V30toV31Compatible "-BfaGapLimitBits4294967295" /*this guarantee correct bitfield positions*/ + +/**************** interrupt vector numbers ****************/ +#define VectorNumber_VReserved63 63U +#define VectorNumber_VReserved62 62U +#define VectorNumber_VReserved61 61U +#define VectorNumber_VReserved60 60U +#define VectorNumber_VReserved59 59U +#define VectorNumber_VReserved58 58U +#define VectorNumber_Vpwmesdn 57U +#define VectorNumber_Vportp 56U +#define VectorNumber_Vcan4tx 55U +#define VectorNumber_Vcan4rx 54U +#define VectorNumber_Vcan4err 53U +#define VectorNumber_Vcan4wkup 52U +#define VectorNumber_VReserved51 51U +#define VectorNumber_VReserved50 50U +#define VectorNumber_VReserved49 49U +#define VectorNumber_VReserved48 48U +#define VectorNumber_VReserved47 47U +#define VectorNumber_VReserved46 46U +#define VectorNumber_VReserved45 45U +#define VectorNumber_VReserved44 44U +#define VectorNumber_VReserved43 43U +#define VectorNumber_VReserved42 42U +#define VectorNumber_VReserved41 41U +#define VectorNumber_VReserved40 40U +#define VectorNumber_Vcan0tx 39U +#define VectorNumber_Vcan0rx 38U +#define VectorNumber_Vcan0err 37U +#define VectorNumber_Vcan0wkup 36U +#define VectorNumber_Vflash 35U +#define VectorNumber_Veeprom 34U +#define VectorNumber_Vspi2 33U +#define VectorNumber_Vspi1 32U +#define VectorNumber_Viic 31U +#define VectorNumber_VReserved30 30U +#define VectorNumber_Vcrgscm 29U +#define VectorNumber_Vcrgplllck 28U +#define VectorNumber_Vtimpabovf 27U +#define VectorNumber_Vtimmdcu 26U +#define VectorNumber_Vporth 25U +#define VectorNumber_Vportj 24U +#define VectorNumber_Vatd1 23U +#define VectorNumber_Vatd0 22U +#define VectorNumber_Vsci1 21U +#define VectorNumber_Vsci0 20U +#define VectorNumber_Vspi0 19U +#define VectorNumber_Vtimpaie 18U +#define VectorNumber_Vtimpaaovf 17U +#define VectorNumber_Vtimovf 16U +#define VectorNumber_Vtimch7 15U +#define VectorNumber_Vtimch6 14U +#define VectorNumber_Vtimch5 13U +#define VectorNumber_Vtimch4 12U +#define VectorNumber_Vtimch3 11U +#define VectorNumber_Vtimch2 10U +#define VectorNumber_Vtimch1 9U +#define VectorNumber_Vtimch0 8U +#define VectorNumber_Vrti 7U +#define VectorNumber_Virq 6U +#define VectorNumber_Vxirq 5U +#define VectorNumber_Vswi 4U +#define VectorNumber_Vtrap 3U +#define VectorNumber_Vcop 2U +#define VectorNumber_Vclkmon 1U +#define VectorNumber_Vreset 0U + +/**************** interrupt vector table ****************/ +#define VReserved63 0xFF80U +#define VReserved62 0xFF82U +#define VReserved61 0xFF84U +#define VReserved60 0xFF86U +#define VReserved59 0xFF88U +#define VReserved58 0xFF8AU +#define Vpwmesdn 0xFF8CU +#define Vportp 0xFF8EU +#define Vcan4tx 0xFF90U +#define Vcan4rx 0xFF92U +#define Vcan4err 0xFF94U +#define Vcan4wkup 0xFF96U +#define VReserved51 0xFF98U +#define VReserved50 0xFF9AU +#define VReserved49 0xFF9CU +#define VReserved48 0xFF9EU +#define VReserved47 0xFFA0U +#define VReserved46 0xFFA2U +#define VReserved45 0xFFA4U +#define VReserved44 0xFFA6U +#define VReserved43 0xFFA8U +#define VReserved42 0xFFAAU +#define VReserved41 0xFFACU +#define VReserved40 0xFFAEU +#define Vcan0tx 0xFFB0U +#define Vcan0rx 0xFFB2U +#define Vcan0err 0xFFB4U +#define Vcan0wkup 0xFFB6U +#define Vflash 0xFFB8U +#define Veeprom 0xFFBAU +#define Vspi2 0xFFBCU +#define Vspi1 0xFFBEU +#define Viic 0xFFC0U +#define VReserved30 0xFFC2U +#define Vcrgscm 0xFFC4U +#define Vcrgplllck 0xFFC6U +#define Vtimpabovf 0xFFC8U +#define Vtimmdcu 0xFFCAU +#define Vporth 0xFFCCU +#define Vportj 0xFFCEU +#define Vatd1 0xFFD0U +#define Vatd0 0xFFD2U +#define Vsci1 0xFFD4U +#define Vsci0 0xFFD6U +#define Vspi0 0xFFD8U +#define Vtimpaie 0xFFDAU +#define Vtimpaaovf 0xFFDCU +#define Vtimovf 0xFFDEU +#define Vtimch7 0xFFE0U +#define Vtimch6 0xFFE2U +#define Vtimch5 0xFFE4U +#define Vtimch4 0xFFE6U +#define Vtimch3 0xFFE8U +#define Vtimch2 0xFFEAU +#define Vtimch1 0xFFECU +#define Vtimch0 0xFFEEU +#define Vrti 0xFFF0U +#define Virq 0xFFF2U +#define Vxirq 0xFFF4U +#define Vswi 0xFFF6U +#define Vtrap 0xFFF8U +#define Vcop 0xFFFAU +#define Vclkmon 0xFFFCU +#define Vreset 0xFFFEU + +/**************** registers I/O map ****************/ + +/*** PORTAB - Port AB Register; 0x00000000 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PORTA - Port A Register; 0x00000000 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Port A Bit 0 */ + byte BIT1 :1; /* Port A Bit 1 */ + byte BIT2 :1; /* Port A Bit 2 */ + byte BIT3 :1; /* Port A Bit 3 */ + byte BIT4 :1; /* Port A Bit 4 */ + byte BIT5 :1; /* Port A Bit 5 */ + byte BIT6 :1; /* Port A Bit 6 */ + byte BIT7 :1; /* Port A Bit 7 */ + } Bits; + } PORTASTR; + #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte + #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0 + #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1 + #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2 + #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3 + #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4 + #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5 + #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6 + #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7 + + #define PORTA_BIT0_MASK 1U + #define PORTA_BIT1_MASK 2U + #define PORTA_BIT2_MASK 4U + #define PORTA_BIT3_MASK 8U + #define PORTA_BIT4_MASK 16U + #define PORTA_BIT5_MASK 32U + #define PORTA_BIT6_MASK 64U + #define PORTA_BIT7_MASK 128U + + + /*** PORTB - Port B Register; 0x00000001 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Port B Bit 0 */ + byte BIT1 :1; /* Port B Bit 1 */ + byte BIT2 :1; /* Port B Bit 2 */ + byte BIT3 :1; /* Port B Bit 3 */ + byte BIT4 :1; /* Port B Bit 4 */ + byte BIT5 :1; /* Port B Bit 5 */ + byte BIT6 :1; /* Port B Bit 6 */ + byte BIT7 :1; /* Port B Bit 7 */ + } Bits; + } PORTBSTR; + #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte + #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0 + #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1 + #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2 + #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3 + #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4 + #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5 + #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6 + #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7 + + #define PORTB_BIT0_MASK 1U + #define PORTB_BIT1_MASK 2U + #define PORTB_BIT2_MASK 4U + #define PORTB_BIT3_MASK 8U + #define PORTB_BIT4_MASK 16U + #define PORTB_BIT5_MASK 32U + #define PORTB_BIT6_MASK 64U + #define PORTB_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Port AB Bit 0 */ + word BIT1 :1; /* Port AB Bit 1 */ + word BIT2 :1; /* Port AB Bit 2 */ + word BIT3 :1; /* Port AB Bit 3 */ + word BIT4 :1; /* Port AB Bit 4 */ + word BIT5 :1; /* Port AB Bit 5 */ + word BIT6 :1; /* Port AB Bit 6 */ + word BIT7 :1; /* Port AB Bit 7 */ + word BIT8 :1; /* Port AB Bit 8 */ + word BIT9 :1; /* Port AB Bit 9 */ + word BIT10 :1; /* Port AB Bit 10 */ + word BIT11 :1; /* Port AB Bit 11 */ + word BIT12 :1; /* Port AB Bit 12 */ + word BIT13 :1; /* Port AB Bit 13 */ + word BIT14 :1; /* Port AB Bit 14 */ + word BIT15 :1; /* Port AB Bit 15 */ + } Bits; +} PORTABSTR; +extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000UL); +#define PORTAB _PORTAB.Word +#define PORTAB_BIT0 _PORTAB.Bits.BIT0 +#define PORTAB_BIT1 _PORTAB.Bits.BIT1 +#define PORTAB_BIT2 _PORTAB.Bits.BIT2 +#define PORTAB_BIT3 _PORTAB.Bits.BIT3 +#define PORTAB_BIT4 _PORTAB.Bits.BIT4 +#define PORTAB_BIT5 _PORTAB.Bits.BIT5 +#define PORTAB_BIT6 _PORTAB.Bits.BIT6 +#define PORTAB_BIT7 _PORTAB.Bits.BIT7 +#define PORTAB_BIT8 _PORTAB.Bits.BIT8 +#define PORTAB_BIT9 _PORTAB.Bits.BIT9 +#define PORTAB_BIT10 _PORTAB.Bits.BIT10 +#define PORTAB_BIT11 _PORTAB.Bits.BIT11 +#define PORTAB_BIT12 _PORTAB.Bits.BIT12 +#define PORTAB_BIT13 _PORTAB.Bits.BIT13 +#define PORTAB_BIT14 _PORTAB.Bits.BIT14 +#define PORTAB_BIT15 _PORTAB.Bits.BIT15 + +#define PORTAB_BIT0_MASK 1U +#define PORTAB_BIT1_MASK 2U +#define PORTAB_BIT2_MASK 4U +#define PORTAB_BIT3_MASK 8U +#define PORTAB_BIT4_MASK 16U +#define PORTAB_BIT5_MASK 32U +#define PORTAB_BIT6_MASK 64U +#define PORTAB_BIT7_MASK 128U +#define PORTAB_BIT8_MASK 256U +#define PORTAB_BIT9_MASK 512U +#define PORTAB_BIT10_MASK 1024U +#define PORTAB_BIT11_MASK 2048U +#define PORTAB_BIT12_MASK 4096U +#define PORTAB_BIT13_MASK 8192U +#define PORTAB_BIT14_MASK 16384U +#define PORTAB_BIT15_MASK 32768U + + +/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** DDRA - Port A Data Direction Register; 0x00000002 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port A Bit 0 */ + byte BIT1 :1; /* Data Direction Port A Bit 1 */ + byte BIT2 :1; /* Data Direction Port A Bit 2 */ + byte BIT3 :1; /* Data Direction Port A Bit 3 */ + byte BIT4 :1; /* Data Direction Port A Bit 4 */ + byte BIT5 :1; /* Data Direction Port A Bit 5 */ + byte BIT6 :1; /* Data Direction Port A Bit 6 */ + byte BIT7 :1; /* Data Direction Port A Bit 7 */ + } Bits; + } DDRASTR; + #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte + #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0 + #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1 + #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2 + #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3 + #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4 + #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5 + #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6 + #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7 + + #define DDRA_BIT0_MASK 1U + #define DDRA_BIT1_MASK 2U + #define DDRA_BIT2_MASK 4U + #define DDRA_BIT3_MASK 8U + #define DDRA_BIT4_MASK 16U + #define DDRA_BIT5_MASK 32U + #define DDRA_BIT6_MASK 64U + #define DDRA_BIT7_MASK 128U + + + /*** DDRB - Port B Data Direction Register; 0x00000003 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port B Bit 0 */ + byte BIT1 :1; /* Data Direction Port B Bit 1 */ + byte BIT2 :1; /* Data Direction Port B Bit 2 */ + byte BIT3 :1; /* Data Direction Port B Bit 3 */ + byte BIT4 :1; /* Data Direction Port B Bit 4 */ + byte BIT5 :1; /* Data Direction Port B Bit 5 */ + byte BIT6 :1; /* Data Direction Port B Bit 6 */ + byte BIT7 :1; /* Data Direction Port B Bit 7 */ + } Bits; + } DDRBSTR; + #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte + #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0 + #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1 + #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2 + #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3 + #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4 + #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5 + #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6 + #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7 + + #define DDRB_BIT0_MASK 1U + #define DDRB_BIT1_MASK 2U + #define DDRB_BIT2_MASK 4U + #define DDRB_BIT3_MASK 8U + #define DDRB_BIT4_MASK 16U + #define DDRB_BIT5_MASK 32U + #define DDRB_BIT6_MASK 64U + #define DDRB_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Data Direction Port AB Bit 0 */ + word BIT1 :1; /* Data Direction Port AB Bit 1 */ + word BIT2 :1; /* Data Direction Port AB Bit 2 */ + word BIT3 :1; /* Data Direction Port AB Bit 3 */ + word BIT4 :1; /* Data Direction Port AB Bit 4 */ + word BIT5 :1; /* Data Direction Port AB Bit 5 */ + word BIT6 :1; /* Data Direction Port AB Bit 6 */ + word BIT7 :1; /* Data Direction Port AB Bit 7 */ + word BIT8 :1; /* Data Direction Port AB Bit 8 */ + word BIT9 :1; /* Data Direction Port AB Bit 9 */ + word BIT10 :1; /* Data Direction Port AB Bit 10 */ + word BIT11 :1; /* Data Direction Port AB Bit 11 */ + word BIT12 :1; /* Data Direction Port AB Bit 12 */ + word BIT13 :1; /* Data Direction Port AB Bit 13 */ + word BIT14 :1; /* Data Direction Port AB Bit 14 */ + word BIT15 :1; /* Data Direction Port AB Bit 15 */ + } Bits; +} DDRABSTR; +extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002UL); +#define DDRAB _DDRAB.Word +#define DDRAB_BIT0 _DDRAB.Bits.BIT0 +#define DDRAB_BIT1 _DDRAB.Bits.BIT1 +#define DDRAB_BIT2 _DDRAB.Bits.BIT2 +#define DDRAB_BIT3 _DDRAB.Bits.BIT3 +#define DDRAB_BIT4 _DDRAB.Bits.BIT4 +#define DDRAB_BIT5 _DDRAB.Bits.BIT5 +#define DDRAB_BIT6 _DDRAB.Bits.BIT6 +#define DDRAB_BIT7 _DDRAB.Bits.BIT7 +#define DDRAB_BIT8 _DDRAB.Bits.BIT8 +#define DDRAB_BIT9 _DDRAB.Bits.BIT9 +#define DDRAB_BIT10 _DDRAB.Bits.BIT10 +#define DDRAB_BIT11 _DDRAB.Bits.BIT11 +#define DDRAB_BIT12 _DDRAB.Bits.BIT12 +#define DDRAB_BIT13 _DDRAB.Bits.BIT13 +#define DDRAB_BIT14 _DDRAB.Bits.BIT14 +#define DDRAB_BIT15 _DDRAB.Bits.BIT15 + +#define DDRAB_BIT0_MASK 1U +#define DDRAB_BIT1_MASK 2U +#define DDRAB_BIT2_MASK 4U +#define DDRAB_BIT3_MASK 8U +#define DDRAB_BIT4_MASK 16U +#define DDRAB_BIT5_MASK 32U +#define DDRAB_BIT6_MASK 64U +#define DDRAB_BIT7_MASK 128U +#define DDRAB_BIT8_MASK 256U +#define DDRAB_BIT9_MASK 512U +#define DDRAB_BIT10_MASK 1024U +#define DDRAB_BIT11_MASK 2048U +#define DDRAB_BIT12_MASK 4096U +#define DDRAB_BIT13_MASK 8192U +#define DDRAB_BIT14_MASK 16384U +#define DDRAB_BIT15_MASK 32768U + + +/*** PORTE - Port E Register; 0x00000008 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port E Bit 0 */ + byte BIT1 :1; /* Port E Bit 1 */ + byte BIT2 :1; /* Port E Bit 2 */ + byte BIT3 :1; /* Port E Bit 3 */ + byte BIT4 :1; /* Port E Bit 4 */ + byte BIT5 :1; /* Port E Bit 5 */ + byte BIT6 :1; /* Port E Bit 6 */ + byte BIT7 :1; /* Port E Bit 7 */ + } Bits; +} PORTESTR; +extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008UL); +#define PORTE _PORTE.Byte +#define PORTE_BIT0 _PORTE.Bits.BIT0 +#define PORTE_BIT1 _PORTE.Bits.BIT1 +#define PORTE_BIT2 _PORTE.Bits.BIT2 +#define PORTE_BIT3 _PORTE.Bits.BIT3 +#define PORTE_BIT4 _PORTE.Bits.BIT4 +#define PORTE_BIT5 _PORTE.Bits.BIT5 +#define PORTE_BIT6 _PORTE.Bits.BIT6 +#define PORTE_BIT7 _PORTE.Bits.BIT7 + +#define PORTE_BIT0_MASK 1U +#define PORTE_BIT1_MASK 2U +#define PORTE_BIT2_MASK 4U +#define PORTE_BIT3_MASK 8U +#define PORTE_BIT4_MASK 16U +#define PORTE_BIT5_MASK 32U +#define PORTE_BIT6_MASK 64U +#define PORTE_BIT7_MASK 128U + + +/*** DDRE - Port E Data Direction Register; 0x00000009 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BIT2 :1; /* Data Direction Port E Bit 2 */ + byte BIT3 :1; /* Data Direction Port E Bit 3 */ + byte BIT4 :1; /* Data Direction Port E Bit 4 */ + byte BIT5 :1; /* Data Direction Port E Bit 5 */ + byte BIT6 :1; /* Data Direction Port E Bit 6 */ + byte BIT7 :1; /* Data Direction Port E Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte grpBIT_2 :6; + } MergedBits; +} DDRESTR; +extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009UL); +#define DDRE _DDRE.Byte +#define DDRE_BIT2 _DDRE.Bits.BIT2 +#define DDRE_BIT3 _DDRE.Bits.BIT3 +#define DDRE_BIT4 _DDRE.Bits.BIT4 +#define DDRE_BIT5 _DDRE.Bits.BIT5 +#define DDRE_BIT6 _DDRE.Bits.BIT6 +#define DDRE_BIT7 _DDRE.Bits.BIT7 +#define DDRE_BIT_2 _DDRE.MergedBits.grpBIT_2 +#define DDRE_BIT DDRE_BIT_2 + +#define DDRE_BIT2_MASK 4U +#define DDRE_BIT3_MASK 8U +#define DDRE_BIT4_MASK 16U +#define DDRE_BIT5_MASK 32U +#define DDRE_BIT6_MASK 64U +#define DDRE_BIT7_MASK 128U +#define DDRE_BIT_2_MASK 252U +#define DDRE_BIT_2_BITNUM 2U + + +/*** PEAR - Port E Assignment Register; 0x0000000A ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte RDWE :1; /* Read / Write Enable */ + byte LSTRE :1; /* Low Strobe (LSTRB) Enable */ + byte NECLK :1; /* No External E Clock */ + byte PIPOE :1; /* Pipe Status Signal Output Enable */ + byte :1; + byte NOACCE :1; /* CPU No Access Output Enable */ + } Bits; +} PEARSTR; +extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000AUL); +#define PEAR _PEAR.Byte +#define PEAR_RDWE _PEAR.Bits.RDWE +#define PEAR_LSTRE _PEAR.Bits.LSTRE +#define PEAR_NECLK _PEAR.Bits.NECLK +#define PEAR_PIPOE _PEAR.Bits.PIPOE +#define PEAR_NOACCE _PEAR.Bits.NOACCE + +#define PEAR_RDWE_MASK 4U +#define PEAR_LSTRE_MASK 8U +#define PEAR_NECLK_MASK 16U +#define PEAR_PIPOE_MASK 32U +#define PEAR_NOACCE_MASK 128U + + +/*** MODE - Mode Register; 0x0000000B ***/ +typedef union { + byte Byte; + struct { + byte EME :1; /* Emulate Port E */ + byte EMK :1; /* Emulate Port K */ + byte :1; + byte IVIS :1; /* Internal Visibility */ + byte :1; + byte MODA :1; /* Mode Select Bit A */ + byte MODB :1; /* Mode Select Bit B */ + byte MODC :1; /* Mode Select Bit C */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpMODx :3; + } MergedBits; +} MODESTR; +extern volatile MODESTR _MODE @(REG_BASE + 0x0000000BUL); +#define MODE _MODE.Byte +#define MODE_EME _MODE.Bits.EME +#define MODE_EMK _MODE.Bits.EMK +#define MODE_IVIS _MODE.Bits.IVIS +#define MODE_MODA _MODE.Bits.MODA +#define MODE_MODB _MODE.Bits.MODB +#define MODE_MODC _MODE.Bits.MODC +#define MODE_MODx _MODE.MergedBits.grpMODx + +#define MODE_EME_MASK 1U +#define MODE_EMK_MASK 2U +#define MODE_IVIS_MASK 8U +#define MODE_MODA_MASK 32U +#define MODE_MODB_MASK 64U +#define MODE_MODC_MASK 128U +#define MODE_MODx_MASK 224U +#define MODE_MODx_BITNUM 5U + + +/*** PUCR - Pull-Up Control Register; 0x0000000C ***/ +typedef union { + byte Byte; + struct { + byte PUPAE :1; /* Pull-Up Port A Enable */ + byte PUPBE :1; /* Pull-Up Port B Enable */ + byte :1; + byte :1; + byte PUPEE :1; /* Pull-Up Port E Enable */ + byte :1; + byte :1; + byte PUPKE :1; /* Pull-Up Port K Enable */ + } Bits; +} PUCRSTR; +extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000CUL); +#define PUCR _PUCR.Byte +#define PUCR_PUPAE _PUCR.Bits.PUPAE +#define PUCR_PUPBE _PUCR.Bits.PUPBE +#define PUCR_PUPEE _PUCR.Bits.PUPEE +#define PUCR_PUPKE _PUCR.Bits.PUPKE + +#define PUCR_PUPAE_MASK 1U +#define PUCR_PUPBE_MASK 2U +#define PUCR_PUPEE_MASK 16U +#define PUCR_PUPKE_MASK 128U + + +/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/ +typedef union { + byte Byte; + struct { + byte RDPA :1; /* Reduced Drive of Port A */ + byte RDPB :1; /* Reduced Drive of Port B */ + byte :1; + byte :1; + byte RDPE :1; /* Reduced Drive of Port E */ + byte :1; + byte :1; + byte RDPK :1; /* Reduced Drive of Port K */ + } Bits; + struct { + byte grpRDPx :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} RDRIVSTR; +extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000DUL); +#define RDRIV _RDRIV.Byte +#define RDRIV_RDPA _RDRIV.Bits.RDPA +#define RDRIV_RDPB _RDRIV.Bits.RDPB +#define RDRIV_RDPE _RDRIV.Bits.RDPE +#define RDRIV_RDPK _RDRIV.Bits.RDPK +#define RDRIV_RDPx _RDRIV.MergedBits.grpRDPx + +#define RDRIV_RDPA_MASK 1U +#define RDRIV_RDPB_MASK 2U +#define RDRIV_RDPE_MASK 16U +#define RDRIV_RDPK_MASK 128U +#define RDRIV_RDPx_MASK 3U +#define RDRIV_RDPx_BITNUM 0U + + +/*** EBICTL - External Bus Interface Control; 0x0000000E ***/ +typedef union { + byte Byte; + struct { + byte ESTR :1; /* E Stretches */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} EBICTLSTR; +extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000EUL); +#define EBICTL _EBICTL.Byte +#define EBICTL_ESTR _EBICTL.Bits.ESTR + +#define EBICTL_ESTR_MASK 1U + + +/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/ +typedef union { + byte Byte; + struct { + byte RAMHAL :1; /* Internal RAM map alignment */ + byte :1; + byte :1; + byte RAM11 :1; /* Internal RAM map position Bit 11 */ + byte RAM12 :1; /* Internal RAM map position Bit 12 */ + byte RAM13 :1; /* Internal RAM map position Bit 13 */ + byte RAM14 :1; /* Internal RAM map position Bit 14 */ + byte RAM15 :1; /* Internal RAM map position Bit 15 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpRAM_11 :5; + } MergedBits; +} INITRMSTR; +extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010UL); +#define INITRM _INITRM.Byte +#define INITRM_RAMHAL _INITRM.Bits.RAMHAL +#define INITRM_RAM11 _INITRM.Bits.RAM11 +#define INITRM_RAM12 _INITRM.Bits.RAM12 +#define INITRM_RAM13 _INITRM.Bits.RAM13 +#define INITRM_RAM14 _INITRM.Bits.RAM14 +#define INITRM_RAM15 _INITRM.Bits.RAM15 +#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11 +#define INITRM_RAM INITRM_RAM_11 + +#define INITRM_RAMHAL_MASK 1U +#define INITRM_RAM11_MASK 8U +#define INITRM_RAM12_MASK 16U +#define INITRM_RAM13_MASK 32U +#define INITRM_RAM14_MASK 64U +#define INITRM_RAM15_MASK 128U +#define INITRM_RAM_11_MASK 248U +#define INITRM_RAM_11_BITNUM 3U + + +/*** INITRG - Initialization of Internal Registers Position Register; 0x00000011 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte REG11 :1; /* Internal Registers Map Position Bit 11 */ + byte REG12 :1; /* Internal Registers Map Position Bit 12 */ + byte REG13 :1; /* Internal Registers Map Position Bit 13 */ + byte REG14 :1; /* Internal Registers Map Position Bit 14 */ + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpREG_11 :4; + byte :1; + } MergedBits; +} INITRGSTR; +extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011UL); +#define INITRG _INITRG.Byte +#define INITRG_REG11 _INITRG.Bits.REG11 +#define INITRG_REG12 _INITRG.Bits.REG12 +#define INITRG_REG13 _INITRG.Bits.REG13 +#define INITRG_REG14 _INITRG.Bits.REG14 +#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11 +#define INITRG_REG INITRG_REG_11 + +#define INITRG_REG11_MASK 8U +#define INITRG_REG12_MASK 16U +#define INITRG_REG13_MASK 32U +#define INITRG_REG14_MASK 64U +#define INITRG_REG_11_MASK 120U +#define INITRG_REG_11_BITNUM 3U + + +/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/ +typedef union { + byte Byte; + struct { + byte EEON :1; /* Internal EEPROM On */ + byte :1; + byte :1; + byte :1; + byte EE12 :1; /* Internal EEPROM map position Bit 12 */ + byte EE13 :1; /* Internal EEPROM map position Bit 13 */ + byte EE14 :1; /* Internal EEPROM map position Bit 14 */ + byte EE15 :1; /* Internal EEPROM map position Bit 15 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte grpEE_12 :4; + } MergedBits; +} INITEESTR; +extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012UL); +#define INITEE _INITEE.Byte +#define INITEE_EEON _INITEE.Bits.EEON +#define INITEE_EE12 _INITEE.Bits.EE12 +#define INITEE_EE13 _INITEE.Bits.EE13 +#define INITEE_EE14 _INITEE.Bits.EE14 +#define INITEE_EE15 _INITEE.Bits.EE15 +#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12 +#define INITEE_EE INITEE_EE_12 + +#define INITEE_EEON_MASK 1U +#define INITEE_EE12_MASK 16U +#define INITEE_EE13_MASK 32U +#define INITEE_EE14_MASK 64U +#define INITEE_EE15_MASK 128U +#define INITEE_EE_12_MASK 240U +#define INITEE_EE_12_BITNUM 4U + + +/*** MISC - Miscellaneous System Control Register; 0x00000013 ***/ +typedef union { + byte Byte; + struct { + byte ROMON :1; /* Enable Flash EEPROM */ + byte ROMHM :1; /* Flash EEPROM only in second half of memory map */ + byte EXSTR0 :1; /* External Access Stretch Bit 0 */ + byte EXSTR1 :1; /* External Access Stretch Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpEXSTR :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MISCSTR; +extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013UL); +#define MISC _MISC.Byte +#define MISC_ROMON _MISC.Bits.ROMON +#define MISC_ROMHM _MISC.Bits.ROMHM +#define MISC_EXSTR0 _MISC.Bits.EXSTR0 +#define MISC_EXSTR1 _MISC.Bits.EXSTR1 +#define MISC_EXSTR _MISC.MergedBits.grpEXSTR + +#define MISC_ROMON_MASK 1U +#define MISC_ROMHM_MASK 2U +#define MISC_EXSTR0_MASK 4U +#define MISC_EXSTR1_MASK 8U +#define MISC_EXSTR_MASK 12U +#define MISC_EXSTR_BITNUM 2U + + +/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/ +typedef union { + byte Byte; + struct { + byte ADR0 :1; /* Test register select Bit 0 */ + byte ADR1 :1; /* Test register select Bit 1 */ + byte ADR2 :1; /* Test register select Bit 2 */ + byte ADR3 :1; /* Test register select Bit 3 */ + byte WRTINT :1; /* Write to the Interrupt Test Registers */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpADR :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ITCRSTR; +extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015UL); +#define ITCR _ITCR.Byte +#define ITCR_ADR0 _ITCR.Bits.ADR0 +#define ITCR_ADR1 _ITCR.Bits.ADR1 +#define ITCR_ADR2 _ITCR.Bits.ADR2 +#define ITCR_ADR3 _ITCR.Bits.ADR3 +#define ITCR_WRTINT _ITCR.Bits.WRTINT +#define ITCR_ADR _ITCR.MergedBits.grpADR + +#define ITCR_ADR0_MASK 1U +#define ITCR_ADR1_MASK 2U +#define ITCR_ADR2_MASK 4U +#define ITCR_ADR3_MASK 8U +#define ITCR_WRTINT_MASK 16U +#define ITCR_ADR_MASK 15U +#define ITCR_ADR_BITNUM 0U + + +/*** ITEST - Interrupt Test Register; 0x00000016 ***/ +typedef union { + byte Byte; + struct { + byte INT0 :1; /* Interrupt Test Register Bit 0 */ + byte INT2 :1; /* Interrupt Test Register Bit 1 */ + byte INT4 :1; /* Interrupt Test Register Bit 2 */ + byte INT6 :1; /* Interrupt Test Register Bit 3 */ + byte INT8 :1; /* Interrupt Test Register Bit 4 */ + byte INTA :1; /* Interrupt Test Register Bit 5 */ + byte INTC :1; /* Interrupt Test Register Bit 6 */ + byte INTE :1; /* Interrupt Test Register Bit 7 */ + } Bits; +} ITESTSTR; +extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016UL); +#define ITEST _ITEST.Byte +#define ITEST_INT0 _ITEST.Bits.INT0 +#define ITEST_INT2 _ITEST.Bits.INT2 +#define ITEST_INT4 _ITEST.Bits.INT4 +#define ITEST_INT6 _ITEST.Bits.INT6 +#define ITEST_INT8 _ITEST.Bits.INT8 +#define ITEST_INTA _ITEST.Bits.INTA +#define ITEST_INTC _ITEST.Bits.INTC +#define ITEST_INTE _ITEST.Bits.INTE + +#define ITEST_INT0_MASK 1U +#define ITEST_INT2_MASK 2U +#define ITEST_INT4_MASK 4U +#define ITEST_INT6_MASK 8U +#define ITEST_INT8_MASK 16U +#define ITEST_INTA_MASK 32U +#define ITEST_INTC_MASK 64U +#define ITEST_INTE_MASK 128U + + +/*** PARTID - Part ID Register; 0x0000001A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PARTIDH - Part ID Register High; 0x0000001A ***/ + union { + byte Byte; + struct { + byte ID8 :1; /* Part ID Register Bit 8 */ + byte ID9 :1; /* Part ID Register Bit 9 */ + byte ID10 :1; /* Part ID Register Bit 10 */ + byte ID11 :1; /* Part ID Register Bit 11 */ + byte ID12 :1; /* Part ID Register Bit 12 */ + byte ID13 :1; /* Part ID Register Bit 13 */ + byte ID14 :1; /* Part ID Register Bit 14 */ + byte ID15 :1; /* Part ID Register Bit 15 */ + } Bits; + } PARTIDHSTR; + #define PARTIDH _PARTID.Overlap_STR.PARTIDHSTR.Byte + #define PARTIDH_ID8 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID8 + #define PARTIDH_ID9 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID9 + #define PARTIDH_ID10 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID10 + #define PARTIDH_ID11 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID11 + #define PARTIDH_ID12 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID12 + #define PARTIDH_ID13 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID13 + #define PARTIDH_ID14 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID14 + #define PARTIDH_ID15 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID15 + + #define PARTIDH_ID8_MASK 1U + #define PARTIDH_ID9_MASK 2U + #define PARTIDH_ID10_MASK 4U + #define PARTIDH_ID11_MASK 8U + #define PARTIDH_ID12_MASK 16U + #define PARTIDH_ID13_MASK 32U + #define PARTIDH_ID14_MASK 64U + #define PARTIDH_ID15_MASK 128U + + + /*** PARTIDL - Part ID Register Low; 0x0000001B ***/ + union { + byte Byte; + struct { + byte ID0 :1; /* Part ID Register Bit 0 */ + byte ID1 :1; /* Part ID Register Bit 1 */ + byte ID2 :1; /* Part ID Register Bit 2 */ + byte ID3 :1; /* Part ID Register Bit 3 */ + byte ID4 :1; /* Part ID Register Bit 4 */ + byte ID5 :1; /* Part ID Register Bit 5 */ + byte ID6 :1; /* Part ID Register Bit 6 */ + byte ID7 :1; /* Part ID Register Bit 7 */ + } Bits; + } PARTIDLSTR; + #define PARTIDL _PARTID.Overlap_STR.PARTIDLSTR.Byte + #define PARTIDL_ID0 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID0 + #define PARTIDL_ID1 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID1 + #define PARTIDL_ID2 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID2 + #define PARTIDL_ID3 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID3 + #define PARTIDL_ID4 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID4 + #define PARTIDL_ID5 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID5 + #define PARTIDL_ID6 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID6 + #define PARTIDL_ID7 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID7 + + #define PARTIDL_ID0_MASK 1U + #define PARTIDL_ID1_MASK 2U + #define PARTIDL_ID2_MASK 4U + #define PARTIDL_ID3_MASK 8U + #define PARTIDL_ID4_MASK 16U + #define PARTIDL_ID5_MASK 32U + #define PARTIDL_ID6_MASK 64U + #define PARTIDL_ID7_MASK 128U + + } Overlap_STR; + + struct { + word ID0 :1; /* Part ID Register Bit 0 */ + word ID1 :1; /* Part ID Register Bit 1 */ + word ID2 :1; /* Part ID Register Bit 2 */ + word ID3 :1; /* Part ID Register Bit 3 */ + word ID4 :1; /* Part ID Register Bit 4 */ + word ID5 :1; /* Part ID Register Bit 5 */ + word ID6 :1; /* Part ID Register Bit 6 */ + word ID7 :1; /* Part ID Register Bit 7 */ + word ID8 :1; /* Part ID Register Bit 8 */ + word ID9 :1; /* Part ID Register Bit 9 */ + word ID10 :1; /* Part ID Register Bit 10 */ + word ID11 :1; /* Part ID Register Bit 11 */ + word ID12 :1; /* Part ID Register Bit 12 */ + word ID13 :1; /* Part ID Register Bit 13 */ + word ID14 :1; /* Part ID Register Bit 14 */ + word ID15 :1; /* Part ID Register Bit 15 */ + } Bits; +} PARTIDSTR; +extern volatile PARTIDSTR _PARTID @(REG_BASE + 0x0000001AUL); +#define PARTID _PARTID.Word +#define PARTID_ID0 _PARTID.Bits.ID0 +#define PARTID_ID1 _PARTID.Bits.ID1 +#define PARTID_ID2 _PARTID.Bits.ID2 +#define PARTID_ID3 _PARTID.Bits.ID3 +#define PARTID_ID4 _PARTID.Bits.ID4 +#define PARTID_ID5 _PARTID.Bits.ID5 +#define PARTID_ID6 _PARTID.Bits.ID6 +#define PARTID_ID7 _PARTID.Bits.ID7 +#define PARTID_ID8 _PARTID.Bits.ID8 +#define PARTID_ID9 _PARTID.Bits.ID9 +#define PARTID_ID10 _PARTID.Bits.ID10 +#define PARTID_ID11 _PARTID.Bits.ID11 +#define PARTID_ID12 _PARTID.Bits.ID12 +#define PARTID_ID13 _PARTID.Bits.ID13 +#define PARTID_ID14 _PARTID.Bits.ID14 +#define PARTID_ID15 _PARTID.Bits.ID15 + +#define PARTID_ID0_MASK 1U +#define PARTID_ID1_MASK 2U +#define PARTID_ID2_MASK 4U +#define PARTID_ID3_MASK 8U +#define PARTID_ID4_MASK 16U +#define PARTID_ID5_MASK 32U +#define PARTID_ID6_MASK 64U +#define PARTID_ID7_MASK 128U +#define PARTID_ID8_MASK 256U +#define PARTID_ID9_MASK 512U +#define PARTID_ID10_MASK 1024U +#define PARTID_ID11_MASK 2048U +#define PARTID_ID12_MASK 4096U +#define PARTID_ID13_MASK 8192U +#define PARTID_ID14_MASK 16384U +#define PARTID_ID15_MASK 32768U + + +/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/ +typedef union { + byte Byte; + struct { + byte ram_sw0 :1; /* Allocated System RAM Memory Space Bit 0 */ + byte ram_sw1 :1; /* Allocated System RAM Memory Space Bit 1 */ + byte ram_sw2 :1; /* Allocated System RAM Memory Space Bit 2 */ + byte :1; + byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */ + byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */ + byte :1; + byte reg_sw0 :1; /* Allocated System Register Space */ + } Bits; + struct { + byte grpram_sw :3; + byte :1; + byte grpeep_sw :2; + byte :1; + byte grpreg_sw :1; + } MergedBits; +} MEMSIZ0STR; +extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001CUL); +#define MEMSIZ0 _MEMSIZ0.Byte +#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0 +#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1 +#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2 +#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0 +#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1 +#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0 +/* MEMSIZ_ARR: Access 2 MEMSIZx registers in an array */ +#define MEMSIZ_ARR ((volatile byte *) &MEMSIZ0) +#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw +#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw + +#define MEMSIZ0_ram_sw0_MASK 1U +#define MEMSIZ0_ram_sw1_MASK 2U +#define MEMSIZ0_ram_sw2_MASK 4U +#define MEMSIZ0_eep_sw0_MASK 16U +#define MEMSIZ0_eep_sw1_MASK 32U +#define MEMSIZ0_reg_sw0_MASK 128U +#define MEMSIZ0_ram_sw_MASK 7U +#define MEMSIZ0_ram_sw_BITNUM 0U +#define MEMSIZ0_eep_sw_MASK 48U +#define MEMSIZ0_eep_sw_BITNUM 4U + + +/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/ +typedef union { + byte Byte; + struct { + byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */ + byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */ + byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */ + } Bits; + struct { + byte grppag_sw :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grprom_sw :2; + } MergedBits; +} MEMSIZ1STR; +extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001DUL); +#define MEMSIZ1 _MEMSIZ1.Byte +#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0 +#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1 +#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0 +#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1 +#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw +#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw + +#define MEMSIZ1_pag_sw0_MASK 1U +#define MEMSIZ1_pag_sw1_MASK 2U +#define MEMSIZ1_rom_sw0_MASK 64U +#define MEMSIZ1_rom_sw1_MASK 128U +#define MEMSIZ1_pag_sw_MASK 3U +#define MEMSIZ1_pag_sw_BITNUM 0U +#define MEMSIZ1_rom_sw_MASK 192U +#define MEMSIZ1_rom_sw_BITNUM 6U + + +/*** INTCR - Interrupt Control Register; 0x0000001E ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte IRQEN :1; /* External IRQ Enable */ + byte IRQE :1; /* IRQ Select Edge Sensitive Only */ + } Bits; +} INTCRSTR; +extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001EUL); +#define INTCR _INTCR.Byte +#define INTCR_IRQEN _INTCR.Bits.IRQEN +#define INTCR_IRQE _INTCR.Bits.IRQE + +#define INTCR_IRQEN_MASK 64U +#define INTCR_IRQE_MASK 128U + + +/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */ + byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */ + byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */ + byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */ + byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */ + byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */ + byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */ + } Bits; + struct { + byte :1; + byte grpPSEL_1 :7; + } MergedBits; +} HPRIOSTR; +extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001FUL); +#define HPRIO _HPRIO.Byte +#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1 +#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2 +#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3 +#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4 +#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5 +#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6 +#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7 +#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1 +#define HPRIO_PSEL HPRIO_PSEL_1 + +#define HPRIO_PSEL1_MASK 2U +#define HPRIO_PSEL2_MASK 4U +#define HPRIO_PSEL3_MASK 8U +#define HPRIO_PSEL4_MASK 16U +#define HPRIO_PSEL5_MASK 32U +#define HPRIO_PSEL6_MASK 64U +#define HPRIO_PSEL7_MASK 128U +#define HPRIO_PSEL_1_MASK 254U +#define HPRIO_PSEL_1_BITNUM 1U + + +/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte BKTAG :1; /* Breakpoint on Tag */ + byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */ + byte BKFULL :1; /* Full Breakpoint Mode Enable */ + byte BKEN :1; /* Breakpoint Enable */ + } Bits; +} BKPCT0STR; +extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028UL); +#define BKPCT0 _BKPCT0.Byte +#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG +#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM +#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL +#define BKPCT0_BKEN _BKPCT0.Bits.BKEN +/* BKPCT_ARR: Access 2 BKPCTx registers in an array */ +#define BKPCT_ARR ((volatile byte *) &BKPCT0) + +#define BKPCT0_BKTAG_MASK 16U +#define BKPCT0_BKBDM_MASK 32U +#define BKPCT0_BKFULL_MASK 64U +#define BKPCT0_BKEN_MASK 128U + + +/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/ +typedef union { + byte Byte; + struct { + byte BK1RW :1; /* R/W Compare Value 1 */ + byte BK1RWE :1; /* R/W Compare Enable 1 */ + byte BK0RW :1; /* R/W Compare Value 0 */ + byte BK0RWE :1; /* R/W Compare Enable 0 */ + byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */ + byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */ + byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */ + byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */ + } Bits; +} BKPCT1STR; +extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029UL); +#define BKPCT1 _BKPCT1.Byte +#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW +#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE +#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW +#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE +#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL +#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH +#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL +#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH + +#define BKPCT1_BK1RW_MASK 1U +#define BKPCT1_BK1RWE_MASK 2U +#define BKPCT1_BK0RW_MASK 4U +#define BKPCT1_BK0RWE_MASK 8U +#define BKPCT1_BK1MBL_MASK 16U +#define BKPCT1_BK1MBH_MASK 32U +#define BKPCT1_BK0MBL_MASK 64U +#define BKPCT1_BK0MBH_MASK 128U + + +/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/ +typedef union { + byte Byte; + struct { + byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */ + byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */ + byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */ + byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */ + byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */ + byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpBK0V :6; + byte :1; + byte :1; + } MergedBits; +} BKP0XSTR; +extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002AUL); +#define BKP0X _BKP0X.Byte +#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0 +#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1 +#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2 +#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3 +#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4 +#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5 +#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V + +#define BKP0X_BK0V0_MASK 1U +#define BKP0X_BK0V1_MASK 2U +#define BKP0X_BK0V2_MASK 4U +#define BKP0X_BK0V3_MASK 8U +#define BKP0X_BK0V4_MASK 16U +#define BKP0X_BK0V5_MASK 32U +#define BKP0X_BK0V_MASK 63U +#define BKP0X_BK0V_BITNUM 0U + + +/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */ + byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */ + byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */ + byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */ + byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */ + byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */ + byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */ + byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */ + } Bits; +} BKP0HSTR; +extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002BUL); +#define BKP0H _BKP0H.Byte +#define BKP0H_BIT8 _BKP0H.Bits.BIT8 +#define BKP0H_BIT9 _BKP0H.Bits.BIT9 +#define BKP0H_BIT10 _BKP0H.Bits.BIT10 +#define BKP0H_BIT11 _BKP0H.Bits.BIT11 +#define BKP0H_BIT12 _BKP0H.Bits.BIT12 +#define BKP0H_BIT13 _BKP0H.Bits.BIT13 +#define BKP0H_BIT14 _BKP0H.Bits.BIT14 +#define BKP0H_BIT15 _BKP0H.Bits.BIT15 + +#define BKP0H_BIT8_MASK 1U +#define BKP0H_BIT9_MASK 2U +#define BKP0H_BIT10_MASK 4U +#define BKP0H_BIT11_MASK 8U +#define BKP0H_BIT12_MASK 16U +#define BKP0H_BIT13_MASK 32U +#define BKP0H_BIT14_MASK 64U +#define BKP0H_BIT15_MASK 128U + + +/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */ + byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */ + byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */ + byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */ + byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */ + byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */ + byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */ + byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */ + } Bits; +} BKP0LSTR; +extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002CUL); +#define BKP0L _BKP0L.Byte +#define BKP0L_BIT0 _BKP0L.Bits.BIT0 +#define BKP0L_BIT1 _BKP0L.Bits.BIT1 +#define BKP0L_BIT2 _BKP0L.Bits.BIT2 +#define BKP0L_BIT3 _BKP0L.Bits.BIT3 +#define BKP0L_BIT4 _BKP0L.Bits.BIT4 +#define BKP0L_BIT5 _BKP0L.Bits.BIT5 +#define BKP0L_BIT6 _BKP0L.Bits.BIT6 +#define BKP0L_BIT7 _BKP0L.Bits.BIT7 + +#define BKP0L_BIT0_MASK 1U +#define BKP0L_BIT1_MASK 2U +#define BKP0L_BIT2_MASK 4U +#define BKP0L_BIT3_MASK 8U +#define BKP0L_BIT4_MASK 16U +#define BKP0L_BIT5_MASK 32U +#define BKP0L_BIT6_MASK 64U +#define BKP0L_BIT7_MASK 128U + + +/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/ +typedef union { + byte Byte; + struct { + byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */ + byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */ + byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */ + byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */ + byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */ + byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpBK1V :6; + byte :1; + byte :1; + } MergedBits; +} BKP1XSTR; +extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002DUL); +#define BKP1X _BKP1X.Byte +#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0 +#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1 +#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2 +#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3 +#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4 +#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5 +#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V + +#define BKP1X_BK1V0_MASK 1U +#define BKP1X_BK1V1_MASK 2U +#define BKP1X_BK1V2_MASK 4U +#define BKP1X_BK1V3_MASK 8U +#define BKP1X_BK1V4_MASK 16U +#define BKP1X_BK1V5_MASK 32U +#define BKP1X_BK1V_MASK 63U +#define BKP1X_BK1V_BITNUM 0U + + +/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */ + byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */ + byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */ + byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */ + byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */ + byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */ + byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */ + byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */ + } Bits; +} BKP1HSTR; +extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002EUL); +#define BKP1H _BKP1H.Byte +#define BKP1H_BIT8 _BKP1H.Bits.BIT8 +#define BKP1H_BIT9 _BKP1H.Bits.BIT9 +#define BKP1H_BIT10 _BKP1H.Bits.BIT10 +#define BKP1H_BIT11 _BKP1H.Bits.BIT11 +#define BKP1H_BIT12 _BKP1H.Bits.BIT12 +#define BKP1H_BIT13 _BKP1H.Bits.BIT13 +#define BKP1H_BIT14 _BKP1H.Bits.BIT14 +#define BKP1H_BIT15 _BKP1H.Bits.BIT15 + +#define BKP1H_BIT8_MASK 1U +#define BKP1H_BIT9_MASK 2U +#define BKP1H_BIT10_MASK 4U +#define BKP1H_BIT11_MASK 8U +#define BKP1H_BIT12_MASK 16U +#define BKP1H_BIT13_MASK 32U +#define BKP1H_BIT14_MASK 64U +#define BKP1H_BIT15_MASK 128U + + +/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */ + byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */ + byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */ + byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */ + byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */ + byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */ + byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */ + byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */ + } Bits; +} BKP1LSTR; +extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002FUL); +#define BKP1L _BKP1L.Byte +#define BKP1L_BIT0 _BKP1L.Bits.BIT0 +#define BKP1L_BIT1 _BKP1L.Bits.BIT1 +#define BKP1L_BIT2 _BKP1L.Bits.BIT2 +#define BKP1L_BIT3 _BKP1L.Bits.BIT3 +#define BKP1L_BIT4 _BKP1L.Bits.BIT4 +#define BKP1L_BIT5 _BKP1L.Bits.BIT5 +#define BKP1L_BIT6 _BKP1L.Bits.BIT6 +#define BKP1L_BIT7 _BKP1L.Bits.BIT7 + +#define BKP1L_BIT0_MASK 1U +#define BKP1L_BIT1_MASK 2U +#define BKP1L_BIT2_MASK 4U +#define BKP1L_BIT3_MASK 8U +#define BKP1L_BIT4_MASK 16U +#define BKP1L_BIT5_MASK 32U +#define BKP1L_BIT6_MASK 64U +#define BKP1L_BIT7_MASK 128U + + +/*** PPAGE - Page Index Register; 0x00000030 ***/ +typedef union { + byte Byte; + struct { + byte PIX0 :1; /* Page Index Register Bit 0 */ + byte PIX1 :1; /* Page Index Register Bit 1 */ + byte PIX2 :1; /* Page Index Register Bit 2 */ + byte PIX3 :1; /* Page Index Register Bit 3 */ + byte PIX4 :1; /* Page Index Register Bit 4 */ + byte PIX5 :1; /* Page Index Register Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPIX :6; + byte :1; + byte :1; + } MergedBits; +} PPAGESTR; +extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030UL); +#define PPAGE _PPAGE.Byte +#define PPAGE_PIX0 _PPAGE.Bits.PIX0 +#define PPAGE_PIX1 _PPAGE.Bits.PIX1 +#define PPAGE_PIX2 _PPAGE.Bits.PIX2 +#define PPAGE_PIX3 _PPAGE.Bits.PIX3 +#define PPAGE_PIX4 _PPAGE.Bits.PIX4 +#define PPAGE_PIX5 _PPAGE.Bits.PIX5 +#define PPAGE_PIX _PPAGE.MergedBits.grpPIX + +#define PPAGE_PIX0_MASK 1U +#define PPAGE_PIX1_MASK 2U +#define PPAGE_PIX2_MASK 4U +#define PPAGE_PIX3_MASK 8U +#define PPAGE_PIX4_MASK 16U +#define PPAGE_PIX5_MASK 32U +#define PPAGE_PIX_MASK 63U +#define PPAGE_PIX_BITNUM 0U + + +/*** PORTK - Port K Data Register; 0x00000032 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port K Bit 0 */ + byte BIT1 :1; /* Port K Bit 1 */ + byte BIT2 :1; /* Port K Bit 2 */ + byte BIT3 :1; /* Port K Bit 3 */ + byte BIT4 :1; /* Port K Bit 4 */ + byte BIT5 :1; /* Port K Bit 5 */ + byte :1; + byte BIT7 :1; /* Port K Bit 7 */ + } Bits; + struct { + byte grpBIT :6; + byte :1; + byte grpBIT_7 :1; + } MergedBits; +} PORTKSTR; +extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032UL); +#define PORTK _PORTK.Byte +#define PORTK_BIT0 _PORTK.Bits.BIT0 +#define PORTK_BIT1 _PORTK.Bits.BIT1 +#define PORTK_BIT2 _PORTK.Bits.BIT2 +#define PORTK_BIT3 _PORTK.Bits.BIT3 +#define PORTK_BIT4 _PORTK.Bits.BIT4 +#define PORTK_BIT5 _PORTK.Bits.BIT5 +#define PORTK_BIT7 _PORTK.Bits.BIT7 +#define PORTK_BIT _PORTK.MergedBits.grpBIT + +#define PORTK_BIT0_MASK 1U +#define PORTK_BIT1_MASK 2U +#define PORTK_BIT2_MASK 4U +#define PORTK_BIT3_MASK 8U +#define PORTK_BIT4_MASK 16U +#define PORTK_BIT5_MASK 32U +#define PORTK_BIT7_MASK 128U +#define PORTK_BIT_MASK 63U +#define PORTK_BIT_BITNUM 0U + + +/*** DDRK - Port K Data Direction Register; 0x00000033 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port K Data Direction Bit 0 */ + byte BIT1 :1; /* Port K Data Direction Bit 1 */ + byte BIT2 :1; /* Port K Data Direction Bit 2 */ + byte BIT3 :1; /* Port K Data Direction Bit 3 */ + byte BIT4 :1; /* Port K Data Direction Bit 4 */ + byte BIT5 :1; /* Port K Data Direction Bit 5 */ + byte :1; + byte BIT7 :1; /* Port K Data Direction Bit 7 */ + } Bits; + struct { + byte grpBIT :6; + byte :1; + byte grpBIT_7 :1; + } MergedBits; +} DDRKSTR; +extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033UL); +#define DDRK _DDRK.Byte +#define DDRK_BIT0 _DDRK.Bits.BIT0 +#define DDRK_BIT1 _DDRK.Bits.BIT1 +#define DDRK_BIT2 _DDRK.Bits.BIT2 +#define DDRK_BIT3 _DDRK.Bits.BIT3 +#define DDRK_BIT4 _DDRK.Bits.BIT4 +#define DDRK_BIT5 _DDRK.Bits.BIT5 +#define DDRK_BIT7 _DDRK.Bits.BIT7 +#define DDRK_BIT _DDRK.MergedBits.grpBIT + +#define DDRK_BIT0_MASK 1U +#define DDRK_BIT1_MASK 2U +#define DDRK_BIT2_MASK 4U +#define DDRK_BIT3_MASK 8U +#define DDRK_BIT4_MASK 16U +#define DDRK_BIT5_MASK 32U +#define DDRK_BIT7_MASK 128U +#define DDRK_BIT_MASK 63U +#define DDRK_BIT_BITNUM 0U + + +/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/ +typedef union { + byte Byte; + struct { + byte SYN0 :1; /* CRG Synthesizer Bit 0 */ + byte SYN1 :1; /* CRG Synthesizer Bit 1 */ + byte SYN2 :1; /* CRG Synthesizer Bit 2 */ + byte SYN3 :1; /* CRG Synthesizer Bit 3 */ + byte SYN4 :1; /* CRG Synthesizer Bit 4 */ + byte SYN5 :1; /* CRG Synthesizer Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpSYN :6; + byte :1; + byte :1; + } MergedBits; +} SYNRSTR; +extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034UL); +#define SYNR _SYNR.Byte +#define SYNR_SYN0 _SYNR.Bits.SYN0 +#define SYNR_SYN1 _SYNR.Bits.SYN1 +#define SYNR_SYN2 _SYNR.Bits.SYN2 +#define SYNR_SYN3 _SYNR.Bits.SYN3 +#define SYNR_SYN4 _SYNR.Bits.SYN4 +#define SYNR_SYN5 _SYNR.Bits.SYN5 +#define SYNR_SYN _SYNR.MergedBits.grpSYN + +#define SYNR_SYN0_MASK 1U +#define SYNR_SYN1_MASK 2U +#define SYNR_SYN2_MASK 4U +#define SYNR_SYN3_MASK 8U +#define SYNR_SYN4_MASK 16U +#define SYNR_SYN5_MASK 32U +#define SYNR_SYN_MASK 63U +#define SYNR_SYN_BITNUM 0U + + +/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/ +typedef union { + byte Byte; + struct { + byte REFDV0 :1; /* CRG Reference Divider Bit 0 */ + byte REFDV1 :1; /* CRG Reference Divider Bit 1 */ + byte REFDV2 :1; /* CRG Reference Divider Bit 2 */ + byte REFDV3 :1; /* CRG Reference Divider Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpREFDV :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} REFDVSTR; +extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035UL); +#define REFDV _REFDV.Byte +#define REFDV_REFDV0 _REFDV.Bits.REFDV0 +#define REFDV_REFDV1 _REFDV.Bits.REFDV1 +#define REFDV_REFDV2 _REFDV.Bits.REFDV2 +#define REFDV_REFDV3 _REFDV.Bits.REFDV3 +#define REFDV_REFDV _REFDV.MergedBits.grpREFDV + +#define REFDV_REFDV0_MASK 1U +#define REFDV_REFDV1_MASK 2U +#define REFDV_REFDV2_MASK 4U +#define REFDV_REFDV3_MASK 8U +#define REFDV_REFDV_MASK 15U +#define REFDV_REFDV_BITNUM 0U + + +/*** CRGFLG - CRG Flags Register; 0x00000037 ***/ +typedef union { + byte Byte; + struct { + byte SCM :1; /* Self-clock mode Status */ + byte SCMIF :1; /* Self-clock mode Interrupt Flag */ + byte TRACK :1; /* Track Status */ + byte LOCK :1; /* Lock Status */ + byte LOCKIF :1; /* PLL Lock Interrupt Flag */ + byte :1; + byte PORF :1; /* Power on Reset Flag */ + byte RTIF :1; /* Real Time Interrupt Flag */ + } Bits; +} CRGFLGSTR; +extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037UL); +#define CRGFLG _CRGFLG.Byte +#define CRGFLG_SCM _CRGFLG.Bits.SCM +#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF +#define CRGFLG_TRACK _CRGFLG.Bits.TRACK +#define CRGFLG_LOCK _CRGFLG.Bits.LOCK +#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF +#define CRGFLG_PORF _CRGFLG.Bits.PORF +#define CRGFLG_RTIF _CRGFLG.Bits.RTIF + +#define CRGFLG_SCM_MASK 1U +#define CRGFLG_SCMIF_MASK 2U +#define CRGFLG_TRACK_MASK 4U +#define CRGFLG_LOCK_MASK 8U +#define CRGFLG_LOCKIF_MASK 16U +#define CRGFLG_PORF_MASK 64U +#define CRGFLG_RTIF_MASK 128U + + +/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte SCMIE :1; /* Self-clock mode Interrupt Enable */ + byte :1; + byte :1; + byte LOCKIE :1; /* Lock Interrupt Enable */ + byte :1; + byte :1; + byte RTIE :1; /* Real Time Interrupt Enable */ + } Bits; +} CRGINTSTR; +extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038UL); +#define CRGINT _CRGINT.Byte +#define CRGINT_SCMIE _CRGINT.Bits.SCMIE +#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE +#define CRGINT_RTIE _CRGINT.Bits.RTIE + +#define CRGINT_SCMIE_MASK 2U +#define CRGINT_LOCKIE_MASK 16U +#define CRGINT_RTIE_MASK 128U + + +/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/ +typedef union { + byte Byte; + struct { + byte COPWAI :1; /* COP stops in WAIT mode */ + byte RTIWAI :1; /* RTI stops in WAIT mode */ + byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */ + byte PLLWAI :1; /* PLL stops in WAIT mode */ + byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */ + byte SYSWAI :1; /* System clocks stop in WAIT mode */ + byte PSTP :1; /* Pseudo Stop */ + byte PLLSEL :1; /* PLL selected for system clock */ + } Bits; +} CLKSELSTR; +extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039UL); +#define CLKSEL _CLKSEL.Byte +#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI +#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI +#define CLKSEL_CWAI _CLKSEL.Bits.CWAI +#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI +#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI +#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI +#define CLKSEL_PSTP _CLKSEL.Bits.PSTP +#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL + +#define CLKSEL_COPWAI_MASK 1U +#define CLKSEL_RTIWAI_MASK 2U +#define CLKSEL_CWAI_MASK 4U +#define CLKSEL_PLLWAI_MASK 8U +#define CLKSEL_ROAWAI_MASK 16U +#define CLKSEL_SYSWAI_MASK 32U +#define CLKSEL_PSTP_MASK 64U +#define CLKSEL_PLLSEL_MASK 128U + + +/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/ +typedef union { + byte Byte; + struct { + byte SCME :1; /* Self-clock mode enable */ + byte PCE :1; /* COP Enable during Pseudo Stop Bit */ + byte PRE :1; /* RTI Enable during Pseudo Stop Bit */ + byte :1; + byte ACQ :1; /* Acquisition */ + byte AUTO :1; /* Automatic Bandwidth Control */ + byte PLLON :1; /* Phase Lock Loop On */ + byte CME :1; /* Clock Monitor Enable */ + } Bits; +} PLLCTLSTR; +extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003AUL); +#define PLLCTL _PLLCTL.Byte +#define PLLCTL_SCME _PLLCTL.Bits.SCME +#define PLLCTL_PCE _PLLCTL.Bits.PCE +#define PLLCTL_PRE _PLLCTL.Bits.PRE +#define PLLCTL_ACQ _PLLCTL.Bits.ACQ +#define PLLCTL_AUTO _PLLCTL.Bits.AUTO +#define PLLCTL_PLLON _PLLCTL.Bits.PLLON +#define PLLCTL_CME _PLLCTL.Bits.CME + +#define PLLCTL_SCME_MASK 1U +#define PLLCTL_PCE_MASK 2U +#define PLLCTL_PRE_MASK 4U +#define PLLCTL_ACQ_MASK 16U +#define PLLCTL_AUTO_MASK 32U +#define PLLCTL_PLLON_MASK 64U +#define PLLCTL_CME_MASK 128U + + +/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/ +typedef union { + byte Byte; + struct { + byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select Bit 0 */ + byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select Bit 1 */ + byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select Bit 2 */ + byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select Bit 3 */ + byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select Bit 4 */ + byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select Bit 5 */ + byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select Bit 6 */ + byte :1; + } Bits; + struct { + byte grpRTR :7; + byte :1; + } MergedBits; +} RTICTLSTR; +extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003BUL); +#define RTICTL _RTICTL.Byte +#define RTICTL_RTR0 _RTICTL.Bits.RTR0 +#define RTICTL_RTR1 _RTICTL.Bits.RTR1 +#define RTICTL_RTR2 _RTICTL.Bits.RTR2 +#define RTICTL_RTR3 _RTICTL.Bits.RTR3 +#define RTICTL_RTR4 _RTICTL.Bits.RTR4 +#define RTICTL_RTR5 _RTICTL.Bits.RTR5 +#define RTICTL_RTR6 _RTICTL.Bits.RTR6 +#define RTICTL_RTR _RTICTL.MergedBits.grpRTR + +#define RTICTL_RTR0_MASK 1U +#define RTICTL_RTR1_MASK 2U +#define RTICTL_RTR2_MASK 4U +#define RTICTL_RTR3_MASK 8U +#define RTICTL_RTR4_MASK 16U +#define RTICTL_RTR5_MASK 32U +#define RTICTL_RTR6_MASK 64U +#define RTICTL_RTR_MASK 127U +#define RTICTL_RTR_BITNUM 0U + + +/*** COPCTL - CRG COP Control Register; 0x0000003C ***/ +typedef union { + byte Byte; + struct { + byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */ + byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */ + byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */ + byte :1; + byte :1; + byte :1; + byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */ + byte WCOP :1; /* Window COP mode */ + } Bits; + struct { + byte grpCR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} COPCTLSTR; +extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003CUL); +#define COPCTL _COPCTL.Byte +#define COPCTL_CR0 _COPCTL.Bits.CR0 +#define COPCTL_CR1 _COPCTL.Bits.CR1 +#define COPCTL_CR2 _COPCTL.Bits.CR2 +#define COPCTL_RSBCK _COPCTL.Bits.RSBCK +#define COPCTL_WCOP _COPCTL.Bits.WCOP +#define COPCTL_CR _COPCTL.MergedBits.grpCR + +#define COPCTL_CR0_MASK 1U +#define COPCTL_CR1_MASK 2U +#define COPCTL_CR2_MASK 4U +#define COPCTL_RSBCK_MASK 64U +#define COPCTL_WCOP_MASK 128U +#define COPCTL_CR_MASK 7U +#define COPCTL_CR_BITNUM 0U + + +/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */ + byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */ + byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */ + byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */ + byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */ + byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */ + byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */ + byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */ + } Bits; +} ARMCOPSTR; +extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003FUL); +#define ARMCOP _ARMCOP.Byte +#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0 +#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1 +#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2 +#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3 +#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4 +#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5 +#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6 +#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7 + +#define ARMCOP_BIT0_MASK 1U +#define ARMCOP_BIT1_MASK 2U +#define ARMCOP_BIT2_MASK 4U +#define ARMCOP_BIT3_MASK 8U +#define ARMCOP_BIT4_MASK 16U +#define ARMCOP_BIT5_MASK 32U +#define ARMCOP_BIT6_MASK 64U +#define ARMCOP_BIT7_MASK 128U + + +/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/ +typedef union { + byte Byte; + struct { + byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */ + byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */ + byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */ + byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */ + byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */ + byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */ + byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */ + byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */ + } Bits; +} TIOSSTR; +extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040UL); +#define TIOS _TIOS.Byte +#define TIOS_IOS0 _TIOS.Bits.IOS0 +#define TIOS_IOS1 _TIOS.Bits.IOS1 +#define TIOS_IOS2 _TIOS.Bits.IOS2 +#define TIOS_IOS3 _TIOS.Bits.IOS3 +#define TIOS_IOS4 _TIOS.Bits.IOS4 +#define TIOS_IOS5 _TIOS.Bits.IOS5 +#define TIOS_IOS6 _TIOS.Bits.IOS6 +#define TIOS_IOS7 _TIOS.Bits.IOS7 + +#define TIOS_IOS0_MASK 1U +#define TIOS_IOS1_MASK 2U +#define TIOS_IOS2_MASK 4U +#define TIOS_IOS3_MASK 8U +#define TIOS_IOS4_MASK 16U +#define TIOS_IOS5_MASK 32U +#define TIOS_IOS6_MASK 64U +#define TIOS_IOS7_MASK 128U + + +/*** CFORC - Timer Compare Force Register; 0x00000041 ***/ +typedef union { + byte Byte; + struct { + byte FOC0 :1; /* Force Output Compare Action for Channel 0 */ + byte FOC1 :1; /* Force Output Compare Action for Channel 1 */ + byte FOC2 :1; /* Force Output Compare Action for Channel 2 */ + byte FOC3 :1; /* Force Output Compare Action for Channel 3 */ + byte FOC4 :1; /* Force Output Compare Action for Channel 4 */ + byte FOC5 :1; /* Force Output Compare Action for Channel 5 */ + byte FOC6 :1; /* Force Output Compare Action for Channel 6 */ + byte FOC7 :1; /* Force Output Compare Action for Channel 7 */ + } Bits; +} CFORCSTR; +extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041UL); +#define CFORC _CFORC.Byte +#define CFORC_FOC0 _CFORC.Bits.FOC0 +#define CFORC_FOC1 _CFORC.Bits.FOC1 +#define CFORC_FOC2 _CFORC.Bits.FOC2 +#define CFORC_FOC3 _CFORC.Bits.FOC3 +#define CFORC_FOC4 _CFORC.Bits.FOC4 +#define CFORC_FOC5 _CFORC.Bits.FOC5 +#define CFORC_FOC6 _CFORC.Bits.FOC6 +#define CFORC_FOC7 _CFORC.Bits.FOC7 + +#define CFORC_FOC0_MASK 1U +#define CFORC_FOC1_MASK 2U +#define CFORC_FOC2_MASK 4U +#define CFORC_FOC3_MASK 8U +#define CFORC_FOC4_MASK 16U +#define CFORC_FOC5_MASK 32U +#define CFORC_FOC6_MASK 64U +#define CFORC_FOC7_MASK 128U + + +/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/ +typedef union { + byte Byte; + struct { + byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */ + byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */ + byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */ + byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */ + byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */ + byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */ + byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */ + byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */ + } Bits; +} OC7MSTR; +extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042UL); +#define OC7M _OC7M.Byte +#define OC7M_OC7M0 _OC7M.Bits.OC7M0 +#define OC7M_OC7M1 _OC7M.Bits.OC7M1 +#define OC7M_OC7M2 _OC7M.Bits.OC7M2 +#define OC7M_OC7M3 _OC7M.Bits.OC7M3 +#define OC7M_OC7M4 _OC7M.Bits.OC7M4 +#define OC7M_OC7M5 _OC7M.Bits.OC7M5 +#define OC7M_OC7M6 _OC7M.Bits.OC7M6 +#define OC7M_OC7M7 _OC7M.Bits.OC7M7 + +#define OC7M_OC7M0_MASK 1U +#define OC7M_OC7M1_MASK 2U +#define OC7M_OC7M2_MASK 4U +#define OC7M_OC7M3_MASK 8U +#define OC7M_OC7M4_MASK 16U +#define OC7M_OC7M5_MASK 32U +#define OC7M_OC7M6_MASK 64U +#define OC7M_OC7M7_MASK 128U + + +/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/ +typedef union { + byte Byte; +} OC7DSTR; +extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043UL); +#define OC7D _OC7D.Byte + + +/*** TCNT - Timer Count Register; 0x00000044 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TCNTHi - Timer Count Register High; 0x00000044 ***/ + union { + byte Byte; + } TCNTHiSTR; + #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte + + + /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/ + union { + byte Byte; + } TCNTLoSTR; + #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte + + } Overlap_STR; + +} TCNTSTR; +extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044UL); +#define TCNT _TCNT.Word + + +/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte TFFCA :1; /* Timer Fast Flag Clear All */ + byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */ + byte TSWAI :1; /* Timer Module Stops While in Wait */ + byte TEN :1; /* Timer Enable */ + } Bits; +} TSCR1STR; +extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046UL); +#define TSCR1 _TSCR1.Byte +#define TSCR1_TFFCA _TSCR1.Bits.TFFCA +#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ +#define TSCR1_TSWAI _TSCR1.Bits.TSWAI +#define TSCR1_TEN _TSCR1.Bits.TEN + +#define TSCR1_TFFCA_MASK 16U +#define TSCR1_TSFRZ_MASK 32U +#define TSCR1_TSWAI_MASK 64U +#define TSCR1_TEN_MASK 128U + + +/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/ +typedef union { + byte Byte; + struct { + byte TOV0 :1; /* Toggle On Overflow Bit 0 */ + byte TOV1 :1; /* Toggle On Overflow Bit 1 */ + byte TOV2 :1; /* Toggle On Overflow Bit 2 */ + byte TOV3 :1; /* Toggle On Overflow Bit 3 */ + byte TOV4 :1; /* Toggle On Overflow Bit 4 */ + byte TOV5 :1; /* Toggle On Overflow Bit 5 */ + byte TOV6 :1; /* Toggle On Overflow Bit 6 */ + byte TOV7 :1; /* Toggle On Overflow Bit 7 */ + } Bits; +} TTOVSTR; +extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047UL); +#define TTOV _TTOV.Byte +#define TTOV_TOV0 _TTOV.Bits.TOV0 +#define TTOV_TOV1 _TTOV.Bits.TOV1 +#define TTOV_TOV2 _TTOV.Bits.TOV2 +#define TTOV_TOV3 _TTOV.Bits.TOV3 +#define TTOV_TOV4 _TTOV.Bits.TOV4 +#define TTOV_TOV5 _TTOV.Bits.TOV5 +#define TTOV_TOV6 _TTOV.Bits.TOV6 +#define TTOV_TOV7 _TTOV.Bits.TOV7 + +#define TTOV_TOV0_MASK 1U +#define TTOV_TOV1_MASK 2U +#define TTOV_TOV2_MASK 4U +#define TTOV_TOV3_MASK 8U +#define TTOV_TOV4_MASK 16U +#define TTOV_TOV5_MASK 32U +#define TTOV_TOV6_MASK 64U +#define TTOV_TOV7_MASK 128U + + +/*** TCTL1 - Timer Control Register 1; 0x00000048 ***/ +typedef union { + byte Byte; + struct { + byte OL4 :1; /* Output Level Bit 4 */ + byte OM4 :1; /* Output Mode Bit 4 */ + byte OL5 :1; /* Output Level Bit 5 */ + byte OM5 :1; /* Output Mode Bit 5 */ + byte OL6 :1; /* Output Level Bit 6 */ + byte OM6 :1; /* Output Mode Bit 6 */ + byte OL7 :1; /* Output Level Bit 7 */ + byte OM7 :1; /* Output Mode Bit 7 */ + } Bits; +} TCTL1STR; +extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048UL); +#define TCTL1 _TCTL1.Byte +#define TCTL1_OL4 _TCTL1.Bits.OL4 +#define TCTL1_OM4 _TCTL1.Bits.OM4 +#define TCTL1_OL5 _TCTL1.Bits.OL5 +#define TCTL1_OM5 _TCTL1.Bits.OM5 +#define TCTL1_OL6 _TCTL1.Bits.OL6 +#define TCTL1_OM6 _TCTL1.Bits.OM6 +#define TCTL1_OL7 _TCTL1.Bits.OL7 +#define TCTL1_OM7 _TCTL1.Bits.OM7 + +#define TCTL1_OL4_MASK 1U +#define TCTL1_OM4_MASK 2U +#define TCTL1_OL5_MASK 4U +#define TCTL1_OM5_MASK 8U +#define TCTL1_OL6_MASK 16U +#define TCTL1_OM6_MASK 32U +#define TCTL1_OL7_MASK 64U +#define TCTL1_OM7_MASK 128U + + +/*** TCTL2 - Timer Control Register 2; 0x00000049 ***/ +typedef union { + byte Byte; + struct { + byte OL0 :1; /* Output Level Bit 0 */ + byte OM0 :1; /* Output Mode Bit 0 */ + byte OL1 :1; /* Output Level Bit 1 */ + byte OM1 :1; /* Output Mode Bit 1 */ + byte OL2 :1; /* Output Level Bit 2 */ + byte OM2 :1; /* Output Mode Bit 2 */ + byte OL3 :1; /* Output Level Bit 3 */ + byte OM3 :1; /* Output Mode Bit 3 */ + } Bits; +} TCTL2STR; +extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049UL); +#define TCTL2 _TCTL2.Byte +#define TCTL2_OL0 _TCTL2.Bits.OL0 +#define TCTL2_OM0 _TCTL2.Bits.OM0 +#define TCTL2_OL1 _TCTL2.Bits.OL1 +#define TCTL2_OM1 _TCTL2.Bits.OM1 +#define TCTL2_OL2 _TCTL2.Bits.OL2 +#define TCTL2_OM2 _TCTL2.Bits.OM2 +#define TCTL2_OL3 _TCTL2.Bits.OL3 +#define TCTL2_OM3 _TCTL2.Bits.OM3 + +#define TCTL2_OL0_MASK 1U +#define TCTL2_OM0_MASK 2U +#define TCTL2_OL1_MASK 4U +#define TCTL2_OM1_MASK 8U +#define TCTL2_OL2_MASK 16U +#define TCTL2_OM2_MASK 32U +#define TCTL2_OL3_MASK 64U +#define TCTL2_OM3_MASK 128U + + +/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/ +typedef union { + byte Byte; + struct { + byte EDG4A :1; /* Input Capture Edge Control 4A */ + byte EDG4B :1; /* Input Capture Edge Control 4B */ + byte EDG5A :1; /* Input Capture Edge Control 5A */ + byte EDG5B :1; /* Input Capture Edge Control 5B */ + byte EDG6A :1; /* Input Capture Edge Control 6A */ + byte EDG6B :1; /* Input Capture Edge Control 6B */ + byte EDG7A :1; /* Input Capture Edge Control 7A */ + byte EDG7B :1; /* Input Capture Edge Control 7B */ + } Bits; + struct { + byte grpEDG4x :2; + byte grpEDG5x :2; + byte grpEDG6x :2; + byte grpEDG7x :2; + } MergedBits; +} TCTL3STR; +extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004AUL); +#define TCTL3 _TCTL3.Byte +#define TCTL3_EDG4A _TCTL3.Bits.EDG4A +#define TCTL3_EDG4B _TCTL3.Bits.EDG4B +#define TCTL3_EDG5A _TCTL3.Bits.EDG5A +#define TCTL3_EDG5B _TCTL3.Bits.EDG5B +#define TCTL3_EDG6A _TCTL3.Bits.EDG6A +#define TCTL3_EDG6B _TCTL3.Bits.EDG6B +#define TCTL3_EDG7A _TCTL3.Bits.EDG7A +#define TCTL3_EDG7B _TCTL3.Bits.EDG7B +#define TCTL3_EDG4x _TCTL3.MergedBits.grpEDG4x +#define TCTL3_EDG5x _TCTL3.MergedBits.grpEDG5x +#define TCTL3_EDG6x _TCTL3.MergedBits.grpEDG6x +#define TCTL3_EDG7x _TCTL3.MergedBits.grpEDG7x + +#define TCTL3_EDG4A_MASK 1U +#define TCTL3_EDG4B_MASK 2U +#define TCTL3_EDG5A_MASK 4U +#define TCTL3_EDG5B_MASK 8U +#define TCTL3_EDG6A_MASK 16U +#define TCTL3_EDG6B_MASK 32U +#define TCTL3_EDG7A_MASK 64U +#define TCTL3_EDG7B_MASK 128U +#define TCTL3_EDG4x_MASK 3U +#define TCTL3_EDG4x_BITNUM 0U +#define TCTL3_EDG5x_MASK 12U +#define TCTL3_EDG5x_BITNUM 2U +#define TCTL3_EDG6x_MASK 48U +#define TCTL3_EDG6x_BITNUM 4U +#define TCTL3_EDG7x_MASK 192U +#define TCTL3_EDG7x_BITNUM 6U + + +/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/ +typedef union { + byte Byte; + struct { + byte EDG0A :1; /* Input Capture Edge Control 0A */ + byte EDG0B :1; /* Input Capture Edge Control 0B */ + byte EDG1A :1; /* Input Capture Edge Control 1A */ + byte EDG1B :1; /* Input Capture Edge Control 1B */ + byte EDG2A :1; /* Input Capture Edge Control 2A */ + byte EDG2B :1; /* Input Capture Edge Control 2B */ + byte EDG3A :1; /* Input Capture Edge Control 3A */ + byte EDG3B :1; /* Input Capture Edge Control 3B */ + } Bits; + struct { + byte grpEDG0x :2; + byte grpEDG1x :2; + byte grpEDG2x :2; + byte grpEDG3x :2; + } MergedBits; +} TCTL4STR; +extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004BUL); +#define TCTL4 _TCTL4.Byte +#define TCTL4_EDG0A _TCTL4.Bits.EDG0A +#define TCTL4_EDG0B _TCTL4.Bits.EDG0B +#define TCTL4_EDG1A _TCTL4.Bits.EDG1A +#define TCTL4_EDG1B _TCTL4.Bits.EDG1B +#define TCTL4_EDG2A _TCTL4.Bits.EDG2A +#define TCTL4_EDG2B _TCTL4.Bits.EDG2B +#define TCTL4_EDG3A _TCTL4.Bits.EDG3A +#define TCTL4_EDG3B _TCTL4.Bits.EDG3B +#define TCTL4_EDG0x _TCTL4.MergedBits.grpEDG0x +#define TCTL4_EDG1x _TCTL4.MergedBits.grpEDG1x +#define TCTL4_EDG2x _TCTL4.MergedBits.grpEDG2x +#define TCTL4_EDG3x _TCTL4.MergedBits.grpEDG3x + +#define TCTL4_EDG0A_MASK 1U +#define TCTL4_EDG0B_MASK 2U +#define TCTL4_EDG1A_MASK 4U +#define TCTL4_EDG1B_MASK 8U +#define TCTL4_EDG2A_MASK 16U +#define TCTL4_EDG2B_MASK 32U +#define TCTL4_EDG3A_MASK 64U +#define TCTL4_EDG3B_MASK 128U +#define TCTL4_EDG0x_MASK 3U +#define TCTL4_EDG0x_BITNUM 0U +#define TCTL4_EDG1x_MASK 12U +#define TCTL4_EDG1x_BITNUM 2U +#define TCTL4_EDG2x_MASK 48U +#define TCTL4_EDG2x_BITNUM 4U +#define TCTL4_EDG3x_MASK 192U +#define TCTL4_EDG3x_BITNUM 6U + + +/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/ +typedef union { + byte Byte; + struct { + byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */ + byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */ + byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */ + byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */ + byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */ + byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */ + byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */ + byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */ + } Bits; +} TIESTR; +extern volatile TIESTR _TIE @(REG_BASE + 0x0000004CUL); +#define TIE _TIE.Byte +#define TIE_C0I _TIE.Bits.C0I +#define TIE_C1I _TIE.Bits.C1I +#define TIE_C2I _TIE.Bits.C2I +#define TIE_C3I _TIE.Bits.C3I +#define TIE_C4I _TIE.Bits.C4I +#define TIE_C5I _TIE.Bits.C5I +#define TIE_C6I _TIE.Bits.C6I +#define TIE_C7I _TIE.Bits.C7I + +#define TIE_C0I_MASK 1U +#define TIE_C1I_MASK 2U +#define TIE_C2I_MASK 4U +#define TIE_C3I_MASK 8U +#define TIE_C4I_MASK 16U +#define TIE_C5I_MASK 32U +#define TIE_C6I_MASK 64U +#define TIE_C7I_MASK 128U + + +/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/ +typedef union { + byte Byte; + struct { + byte PR0 :1; /* Timer Prescaler Select Bit 0 */ + byte PR1 :1; /* Timer Prescaler Select Bit 1 */ + byte PR2 :1; /* Timer Prescaler Select Bit 2 */ + byte TCRE :1; /* Timer Counter Reset Enable */ + byte :1; + byte :1; + byte :1; + byte TOI :1; /* Timer Overflow Interrupt Enable */ + } Bits; + struct { + byte grpPR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TSCR2STR; +extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004DUL); +#define TSCR2 _TSCR2.Byte +#define TSCR2_PR0 _TSCR2.Bits.PR0 +#define TSCR2_PR1 _TSCR2.Bits.PR1 +#define TSCR2_PR2 _TSCR2.Bits.PR2 +#define TSCR2_TCRE _TSCR2.Bits.TCRE +#define TSCR2_TOI _TSCR2.Bits.TOI +#define TSCR2_PR _TSCR2.MergedBits.grpPR + +#define TSCR2_PR0_MASK 1U +#define TSCR2_PR1_MASK 2U +#define TSCR2_PR2_MASK 4U +#define TSCR2_TCRE_MASK 8U +#define TSCR2_TOI_MASK 128U +#define TSCR2_PR_MASK 7U +#define TSCR2_PR_BITNUM 0U + + +/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/ +typedef union { + byte Byte; + struct { + byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */ + byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */ + byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */ + byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */ + byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */ + byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */ + byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */ + byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */ + } Bits; +} TFLG1STR; +extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004EUL); +#define TFLG1 _TFLG1.Byte +#define TFLG1_C0F _TFLG1.Bits.C0F +#define TFLG1_C1F _TFLG1.Bits.C1F +#define TFLG1_C2F _TFLG1.Bits.C2F +#define TFLG1_C3F _TFLG1.Bits.C3F +#define TFLG1_C4F _TFLG1.Bits.C4F +#define TFLG1_C5F _TFLG1.Bits.C5F +#define TFLG1_C6F _TFLG1.Bits.C6F +#define TFLG1_C7F _TFLG1.Bits.C7F + +#define TFLG1_C0F_MASK 1U +#define TFLG1_C1F_MASK 2U +#define TFLG1_C2F_MASK 4U +#define TFLG1_C3F_MASK 8U +#define TFLG1_C4F_MASK 16U +#define TFLG1_C5F_MASK 32U +#define TFLG1_C6F_MASK 64U +#define TFLG1_C7F_MASK 128U + + +/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte TOF :1; /* Timer Overflow Flag */ + } Bits; +} TFLG2STR; +extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004FUL); +#define TFLG2 _TFLG2.Byte +#define TFLG2_TOF _TFLG2.Bits.TOF + +#define TFLG2_TOF_MASK 128U + + +/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/ + union { + byte Byte; + } TC0HiSTR; + #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte + + + /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/ + union { + byte Byte; + } TC0LoSTR; + #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte + + } Overlap_STR; + +} TC0STR; +extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050UL); +#define TC0 _TC0.Word +/* TC_ARR: Access 8 TCx registers in an array */ +#define TC_ARR ((volatile word *) &TC0) + + +/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/ + union { + byte Byte; + } TC1HiSTR; + #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte + + + /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/ + union { + byte Byte; + } TC1LoSTR; + #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte + + } Overlap_STR; + +} TC1STR; +extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052UL); +#define TC1 _TC1.Word + + +/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/ + union { + byte Byte; + } TC2HiSTR; + #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte + + + /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/ + union { + byte Byte; + } TC2LoSTR; + #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte + + } Overlap_STR; + +} TC2STR; +extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054UL); +#define TC2 _TC2.Word + + +/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/ + union { + byte Byte; + } TC3HiSTR; + #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte + + + /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/ + union { + byte Byte; + } TC3LoSTR; + #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte + + } Overlap_STR; + +} TC3STR; +extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056UL); +#define TC3 _TC3.Word + + +/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/ + union { + byte Byte; + } TC4HiSTR; + #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte + + + /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/ + union { + byte Byte; + } TC4LoSTR; + #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte + + } Overlap_STR; + +} TC4STR; +extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058UL); +#define TC4 _TC4.Word + + +/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/ + union { + byte Byte; + } TC5HiSTR; + #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte + + + /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/ + union { + byte Byte; + } TC5LoSTR; + #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte + + } Overlap_STR; + +} TC5STR; +extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005AUL); +#define TC5 _TC5.Word + + +/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/ + union { + byte Byte; + } TC6HiSTR; + #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte + + + /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/ + union { + byte Byte; + } TC6LoSTR; + #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte + + } Overlap_STR; + +} TC6STR; +extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005CUL); +#define TC6 _TC6.Word + + +/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/ + union { + byte Byte; + } TC7HiSTR; + #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte + + + /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/ + union { + byte Byte; + } TC7LoSTR; + #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte + + } Overlap_STR; + +} TC7STR; +extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005EUL); +#define TC7 _TC7.Word + + +/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/ +typedef union { + byte Byte; + struct { + byte PAI :1; /* Pulse Accumulator Input Interrupt enable */ + byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */ + byte CLK0 :1; /* Clock Select Bit 0 */ + byte CLK1 :1; /* Clock Select Bit 1 */ + byte PEDGE :1; /* Pulse Accumulator Edge Control */ + byte PAMOD :1; /* Pulse Accumulator Mode */ + byte PAEN :1; /* Pulse Accumulator A System Enable */ + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpCLK :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PACTLSTR; +extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060UL); +#define PACTL _PACTL.Byte +#define PACTL_PAI _PACTL.Bits.PAI +#define PACTL_PAOVI _PACTL.Bits.PAOVI +#define PACTL_CLK0 _PACTL.Bits.CLK0 +#define PACTL_CLK1 _PACTL.Bits.CLK1 +#define PACTL_PEDGE _PACTL.Bits.PEDGE +#define PACTL_PAMOD _PACTL.Bits.PAMOD +#define PACTL_PAEN _PACTL.Bits.PAEN +#define PACTL_CLK _PACTL.MergedBits.grpCLK + +#define PACTL_PAI_MASK 1U +#define PACTL_PAOVI_MASK 2U +#define PACTL_CLK0_MASK 4U +#define PACTL_CLK1_MASK 8U +#define PACTL_PEDGE_MASK 16U +#define PACTL_PAMOD_MASK 32U +#define PACTL_PAEN_MASK 64U +#define PACTL_CLK_MASK 12U +#define PACTL_CLK_BITNUM 2U + + +/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/ +typedef union { + byte Byte; + struct { + byte PAIF :1; /* Pulse Accumulator Input edge Flag */ + byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PAFLGSTR; +extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061UL); +#define PAFLG _PAFLG.Byte +#define PAFLG_PAIF _PAFLG.Bits.PAIF +#define PAFLG_PAOVF _PAFLG.Bits.PAOVF + +#define PAFLG_PAIF_MASK 1U +#define PAFLG_PAOVF_MASK 2U + + +/*** PACN32 - Pulse Accumulators Count 32 Register; 0x00000062 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PACN3 - Pulse Accumulators Count 3 Register; 0x00000062 ***/ + union { + byte Byte; + } PACN3STR; + #define PACN3 _PACN32.Overlap_STR.PACN3STR.Byte + + + /*** PACN2 - Pulse Accumulators Count 2 Register; 0x00000063 ***/ + union { + byte Byte; + } PACN2STR; + #define PACN2 _PACN32.Overlap_STR.PACN2STR.Byte + + } Overlap_STR; + +} PACN32STR; +extern volatile PACN32STR _PACN32 @(REG_BASE + 0x00000062UL); +#define PACN32 _PACN32.Word + + +/*** PACN10 - Pulse Accumulators Count 10 Register; 0x00000064 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PACN1 - Pulse Accumulators Count 1 Register; 0x00000064 ***/ + union { + byte Byte; + } PACN1STR; + #define PACN1 _PACN10.Overlap_STR.PACN1STR.Byte + + + /*** PACN0 - Pulse Accumulators Count 0 Register; 0x00000065 ***/ + union { + byte Byte; + } PACN0STR; + #define PACN0 _PACN10.Overlap_STR.PACN0STR.Byte + + } Overlap_STR; + +} PACN10STR; +extern volatile PACN10STR _PACN10 @(REG_BASE + 0x00000064UL); +#define PACN10 _PACN10.Word + + +/*** MCCTL - Modulus Down Counter underflow; 0x00000066 ***/ +typedef union { + byte Byte; + struct { + byte MCPR0 :1; /* Modulus Counter Prescaler select 0 */ + byte MCPR1 :1; /* Modulus Counter Prescaler select 1 */ + byte MCEN :1; /* Modulus Down-Counter Enable */ + byte FLMC :1; /* Force Load Register into the Modulus Counter Count Register */ + byte ICLAT :1; /* Input Capture Force Latch Action */ + byte RDMCL :1; /* Read Modulus Down-Counter Load */ + byte MODMC :1; /* Modulus Mode Enable */ + byte MCZI :1; /* Modulus Counter Underflow Interrupt Enable */ + } Bits; + struct { + byte grpMCPR :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MCCTLSTR; +extern volatile MCCTLSTR _MCCTL @(REG_BASE + 0x00000066UL); +#define MCCTL _MCCTL.Byte +#define MCCTL_MCPR0 _MCCTL.Bits.MCPR0 +#define MCCTL_MCPR1 _MCCTL.Bits.MCPR1 +#define MCCTL_MCEN _MCCTL.Bits.MCEN +#define MCCTL_FLMC _MCCTL.Bits.FLMC +#define MCCTL_ICLAT _MCCTL.Bits.ICLAT +#define MCCTL_RDMCL _MCCTL.Bits.RDMCL +#define MCCTL_MODMC _MCCTL.Bits.MODMC +#define MCCTL_MCZI _MCCTL.Bits.MCZI +#define MCCTL_MCPR _MCCTL.MergedBits.grpMCPR + +#define MCCTL_MCPR0_MASK 1U +#define MCCTL_MCPR1_MASK 2U +#define MCCTL_MCEN_MASK 4U +#define MCCTL_FLMC_MASK 8U +#define MCCTL_ICLAT_MASK 16U +#define MCCTL_RDMCL_MASK 32U +#define MCCTL_MODMC_MASK 64U +#define MCCTL_MCZI_MASK 128U +#define MCCTL_MCPR_MASK 3U +#define MCCTL_MCPR_BITNUM 0U + + +/*** MCFLG - 16-Bit Modulus Down Counter Flag Register; 0x00000067 ***/ +typedef union { + byte Byte; + struct { + byte POLF0 :1; /* First Input Capture Polarity Status 0 */ + byte POLF1 :1; /* First Input Capture Polarity Status 1 */ + byte POLF2 :1; /* First Input Capture Polarity Status 2 */ + byte POLF3 :1; /* First Input Capture Polarity Status 3 */ + byte :1; + byte :1; + byte :1; + byte MCZF :1; /* Modulus Counter Underflow Flag */ + } Bits; + struct { + byte grpPOLF :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MCFLGSTR; +extern volatile MCFLGSTR _MCFLG @(REG_BASE + 0x00000067UL); +#define MCFLG _MCFLG.Byte +#define MCFLG_POLF0 _MCFLG.Bits.POLF0 +#define MCFLG_POLF1 _MCFLG.Bits.POLF1 +#define MCFLG_POLF2 _MCFLG.Bits.POLF2 +#define MCFLG_POLF3 _MCFLG.Bits.POLF3 +#define MCFLG_MCZF _MCFLG.Bits.MCZF +#define MCFLG_POLF _MCFLG.MergedBits.grpPOLF + +#define MCFLG_POLF0_MASK 1U +#define MCFLG_POLF1_MASK 2U +#define MCFLG_POLF2_MASK 4U +#define MCFLG_POLF3_MASK 8U +#define MCFLG_MCZF_MASK 128U +#define MCFLG_POLF_MASK 15U +#define MCFLG_POLF_BITNUM 0U + + +/*** ICPAR - Input Control Pulse Accumulator Register; 0x00000068 ***/ +typedef union { + byte Byte; + struct { + byte PA0EN :1; /* 8-Bit Pulse Accumulator 0 Enable */ + byte PA1EN :1; /* 8-Bit Pulse Accumulator 1 Enable */ + byte PA2EN :1; /* 8-Bit Pulse Accumulator 2 Enable */ + byte PA3EN :1; /* 8-Bit Pulse Accumulator 3 Enable */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} ICPARSTR; +extern volatile ICPARSTR _ICPAR @(REG_BASE + 0x00000068UL); +#define ICPAR _ICPAR.Byte +#define ICPAR_PA0EN _ICPAR.Bits.PA0EN +#define ICPAR_PA1EN _ICPAR.Bits.PA1EN +#define ICPAR_PA2EN _ICPAR.Bits.PA2EN +#define ICPAR_PA3EN _ICPAR.Bits.PA3EN + +#define ICPAR_PA0EN_MASK 1U +#define ICPAR_PA1EN_MASK 2U +#define ICPAR_PA2EN_MASK 4U +#define ICPAR_PA3EN_MASK 8U + + +/*** DLYCT - Delay Counter Control Register; 0x00000069 ***/ +typedef union { + byte Byte; + struct { + byte DLY0 :1; /* Delay Counter Select 0 */ + byte DLY1 :1; /* Delay Counter Select 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLY :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DLYCTSTR; +extern volatile DLYCTSTR _DLYCT @(REG_BASE + 0x00000069UL); +#define DLYCT _DLYCT.Byte +#define DLYCT_DLY0 _DLYCT.Bits.DLY0 +#define DLYCT_DLY1 _DLYCT.Bits.DLY1 +#define DLYCT_DLY _DLYCT.MergedBits.grpDLY + +#define DLYCT_DLY0_MASK 1U +#define DLYCT_DLY1_MASK 2U +#define DLYCT_DLY_MASK 3U +#define DLYCT_DLY_BITNUM 0U + + +/*** ICOVW - Input Control Overwrite Register; 0x0000006A ***/ +typedef union { + byte Byte; + struct { + byte NOVW0 :1; /* No Input Capture Overwrite 0 */ + byte NOVW1 :1; /* No Input Capture Overwrite 1 */ + byte NOVW2 :1; /* No Input Capture Overwrite 2 */ + byte NOVW3 :1; /* No Input Capture Overwrite 3 */ + byte NOVW4 :1; /* No Input Capture Overwrite 4 */ + byte NOVW5 :1; /* No Input Capture Overwrite 5 */ + byte NOVW6 :1; /* No Input Capture Overwrite 6 */ + byte NOVW7 :1; /* No Input Capture Overwrite 7 */ + } Bits; +} ICOVWSTR; +extern volatile ICOVWSTR _ICOVW @(REG_BASE + 0x0000006AUL); +#define ICOVW _ICOVW.Byte +#define ICOVW_NOVW0 _ICOVW.Bits.NOVW0 +#define ICOVW_NOVW1 _ICOVW.Bits.NOVW1 +#define ICOVW_NOVW2 _ICOVW.Bits.NOVW2 +#define ICOVW_NOVW3 _ICOVW.Bits.NOVW3 +#define ICOVW_NOVW4 _ICOVW.Bits.NOVW4 +#define ICOVW_NOVW5 _ICOVW.Bits.NOVW5 +#define ICOVW_NOVW6 _ICOVW.Bits.NOVW6 +#define ICOVW_NOVW7 _ICOVW.Bits.NOVW7 + +#define ICOVW_NOVW0_MASK 1U +#define ICOVW_NOVW1_MASK 2U +#define ICOVW_NOVW2_MASK 4U +#define ICOVW_NOVW3_MASK 8U +#define ICOVW_NOVW4_MASK 16U +#define ICOVW_NOVW5_MASK 32U +#define ICOVW_NOVW6_MASK 64U +#define ICOVW_NOVW7_MASK 128U + + +/*** ICSYS - Input Control System Control Register; 0x0000006B ***/ +typedef union { + byte Byte; + struct { + byte LATQ :1; /* Input Control Latch or Queue Mode Enable */ + byte BUFEN :1; /* IC Buffer Enable */ + byte PACMX :1; /* 8-Bit Pulse Accumulators Maximum Count */ + byte TFMOD :1; /* Timer Flag-setting Mode */ + byte SH04 :1; /* Share Input action of Input Capture Channels 0 and 4 */ + byte SH15 :1; /* Share Input action of Input Capture Channels 1 and 5 */ + byte SH26 :1; /* Share Input action of Input Capture Channels 2 and 6 */ + byte SH37 :1; /* Share Input action of Input Capture Channels 3 and 7 */ + } Bits; +} ICSYSSTR; +extern volatile ICSYSSTR _ICSYS @(REG_BASE + 0x0000006BUL); +#define ICSYS _ICSYS.Byte +#define ICSYS_LATQ _ICSYS.Bits.LATQ +#define ICSYS_BUFEN _ICSYS.Bits.BUFEN +#define ICSYS_PACMX _ICSYS.Bits.PACMX +#define ICSYS_TFMOD _ICSYS.Bits.TFMOD +#define ICSYS_SH04 _ICSYS.Bits.SH04 +#define ICSYS_SH15 _ICSYS.Bits.SH15 +#define ICSYS_SH26 _ICSYS.Bits.SH26 +#define ICSYS_SH37 _ICSYS.Bits.SH37 + +#define ICSYS_LATQ_MASK 1U +#define ICSYS_BUFEN_MASK 2U +#define ICSYS_PACMX_MASK 4U +#define ICSYS_TFMOD_MASK 8U +#define ICSYS_SH04_MASK 16U +#define ICSYS_SH15_MASK 32U +#define ICSYS_SH26_MASK 64U +#define ICSYS_SH37_MASK 128U + + +/*** PBCTL - 16-Bit Pulse Accumulator B Control Register; 0x00000070 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PBOVI :1; /* Pulse Accumulator B Overflow Interrupt enable */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PBEN :1; /* Pulse Accumulator B System Enable */ + byte :1; + } Bits; +} PBCTLSTR; +extern volatile PBCTLSTR _PBCTL @(REG_BASE + 0x00000070UL); +#define PBCTL _PBCTL.Byte +#define PBCTL_PBOVI _PBCTL.Bits.PBOVI +#define PBCTL_PBEN _PBCTL.Bits.PBEN + +#define PBCTL_PBOVI_MASK 2U +#define PBCTL_PBEN_MASK 64U + + +/*** PBFLG - Pulse Accumulator B Flag Register; 0x00000071 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PBOVF :1; /* Pulse Accumulator B Overflow Flag */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PBFLGSTR; +extern volatile PBFLGSTR _PBFLG @(REG_BASE + 0x00000071UL); +#define PBFLG _PBFLG.Byte +#define PBFLG_PBOVF _PBFLG.Bits.PBOVF + +#define PBFLG_PBOVF_MASK 2U + + +/*** PA32H - 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PA3H - 8-Bit Pulse Accumulators Holding 3 Register; 0x00000072 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + } PA3HSTR; + #define PA3H _PA32H.Overlap_STR.PA3HSTR.Byte + #define PA3H_BIT0 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT0 + #define PA3H_BIT1 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT1 + #define PA3H_BIT2 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT2 + #define PA3H_BIT3 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT3 + #define PA3H_BIT4 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT4 + #define PA3H_BIT5 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT5 + #define PA3H_BIT6 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT6 + #define PA3H_BIT7 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT7 + + #define PA3H_BIT0_MASK 1U + #define PA3H_BIT1_MASK 2U + #define PA3H_BIT2_MASK 4U + #define PA3H_BIT3_MASK 8U + #define PA3H_BIT4_MASK 16U + #define PA3H_BIT5_MASK 32U + #define PA3H_BIT6_MASK 64U + #define PA3H_BIT7_MASK 128U + + + /*** PA2H - 8-Bit Pulse Accumulators Holding 2 Register; 0x00000073 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + } PA2HSTR; + #define PA2H _PA32H.Overlap_STR.PA2HSTR.Byte + #define PA2H_BIT0 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT0 + #define PA2H_BIT1 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT1 + #define PA2H_BIT2 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT2 + #define PA2H_BIT3 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT3 + #define PA2H_BIT4 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT4 + #define PA2H_BIT5 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT5 + #define PA2H_BIT6 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT6 + #define PA2H_BIT7 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT7 + + #define PA2H_BIT0_MASK 1U + #define PA2H_BIT1_MASK 2U + #define PA2H_BIT2_MASK 4U + #define PA2H_BIT3_MASK 8U + #define PA2H_BIT4_MASK 16U + #define PA2H_BIT5_MASK 32U + #define PA2H_BIT6_MASK 64U + #define PA2H_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Pulse Accumulator Bit 0 */ + word BIT1 :1; /* Pulse Accumulator Bit 1 */ + word BIT2 :1; /* Pulse Accumulator Bit 2 */ + word BIT3 :1; /* Pulse Accumulator Bit 3 */ + word BIT4 :1; /* Pulse Accumulator Bit 4 */ + word BIT5 :1; /* Pulse Accumulator Bit 5 */ + word BIT6 :1; /* Pulse Accumulator Bit 6 */ + word BIT7 :1; /* Pulse Accumulator Bit 7 */ + word BIT8 :1; /* Pulse Accumulator Bit 8 */ + word BIT9 :1; /* Pulse Accumulator Bit 9 */ + word BIT10 :1; /* Pulse Accumulator Bit 10 */ + word BIT11 :1; /* Pulse Accumulator Bit 11 */ + word BIT12 :1; /* Pulse Accumulator Bit 12 */ + word BIT13 :1; /* Pulse Accumulator Bit 13 */ + word BIT14 :1; /* Pulse Accumulator Bit 14 */ + word BIT15 :1; /* Pulse Accumulator Bit 15 */ + } Bits; +} PA32HSTR; +extern volatile PA32HSTR _PA32H @(REG_BASE + 0x00000072UL); +#define PA32H _PA32H.Word +#define PA32H_BIT0 _PA32H.Bits.BIT0 +#define PA32H_BIT1 _PA32H.Bits.BIT1 +#define PA32H_BIT2 _PA32H.Bits.BIT2 +#define PA32H_BIT3 _PA32H.Bits.BIT3 +#define PA32H_BIT4 _PA32H.Bits.BIT4 +#define PA32H_BIT5 _PA32H.Bits.BIT5 +#define PA32H_BIT6 _PA32H.Bits.BIT6 +#define PA32H_BIT7 _PA32H.Bits.BIT7 +#define PA32H_BIT8 _PA32H.Bits.BIT8 +#define PA32H_BIT9 _PA32H.Bits.BIT9 +#define PA32H_BIT10 _PA32H.Bits.BIT10 +#define PA32H_BIT11 _PA32H.Bits.BIT11 +#define PA32H_BIT12 _PA32H.Bits.BIT12 +#define PA32H_BIT13 _PA32H.Bits.BIT13 +#define PA32H_BIT14 _PA32H.Bits.BIT14 +#define PA32H_BIT15 _PA32H.Bits.BIT15 + +#define PA32H_BIT0_MASK 1U +#define PA32H_BIT1_MASK 2U +#define PA32H_BIT2_MASK 4U +#define PA32H_BIT3_MASK 8U +#define PA32H_BIT4_MASK 16U +#define PA32H_BIT5_MASK 32U +#define PA32H_BIT6_MASK 64U +#define PA32H_BIT7_MASK 128U +#define PA32H_BIT8_MASK 256U +#define PA32H_BIT9_MASK 512U +#define PA32H_BIT10_MASK 1024U +#define PA32H_BIT11_MASK 2048U +#define PA32H_BIT12_MASK 4096U +#define PA32H_BIT13_MASK 8192U +#define PA32H_BIT14_MASK 16384U +#define PA32H_BIT15_MASK 32768U + + +/*** PA10H - 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PA1H - 8-Bit Pulse Accumulators Holding 1 Register; 0x00000074 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + } PA1HSTR; + #define PA1H _PA10H.Overlap_STR.PA1HSTR.Byte + #define PA1H_BIT0 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT0 + #define PA1H_BIT1 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT1 + #define PA1H_BIT2 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT2 + #define PA1H_BIT3 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT3 + #define PA1H_BIT4 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT4 + #define PA1H_BIT5 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT5 + #define PA1H_BIT6 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT6 + #define PA1H_BIT7 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT7 + + #define PA1H_BIT0_MASK 1U + #define PA1H_BIT1_MASK 2U + #define PA1H_BIT2_MASK 4U + #define PA1H_BIT3_MASK 8U + #define PA1H_BIT4_MASK 16U + #define PA1H_BIT5_MASK 32U + #define PA1H_BIT6_MASK 64U + #define PA1H_BIT7_MASK 128U + + + /*** PA0H - 8-Bit Pulse Accumulators Holding 0 Register; 0x00000075 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + } PA0HSTR; + #define PA0H _PA10H.Overlap_STR.PA0HSTR.Byte + #define PA0H_BIT0 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT0 + #define PA0H_BIT1 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT1 + #define PA0H_BIT2 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT2 + #define PA0H_BIT3 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT3 + #define PA0H_BIT4 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT4 + #define PA0H_BIT5 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT5 + #define PA0H_BIT6 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT6 + #define PA0H_BIT7 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT7 + + #define PA0H_BIT0_MASK 1U + #define PA0H_BIT1_MASK 2U + #define PA0H_BIT2_MASK 4U + #define PA0H_BIT3_MASK 8U + #define PA0H_BIT4_MASK 16U + #define PA0H_BIT5_MASK 32U + #define PA0H_BIT6_MASK 64U + #define PA0H_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Pulse Accumulator Bit 0 */ + word BIT1 :1; /* Pulse Accumulator Bit 1 */ + word BIT2 :1; /* Pulse Accumulator Bit 2 */ + word BIT3 :1; /* Pulse Accumulator Bit 3 */ + word BIT4 :1; /* Pulse Accumulator Bit 4 */ + word BIT5 :1; /* Pulse Accumulator Bit 5 */ + word BIT6 :1; /* Pulse Accumulator Bit 6 */ + word BIT7 :1; /* Pulse Accumulator Bit 7 */ + word BIT8 :1; /* Pulse Accumulator Bit 8 */ + word BIT9 :1; /* Pulse Accumulator Bit 9 */ + word BIT10 :1; /* Pulse Accumulator Bit 10 */ + word BIT11 :1; /* Pulse Accumulator Bit 11 */ + word BIT12 :1; /* Pulse Accumulator Bit 12 */ + word BIT13 :1; /* Pulse Accumulator Bit 13 */ + word BIT14 :1; /* Pulse Accumulator Bit 14 */ + word BIT15 :1; /* Pulse Accumulator Bit 15 */ + } Bits; +} PA10HSTR; +extern volatile PA10HSTR _PA10H @(REG_BASE + 0x00000074UL); +#define PA10H _PA10H.Word +#define PA10H_BIT0 _PA10H.Bits.BIT0 +#define PA10H_BIT1 _PA10H.Bits.BIT1 +#define PA10H_BIT2 _PA10H.Bits.BIT2 +#define PA10H_BIT3 _PA10H.Bits.BIT3 +#define PA10H_BIT4 _PA10H.Bits.BIT4 +#define PA10H_BIT5 _PA10H.Bits.BIT5 +#define PA10H_BIT6 _PA10H.Bits.BIT6 +#define PA10H_BIT7 _PA10H.Bits.BIT7 +#define PA10H_BIT8 _PA10H.Bits.BIT8 +#define PA10H_BIT9 _PA10H.Bits.BIT9 +#define PA10H_BIT10 _PA10H.Bits.BIT10 +#define PA10H_BIT11 _PA10H.Bits.BIT11 +#define PA10H_BIT12 _PA10H.Bits.BIT12 +#define PA10H_BIT13 _PA10H.Bits.BIT13 +#define PA10H_BIT14 _PA10H.Bits.BIT14 +#define PA10H_BIT15 _PA10H.Bits.BIT15 + +#define PA10H_BIT0_MASK 1U +#define PA10H_BIT1_MASK 2U +#define PA10H_BIT2_MASK 4U +#define PA10H_BIT3_MASK 8U +#define PA10H_BIT4_MASK 16U +#define PA10H_BIT5_MASK 32U +#define PA10H_BIT6_MASK 64U +#define PA10H_BIT7_MASK 128U +#define PA10H_BIT8_MASK 256U +#define PA10H_BIT9_MASK 512U +#define PA10H_BIT10_MASK 1024U +#define PA10H_BIT11_MASK 2048U +#define PA10H_BIT12_MASK 4096U +#define PA10H_BIT13_MASK 8192U +#define PA10H_BIT14_MASK 16384U +#define PA10H_BIT15_MASK 32768U + + +/*** MCCNT - Modulus Down-Counter Count Register; 0x00000076 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** MCCNThi - Modulus Down-Counter Count Register High; 0x00000076 ***/ + union { + byte Byte; + } MCCNThiSTR; + #define MCCNThi _MCCNT.Overlap_STR.MCCNThiSTR.Byte + + + /*** MCCNTlo - Modulus Down-Counter Count Register Low; 0x00000077 ***/ + union { + byte Byte; + } MCCNTloSTR; + #define MCCNTlo _MCCNT.Overlap_STR.MCCNTloSTR.Byte + + } Overlap_STR; + +} MCCNTSTR; +extern volatile MCCNTSTR _MCCNT @(REG_BASE + 0x00000076UL); +#define MCCNT _MCCNT.Word + + +/*** TC0H - Timer Input Capture Holding Registers 0; 0x00000078 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC0Hhi - Timer Input Capture Holding Registers 0 High; 0x00000078 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + } TC0HhiSTR; + #define TC0Hhi _TC0H.Overlap_STR.TC0HhiSTR.Byte + #define TC0Hhi_BIT8 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT8 + #define TC0Hhi_BIT9 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT9 + #define TC0Hhi_BIT10 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT10 + #define TC0Hhi_BIT11 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT11 + #define TC0Hhi_BIT12 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT12 + #define TC0Hhi_BIT13 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT13 + #define TC0Hhi_BIT14 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT14 + #define TC0Hhi_BIT15 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT15 + + #define TC0Hhi_BIT8_MASK 1U + #define TC0Hhi_BIT9_MASK 2U + #define TC0Hhi_BIT10_MASK 4U + #define TC0Hhi_BIT11_MASK 8U + #define TC0Hhi_BIT12_MASK 16U + #define TC0Hhi_BIT13_MASK 32U + #define TC0Hhi_BIT14_MASK 64U + #define TC0Hhi_BIT15_MASK 128U + + + /*** TC0Hlo - Timer Input Capture Holding Registers 0 Low; 0x00000079 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + } TC0HloSTR; + #define TC0Hlo _TC0H.Overlap_STR.TC0HloSTR.Byte + #define TC0Hlo_BIT0 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT0 + #define TC0Hlo_BIT1 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT1 + #define TC0Hlo_BIT2 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT2 + #define TC0Hlo_BIT3 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT3 + #define TC0Hlo_BIT4 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT4 + #define TC0Hlo_BIT5 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT5 + #define TC0Hlo_BIT6 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT6 + #define TC0Hlo_BIT7 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT7 + + #define TC0Hlo_BIT0_MASK 1U + #define TC0Hlo_BIT1_MASK 2U + #define TC0Hlo_BIT2_MASK 4U + #define TC0Hlo_BIT3_MASK 8U + #define TC0Hlo_BIT4_MASK 16U + #define TC0Hlo_BIT5_MASK 32U + #define TC0Hlo_BIT6_MASK 64U + #define TC0Hlo_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; +} TC0HSTR; +extern volatile TC0HSTR _TC0H @(REG_BASE + 0x00000078UL); +#define TC0H _TC0H.Word +#define TC0H_BIT0 _TC0H.Bits.BIT0 +#define TC0H_BIT1 _TC0H.Bits.BIT1 +#define TC0H_BIT2 _TC0H.Bits.BIT2 +#define TC0H_BIT3 _TC0H.Bits.BIT3 +#define TC0H_BIT4 _TC0H.Bits.BIT4 +#define TC0H_BIT5 _TC0H.Bits.BIT5 +#define TC0H_BIT6 _TC0H.Bits.BIT6 +#define TC0H_BIT7 _TC0H.Bits.BIT7 +#define TC0H_BIT8 _TC0H.Bits.BIT8 +#define TC0H_BIT9 _TC0H.Bits.BIT9 +#define TC0H_BIT10 _TC0H.Bits.BIT10 +#define TC0H_BIT11 _TC0H.Bits.BIT11 +#define TC0H_BIT12 _TC0H.Bits.BIT12 +#define TC0H_BIT13 _TC0H.Bits.BIT13 +#define TC0H_BIT14 _TC0H.Bits.BIT14 +#define TC0H_BIT15 _TC0H.Bits.BIT15 + +#define TC0H_BIT0_MASK 1U +#define TC0H_BIT1_MASK 2U +#define TC0H_BIT2_MASK 4U +#define TC0H_BIT3_MASK 8U +#define TC0H_BIT4_MASK 16U +#define TC0H_BIT5_MASK 32U +#define TC0H_BIT6_MASK 64U +#define TC0H_BIT7_MASK 128U +#define TC0H_BIT8_MASK 256U +#define TC0H_BIT9_MASK 512U +#define TC0H_BIT10_MASK 1024U +#define TC0H_BIT11_MASK 2048U +#define TC0H_BIT12_MASK 4096U +#define TC0H_BIT13_MASK 8192U +#define TC0H_BIT14_MASK 16384U +#define TC0H_BIT15_MASK 32768U + + +/*** TC1H - Timer Input Capture Holding Registers 1; 0x0000007A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC1Hhi - Timer Input Capture Holding Registers 1 High; 0x0000007A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + } TC1HhiSTR; + #define TC1Hhi _TC1H.Overlap_STR.TC1HhiSTR.Byte + #define TC1Hhi_BIT8 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT8 + #define TC1Hhi_BIT9 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT9 + #define TC1Hhi_BIT10 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT10 + #define TC1Hhi_BIT11 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT11 + #define TC1Hhi_BIT12 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT12 + #define TC1Hhi_BIT13 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT13 + #define TC1Hhi_BIT14 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT14 + #define TC1Hhi_BIT15 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT15 + + #define TC1Hhi_BIT8_MASK 1U + #define TC1Hhi_BIT9_MASK 2U + #define TC1Hhi_BIT10_MASK 4U + #define TC1Hhi_BIT11_MASK 8U + #define TC1Hhi_BIT12_MASK 16U + #define TC1Hhi_BIT13_MASK 32U + #define TC1Hhi_BIT14_MASK 64U + #define TC1Hhi_BIT15_MASK 128U + + + /*** TC1Hlo - Timer Input Capture Holding Registers 1 Low; 0x0000007B ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + } TC1HloSTR; + #define TC1Hlo _TC1H.Overlap_STR.TC1HloSTR.Byte + #define TC1Hlo_BIT0 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT0 + #define TC1Hlo_BIT1 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT1 + #define TC1Hlo_BIT2 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT2 + #define TC1Hlo_BIT3 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT3 + #define TC1Hlo_BIT4 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT4 + #define TC1Hlo_BIT5 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT5 + #define TC1Hlo_BIT6 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT6 + #define TC1Hlo_BIT7 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT7 + + #define TC1Hlo_BIT0_MASK 1U + #define TC1Hlo_BIT1_MASK 2U + #define TC1Hlo_BIT2_MASK 4U + #define TC1Hlo_BIT3_MASK 8U + #define TC1Hlo_BIT4_MASK 16U + #define TC1Hlo_BIT5_MASK 32U + #define TC1Hlo_BIT6_MASK 64U + #define TC1Hlo_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; +} TC1HSTR; +extern volatile TC1HSTR _TC1H @(REG_BASE + 0x0000007AUL); +#define TC1H _TC1H.Word +#define TC1H_BIT0 _TC1H.Bits.BIT0 +#define TC1H_BIT1 _TC1H.Bits.BIT1 +#define TC1H_BIT2 _TC1H.Bits.BIT2 +#define TC1H_BIT3 _TC1H.Bits.BIT3 +#define TC1H_BIT4 _TC1H.Bits.BIT4 +#define TC1H_BIT5 _TC1H.Bits.BIT5 +#define TC1H_BIT6 _TC1H.Bits.BIT6 +#define TC1H_BIT7 _TC1H.Bits.BIT7 +#define TC1H_BIT8 _TC1H.Bits.BIT8 +#define TC1H_BIT9 _TC1H.Bits.BIT9 +#define TC1H_BIT10 _TC1H.Bits.BIT10 +#define TC1H_BIT11 _TC1H.Bits.BIT11 +#define TC1H_BIT12 _TC1H.Bits.BIT12 +#define TC1H_BIT13 _TC1H.Bits.BIT13 +#define TC1H_BIT14 _TC1H.Bits.BIT14 +#define TC1H_BIT15 _TC1H.Bits.BIT15 + +#define TC1H_BIT0_MASK 1U +#define TC1H_BIT1_MASK 2U +#define TC1H_BIT2_MASK 4U +#define TC1H_BIT3_MASK 8U +#define TC1H_BIT4_MASK 16U +#define TC1H_BIT5_MASK 32U +#define TC1H_BIT6_MASK 64U +#define TC1H_BIT7_MASK 128U +#define TC1H_BIT8_MASK 256U +#define TC1H_BIT9_MASK 512U +#define TC1H_BIT10_MASK 1024U +#define TC1H_BIT11_MASK 2048U +#define TC1H_BIT12_MASK 4096U +#define TC1H_BIT13_MASK 8192U +#define TC1H_BIT14_MASK 16384U +#define TC1H_BIT15_MASK 32768U + + +/*** TC2H - Timer Input Capture Holding Registers 2; 0x0000007C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC2Hhi - Timer Input Capture Holding Registers 2 High; 0x0000007C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + } TC2HhiSTR; + #define TC2Hhi _TC2H.Overlap_STR.TC2HhiSTR.Byte + #define TC2Hhi_BIT8 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT8 + #define TC2Hhi_BIT9 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT9 + #define TC2Hhi_BIT10 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT10 + #define TC2Hhi_BIT11 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT11 + #define TC2Hhi_BIT12 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT12 + #define TC2Hhi_BIT13 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT13 + #define TC2Hhi_BIT14 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT14 + #define TC2Hhi_BIT15 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT15 + + #define TC2Hhi_BIT8_MASK 1U + #define TC2Hhi_BIT9_MASK 2U + #define TC2Hhi_BIT10_MASK 4U + #define TC2Hhi_BIT11_MASK 8U + #define TC2Hhi_BIT12_MASK 16U + #define TC2Hhi_BIT13_MASK 32U + #define TC2Hhi_BIT14_MASK 64U + #define TC2Hhi_BIT15_MASK 128U + + + /*** TC2Hlo - Timer Input Capture Holding Registers 2 Low; 0x0000007D ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + } TC2HloSTR; + #define TC2Hlo _TC2H.Overlap_STR.TC2HloSTR.Byte + #define TC2Hlo_BIT0 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT0 + #define TC2Hlo_BIT1 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT1 + #define TC2Hlo_BIT2 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT2 + #define TC2Hlo_BIT3 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT3 + #define TC2Hlo_BIT4 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT4 + #define TC2Hlo_BIT5 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT5 + #define TC2Hlo_BIT6 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT6 + #define TC2Hlo_BIT7 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT7 + + #define TC2Hlo_BIT0_MASK 1U + #define TC2Hlo_BIT1_MASK 2U + #define TC2Hlo_BIT2_MASK 4U + #define TC2Hlo_BIT3_MASK 8U + #define TC2Hlo_BIT4_MASK 16U + #define TC2Hlo_BIT5_MASK 32U + #define TC2Hlo_BIT6_MASK 64U + #define TC2Hlo_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; +} TC2HSTR; +extern volatile TC2HSTR _TC2H @(REG_BASE + 0x0000007CUL); +#define TC2H _TC2H.Word +#define TC2H_BIT0 _TC2H.Bits.BIT0 +#define TC2H_BIT1 _TC2H.Bits.BIT1 +#define TC2H_BIT2 _TC2H.Bits.BIT2 +#define TC2H_BIT3 _TC2H.Bits.BIT3 +#define TC2H_BIT4 _TC2H.Bits.BIT4 +#define TC2H_BIT5 _TC2H.Bits.BIT5 +#define TC2H_BIT6 _TC2H.Bits.BIT6 +#define TC2H_BIT7 _TC2H.Bits.BIT7 +#define TC2H_BIT8 _TC2H.Bits.BIT8 +#define TC2H_BIT9 _TC2H.Bits.BIT9 +#define TC2H_BIT10 _TC2H.Bits.BIT10 +#define TC2H_BIT11 _TC2H.Bits.BIT11 +#define TC2H_BIT12 _TC2H.Bits.BIT12 +#define TC2H_BIT13 _TC2H.Bits.BIT13 +#define TC2H_BIT14 _TC2H.Bits.BIT14 +#define TC2H_BIT15 _TC2H.Bits.BIT15 + +#define TC2H_BIT0_MASK 1U +#define TC2H_BIT1_MASK 2U +#define TC2H_BIT2_MASK 4U +#define TC2H_BIT3_MASK 8U +#define TC2H_BIT4_MASK 16U +#define TC2H_BIT5_MASK 32U +#define TC2H_BIT6_MASK 64U +#define TC2H_BIT7_MASK 128U +#define TC2H_BIT8_MASK 256U +#define TC2H_BIT9_MASK 512U +#define TC2H_BIT10_MASK 1024U +#define TC2H_BIT11_MASK 2048U +#define TC2H_BIT12_MASK 4096U +#define TC2H_BIT13_MASK 8192U +#define TC2H_BIT14_MASK 16384U +#define TC2H_BIT15_MASK 32768U + + +/*** TC3H - Timer Input Capture Holding Registers 3; 0x0000007E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC3Hhi - Timer Input Capture Holding Registers 3 High; 0x0000007E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + } TC3HhiSTR; + #define TC3Hhi _TC3H.Overlap_STR.TC3HhiSTR.Byte + #define TC3Hhi_BIT8 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT8 + #define TC3Hhi_BIT9 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT9 + #define TC3Hhi_BIT10 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT10 + #define TC3Hhi_BIT11 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT11 + #define TC3Hhi_BIT12 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT12 + #define TC3Hhi_BIT13 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT13 + #define TC3Hhi_BIT14 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT14 + #define TC3Hhi_BIT15 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT15 + + #define TC3Hhi_BIT8_MASK 1U + #define TC3Hhi_BIT9_MASK 2U + #define TC3Hhi_BIT10_MASK 4U + #define TC3Hhi_BIT11_MASK 8U + #define TC3Hhi_BIT12_MASK 16U + #define TC3Hhi_BIT13_MASK 32U + #define TC3Hhi_BIT14_MASK 64U + #define TC3Hhi_BIT15_MASK 128U + + + /*** TC3Hlo - Timer Input Capture Holding Registers 3 Low; 0x0000007F ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + } TC3HloSTR; + #define TC3Hlo _TC3H.Overlap_STR.TC3HloSTR.Byte + #define TC3Hlo_BIT0 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT0 + #define TC3Hlo_BIT1 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT1 + #define TC3Hlo_BIT2 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT2 + #define TC3Hlo_BIT3 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT3 + #define TC3Hlo_BIT4 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT4 + #define TC3Hlo_BIT5 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT5 + #define TC3Hlo_BIT6 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT6 + #define TC3Hlo_BIT7 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT7 + + #define TC3Hlo_BIT0_MASK 1U + #define TC3Hlo_BIT1_MASK 2U + #define TC3Hlo_BIT2_MASK 4U + #define TC3Hlo_BIT3_MASK 8U + #define TC3Hlo_BIT4_MASK 16U + #define TC3Hlo_BIT5_MASK 32U + #define TC3Hlo_BIT6_MASK 64U + #define TC3Hlo_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; +} TC3HSTR; +extern volatile TC3HSTR _TC3H @(REG_BASE + 0x0000007EUL); +#define TC3H _TC3H.Word +#define TC3H_BIT0 _TC3H.Bits.BIT0 +#define TC3H_BIT1 _TC3H.Bits.BIT1 +#define TC3H_BIT2 _TC3H.Bits.BIT2 +#define TC3H_BIT3 _TC3H.Bits.BIT3 +#define TC3H_BIT4 _TC3H.Bits.BIT4 +#define TC3H_BIT5 _TC3H.Bits.BIT5 +#define TC3H_BIT6 _TC3H.Bits.BIT6 +#define TC3H_BIT7 _TC3H.Bits.BIT7 +#define TC3H_BIT8 _TC3H.Bits.BIT8 +#define TC3H_BIT9 _TC3H.Bits.BIT9 +#define TC3H_BIT10 _TC3H.Bits.BIT10 +#define TC3H_BIT11 _TC3H.Bits.BIT11 +#define TC3H_BIT12 _TC3H.Bits.BIT12 +#define TC3H_BIT13 _TC3H.Bits.BIT13 +#define TC3H_BIT14 _TC3H.Bits.BIT14 +#define TC3H_BIT15 _TC3H.Bits.BIT15 + +#define TC3H_BIT0_MASK 1U +#define TC3H_BIT1_MASK 2U +#define TC3H_BIT2_MASK 4U +#define TC3H_BIT3_MASK 8U +#define TC3H_BIT4_MASK 16U +#define TC3H_BIT5_MASK 32U +#define TC3H_BIT6_MASK 64U +#define TC3H_BIT7_MASK 128U +#define TC3H_BIT8_MASK 256U +#define TC3H_BIT9_MASK 512U +#define TC3H_BIT10_MASK 1024U +#define TC3H_BIT11_MASK 2048U +#define TC3H_BIT12_MASK 4096U +#define TC3H_BIT13_MASK 8192U +#define TC3H_BIT14_MASK 16384U +#define TC3H_BIT15_MASK 32768U + + +/*** ATD0CTL23 - ATD 0 Control Register 23; 0x00000082 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0CTL2 - ATD 0 Control Register 2; 0x00000082 ***/ + union { + byte Byte; + struct { + byte ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */ + byte ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */ + byte ETRIGE :1; /* External Trigger Mode enable */ + byte ETRIGP :1; /* External Trigger Polarity */ + byte ETRIGLE :1; /* External Trigger Level/Edge control */ + byte AWAI :1; /* ATD Power Down in Wait Mode */ + byte AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ + byte ADPU :1; /* ATD Disable / Power Down */ + } Bits; + } ATD0CTL2STR; + #define ATD0CTL2 _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Byte + #define ATD0CTL2_ASCIF _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIF + #define ATD0CTL2_ASCIE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIE + #define ATD0CTL2_ETRIGE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGE + #define ATD0CTL2_ETRIGP _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGP + #define ATD0CTL2_ETRIGLE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGLE + #define ATD0CTL2_AWAI _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AWAI + #define ATD0CTL2_AFFC _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AFFC + #define ATD0CTL2_ADPU _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ADPU + + #define ATD0CTL2_ASCIF_MASK 1U + #define ATD0CTL2_ASCIE_MASK 2U + #define ATD0CTL2_ETRIGE_MASK 4U + #define ATD0CTL2_ETRIGP_MASK 8U + #define ATD0CTL2_ETRIGLE_MASK 16U + #define ATD0CTL2_AWAI_MASK 32U + #define ATD0CTL2_AFFC_MASK 64U + #define ATD0CTL2_ADPU_MASK 128U + + + /*** ATD0CTL3 - ATD 0 Control Register 3; 0x00000083 ***/ + union { + byte Byte; + struct { + byte FRZ0 :1; /* Background Debug Freeze Enable Bit 0 */ + byte FRZ1 :1; /* Background Debug Freeze Enable Bit 1 */ + byte FIFO :1; /* Result Register FIFO Mode */ + byte S1C :1; /* Conversion Sequence Length 1 */ + byte S2C :1; /* Conversion Sequence Length 2 */ + byte S4C :1; /* Conversion Sequence Length 4 */ + byte S8C :1; /* Conversion Sequence Length 8 */ + byte :1; + } Bits; + struct { + byte grpFRZ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATD0CTL3STR; + #define ATD0CTL3 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Byte + #define ATD0CTL3_FRZ0 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ0 + #define ATD0CTL3_FRZ1 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ1 + #define ATD0CTL3_FIFO _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FIFO + #define ATD0CTL3_S1C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S1C + #define ATD0CTL3_S2C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S2C + #define ATD0CTL3_S4C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S4C + #define ATD0CTL3_S8C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S8C + #define ATD0CTL3_FRZ _ATD0CTL23.Overlap_STR.ATD0CTL3STR.MergedBits.grpFRZ + + #define ATD0CTL3_FRZ0_MASK 1U + #define ATD0CTL3_FRZ1_MASK 2U + #define ATD0CTL3_FIFO_MASK 4U + #define ATD0CTL3_S1C_MASK 8U + #define ATD0CTL3_S2C_MASK 16U + #define ATD0CTL3_S4C_MASK 32U + #define ATD0CTL3_S8C_MASK 64U + #define ATD0CTL3_FRZ_MASK 3U + #define ATD0CTL3_FRZ_BITNUM 0U + + } Overlap_STR; + + struct { + word FRZ0 :1; /* Background Debug Freeze Enable Bit 0 */ + word FRZ1 :1; /* Background Debug Freeze Enable Bit 1 */ + word FIFO :1; /* Result Register FIFO Mode */ + word S1C :1; /* Conversion Sequence Length 1 */ + word S2C :1; /* Conversion Sequence Length 2 */ + word S4C :1; /* Conversion Sequence Length 4 */ + word S8C :1; /* Conversion Sequence Length 8 */ + word :1; + word ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */ + word ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */ + word ETRIGE :1; /* External Trigger Mode enable */ + word ETRIGP :1; /* External Trigger Polarity */ + word ETRIGLE :1; /* External Trigger Level/Edge control */ + word AWAI :1; /* ATD Power Down in Wait Mode */ + word AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ + word ADPU :1; /* ATD Disable / Power Down */ + } Bits; + struct { + word grpFRZ :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} ATD0CTL23STR; +extern volatile ATD0CTL23STR _ATD0CTL23 @(REG_BASE + 0x00000082UL); +#define ATD0CTL23 _ATD0CTL23.Word +#define ATD0CTL23_FRZ0 _ATD0CTL23.Bits.FRZ0 +#define ATD0CTL23_FRZ1 _ATD0CTL23.Bits.FRZ1 +#define ATD0CTL23_FIFO _ATD0CTL23.Bits.FIFO +#define ATD0CTL23_S1C _ATD0CTL23.Bits.S1C +#define ATD0CTL23_S2C _ATD0CTL23.Bits.S2C +#define ATD0CTL23_S4C _ATD0CTL23.Bits.S4C +#define ATD0CTL23_S8C _ATD0CTL23.Bits.S8C +#define ATD0CTL23_ASCIF _ATD0CTL23.Bits.ASCIF +#define ATD0CTL23_ASCIE _ATD0CTL23.Bits.ASCIE +#define ATD0CTL23_ETRIGE _ATD0CTL23.Bits.ETRIGE +#define ATD0CTL23_ETRIGP _ATD0CTL23.Bits.ETRIGP +#define ATD0CTL23_ETRIGLE _ATD0CTL23.Bits.ETRIGLE +#define ATD0CTL23_AWAI _ATD0CTL23.Bits.AWAI +#define ATD0CTL23_AFFC _ATD0CTL23.Bits.AFFC +#define ATD0CTL23_ADPU _ATD0CTL23.Bits.ADPU +#define ATD0CTL23_FRZ _ATD0CTL23.MergedBits.grpFRZ + +#define ATD0CTL23_FRZ0_MASK 1U +#define ATD0CTL23_FRZ1_MASK 2U +#define ATD0CTL23_FIFO_MASK 4U +#define ATD0CTL23_S1C_MASK 8U +#define ATD0CTL23_S2C_MASK 16U +#define ATD0CTL23_S4C_MASK 32U +#define ATD0CTL23_S8C_MASK 64U +#define ATD0CTL23_ASCIF_MASK 256U +#define ATD0CTL23_ASCIE_MASK 512U +#define ATD0CTL23_ETRIGE_MASK 1024U +#define ATD0CTL23_ETRIGP_MASK 2048U +#define ATD0CTL23_ETRIGLE_MASK 4096U +#define ATD0CTL23_AWAI_MASK 8192U +#define ATD0CTL23_AFFC_MASK 16384U +#define ATD0CTL23_ADPU_MASK 32768U +#define ATD0CTL23_FRZ_MASK 3U +#define ATD0CTL23_FRZ_BITNUM 0U + + +/*** ATD0CTL45 - ATD 0 Control Register 45; 0x00000084 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0CTL4 - ATD 0 Control Register 4; 0x00000084 ***/ + union { + byte Byte; + struct { + byte PRS0 :1; /* ATD Clock Prescaler 0 */ + byte PRS1 :1; /* ATD Clock Prescaler 1 */ + byte PRS2 :1; /* ATD Clock Prescaler 2 */ + byte PRS3 :1; /* ATD Clock Prescaler 3 */ + byte PRS4 :1; /* ATD Clock Prescaler 4 */ + byte SMP0 :1; /* Sample Time Select 0 */ + byte SMP1 :1; /* Sample Time Select 1 */ + byte SRES8 :1; /* ATD Resolution Select */ + } Bits; + struct { + byte grpPRS :5; + byte grpSMP :2; + byte grpSRES_8 :1; + } MergedBits; + } ATD0CTL4STR; + #define ATD0CTL4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Byte + #define ATD0CTL4_PRS0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS0 + #define ATD0CTL4_PRS1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS1 + #define ATD0CTL4_PRS2 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS2 + #define ATD0CTL4_PRS3 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS3 + #define ATD0CTL4_PRS4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS4 + #define ATD0CTL4_SMP0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP0 + #define ATD0CTL4_SMP1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP1 + #define ATD0CTL4_SRES8 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SRES8 + #define ATD0CTL4_PRS _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpPRS + #define ATD0CTL4_SMP _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpSMP + + #define ATD0CTL4_PRS0_MASK 1U + #define ATD0CTL4_PRS1_MASK 2U + #define ATD0CTL4_PRS2_MASK 4U + #define ATD0CTL4_PRS3_MASK 8U + #define ATD0CTL4_PRS4_MASK 16U + #define ATD0CTL4_SMP0_MASK 32U + #define ATD0CTL4_SMP1_MASK 64U + #define ATD0CTL4_SRES8_MASK 128U + #define ATD0CTL4_PRS_MASK 31U + #define ATD0CTL4_PRS_BITNUM 0U + #define ATD0CTL4_SMP_MASK 96U + #define ATD0CTL4_SMP_BITNUM 5U + + + /*** ATD0CTL5 - ATD 0 Control Register 5; 0x00000085 ***/ + union { + byte Byte; + struct { + byte CA :1; /* Analog Input Channel Select Code A */ + byte CB :1; /* Analog Input Channel Select Code B */ + byte CC :1; /* Analog Input Channel Select Code C */ + byte :1; + byte MULT :1; /* Multi-Channel Sample Mode */ + byte SCAN :1; /* Continuous Conversion Sequence Mode */ + byte DSGN :1; /* Signed/Unsigned Result Data Mode */ + byte DJM :1; /* Result Register Data Justification Mode */ + } Bits; + struct { + byte grpCx :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATD0CTL5STR; + #define ATD0CTL5 _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Byte + #define ATD0CTL5_CA _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CA + #define ATD0CTL5_CB _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CB + #define ATD0CTL5_CC _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CC + #define ATD0CTL5_MULT _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.MULT + #define ATD0CTL5_SCAN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.SCAN + #define ATD0CTL5_DSGN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DSGN + #define ATD0CTL5_DJM _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DJM + #define ATD0CTL5_Cx _ATD0CTL45.Overlap_STR.ATD0CTL5STR.MergedBits.grpCx + + #define ATD0CTL5_CA_MASK 1U + #define ATD0CTL5_CB_MASK 2U + #define ATD0CTL5_CC_MASK 4U + #define ATD0CTL5_MULT_MASK 16U + #define ATD0CTL5_SCAN_MASK 32U + #define ATD0CTL5_DSGN_MASK 64U + #define ATD0CTL5_DJM_MASK 128U + #define ATD0CTL5_Cx_MASK 7U + #define ATD0CTL5_Cx_BITNUM 0U + + } Overlap_STR; + + struct { + word CA :1; /* Analog Input Channel Select Code A */ + word CB :1; /* Analog Input Channel Select Code B */ + word CC :1; /* Analog Input Channel Select Code C */ + word :1; + word MULT :1; /* Multi-Channel Sample Mode */ + word SCAN :1; /* Continuous Conversion Sequence Mode */ + word DSGN :1; /* Signed/Unsigned Result Data Mode */ + word DJM :1; /* Result Register Data Justification Mode */ + word PRS0 :1; /* ATD Clock Prescaler 0 */ + word PRS1 :1; /* ATD Clock Prescaler 1 */ + word PRS2 :1; /* ATD Clock Prescaler 2 */ + word PRS3 :1; /* ATD Clock Prescaler 3 */ + word PRS4 :1; /* ATD Clock Prescaler 4 */ + word SMP0 :1; /* Sample Time Select 0 */ + word SMP1 :1; /* Sample Time Select 1 */ + word SRES8 :1; /* ATD Resolution Select */ + } Bits; + struct { + word grpCx :3; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpPRS :5; + word grpSMP :2; + word grpSRES_8 :1; + } MergedBits; +} ATD0CTL45STR; +extern volatile ATD0CTL45STR _ATD0CTL45 @(REG_BASE + 0x00000084UL); +#define ATD0CTL45 _ATD0CTL45.Word +#define ATD0CTL45_CA _ATD0CTL45.Bits.CA +#define ATD0CTL45_CB _ATD0CTL45.Bits.CB +#define ATD0CTL45_CC _ATD0CTL45.Bits.CC +#define ATD0CTL45_MULT _ATD0CTL45.Bits.MULT +#define ATD0CTL45_SCAN _ATD0CTL45.Bits.SCAN +#define ATD0CTL45_DSGN _ATD0CTL45.Bits.DSGN +#define ATD0CTL45_DJM _ATD0CTL45.Bits.DJM +#define ATD0CTL45_PRS0 _ATD0CTL45.Bits.PRS0 +#define ATD0CTL45_PRS1 _ATD0CTL45.Bits.PRS1 +#define ATD0CTL45_PRS2 _ATD0CTL45.Bits.PRS2 +#define ATD0CTL45_PRS3 _ATD0CTL45.Bits.PRS3 +#define ATD0CTL45_PRS4 _ATD0CTL45.Bits.PRS4 +#define ATD0CTL45_SMP0 _ATD0CTL45.Bits.SMP0 +#define ATD0CTL45_SMP1 _ATD0CTL45.Bits.SMP1 +#define ATD0CTL45_SRES8 _ATD0CTL45.Bits.SRES8 +#define ATD0CTL45_Cx _ATD0CTL45.MergedBits.grpCx +#define ATD0CTL45_PRS _ATD0CTL45.MergedBits.grpPRS +#define ATD0CTL45_SMP _ATD0CTL45.MergedBits.grpSMP + +#define ATD0CTL45_CA_MASK 1U +#define ATD0CTL45_CB_MASK 2U +#define ATD0CTL45_CC_MASK 4U +#define ATD0CTL45_MULT_MASK 16U +#define ATD0CTL45_SCAN_MASK 32U +#define ATD0CTL45_DSGN_MASK 64U +#define ATD0CTL45_DJM_MASK 128U +#define ATD0CTL45_PRS0_MASK 256U +#define ATD0CTL45_PRS1_MASK 512U +#define ATD0CTL45_PRS2_MASK 1024U +#define ATD0CTL45_PRS3_MASK 2048U +#define ATD0CTL45_PRS4_MASK 4096U +#define ATD0CTL45_SMP0_MASK 8192U +#define ATD0CTL45_SMP1_MASK 16384U +#define ATD0CTL45_SRES8_MASK 32768U +#define ATD0CTL45_Cx_MASK 7U +#define ATD0CTL45_Cx_BITNUM 0U +#define ATD0CTL45_PRS_MASK 7936U +#define ATD0CTL45_PRS_BITNUM 8U +#define ATD0CTL45_SMP_MASK 24576U +#define ATD0CTL45_SMP_BITNUM 13U + + +/*** ATD0STAT0 - ATD 0 Status Register 0; 0x00000086 ***/ +typedef union { + byte Byte; + struct { + byte CC0 :1; /* Conversion Counter 0 */ + byte CC1 :1; /* Conversion Counter 1 */ + byte CC2 :1; /* Conversion Counter 2 */ + byte :1; + byte FIFOR :1; /* FIFO Over Run Flag */ + byte ETORF :1; /* External Trigger Overrun Flag */ + byte :1; + byte SCF :1; /* Sequence Complete Flag */ + } Bits; + struct { + byte grpCC :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ATD0STAT0STR; +extern volatile ATD0STAT0STR _ATD0STAT0 @(REG_BASE + 0x00000086UL); +#define ATD0STAT0 _ATD0STAT0.Byte +#define ATD0STAT0_CC0 _ATD0STAT0.Bits.CC0 +#define ATD0STAT0_CC1 _ATD0STAT0.Bits.CC1 +#define ATD0STAT0_CC2 _ATD0STAT0.Bits.CC2 +#define ATD0STAT0_FIFOR _ATD0STAT0.Bits.FIFOR +#define ATD0STAT0_ETORF _ATD0STAT0.Bits.ETORF +#define ATD0STAT0_SCF _ATD0STAT0.Bits.SCF +#define ATD0STAT0_CC _ATD0STAT0.MergedBits.grpCC + +#define ATD0STAT0_CC0_MASK 1U +#define ATD0STAT0_CC1_MASK 2U +#define ATD0STAT0_CC2_MASK 4U +#define ATD0STAT0_FIFOR_MASK 16U +#define ATD0STAT0_ETORF_MASK 32U +#define ATD0STAT0_SCF_MASK 128U +#define ATD0STAT0_CC_MASK 7U +#define ATD0STAT0_CC_BITNUM 0U + + +/*** ATD0TEST1 - ATD0 Test Register; 0x00000089 ***/ +typedef union { + byte Byte; + struct { + byte SC :1; /* Special Channel Conversion Bit */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} ATD0TEST1STR; +extern volatile ATD0TEST1STR _ATD0TEST1 @(REG_BASE + 0x00000089UL); +#define ATD0TEST1 _ATD0TEST1.Byte +#define ATD0TEST1_SC _ATD0TEST1.Bits.SC + +#define ATD0TEST1_SC_MASK 1U + + +/*** ATD0STAT1 - ATD 0 Status Register 1; 0x0000008B ***/ +typedef union { + byte Byte; + struct { + byte CCF0 :1; /* Conversion Complete Flag 0 */ + byte CCF1 :1; /* Conversion Complete Flag 1 */ + byte CCF2 :1; /* Conversion Complete Flag 2 */ + byte CCF3 :1; /* Conversion Complete Flag 3 */ + byte CCF4 :1; /* Conversion Complete Flag 4 */ + byte CCF5 :1; /* Conversion Complete Flag 5 */ + byte CCF6 :1; /* Conversion Complete Flag 6 */ + byte CCF7 :1; /* Conversion Complete Flag 7 */ + } Bits; +} ATD0STAT1STR; +extern volatile ATD0STAT1STR _ATD0STAT1 @(REG_BASE + 0x0000008BUL); +#define ATD0STAT1 _ATD0STAT1.Byte +#define ATD0STAT1_CCF0 _ATD0STAT1.Bits.CCF0 +#define ATD0STAT1_CCF1 _ATD0STAT1.Bits.CCF1 +#define ATD0STAT1_CCF2 _ATD0STAT1.Bits.CCF2 +#define ATD0STAT1_CCF3 _ATD0STAT1.Bits.CCF3 +#define ATD0STAT1_CCF4 _ATD0STAT1.Bits.CCF4 +#define ATD0STAT1_CCF5 _ATD0STAT1.Bits.CCF5 +#define ATD0STAT1_CCF6 _ATD0STAT1.Bits.CCF6 +#define ATD0STAT1_CCF7 _ATD0STAT1.Bits.CCF7 + +#define ATD0STAT1_CCF0_MASK 1U +#define ATD0STAT1_CCF1_MASK 2U +#define ATD0STAT1_CCF2_MASK 4U +#define ATD0STAT1_CCF3_MASK 8U +#define ATD0STAT1_CCF4_MASK 16U +#define ATD0STAT1_CCF5_MASK 32U +#define ATD0STAT1_CCF6_MASK 64U +#define ATD0STAT1_CCF7_MASK 128U + + +/*** ATD0DIEN - ATD 0 Input Enable Register; 0x0000008D ***/ +typedef union { + byte Byte; + struct { + byte IEN0 :1; /* ATD Digital Input Enable on channel 0 */ + byte IEN1 :1; /* ATD Digital Input Enable on channel 1 */ + byte IEN2 :1; /* ATD Digital Input Enable on channel 2 */ + byte IEN3 :1; /* ATD Digital Input Enable on channel 3 */ + byte IEN4 :1; /* ATD Digital Input Enable on channel 4 */ + byte IEN5 :1; /* ATD Digital Input Enable on channel 5 */ + byte IEN6 :1; /* ATD Digital Input Enable on channel 6 */ + byte IEN7 :1; /* ATD Digital Input Enable on channel 7 */ + } Bits; +} ATD0DIENSTR; +extern volatile ATD0DIENSTR _ATD0DIEN @(REG_BASE + 0x0000008DUL); +#define ATD0DIEN _ATD0DIEN.Byte +#define ATD0DIEN_IEN0 _ATD0DIEN.Bits.IEN0 +#define ATD0DIEN_IEN1 _ATD0DIEN.Bits.IEN1 +#define ATD0DIEN_IEN2 _ATD0DIEN.Bits.IEN2 +#define ATD0DIEN_IEN3 _ATD0DIEN.Bits.IEN3 +#define ATD0DIEN_IEN4 _ATD0DIEN.Bits.IEN4 +#define ATD0DIEN_IEN5 _ATD0DIEN.Bits.IEN5 +#define ATD0DIEN_IEN6 _ATD0DIEN.Bits.IEN6 +#define ATD0DIEN_IEN7 _ATD0DIEN.Bits.IEN7 + +#define ATD0DIEN_IEN0_MASK 1U +#define ATD0DIEN_IEN1_MASK 2U +#define ATD0DIEN_IEN2_MASK 4U +#define ATD0DIEN_IEN3_MASK 8U +#define ATD0DIEN_IEN4_MASK 16U +#define ATD0DIEN_IEN5_MASK 32U +#define ATD0DIEN_IEN6_MASK 64U +#define ATD0DIEN_IEN7_MASK 128U + + +/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/ +typedef union { + byte Byte; + struct { + byte PTAD0 :1; /* A/D Channel 0 (AN0) Digital Input */ + byte PTAD1 :1; /* A/D Channel 1 (AN1) Digital Input */ + byte PTAD2 :1; /* A/D Channel 2 (AN2) Digital Input */ + byte PTAD3 :1; /* A/D Channel 3 (AN3) Digital Input */ + byte PTAD4 :1; /* A/D Channel 4 (AN4) Digital Input */ + byte PTAD5 :1; /* A/D Channel 5 (AN5) Digital Input */ + byte PTAD6 :1; /* A/D Channel 6 (AN6) Digital Input */ + byte PTAD7 :1; /* A/D Channel 7 (AN7) Digital Input */ + } Bits; +} PORTAD0STR; +extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008FUL); +#define PORTAD0 _PORTAD0.Byte +#define PORTAD0_PTAD0 _PORTAD0.Bits.PTAD0 +#define PORTAD0_PTAD1 _PORTAD0.Bits.PTAD1 +#define PORTAD0_PTAD2 _PORTAD0.Bits.PTAD2 +#define PORTAD0_PTAD3 _PORTAD0.Bits.PTAD3 +#define PORTAD0_PTAD4 _PORTAD0.Bits.PTAD4 +#define PORTAD0_PTAD5 _PORTAD0.Bits.PTAD5 +#define PORTAD0_PTAD6 _PORTAD0.Bits.PTAD6 +#define PORTAD0_PTAD7 _PORTAD0.Bits.PTAD7 + +#define PORTAD0_PTAD0_MASK 1U +#define PORTAD0_PTAD1_MASK 2U +#define PORTAD0_PTAD2_MASK 4U +#define PORTAD0_PTAD3_MASK 8U +#define PORTAD0_PTAD4_MASK 16U +#define PORTAD0_PTAD5_MASK 32U +#define PORTAD0_PTAD6_MASK 64U +#define PORTAD0_PTAD7_MASK 128U + + +/*** ATD0DR0 - ATD 0 Conversion Result Register 0; 0x00000090 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR0H - ATD 0 Conversion Result Register 0 High; 0x00000090 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR0HSTR; + #define ATD0DR0H _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Byte + #define ATD0DR0H_BIT8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT8 + #define ATD0DR0H_BIT9 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT9 + #define ATD0DR0H_BIT10 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT10 + #define ATD0DR0H_BIT11 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT11 + #define ATD0DR0H_BIT12 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT12 + #define ATD0DR0H_BIT13 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT13 + #define ATD0DR0H_BIT14 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT14 + #define ATD0DR0H_BIT15 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT15 + + #define ATD0DR0H_BIT8_MASK 1U + #define ATD0DR0H_BIT9_MASK 2U + #define ATD0DR0H_BIT10_MASK 4U + #define ATD0DR0H_BIT11_MASK 8U + #define ATD0DR0H_BIT12_MASK 16U + #define ATD0DR0H_BIT13_MASK 32U + #define ATD0DR0H_BIT14_MASK 64U + #define ATD0DR0H_BIT15_MASK 128U + + + /*** ATD0DR0L - ATD 0 Conversion Result Register 0 Low; 0x00000091 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR0LSTR; + #define ATD0DR0L _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Byte + #define ATD0DR0L_BIT6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT6 + #define ATD0DR0L_BIT7 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT7 + #define ATD0DR0L_BIT_6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.MergedBits.grpBIT_6 + #define ATD0DR0L_BIT ATD0DR0L_BIT_6 + + #define ATD0DR0L_BIT6_MASK 64U + #define ATD0DR0L_BIT7_MASK 128U + #define ATD0DR0L_BIT_6_MASK 192U + #define ATD0DR0L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR0STR; +extern volatile ATD0DR0STR _ATD0DR0 @(REG_BASE + 0x00000090UL); +#define ATD0DR0 _ATD0DR0.Word +#define ATD0DR0_BIT6 _ATD0DR0.Bits.BIT6 +#define ATD0DR0_BIT7 _ATD0DR0.Bits.BIT7 +#define ATD0DR0_BIT8 _ATD0DR0.Bits.BIT8 +#define ATD0DR0_BIT9 _ATD0DR0.Bits.BIT9 +#define ATD0DR0_BIT10 _ATD0DR0.Bits.BIT10 +#define ATD0DR0_BIT11 _ATD0DR0.Bits.BIT11 +#define ATD0DR0_BIT12 _ATD0DR0.Bits.BIT12 +#define ATD0DR0_BIT13 _ATD0DR0.Bits.BIT13 +#define ATD0DR0_BIT14 _ATD0DR0.Bits.BIT14 +#define ATD0DR0_BIT15 _ATD0DR0.Bits.BIT15 +/* ATD0DR_ARR: Access 8 ATD0DRx registers in an array */ +#define ATD0DR_ARR ((volatile word *) &ATD0DR0) +#define ATD0DR0_BIT_6 _ATD0DR0.MergedBits.grpBIT_6 +#define ATD0DR0_BIT ATD0DR0_BIT_6 + +#define ATD0DR0_BIT6_MASK 64U +#define ATD0DR0_BIT7_MASK 128U +#define ATD0DR0_BIT8_MASK 256U +#define ATD0DR0_BIT9_MASK 512U +#define ATD0DR0_BIT10_MASK 1024U +#define ATD0DR0_BIT11_MASK 2048U +#define ATD0DR0_BIT12_MASK 4096U +#define ATD0DR0_BIT13_MASK 8192U +#define ATD0DR0_BIT14_MASK 16384U +#define ATD0DR0_BIT15_MASK 32768U +#define ATD0DR0_BIT_6_MASK 65472U +#define ATD0DR0_BIT_6_BITNUM 6U + + +/*** ATD0DR1 - ATD 0 Conversion Result Register 1; 0x00000092 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR1H - ATD 0 Conversion Result Register 1 High; 0x00000092 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR1HSTR; + #define ATD0DR1H _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Byte + #define ATD0DR1H_BIT8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT8 + #define ATD0DR1H_BIT9 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT9 + #define ATD0DR1H_BIT10 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT10 + #define ATD0DR1H_BIT11 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT11 + #define ATD0DR1H_BIT12 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT12 + #define ATD0DR1H_BIT13 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT13 + #define ATD0DR1H_BIT14 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT14 + #define ATD0DR1H_BIT15 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT15 + + #define ATD0DR1H_BIT8_MASK 1U + #define ATD0DR1H_BIT9_MASK 2U + #define ATD0DR1H_BIT10_MASK 4U + #define ATD0DR1H_BIT11_MASK 8U + #define ATD0DR1H_BIT12_MASK 16U + #define ATD0DR1H_BIT13_MASK 32U + #define ATD0DR1H_BIT14_MASK 64U + #define ATD0DR1H_BIT15_MASK 128U + + + /*** ATD0DR1L - ATD 0 Conversion Result Register 1 Low; 0x00000093 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR1LSTR; + #define ATD0DR1L _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Byte + #define ATD0DR1L_BIT6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT6 + #define ATD0DR1L_BIT7 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT7 + #define ATD0DR1L_BIT_6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.MergedBits.grpBIT_6 + #define ATD0DR1L_BIT ATD0DR1L_BIT_6 + + #define ATD0DR1L_BIT6_MASK 64U + #define ATD0DR1L_BIT7_MASK 128U + #define ATD0DR1L_BIT_6_MASK 192U + #define ATD0DR1L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR1STR; +extern volatile ATD0DR1STR _ATD0DR1 @(REG_BASE + 0x00000092UL); +#define ATD0DR1 _ATD0DR1.Word +#define ATD0DR1_BIT6 _ATD0DR1.Bits.BIT6 +#define ATD0DR1_BIT7 _ATD0DR1.Bits.BIT7 +#define ATD0DR1_BIT8 _ATD0DR1.Bits.BIT8 +#define ATD0DR1_BIT9 _ATD0DR1.Bits.BIT9 +#define ATD0DR1_BIT10 _ATD0DR1.Bits.BIT10 +#define ATD0DR1_BIT11 _ATD0DR1.Bits.BIT11 +#define ATD0DR1_BIT12 _ATD0DR1.Bits.BIT12 +#define ATD0DR1_BIT13 _ATD0DR1.Bits.BIT13 +#define ATD0DR1_BIT14 _ATD0DR1.Bits.BIT14 +#define ATD0DR1_BIT15 _ATD0DR1.Bits.BIT15 +#define ATD0DR1_BIT_6 _ATD0DR1.MergedBits.grpBIT_6 +#define ATD0DR1_BIT ATD0DR1_BIT_6 + +#define ATD0DR1_BIT6_MASK 64U +#define ATD0DR1_BIT7_MASK 128U +#define ATD0DR1_BIT8_MASK 256U +#define ATD0DR1_BIT9_MASK 512U +#define ATD0DR1_BIT10_MASK 1024U +#define ATD0DR1_BIT11_MASK 2048U +#define ATD0DR1_BIT12_MASK 4096U +#define ATD0DR1_BIT13_MASK 8192U +#define ATD0DR1_BIT14_MASK 16384U +#define ATD0DR1_BIT15_MASK 32768U +#define ATD0DR1_BIT_6_MASK 65472U +#define ATD0DR1_BIT_6_BITNUM 6U + + +/*** ATD0DR2 - ATD 0 Conversion Result Register 2; 0x00000094 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR2H - ATD 0 Conversion Result Register 2 High; 0x00000094 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR2HSTR; + #define ATD0DR2H _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Byte + #define ATD0DR2H_BIT8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT8 + #define ATD0DR2H_BIT9 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT9 + #define ATD0DR2H_BIT10 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT10 + #define ATD0DR2H_BIT11 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT11 + #define ATD0DR2H_BIT12 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT12 + #define ATD0DR2H_BIT13 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT13 + #define ATD0DR2H_BIT14 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT14 + #define ATD0DR2H_BIT15 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT15 + + #define ATD0DR2H_BIT8_MASK 1U + #define ATD0DR2H_BIT9_MASK 2U + #define ATD0DR2H_BIT10_MASK 4U + #define ATD0DR2H_BIT11_MASK 8U + #define ATD0DR2H_BIT12_MASK 16U + #define ATD0DR2H_BIT13_MASK 32U + #define ATD0DR2H_BIT14_MASK 64U + #define ATD0DR2H_BIT15_MASK 128U + + + /*** ATD0DR2L - ATD 0 Conversion Result Register 2 Low; 0x00000095 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR2LSTR; + #define ATD0DR2L _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Byte + #define ATD0DR2L_BIT6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT6 + #define ATD0DR2L_BIT7 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT7 + #define ATD0DR2L_BIT_6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.MergedBits.grpBIT_6 + #define ATD0DR2L_BIT ATD0DR2L_BIT_6 + + #define ATD0DR2L_BIT6_MASK 64U + #define ATD0DR2L_BIT7_MASK 128U + #define ATD0DR2L_BIT_6_MASK 192U + #define ATD0DR2L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR2STR; +extern volatile ATD0DR2STR _ATD0DR2 @(REG_BASE + 0x00000094UL); +#define ATD0DR2 _ATD0DR2.Word +#define ATD0DR2_BIT6 _ATD0DR2.Bits.BIT6 +#define ATD0DR2_BIT7 _ATD0DR2.Bits.BIT7 +#define ATD0DR2_BIT8 _ATD0DR2.Bits.BIT8 +#define ATD0DR2_BIT9 _ATD0DR2.Bits.BIT9 +#define ATD0DR2_BIT10 _ATD0DR2.Bits.BIT10 +#define ATD0DR2_BIT11 _ATD0DR2.Bits.BIT11 +#define ATD0DR2_BIT12 _ATD0DR2.Bits.BIT12 +#define ATD0DR2_BIT13 _ATD0DR2.Bits.BIT13 +#define ATD0DR2_BIT14 _ATD0DR2.Bits.BIT14 +#define ATD0DR2_BIT15 _ATD0DR2.Bits.BIT15 +#define ATD0DR2_BIT_6 _ATD0DR2.MergedBits.grpBIT_6 +#define ATD0DR2_BIT ATD0DR2_BIT_6 + +#define ATD0DR2_BIT6_MASK 64U +#define ATD0DR2_BIT7_MASK 128U +#define ATD0DR2_BIT8_MASK 256U +#define ATD0DR2_BIT9_MASK 512U +#define ATD0DR2_BIT10_MASK 1024U +#define ATD0DR2_BIT11_MASK 2048U +#define ATD0DR2_BIT12_MASK 4096U +#define ATD0DR2_BIT13_MASK 8192U +#define ATD0DR2_BIT14_MASK 16384U +#define ATD0DR2_BIT15_MASK 32768U +#define ATD0DR2_BIT_6_MASK 65472U +#define ATD0DR2_BIT_6_BITNUM 6U + + +/*** ATD0DR3 - ATD 0 Conversion Result Register 3; 0x00000096 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR3H - ATD 0 Conversion Result Register 3 High; 0x00000096 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR3HSTR; + #define ATD0DR3H _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Byte + #define ATD0DR3H_BIT8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT8 + #define ATD0DR3H_BIT9 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT9 + #define ATD0DR3H_BIT10 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT10 + #define ATD0DR3H_BIT11 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT11 + #define ATD0DR3H_BIT12 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT12 + #define ATD0DR3H_BIT13 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT13 + #define ATD0DR3H_BIT14 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT14 + #define ATD0DR3H_BIT15 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT15 + + #define ATD0DR3H_BIT8_MASK 1U + #define ATD0DR3H_BIT9_MASK 2U + #define ATD0DR3H_BIT10_MASK 4U + #define ATD0DR3H_BIT11_MASK 8U + #define ATD0DR3H_BIT12_MASK 16U + #define ATD0DR3H_BIT13_MASK 32U + #define ATD0DR3H_BIT14_MASK 64U + #define ATD0DR3H_BIT15_MASK 128U + + + /*** ATD0DR3L - ATD 0 Conversion Result Register 3 Low; 0x00000097 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR3LSTR; + #define ATD0DR3L _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Byte + #define ATD0DR3L_BIT6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT6 + #define ATD0DR3L_BIT7 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT7 + #define ATD0DR3L_BIT_6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.MergedBits.grpBIT_6 + #define ATD0DR3L_BIT ATD0DR3L_BIT_6 + + #define ATD0DR3L_BIT6_MASK 64U + #define ATD0DR3L_BIT7_MASK 128U + #define ATD0DR3L_BIT_6_MASK 192U + #define ATD0DR3L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR3STR; +extern volatile ATD0DR3STR _ATD0DR3 @(REG_BASE + 0x00000096UL); +#define ATD0DR3 _ATD0DR3.Word +#define ATD0DR3_BIT6 _ATD0DR3.Bits.BIT6 +#define ATD0DR3_BIT7 _ATD0DR3.Bits.BIT7 +#define ATD0DR3_BIT8 _ATD0DR3.Bits.BIT8 +#define ATD0DR3_BIT9 _ATD0DR3.Bits.BIT9 +#define ATD0DR3_BIT10 _ATD0DR3.Bits.BIT10 +#define ATD0DR3_BIT11 _ATD0DR3.Bits.BIT11 +#define ATD0DR3_BIT12 _ATD0DR3.Bits.BIT12 +#define ATD0DR3_BIT13 _ATD0DR3.Bits.BIT13 +#define ATD0DR3_BIT14 _ATD0DR3.Bits.BIT14 +#define ATD0DR3_BIT15 _ATD0DR3.Bits.BIT15 +#define ATD0DR3_BIT_6 _ATD0DR3.MergedBits.grpBIT_6 +#define ATD0DR3_BIT ATD0DR3_BIT_6 + +#define ATD0DR3_BIT6_MASK 64U +#define ATD0DR3_BIT7_MASK 128U +#define ATD0DR3_BIT8_MASK 256U +#define ATD0DR3_BIT9_MASK 512U +#define ATD0DR3_BIT10_MASK 1024U +#define ATD0DR3_BIT11_MASK 2048U +#define ATD0DR3_BIT12_MASK 4096U +#define ATD0DR3_BIT13_MASK 8192U +#define ATD0DR3_BIT14_MASK 16384U +#define ATD0DR3_BIT15_MASK 32768U +#define ATD0DR3_BIT_6_MASK 65472U +#define ATD0DR3_BIT_6_BITNUM 6U + + +/*** ATD0DR4 - ATD 0 Conversion Result Register 4; 0x00000098 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR4H - ATD 0 Conversion Result Register 4 High; 0x00000098 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR4HSTR; + #define ATD0DR4H _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Byte + #define ATD0DR4H_BIT8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT8 + #define ATD0DR4H_BIT9 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT9 + #define ATD0DR4H_BIT10 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT10 + #define ATD0DR4H_BIT11 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT11 + #define ATD0DR4H_BIT12 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT12 + #define ATD0DR4H_BIT13 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT13 + #define ATD0DR4H_BIT14 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT14 + #define ATD0DR4H_BIT15 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT15 + + #define ATD0DR4H_BIT8_MASK 1U + #define ATD0DR4H_BIT9_MASK 2U + #define ATD0DR4H_BIT10_MASK 4U + #define ATD0DR4H_BIT11_MASK 8U + #define ATD0DR4H_BIT12_MASK 16U + #define ATD0DR4H_BIT13_MASK 32U + #define ATD0DR4H_BIT14_MASK 64U + #define ATD0DR4H_BIT15_MASK 128U + + + /*** ATD0DR4L - ATD 0 Conversion Result Register 4 Low; 0x00000099 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR4LSTR; + #define ATD0DR4L _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Byte + #define ATD0DR4L_BIT6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT6 + #define ATD0DR4L_BIT7 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT7 + #define ATD0DR4L_BIT_6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.MergedBits.grpBIT_6 + #define ATD0DR4L_BIT ATD0DR4L_BIT_6 + + #define ATD0DR4L_BIT6_MASK 64U + #define ATD0DR4L_BIT7_MASK 128U + #define ATD0DR4L_BIT_6_MASK 192U + #define ATD0DR4L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR4STR; +extern volatile ATD0DR4STR _ATD0DR4 @(REG_BASE + 0x00000098UL); +#define ATD0DR4 _ATD0DR4.Word +#define ATD0DR4_BIT6 _ATD0DR4.Bits.BIT6 +#define ATD0DR4_BIT7 _ATD0DR4.Bits.BIT7 +#define ATD0DR4_BIT8 _ATD0DR4.Bits.BIT8 +#define ATD0DR4_BIT9 _ATD0DR4.Bits.BIT9 +#define ATD0DR4_BIT10 _ATD0DR4.Bits.BIT10 +#define ATD0DR4_BIT11 _ATD0DR4.Bits.BIT11 +#define ATD0DR4_BIT12 _ATD0DR4.Bits.BIT12 +#define ATD0DR4_BIT13 _ATD0DR4.Bits.BIT13 +#define ATD0DR4_BIT14 _ATD0DR4.Bits.BIT14 +#define ATD0DR4_BIT15 _ATD0DR4.Bits.BIT15 +#define ATD0DR4_BIT_6 _ATD0DR4.MergedBits.grpBIT_6 +#define ATD0DR4_BIT ATD0DR4_BIT_6 + +#define ATD0DR4_BIT6_MASK 64U +#define ATD0DR4_BIT7_MASK 128U +#define ATD0DR4_BIT8_MASK 256U +#define ATD0DR4_BIT9_MASK 512U +#define ATD0DR4_BIT10_MASK 1024U +#define ATD0DR4_BIT11_MASK 2048U +#define ATD0DR4_BIT12_MASK 4096U +#define ATD0DR4_BIT13_MASK 8192U +#define ATD0DR4_BIT14_MASK 16384U +#define ATD0DR4_BIT15_MASK 32768U +#define ATD0DR4_BIT_6_MASK 65472U +#define ATD0DR4_BIT_6_BITNUM 6U + + +/*** ATD0DR5 - ATD 0 Conversion Result Register 5; 0x0000009A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR5H - ATD 0 Conversion Result Register 5 High; 0x0000009A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR5HSTR; + #define ATD0DR5H _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Byte + #define ATD0DR5H_BIT8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT8 + #define ATD0DR5H_BIT9 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT9 + #define ATD0DR5H_BIT10 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT10 + #define ATD0DR5H_BIT11 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT11 + #define ATD0DR5H_BIT12 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT12 + #define ATD0DR5H_BIT13 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT13 + #define ATD0DR5H_BIT14 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT14 + #define ATD0DR5H_BIT15 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT15 + + #define ATD0DR5H_BIT8_MASK 1U + #define ATD0DR5H_BIT9_MASK 2U + #define ATD0DR5H_BIT10_MASK 4U + #define ATD0DR5H_BIT11_MASK 8U + #define ATD0DR5H_BIT12_MASK 16U + #define ATD0DR5H_BIT13_MASK 32U + #define ATD0DR5H_BIT14_MASK 64U + #define ATD0DR5H_BIT15_MASK 128U + + + /*** ATD0DR5L - ATD 0 Conversion Result Register 5 Low; 0x0000009B ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR5LSTR; + #define ATD0DR5L _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Byte + #define ATD0DR5L_BIT6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT6 + #define ATD0DR5L_BIT7 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT7 + #define ATD0DR5L_BIT_6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.MergedBits.grpBIT_6 + #define ATD0DR5L_BIT ATD0DR5L_BIT_6 + + #define ATD0DR5L_BIT6_MASK 64U + #define ATD0DR5L_BIT7_MASK 128U + #define ATD0DR5L_BIT_6_MASK 192U + #define ATD0DR5L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR5STR; +extern volatile ATD0DR5STR _ATD0DR5 @(REG_BASE + 0x0000009AUL); +#define ATD0DR5 _ATD0DR5.Word +#define ATD0DR5_BIT6 _ATD0DR5.Bits.BIT6 +#define ATD0DR5_BIT7 _ATD0DR5.Bits.BIT7 +#define ATD0DR5_BIT8 _ATD0DR5.Bits.BIT8 +#define ATD0DR5_BIT9 _ATD0DR5.Bits.BIT9 +#define ATD0DR5_BIT10 _ATD0DR5.Bits.BIT10 +#define ATD0DR5_BIT11 _ATD0DR5.Bits.BIT11 +#define ATD0DR5_BIT12 _ATD0DR5.Bits.BIT12 +#define ATD0DR5_BIT13 _ATD0DR5.Bits.BIT13 +#define ATD0DR5_BIT14 _ATD0DR5.Bits.BIT14 +#define ATD0DR5_BIT15 _ATD0DR5.Bits.BIT15 +#define ATD0DR5_BIT_6 _ATD0DR5.MergedBits.grpBIT_6 +#define ATD0DR5_BIT ATD0DR5_BIT_6 + +#define ATD0DR5_BIT6_MASK 64U +#define ATD0DR5_BIT7_MASK 128U +#define ATD0DR5_BIT8_MASK 256U +#define ATD0DR5_BIT9_MASK 512U +#define ATD0DR5_BIT10_MASK 1024U +#define ATD0DR5_BIT11_MASK 2048U +#define ATD0DR5_BIT12_MASK 4096U +#define ATD0DR5_BIT13_MASK 8192U +#define ATD0DR5_BIT14_MASK 16384U +#define ATD0DR5_BIT15_MASK 32768U +#define ATD0DR5_BIT_6_MASK 65472U +#define ATD0DR5_BIT_6_BITNUM 6U + + +/*** ATD0DR6 - ATD 0 Conversion Result Register 6; 0x0000009C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR6H - ATD 0 Conversion Result Register 6 High; 0x0000009C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR6HSTR; + #define ATD0DR6H _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Byte + #define ATD0DR6H_BIT8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT8 + #define ATD0DR6H_BIT9 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT9 + #define ATD0DR6H_BIT10 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT10 + #define ATD0DR6H_BIT11 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT11 + #define ATD0DR6H_BIT12 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT12 + #define ATD0DR6H_BIT13 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT13 + #define ATD0DR6H_BIT14 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT14 + #define ATD0DR6H_BIT15 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT15 + + #define ATD0DR6H_BIT8_MASK 1U + #define ATD0DR6H_BIT9_MASK 2U + #define ATD0DR6H_BIT10_MASK 4U + #define ATD0DR6H_BIT11_MASK 8U + #define ATD0DR6H_BIT12_MASK 16U + #define ATD0DR6H_BIT13_MASK 32U + #define ATD0DR6H_BIT14_MASK 64U + #define ATD0DR6H_BIT15_MASK 128U + + + /*** ATD0DR6L - ATD 0 Conversion Result Register 6 Low; 0x0000009D ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR6LSTR; + #define ATD0DR6L _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Byte + #define ATD0DR6L_BIT6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT6 + #define ATD0DR6L_BIT7 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT7 + #define ATD0DR6L_BIT_6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.MergedBits.grpBIT_6 + #define ATD0DR6L_BIT ATD0DR6L_BIT_6 + + #define ATD0DR6L_BIT6_MASK 64U + #define ATD0DR6L_BIT7_MASK 128U + #define ATD0DR6L_BIT_6_MASK 192U + #define ATD0DR6L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR6STR; +extern volatile ATD0DR6STR _ATD0DR6 @(REG_BASE + 0x0000009CUL); +#define ATD0DR6 _ATD0DR6.Word +#define ATD0DR6_BIT6 _ATD0DR6.Bits.BIT6 +#define ATD0DR6_BIT7 _ATD0DR6.Bits.BIT7 +#define ATD0DR6_BIT8 _ATD0DR6.Bits.BIT8 +#define ATD0DR6_BIT9 _ATD0DR6.Bits.BIT9 +#define ATD0DR6_BIT10 _ATD0DR6.Bits.BIT10 +#define ATD0DR6_BIT11 _ATD0DR6.Bits.BIT11 +#define ATD0DR6_BIT12 _ATD0DR6.Bits.BIT12 +#define ATD0DR6_BIT13 _ATD0DR6.Bits.BIT13 +#define ATD0DR6_BIT14 _ATD0DR6.Bits.BIT14 +#define ATD0DR6_BIT15 _ATD0DR6.Bits.BIT15 +#define ATD0DR6_BIT_6 _ATD0DR6.MergedBits.grpBIT_6 +#define ATD0DR6_BIT ATD0DR6_BIT_6 + +#define ATD0DR6_BIT6_MASK 64U +#define ATD0DR6_BIT7_MASK 128U +#define ATD0DR6_BIT8_MASK 256U +#define ATD0DR6_BIT9_MASK 512U +#define ATD0DR6_BIT10_MASK 1024U +#define ATD0DR6_BIT11_MASK 2048U +#define ATD0DR6_BIT12_MASK 4096U +#define ATD0DR6_BIT13_MASK 8192U +#define ATD0DR6_BIT14_MASK 16384U +#define ATD0DR6_BIT15_MASK 32768U +#define ATD0DR6_BIT_6_MASK 65472U +#define ATD0DR6_BIT_6_BITNUM 6U + + +/*** ATD0DR7 - ATD 0 Conversion Result Register 7; 0x0000009E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR7H - ATD 0 Conversion Result Register 7 High; 0x0000009E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR7HSTR; + #define ATD0DR7H _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Byte + #define ATD0DR7H_BIT8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT8 + #define ATD0DR7H_BIT9 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT9 + #define ATD0DR7H_BIT10 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT10 + #define ATD0DR7H_BIT11 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT11 + #define ATD0DR7H_BIT12 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT12 + #define ATD0DR7H_BIT13 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT13 + #define ATD0DR7H_BIT14 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT14 + #define ATD0DR7H_BIT15 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT15 + + #define ATD0DR7H_BIT8_MASK 1U + #define ATD0DR7H_BIT9_MASK 2U + #define ATD0DR7H_BIT10_MASK 4U + #define ATD0DR7H_BIT11_MASK 8U + #define ATD0DR7H_BIT12_MASK 16U + #define ATD0DR7H_BIT13_MASK 32U + #define ATD0DR7H_BIT14_MASK 64U + #define ATD0DR7H_BIT15_MASK 128U + + + /*** ATD0DR7L - ATD 0 Conversion Result Register 7 Low; 0x0000009F ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR7LSTR; + #define ATD0DR7L _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Byte + #define ATD0DR7L_BIT6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT6 + #define ATD0DR7L_BIT7 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT7 + #define ATD0DR7L_BIT_6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.MergedBits.grpBIT_6 + #define ATD0DR7L_BIT ATD0DR7L_BIT_6 + + #define ATD0DR7L_BIT6_MASK 64U + #define ATD0DR7L_BIT7_MASK 128U + #define ATD0DR7L_BIT_6_MASK 192U + #define ATD0DR7L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR7STR; +extern volatile ATD0DR7STR _ATD0DR7 @(REG_BASE + 0x0000009EUL); +#define ATD0DR7 _ATD0DR7.Word +#define ATD0DR7_BIT6 _ATD0DR7.Bits.BIT6 +#define ATD0DR7_BIT7 _ATD0DR7.Bits.BIT7 +#define ATD0DR7_BIT8 _ATD0DR7.Bits.BIT8 +#define ATD0DR7_BIT9 _ATD0DR7.Bits.BIT9 +#define ATD0DR7_BIT10 _ATD0DR7.Bits.BIT10 +#define ATD0DR7_BIT11 _ATD0DR7.Bits.BIT11 +#define ATD0DR7_BIT12 _ATD0DR7.Bits.BIT12 +#define ATD0DR7_BIT13 _ATD0DR7.Bits.BIT13 +#define ATD0DR7_BIT14 _ATD0DR7.Bits.BIT14 +#define ATD0DR7_BIT15 _ATD0DR7.Bits.BIT15 +#define ATD0DR7_BIT_6 _ATD0DR7.MergedBits.grpBIT_6 +#define ATD0DR7_BIT ATD0DR7_BIT_6 + +#define ATD0DR7_BIT6_MASK 64U +#define ATD0DR7_BIT7_MASK 128U +#define ATD0DR7_BIT8_MASK 256U +#define ATD0DR7_BIT9_MASK 512U +#define ATD0DR7_BIT10_MASK 1024U +#define ATD0DR7_BIT11_MASK 2048U +#define ATD0DR7_BIT12_MASK 4096U +#define ATD0DR7_BIT13_MASK 8192U +#define ATD0DR7_BIT14_MASK 16384U +#define ATD0DR7_BIT15_MASK 32768U +#define ATD0DR7_BIT_6_MASK 65472U +#define ATD0DR7_BIT_6_BITNUM 6U + + +/*** PWME - PWM Enable Register; 0x000000A0 ***/ +typedef union { + byte Byte; + struct { + byte PWME0 :1; /* Pulse Width Channel 0 Enable */ + byte PWME1 :1; /* Pulse Width Channel 1 Enable */ + byte PWME2 :1; /* Pulse Width Channel 2 Enable */ + byte PWME3 :1; /* Pulse Width Channel 3 Enable */ + byte PWME4 :1; /* Pulse Width Channel 4 Enable */ + byte PWME5 :1; /* Pulse Width Channel 5 Enable */ + byte PWME6 :1; /* Pulse Width Channel 6 Enable */ + byte PWME7 :1; /* Pulse Width Channel 7 Enable */ + } Bits; +} PWMESTR; +extern volatile PWMESTR _PWME @(REG_BASE + 0x000000A0UL); +#define PWME _PWME.Byte +#define PWME_PWME0 _PWME.Bits.PWME0 +#define PWME_PWME1 _PWME.Bits.PWME1 +#define PWME_PWME2 _PWME.Bits.PWME2 +#define PWME_PWME3 _PWME.Bits.PWME3 +#define PWME_PWME4 _PWME.Bits.PWME4 +#define PWME_PWME5 _PWME.Bits.PWME5 +#define PWME_PWME6 _PWME.Bits.PWME6 +#define PWME_PWME7 _PWME.Bits.PWME7 + +#define PWME_PWME0_MASK 1U +#define PWME_PWME1_MASK 2U +#define PWME_PWME2_MASK 4U +#define PWME_PWME3_MASK 8U +#define PWME_PWME4_MASK 16U +#define PWME_PWME5_MASK 32U +#define PWME_PWME6_MASK 64U +#define PWME_PWME7_MASK 128U + + +/*** PWMPOL - PWM Polarity Register; 0x000000A1 ***/ +typedef union { + byte Byte; + struct { + byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */ + byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */ + byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */ + byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */ + byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */ + byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */ + byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */ + byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */ + } Bits; +} PWMPOLSTR; +extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000A1UL); +#define PWMPOL _PWMPOL.Byte +#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0 +#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1 +#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2 +#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3 +#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4 +#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5 +#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6 +#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7 + +#define PWMPOL_PPOL0_MASK 1U +#define PWMPOL_PPOL1_MASK 2U +#define PWMPOL_PPOL2_MASK 4U +#define PWMPOL_PPOL3_MASK 8U +#define PWMPOL_PPOL4_MASK 16U +#define PWMPOL_PPOL5_MASK 32U +#define PWMPOL_PPOL6_MASK 64U +#define PWMPOL_PPOL7_MASK 128U + + +/*** PWMCLK - PWM Clock Select Register; 0x000000A2 ***/ +typedef union { + byte Byte; + struct { + byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */ + byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */ + byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */ + byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */ + byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */ + byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */ + byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */ + byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */ + } Bits; +} PWMCLKSTR; +extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000A2UL); +#define PWMCLK _PWMCLK.Byte +#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0 +#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1 +#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2 +#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3 +#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4 +#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5 +#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6 +#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7 + +#define PWMCLK_PCLK0_MASK 1U +#define PWMCLK_PCLK1_MASK 2U +#define PWMCLK_PCLK2_MASK 4U +#define PWMCLK_PCLK3_MASK 8U +#define PWMCLK_PCLK4_MASK 16U +#define PWMCLK_PCLK5_MASK 32U +#define PWMCLK_PCLK6_MASK 64U +#define PWMCLK_PCLK7_MASK 128U + + +/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000A3 ***/ +typedef union { + byte Byte; + struct { + byte PCKA0 :1; /* Prescaler Select for Clock A 0 */ + byte PCKA1 :1; /* Prescaler Select for Clock A 1 */ + byte PCKA2 :1; /* Prescaler Select for Clock A 2 */ + byte :1; + byte PCKB0 :1; /* Prescaler Select for Clock B 0 */ + byte PCKB1 :1; /* Prescaler Select for Clock B 1 */ + byte PCKB2 :1; /* Prescaler Select for Clock B 2 */ + byte :1; + } Bits; + struct { + byte grpPCKA :3; + byte :1; + byte grpPCKB :3; + byte :1; + } MergedBits; +} PWMPRCLKSTR; +extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000A3UL); +#define PWMPRCLK _PWMPRCLK.Byte +#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0 +#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1 +#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2 +#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0 +#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1 +#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2 +#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA +#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB + +#define PWMPRCLK_PCKA0_MASK 1U +#define PWMPRCLK_PCKA1_MASK 2U +#define PWMPRCLK_PCKA2_MASK 4U +#define PWMPRCLK_PCKB0_MASK 16U +#define PWMPRCLK_PCKB1_MASK 32U +#define PWMPRCLK_PCKB2_MASK 64U +#define PWMPRCLK_PCKA_MASK 7U +#define PWMPRCLK_PCKA_BITNUM 0U +#define PWMPRCLK_PCKB_MASK 112U +#define PWMPRCLK_PCKB_BITNUM 4U + + +/*** PWMCAE - PWM Center Align Enable Register; 0x000000A4 ***/ +typedef union { + byte Byte; + struct { + byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */ + byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */ + byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */ + byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */ + byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */ + byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */ + byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */ + byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */ + } Bits; +} PWMCAESTR; +extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000A4UL); +#define PWMCAE _PWMCAE.Byte +#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0 +#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1 +#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2 +#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3 +#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4 +#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5 +#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6 +#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7 + +#define PWMCAE_CAE0_MASK 1U +#define PWMCAE_CAE1_MASK 2U +#define PWMCAE_CAE2_MASK 4U +#define PWMCAE_CAE3_MASK 8U +#define PWMCAE_CAE4_MASK 16U +#define PWMCAE_CAE5_MASK 32U +#define PWMCAE_CAE6_MASK 64U +#define PWMCAE_CAE7_MASK 128U + + +/*** PWMCTL - PWM Control Register; 0x000000A5 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */ + byte PSWAI :1; /* PWM Stops in Wait Mode */ + byte CON01 :1; /* Concatenate channels 0 and 1 */ + byte CON23 :1; /* Concatenate channels 2 and 3 */ + byte CON45 :1; /* Concatenate channels 4 and 5 */ + byte CON67 :1; /* Concatenate channels 6 and 7 */ + } Bits; +} PWMCTLSTR; +extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000A5UL); +#define PWMCTL _PWMCTL.Byte +#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ +#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI +#define PWMCTL_CON01 _PWMCTL.Bits.CON01 +#define PWMCTL_CON23 _PWMCTL.Bits.CON23 +#define PWMCTL_CON45 _PWMCTL.Bits.CON45 +#define PWMCTL_CON67 _PWMCTL.Bits.CON67 + +#define PWMCTL_PFRZ_MASK 4U +#define PWMCTL_PSWAI_MASK 8U +#define PWMCTL_CON01_MASK 16U +#define PWMCTL_CON23_MASK 32U +#define PWMCTL_CON45_MASK 64U +#define PWMCTL_CON67_MASK 128U + + +/*** PWMSCLA - PWM Scale A Register; 0x000000A8 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale A Bit 0 */ + byte BIT1 :1; /* PWM Scale A Bit 1 */ + byte BIT2 :1; /* PWM Scale A Bit 2 */ + byte BIT3 :1; /* PWM Scale A Bit 3 */ + byte BIT4 :1; /* PWM Scale A Bit 4 */ + byte BIT5 :1; /* PWM Scale A Bit 5 */ + byte BIT6 :1; /* PWM Scale A Bit 6 */ + byte BIT7 :1; /* PWM Scale A Bit 7 */ + } Bits; +} PWMSCLASTR; +extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000A8UL); +#define PWMSCLA _PWMSCLA.Byte +#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0 +#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1 +#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2 +#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3 +#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4 +#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5 +#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6 +#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7 + +#define PWMSCLA_BIT0_MASK 1U +#define PWMSCLA_BIT1_MASK 2U +#define PWMSCLA_BIT2_MASK 4U +#define PWMSCLA_BIT3_MASK 8U +#define PWMSCLA_BIT4_MASK 16U +#define PWMSCLA_BIT5_MASK 32U +#define PWMSCLA_BIT6_MASK 64U +#define PWMSCLA_BIT7_MASK 128U + + +/*** PWMSCLB - PWM Scale B Register; 0x000000A9 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale B Bit 0 */ + byte BIT1 :1; /* PWM Scale B Bit 1 */ + byte BIT2 :1; /* PWM Scale B Bit 2 */ + byte BIT3 :1; /* PWM Scale B Bit 3 */ + byte BIT4 :1; /* PWM Scale B Bit 4 */ + byte BIT5 :1; /* PWM Scale B Bit 5 */ + byte BIT6 :1; /* PWM Scale B Bit 6 */ + byte BIT7 :1; /* PWM Scale B Bit 7 */ + } Bits; +} PWMSCLBSTR; +extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000A9UL); +#define PWMSCLB _PWMSCLB.Byte +#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0 +#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1 +#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2 +#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3 +#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4 +#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5 +#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6 +#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7 + +#define PWMSCLB_BIT0_MASK 1U +#define PWMSCLB_BIT1_MASK 2U +#define PWMSCLB_BIT2_MASK 4U +#define PWMSCLB_BIT3_MASK 8U +#define PWMSCLB_BIT4_MASK 16U +#define PWMSCLB_BIT5_MASK 32U +#define PWMSCLB_BIT6_MASK 64U +#define PWMSCLB_BIT7_MASK 128U + + +/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000AC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000AC ***/ + union { + byte Byte; + } PWMCNT0STR; + #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte + /* PWMCNT_ARR: Access 8 PWMCNTx registers in an array */ + #define PWMCNT_ARR ((volatile byte *) &PWMCNT0) + + + /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000AD ***/ + union { + byte Byte; + } PWMCNT1STR; + #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte + + } Overlap_STR; + +} PWMCNT01STR; +extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000ACUL); +#define PWMCNT01 _PWMCNT01.Word + + +/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000AE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000AE ***/ + union { + byte Byte; + } PWMCNT2STR; + #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte + + + /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000AF ***/ + union { + byte Byte; + } PWMCNT3STR; + #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte + + } Overlap_STR; + +} PWMCNT23STR; +extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000AEUL); +#define PWMCNT23 _PWMCNT23.Word + + +/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000B0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000B0 ***/ + union { + byte Byte; + } PWMCNT4STR; + #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte + + + /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000B1 ***/ + union { + byte Byte; + } PWMCNT5STR; + #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte + + } Overlap_STR; + +} PWMCNT45STR; +extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000B0UL); +#define PWMCNT45 _PWMCNT45.Word + + +/*** PWMCNT67 - PWM Channel Counter 67 Register; 0x000000B2 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT6 - PWM Channel Counter 6 Register; 0x000000B2 ***/ + union { + byte Byte; + } PWMCNT6STR; + #define PWMCNT6 _PWMCNT67.Overlap_STR.PWMCNT6STR.Byte + + + /*** PWMCNT7 - PWM Channel Counter 7 Register; 0x000000B3 ***/ + union { + byte Byte; + } PWMCNT7STR; + #define PWMCNT7 _PWMCNT67.Overlap_STR.PWMCNT7STR.Byte + + } Overlap_STR; + +} PWMCNT67STR; +extern volatile PWMCNT67STR _PWMCNT67 @(REG_BASE + 0x000000B2UL); +#define PWMCNT67 _PWMCNT67.Word + + +/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000B4 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000B4 ***/ + union { + byte Byte; + } PWMPER0STR; + #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte + /* PWMPER_ARR: Access 8 PWMPERx registers in an array */ + #define PWMPER_ARR ((volatile byte *) &PWMPER0) + + + /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000B5 ***/ + union { + byte Byte; + } PWMPER1STR; + #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte + + } Overlap_STR; + +} PWMPER01STR; +extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000B4UL); +#define PWMPER01 _PWMPER01.Word + + +/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000B6 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000B6 ***/ + union { + byte Byte; + } PWMPER2STR; + #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte + + + /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000B7 ***/ + union { + byte Byte; + } PWMPER3STR; + #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte + + } Overlap_STR; + +} PWMPER23STR; +extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000B6UL); +#define PWMPER23 _PWMPER23.Word + + +/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000B8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000B8 ***/ + union { + byte Byte; + } PWMPER4STR; + #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte + + + /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000B9 ***/ + union { + byte Byte; + } PWMPER5STR; + #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte + + } Overlap_STR; + +} PWMPER45STR; +extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000B8UL); +#define PWMPER45 _PWMPER45.Word + + +/*** PWMPER67 - PWM Channel Period 67 Register; 0x000000BA ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER6 - PWM Channel Period 6 Register; 0x000000BA ***/ + union { + byte Byte; + } PWMPER6STR; + #define PWMPER6 _PWMPER67.Overlap_STR.PWMPER6STR.Byte + + + /*** PWMPER7 - PWM Channel Period 7 Register; 0x000000BB ***/ + union { + byte Byte; + } PWMPER7STR; + #define PWMPER7 _PWMPER67.Overlap_STR.PWMPER7STR.Byte + + } Overlap_STR; + +} PWMPER67STR; +extern volatile PWMPER67STR _PWMPER67 @(REG_BASE + 0x000000BAUL); +#define PWMPER67 _PWMPER67.Word + + +/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000BC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000BC ***/ + union { + byte Byte; + } PWMDTY0STR; + #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte + /* PWMDTY_ARR: Access 8 PWMDTYx registers in an array */ + #define PWMDTY_ARR ((volatile byte *) &PWMDTY0) + + + /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000BD ***/ + union { + byte Byte; + } PWMDTY1STR; + #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte + + } Overlap_STR; + +} PWMDTY01STR; +extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000BCUL); +#define PWMDTY01 _PWMDTY01.Word + + +/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000BE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000BE ***/ + union { + byte Byte; + } PWMDTY2STR; + #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte + + + /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000BF ***/ + union { + byte Byte; + } PWMDTY3STR; + #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte + + } Overlap_STR; + +} PWMDTY23STR; +extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000BEUL); +#define PWMDTY23 _PWMDTY23.Word + + +/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000C0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000C0 ***/ + union { + byte Byte; + } PWMDTY4STR; + #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte + + + /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000C1 ***/ + union { + byte Byte; + } PWMDTY5STR; + #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte + + } Overlap_STR; + +} PWMDTY45STR; +extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000C0UL); +#define PWMDTY45 _PWMDTY45.Word + + +/*** PWMDTY67 - PWM Channel Duty 67 Register; 0x000000C2 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY6 - PWM Channel Duty 6 Register; 0x000000C2 ***/ + union { + byte Byte; + } PWMDTY6STR; + #define PWMDTY6 _PWMDTY67.Overlap_STR.PWMDTY6STR.Byte + + + /*** PWMDTY7 - PWM Channel Duty 7 Register; 0x000000C3 ***/ + union { + byte Byte; + } PWMDTY7STR; + #define PWMDTY7 _PWMDTY67.Overlap_STR.PWMDTY7STR.Byte + + } Overlap_STR; + +} PWMDTY67STR; +extern volatile PWMDTY67STR _PWMDTY67 @(REG_BASE + 0x000000C2UL); +#define PWMDTY67 _PWMDTY67.Word + + +/*** PWMSDN - PWM Shutdown Register; 0x000000C4 ***/ +typedef union { + byte Byte; + struct { + byte PWM7ENA :1; /* PWM emergency shutdown Enable */ + byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */ + byte PWM7IN :1; /* PWM channel 7 input status */ + byte :1; + byte PWMLVL :1; /* PWM shutdown output Level */ + byte PWMRSTRT :1; /* PWM Restart */ + byte PWMIE :1; /* PWM Interrupt Enable */ + byte PWMIF :1; /* PWM Interrupt Flag */ + } Bits; +} PWMSDNSTR; +extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000C4UL); +#define PWMSDN _PWMSDN.Byte +#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA +#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL +#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN +#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL +#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT +#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE +#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF + +#define PWMSDN_PWM7ENA_MASK 1U +#define PWMSDN_PWM7INL_MASK 2U +#define PWMSDN_PWM7IN_MASK 4U +#define PWMSDN_PWMLVL_MASK 16U +#define PWMSDN_PWMRSTRT_MASK 32U +#define PWMSDN_PWMIE_MASK 64U +#define PWMSDN_PWMIF_MASK 128U + + +/*** SCI0BD - SCI 0 Baud Rate Register; 0x000000C8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SCI0BDH - SCI 0 Baud Rate Register High; 0x000000C8 ***/ + union { + byte Byte; + struct { + byte SBR8 :1; /* SCI Baud Rate Bit 8 */ + byte SBR9 :1; /* SCI Baud Rate Bit 9 */ + byte SBR10 :1; /* SCI Baud Rate Bit 10 */ + byte SBR11 :1; /* SCI Baud Rate Bit 11 */ + byte SBR12 :1; /* SCI Baud Rate Bit 12 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpSBR_8 :5; + byte :1; + byte :1; + byte :1; + } MergedBits; + } SCI0BDHSTR; + #define SCI0BDH _SCI0BD.Overlap_STR.SCI0BDHSTR.Byte + #define SCI0BDH_SBR8 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR8 + #define SCI0BDH_SBR9 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR9 + #define SCI0BDH_SBR10 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR10 + #define SCI0BDH_SBR11 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR11 + #define SCI0BDH_SBR12 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR12 + #define SCI0BDH_SBR_8 _SCI0BD.Overlap_STR.SCI0BDHSTR.MergedBits.grpSBR_8 + #define SCI0BDH_SBR SCI0BDH_SBR_8 + + #define SCI0BDH_SBR8_MASK 1U + #define SCI0BDH_SBR9_MASK 2U + #define SCI0BDH_SBR10_MASK 4U + #define SCI0BDH_SBR11_MASK 8U + #define SCI0BDH_SBR12_MASK 16U + #define SCI0BDH_SBR_8_MASK 31U + #define SCI0BDH_SBR_8_BITNUM 0U + + + /*** SCI0BDL - SCI 0 Baud Rate Register Low; 0x000000C9 ***/ + union { + byte Byte; + struct { + byte SBR0 :1; /* SCI Baud Rate Bit 0 */ + byte SBR1 :1; /* SCI Baud Rate Bit 1 */ + byte SBR2 :1; /* SCI Baud Rate Bit 2 */ + byte SBR3 :1; /* SCI Baud Rate Bit 3 */ + byte SBR4 :1; /* SCI Baud Rate Bit 4 */ + byte SBR5 :1; /* SCI Baud Rate Bit 5 */ + byte SBR6 :1; /* SCI Baud Rate Bit 6 */ + byte SBR7 :1; /* SCI Baud Rate Bit 7 */ + } Bits; + } SCI0BDLSTR; + #define SCI0BDL _SCI0BD.Overlap_STR.SCI0BDLSTR.Byte + #define SCI0BDL_SBR0 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR0 + #define SCI0BDL_SBR1 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR1 + #define SCI0BDL_SBR2 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR2 + #define SCI0BDL_SBR3 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR3 + #define SCI0BDL_SBR4 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR4 + #define SCI0BDL_SBR5 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR5 + #define SCI0BDL_SBR6 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR6 + #define SCI0BDL_SBR7 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR7 + + #define SCI0BDL_SBR0_MASK 1U + #define SCI0BDL_SBR1_MASK 2U + #define SCI0BDL_SBR2_MASK 4U + #define SCI0BDL_SBR3_MASK 8U + #define SCI0BDL_SBR4_MASK 16U + #define SCI0BDL_SBR5_MASK 32U + #define SCI0BDL_SBR6_MASK 64U + #define SCI0BDL_SBR7_MASK 128U + + } Overlap_STR; + + struct { + word SBR0 :1; /* SCI Baud Rate Bit 0 */ + word SBR1 :1; /* SCI Baud Rate Bit 1 */ + word SBR2 :1; /* SCI Baud Rate Bit 2 */ + word SBR3 :1; /* SCI Baud Rate Bit 3 */ + word SBR4 :1; /* SCI Baud Rate Bit 4 */ + word SBR5 :1; /* SCI Baud Rate Bit 5 */ + word SBR6 :1; /* SCI Baud Rate Bit 6 */ + word SBR7 :1; /* SCI Baud Rate Bit 7 */ + word SBR8 :1; /* SCI Baud Rate Bit 8 */ + word SBR9 :1; /* SCI Baud Rate Bit 9 */ + word SBR10 :1; /* SCI Baud Rate Bit 10 */ + word SBR11 :1; /* SCI Baud Rate Bit 11 */ + word SBR12 :1; /* SCI Baud Rate Bit 12 */ + word :1; + word :1; + word :1; + } Bits; + struct { + word grpSBR :13; + word :1; + word :1; + word :1; + } MergedBits; +} SCI0BDSTR; +extern volatile SCI0BDSTR _SCI0BD @(REG_BASE + 0x000000C8UL); +#define SCI0BD _SCI0BD.Word +#define SCI0BD_SBR0 _SCI0BD.Bits.SBR0 +#define SCI0BD_SBR1 _SCI0BD.Bits.SBR1 +#define SCI0BD_SBR2 _SCI0BD.Bits.SBR2 +#define SCI0BD_SBR3 _SCI0BD.Bits.SBR3 +#define SCI0BD_SBR4 _SCI0BD.Bits.SBR4 +#define SCI0BD_SBR5 _SCI0BD.Bits.SBR5 +#define SCI0BD_SBR6 _SCI0BD.Bits.SBR6 +#define SCI0BD_SBR7 _SCI0BD.Bits.SBR7 +#define SCI0BD_SBR8 _SCI0BD.Bits.SBR8 +#define SCI0BD_SBR9 _SCI0BD.Bits.SBR9 +#define SCI0BD_SBR10 _SCI0BD.Bits.SBR10 +#define SCI0BD_SBR11 _SCI0BD.Bits.SBR11 +#define SCI0BD_SBR12 _SCI0BD.Bits.SBR12 +#define SCI0BD_SBR _SCI0BD.MergedBits.grpSBR + +#define SCI0BD_SBR0_MASK 1U +#define SCI0BD_SBR1_MASK 2U +#define SCI0BD_SBR2_MASK 4U +#define SCI0BD_SBR3_MASK 8U +#define SCI0BD_SBR4_MASK 16U +#define SCI0BD_SBR5_MASK 32U +#define SCI0BD_SBR6_MASK 64U +#define SCI0BD_SBR7_MASK 128U +#define SCI0BD_SBR8_MASK 256U +#define SCI0BD_SBR9_MASK 512U +#define SCI0BD_SBR10_MASK 1024U +#define SCI0BD_SBR11_MASK 2048U +#define SCI0BD_SBR12_MASK 4096U +#define SCI0BD_SBR_MASK 8191U +#define SCI0BD_SBR_BITNUM 0U + + +/*** SCI0CR1 - SCI 0 Control Register 1; 0x000000CA ***/ +typedef union { + byte Byte; + struct { + byte PT :1; /* Parity Type Bit */ + byte PE :1; /* Parity Enable Bit */ + byte ILT :1; /* Idle Line Type Bit */ + byte WAKE :1; /* Wakeup Condition Bit */ + byte M :1; /* Data Format Mode Bit */ + byte RSRC :1; /* Receiver Source Bit */ + byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */ + byte LOOPS :1; /* Loop Select Bit */ + } Bits; +} SCI0CR1STR; +extern volatile SCI0CR1STR _SCI0CR1 @(REG_BASE + 0x000000CAUL); +#define SCI0CR1 _SCI0CR1.Byte +#define SCI0CR1_PT _SCI0CR1.Bits.PT +#define SCI0CR1_PE _SCI0CR1.Bits.PE +#define SCI0CR1_ILT _SCI0CR1.Bits.ILT +#define SCI0CR1_WAKE _SCI0CR1.Bits.WAKE +#define SCI0CR1_M _SCI0CR1.Bits.M +#define SCI0CR1_RSRC _SCI0CR1.Bits.RSRC +#define SCI0CR1_SCISWAI _SCI0CR1.Bits.SCISWAI +#define SCI0CR1_LOOPS _SCI0CR1.Bits.LOOPS + +#define SCI0CR1_PT_MASK 1U +#define SCI0CR1_PE_MASK 2U +#define SCI0CR1_ILT_MASK 4U +#define SCI0CR1_WAKE_MASK 8U +#define SCI0CR1_M_MASK 16U +#define SCI0CR1_RSRC_MASK 32U +#define SCI0CR1_SCISWAI_MASK 64U +#define SCI0CR1_LOOPS_MASK 128U + + +/*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB ***/ +typedef union { + byte Byte; + struct { + byte SBK :1; /* Send Break Bit */ + byte RWU :1; /* Receiver Wakeup Bit */ + byte RE :1; /* Receiver Enable Bit */ + byte TE :1; /* Transmitter Enable Bit */ + byte ILIE :1; /* Idle Line Interrupt Enable Bit */ + byte RIE :1; /* Receiver Full Interrupt Enable Bit */ + byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ + byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ + } Bits; +} SCI0CR2STR; +extern volatile SCI0CR2STR _SCI0CR2 @(REG_BASE + 0x000000CBUL); +#define SCI0CR2 _SCI0CR2.Byte +#define SCI0CR2_SBK _SCI0CR2.Bits.SBK +#define SCI0CR2_RWU _SCI0CR2.Bits.RWU +#define SCI0CR2_RE _SCI0CR2.Bits.RE +#define SCI0CR2_TE _SCI0CR2.Bits.TE +#define SCI0CR2_ILIE _SCI0CR2.Bits.ILIE +#define SCI0CR2_RIE _SCI0CR2.Bits.RIE +#define SCI0CR2_TCIE _SCI0CR2.Bits.TCIE +#define SCI0CR2_SCTIE _SCI0CR2.Bits.SCTIE + +#define SCI0CR2_SBK_MASK 1U +#define SCI0CR2_RWU_MASK 2U +#define SCI0CR2_RE_MASK 4U +#define SCI0CR2_TE_MASK 8U +#define SCI0CR2_ILIE_MASK 16U +#define SCI0CR2_RIE_MASK 32U +#define SCI0CR2_TCIE_MASK 64U +#define SCI0CR2_SCTIE_MASK 128U + + +/*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC ***/ +typedef union { + byte Byte; + struct { + byte PF :1; /* Parity Error Flag */ + byte FE :1; /* Framing Error Flag */ + byte NF :1; /* Noise Flag */ + byte OR :1; /* Overrun Flag */ + byte IDLE :1; /* Idle Line Flag */ + byte RDRF :1; /* Receive Data Register Full Flag */ + byte TC :1; /* Transmit Complete Flag */ + byte TDRE :1; /* Transmit Data Register Empty Flag */ + } Bits; +} SCI0SR1STR; +extern volatile SCI0SR1STR _SCI0SR1 @(REG_BASE + 0x000000CCUL); +#define SCI0SR1 _SCI0SR1.Byte +#define SCI0SR1_PF _SCI0SR1.Bits.PF +#define SCI0SR1_FE _SCI0SR1.Bits.FE +#define SCI0SR1_NF _SCI0SR1.Bits.NF +#define SCI0SR1_OR _SCI0SR1.Bits.OR +#define SCI0SR1_IDLE _SCI0SR1.Bits.IDLE +#define SCI0SR1_RDRF _SCI0SR1.Bits.RDRF +#define SCI0SR1_TC _SCI0SR1.Bits.TC +#define SCI0SR1_TDRE _SCI0SR1.Bits.TDRE + +#define SCI0SR1_PF_MASK 1U +#define SCI0SR1_FE_MASK 2U +#define SCI0SR1_NF_MASK 4U +#define SCI0SR1_OR_MASK 8U +#define SCI0SR1_IDLE_MASK 16U +#define SCI0SR1_RDRF_MASK 32U +#define SCI0SR1_TC_MASK 64U +#define SCI0SR1_TDRE_MASK 128U + + +/*** SCI0SR2 - SCI 0 Status Register 2; 0x000000CD ***/ +typedef union { + byte Byte; + struct { + byte RAF :1; /* Receiver Active Flag */ + byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ + byte BRK13 :1; /* Break Transmit character length */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} SCI0SR2STR; +extern volatile SCI0SR2STR _SCI0SR2 @(REG_BASE + 0x000000CDUL); +#define SCI0SR2 _SCI0SR2.Byte +#define SCI0SR2_RAF _SCI0SR2.Bits.RAF +#define SCI0SR2_TXDIR _SCI0SR2.Bits.TXDIR +#define SCI0SR2_BRK13 _SCI0SR2.Bits.BRK13 + +#define SCI0SR2_RAF_MASK 1U +#define SCI0SR2_TXDIR_MASK 2U +#define SCI0SR2_BRK13_MASK 4U + + +/*** SCI0DRH - SCI 0 Data Register High; 0x000000CE ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte T8 :1; /* Transmit Bit 8 */ + byte R8 :1; /* Received Bit 8 */ + } Bits; +} SCI0DRHSTR; +extern volatile SCI0DRHSTR _SCI0DRH @(REG_BASE + 0x000000CEUL); +#define SCI0DRH _SCI0DRH.Byte +#define SCI0DRH_T8 _SCI0DRH.Bits.T8 +#define SCI0DRH_R8 _SCI0DRH.Bits.R8 + +#define SCI0DRH_T8_MASK 64U +#define SCI0DRH_R8_MASK 128U + + +/*** SCI0DRL - SCI 0 Data Register Low; 0x000000CF ***/ +typedef union { + byte Byte; + struct { + byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ + byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ + byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ + byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ + byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ + byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ + byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ + byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ + } Bits; +} SCI0DRLSTR; +extern volatile SCI0DRLSTR _SCI0DRL @(REG_BASE + 0x000000CFUL); +#define SCI0DRL _SCI0DRL.Byte +#define SCI0DRL_R0_T0 _SCI0DRL.Bits.R0_T0 +#define SCI0DRL_R1_T1 _SCI0DRL.Bits.R1_T1 +#define SCI0DRL_R2_T2 _SCI0DRL.Bits.R2_T2 +#define SCI0DRL_R3_T3 _SCI0DRL.Bits.R3_T3 +#define SCI0DRL_R4_T4 _SCI0DRL.Bits.R4_T4 +#define SCI0DRL_R5_T5 _SCI0DRL.Bits.R5_T5 +#define SCI0DRL_R6_T6 _SCI0DRL.Bits.R6_T6 +#define SCI0DRL_R7_T7 _SCI0DRL.Bits.R7_T7 + +#define SCI0DRL_R0_T0_MASK 1U +#define SCI0DRL_R1_T1_MASK 2U +#define SCI0DRL_R2_T2_MASK 4U +#define SCI0DRL_R3_T3_MASK 8U +#define SCI0DRL_R4_T4_MASK 16U +#define SCI0DRL_R5_T5_MASK 32U +#define SCI0DRL_R6_T6_MASK 64U +#define SCI0DRL_R7_T7_MASK 128U + + +/*** SCI1BD - SCI 1 Baud Rate Register; 0x000000D0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SCI1BDH - SCI 1 Baud Rate Register High; 0x000000D0 ***/ + union { + byte Byte; + struct { + byte SBR8 :1; /* SCI Baud Rate Bit 8 */ + byte SBR9 :1; /* SCI Baud Rate Bit 9 */ + byte SBR10 :1; /* SCI Baud Rate Bit 10 */ + byte SBR11 :1; /* SCI Baud Rate Bit 11 */ + byte SBR12 :1; /* SCI Baud Rate Bit 12 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpSBR_8 :5; + byte :1; + byte :1; + byte :1; + } MergedBits; + } SCI1BDHSTR; + #define SCI1BDH _SCI1BD.Overlap_STR.SCI1BDHSTR.Byte + #define SCI1BDH_SBR8 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR8 + #define SCI1BDH_SBR9 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR9 + #define SCI1BDH_SBR10 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR10 + #define SCI1BDH_SBR11 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR11 + #define SCI1BDH_SBR12 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR12 + #define SCI1BDH_SBR_8 _SCI1BD.Overlap_STR.SCI1BDHSTR.MergedBits.grpSBR_8 + #define SCI1BDH_SBR SCI1BDH_SBR_8 + + #define SCI1BDH_SBR8_MASK 1U + #define SCI1BDH_SBR9_MASK 2U + #define SCI1BDH_SBR10_MASK 4U + #define SCI1BDH_SBR11_MASK 8U + #define SCI1BDH_SBR12_MASK 16U + #define SCI1BDH_SBR_8_MASK 31U + #define SCI1BDH_SBR_8_BITNUM 0U + + + /*** SCI1BDL - SCI 1 Baud Rate Register Low; 0x000000D1 ***/ + union { + byte Byte; + struct { + byte SBR0 :1; /* SCI Baud Rate Bit 0 */ + byte SBR1 :1; /* SCI Baud Rate Bit 1 */ + byte SBR2 :1; /* SCI Baud Rate Bit 2 */ + byte SBR3 :1; /* SCI Baud Rate Bit 3 */ + byte SBR4 :1; /* SCI Baud Rate Bit 4 */ + byte SBR5 :1; /* SCI Baud Rate Bit 5 */ + byte SBR6 :1; /* SCI Baud Rate Bit 6 */ + byte SBR7 :1; /* SCI Baud Rate Bit 7 */ + } Bits; + } SCI1BDLSTR; + #define SCI1BDL _SCI1BD.Overlap_STR.SCI1BDLSTR.Byte + #define SCI1BDL_SBR0 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR0 + #define SCI1BDL_SBR1 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR1 + #define SCI1BDL_SBR2 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR2 + #define SCI1BDL_SBR3 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR3 + #define SCI1BDL_SBR4 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR4 + #define SCI1BDL_SBR5 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR5 + #define SCI1BDL_SBR6 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR6 + #define SCI1BDL_SBR7 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR7 + + #define SCI1BDL_SBR0_MASK 1U + #define SCI1BDL_SBR1_MASK 2U + #define SCI1BDL_SBR2_MASK 4U + #define SCI1BDL_SBR3_MASK 8U + #define SCI1BDL_SBR4_MASK 16U + #define SCI1BDL_SBR5_MASK 32U + #define SCI1BDL_SBR6_MASK 64U + #define SCI1BDL_SBR7_MASK 128U + + } Overlap_STR; + + struct { + word SBR0 :1; /* SCI Baud Rate Bit 0 */ + word SBR1 :1; /* SCI Baud Rate Bit 1 */ + word SBR2 :1; /* SCI Baud Rate Bit 2 */ + word SBR3 :1; /* SCI Baud Rate Bit 3 */ + word SBR4 :1; /* SCI Baud Rate Bit 4 */ + word SBR5 :1; /* SCI Baud Rate Bit 5 */ + word SBR6 :1; /* SCI Baud Rate Bit 6 */ + word SBR7 :1; /* SCI Baud Rate Bit 7 */ + word SBR8 :1; /* SCI Baud Rate Bit 8 */ + word SBR9 :1; /* SCI Baud Rate Bit 9 */ + word SBR10 :1; /* SCI Baud Rate Bit 10 */ + word SBR11 :1; /* SCI Baud Rate Bit 11 */ + word SBR12 :1; /* SCI Baud Rate Bit 12 */ + word :1; + word :1; + word :1; + } Bits; + struct { + word grpSBR :13; + word :1; + word :1; + word :1; + } MergedBits; +} SCI1BDSTR; +extern volatile SCI1BDSTR _SCI1BD @(REG_BASE + 0x000000D0UL); +#define SCI1BD _SCI1BD.Word +#define SCI1BD_SBR0 _SCI1BD.Bits.SBR0 +#define SCI1BD_SBR1 _SCI1BD.Bits.SBR1 +#define SCI1BD_SBR2 _SCI1BD.Bits.SBR2 +#define SCI1BD_SBR3 _SCI1BD.Bits.SBR3 +#define SCI1BD_SBR4 _SCI1BD.Bits.SBR4 +#define SCI1BD_SBR5 _SCI1BD.Bits.SBR5 +#define SCI1BD_SBR6 _SCI1BD.Bits.SBR6 +#define SCI1BD_SBR7 _SCI1BD.Bits.SBR7 +#define SCI1BD_SBR8 _SCI1BD.Bits.SBR8 +#define SCI1BD_SBR9 _SCI1BD.Bits.SBR9 +#define SCI1BD_SBR10 _SCI1BD.Bits.SBR10 +#define SCI1BD_SBR11 _SCI1BD.Bits.SBR11 +#define SCI1BD_SBR12 _SCI1BD.Bits.SBR12 +#define SCI1BD_SBR _SCI1BD.MergedBits.grpSBR + +#define SCI1BD_SBR0_MASK 1U +#define SCI1BD_SBR1_MASK 2U +#define SCI1BD_SBR2_MASK 4U +#define SCI1BD_SBR3_MASK 8U +#define SCI1BD_SBR4_MASK 16U +#define SCI1BD_SBR5_MASK 32U +#define SCI1BD_SBR6_MASK 64U +#define SCI1BD_SBR7_MASK 128U +#define SCI1BD_SBR8_MASK 256U +#define SCI1BD_SBR9_MASK 512U +#define SCI1BD_SBR10_MASK 1024U +#define SCI1BD_SBR11_MASK 2048U +#define SCI1BD_SBR12_MASK 4096U +#define SCI1BD_SBR_MASK 8191U +#define SCI1BD_SBR_BITNUM 0U + + +/*** SCI1CR1 - SCI 1 Control Register 1; 0x000000D2 ***/ +typedef union { + byte Byte; + struct { + byte PT :1; /* Parity Type Bit */ + byte PE :1; /* Parity Enable Bit */ + byte ILT :1; /* Idle Line Type Bit */ + byte WAKE :1; /* Wakeup Condition Bit */ + byte M :1; /* Data Format Mode Bit */ + byte RSRC :1; /* Receiver Source Bit */ + byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */ + byte LOOPS :1; /* Loop Select Bit */ + } Bits; +} SCI1CR1STR; +extern volatile SCI1CR1STR _SCI1CR1 @(REG_BASE + 0x000000D2UL); +#define SCI1CR1 _SCI1CR1.Byte +#define SCI1CR1_PT _SCI1CR1.Bits.PT +#define SCI1CR1_PE _SCI1CR1.Bits.PE +#define SCI1CR1_ILT _SCI1CR1.Bits.ILT +#define SCI1CR1_WAKE _SCI1CR1.Bits.WAKE +#define SCI1CR1_M _SCI1CR1.Bits.M +#define SCI1CR1_RSRC _SCI1CR1.Bits.RSRC +#define SCI1CR1_SCISWAI _SCI1CR1.Bits.SCISWAI +#define SCI1CR1_LOOPS _SCI1CR1.Bits.LOOPS + +#define SCI1CR1_PT_MASK 1U +#define SCI1CR1_PE_MASK 2U +#define SCI1CR1_ILT_MASK 4U +#define SCI1CR1_WAKE_MASK 8U +#define SCI1CR1_M_MASK 16U +#define SCI1CR1_RSRC_MASK 32U +#define SCI1CR1_SCISWAI_MASK 64U +#define SCI1CR1_LOOPS_MASK 128U + + +/*** SCI1CR2 - SCI 1 Control Register 2; 0x000000D3 ***/ +typedef union { + byte Byte; + struct { + byte SBK :1; /* Send Break Bit */ + byte RWU :1; /* Receiver Wakeup Bit */ + byte RE :1; /* Receiver Enable Bit */ + byte TE :1; /* Transmitter Enable Bit */ + byte ILIE :1; /* Idle Line Interrupt Enable Bit */ + byte RIE :1; /* Receiver Full Interrupt Enable Bit */ + byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ + byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ + } Bits; +} SCI1CR2STR; +extern volatile SCI1CR2STR _SCI1CR2 @(REG_BASE + 0x000000D3UL); +#define SCI1CR2 _SCI1CR2.Byte +#define SCI1CR2_SBK _SCI1CR2.Bits.SBK +#define SCI1CR2_RWU _SCI1CR2.Bits.RWU +#define SCI1CR2_RE _SCI1CR2.Bits.RE +#define SCI1CR2_TE _SCI1CR2.Bits.TE +#define SCI1CR2_ILIE _SCI1CR2.Bits.ILIE +#define SCI1CR2_RIE _SCI1CR2.Bits.RIE +#define SCI1CR2_TCIE _SCI1CR2.Bits.TCIE +#define SCI1CR2_SCTIE _SCI1CR2.Bits.SCTIE + +#define SCI1CR2_SBK_MASK 1U +#define SCI1CR2_RWU_MASK 2U +#define SCI1CR2_RE_MASK 4U +#define SCI1CR2_TE_MASK 8U +#define SCI1CR2_ILIE_MASK 16U +#define SCI1CR2_RIE_MASK 32U +#define SCI1CR2_TCIE_MASK 64U +#define SCI1CR2_SCTIE_MASK 128U + + +/*** SCI1SR1 - SCI 1 Status Register 1; 0x000000D4 ***/ +typedef union { + byte Byte; + struct { + byte PF :1; /* Parity Error Flag */ + byte FE :1; /* Framing Error Flag */ + byte NF :1; /* Noise Flag */ + byte OR :1; /* Overrun Flag */ + byte IDLE :1; /* Idle Line Flag */ + byte RDRF :1; /* Receive Data Register Full Flag */ + byte TC :1; /* Transmit Complete Flag */ + byte TDRE :1; /* Transmit Data Register Empty Flag */ + } Bits; +} SCI1SR1STR; +extern volatile SCI1SR1STR _SCI1SR1 @(REG_BASE + 0x000000D4UL); +#define SCI1SR1 _SCI1SR1.Byte +#define SCI1SR1_PF _SCI1SR1.Bits.PF +#define SCI1SR1_FE _SCI1SR1.Bits.FE +#define SCI1SR1_NF _SCI1SR1.Bits.NF +#define SCI1SR1_OR _SCI1SR1.Bits.OR +#define SCI1SR1_IDLE _SCI1SR1.Bits.IDLE +#define SCI1SR1_RDRF _SCI1SR1.Bits.RDRF +#define SCI1SR1_TC _SCI1SR1.Bits.TC +#define SCI1SR1_TDRE _SCI1SR1.Bits.TDRE + +#define SCI1SR1_PF_MASK 1U +#define SCI1SR1_FE_MASK 2U +#define SCI1SR1_NF_MASK 4U +#define SCI1SR1_OR_MASK 8U +#define SCI1SR1_IDLE_MASK 16U +#define SCI1SR1_RDRF_MASK 32U +#define SCI1SR1_TC_MASK 64U +#define SCI1SR1_TDRE_MASK 128U + + +/*** SCI1SR2 - SCI 1 Status Register 2; 0x000000D5 ***/ +typedef union { + byte Byte; + struct { + byte RAF :1; /* Receiver Active Flag */ + byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ + byte BRK13 :1; /* Break Transmit character length */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} SCI1SR2STR; +extern volatile SCI1SR2STR _SCI1SR2 @(REG_BASE + 0x000000D5UL); +#define SCI1SR2 _SCI1SR2.Byte +#define SCI1SR2_RAF _SCI1SR2.Bits.RAF +#define SCI1SR2_TXDIR _SCI1SR2.Bits.TXDIR +#define SCI1SR2_BRK13 _SCI1SR2.Bits.BRK13 + +#define SCI1SR2_RAF_MASK 1U +#define SCI1SR2_TXDIR_MASK 2U +#define SCI1SR2_BRK13_MASK 4U + + +/*** SCI1DRH - SCI 1 Data Register High; 0x000000D6 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte T8 :1; /* Transmit Bit 8 */ + byte R8 :1; /* Received Bit 8 */ + } Bits; +} SCI1DRHSTR; +extern volatile SCI1DRHSTR _SCI1DRH @(REG_BASE + 0x000000D6UL); +#define SCI1DRH _SCI1DRH.Byte +#define SCI1DRH_T8 _SCI1DRH.Bits.T8 +#define SCI1DRH_R8 _SCI1DRH.Bits.R8 + +#define SCI1DRH_T8_MASK 64U +#define SCI1DRH_R8_MASK 128U + + +/*** SCI1DRL - SCI 1 Data Register Low; 0x000000D7 ***/ +typedef union { + byte Byte; + struct { + byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ + byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ + byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ + byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ + byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ + byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ + byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ + byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ + } Bits; +} SCI1DRLSTR; +extern volatile SCI1DRLSTR _SCI1DRL @(REG_BASE + 0x000000D7UL); +#define SCI1DRL _SCI1DRL.Byte +#define SCI1DRL_R0_T0 _SCI1DRL.Bits.R0_T0 +#define SCI1DRL_R1_T1 _SCI1DRL.Bits.R1_T1 +#define SCI1DRL_R2_T2 _SCI1DRL.Bits.R2_T2 +#define SCI1DRL_R3_T3 _SCI1DRL.Bits.R3_T3 +#define SCI1DRL_R4_T4 _SCI1DRL.Bits.R4_T4 +#define SCI1DRL_R5_T5 _SCI1DRL.Bits.R5_T5 +#define SCI1DRL_R6_T6 _SCI1DRL.Bits.R6_T6 +#define SCI1DRL_R7_T7 _SCI1DRL.Bits.R7_T7 + +#define SCI1DRL_R0_T0_MASK 1U +#define SCI1DRL_R1_T1_MASK 2U +#define SCI1DRL_R2_T2_MASK 4U +#define SCI1DRL_R3_T3_MASK 8U +#define SCI1DRL_R4_T4_MASK 16U +#define SCI1DRL_R5_T5_MASK 32U +#define SCI1DRL_R6_T6_MASK 64U +#define SCI1DRL_R7_T7_MASK 128U + + +/*** SPI0CR1 - SPI 0 Control Register; 0x000000D8 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI Clock Phase Bit */ + byte CPOL :1; /* SPI Clock Polarity Bit */ + byte MSTR :1; /* SPI Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI Transmit Interrupt Enable */ + byte SPE :1; /* SPI System Enable Bit */ + byte SPIE :1; /* SPI Interrupt Enable Bit */ + } Bits; +} SPI0CR1STR; +extern volatile SPI0CR1STR _SPI0CR1 @(REG_BASE + 0x000000D8UL); +#define SPI0CR1 _SPI0CR1.Byte +#define SPI0CR1_LSBFE _SPI0CR1.Bits.LSBFE +#define SPI0CR1_SSOE _SPI0CR1.Bits.SSOE +#define SPI0CR1_CPHA _SPI0CR1.Bits.CPHA +#define SPI0CR1_CPOL _SPI0CR1.Bits.CPOL +#define SPI0CR1_MSTR _SPI0CR1.Bits.MSTR +#define SPI0CR1_SPTIE _SPI0CR1.Bits.SPTIE +#define SPI0CR1_SPE _SPI0CR1.Bits.SPE +#define SPI0CR1_SPIE _SPI0CR1.Bits.SPIE + +#define SPI0CR1_LSBFE_MASK 1U +#define SPI0CR1_SSOE_MASK 2U +#define SPI0CR1_CPHA_MASK 4U +#define SPI0CR1_CPOL_MASK 8U +#define SPI0CR1_MSTR_MASK 16U +#define SPI0CR1_SPTIE_MASK 32U +#define SPI0CR1_SPE_MASK 64U +#define SPI0CR1_SPIE_MASK 128U + + +/*** SPI0CR2 - SPI 0 Control Register 2; 0x000000D9 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPI0CR2STR; +extern volatile SPI0CR2STR _SPI0CR2 @(REG_BASE + 0x000000D9UL); +#define SPI0CR2 _SPI0CR2.Byte +#define SPI0CR2_SPC0 _SPI0CR2.Bits.SPC0 +#define SPI0CR2_SPISWAI _SPI0CR2.Bits.SPISWAI +#define SPI0CR2_BIDIROE _SPI0CR2.Bits.BIDIROE +#define SPI0CR2_MODFEN _SPI0CR2.Bits.MODFEN + +#define SPI0CR2_SPC0_MASK 1U +#define SPI0CR2_SPISWAI_MASK 2U +#define SPI0CR2_BIDIROE_MASK 8U +#define SPI0CR2_MODFEN_MASK 16U + + +/*** SPI0BR - SPI 0 Baud Rate Register; 0x000000DA ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI0BRSTR; +extern volatile SPI0BRSTR _SPI0BR @(REG_BASE + 0x000000DAUL); +#define SPI0BR _SPI0BR.Byte +#define SPI0BR_SPR0 _SPI0BR.Bits.SPR0 +#define SPI0BR_SPR1 _SPI0BR.Bits.SPR1 +#define SPI0BR_SPR2 _SPI0BR.Bits.SPR2 +#define SPI0BR_SPPR0 _SPI0BR.Bits.SPPR0 +#define SPI0BR_SPPR1 _SPI0BR.Bits.SPPR1 +#define SPI0BR_SPPR2 _SPI0BR.Bits.SPPR2 +#define SPI0BR_SPR _SPI0BR.MergedBits.grpSPR +#define SPI0BR_SPPR _SPI0BR.MergedBits.grpSPPR + +#define SPI0BR_SPR0_MASK 1U +#define SPI0BR_SPR1_MASK 2U +#define SPI0BR_SPR2_MASK 4U +#define SPI0BR_SPPR0_MASK 16U +#define SPI0BR_SPPR1_MASK 32U +#define SPI0BR_SPPR2_MASK 64U +#define SPI0BR_SPR_MASK 7U +#define SPI0BR_SPR_BITNUM 0U +#define SPI0BR_SPPR_MASK 112U +#define SPI0BR_SPPR_BITNUM 4U + + +/*** SPI0SR - SPI 0 Status Register; 0x000000DB ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI0SRSTR; +extern volatile SPI0SRSTR _SPI0SR @(REG_BASE + 0x000000DBUL); +#define SPI0SR _SPI0SR.Byte +#define SPI0SR_MODF _SPI0SR.Bits.MODF +#define SPI0SR_SPTEF _SPI0SR.Bits.SPTEF +#define SPI0SR_SPIF _SPI0SR.Bits.SPIF + +#define SPI0SR_MODF_MASK 16U +#define SPI0SR_SPTEF_MASK 32U +#define SPI0SR_SPIF_MASK 128U + + +/*** SPI0DR - SPI 0 Data Register; 0x000000DD ***/ +typedef union { + byte Byte; +} SPI0DRSTR; +extern volatile SPI0DRSTR _SPI0DR @(REG_BASE + 0x000000DDUL); +#define SPI0DR _SPI0DR.Byte + + +/*** IBAD - IIC Address Register; 0x000000E0 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte ADR1 :1; /* Slave Address Bit 1 */ + byte ADR2 :1; /* Slave Address Bit 2 */ + byte ADR3 :1; /* Slave Address Bit 3 */ + byte ADR4 :1; /* Slave Address Bit 4 */ + byte ADR5 :1; /* Slave Address Bit 5 */ + byte ADR6 :1; /* Slave Address Bit 6 */ + byte ADR7 :1; /* Slave Address Bit 7 */ + } Bits; + struct { + byte :1; + byte grpADR_1 :7; + } MergedBits; +} IBADSTR; +extern volatile IBADSTR _IBAD @(REG_BASE + 0x000000E0UL); +#define IBAD _IBAD.Byte +#define IBAD_ADR1 _IBAD.Bits.ADR1 +#define IBAD_ADR2 _IBAD.Bits.ADR2 +#define IBAD_ADR3 _IBAD.Bits.ADR3 +#define IBAD_ADR4 _IBAD.Bits.ADR4 +#define IBAD_ADR5 _IBAD.Bits.ADR5 +#define IBAD_ADR6 _IBAD.Bits.ADR6 +#define IBAD_ADR7 _IBAD.Bits.ADR7 +#define IBAD_ADR_1 _IBAD.MergedBits.grpADR_1 +#define IBAD_ADR IBAD_ADR_1 + +#define IBAD_ADR1_MASK 2U +#define IBAD_ADR2_MASK 4U +#define IBAD_ADR3_MASK 8U +#define IBAD_ADR4_MASK 16U +#define IBAD_ADR5_MASK 32U +#define IBAD_ADR6_MASK 64U +#define IBAD_ADR7_MASK 128U +#define IBAD_ADR_1_MASK 254U +#define IBAD_ADR_1_BITNUM 1U + + +/*** IBFD - IIC Frequency Divider Register; 0x000000E1 ***/ +typedef union { + byte Byte; + struct { + byte IBC0 :1; /* I-Bus Clock Rate 0 */ + byte IBC1 :1; /* I-Bus Clock Rate 1 */ + byte IBC2 :1; /* I-Bus Clock Rate 2 */ + byte IBC3 :1; /* I-Bus Clock Rate 3 */ + byte IBC4 :1; /* I-Bus Clock Rate 4 */ + byte IBC5 :1; /* I-Bus Clock Rate 5 */ + byte IBC6 :1; /* I-Bus Clock Rate 6 */ + byte IBC7 :1; /* I-Bus Clock Rate 7 */ + } Bits; +} IBFDSTR; +extern volatile IBFDSTR _IBFD @(REG_BASE + 0x000000E1UL); +#define IBFD _IBFD.Byte +#define IBFD_IBC0 _IBFD.Bits.IBC0 +#define IBFD_IBC1 _IBFD.Bits.IBC1 +#define IBFD_IBC2 _IBFD.Bits.IBC2 +#define IBFD_IBC3 _IBFD.Bits.IBC3 +#define IBFD_IBC4 _IBFD.Bits.IBC4 +#define IBFD_IBC5 _IBFD.Bits.IBC5 +#define IBFD_IBC6 _IBFD.Bits.IBC6 +#define IBFD_IBC7 _IBFD.Bits.IBC7 + +#define IBFD_IBC0_MASK 1U +#define IBFD_IBC1_MASK 2U +#define IBFD_IBC2_MASK 4U +#define IBFD_IBC3_MASK 8U +#define IBFD_IBC4_MASK 16U +#define IBFD_IBC5_MASK 32U +#define IBFD_IBC6_MASK 64U +#define IBFD_IBC7_MASK 128U + + +/*** IBCR - IIC Control Register; 0x000000E2 ***/ +typedef union { + byte Byte; + struct { + byte IBSWAI :1; /* I-Bus Interface Stop in WAIT mode */ + byte :1; + byte RSTA :1; /* Repeat Start */ + byte TXAK :1; /* Transmit Acknowledge enable */ + byte TX_RX :1; /* Transmit/Receive mode select bit */ + byte MS_SL :1; /* Master/Slave mode select bit */ + byte IBIE :1; /* I-Bus Interrupt Enable */ + byte IBEN :1; /* I-Bus Enable */ + } Bits; +} IBCRSTR; +extern volatile IBCRSTR _IBCR @(REG_BASE + 0x000000E2UL); +#define IBCR _IBCR.Byte +#define IBCR_IBSWAI _IBCR.Bits.IBSWAI +#define IBCR_RSTA _IBCR.Bits.RSTA +#define IBCR_TXAK _IBCR.Bits.TXAK +#define IBCR_TX_RX _IBCR.Bits.TX_RX +#define IBCR_MS_SL _IBCR.Bits.MS_SL +#define IBCR_IBIE _IBCR.Bits.IBIE +#define IBCR_IBEN _IBCR.Bits.IBEN + +#define IBCR_IBSWAI_MASK 1U +#define IBCR_RSTA_MASK 4U +#define IBCR_TXAK_MASK 8U +#define IBCR_TX_RX_MASK 16U +#define IBCR_MS_SL_MASK 32U +#define IBCR_IBIE_MASK 64U +#define IBCR_IBEN_MASK 128U + + +/*** IBSR - IIC Status Register; 0x000000E3 ***/ +typedef union { + byte Byte; + struct { + byte RXAK :1; /* Received Acknowledge */ + byte IBIF :1; /* I-Bus Interrupt */ + byte SRW :1; /* Slave Read/Write */ + byte :1; + byte IBAL :1; /* Arbitration Lost */ + byte IBB :1; /* Bus busy bit */ + byte IAAS :1; /* Addressed as a slave bit */ + byte TCF :1; /* Data transferring bit */ + } Bits; +} IBSRSTR; +extern volatile IBSRSTR _IBSR @(REG_BASE + 0x000000E3UL); +#define IBSR _IBSR.Byte +#define IBSR_RXAK _IBSR.Bits.RXAK +#define IBSR_IBIF _IBSR.Bits.IBIF +#define IBSR_SRW _IBSR.Bits.SRW +#define IBSR_IBAL _IBSR.Bits.IBAL +#define IBSR_IBB _IBSR.Bits.IBB +#define IBSR_IAAS _IBSR.Bits.IAAS +#define IBSR_TCF _IBSR.Bits.TCF + +#define IBSR_RXAK_MASK 1U +#define IBSR_IBIF_MASK 2U +#define IBSR_SRW_MASK 4U +#define IBSR_IBAL_MASK 16U +#define IBSR_IBB_MASK 32U +#define IBSR_IAAS_MASK 64U +#define IBSR_TCF_MASK 128U + + +/*** IBDR - IIC Data I/O Register; 0x000000E4 ***/ +typedef union { + byte Byte; + struct { + byte D0 :1; /* IIC Data Bit 0 */ + byte D1 :1; /* IIC Data Bit 1 */ + byte D2 :1; /* IIC Data Bit 2 */ + byte D3 :1; /* IIC Data Bit 3 */ + byte D4 :1; /* IIC Data Bit 4 */ + byte D5 :1; /* IIC Data Bit 5 */ + byte D6 :1; /* IIC Data Bit 6 */ + byte D7 :1; /* IIC Data Bit 7 */ + } Bits; +} IBDRSTR; +extern volatile IBDRSTR _IBDR @(REG_BASE + 0x000000E4UL); +#define IBDR _IBDR.Byte +#define IBDR_D0 _IBDR.Bits.D0 +#define IBDR_D1 _IBDR.Bits.D1 +#define IBDR_D2 _IBDR.Bits.D2 +#define IBDR_D3 _IBDR.Bits.D3 +#define IBDR_D4 _IBDR.Bits.D4 +#define IBDR_D5 _IBDR.Bits.D5 +#define IBDR_D6 _IBDR.Bits.D6 +#define IBDR_D7 _IBDR.Bits.D7 + +#define IBDR_D0_MASK 1U +#define IBDR_D1_MASK 2U +#define IBDR_D2_MASK 4U +#define IBDR_D3_MASK 8U +#define IBDR_D4_MASK 16U +#define IBDR_D5_MASK 32U +#define IBDR_D6_MASK 64U +#define IBDR_D7_MASK 128U + + +/*** SPI1CR1 - SPI 1 Control Register; 0x000000F0 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI Clock Phase Bit */ + byte CPOL :1; /* SPI Clock Polarity Bit */ + byte MSTR :1; /* SPI Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI Transmit Interrupt Enable */ + byte SPE :1; /* SPI System Enable Bit */ + byte SPIE :1; /* SPI Interrupt Enable Bit */ + } Bits; +} SPI1CR1STR; +extern volatile SPI1CR1STR _SPI1CR1 @(REG_BASE + 0x000000F0UL); +#define SPI1CR1 _SPI1CR1.Byte +#define SPI1CR1_LSBFE _SPI1CR1.Bits.LSBFE +#define SPI1CR1_SSOE _SPI1CR1.Bits.SSOE +#define SPI1CR1_CPHA _SPI1CR1.Bits.CPHA +#define SPI1CR1_CPOL _SPI1CR1.Bits.CPOL +#define SPI1CR1_MSTR _SPI1CR1.Bits.MSTR +#define SPI1CR1_SPTIE _SPI1CR1.Bits.SPTIE +#define SPI1CR1_SPE _SPI1CR1.Bits.SPE +#define SPI1CR1_SPIE _SPI1CR1.Bits.SPIE + +#define SPI1CR1_LSBFE_MASK 1U +#define SPI1CR1_SSOE_MASK 2U +#define SPI1CR1_CPHA_MASK 4U +#define SPI1CR1_CPOL_MASK 8U +#define SPI1CR1_MSTR_MASK 16U +#define SPI1CR1_SPTIE_MASK 32U +#define SPI1CR1_SPE_MASK 64U +#define SPI1CR1_SPIE_MASK 128U + + +/*** SPI1CR2 - SPI 1 Control Register 2; 0x000000F1 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPI1CR2STR; +extern volatile SPI1CR2STR _SPI1CR2 @(REG_BASE + 0x000000F1UL); +#define SPI1CR2 _SPI1CR2.Byte +#define SPI1CR2_SPC0 _SPI1CR2.Bits.SPC0 +#define SPI1CR2_SPISWAI _SPI1CR2.Bits.SPISWAI +#define SPI1CR2_BIDIROE _SPI1CR2.Bits.BIDIROE +#define SPI1CR2_MODFEN _SPI1CR2.Bits.MODFEN + +#define SPI1CR2_SPC0_MASK 1U +#define SPI1CR2_SPISWAI_MASK 2U +#define SPI1CR2_BIDIROE_MASK 8U +#define SPI1CR2_MODFEN_MASK 16U + + +/*** SPI1BR - SPI 1 Baud Rate Register; 0x000000F2 ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI1BRSTR; +extern volatile SPI1BRSTR _SPI1BR @(REG_BASE + 0x000000F2UL); +#define SPI1BR _SPI1BR.Byte +#define SPI1BR_SPR0 _SPI1BR.Bits.SPR0 +#define SPI1BR_SPR1 _SPI1BR.Bits.SPR1 +#define SPI1BR_SPR2 _SPI1BR.Bits.SPR2 +#define SPI1BR_SPPR0 _SPI1BR.Bits.SPPR0 +#define SPI1BR_SPPR1 _SPI1BR.Bits.SPPR1 +#define SPI1BR_SPPR2 _SPI1BR.Bits.SPPR2 +#define SPI1BR_SPR _SPI1BR.MergedBits.grpSPR +#define SPI1BR_SPPR _SPI1BR.MergedBits.grpSPPR + +#define SPI1BR_SPR0_MASK 1U +#define SPI1BR_SPR1_MASK 2U +#define SPI1BR_SPR2_MASK 4U +#define SPI1BR_SPPR0_MASK 16U +#define SPI1BR_SPPR1_MASK 32U +#define SPI1BR_SPPR2_MASK 64U +#define SPI1BR_SPR_MASK 7U +#define SPI1BR_SPR_BITNUM 0U +#define SPI1BR_SPPR_MASK 112U +#define SPI1BR_SPPR_BITNUM 4U + + +/*** SPI1SR - SPI 1 Status Register; 0x000000F3 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI1SRSTR; +extern volatile SPI1SRSTR _SPI1SR @(REG_BASE + 0x000000F3UL); +#define SPI1SR _SPI1SR.Byte +#define SPI1SR_MODF _SPI1SR.Bits.MODF +#define SPI1SR_SPTEF _SPI1SR.Bits.SPTEF +#define SPI1SR_SPIF _SPI1SR.Bits.SPIF + +#define SPI1SR_MODF_MASK 16U +#define SPI1SR_SPTEF_MASK 32U +#define SPI1SR_SPIF_MASK 128U + + +/*** SPI1DR - SPI 1 Data Register; 0x000000F5 ***/ +typedef union { + byte Byte; +} SPI1DRSTR; +extern volatile SPI1DRSTR _SPI1DR @(REG_BASE + 0x000000F5UL); +#define SPI1DR _SPI1DR.Byte + + +/*** SPI2CR1 - SPI 2 Control Register; 0x000000F8 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI Clock Phase Bit */ + byte CPOL :1; /* SPI Clock Polarity Bit */ + byte MSTR :1; /* SPI Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI Transmit Interrupt Enable */ + byte SPE :1; /* SPI System Enable Bit */ + byte SPIE :1; /* SPI Interrupt Enable Bit */ + } Bits; +} SPI2CR1STR; +extern volatile SPI2CR1STR _SPI2CR1 @(REG_BASE + 0x000000F8UL); +#define SPI2CR1 _SPI2CR1.Byte +#define SPI2CR1_LSBFE _SPI2CR1.Bits.LSBFE +#define SPI2CR1_SSOE _SPI2CR1.Bits.SSOE +#define SPI2CR1_CPHA _SPI2CR1.Bits.CPHA +#define SPI2CR1_CPOL _SPI2CR1.Bits.CPOL +#define SPI2CR1_MSTR _SPI2CR1.Bits.MSTR +#define SPI2CR1_SPTIE _SPI2CR1.Bits.SPTIE +#define SPI2CR1_SPE _SPI2CR1.Bits.SPE +#define SPI2CR1_SPIE _SPI2CR1.Bits.SPIE + +#define SPI2CR1_LSBFE_MASK 1U +#define SPI2CR1_SSOE_MASK 2U +#define SPI2CR1_CPHA_MASK 4U +#define SPI2CR1_CPOL_MASK 8U +#define SPI2CR1_MSTR_MASK 16U +#define SPI2CR1_SPTIE_MASK 32U +#define SPI2CR1_SPE_MASK 64U +#define SPI2CR1_SPIE_MASK 128U + + +/*** SPI2CR2 - SPI 2 Control Register 2; 0x000000F9 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPI2CR2STR; +extern volatile SPI2CR2STR _SPI2CR2 @(REG_BASE + 0x000000F9UL); +#define SPI2CR2 _SPI2CR2.Byte +#define SPI2CR2_SPC0 _SPI2CR2.Bits.SPC0 +#define SPI2CR2_SPISWAI _SPI2CR2.Bits.SPISWAI +#define SPI2CR2_BIDIROE _SPI2CR2.Bits.BIDIROE +#define SPI2CR2_MODFEN _SPI2CR2.Bits.MODFEN + +#define SPI2CR2_SPC0_MASK 1U +#define SPI2CR2_SPISWAI_MASK 2U +#define SPI2CR2_BIDIROE_MASK 8U +#define SPI2CR2_MODFEN_MASK 16U + + +/*** SPI2BR - SPI 2 Baud Rate Register; 0x000000FA ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI2BRSTR; +extern volatile SPI2BRSTR _SPI2BR @(REG_BASE + 0x000000FAUL); +#define SPI2BR _SPI2BR.Byte +#define SPI2BR_SPR0 _SPI2BR.Bits.SPR0 +#define SPI2BR_SPR1 _SPI2BR.Bits.SPR1 +#define SPI2BR_SPR2 _SPI2BR.Bits.SPR2 +#define SPI2BR_SPPR0 _SPI2BR.Bits.SPPR0 +#define SPI2BR_SPPR1 _SPI2BR.Bits.SPPR1 +#define SPI2BR_SPPR2 _SPI2BR.Bits.SPPR2 +#define SPI2BR_SPR _SPI2BR.MergedBits.grpSPR +#define SPI2BR_SPPR _SPI2BR.MergedBits.grpSPPR + +#define SPI2BR_SPR0_MASK 1U +#define SPI2BR_SPR1_MASK 2U +#define SPI2BR_SPR2_MASK 4U +#define SPI2BR_SPPR0_MASK 16U +#define SPI2BR_SPPR1_MASK 32U +#define SPI2BR_SPPR2_MASK 64U +#define SPI2BR_SPR_MASK 7U +#define SPI2BR_SPR_BITNUM 0U +#define SPI2BR_SPPR_MASK 112U +#define SPI2BR_SPPR_BITNUM 4U + + +/*** SPI2SR - SPI 2 Status Register; 0x000000FB ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI2SRSTR; +extern volatile SPI2SRSTR _SPI2SR @(REG_BASE + 0x000000FBUL); +#define SPI2SR _SPI2SR.Byte +#define SPI2SR_MODF _SPI2SR.Bits.MODF +#define SPI2SR_SPTEF _SPI2SR.Bits.SPTEF +#define SPI2SR_SPIF _SPI2SR.Bits.SPIF + +#define SPI2SR_MODF_MASK 16U +#define SPI2SR_SPTEF_MASK 32U +#define SPI2SR_SPIF_MASK 128U + + +/*** SPI2DR - SPI 2 Data Register; 0x000000FD ***/ +typedef union { + byte Byte; +} SPI2DRSTR; +extern volatile SPI2DRSTR _SPI2DR @(REG_BASE + 0x000000FDUL); +#define SPI2DR _SPI2DR.Byte + + +/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/ +typedef union { + byte Byte; + struct { + byte FDIV0 :1; /* Flash Clock Divider Bit 0 */ + byte FDIV1 :1; /* Flash Clock Divider Bit 1 */ + byte FDIV2 :1; /* Flash Clock Divider Bit 2 */ + byte FDIV3 :1; /* Flash Clock Divider Bit 3 */ + byte FDIV4 :1; /* Flash Clock Divider Bit 4 */ + byte FDIV5 :1; /* Flash Clock Divider Bit 5 */ + byte PRDIV8 :1; /* Enable Prescaler by 8 */ + byte FDIVLD :1; /* Flash Clock Divider Loaded */ + } Bits; + struct { + byte grpFDIV :6; + byte grpPRDIV_8 :1; + byte :1; + } MergedBits; +} FCLKDIVSTR; +extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100UL); +#define FCLKDIV _FCLKDIV.Byte +#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0 +#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1 +#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2 +#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3 +#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4 +#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5 +#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8 +#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD +#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV + +#define FCLKDIV_FDIV0_MASK 1U +#define FCLKDIV_FDIV1_MASK 2U +#define FCLKDIV_FDIV2_MASK 4U +#define FCLKDIV_FDIV3_MASK 8U +#define FCLKDIV_FDIV4_MASK 16U +#define FCLKDIV_FDIV5_MASK 32U +#define FCLKDIV_PRDIV8_MASK 64U +#define FCLKDIV_FDIVLD_MASK 128U +#define FCLKDIV_FDIV_MASK 63U +#define FCLKDIV_FDIV_BITNUM 0U + + +/*** FSEC - Flash Security Register; 0x00000101 ***/ +typedef union { + byte Byte; + struct { + byte SEC0 :1; /* Memory security bit 0 */ + byte SEC1 :1; /* Memory security bit 1 */ + byte NV2 :1; /* Non Volatile flag bit 2 */ + byte NV3 :1; /* Non Volatile flag bit 3 */ + byte NV4 :1; /* Non Volatile flag bit 4 */ + byte NV5 :1; /* Non Volatile flag bit 5 */ + byte KEYEN0 :1; /* Backdoor Key Security Enable Bit 0 */ + byte KEYEN1 :1; /* Backdoor Key Security Enable Bit 1 */ + } Bits; + struct { + byte grpSEC :2; + byte grpNV_2 :4; + byte grpKEYEN :2; + } MergedBits; +} FSECSTR; +extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101UL); +#define FSEC _FSEC.Byte +#define FSEC_SEC0 _FSEC.Bits.SEC0 +#define FSEC_SEC1 _FSEC.Bits.SEC1 +#define FSEC_NV2 _FSEC.Bits.NV2 +#define FSEC_NV3 _FSEC.Bits.NV3 +#define FSEC_NV4 _FSEC.Bits.NV4 +#define FSEC_NV5 _FSEC.Bits.NV5 +#define FSEC_KEYEN0 _FSEC.Bits.KEYEN0 +#define FSEC_KEYEN1 _FSEC.Bits.KEYEN1 +#define FSEC_SEC _FSEC.MergedBits.grpSEC +#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2 +#define FSEC_KEYEN _FSEC.MergedBits.grpKEYEN +#define FSEC_NV FSEC_NV_2 + +#define FSEC_SEC0_MASK 1U +#define FSEC_SEC1_MASK 2U +#define FSEC_NV2_MASK 4U +#define FSEC_NV3_MASK 8U +#define FSEC_NV4_MASK 16U +#define FSEC_NV5_MASK 32U +#define FSEC_KEYEN0_MASK 64U +#define FSEC_KEYEN1_MASK 128U +#define FSEC_SEC_MASK 3U +#define FSEC_SEC_BITNUM 0U +#define FSEC_NV_2_MASK 60U +#define FSEC_NV_2_BITNUM 2U +#define FSEC_KEYEN_MASK 192U +#define FSEC_KEYEN_BITNUM 6U + + +/*** FCNFG - Flash Configuration Register; 0x00000103 ***/ +typedef union { + byte Byte; + struct { + byte BKSEL0 :1; /* Register bank select 0 */ + byte BKSEL1 :1; /* Register bank select 1 */ + byte :1; + byte :1; + byte :1; + byte KEYACC :1; /* Enable Security Key Writing */ + byte CCIE :1; /* Command Complete Interrupt Enable */ + byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ + } Bits; + struct { + byte grpBKSEL :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} FCNFGSTR; +extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103UL); +#define FCNFG _FCNFG.Byte +#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0 +#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1 +#define FCNFG_KEYACC _FCNFG.Bits.KEYACC +#define FCNFG_CCIE _FCNFG.Bits.CCIE +#define FCNFG_CBEIE _FCNFG.Bits.CBEIE +#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL + +#define FCNFG_BKSEL0_MASK 1U +#define FCNFG_BKSEL1_MASK 2U +#define FCNFG_KEYACC_MASK 32U +#define FCNFG_CCIE_MASK 64U +#define FCNFG_CBEIE_MASK 128U +#define FCNFG_BKSEL_MASK 3U +#define FCNFG_BKSEL_BITNUM 0U + + +/*** FPROT - Flash Protection Register; 0x00000104 ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} FPROTSTR; +extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104UL); +#define FPROT _FPROT.Byte +#define FPROT_FPLS0 _FPROT.Bits.FPLS0 +#define FPROT_FPLS1 _FPROT.Bits.FPLS1 +#define FPROT_FPLDIS _FPROT.Bits.FPLDIS +#define FPROT_FPHS0 _FPROT.Bits.FPHS0 +#define FPROT_FPHS1 _FPROT.Bits.FPHS1 +#define FPROT_FPHDIS _FPROT.Bits.FPHDIS +#define FPROT_NV6 _FPROT.Bits.NV6 +#define FPROT_FPOPEN _FPROT.Bits.FPOPEN +#define FPROT_FPLS _FPROT.MergedBits.grpFPLS +#define FPROT_FPHS _FPROT.MergedBits.grpFPHS + +#define FPROT_FPLS0_MASK 1U +#define FPROT_FPLS1_MASK 2U +#define FPROT_FPLDIS_MASK 4U +#define FPROT_FPHS0_MASK 8U +#define FPROT_FPHS1_MASK 16U +#define FPROT_FPHDIS_MASK 32U +#define FPROT_NV6_MASK 64U +#define FPROT_FPOPEN_MASK 128U +#define FPROT_FPLS_MASK 3U +#define FPROT_FPLS_BITNUM 0U +#define FPROT_FPHS_MASK 24U +#define FPROT_FPHS_BITNUM 3U + + +/*** FSTAT - Flash Status Register; 0x00000105 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BLANK :1; /* Blank Verify Flag */ + byte :1; + byte ACCERR :1; /* Access error */ + byte PVIOL :1; /* Protection violation */ + byte CCIF :1; /* Command Complete Interrupt Flag */ + byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */ + } Bits; +} FSTATSTR; +extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105UL); +#define FSTAT _FSTAT.Byte +#define FSTAT_BLANK _FSTAT.Bits.BLANK +#define FSTAT_ACCERR _FSTAT.Bits.ACCERR +#define FSTAT_PVIOL _FSTAT.Bits.PVIOL +#define FSTAT_CCIF _FSTAT.Bits.CCIF +#define FSTAT_CBEIF _FSTAT.Bits.CBEIF + +#define FSTAT_BLANK_MASK 4U +#define FSTAT_ACCERR_MASK 16U +#define FSTAT_PVIOL_MASK 32U +#define FSTAT_CCIF_MASK 64U +#define FSTAT_CBEIF_MASK 128U + + +/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/ +typedef union { + byte Byte; + struct { + byte CMDB0 :1; /* NVM User Mode Command Bit 0 */ + byte :1; + byte CMDB2 :1; /* NVM User Mode Command Bit 2 */ + byte :1; + byte :1; + byte CMDB5 :1; /* NVM User Mode Command Bit 5 */ + byte CMDB6 :1; /* NVM User Mode Command Bit 6 */ + byte :1; + } Bits; + struct { + byte grpCMDB :1; + byte :1; + byte grpCMDB_2 :1; + byte :1; + byte :1; + byte grpCMDB_5 :2; + byte :1; + } MergedBits; +} FCMDSTR; +extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106UL); +#define FCMD _FCMD.Byte +#define FCMD_CMDB0 _FCMD.Bits.CMDB0 +#define FCMD_CMDB2 _FCMD.Bits.CMDB2 +#define FCMD_CMDB5 _FCMD.Bits.CMDB5 +#define FCMD_CMDB6 _FCMD.Bits.CMDB6 +#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5 +#define FCMD_CMDB FCMD_CMDB_5 + +#define FCMD_CMDB0_MASK 1U +#define FCMD_CMDB2_MASK 4U +#define FCMD_CMDB5_MASK 32U +#define FCMD_CMDB6_MASK 64U +#define FCMD_CMDB_5_MASK 96U +#define FCMD_CMDB_5_BITNUM 5U + + +/*** ECLKDIV - EEPROM Clock Divider Register; 0x00000110 ***/ +typedef union { + byte Byte; + struct { + byte EDIV0 :1; /* EEPROM Clock Divider 0 */ + byte EDIV1 :1; /* EEPROM Clock Divider 1 */ + byte EDIV2 :1; /* EEPROM Clock Divider 2 */ + byte EDIV3 :1; /* EEPROM Clock Divider 3 */ + byte EDIV4 :1; /* EEPROM Clock Divider 4 */ + byte EDIV5 :1; /* EEPROM Clock Divider 5 */ + byte PRDIV8 :1; /* Enable Prescaler by 8 */ + byte EDIVLD :1; /* EEPROM Clock Divider Loaded */ + } Bits; + struct { + byte grpEDIV :6; + byte grpPRDIV_8 :1; + byte :1; + } MergedBits; +} ECLKDIVSTR; +extern volatile ECLKDIVSTR _ECLKDIV @(REG_BASE + 0x00000110UL); +#define ECLKDIV _ECLKDIV.Byte +#define ECLKDIV_EDIV0 _ECLKDIV.Bits.EDIV0 +#define ECLKDIV_EDIV1 _ECLKDIV.Bits.EDIV1 +#define ECLKDIV_EDIV2 _ECLKDIV.Bits.EDIV2 +#define ECLKDIV_EDIV3 _ECLKDIV.Bits.EDIV3 +#define ECLKDIV_EDIV4 _ECLKDIV.Bits.EDIV4 +#define ECLKDIV_EDIV5 _ECLKDIV.Bits.EDIV5 +#define ECLKDIV_PRDIV8 _ECLKDIV.Bits.PRDIV8 +#define ECLKDIV_EDIVLD _ECLKDIV.Bits.EDIVLD +#define ECLKDIV_EDIV _ECLKDIV.MergedBits.grpEDIV + +#define ECLKDIV_EDIV0_MASK 1U +#define ECLKDIV_EDIV1_MASK 2U +#define ECLKDIV_EDIV2_MASK 4U +#define ECLKDIV_EDIV3_MASK 8U +#define ECLKDIV_EDIV4_MASK 16U +#define ECLKDIV_EDIV5_MASK 32U +#define ECLKDIV_PRDIV8_MASK 64U +#define ECLKDIV_EDIVLD_MASK 128U +#define ECLKDIV_EDIV_MASK 63U +#define ECLKDIV_EDIV_BITNUM 0U + + +/*** ECNFG - EEPROM Configuration Register; 0x00000113 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte CCIE :1; /* Command Complete Interrupt Enable */ + byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ + } Bits; +} ECNFGSTR; +extern volatile ECNFGSTR _ECNFG @(REG_BASE + 0x00000113UL); +#define ECNFG _ECNFG.Byte +#define ECNFG_CCIE _ECNFG.Bits.CCIE +#define ECNFG_CBEIE _ECNFG.Bits.CBEIE + +#define ECNFG_CCIE_MASK 64U +#define ECNFG_CBEIE_MASK 128U + + +/*** EPROT - EEPROM Protection Register; 0x00000114 ***/ +typedef union { + byte Byte; + struct { + byte EP0 :1; /* EEPROM Protection address size 0 */ + byte EP1 :1; /* EEPROM Protection address size 1 */ + byte EP2 :1; /* EEPROM Protection address size 2 */ + byte EPDIS :1; /* EEPROM Protection disable */ + byte NV4 :1; /* Non Volatile Flag Bit 4 */ + byte NV5 :1; /* Non Volatile Flag Bit 5 */ + byte NV6 :1; /* Non Volatile Flag Bit 6 */ + byte EPOPEN :1; /* Opens the EEPROM block or a subsection of it for program or erase */ + } Bits; + struct { + byte grpEP :3; + byte :1; + byte grpNV_4 :3; + byte :1; + } MergedBits; +} EPROTSTR; +extern volatile EPROTSTR _EPROT @(REG_BASE + 0x00000114UL); +#define EPROT _EPROT.Byte +#define EPROT_EP0 _EPROT.Bits.EP0 +#define EPROT_EP1 _EPROT.Bits.EP1 +#define EPROT_EP2 _EPROT.Bits.EP2 +#define EPROT_EPDIS _EPROT.Bits.EPDIS +#define EPROT_NV4 _EPROT.Bits.NV4 +#define EPROT_NV5 _EPROT.Bits.NV5 +#define EPROT_NV6 _EPROT.Bits.NV6 +#define EPROT_EPOPEN _EPROT.Bits.EPOPEN +#define EPROT_EP _EPROT.MergedBits.grpEP +#define EPROT_NV_4 _EPROT.MergedBits.grpNV_4 +#define EPROT_NV EPROT_NV_4 + +#define EPROT_EP0_MASK 1U +#define EPROT_EP1_MASK 2U +#define EPROT_EP2_MASK 4U +#define EPROT_EPDIS_MASK 8U +#define EPROT_NV4_MASK 16U +#define EPROT_NV5_MASK 32U +#define EPROT_NV6_MASK 64U +#define EPROT_EPOPEN_MASK 128U +#define EPROT_EP_MASK 7U +#define EPROT_EP_BITNUM 0U +#define EPROT_NV_4_MASK 112U +#define EPROT_NV_4_BITNUM 4U + + +/*** ESTAT - EEPROM Status Register; 0x00000115 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BLANK :1; /* Blank Verify Flag */ + byte :1; + byte ACCERR :1; /* Access error */ + byte PVIOL :1; /* Protection violation */ + byte CCIF :1; /* Command Complete Interrupt Flag */ + byte CBEIF :1; /* Command Buffer Empty Interrupt Flag */ + } Bits; +} ESTATSTR; +extern volatile ESTATSTR _ESTAT @(REG_BASE + 0x00000115UL); +#define ESTAT _ESTAT.Byte +#define ESTAT_BLANK _ESTAT.Bits.BLANK +#define ESTAT_ACCERR _ESTAT.Bits.ACCERR +#define ESTAT_PVIOL _ESTAT.Bits.PVIOL +#define ESTAT_CCIF _ESTAT.Bits.CCIF +#define ESTAT_CBEIF _ESTAT.Bits.CBEIF + +#define ESTAT_BLANK_MASK 4U +#define ESTAT_ACCERR_MASK 16U +#define ESTAT_PVIOL_MASK 32U +#define ESTAT_CCIF_MASK 64U +#define ESTAT_CBEIF_MASK 128U + + +/*** ECMD - EEPROM Command Buffer and Register; 0x00000116 ***/ +typedef union { + byte Byte; + struct { + byte CMDB0 :1; /* EEPROM User Mode Command 0 */ + byte :1; + byte CMDB2 :1; /* EEPROM User Mode Command 2 */ + byte :1; + byte :1; + byte CMDB5 :1; /* EEPROM User Mode Command 5 */ + byte CMDB6 :1; /* EEPROM User Mode Command 6 */ + byte :1; + } Bits; + struct { + byte grpCMDB :1; + byte :1; + byte grpCMDB_2 :1; + byte :1; + byte :1; + byte grpCMDB_5 :2; + byte :1; + } MergedBits; +} ECMDSTR; +extern volatile ECMDSTR _ECMD @(REG_BASE + 0x00000116UL); +#define ECMD _ECMD.Byte +#define ECMD_CMDB0 _ECMD.Bits.CMDB0 +#define ECMD_CMDB2 _ECMD.Bits.CMDB2 +#define ECMD_CMDB5 _ECMD.Bits.CMDB5 +#define ECMD_CMDB6 _ECMD.Bits.CMDB6 +#define ECMD_CMDB_5 _ECMD.MergedBits.grpCMDB_5 +#define ECMD_CMDB ECMD_CMDB_5 + +#define ECMD_CMDB0_MASK 1U +#define ECMD_CMDB2_MASK 4U +#define ECMD_CMDB5_MASK 32U +#define ECMD_CMDB6_MASK 64U +#define ECMD_CMDB_5_MASK 96U +#define ECMD_CMDB_5_BITNUM 5U + + +/*** ATD1CTL23 - ATD 1 Control Register 23; 0x00000122 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1CTL2 - ATD 1 Control Register 2; 0x00000122 ***/ + union { + byte Byte; + struct { + byte ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */ + byte ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */ + byte ETRIGE :1; /* External Trigger Mode enable */ + byte ETRIGP :1; /* External Trigger Polarity */ + byte ETRIGLE :1; /* External Trigger Level/Edge control */ + byte AWAI :1; /* ATD Power Down in Wait Mode */ + byte AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ + byte ADPU :1; /* ATD Disable / Power Down */ + } Bits; + } ATD1CTL2STR; + #define ATD1CTL2 _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Byte + #define ATD1CTL2_ASCIF _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIF + #define ATD1CTL2_ASCIE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIE + #define ATD1CTL2_ETRIGE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGE + #define ATD1CTL2_ETRIGP _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGP + #define ATD1CTL2_ETRIGLE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGLE + #define ATD1CTL2_AWAI _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AWAI + #define ATD1CTL2_AFFC _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AFFC + #define ATD1CTL2_ADPU _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ADPU + + #define ATD1CTL2_ASCIF_MASK 1U + #define ATD1CTL2_ASCIE_MASK 2U + #define ATD1CTL2_ETRIGE_MASK 4U + #define ATD1CTL2_ETRIGP_MASK 8U + #define ATD1CTL2_ETRIGLE_MASK 16U + #define ATD1CTL2_AWAI_MASK 32U + #define ATD1CTL2_AFFC_MASK 64U + #define ATD1CTL2_ADPU_MASK 128U + + + /*** ATD1CTL3 - ATD 1 Control Register 3; 0x00000123 ***/ + union { + byte Byte; + struct { + byte FRZ0 :1; /* Background Debug Freeze Enable Bit 0 */ + byte FRZ1 :1; /* Background Debug Freeze Enable Bit 1 */ + byte FIFO :1; /* Result Register FIFO Mode */ + byte S1C :1; /* Conversion Sequence Length 1 */ + byte S2C :1; /* Conversion Sequence Length 2 */ + byte S4C :1; /* Conversion Sequence Length 4 */ + byte S8C :1; /* Conversion Sequence Length 8 */ + byte :1; + } Bits; + struct { + byte grpFRZ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATD1CTL3STR; + #define ATD1CTL3 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Byte + #define ATD1CTL3_FRZ0 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ0 + #define ATD1CTL3_FRZ1 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ1 + #define ATD1CTL3_FIFO _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FIFO + #define ATD1CTL3_S1C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S1C + #define ATD1CTL3_S2C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S2C + #define ATD1CTL3_S4C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S4C + #define ATD1CTL3_S8C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S8C + #define ATD1CTL3_FRZ _ATD1CTL23.Overlap_STR.ATD1CTL3STR.MergedBits.grpFRZ + + #define ATD1CTL3_FRZ0_MASK 1U + #define ATD1CTL3_FRZ1_MASK 2U + #define ATD1CTL3_FIFO_MASK 4U + #define ATD1CTL3_S1C_MASK 8U + #define ATD1CTL3_S2C_MASK 16U + #define ATD1CTL3_S4C_MASK 32U + #define ATD1CTL3_S8C_MASK 64U + #define ATD1CTL3_FRZ_MASK 3U + #define ATD1CTL3_FRZ_BITNUM 0U + + } Overlap_STR; + + struct { + word FRZ0 :1; /* Background Debug Freeze Enable Bit 0 */ + word FRZ1 :1; /* Background Debug Freeze Enable Bit 1 */ + word FIFO :1; /* Result Register FIFO Mode */ + word S1C :1; /* Conversion Sequence Length 1 */ + word S2C :1; /* Conversion Sequence Length 2 */ + word S4C :1; /* Conversion Sequence Length 4 */ + word S8C :1; /* Conversion Sequence Length 8 */ + word :1; + word ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */ + word ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */ + word ETRIGE :1; /* External Trigger Mode enable */ + word ETRIGP :1; /* External Trigger Polarity */ + word ETRIGLE :1; /* External Trigger Level/Edge control */ + word AWAI :1; /* ATD Power Down in Wait Mode */ + word AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ + word ADPU :1; /* ATD Disable / Power Down */ + } Bits; + struct { + word grpFRZ :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} ATD1CTL23STR; +extern volatile ATD1CTL23STR _ATD1CTL23 @(REG_BASE + 0x00000122UL); +#define ATD1CTL23 _ATD1CTL23.Word +#define ATD1CTL23_FRZ0 _ATD1CTL23.Bits.FRZ0 +#define ATD1CTL23_FRZ1 _ATD1CTL23.Bits.FRZ1 +#define ATD1CTL23_FIFO _ATD1CTL23.Bits.FIFO +#define ATD1CTL23_S1C _ATD1CTL23.Bits.S1C +#define ATD1CTL23_S2C _ATD1CTL23.Bits.S2C +#define ATD1CTL23_S4C _ATD1CTL23.Bits.S4C +#define ATD1CTL23_S8C _ATD1CTL23.Bits.S8C +#define ATD1CTL23_ASCIF _ATD1CTL23.Bits.ASCIF +#define ATD1CTL23_ASCIE _ATD1CTL23.Bits.ASCIE +#define ATD1CTL23_ETRIGE _ATD1CTL23.Bits.ETRIGE +#define ATD1CTL23_ETRIGP _ATD1CTL23.Bits.ETRIGP +#define ATD1CTL23_ETRIGLE _ATD1CTL23.Bits.ETRIGLE +#define ATD1CTL23_AWAI _ATD1CTL23.Bits.AWAI +#define ATD1CTL23_AFFC _ATD1CTL23.Bits.AFFC +#define ATD1CTL23_ADPU _ATD1CTL23.Bits.ADPU +#define ATD1CTL23_FRZ _ATD1CTL23.MergedBits.grpFRZ + +#define ATD1CTL23_FRZ0_MASK 1U +#define ATD1CTL23_FRZ1_MASK 2U +#define ATD1CTL23_FIFO_MASK 4U +#define ATD1CTL23_S1C_MASK 8U +#define ATD1CTL23_S2C_MASK 16U +#define ATD1CTL23_S4C_MASK 32U +#define ATD1CTL23_S8C_MASK 64U +#define ATD1CTL23_ASCIF_MASK 256U +#define ATD1CTL23_ASCIE_MASK 512U +#define ATD1CTL23_ETRIGE_MASK 1024U +#define ATD1CTL23_ETRIGP_MASK 2048U +#define ATD1CTL23_ETRIGLE_MASK 4096U +#define ATD1CTL23_AWAI_MASK 8192U +#define ATD1CTL23_AFFC_MASK 16384U +#define ATD1CTL23_ADPU_MASK 32768U +#define ATD1CTL23_FRZ_MASK 3U +#define ATD1CTL23_FRZ_BITNUM 0U + + +/*** ATD1CTL45 - ATD 1 Control Register 45; 0x00000124 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1CTL4 - ATD 1 Control Register 4; 0x00000124 ***/ + union { + byte Byte; + struct { + byte PRS0 :1; /* ATD Clock Prescaler 0 */ + byte PRS1 :1; /* ATD Clock Prescaler 1 */ + byte PRS2 :1; /* ATD Clock Prescaler 2 */ + byte PRS3 :1; /* ATD Clock Prescaler 3 */ + byte PRS4 :1; /* ATD Clock Prescaler 4 */ + byte SMP0 :1; /* Sample Time Select 0 */ + byte SMP1 :1; /* Sample Time Select 1 */ + byte SRES8 :1; /* ATD Resolution Select */ + } Bits; + struct { + byte grpPRS :5; + byte grpSMP :2; + byte grpSRES_8 :1; + } MergedBits; + } ATD1CTL4STR; + #define ATD1CTL4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Byte + #define ATD1CTL4_PRS0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS0 + #define ATD1CTL4_PRS1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS1 + #define ATD1CTL4_PRS2 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS2 + #define ATD1CTL4_PRS3 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS3 + #define ATD1CTL4_PRS4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS4 + #define ATD1CTL4_SMP0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP0 + #define ATD1CTL4_SMP1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP1 + #define ATD1CTL4_SRES8 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SRES8 + #define ATD1CTL4_PRS _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpPRS + #define ATD1CTL4_SMP _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpSMP + + #define ATD1CTL4_PRS0_MASK 1U + #define ATD1CTL4_PRS1_MASK 2U + #define ATD1CTL4_PRS2_MASK 4U + #define ATD1CTL4_PRS3_MASK 8U + #define ATD1CTL4_PRS4_MASK 16U + #define ATD1CTL4_SMP0_MASK 32U + #define ATD1CTL4_SMP1_MASK 64U + #define ATD1CTL4_SRES8_MASK 128U + #define ATD1CTL4_PRS_MASK 31U + #define ATD1CTL4_PRS_BITNUM 0U + #define ATD1CTL4_SMP_MASK 96U + #define ATD1CTL4_SMP_BITNUM 5U + + + /*** ATD1CTL5 - ATD 1 Control Register 5; 0x00000125 ***/ + union { + byte Byte; + struct { + byte CA :1; /* Analog Input Channel Select Code A */ + byte CB :1; /* Analog Input Channel Select Code B */ + byte CC :1; /* Analog Input Channel Select Code C */ + byte :1; + byte MULT :1; /* Multi-Channel Sample Mode */ + byte SCAN :1; /* Continuous Conversion Sequence Mode */ + byte DSGN :1; /* Signed/Unsigned Result Data Mode */ + byte DJM :1; /* Result Register Data Justification Mode */ + } Bits; + struct { + byte grpCx :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATD1CTL5STR; + #define ATD1CTL5 _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Byte + #define ATD1CTL5_CA _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CA + #define ATD1CTL5_CB _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CB + #define ATD1CTL5_CC _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CC + #define ATD1CTL5_MULT _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.MULT + #define ATD1CTL5_SCAN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.SCAN + #define ATD1CTL5_DSGN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DSGN + #define ATD1CTL5_DJM _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DJM + #define ATD1CTL5_Cx _ATD1CTL45.Overlap_STR.ATD1CTL5STR.MergedBits.grpCx + + #define ATD1CTL5_CA_MASK 1U + #define ATD1CTL5_CB_MASK 2U + #define ATD1CTL5_CC_MASK 4U + #define ATD1CTL5_MULT_MASK 16U + #define ATD1CTL5_SCAN_MASK 32U + #define ATD1CTL5_DSGN_MASK 64U + #define ATD1CTL5_DJM_MASK 128U + #define ATD1CTL5_Cx_MASK 7U + #define ATD1CTL5_Cx_BITNUM 0U + + } Overlap_STR; + + struct { + word CA :1; /* Analog Input Channel Select Code A */ + word CB :1; /* Analog Input Channel Select Code B */ + word CC :1; /* Analog Input Channel Select Code C */ + word :1; + word MULT :1; /* Multi-Channel Sample Mode */ + word SCAN :1; /* Continuous Conversion Sequence Mode */ + word DSGN :1; /* Signed/Unsigned Result Data Mode */ + word DJM :1; /* Result Register Data Justification Mode */ + word PRS0 :1; /* ATD Clock Prescaler 0 */ + word PRS1 :1; /* ATD Clock Prescaler 1 */ + word PRS2 :1; /* ATD Clock Prescaler 2 */ + word PRS3 :1; /* ATD Clock Prescaler 3 */ + word PRS4 :1; /* ATD Clock Prescaler 4 */ + word SMP0 :1; /* Sample Time Select 0 */ + word SMP1 :1; /* Sample Time Select 1 */ + word SRES8 :1; /* ATD Resolution Select */ + } Bits; + struct { + word grpCx :3; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpPRS :5; + word grpSMP :2; + word grpSRES_8 :1; + } MergedBits; +} ATD1CTL45STR; +extern volatile ATD1CTL45STR _ATD1CTL45 @(REG_BASE + 0x00000124UL); +#define ATD1CTL45 _ATD1CTL45.Word +#define ATD1CTL45_CA _ATD1CTL45.Bits.CA +#define ATD1CTL45_CB _ATD1CTL45.Bits.CB +#define ATD1CTL45_CC _ATD1CTL45.Bits.CC +#define ATD1CTL45_MULT _ATD1CTL45.Bits.MULT +#define ATD1CTL45_SCAN _ATD1CTL45.Bits.SCAN +#define ATD1CTL45_DSGN _ATD1CTL45.Bits.DSGN +#define ATD1CTL45_DJM _ATD1CTL45.Bits.DJM +#define ATD1CTL45_PRS0 _ATD1CTL45.Bits.PRS0 +#define ATD1CTL45_PRS1 _ATD1CTL45.Bits.PRS1 +#define ATD1CTL45_PRS2 _ATD1CTL45.Bits.PRS2 +#define ATD1CTL45_PRS3 _ATD1CTL45.Bits.PRS3 +#define ATD1CTL45_PRS4 _ATD1CTL45.Bits.PRS4 +#define ATD1CTL45_SMP0 _ATD1CTL45.Bits.SMP0 +#define ATD1CTL45_SMP1 _ATD1CTL45.Bits.SMP1 +#define ATD1CTL45_SRES8 _ATD1CTL45.Bits.SRES8 +#define ATD1CTL45_Cx _ATD1CTL45.MergedBits.grpCx +#define ATD1CTL45_PRS _ATD1CTL45.MergedBits.grpPRS +#define ATD1CTL45_SMP _ATD1CTL45.MergedBits.grpSMP + +#define ATD1CTL45_CA_MASK 1U +#define ATD1CTL45_CB_MASK 2U +#define ATD1CTL45_CC_MASK 4U +#define ATD1CTL45_MULT_MASK 16U +#define ATD1CTL45_SCAN_MASK 32U +#define ATD1CTL45_DSGN_MASK 64U +#define ATD1CTL45_DJM_MASK 128U +#define ATD1CTL45_PRS0_MASK 256U +#define ATD1CTL45_PRS1_MASK 512U +#define ATD1CTL45_PRS2_MASK 1024U +#define ATD1CTL45_PRS3_MASK 2048U +#define ATD1CTL45_PRS4_MASK 4096U +#define ATD1CTL45_SMP0_MASK 8192U +#define ATD1CTL45_SMP1_MASK 16384U +#define ATD1CTL45_SRES8_MASK 32768U +#define ATD1CTL45_Cx_MASK 7U +#define ATD1CTL45_Cx_BITNUM 0U +#define ATD1CTL45_PRS_MASK 7936U +#define ATD1CTL45_PRS_BITNUM 8U +#define ATD1CTL45_SMP_MASK 24576U +#define ATD1CTL45_SMP_BITNUM 13U + + +/*** ATD1STAT0 - ATD 1 Status Register 0; 0x00000126 ***/ +typedef union { + byte Byte; + struct { + byte CC0 :1; /* Conversion Counter 0 */ + byte CC1 :1; /* Conversion Counter 1 */ + byte CC2 :1; /* Conversion Counter 2 */ + byte :1; + byte FIFOR :1; /* FIFO Over Run Flag */ + byte ETORF :1; /* External Trigger Overrun Flag */ + byte :1; + byte SCF :1; /* Sequence Complete Flag */ + } Bits; + struct { + byte grpCC :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ATD1STAT0STR; +extern volatile ATD1STAT0STR _ATD1STAT0 @(REG_BASE + 0x00000126UL); +#define ATD1STAT0 _ATD1STAT0.Byte +#define ATD1STAT0_CC0 _ATD1STAT0.Bits.CC0 +#define ATD1STAT0_CC1 _ATD1STAT0.Bits.CC1 +#define ATD1STAT0_CC2 _ATD1STAT0.Bits.CC2 +#define ATD1STAT0_FIFOR _ATD1STAT0.Bits.FIFOR +#define ATD1STAT0_ETORF _ATD1STAT0.Bits.ETORF +#define ATD1STAT0_SCF _ATD1STAT0.Bits.SCF +#define ATD1STAT0_CC _ATD1STAT0.MergedBits.grpCC + +#define ATD1STAT0_CC0_MASK 1U +#define ATD1STAT0_CC1_MASK 2U +#define ATD1STAT0_CC2_MASK 4U +#define ATD1STAT0_FIFOR_MASK 16U +#define ATD1STAT0_ETORF_MASK 32U +#define ATD1STAT0_SCF_MASK 128U +#define ATD1STAT0_CC_MASK 7U +#define ATD1STAT0_CC_BITNUM 0U + + +/*** ATD1TEST1 - ATD1 Test Register; 0x00000129 ***/ +typedef union { + byte Byte; + struct { + byte SC :1; /* Special Channel Conversion Bit */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} ATD1TEST1STR; +extern volatile ATD1TEST1STR _ATD1TEST1 @(REG_BASE + 0x00000129UL); +#define ATD1TEST1 _ATD1TEST1.Byte +#define ATD1TEST1_SC _ATD1TEST1.Bits.SC + +#define ATD1TEST1_SC_MASK 1U + + +/*** ATD1STAT1 - ATD 1 Status Register 1; 0x0000012B ***/ +typedef union { + byte Byte; + struct { + byte CCF0 :1; /* Conversion Complete Flag 0 */ + byte CCF1 :1; /* Conversion Complete Flag 1 */ + byte CCF2 :1; /* Conversion Complete Flag 2 */ + byte CCF3 :1; /* Conversion Complete Flag 3 */ + byte CCF4 :1; /* Conversion Complete Flag 4 */ + byte CCF5 :1; /* Conversion Complete Flag 5 */ + byte CCF6 :1; /* Conversion Complete Flag 6 */ + byte CCF7 :1; /* Conversion Complete Flag 7 */ + } Bits; +} ATD1STAT1STR; +extern volatile ATD1STAT1STR _ATD1STAT1 @(REG_BASE + 0x0000012BUL); +#define ATD1STAT1 _ATD1STAT1.Byte +#define ATD1STAT1_CCF0 _ATD1STAT1.Bits.CCF0 +#define ATD1STAT1_CCF1 _ATD1STAT1.Bits.CCF1 +#define ATD1STAT1_CCF2 _ATD1STAT1.Bits.CCF2 +#define ATD1STAT1_CCF3 _ATD1STAT1.Bits.CCF3 +#define ATD1STAT1_CCF4 _ATD1STAT1.Bits.CCF4 +#define ATD1STAT1_CCF5 _ATD1STAT1.Bits.CCF5 +#define ATD1STAT1_CCF6 _ATD1STAT1.Bits.CCF6 +#define ATD1STAT1_CCF7 _ATD1STAT1.Bits.CCF7 + +#define ATD1STAT1_CCF0_MASK 1U +#define ATD1STAT1_CCF1_MASK 2U +#define ATD1STAT1_CCF2_MASK 4U +#define ATD1STAT1_CCF3_MASK 8U +#define ATD1STAT1_CCF4_MASK 16U +#define ATD1STAT1_CCF5_MASK 32U +#define ATD1STAT1_CCF6_MASK 64U +#define ATD1STAT1_CCF7_MASK 128U + + +/*** ATD1DIEN - ATD 1 Input Enable Register; 0x0000012D ***/ +typedef union { + byte Byte; + struct { + byte IEN0 :1; /* ATD Digital Input Enable on channel 0 */ + byte IEN1 :1; /* ATD Digital Input Enable on channel 1 */ + byte IEN2 :1; /* ATD Digital Input Enable on channel 2 */ + byte IEN3 :1; /* ATD Digital Input Enable on channel 3 */ + byte IEN4 :1; /* ATD Digital Input Enable on channel 4 */ + byte IEN5 :1; /* ATD Digital Input Enable on channel 5 */ + byte IEN6 :1; /* ATD Digital Input Enable on channel 6 */ + byte IEN7 :1; /* ATD Digital Input Enable on channel 7 */ + } Bits; +} ATD1DIENSTR; +extern volatile ATD1DIENSTR _ATD1DIEN @(REG_BASE + 0x0000012DUL); +#define ATD1DIEN _ATD1DIEN.Byte +#define ATD1DIEN_IEN0 _ATD1DIEN.Bits.IEN0 +#define ATD1DIEN_IEN1 _ATD1DIEN.Bits.IEN1 +#define ATD1DIEN_IEN2 _ATD1DIEN.Bits.IEN2 +#define ATD1DIEN_IEN3 _ATD1DIEN.Bits.IEN3 +#define ATD1DIEN_IEN4 _ATD1DIEN.Bits.IEN4 +#define ATD1DIEN_IEN5 _ATD1DIEN.Bits.IEN5 +#define ATD1DIEN_IEN6 _ATD1DIEN.Bits.IEN6 +#define ATD1DIEN_IEN7 _ATD1DIEN.Bits.IEN7 + +#define ATD1DIEN_IEN0_MASK 1U +#define ATD1DIEN_IEN1_MASK 2U +#define ATD1DIEN_IEN2_MASK 4U +#define ATD1DIEN_IEN3_MASK 8U +#define ATD1DIEN_IEN4_MASK 16U +#define ATD1DIEN_IEN5_MASK 32U +#define ATD1DIEN_IEN6_MASK 64U +#define ATD1DIEN_IEN7_MASK 128U + + +/*** PORTAD1 - Port AD1 Register; 0x0000012F ***/ +typedef union { + byte Byte; + struct { + byte PTAD0 :1; /* A/D Channel 0 (AN0) Digital Input */ + byte PTAD1 :1; /* A/D Channel 1 (AN1) Digital Input */ + byte PTAD2 :1; /* A/D Channel 2 (AN2) Digital Input */ + byte PTAD3 :1; /* A/D Channel 3 (AN3) Digital Input */ + byte PTAD4 :1; /* A/D Channel 4 (AN4) Digital Input */ + byte PTAD5 :1; /* A/D Channel 5 (AN5) Digital Input */ + byte PTAD6 :1; /* A/D Channel 6 (AN6) Digital Input */ + byte PTAD7 :1; /* A/D Channel 7 (AN7) Digital Input */ + } Bits; +} PORTAD1STR; +extern volatile PORTAD1STR _PORTAD1 @(REG_BASE + 0x0000012FUL); +#define PORTAD1 _PORTAD1.Byte +#define PORTAD1_PTAD0 _PORTAD1.Bits.PTAD0 +#define PORTAD1_PTAD1 _PORTAD1.Bits.PTAD1 +#define PORTAD1_PTAD2 _PORTAD1.Bits.PTAD2 +#define PORTAD1_PTAD3 _PORTAD1.Bits.PTAD3 +#define PORTAD1_PTAD4 _PORTAD1.Bits.PTAD4 +#define PORTAD1_PTAD5 _PORTAD1.Bits.PTAD5 +#define PORTAD1_PTAD6 _PORTAD1.Bits.PTAD6 +#define PORTAD1_PTAD7 _PORTAD1.Bits.PTAD7 + +#define PORTAD1_PTAD0_MASK 1U +#define PORTAD1_PTAD1_MASK 2U +#define PORTAD1_PTAD2_MASK 4U +#define PORTAD1_PTAD3_MASK 8U +#define PORTAD1_PTAD4_MASK 16U +#define PORTAD1_PTAD5_MASK 32U +#define PORTAD1_PTAD6_MASK 64U +#define PORTAD1_PTAD7_MASK 128U + + +/*** ATD1DR0 - ATD 1 Conversion Result Register 0; 0x00000130 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR0H - ATD 1 Conversion Result Register 0 High; 0x00000130 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR0HSTR; + #define ATD1DR0H _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Byte + #define ATD1DR0H_BIT8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT8 + #define ATD1DR0H_BIT9 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT9 + #define ATD1DR0H_BIT10 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT10 + #define ATD1DR0H_BIT11 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT11 + #define ATD1DR0H_BIT12 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT12 + #define ATD1DR0H_BIT13 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT13 + #define ATD1DR0H_BIT14 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT14 + #define ATD1DR0H_BIT15 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT15 + + #define ATD1DR0H_BIT8_MASK 1U + #define ATD1DR0H_BIT9_MASK 2U + #define ATD1DR0H_BIT10_MASK 4U + #define ATD1DR0H_BIT11_MASK 8U + #define ATD1DR0H_BIT12_MASK 16U + #define ATD1DR0H_BIT13_MASK 32U + #define ATD1DR0H_BIT14_MASK 64U + #define ATD1DR0H_BIT15_MASK 128U + + + /*** ATD1DR0L - ATD 1 Conversion Result Register 0 Low; 0x00000131 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR0LSTR; + #define ATD1DR0L _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Byte + #define ATD1DR0L_BIT6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT6 + #define ATD1DR0L_BIT7 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT7 + #define ATD1DR0L_BIT_6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.MergedBits.grpBIT_6 + #define ATD1DR0L_BIT ATD1DR0L_BIT_6 + + #define ATD1DR0L_BIT6_MASK 64U + #define ATD1DR0L_BIT7_MASK 128U + #define ATD1DR0L_BIT_6_MASK 192U + #define ATD1DR0L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR0STR; +extern volatile ATD1DR0STR _ATD1DR0 @(REG_BASE + 0x00000130UL); +#define ATD1DR0 _ATD1DR0.Word +#define ATD1DR0_BIT6 _ATD1DR0.Bits.BIT6 +#define ATD1DR0_BIT7 _ATD1DR0.Bits.BIT7 +#define ATD1DR0_BIT8 _ATD1DR0.Bits.BIT8 +#define ATD1DR0_BIT9 _ATD1DR0.Bits.BIT9 +#define ATD1DR0_BIT10 _ATD1DR0.Bits.BIT10 +#define ATD1DR0_BIT11 _ATD1DR0.Bits.BIT11 +#define ATD1DR0_BIT12 _ATD1DR0.Bits.BIT12 +#define ATD1DR0_BIT13 _ATD1DR0.Bits.BIT13 +#define ATD1DR0_BIT14 _ATD1DR0.Bits.BIT14 +#define ATD1DR0_BIT15 _ATD1DR0.Bits.BIT15 +/* ATD1DR_ARR: Access 8 ATD1DRx registers in an array */ +#define ATD1DR_ARR ((volatile word *) &ATD1DR0) +#define ATD1DR0_BIT_6 _ATD1DR0.MergedBits.grpBIT_6 +#define ATD1DR0_BIT ATD1DR0_BIT_6 + +#define ATD1DR0_BIT6_MASK 64U +#define ATD1DR0_BIT7_MASK 128U +#define ATD1DR0_BIT8_MASK 256U +#define ATD1DR0_BIT9_MASK 512U +#define ATD1DR0_BIT10_MASK 1024U +#define ATD1DR0_BIT11_MASK 2048U +#define ATD1DR0_BIT12_MASK 4096U +#define ATD1DR0_BIT13_MASK 8192U +#define ATD1DR0_BIT14_MASK 16384U +#define ATD1DR0_BIT15_MASK 32768U +#define ATD1DR0_BIT_6_MASK 65472U +#define ATD1DR0_BIT_6_BITNUM 6U + + +/*** ATD1DR1 - ATD 1 Conversion Result Register 1; 0x00000132 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR1H - ATD 1 Conversion Result Register 1 High; 0x00000132 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR1HSTR; + #define ATD1DR1H _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Byte + #define ATD1DR1H_BIT8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT8 + #define ATD1DR1H_BIT9 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT9 + #define ATD1DR1H_BIT10 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT10 + #define ATD1DR1H_BIT11 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT11 + #define ATD1DR1H_BIT12 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT12 + #define ATD1DR1H_BIT13 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT13 + #define ATD1DR1H_BIT14 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT14 + #define ATD1DR1H_BIT15 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT15 + + #define ATD1DR1H_BIT8_MASK 1U + #define ATD1DR1H_BIT9_MASK 2U + #define ATD1DR1H_BIT10_MASK 4U + #define ATD1DR1H_BIT11_MASK 8U + #define ATD1DR1H_BIT12_MASK 16U + #define ATD1DR1H_BIT13_MASK 32U + #define ATD1DR1H_BIT14_MASK 64U + #define ATD1DR1H_BIT15_MASK 128U + + + /*** ATD1DR1L - ATD 1 Conversion Result Register 1 Low; 0x00000133 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR1LSTR; + #define ATD1DR1L _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Byte + #define ATD1DR1L_BIT6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT6 + #define ATD1DR1L_BIT7 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT7 + #define ATD1DR1L_BIT_6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.MergedBits.grpBIT_6 + #define ATD1DR1L_BIT ATD1DR1L_BIT_6 + + #define ATD1DR1L_BIT6_MASK 64U + #define ATD1DR1L_BIT7_MASK 128U + #define ATD1DR1L_BIT_6_MASK 192U + #define ATD1DR1L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR1STR; +extern volatile ATD1DR1STR _ATD1DR1 @(REG_BASE + 0x00000132UL); +#define ATD1DR1 _ATD1DR1.Word +#define ATD1DR1_BIT6 _ATD1DR1.Bits.BIT6 +#define ATD1DR1_BIT7 _ATD1DR1.Bits.BIT7 +#define ATD1DR1_BIT8 _ATD1DR1.Bits.BIT8 +#define ATD1DR1_BIT9 _ATD1DR1.Bits.BIT9 +#define ATD1DR1_BIT10 _ATD1DR1.Bits.BIT10 +#define ATD1DR1_BIT11 _ATD1DR1.Bits.BIT11 +#define ATD1DR1_BIT12 _ATD1DR1.Bits.BIT12 +#define ATD1DR1_BIT13 _ATD1DR1.Bits.BIT13 +#define ATD1DR1_BIT14 _ATD1DR1.Bits.BIT14 +#define ATD1DR1_BIT15 _ATD1DR1.Bits.BIT15 +#define ATD1DR1_BIT_6 _ATD1DR1.MergedBits.grpBIT_6 +#define ATD1DR1_BIT ATD1DR1_BIT_6 + +#define ATD1DR1_BIT6_MASK 64U +#define ATD1DR1_BIT7_MASK 128U +#define ATD1DR1_BIT8_MASK 256U +#define ATD1DR1_BIT9_MASK 512U +#define ATD1DR1_BIT10_MASK 1024U +#define ATD1DR1_BIT11_MASK 2048U +#define ATD1DR1_BIT12_MASK 4096U +#define ATD1DR1_BIT13_MASK 8192U +#define ATD1DR1_BIT14_MASK 16384U +#define ATD1DR1_BIT15_MASK 32768U +#define ATD1DR1_BIT_6_MASK 65472U +#define ATD1DR1_BIT_6_BITNUM 6U + + +/*** ATD1DR2 - ATD 1 Conversion Result Register 2; 0x00000134 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR2H - ATD 1 Conversion Result Register 2 High; 0x00000134 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR2HSTR; + #define ATD1DR2H _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Byte + #define ATD1DR2H_BIT8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT8 + #define ATD1DR2H_BIT9 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT9 + #define ATD1DR2H_BIT10 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT10 + #define ATD1DR2H_BIT11 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT11 + #define ATD1DR2H_BIT12 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT12 + #define ATD1DR2H_BIT13 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT13 + #define ATD1DR2H_BIT14 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT14 + #define ATD1DR2H_BIT15 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT15 + + #define ATD1DR2H_BIT8_MASK 1U + #define ATD1DR2H_BIT9_MASK 2U + #define ATD1DR2H_BIT10_MASK 4U + #define ATD1DR2H_BIT11_MASK 8U + #define ATD1DR2H_BIT12_MASK 16U + #define ATD1DR2H_BIT13_MASK 32U + #define ATD1DR2H_BIT14_MASK 64U + #define ATD1DR2H_BIT15_MASK 128U + + + /*** ATD1DR2L - ATD 1 Conversion Result Register 2 Low; 0x00000135 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR2LSTR; + #define ATD1DR2L _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Byte + #define ATD1DR2L_BIT6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT6 + #define ATD1DR2L_BIT7 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT7 + #define ATD1DR2L_BIT_6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.MergedBits.grpBIT_6 + #define ATD1DR2L_BIT ATD1DR2L_BIT_6 + + #define ATD1DR2L_BIT6_MASK 64U + #define ATD1DR2L_BIT7_MASK 128U + #define ATD1DR2L_BIT_6_MASK 192U + #define ATD1DR2L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR2STR; +extern volatile ATD1DR2STR _ATD1DR2 @(REG_BASE + 0x00000134UL); +#define ATD1DR2 _ATD1DR2.Word +#define ATD1DR2_BIT6 _ATD1DR2.Bits.BIT6 +#define ATD1DR2_BIT7 _ATD1DR2.Bits.BIT7 +#define ATD1DR2_BIT8 _ATD1DR2.Bits.BIT8 +#define ATD1DR2_BIT9 _ATD1DR2.Bits.BIT9 +#define ATD1DR2_BIT10 _ATD1DR2.Bits.BIT10 +#define ATD1DR2_BIT11 _ATD1DR2.Bits.BIT11 +#define ATD1DR2_BIT12 _ATD1DR2.Bits.BIT12 +#define ATD1DR2_BIT13 _ATD1DR2.Bits.BIT13 +#define ATD1DR2_BIT14 _ATD1DR2.Bits.BIT14 +#define ATD1DR2_BIT15 _ATD1DR2.Bits.BIT15 +#define ATD1DR2_BIT_6 _ATD1DR2.MergedBits.grpBIT_6 +#define ATD1DR2_BIT ATD1DR2_BIT_6 + +#define ATD1DR2_BIT6_MASK 64U +#define ATD1DR2_BIT7_MASK 128U +#define ATD1DR2_BIT8_MASK 256U +#define ATD1DR2_BIT9_MASK 512U +#define ATD1DR2_BIT10_MASK 1024U +#define ATD1DR2_BIT11_MASK 2048U +#define ATD1DR2_BIT12_MASK 4096U +#define ATD1DR2_BIT13_MASK 8192U +#define ATD1DR2_BIT14_MASK 16384U +#define ATD1DR2_BIT15_MASK 32768U +#define ATD1DR2_BIT_6_MASK 65472U +#define ATD1DR2_BIT_6_BITNUM 6U + + +/*** ATD1DR3 - ATD 1 Conversion Result Register 3; 0x00000136 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR3H - ATD 1 Conversion Result Register 3 High; 0x00000136 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR3HSTR; + #define ATD1DR3H _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Byte + #define ATD1DR3H_BIT8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT8 + #define ATD1DR3H_BIT9 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT9 + #define ATD1DR3H_BIT10 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT10 + #define ATD1DR3H_BIT11 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT11 + #define ATD1DR3H_BIT12 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT12 + #define ATD1DR3H_BIT13 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT13 + #define ATD1DR3H_BIT14 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT14 + #define ATD1DR3H_BIT15 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT15 + + #define ATD1DR3H_BIT8_MASK 1U + #define ATD1DR3H_BIT9_MASK 2U + #define ATD1DR3H_BIT10_MASK 4U + #define ATD1DR3H_BIT11_MASK 8U + #define ATD1DR3H_BIT12_MASK 16U + #define ATD1DR3H_BIT13_MASK 32U + #define ATD1DR3H_BIT14_MASK 64U + #define ATD1DR3H_BIT15_MASK 128U + + + /*** ATD1DR3L - ATD 1 Conversion Result Register 3 Low; 0x00000137 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR3LSTR; + #define ATD1DR3L _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Byte + #define ATD1DR3L_BIT6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT6 + #define ATD1DR3L_BIT7 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT7 + #define ATD1DR3L_BIT_6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.MergedBits.grpBIT_6 + #define ATD1DR3L_BIT ATD1DR3L_BIT_6 + + #define ATD1DR3L_BIT6_MASK 64U + #define ATD1DR3L_BIT7_MASK 128U + #define ATD1DR3L_BIT_6_MASK 192U + #define ATD1DR3L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR3STR; +extern volatile ATD1DR3STR _ATD1DR3 @(REG_BASE + 0x00000136UL); +#define ATD1DR3 _ATD1DR3.Word +#define ATD1DR3_BIT6 _ATD1DR3.Bits.BIT6 +#define ATD1DR3_BIT7 _ATD1DR3.Bits.BIT7 +#define ATD1DR3_BIT8 _ATD1DR3.Bits.BIT8 +#define ATD1DR3_BIT9 _ATD1DR3.Bits.BIT9 +#define ATD1DR3_BIT10 _ATD1DR3.Bits.BIT10 +#define ATD1DR3_BIT11 _ATD1DR3.Bits.BIT11 +#define ATD1DR3_BIT12 _ATD1DR3.Bits.BIT12 +#define ATD1DR3_BIT13 _ATD1DR3.Bits.BIT13 +#define ATD1DR3_BIT14 _ATD1DR3.Bits.BIT14 +#define ATD1DR3_BIT15 _ATD1DR3.Bits.BIT15 +#define ATD1DR3_BIT_6 _ATD1DR3.MergedBits.grpBIT_6 +#define ATD1DR3_BIT ATD1DR3_BIT_6 + +#define ATD1DR3_BIT6_MASK 64U +#define ATD1DR3_BIT7_MASK 128U +#define ATD1DR3_BIT8_MASK 256U +#define ATD1DR3_BIT9_MASK 512U +#define ATD1DR3_BIT10_MASK 1024U +#define ATD1DR3_BIT11_MASK 2048U +#define ATD1DR3_BIT12_MASK 4096U +#define ATD1DR3_BIT13_MASK 8192U +#define ATD1DR3_BIT14_MASK 16384U +#define ATD1DR3_BIT15_MASK 32768U +#define ATD1DR3_BIT_6_MASK 65472U +#define ATD1DR3_BIT_6_BITNUM 6U + + +/*** ATD1DR4 - ATD 1 Conversion Result Register 4; 0x00000138 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR4H - ATD 1 Conversion Result Register 4 High; 0x00000138 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR4HSTR; + #define ATD1DR4H _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Byte + #define ATD1DR4H_BIT8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT8 + #define ATD1DR4H_BIT9 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT9 + #define ATD1DR4H_BIT10 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT10 + #define ATD1DR4H_BIT11 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT11 + #define ATD1DR4H_BIT12 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT12 + #define ATD1DR4H_BIT13 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT13 + #define ATD1DR4H_BIT14 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT14 + #define ATD1DR4H_BIT15 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT15 + + #define ATD1DR4H_BIT8_MASK 1U + #define ATD1DR4H_BIT9_MASK 2U + #define ATD1DR4H_BIT10_MASK 4U + #define ATD1DR4H_BIT11_MASK 8U + #define ATD1DR4H_BIT12_MASK 16U + #define ATD1DR4H_BIT13_MASK 32U + #define ATD1DR4H_BIT14_MASK 64U + #define ATD1DR4H_BIT15_MASK 128U + + + /*** ATD1DR4L - ATD 1 Conversion Result Register 4 Low; 0x00000139 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR4LSTR; + #define ATD1DR4L _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Byte + #define ATD1DR4L_BIT6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT6 + #define ATD1DR4L_BIT7 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT7 + #define ATD1DR4L_BIT_6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.MergedBits.grpBIT_6 + #define ATD1DR4L_BIT ATD1DR4L_BIT_6 + + #define ATD1DR4L_BIT6_MASK 64U + #define ATD1DR4L_BIT7_MASK 128U + #define ATD1DR4L_BIT_6_MASK 192U + #define ATD1DR4L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR4STR; +extern volatile ATD1DR4STR _ATD1DR4 @(REG_BASE + 0x00000138UL); +#define ATD1DR4 _ATD1DR4.Word +#define ATD1DR4_BIT6 _ATD1DR4.Bits.BIT6 +#define ATD1DR4_BIT7 _ATD1DR4.Bits.BIT7 +#define ATD1DR4_BIT8 _ATD1DR4.Bits.BIT8 +#define ATD1DR4_BIT9 _ATD1DR4.Bits.BIT9 +#define ATD1DR4_BIT10 _ATD1DR4.Bits.BIT10 +#define ATD1DR4_BIT11 _ATD1DR4.Bits.BIT11 +#define ATD1DR4_BIT12 _ATD1DR4.Bits.BIT12 +#define ATD1DR4_BIT13 _ATD1DR4.Bits.BIT13 +#define ATD1DR4_BIT14 _ATD1DR4.Bits.BIT14 +#define ATD1DR4_BIT15 _ATD1DR4.Bits.BIT15 +#define ATD1DR4_BIT_6 _ATD1DR4.MergedBits.grpBIT_6 +#define ATD1DR4_BIT ATD1DR4_BIT_6 + +#define ATD1DR4_BIT6_MASK 64U +#define ATD1DR4_BIT7_MASK 128U +#define ATD1DR4_BIT8_MASK 256U +#define ATD1DR4_BIT9_MASK 512U +#define ATD1DR4_BIT10_MASK 1024U +#define ATD1DR4_BIT11_MASK 2048U +#define ATD1DR4_BIT12_MASK 4096U +#define ATD1DR4_BIT13_MASK 8192U +#define ATD1DR4_BIT14_MASK 16384U +#define ATD1DR4_BIT15_MASK 32768U +#define ATD1DR4_BIT_6_MASK 65472U +#define ATD1DR4_BIT_6_BITNUM 6U + + +/*** ATD1DR5 - ATD 1 Conversion Result Register 5; 0x0000013A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR5H - ATD 1 Conversion Result Register 5 High; 0x0000013A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR5HSTR; + #define ATD1DR5H _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Byte + #define ATD1DR5H_BIT8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT8 + #define ATD1DR5H_BIT9 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT9 + #define ATD1DR5H_BIT10 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT10 + #define ATD1DR5H_BIT11 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT11 + #define ATD1DR5H_BIT12 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT12 + #define ATD1DR5H_BIT13 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT13 + #define ATD1DR5H_BIT14 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT14 + #define ATD1DR5H_BIT15 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT15 + + #define ATD1DR5H_BIT8_MASK 1U + #define ATD1DR5H_BIT9_MASK 2U + #define ATD1DR5H_BIT10_MASK 4U + #define ATD1DR5H_BIT11_MASK 8U + #define ATD1DR5H_BIT12_MASK 16U + #define ATD1DR5H_BIT13_MASK 32U + #define ATD1DR5H_BIT14_MASK 64U + #define ATD1DR5H_BIT15_MASK 128U + + + /*** ATD1DR5L - ATD 1 Conversion Result Register 5 Low; 0x0000013B ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR5LSTR; + #define ATD1DR5L _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Byte + #define ATD1DR5L_BIT6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT6 + #define ATD1DR5L_BIT7 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT7 + #define ATD1DR5L_BIT_6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.MergedBits.grpBIT_6 + #define ATD1DR5L_BIT ATD1DR5L_BIT_6 + + #define ATD1DR5L_BIT6_MASK 64U + #define ATD1DR5L_BIT7_MASK 128U + #define ATD1DR5L_BIT_6_MASK 192U + #define ATD1DR5L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR5STR; +extern volatile ATD1DR5STR _ATD1DR5 @(REG_BASE + 0x0000013AUL); +#define ATD1DR5 _ATD1DR5.Word +#define ATD1DR5_BIT6 _ATD1DR5.Bits.BIT6 +#define ATD1DR5_BIT7 _ATD1DR5.Bits.BIT7 +#define ATD1DR5_BIT8 _ATD1DR5.Bits.BIT8 +#define ATD1DR5_BIT9 _ATD1DR5.Bits.BIT9 +#define ATD1DR5_BIT10 _ATD1DR5.Bits.BIT10 +#define ATD1DR5_BIT11 _ATD1DR5.Bits.BIT11 +#define ATD1DR5_BIT12 _ATD1DR5.Bits.BIT12 +#define ATD1DR5_BIT13 _ATD1DR5.Bits.BIT13 +#define ATD1DR5_BIT14 _ATD1DR5.Bits.BIT14 +#define ATD1DR5_BIT15 _ATD1DR5.Bits.BIT15 +#define ATD1DR5_BIT_6 _ATD1DR5.MergedBits.grpBIT_6 +#define ATD1DR5_BIT ATD1DR5_BIT_6 + +#define ATD1DR5_BIT6_MASK 64U +#define ATD1DR5_BIT7_MASK 128U +#define ATD1DR5_BIT8_MASK 256U +#define ATD1DR5_BIT9_MASK 512U +#define ATD1DR5_BIT10_MASK 1024U +#define ATD1DR5_BIT11_MASK 2048U +#define ATD1DR5_BIT12_MASK 4096U +#define ATD1DR5_BIT13_MASK 8192U +#define ATD1DR5_BIT14_MASK 16384U +#define ATD1DR5_BIT15_MASK 32768U +#define ATD1DR5_BIT_6_MASK 65472U +#define ATD1DR5_BIT_6_BITNUM 6U + + +/*** ATD1DR6 - ATD 1 Conversion Result Register 6; 0x0000013C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR6H - ATD 1 Conversion Result Register 6 High; 0x0000013C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR6HSTR; + #define ATD1DR6H _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Byte + #define ATD1DR6H_BIT8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT8 + #define ATD1DR6H_BIT9 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT9 + #define ATD1DR6H_BIT10 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT10 + #define ATD1DR6H_BIT11 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT11 + #define ATD1DR6H_BIT12 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT12 + #define ATD1DR6H_BIT13 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT13 + #define ATD1DR6H_BIT14 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT14 + #define ATD1DR6H_BIT15 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT15 + + #define ATD1DR6H_BIT8_MASK 1U + #define ATD1DR6H_BIT9_MASK 2U + #define ATD1DR6H_BIT10_MASK 4U + #define ATD1DR6H_BIT11_MASK 8U + #define ATD1DR6H_BIT12_MASK 16U + #define ATD1DR6H_BIT13_MASK 32U + #define ATD1DR6H_BIT14_MASK 64U + #define ATD1DR6H_BIT15_MASK 128U + + + /*** ATD1DR6L - ATD 1 Conversion Result Register 6 Low; 0x0000013D ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR6LSTR; + #define ATD1DR6L _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Byte + #define ATD1DR6L_BIT6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT6 + #define ATD1DR6L_BIT7 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT7 + #define ATD1DR6L_BIT_6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.MergedBits.grpBIT_6 + #define ATD1DR6L_BIT ATD1DR6L_BIT_6 + + #define ATD1DR6L_BIT6_MASK 64U + #define ATD1DR6L_BIT7_MASK 128U + #define ATD1DR6L_BIT_6_MASK 192U + #define ATD1DR6L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR6STR; +extern volatile ATD1DR6STR _ATD1DR6 @(REG_BASE + 0x0000013CUL); +#define ATD1DR6 _ATD1DR6.Word +#define ATD1DR6_BIT6 _ATD1DR6.Bits.BIT6 +#define ATD1DR6_BIT7 _ATD1DR6.Bits.BIT7 +#define ATD1DR6_BIT8 _ATD1DR6.Bits.BIT8 +#define ATD1DR6_BIT9 _ATD1DR6.Bits.BIT9 +#define ATD1DR6_BIT10 _ATD1DR6.Bits.BIT10 +#define ATD1DR6_BIT11 _ATD1DR6.Bits.BIT11 +#define ATD1DR6_BIT12 _ATD1DR6.Bits.BIT12 +#define ATD1DR6_BIT13 _ATD1DR6.Bits.BIT13 +#define ATD1DR6_BIT14 _ATD1DR6.Bits.BIT14 +#define ATD1DR6_BIT15 _ATD1DR6.Bits.BIT15 +#define ATD1DR6_BIT_6 _ATD1DR6.MergedBits.grpBIT_6 +#define ATD1DR6_BIT ATD1DR6_BIT_6 + +#define ATD1DR6_BIT6_MASK 64U +#define ATD1DR6_BIT7_MASK 128U +#define ATD1DR6_BIT8_MASK 256U +#define ATD1DR6_BIT9_MASK 512U +#define ATD1DR6_BIT10_MASK 1024U +#define ATD1DR6_BIT11_MASK 2048U +#define ATD1DR6_BIT12_MASK 4096U +#define ATD1DR6_BIT13_MASK 8192U +#define ATD1DR6_BIT14_MASK 16384U +#define ATD1DR6_BIT15_MASK 32768U +#define ATD1DR6_BIT_6_MASK 65472U +#define ATD1DR6_BIT_6_BITNUM 6U + + +/*** ATD1DR7 - ATD 1 Conversion Result Register 7; 0x0000013E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR7H - ATD 1 Conversion Result Register 7 High; 0x0000013E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR7HSTR; + #define ATD1DR7H _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Byte + #define ATD1DR7H_BIT8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT8 + #define ATD1DR7H_BIT9 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT9 + #define ATD1DR7H_BIT10 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT10 + #define ATD1DR7H_BIT11 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT11 + #define ATD1DR7H_BIT12 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT12 + #define ATD1DR7H_BIT13 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT13 + #define ATD1DR7H_BIT14 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT14 + #define ATD1DR7H_BIT15 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT15 + + #define ATD1DR7H_BIT8_MASK 1U + #define ATD1DR7H_BIT9_MASK 2U + #define ATD1DR7H_BIT10_MASK 4U + #define ATD1DR7H_BIT11_MASK 8U + #define ATD1DR7H_BIT12_MASK 16U + #define ATD1DR7H_BIT13_MASK 32U + #define ATD1DR7H_BIT14_MASK 64U + #define ATD1DR7H_BIT15_MASK 128U + + + /*** ATD1DR7L - ATD 1 Conversion Result Register 7 Low; 0x0000013F ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR7LSTR; + #define ATD1DR7L _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Byte + #define ATD1DR7L_BIT6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT6 + #define ATD1DR7L_BIT7 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT7 + #define ATD1DR7L_BIT_6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.MergedBits.grpBIT_6 + #define ATD1DR7L_BIT ATD1DR7L_BIT_6 + + #define ATD1DR7L_BIT6_MASK 64U + #define ATD1DR7L_BIT7_MASK 128U + #define ATD1DR7L_BIT_6_MASK 192U + #define ATD1DR7L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR7STR; +extern volatile ATD1DR7STR _ATD1DR7 @(REG_BASE + 0x0000013EUL); +#define ATD1DR7 _ATD1DR7.Word +#define ATD1DR7_BIT6 _ATD1DR7.Bits.BIT6 +#define ATD1DR7_BIT7 _ATD1DR7.Bits.BIT7 +#define ATD1DR7_BIT8 _ATD1DR7.Bits.BIT8 +#define ATD1DR7_BIT9 _ATD1DR7.Bits.BIT9 +#define ATD1DR7_BIT10 _ATD1DR7.Bits.BIT10 +#define ATD1DR7_BIT11 _ATD1DR7.Bits.BIT11 +#define ATD1DR7_BIT12 _ATD1DR7.Bits.BIT12 +#define ATD1DR7_BIT13 _ATD1DR7.Bits.BIT13 +#define ATD1DR7_BIT14 _ATD1DR7.Bits.BIT14 +#define ATD1DR7_BIT15 _ATD1DR7.Bits.BIT15 +#define ATD1DR7_BIT_6 _ATD1DR7.MergedBits.grpBIT_6 +#define ATD1DR7_BIT ATD1DR7_BIT_6 + +#define ATD1DR7_BIT6_MASK 64U +#define ATD1DR7_BIT7_MASK 128U +#define ATD1DR7_BIT8_MASK 256U +#define ATD1DR7_BIT9_MASK 512U +#define ATD1DR7_BIT10_MASK 1024U +#define ATD1DR7_BIT11_MASK 2048U +#define ATD1DR7_BIT12_MASK 4096U +#define ATD1DR7_BIT13_MASK 8192U +#define ATD1DR7_BIT14_MASK 16384U +#define ATD1DR7_BIT15_MASK 32768U +#define ATD1DR7_BIT_6_MASK 65472U +#define ATD1DR7_BIT_6_BITNUM 6U + + +/*** CAN0CTL0 - MSCAN 0 Control 0 Register; 0x00000140 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN0CTL0STR; +extern volatile CAN0CTL0STR _CAN0CTL0 @(REG_BASE + 0x00000140UL); +#define CAN0CTL0 _CAN0CTL0.Byte +#define CAN0CTL0_INITRQ _CAN0CTL0.Bits.INITRQ +#define CAN0CTL0_SLPRQ _CAN0CTL0.Bits.SLPRQ +#define CAN0CTL0_WUPE _CAN0CTL0.Bits.WUPE +#define CAN0CTL0_TIME _CAN0CTL0.Bits.TIME +#define CAN0CTL0_SYNCH _CAN0CTL0.Bits.SYNCH +#define CAN0CTL0_CSWAI _CAN0CTL0.Bits.CSWAI +#define CAN0CTL0_RXACT _CAN0CTL0.Bits.RXACT +#define CAN0CTL0_RXFRM _CAN0CTL0.Bits.RXFRM +/* CAN0CTL_ARR: Access 2 CAN0CTLx registers in an array */ +#define CAN0CTL_ARR ((volatile byte *) &CAN0CTL0) + +#define CAN0CTL0_INITRQ_MASK 1U +#define CAN0CTL0_SLPRQ_MASK 2U +#define CAN0CTL0_WUPE_MASK 4U +#define CAN0CTL0_TIME_MASK 8U +#define CAN0CTL0_SYNCH_MASK 16U +#define CAN0CTL0_CSWAI_MASK 32U +#define CAN0CTL0_RXACT_MASK 64U +#define CAN0CTL0_RXFRM_MASK 128U + + +/*** CAN0CTL1 - MSCAN 0 Control 1 Register; 0x00000141 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN 0 Clock Source */ + byte CANE :1; /* MSCAN 0 Enable */ + } Bits; +} CAN0CTL1STR; +extern volatile CAN0CTL1STR _CAN0CTL1 @(REG_BASE + 0x00000141UL); +#define CAN0CTL1 _CAN0CTL1.Byte +#define CAN0CTL1_INITAK _CAN0CTL1.Bits.INITAK +#define CAN0CTL1_SLPAK _CAN0CTL1.Bits.SLPAK +#define CAN0CTL1_WUPM _CAN0CTL1.Bits.WUPM +#define CAN0CTL1_LISTEN _CAN0CTL1.Bits.LISTEN +#define CAN0CTL1_LOOPB _CAN0CTL1.Bits.LOOPB +#define CAN0CTL1_CLKSRC _CAN0CTL1.Bits.CLKSRC +#define CAN0CTL1_CANE _CAN0CTL1.Bits.CANE + +#define CAN0CTL1_INITAK_MASK 1U +#define CAN0CTL1_SLPAK_MASK 2U +#define CAN0CTL1_WUPM_MASK 4U +#define CAN0CTL1_LISTEN_MASK 16U +#define CAN0CTL1_LOOPB_MASK 32U +#define CAN0CTL1_CLKSRC_MASK 64U +#define CAN0CTL1_CANE_MASK 128U + + +/*** CAN0BTR0 - MSCAN 0 Bus Timing Register 0; 0x00000142 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN0BTR0STR; +extern volatile CAN0BTR0STR _CAN0BTR0 @(REG_BASE + 0x00000142UL); +#define CAN0BTR0 _CAN0BTR0.Byte +#define CAN0BTR0_BRP0 _CAN0BTR0.Bits.BRP0 +#define CAN0BTR0_BRP1 _CAN0BTR0.Bits.BRP1 +#define CAN0BTR0_BRP2 _CAN0BTR0.Bits.BRP2 +#define CAN0BTR0_BRP3 _CAN0BTR0.Bits.BRP3 +#define CAN0BTR0_BRP4 _CAN0BTR0.Bits.BRP4 +#define CAN0BTR0_BRP5 _CAN0BTR0.Bits.BRP5 +#define CAN0BTR0_SJW0 _CAN0BTR0.Bits.SJW0 +#define CAN0BTR0_SJW1 _CAN0BTR0.Bits.SJW1 +/* CAN0BTR_ARR: Access 2 CAN0BTRx registers in an array */ +#define CAN0BTR_ARR ((volatile byte *) &CAN0BTR0) +#define CAN0BTR0_BRP _CAN0BTR0.MergedBits.grpBRP +#define CAN0BTR0_SJW _CAN0BTR0.MergedBits.grpSJW + +#define CAN0BTR0_BRP0_MASK 1U +#define CAN0BTR0_BRP1_MASK 2U +#define CAN0BTR0_BRP2_MASK 4U +#define CAN0BTR0_BRP3_MASK 8U +#define CAN0BTR0_BRP4_MASK 16U +#define CAN0BTR0_BRP5_MASK 32U +#define CAN0BTR0_SJW0_MASK 64U +#define CAN0BTR0_SJW1_MASK 128U +#define CAN0BTR0_BRP_MASK 63U +#define CAN0BTR0_BRP_BITNUM 0U +#define CAN0BTR0_SJW_MASK 192U +#define CAN0BTR0_SJW_BITNUM 6U + + +/*** CAN0BTR1 - MSCAN 0 Bus Timing Register 1; 0x00000143 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 10 */ + byte TSEG11 :1; /* Time Segment 11 */ + byte TSEG12 :1; /* Time Segment 12 */ + byte TSEG13 :1; /* Time Segment 13 */ + byte TSEG20 :1; /* Time Segment 20 */ + byte TSEG21 :1; /* Time Segment 21 */ + byte TSEG22 :1; /* Time Segment 22 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN0BTR1STR; +extern volatile CAN0BTR1STR _CAN0BTR1 @(REG_BASE + 0x00000143UL); +#define CAN0BTR1 _CAN0BTR1.Byte +#define CAN0BTR1_TSEG10 _CAN0BTR1.Bits.TSEG10 +#define CAN0BTR1_TSEG11 _CAN0BTR1.Bits.TSEG11 +#define CAN0BTR1_TSEG12 _CAN0BTR1.Bits.TSEG12 +#define CAN0BTR1_TSEG13 _CAN0BTR1.Bits.TSEG13 +#define CAN0BTR1_TSEG20 _CAN0BTR1.Bits.TSEG20 +#define CAN0BTR1_TSEG21 _CAN0BTR1.Bits.TSEG21 +#define CAN0BTR1_TSEG22 _CAN0BTR1.Bits.TSEG22 +#define CAN0BTR1_SAMP _CAN0BTR1.Bits.SAMP +#define CAN0BTR1_TSEG_10 _CAN0BTR1.MergedBits.grpTSEG_10 +#define CAN0BTR1_TSEG_20 _CAN0BTR1.MergedBits.grpTSEG_20 +#define CAN0BTR1_TSEG CAN0BTR1_TSEG_10 + +#define CAN0BTR1_TSEG10_MASK 1U +#define CAN0BTR1_TSEG11_MASK 2U +#define CAN0BTR1_TSEG12_MASK 4U +#define CAN0BTR1_TSEG13_MASK 8U +#define CAN0BTR1_TSEG20_MASK 16U +#define CAN0BTR1_TSEG21_MASK 32U +#define CAN0BTR1_TSEG22_MASK 64U +#define CAN0BTR1_SAMP_MASK 128U +#define CAN0BTR1_TSEG_10_MASK 15U +#define CAN0BTR1_TSEG_10_BITNUM 0U +#define CAN0BTR1_TSEG_20_MASK 112U +#define CAN0BTR1_TSEG_20_BITNUM 4U + + +/*** CAN0RFLG - MSCAN 0 Receiver Flag Register; 0x00000144 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN0RFLGSTR; +extern volatile CAN0RFLGSTR _CAN0RFLG @(REG_BASE + 0x00000144UL); +#define CAN0RFLG _CAN0RFLG.Byte +#define CAN0RFLG_RXF _CAN0RFLG.Bits.RXF +#define CAN0RFLG_OVRIF _CAN0RFLG.Bits.OVRIF +#define CAN0RFLG_TSTAT0 _CAN0RFLG.Bits.TSTAT0 +#define CAN0RFLG_TSTAT1 _CAN0RFLG.Bits.TSTAT1 +#define CAN0RFLG_RSTAT0 _CAN0RFLG.Bits.RSTAT0 +#define CAN0RFLG_RSTAT1 _CAN0RFLG.Bits.RSTAT1 +#define CAN0RFLG_CSCIF _CAN0RFLG.Bits.CSCIF +#define CAN0RFLG_WUPIF _CAN0RFLG.Bits.WUPIF +#define CAN0RFLG_TSTAT _CAN0RFLG.MergedBits.grpTSTAT +#define CAN0RFLG_RSTAT _CAN0RFLG.MergedBits.grpRSTAT + +#define CAN0RFLG_RXF_MASK 1U +#define CAN0RFLG_OVRIF_MASK 2U +#define CAN0RFLG_TSTAT0_MASK 4U +#define CAN0RFLG_TSTAT1_MASK 8U +#define CAN0RFLG_RSTAT0_MASK 16U +#define CAN0RFLG_RSTAT1_MASK 32U +#define CAN0RFLG_CSCIF_MASK 64U +#define CAN0RFLG_WUPIF_MASK 128U +#define CAN0RFLG_TSTAT_MASK 12U +#define CAN0RFLG_TSTAT_BITNUM 2U +#define CAN0RFLG_RSTAT_MASK 48U +#define CAN0RFLG_RSTAT_BITNUM 4U + + +/*** CAN0RIER - MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN0RIERSTR; +extern volatile CAN0RIERSTR _CAN0RIER @(REG_BASE + 0x00000145UL); +#define CAN0RIER _CAN0RIER.Byte +#define CAN0RIER_RXFIE _CAN0RIER.Bits.RXFIE +#define CAN0RIER_OVRIE _CAN0RIER.Bits.OVRIE +#define CAN0RIER_TSTATE0 _CAN0RIER.Bits.TSTATE0 +#define CAN0RIER_TSTATE1 _CAN0RIER.Bits.TSTATE1 +#define CAN0RIER_RSTATE0 _CAN0RIER.Bits.RSTATE0 +#define CAN0RIER_RSTATE1 _CAN0RIER.Bits.RSTATE1 +#define CAN0RIER_CSCIE _CAN0RIER.Bits.CSCIE +#define CAN0RIER_WUPIE _CAN0RIER.Bits.WUPIE +#define CAN0RIER_TSTATE _CAN0RIER.MergedBits.grpTSTATE +#define CAN0RIER_RSTATE _CAN0RIER.MergedBits.grpRSTATE + +#define CAN0RIER_RXFIE_MASK 1U +#define CAN0RIER_OVRIE_MASK 2U +#define CAN0RIER_TSTATE0_MASK 4U +#define CAN0RIER_TSTATE1_MASK 8U +#define CAN0RIER_RSTATE0_MASK 16U +#define CAN0RIER_RSTATE1_MASK 32U +#define CAN0RIER_CSCIE_MASK 64U +#define CAN0RIER_WUPIE_MASK 128U +#define CAN0RIER_TSTATE_MASK 12U +#define CAN0RIER_TSTATE_BITNUM 2U +#define CAN0RIER_RSTATE_MASK 48U +#define CAN0RIER_RSTATE_BITNUM 4U + + +/*** CAN0TFLG - MSCAN 0 Transmitter Flag Register; 0x00000146 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TFLGSTR; +extern volatile CAN0TFLGSTR _CAN0TFLG @(REG_BASE + 0x00000146UL); +#define CAN0TFLG _CAN0TFLG.Byte +#define CAN0TFLG_TXE0 _CAN0TFLG.Bits.TXE0 +#define CAN0TFLG_TXE1 _CAN0TFLG.Bits.TXE1 +#define CAN0TFLG_TXE2 _CAN0TFLG.Bits.TXE2 +#define CAN0TFLG_TXE _CAN0TFLG.MergedBits.grpTXE + +#define CAN0TFLG_TXE0_MASK 1U +#define CAN0TFLG_TXE1_MASK 2U +#define CAN0TFLG_TXE2_MASK 4U +#define CAN0TFLG_TXE_MASK 7U +#define CAN0TFLG_TXE_BITNUM 0U + + +/*** CAN0TIER - MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TIERSTR; +extern volatile CAN0TIERSTR _CAN0TIER @(REG_BASE + 0x00000147UL); +#define CAN0TIER _CAN0TIER.Byte +#define CAN0TIER_TXEIE0 _CAN0TIER.Bits.TXEIE0 +#define CAN0TIER_TXEIE1 _CAN0TIER.Bits.TXEIE1 +#define CAN0TIER_TXEIE2 _CAN0TIER.Bits.TXEIE2 +#define CAN0TIER_TXEIE _CAN0TIER.MergedBits.grpTXEIE + +#define CAN0TIER_TXEIE0_MASK 1U +#define CAN0TIER_TXEIE1_MASK 2U +#define CAN0TIER_TXEIE2_MASK 4U +#define CAN0TIER_TXEIE_MASK 7U +#define CAN0TIER_TXEIE_BITNUM 0U + + +/*** CAN0TARQ - MSCAN 0 Transmitter Message Abort Request; 0x00000148 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TARQSTR; +extern volatile CAN0TARQSTR _CAN0TARQ @(REG_BASE + 0x00000148UL); +#define CAN0TARQ _CAN0TARQ.Byte +#define CAN0TARQ_ABTRQ0 _CAN0TARQ.Bits.ABTRQ0 +#define CAN0TARQ_ABTRQ1 _CAN0TARQ.Bits.ABTRQ1 +#define CAN0TARQ_ABTRQ2 _CAN0TARQ.Bits.ABTRQ2 +#define CAN0TARQ_ABTRQ _CAN0TARQ.MergedBits.grpABTRQ + +#define CAN0TARQ_ABTRQ0_MASK 1U +#define CAN0TARQ_ABTRQ1_MASK 2U +#define CAN0TARQ_ABTRQ2_MASK 4U +#define CAN0TARQ_ABTRQ_MASK 7U +#define CAN0TARQ_ABTRQ_BITNUM 0U + + +/*** CAN0TAAK - MSCAN 0 Transmitter Message Abort Control; 0x00000149 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TAAKSTR; +extern volatile CAN0TAAKSTR _CAN0TAAK @(REG_BASE + 0x00000149UL); +#define CAN0TAAK _CAN0TAAK.Byte +#define CAN0TAAK_ABTAK0 _CAN0TAAK.Bits.ABTAK0 +#define CAN0TAAK_ABTAK1 _CAN0TAAK.Bits.ABTAK1 +#define CAN0TAAK_ABTAK2 _CAN0TAAK.Bits.ABTAK2 +#define CAN0TAAK_ABTAK _CAN0TAAK.MergedBits.grpABTAK + +#define CAN0TAAK_ABTAK0_MASK 1U +#define CAN0TAAK_ABTAK1_MASK 2U +#define CAN0TAAK_ABTAK2_MASK 4U +#define CAN0TAAK_ABTAK_MASK 7U +#define CAN0TAAK_ABTAK_BITNUM 0U + + +/*** CAN0TBSEL - MSCAN 0 Transmit Buffer Selection; 0x0000014A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TBSELSTR; +extern volatile CAN0TBSELSTR _CAN0TBSEL @(REG_BASE + 0x0000014AUL); +#define CAN0TBSEL _CAN0TBSEL.Byte +#define CAN0TBSEL_TX0 _CAN0TBSEL.Bits.TX0 +#define CAN0TBSEL_TX1 _CAN0TBSEL.Bits.TX1 +#define CAN0TBSEL_TX2 _CAN0TBSEL.Bits.TX2 +#define CAN0TBSEL_TX _CAN0TBSEL.MergedBits.grpTX + +#define CAN0TBSEL_TX0_MASK 1U +#define CAN0TBSEL_TX1_MASK 2U +#define CAN0TBSEL_TX2_MASK 4U +#define CAN0TBSEL_TX_MASK 7U +#define CAN0TBSEL_TX_BITNUM 0U + + +/*** CAN0IDAC - MSCAN 0 Identifier Acceptance Control Register; 0x0000014B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN0IDACSTR; +extern volatile CAN0IDACSTR _CAN0IDAC @(REG_BASE + 0x0000014BUL); +#define CAN0IDAC _CAN0IDAC.Byte +#define CAN0IDAC_IDHIT0 _CAN0IDAC.Bits.IDHIT0 +#define CAN0IDAC_IDHIT1 _CAN0IDAC.Bits.IDHIT1 +#define CAN0IDAC_IDHIT2 _CAN0IDAC.Bits.IDHIT2 +#define CAN0IDAC_IDAM0 _CAN0IDAC.Bits.IDAM0 +#define CAN0IDAC_IDAM1 _CAN0IDAC.Bits.IDAM1 +#define CAN0IDAC_IDHIT _CAN0IDAC.MergedBits.grpIDHIT +#define CAN0IDAC_IDAM _CAN0IDAC.MergedBits.grpIDAM + +#define CAN0IDAC_IDHIT0_MASK 1U +#define CAN0IDAC_IDHIT1_MASK 2U +#define CAN0IDAC_IDHIT2_MASK 4U +#define CAN0IDAC_IDAM0_MASK 16U +#define CAN0IDAC_IDAM1_MASK 32U +#define CAN0IDAC_IDHIT_MASK 7U +#define CAN0IDAC_IDHIT_BITNUM 0U +#define CAN0IDAC_IDAM_MASK 48U +#define CAN0IDAC_IDAM_BITNUM 4U + + +/*** CAN0RXERR - MSCAN 0 Receive Error Counter Register; 0x0000014E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; +} CAN0RXERRSTR; +extern volatile CAN0RXERRSTR _CAN0RXERR @(REG_BASE + 0x0000014EUL); +#define CAN0RXERR _CAN0RXERR.Byte +#define CAN0RXERR_RXERR0 _CAN0RXERR.Bits.RXERR0 +#define CAN0RXERR_RXERR1 _CAN0RXERR.Bits.RXERR1 +#define CAN0RXERR_RXERR2 _CAN0RXERR.Bits.RXERR2 +#define CAN0RXERR_RXERR3 _CAN0RXERR.Bits.RXERR3 +#define CAN0RXERR_RXERR4 _CAN0RXERR.Bits.RXERR4 +#define CAN0RXERR_RXERR5 _CAN0RXERR.Bits.RXERR5 +#define CAN0RXERR_RXERR6 _CAN0RXERR.Bits.RXERR6 +#define CAN0RXERR_RXERR7 _CAN0RXERR.Bits.RXERR7 + +#define CAN0RXERR_RXERR0_MASK 1U +#define CAN0RXERR_RXERR1_MASK 2U +#define CAN0RXERR_RXERR2_MASK 4U +#define CAN0RXERR_RXERR3_MASK 8U +#define CAN0RXERR_RXERR4_MASK 16U +#define CAN0RXERR_RXERR5_MASK 32U +#define CAN0RXERR_RXERR6_MASK 64U +#define CAN0RXERR_RXERR7_MASK 128U + + +/*** CAN0TXERR - MSCAN 0 Transmit Error Counter Register; 0x0000014F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; +} CAN0TXERRSTR; +extern volatile CAN0TXERRSTR _CAN0TXERR @(REG_BASE + 0x0000014FUL); +#define CAN0TXERR _CAN0TXERR.Byte +#define CAN0TXERR_TXERR0 _CAN0TXERR.Bits.TXERR0 +#define CAN0TXERR_TXERR1 _CAN0TXERR.Bits.TXERR1 +#define CAN0TXERR_TXERR2 _CAN0TXERR.Bits.TXERR2 +#define CAN0TXERR_TXERR3 _CAN0TXERR.Bits.TXERR3 +#define CAN0TXERR_TXERR4 _CAN0TXERR.Bits.TXERR4 +#define CAN0TXERR_TXERR5 _CAN0TXERR.Bits.TXERR5 +#define CAN0TXERR_TXERR6 _CAN0TXERR.Bits.TXERR6 +#define CAN0TXERR_TXERR7 _CAN0TXERR.Bits.TXERR7 + +#define CAN0TXERR_TXERR0_MASK 1U +#define CAN0TXERR_TXERR1_MASK 2U +#define CAN0TXERR_TXERR2_MASK 4U +#define CAN0TXERR_TXERR3_MASK 8U +#define CAN0TXERR_TXERR4_MASK 16U +#define CAN0TXERR_TXERR5_MASK 32U +#define CAN0TXERR_TXERR6_MASK 64U +#define CAN0TXERR_TXERR7_MASK 128U + + +/*** CAN0IDAR0 - MSCAN 0 Identifier Acceptance Register 0; 0x00000150 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR0STR; +extern volatile CAN0IDAR0STR _CAN0IDAR0 @(REG_BASE + 0x00000150UL); +#define CAN0IDAR0 _CAN0IDAR0.Byte +#define CAN0IDAR0_AC0 _CAN0IDAR0.Bits.AC0 +#define CAN0IDAR0_AC1 _CAN0IDAR0.Bits.AC1 +#define CAN0IDAR0_AC2 _CAN0IDAR0.Bits.AC2 +#define CAN0IDAR0_AC3 _CAN0IDAR0.Bits.AC3 +#define CAN0IDAR0_AC4 _CAN0IDAR0.Bits.AC4 +#define CAN0IDAR0_AC5 _CAN0IDAR0.Bits.AC5 +#define CAN0IDAR0_AC6 _CAN0IDAR0.Bits.AC6 +#define CAN0IDAR0_AC7 _CAN0IDAR0.Bits.AC7 +/* CAN0IDAR_ARR: Access 4 CAN0IDARx registers in an array */ +#define CAN0IDAR_ARR ((volatile byte *) &CAN0IDAR0) + +#define CAN0IDAR0_AC0_MASK 1U +#define CAN0IDAR0_AC1_MASK 2U +#define CAN0IDAR0_AC2_MASK 4U +#define CAN0IDAR0_AC3_MASK 8U +#define CAN0IDAR0_AC4_MASK 16U +#define CAN0IDAR0_AC5_MASK 32U +#define CAN0IDAR0_AC6_MASK 64U +#define CAN0IDAR0_AC7_MASK 128U + + +/*** CAN0IDAR1 - MSCAN 0 Identifier Acceptance Register 1; 0x00000151 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR1STR; +extern volatile CAN0IDAR1STR _CAN0IDAR1 @(REG_BASE + 0x00000151UL); +#define CAN0IDAR1 _CAN0IDAR1.Byte +#define CAN0IDAR1_AC0 _CAN0IDAR1.Bits.AC0 +#define CAN0IDAR1_AC1 _CAN0IDAR1.Bits.AC1 +#define CAN0IDAR1_AC2 _CAN0IDAR1.Bits.AC2 +#define CAN0IDAR1_AC3 _CAN0IDAR1.Bits.AC3 +#define CAN0IDAR1_AC4 _CAN0IDAR1.Bits.AC4 +#define CAN0IDAR1_AC5 _CAN0IDAR1.Bits.AC5 +#define CAN0IDAR1_AC6 _CAN0IDAR1.Bits.AC6 +#define CAN0IDAR1_AC7 _CAN0IDAR1.Bits.AC7 + +#define CAN0IDAR1_AC0_MASK 1U +#define CAN0IDAR1_AC1_MASK 2U +#define CAN0IDAR1_AC2_MASK 4U +#define CAN0IDAR1_AC3_MASK 8U +#define CAN0IDAR1_AC4_MASK 16U +#define CAN0IDAR1_AC5_MASK 32U +#define CAN0IDAR1_AC6_MASK 64U +#define CAN0IDAR1_AC7_MASK 128U + + +/*** CAN0IDAR2 - MSCAN 0 Identifier Acceptance Register 2; 0x00000152 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR2STR; +extern volatile CAN0IDAR2STR _CAN0IDAR2 @(REG_BASE + 0x00000152UL); +#define CAN0IDAR2 _CAN0IDAR2.Byte +#define CAN0IDAR2_AC0 _CAN0IDAR2.Bits.AC0 +#define CAN0IDAR2_AC1 _CAN0IDAR2.Bits.AC1 +#define CAN0IDAR2_AC2 _CAN0IDAR2.Bits.AC2 +#define CAN0IDAR2_AC3 _CAN0IDAR2.Bits.AC3 +#define CAN0IDAR2_AC4 _CAN0IDAR2.Bits.AC4 +#define CAN0IDAR2_AC5 _CAN0IDAR2.Bits.AC5 +#define CAN0IDAR2_AC6 _CAN0IDAR2.Bits.AC6 +#define CAN0IDAR2_AC7 _CAN0IDAR2.Bits.AC7 + +#define CAN0IDAR2_AC0_MASK 1U +#define CAN0IDAR2_AC1_MASK 2U +#define CAN0IDAR2_AC2_MASK 4U +#define CAN0IDAR2_AC3_MASK 8U +#define CAN0IDAR2_AC4_MASK 16U +#define CAN0IDAR2_AC5_MASK 32U +#define CAN0IDAR2_AC6_MASK 64U +#define CAN0IDAR2_AC7_MASK 128U + + +/*** CAN0IDAR3 - MSCAN 0 Identifier Acceptance Register 3; 0x00000153 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR3STR; +extern volatile CAN0IDAR3STR _CAN0IDAR3 @(REG_BASE + 0x00000153UL); +#define CAN0IDAR3 _CAN0IDAR3.Byte +#define CAN0IDAR3_AC0 _CAN0IDAR3.Bits.AC0 +#define CAN0IDAR3_AC1 _CAN0IDAR3.Bits.AC1 +#define CAN0IDAR3_AC2 _CAN0IDAR3.Bits.AC2 +#define CAN0IDAR3_AC3 _CAN0IDAR3.Bits.AC3 +#define CAN0IDAR3_AC4 _CAN0IDAR3.Bits.AC4 +#define CAN0IDAR3_AC5 _CAN0IDAR3.Bits.AC5 +#define CAN0IDAR3_AC6 _CAN0IDAR3.Bits.AC6 +#define CAN0IDAR3_AC7 _CAN0IDAR3.Bits.AC7 + +#define CAN0IDAR3_AC0_MASK 1U +#define CAN0IDAR3_AC1_MASK 2U +#define CAN0IDAR3_AC2_MASK 4U +#define CAN0IDAR3_AC3_MASK 8U +#define CAN0IDAR3_AC4_MASK 16U +#define CAN0IDAR3_AC5_MASK 32U +#define CAN0IDAR3_AC6_MASK 64U +#define CAN0IDAR3_AC7_MASK 128U + + +/*** CAN0IDMR0 - MSCAN 0 Identifier Mask Register 0; 0x00000154 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR0STR; +extern volatile CAN0IDMR0STR _CAN0IDMR0 @(REG_BASE + 0x00000154UL); +#define CAN0IDMR0 _CAN0IDMR0.Byte +#define CAN0IDMR0_AM0 _CAN0IDMR0.Bits.AM0 +#define CAN0IDMR0_AM1 _CAN0IDMR0.Bits.AM1 +#define CAN0IDMR0_AM2 _CAN0IDMR0.Bits.AM2 +#define CAN0IDMR0_AM3 _CAN0IDMR0.Bits.AM3 +#define CAN0IDMR0_AM4 _CAN0IDMR0.Bits.AM4 +#define CAN0IDMR0_AM5 _CAN0IDMR0.Bits.AM5 +#define CAN0IDMR0_AM6 _CAN0IDMR0.Bits.AM6 +#define CAN0IDMR0_AM7 _CAN0IDMR0.Bits.AM7 +/* CAN0IDMR_ARR: Access 4 CAN0IDMRx registers in an array */ +#define CAN0IDMR_ARR ((volatile byte *) &CAN0IDMR0) + +#define CAN0IDMR0_AM0_MASK 1U +#define CAN0IDMR0_AM1_MASK 2U +#define CAN0IDMR0_AM2_MASK 4U +#define CAN0IDMR0_AM3_MASK 8U +#define CAN0IDMR0_AM4_MASK 16U +#define CAN0IDMR0_AM5_MASK 32U +#define CAN0IDMR0_AM6_MASK 64U +#define CAN0IDMR0_AM7_MASK 128U + + +/*** CAN0IDMR1 - MSCAN 0 Identifier Mask Register 1; 0x00000155 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR1STR; +extern volatile CAN0IDMR1STR _CAN0IDMR1 @(REG_BASE + 0x00000155UL); +#define CAN0IDMR1 _CAN0IDMR1.Byte +#define CAN0IDMR1_AM0 _CAN0IDMR1.Bits.AM0 +#define CAN0IDMR1_AM1 _CAN0IDMR1.Bits.AM1 +#define CAN0IDMR1_AM2 _CAN0IDMR1.Bits.AM2 +#define CAN0IDMR1_AM3 _CAN0IDMR1.Bits.AM3 +#define CAN0IDMR1_AM4 _CAN0IDMR1.Bits.AM4 +#define CAN0IDMR1_AM5 _CAN0IDMR1.Bits.AM5 +#define CAN0IDMR1_AM6 _CAN0IDMR1.Bits.AM6 +#define CAN0IDMR1_AM7 _CAN0IDMR1.Bits.AM7 + +#define CAN0IDMR1_AM0_MASK 1U +#define CAN0IDMR1_AM1_MASK 2U +#define CAN0IDMR1_AM2_MASK 4U +#define CAN0IDMR1_AM3_MASK 8U +#define CAN0IDMR1_AM4_MASK 16U +#define CAN0IDMR1_AM5_MASK 32U +#define CAN0IDMR1_AM6_MASK 64U +#define CAN0IDMR1_AM7_MASK 128U + + +/*** CAN0IDMR2 - MSCAN 0 Identifier Mask Register 2; 0x00000156 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR2STR; +extern volatile CAN0IDMR2STR _CAN0IDMR2 @(REG_BASE + 0x00000156UL); +#define CAN0IDMR2 _CAN0IDMR2.Byte +#define CAN0IDMR2_AM0 _CAN0IDMR2.Bits.AM0 +#define CAN0IDMR2_AM1 _CAN0IDMR2.Bits.AM1 +#define CAN0IDMR2_AM2 _CAN0IDMR2.Bits.AM2 +#define CAN0IDMR2_AM3 _CAN0IDMR2.Bits.AM3 +#define CAN0IDMR2_AM4 _CAN0IDMR2.Bits.AM4 +#define CAN0IDMR2_AM5 _CAN0IDMR2.Bits.AM5 +#define CAN0IDMR2_AM6 _CAN0IDMR2.Bits.AM6 +#define CAN0IDMR2_AM7 _CAN0IDMR2.Bits.AM7 + +#define CAN0IDMR2_AM0_MASK 1U +#define CAN0IDMR2_AM1_MASK 2U +#define CAN0IDMR2_AM2_MASK 4U +#define CAN0IDMR2_AM3_MASK 8U +#define CAN0IDMR2_AM4_MASK 16U +#define CAN0IDMR2_AM5_MASK 32U +#define CAN0IDMR2_AM6_MASK 64U +#define CAN0IDMR2_AM7_MASK 128U + + +/*** CAN0IDMR3 - MSCAN 0 Identifier Mask Register 3; 0x00000157 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR3STR; +extern volatile CAN0IDMR3STR _CAN0IDMR3 @(REG_BASE + 0x00000157UL); +#define CAN0IDMR3 _CAN0IDMR3.Byte +#define CAN0IDMR3_AM0 _CAN0IDMR3.Bits.AM0 +#define CAN0IDMR3_AM1 _CAN0IDMR3.Bits.AM1 +#define CAN0IDMR3_AM2 _CAN0IDMR3.Bits.AM2 +#define CAN0IDMR3_AM3 _CAN0IDMR3.Bits.AM3 +#define CAN0IDMR3_AM4 _CAN0IDMR3.Bits.AM4 +#define CAN0IDMR3_AM5 _CAN0IDMR3.Bits.AM5 +#define CAN0IDMR3_AM6 _CAN0IDMR3.Bits.AM6 +#define CAN0IDMR3_AM7 _CAN0IDMR3.Bits.AM7 + +#define CAN0IDMR3_AM0_MASK 1U +#define CAN0IDMR3_AM1_MASK 2U +#define CAN0IDMR3_AM2_MASK 4U +#define CAN0IDMR3_AM3_MASK 8U +#define CAN0IDMR3_AM4_MASK 16U +#define CAN0IDMR3_AM5_MASK 32U +#define CAN0IDMR3_AM6_MASK 64U +#define CAN0IDMR3_AM7_MASK 128U + + +/*** CAN0IDAR4 - MSCAN 0 Identifier Acceptance Register 4; 0x00000158 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR4STR; +extern volatile CAN0IDAR4STR _CAN0IDAR4 @(REG_BASE + 0x00000158UL); +#define CAN0IDAR4 _CAN0IDAR4.Byte +#define CAN0IDAR4_AC0 _CAN0IDAR4.Bits.AC0 +#define CAN0IDAR4_AC1 _CAN0IDAR4.Bits.AC1 +#define CAN0IDAR4_AC2 _CAN0IDAR4.Bits.AC2 +#define CAN0IDAR4_AC3 _CAN0IDAR4.Bits.AC3 +#define CAN0IDAR4_AC4 _CAN0IDAR4.Bits.AC4 +#define CAN0IDAR4_AC5 _CAN0IDAR4.Bits.AC5 +#define CAN0IDAR4_AC6 _CAN0IDAR4.Bits.AC6 +#define CAN0IDAR4_AC7 _CAN0IDAR4.Bits.AC7 + +#define CAN0IDAR4_AC0_MASK 1U +#define CAN0IDAR4_AC1_MASK 2U +#define CAN0IDAR4_AC2_MASK 4U +#define CAN0IDAR4_AC3_MASK 8U +#define CAN0IDAR4_AC4_MASK 16U +#define CAN0IDAR4_AC5_MASK 32U +#define CAN0IDAR4_AC6_MASK 64U +#define CAN0IDAR4_AC7_MASK 128U + + +/*** CAN0IDAR5 - MSCAN 0 Identifier Acceptance Register 5; 0x00000159 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR5STR; +extern volatile CAN0IDAR5STR _CAN0IDAR5 @(REG_BASE + 0x00000159UL); +#define CAN0IDAR5 _CAN0IDAR5.Byte +#define CAN0IDAR5_AC0 _CAN0IDAR5.Bits.AC0 +#define CAN0IDAR5_AC1 _CAN0IDAR5.Bits.AC1 +#define CAN0IDAR5_AC2 _CAN0IDAR5.Bits.AC2 +#define CAN0IDAR5_AC3 _CAN0IDAR5.Bits.AC3 +#define CAN0IDAR5_AC4 _CAN0IDAR5.Bits.AC4 +#define CAN0IDAR5_AC5 _CAN0IDAR5.Bits.AC5 +#define CAN0IDAR5_AC6 _CAN0IDAR5.Bits.AC6 +#define CAN0IDAR5_AC7 _CAN0IDAR5.Bits.AC7 + +#define CAN0IDAR5_AC0_MASK 1U +#define CAN0IDAR5_AC1_MASK 2U +#define CAN0IDAR5_AC2_MASK 4U +#define CAN0IDAR5_AC3_MASK 8U +#define CAN0IDAR5_AC4_MASK 16U +#define CAN0IDAR5_AC5_MASK 32U +#define CAN0IDAR5_AC6_MASK 64U +#define CAN0IDAR5_AC7_MASK 128U + + +/*** CAN0IDAR6 - MSCAN 0 Identifier Acceptance Register 6; 0x0000015A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR6STR; +extern volatile CAN0IDAR6STR _CAN0IDAR6 @(REG_BASE + 0x0000015AUL); +#define CAN0IDAR6 _CAN0IDAR6.Byte +#define CAN0IDAR6_AC0 _CAN0IDAR6.Bits.AC0 +#define CAN0IDAR6_AC1 _CAN0IDAR6.Bits.AC1 +#define CAN0IDAR6_AC2 _CAN0IDAR6.Bits.AC2 +#define CAN0IDAR6_AC3 _CAN0IDAR6.Bits.AC3 +#define CAN0IDAR6_AC4 _CAN0IDAR6.Bits.AC4 +#define CAN0IDAR6_AC5 _CAN0IDAR6.Bits.AC5 +#define CAN0IDAR6_AC6 _CAN0IDAR6.Bits.AC6 +#define CAN0IDAR6_AC7 _CAN0IDAR6.Bits.AC7 + +#define CAN0IDAR6_AC0_MASK 1U +#define CAN0IDAR6_AC1_MASK 2U +#define CAN0IDAR6_AC2_MASK 4U +#define CAN0IDAR6_AC3_MASK 8U +#define CAN0IDAR6_AC4_MASK 16U +#define CAN0IDAR6_AC5_MASK 32U +#define CAN0IDAR6_AC6_MASK 64U +#define CAN0IDAR6_AC7_MASK 128U + + +/*** CAN0IDAR7 - MSCAN 0 Identifier Acceptance Register 7; 0x0000015B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR7STR; +extern volatile CAN0IDAR7STR _CAN0IDAR7 @(REG_BASE + 0x0000015BUL); +#define CAN0IDAR7 _CAN0IDAR7.Byte +#define CAN0IDAR7_AC0 _CAN0IDAR7.Bits.AC0 +#define CAN0IDAR7_AC1 _CAN0IDAR7.Bits.AC1 +#define CAN0IDAR7_AC2 _CAN0IDAR7.Bits.AC2 +#define CAN0IDAR7_AC3 _CAN0IDAR7.Bits.AC3 +#define CAN0IDAR7_AC4 _CAN0IDAR7.Bits.AC4 +#define CAN0IDAR7_AC5 _CAN0IDAR7.Bits.AC5 +#define CAN0IDAR7_AC6 _CAN0IDAR7.Bits.AC6 +#define CAN0IDAR7_AC7 _CAN0IDAR7.Bits.AC7 + +#define CAN0IDAR7_AC0_MASK 1U +#define CAN0IDAR7_AC1_MASK 2U +#define CAN0IDAR7_AC2_MASK 4U +#define CAN0IDAR7_AC3_MASK 8U +#define CAN0IDAR7_AC4_MASK 16U +#define CAN0IDAR7_AC5_MASK 32U +#define CAN0IDAR7_AC6_MASK 64U +#define CAN0IDAR7_AC7_MASK 128U + + +/*** CAN0IDMR4 - MSCAN 0 Identifier Mask Register 4; 0x0000015C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR4STR; +extern volatile CAN0IDMR4STR _CAN0IDMR4 @(REG_BASE + 0x0000015CUL); +#define CAN0IDMR4 _CAN0IDMR4.Byte +#define CAN0IDMR4_AM0 _CAN0IDMR4.Bits.AM0 +#define CAN0IDMR4_AM1 _CAN0IDMR4.Bits.AM1 +#define CAN0IDMR4_AM2 _CAN0IDMR4.Bits.AM2 +#define CAN0IDMR4_AM3 _CAN0IDMR4.Bits.AM3 +#define CAN0IDMR4_AM4 _CAN0IDMR4.Bits.AM4 +#define CAN0IDMR4_AM5 _CAN0IDMR4.Bits.AM5 +#define CAN0IDMR4_AM6 _CAN0IDMR4.Bits.AM6 +#define CAN0IDMR4_AM7 _CAN0IDMR4.Bits.AM7 + +#define CAN0IDMR4_AM0_MASK 1U +#define CAN0IDMR4_AM1_MASK 2U +#define CAN0IDMR4_AM2_MASK 4U +#define CAN0IDMR4_AM3_MASK 8U +#define CAN0IDMR4_AM4_MASK 16U +#define CAN0IDMR4_AM5_MASK 32U +#define CAN0IDMR4_AM6_MASK 64U +#define CAN0IDMR4_AM7_MASK 128U + + +/*** CAN0IDMR5 - MSCAN 0 Identifier Mask Register 5; 0x0000015D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR5STR; +extern volatile CAN0IDMR5STR _CAN0IDMR5 @(REG_BASE + 0x0000015DUL); +#define CAN0IDMR5 _CAN0IDMR5.Byte +#define CAN0IDMR5_AM0 _CAN0IDMR5.Bits.AM0 +#define CAN0IDMR5_AM1 _CAN0IDMR5.Bits.AM1 +#define CAN0IDMR5_AM2 _CAN0IDMR5.Bits.AM2 +#define CAN0IDMR5_AM3 _CAN0IDMR5.Bits.AM3 +#define CAN0IDMR5_AM4 _CAN0IDMR5.Bits.AM4 +#define CAN0IDMR5_AM5 _CAN0IDMR5.Bits.AM5 +#define CAN0IDMR5_AM6 _CAN0IDMR5.Bits.AM6 +#define CAN0IDMR5_AM7 _CAN0IDMR5.Bits.AM7 + +#define CAN0IDMR5_AM0_MASK 1U +#define CAN0IDMR5_AM1_MASK 2U +#define CAN0IDMR5_AM2_MASK 4U +#define CAN0IDMR5_AM3_MASK 8U +#define CAN0IDMR5_AM4_MASK 16U +#define CAN0IDMR5_AM5_MASK 32U +#define CAN0IDMR5_AM6_MASK 64U +#define CAN0IDMR5_AM7_MASK 128U + + +/*** CAN0IDMR6 - MSCAN 0 Identifier Mask Register 6; 0x0000015E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR6STR; +extern volatile CAN0IDMR6STR _CAN0IDMR6 @(REG_BASE + 0x0000015EUL); +#define CAN0IDMR6 _CAN0IDMR6.Byte +#define CAN0IDMR6_AM0 _CAN0IDMR6.Bits.AM0 +#define CAN0IDMR6_AM1 _CAN0IDMR6.Bits.AM1 +#define CAN0IDMR6_AM2 _CAN0IDMR6.Bits.AM2 +#define CAN0IDMR6_AM3 _CAN0IDMR6.Bits.AM3 +#define CAN0IDMR6_AM4 _CAN0IDMR6.Bits.AM4 +#define CAN0IDMR6_AM5 _CAN0IDMR6.Bits.AM5 +#define CAN0IDMR6_AM6 _CAN0IDMR6.Bits.AM6 +#define CAN0IDMR6_AM7 _CAN0IDMR6.Bits.AM7 + +#define CAN0IDMR6_AM0_MASK 1U +#define CAN0IDMR6_AM1_MASK 2U +#define CAN0IDMR6_AM2_MASK 4U +#define CAN0IDMR6_AM3_MASK 8U +#define CAN0IDMR6_AM4_MASK 16U +#define CAN0IDMR6_AM5_MASK 32U +#define CAN0IDMR6_AM6_MASK 64U +#define CAN0IDMR6_AM7_MASK 128U + + +/*** CAN0IDMR7 - MSCAN 0 Identifier Mask Register 7; 0x0000015F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR7STR; +extern volatile CAN0IDMR7STR _CAN0IDMR7 @(REG_BASE + 0x0000015FUL); +#define CAN0IDMR7 _CAN0IDMR7.Byte +#define CAN0IDMR7_AM0 _CAN0IDMR7.Bits.AM0 +#define CAN0IDMR7_AM1 _CAN0IDMR7.Bits.AM1 +#define CAN0IDMR7_AM2 _CAN0IDMR7.Bits.AM2 +#define CAN0IDMR7_AM3 _CAN0IDMR7.Bits.AM3 +#define CAN0IDMR7_AM4 _CAN0IDMR7.Bits.AM4 +#define CAN0IDMR7_AM5 _CAN0IDMR7.Bits.AM5 +#define CAN0IDMR7_AM6 _CAN0IDMR7.Bits.AM6 +#define CAN0IDMR7_AM7 _CAN0IDMR7.Bits.AM7 + +#define CAN0IDMR7_AM0_MASK 1U +#define CAN0IDMR7_AM1_MASK 2U +#define CAN0IDMR7_AM2_MASK 4U +#define CAN0IDMR7_AM3_MASK 8U +#define CAN0IDMR7_AM4_MASK 16U +#define CAN0IDMR7_AM5_MASK 32U +#define CAN0IDMR7_AM6_MASK 64U +#define CAN0IDMR7_AM7_MASK 128U + + +/*** CAN0RXIDR0 - MSCAN 0 Receive Identifier Register 0; 0x00000160 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; +} CAN0RXIDR0STR; +extern volatile CAN0RXIDR0STR _CAN0RXIDR0 @(REG_BASE + 0x00000160UL); +#define CAN0RXIDR0 _CAN0RXIDR0.Byte +#define CAN0RXIDR0_ID21 _CAN0RXIDR0.Bits.ID21 +#define CAN0RXIDR0_ID22 _CAN0RXIDR0.Bits.ID22 +#define CAN0RXIDR0_ID23 _CAN0RXIDR0.Bits.ID23 +#define CAN0RXIDR0_ID24 _CAN0RXIDR0.Bits.ID24 +#define CAN0RXIDR0_ID25 _CAN0RXIDR0.Bits.ID25 +#define CAN0RXIDR0_ID26 _CAN0RXIDR0.Bits.ID26 +#define CAN0RXIDR0_ID27 _CAN0RXIDR0.Bits.ID27 +#define CAN0RXIDR0_ID28 _CAN0RXIDR0.Bits.ID28 +/* CAN0RXIDR_ARR: Access 4 CAN0RXIDRx registers in an array */ +#define CAN0RXIDR_ARR ((volatile byte *) &CAN0RXIDR0) + +#define CAN0RXIDR0_ID21_MASK 1U +#define CAN0RXIDR0_ID22_MASK 2U +#define CAN0RXIDR0_ID23_MASK 4U +#define CAN0RXIDR0_ID24_MASK 8U +#define CAN0RXIDR0_ID25_MASK 16U +#define CAN0RXIDR0_ID26_MASK 32U +#define CAN0RXIDR0_ID27_MASK 64U +#define CAN0RXIDR0_ID28_MASK 128U + + +/*** CAN0RXIDR1 - MSCAN 0 Receive Identifier Register 1; 0x00000161 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN0RXIDR1STR; +extern volatile CAN0RXIDR1STR _CAN0RXIDR1 @(REG_BASE + 0x00000161UL); +#define CAN0RXIDR1 _CAN0RXIDR1.Byte +#define CAN0RXIDR1_ID15 _CAN0RXIDR1.Bits.ID15 +#define CAN0RXIDR1_ID16 _CAN0RXIDR1.Bits.ID16 +#define CAN0RXIDR1_ID17 _CAN0RXIDR1.Bits.ID17 +#define CAN0RXIDR1_IDE _CAN0RXIDR1.Bits.IDE +#define CAN0RXIDR1_SRR _CAN0RXIDR1.Bits.SRR +#define CAN0RXIDR1_ID18 _CAN0RXIDR1.Bits.ID18 +#define CAN0RXIDR1_ID19 _CAN0RXIDR1.Bits.ID19 +#define CAN0RXIDR1_ID20 _CAN0RXIDR1.Bits.ID20 +#define CAN0RXIDR1_ID_15 _CAN0RXIDR1.MergedBits.grpID_15 +#define CAN0RXIDR1_ID_18 _CAN0RXIDR1.MergedBits.grpID_18 +#define CAN0RXIDR1_ID CAN0RXIDR1_ID_15 + +#define CAN0RXIDR1_ID15_MASK 1U +#define CAN0RXIDR1_ID16_MASK 2U +#define CAN0RXIDR1_ID17_MASK 4U +#define CAN0RXIDR1_IDE_MASK 8U +#define CAN0RXIDR1_SRR_MASK 16U +#define CAN0RXIDR1_ID18_MASK 32U +#define CAN0RXIDR1_ID19_MASK 64U +#define CAN0RXIDR1_ID20_MASK 128U +#define CAN0RXIDR1_ID_15_MASK 7U +#define CAN0RXIDR1_ID_15_BITNUM 0U +#define CAN0RXIDR1_ID_18_MASK 224U +#define CAN0RXIDR1_ID_18_BITNUM 5U + + +/*** CAN0RXIDR2 - MSCAN 0 Receive Identifier Register 2; 0x00000162 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; +} CAN0RXIDR2STR; +extern volatile CAN0RXIDR2STR _CAN0RXIDR2 @(REG_BASE + 0x00000162UL); +#define CAN0RXIDR2 _CAN0RXIDR2.Byte +#define CAN0RXIDR2_ID7 _CAN0RXIDR2.Bits.ID7 +#define CAN0RXIDR2_ID8 _CAN0RXIDR2.Bits.ID8 +#define CAN0RXIDR2_ID9 _CAN0RXIDR2.Bits.ID9 +#define CAN0RXIDR2_ID10 _CAN0RXIDR2.Bits.ID10 +#define CAN0RXIDR2_ID11 _CAN0RXIDR2.Bits.ID11 +#define CAN0RXIDR2_ID12 _CAN0RXIDR2.Bits.ID12 +#define CAN0RXIDR2_ID13 _CAN0RXIDR2.Bits.ID13 +#define CAN0RXIDR2_ID14 _CAN0RXIDR2.Bits.ID14 + +#define CAN0RXIDR2_ID7_MASK 1U +#define CAN0RXIDR2_ID8_MASK 2U +#define CAN0RXIDR2_ID9_MASK 4U +#define CAN0RXIDR2_ID10_MASK 8U +#define CAN0RXIDR2_ID11_MASK 16U +#define CAN0RXIDR2_ID12_MASK 32U +#define CAN0RXIDR2_ID13_MASK 64U +#define CAN0RXIDR2_ID14_MASK 128U + + +/*** CAN0RXIDR3 - MSCAN 0 Receive Identifier Register 3; 0x00000163 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN0RXIDR3STR; +extern volatile CAN0RXIDR3STR _CAN0RXIDR3 @(REG_BASE + 0x00000163UL); +#define CAN0RXIDR3 _CAN0RXIDR3.Byte +#define CAN0RXIDR3_RTR _CAN0RXIDR3.Bits.RTR +#define CAN0RXIDR3_ID0 _CAN0RXIDR3.Bits.ID0 +#define CAN0RXIDR3_ID1 _CAN0RXIDR3.Bits.ID1 +#define CAN0RXIDR3_ID2 _CAN0RXIDR3.Bits.ID2 +#define CAN0RXIDR3_ID3 _CAN0RXIDR3.Bits.ID3 +#define CAN0RXIDR3_ID4 _CAN0RXIDR3.Bits.ID4 +#define CAN0RXIDR3_ID5 _CAN0RXIDR3.Bits.ID5 +#define CAN0RXIDR3_ID6 _CAN0RXIDR3.Bits.ID6 +#define CAN0RXIDR3_ID _CAN0RXIDR3.MergedBits.grpID + +#define CAN0RXIDR3_RTR_MASK 1U +#define CAN0RXIDR3_ID0_MASK 2U +#define CAN0RXIDR3_ID1_MASK 4U +#define CAN0RXIDR3_ID2_MASK 8U +#define CAN0RXIDR3_ID3_MASK 16U +#define CAN0RXIDR3_ID4_MASK 32U +#define CAN0RXIDR3_ID5_MASK 64U +#define CAN0RXIDR3_ID6_MASK 128U +#define CAN0RXIDR3_ID_MASK 254U +#define CAN0RXIDR3_ID_BITNUM 1U + + +/*** CAN0RXDSR0 - MSCAN 0 Receive Data Segment Register 0; 0x00000164 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR0STR; +extern volatile CAN0RXDSR0STR _CAN0RXDSR0 @(REG_BASE + 0x00000164UL); +#define CAN0RXDSR0 _CAN0RXDSR0.Byte +#define CAN0RXDSR0_DB0 _CAN0RXDSR0.Bits.DB0 +#define CAN0RXDSR0_DB1 _CAN0RXDSR0.Bits.DB1 +#define CAN0RXDSR0_DB2 _CAN0RXDSR0.Bits.DB2 +#define CAN0RXDSR0_DB3 _CAN0RXDSR0.Bits.DB3 +#define CAN0RXDSR0_DB4 _CAN0RXDSR0.Bits.DB4 +#define CAN0RXDSR0_DB5 _CAN0RXDSR0.Bits.DB5 +#define CAN0RXDSR0_DB6 _CAN0RXDSR0.Bits.DB6 +#define CAN0RXDSR0_DB7 _CAN0RXDSR0.Bits.DB7 +/* CAN0RXDSR_ARR: Access 8 CAN0RXDSRx registers in an array */ +#define CAN0RXDSR_ARR ((volatile byte *) &CAN0RXDSR0) + +#define CAN0RXDSR0_DB0_MASK 1U +#define CAN0RXDSR0_DB1_MASK 2U +#define CAN0RXDSR0_DB2_MASK 4U +#define CAN0RXDSR0_DB3_MASK 8U +#define CAN0RXDSR0_DB4_MASK 16U +#define CAN0RXDSR0_DB5_MASK 32U +#define CAN0RXDSR0_DB6_MASK 64U +#define CAN0RXDSR0_DB7_MASK 128U + + +/*** CAN0RXDSR1 - MSCAN 0 Receive Data Segment Register 1; 0x00000165 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR1STR; +extern volatile CAN0RXDSR1STR _CAN0RXDSR1 @(REG_BASE + 0x00000165UL); +#define CAN0RXDSR1 _CAN0RXDSR1.Byte +#define CAN0RXDSR1_DB0 _CAN0RXDSR1.Bits.DB0 +#define CAN0RXDSR1_DB1 _CAN0RXDSR1.Bits.DB1 +#define CAN0RXDSR1_DB2 _CAN0RXDSR1.Bits.DB2 +#define CAN0RXDSR1_DB3 _CAN0RXDSR1.Bits.DB3 +#define CAN0RXDSR1_DB4 _CAN0RXDSR1.Bits.DB4 +#define CAN0RXDSR1_DB5 _CAN0RXDSR1.Bits.DB5 +#define CAN0RXDSR1_DB6 _CAN0RXDSR1.Bits.DB6 +#define CAN0RXDSR1_DB7 _CAN0RXDSR1.Bits.DB7 + +#define CAN0RXDSR1_DB0_MASK 1U +#define CAN0RXDSR1_DB1_MASK 2U +#define CAN0RXDSR1_DB2_MASK 4U +#define CAN0RXDSR1_DB3_MASK 8U +#define CAN0RXDSR1_DB4_MASK 16U +#define CAN0RXDSR1_DB5_MASK 32U +#define CAN0RXDSR1_DB6_MASK 64U +#define CAN0RXDSR1_DB7_MASK 128U + + +/*** CAN0RXDSR2 - MSCAN 0 Receive Data Segment Register 2; 0x00000166 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR2STR; +extern volatile CAN0RXDSR2STR _CAN0RXDSR2 @(REG_BASE + 0x00000166UL); +#define CAN0RXDSR2 _CAN0RXDSR2.Byte +#define CAN0RXDSR2_DB0 _CAN0RXDSR2.Bits.DB0 +#define CAN0RXDSR2_DB1 _CAN0RXDSR2.Bits.DB1 +#define CAN0RXDSR2_DB2 _CAN0RXDSR2.Bits.DB2 +#define CAN0RXDSR2_DB3 _CAN0RXDSR2.Bits.DB3 +#define CAN0RXDSR2_DB4 _CAN0RXDSR2.Bits.DB4 +#define CAN0RXDSR2_DB5 _CAN0RXDSR2.Bits.DB5 +#define CAN0RXDSR2_DB6 _CAN0RXDSR2.Bits.DB6 +#define CAN0RXDSR2_DB7 _CAN0RXDSR2.Bits.DB7 + +#define CAN0RXDSR2_DB0_MASK 1U +#define CAN0RXDSR2_DB1_MASK 2U +#define CAN0RXDSR2_DB2_MASK 4U +#define CAN0RXDSR2_DB3_MASK 8U +#define CAN0RXDSR2_DB4_MASK 16U +#define CAN0RXDSR2_DB5_MASK 32U +#define CAN0RXDSR2_DB6_MASK 64U +#define CAN0RXDSR2_DB7_MASK 128U + + +/*** CAN0RXDSR3 - MSCAN 0 Receive Data Segment Register 3; 0x00000167 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR3STR; +extern volatile CAN0RXDSR3STR _CAN0RXDSR3 @(REG_BASE + 0x00000167UL); +#define CAN0RXDSR3 _CAN0RXDSR3.Byte +#define CAN0RXDSR3_DB0 _CAN0RXDSR3.Bits.DB0 +#define CAN0RXDSR3_DB1 _CAN0RXDSR3.Bits.DB1 +#define CAN0RXDSR3_DB2 _CAN0RXDSR3.Bits.DB2 +#define CAN0RXDSR3_DB3 _CAN0RXDSR3.Bits.DB3 +#define CAN0RXDSR3_DB4 _CAN0RXDSR3.Bits.DB4 +#define CAN0RXDSR3_DB5 _CAN0RXDSR3.Bits.DB5 +#define CAN0RXDSR3_DB6 _CAN0RXDSR3.Bits.DB6 +#define CAN0RXDSR3_DB7 _CAN0RXDSR3.Bits.DB7 + +#define CAN0RXDSR3_DB0_MASK 1U +#define CAN0RXDSR3_DB1_MASK 2U +#define CAN0RXDSR3_DB2_MASK 4U +#define CAN0RXDSR3_DB3_MASK 8U +#define CAN0RXDSR3_DB4_MASK 16U +#define CAN0RXDSR3_DB5_MASK 32U +#define CAN0RXDSR3_DB6_MASK 64U +#define CAN0RXDSR3_DB7_MASK 128U + + +/*** CAN0RXDSR4 - MSCAN 0 Receive Data Segment Register 4; 0x00000168 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR4STR; +extern volatile CAN0RXDSR4STR _CAN0RXDSR4 @(REG_BASE + 0x00000168UL); +#define CAN0RXDSR4 _CAN0RXDSR4.Byte +#define CAN0RXDSR4_DB0 _CAN0RXDSR4.Bits.DB0 +#define CAN0RXDSR4_DB1 _CAN0RXDSR4.Bits.DB1 +#define CAN0RXDSR4_DB2 _CAN0RXDSR4.Bits.DB2 +#define CAN0RXDSR4_DB3 _CAN0RXDSR4.Bits.DB3 +#define CAN0RXDSR4_DB4 _CAN0RXDSR4.Bits.DB4 +#define CAN0RXDSR4_DB5 _CAN0RXDSR4.Bits.DB5 +#define CAN0RXDSR4_DB6 _CAN0RXDSR4.Bits.DB6 +#define CAN0RXDSR4_DB7 _CAN0RXDSR4.Bits.DB7 + +#define CAN0RXDSR4_DB0_MASK 1U +#define CAN0RXDSR4_DB1_MASK 2U +#define CAN0RXDSR4_DB2_MASK 4U +#define CAN0RXDSR4_DB3_MASK 8U +#define CAN0RXDSR4_DB4_MASK 16U +#define CAN0RXDSR4_DB5_MASK 32U +#define CAN0RXDSR4_DB6_MASK 64U +#define CAN0RXDSR4_DB7_MASK 128U + + +/*** CAN0RXDSR5 - MSCAN 0 Receive Data Segment Register 5; 0x00000169 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR5STR; +extern volatile CAN0RXDSR5STR _CAN0RXDSR5 @(REG_BASE + 0x00000169UL); +#define CAN0RXDSR5 _CAN0RXDSR5.Byte +#define CAN0RXDSR5_DB0 _CAN0RXDSR5.Bits.DB0 +#define CAN0RXDSR5_DB1 _CAN0RXDSR5.Bits.DB1 +#define CAN0RXDSR5_DB2 _CAN0RXDSR5.Bits.DB2 +#define CAN0RXDSR5_DB3 _CAN0RXDSR5.Bits.DB3 +#define CAN0RXDSR5_DB4 _CAN0RXDSR5.Bits.DB4 +#define CAN0RXDSR5_DB5 _CAN0RXDSR5.Bits.DB5 +#define CAN0RXDSR5_DB6 _CAN0RXDSR5.Bits.DB6 +#define CAN0RXDSR5_DB7 _CAN0RXDSR5.Bits.DB7 + +#define CAN0RXDSR5_DB0_MASK 1U +#define CAN0RXDSR5_DB1_MASK 2U +#define CAN0RXDSR5_DB2_MASK 4U +#define CAN0RXDSR5_DB3_MASK 8U +#define CAN0RXDSR5_DB4_MASK 16U +#define CAN0RXDSR5_DB5_MASK 32U +#define CAN0RXDSR5_DB6_MASK 64U +#define CAN0RXDSR5_DB7_MASK 128U + + +/*** CAN0RXDSR6 - MSCAN 0 Receive Data Segment Register 6; 0x0000016A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR6STR; +extern volatile CAN0RXDSR6STR _CAN0RXDSR6 @(REG_BASE + 0x0000016AUL); +#define CAN0RXDSR6 _CAN0RXDSR6.Byte +#define CAN0RXDSR6_DB0 _CAN0RXDSR6.Bits.DB0 +#define CAN0RXDSR6_DB1 _CAN0RXDSR6.Bits.DB1 +#define CAN0RXDSR6_DB2 _CAN0RXDSR6.Bits.DB2 +#define CAN0RXDSR6_DB3 _CAN0RXDSR6.Bits.DB3 +#define CAN0RXDSR6_DB4 _CAN0RXDSR6.Bits.DB4 +#define CAN0RXDSR6_DB5 _CAN0RXDSR6.Bits.DB5 +#define CAN0RXDSR6_DB6 _CAN0RXDSR6.Bits.DB6 +#define CAN0RXDSR6_DB7 _CAN0RXDSR6.Bits.DB7 + +#define CAN0RXDSR6_DB0_MASK 1U +#define CAN0RXDSR6_DB1_MASK 2U +#define CAN0RXDSR6_DB2_MASK 4U +#define CAN0RXDSR6_DB3_MASK 8U +#define CAN0RXDSR6_DB4_MASK 16U +#define CAN0RXDSR6_DB5_MASK 32U +#define CAN0RXDSR6_DB6_MASK 64U +#define CAN0RXDSR6_DB7_MASK 128U + + +/*** CAN0RXDSR7 - MSCAN 0 Receive Data Segment Register 7; 0x0000016B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR7STR; +extern volatile CAN0RXDSR7STR _CAN0RXDSR7 @(REG_BASE + 0x0000016BUL); +#define CAN0RXDSR7 _CAN0RXDSR7.Byte +#define CAN0RXDSR7_DB0 _CAN0RXDSR7.Bits.DB0 +#define CAN0RXDSR7_DB1 _CAN0RXDSR7.Bits.DB1 +#define CAN0RXDSR7_DB2 _CAN0RXDSR7.Bits.DB2 +#define CAN0RXDSR7_DB3 _CAN0RXDSR7.Bits.DB3 +#define CAN0RXDSR7_DB4 _CAN0RXDSR7.Bits.DB4 +#define CAN0RXDSR7_DB5 _CAN0RXDSR7.Bits.DB5 +#define CAN0RXDSR7_DB6 _CAN0RXDSR7.Bits.DB6 +#define CAN0RXDSR7_DB7 _CAN0RXDSR7.Bits.DB7 + +#define CAN0RXDSR7_DB0_MASK 1U +#define CAN0RXDSR7_DB1_MASK 2U +#define CAN0RXDSR7_DB2_MASK 4U +#define CAN0RXDSR7_DB3_MASK 8U +#define CAN0RXDSR7_DB4_MASK 16U +#define CAN0RXDSR7_DB5_MASK 32U +#define CAN0RXDSR7_DB6_MASK 64U +#define CAN0RXDSR7_DB7_MASK 128U + + +/*** CAN0RXDLR - MSCAN 0 Receive Data Length Register; 0x0000016C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0RXDLRSTR; +extern volatile CAN0RXDLRSTR _CAN0RXDLR @(REG_BASE + 0x0000016CUL); +#define CAN0RXDLR _CAN0RXDLR.Byte +#define CAN0RXDLR_DLC0 _CAN0RXDLR.Bits.DLC0 +#define CAN0RXDLR_DLC1 _CAN0RXDLR.Bits.DLC1 +#define CAN0RXDLR_DLC2 _CAN0RXDLR.Bits.DLC2 +#define CAN0RXDLR_DLC3 _CAN0RXDLR.Bits.DLC3 +#define CAN0RXDLR_DLC _CAN0RXDLR.MergedBits.grpDLC + +#define CAN0RXDLR_DLC0_MASK 1U +#define CAN0RXDLR_DLC1_MASK 2U +#define CAN0RXDLR_DLC2_MASK 4U +#define CAN0RXDLR_DLC3_MASK 8U +#define CAN0RXDLR_DLC_MASK 15U +#define CAN0RXDLR_DLC_BITNUM 0U + + +/*** CAN0RXTSR - MSCAN 0 Receive Time Stamp Register; 0x0000016E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** CAN0RXTSRH - MSCAN 0 Receive Time Stamp Register High; 0x0000016E ***/ + union { + byte Byte; + struct { + byte TSR8 :1; /* Time Stamp Bit 8 */ + byte TSR9 :1; /* Time Stamp Bit 9 */ + byte TSR10 :1; /* Time Stamp Bit 10 */ + byte TSR11 :1; /* Time Stamp Bit 11 */ + byte TSR12 :1; /* Time Stamp Bit 12 */ + byte TSR13 :1; /* Time Stamp Bit 13 */ + byte TSR14 :1; /* Time Stamp Bit 14 */ + byte TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; + } CAN0RXTSRHSTR; + #define CAN0RXTSRH _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Byte + #define CAN0RXTSRH_TSR8 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR8 + #define CAN0RXTSRH_TSR9 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR9 + #define CAN0RXTSRH_TSR10 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR10 + #define CAN0RXTSRH_TSR11 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR11 + #define CAN0RXTSRH_TSR12 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR12 + #define CAN0RXTSRH_TSR13 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR13 + #define CAN0RXTSRH_TSR14 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR14 + #define CAN0RXTSRH_TSR15 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR15 + + #define CAN0RXTSRH_TSR8_MASK 1U + #define CAN0RXTSRH_TSR9_MASK 2U + #define CAN0RXTSRH_TSR10_MASK 4U + #define CAN0RXTSRH_TSR11_MASK 8U + #define CAN0RXTSRH_TSR12_MASK 16U + #define CAN0RXTSRH_TSR13_MASK 32U + #define CAN0RXTSRH_TSR14_MASK 64U + #define CAN0RXTSRH_TSR15_MASK 128U + + + /*** CAN0RXTSRL - MSCAN 0 Receive Time Stamp Register Low; 0x0000016F ***/ + union { + byte Byte; + struct { + byte TSR0 :1; /* Time Stamp Bit 0 */ + byte TSR1 :1; /* Time Stamp Bit 1 */ + byte TSR2 :1; /* Time Stamp Bit 2 */ + byte TSR3 :1; /* Time Stamp Bit 3 */ + byte TSR4 :1; /* Time Stamp Bit 4 */ + byte TSR5 :1; /* Time Stamp Bit 5 */ + byte TSR6 :1; /* Time Stamp Bit 6 */ + byte TSR7 :1; /* Time Stamp Bit 7 */ + } Bits; + } CAN0RXTSRLSTR; + #define CAN0RXTSRL _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Byte + #define CAN0RXTSRL_TSR0 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR0 + #define CAN0RXTSRL_TSR1 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR1 + #define CAN0RXTSRL_TSR2 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR2 + #define CAN0RXTSRL_TSR3 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR3 + #define CAN0RXTSRL_TSR4 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR4 + #define CAN0RXTSRL_TSR5 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR5 + #define CAN0RXTSRL_TSR6 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR6 + #define CAN0RXTSRL_TSR7 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR7 + + #define CAN0RXTSRL_TSR0_MASK 1U + #define CAN0RXTSRL_TSR1_MASK 2U + #define CAN0RXTSRL_TSR2_MASK 4U + #define CAN0RXTSRL_TSR3_MASK 8U + #define CAN0RXTSRL_TSR4_MASK 16U + #define CAN0RXTSRL_TSR5_MASK 32U + #define CAN0RXTSRL_TSR6_MASK 64U + #define CAN0RXTSRL_TSR7_MASK 128U + + } Overlap_STR; + + struct { + word TSR0 :1; /* Time Stamp Bit 0 */ + word TSR1 :1; /* Time Stamp Bit 1 */ + word TSR2 :1; /* Time Stamp Bit 2 */ + word TSR3 :1; /* Time Stamp Bit 3 */ + word TSR4 :1; /* Time Stamp Bit 4 */ + word TSR5 :1; /* Time Stamp Bit 5 */ + word TSR6 :1; /* Time Stamp Bit 6 */ + word TSR7 :1; /* Time Stamp Bit 7 */ + word TSR8 :1; /* Time Stamp Bit 8 */ + word TSR9 :1; /* Time Stamp Bit 9 */ + word TSR10 :1; /* Time Stamp Bit 10 */ + word TSR11 :1; /* Time Stamp Bit 11 */ + word TSR12 :1; /* Time Stamp Bit 12 */ + word TSR13 :1; /* Time Stamp Bit 13 */ + word TSR14 :1; /* Time Stamp Bit 14 */ + word TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; +} CAN0RXTSRSTR; +extern volatile CAN0RXTSRSTR _CAN0RXTSR @(REG_BASE + 0x0000016EUL); +#define CAN0RXTSR _CAN0RXTSR.Word +#define CAN0RXTSR_TSR0 _CAN0RXTSR.Bits.TSR0 +#define CAN0RXTSR_TSR1 _CAN0RXTSR.Bits.TSR1 +#define CAN0RXTSR_TSR2 _CAN0RXTSR.Bits.TSR2 +#define CAN0RXTSR_TSR3 _CAN0RXTSR.Bits.TSR3 +#define CAN0RXTSR_TSR4 _CAN0RXTSR.Bits.TSR4 +#define CAN0RXTSR_TSR5 _CAN0RXTSR.Bits.TSR5 +#define CAN0RXTSR_TSR6 _CAN0RXTSR.Bits.TSR6 +#define CAN0RXTSR_TSR7 _CAN0RXTSR.Bits.TSR7 +#define CAN0RXTSR_TSR8 _CAN0RXTSR.Bits.TSR8 +#define CAN0RXTSR_TSR9 _CAN0RXTSR.Bits.TSR9 +#define CAN0RXTSR_TSR10 _CAN0RXTSR.Bits.TSR10 +#define CAN0RXTSR_TSR11 _CAN0RXTSR.Bits.TSR11 +#define CAN0RXTSR_TSR12 _CAN0RXTSR.Bits.TSR12 +#define CAN0RXTSR_TSR13 _CAN0RXTSR.Bits.TSR13 +#define CAN0RXTSR_TSR14 _CAN0RXTSR.Bits.TSR14 +#define CAN0RXTSR_TSR15 _CAN0RXTSR.Bits.TSR15 + +#define CAN0RXTSR_TSR0_MASK 1U +#define CAN0RXTSR_TSR1_MASK 2U +#define CAN0RXTSR_TSR2_MASK 4U +#define CAN0RXTSR_TSR3_MASK 8U +#define CAN0RXTSR_TSR4_MASK 16U +#define CAN0RXTSR_TSR5_MASK 32U +#define CAN0RXTSR_TSR6_MASK 64U +#define CAN0RXTSR_TSR7_MASK 128U +#define CAN0RXTSR_TSR8_MASK 256U +#define CAN0RXTSR_TSR9_MASK 512U +#define CAN0RXTSR_TSR10_MASK 1024U +#define CAN0RXTSR_TSR11_MASK 2048U +#define CAN0RXTSR_TSR12_MASK 4096U +#define CAN0RXTSR_TSR13_MASK 8192U +#define CAN0RXTSR_TSR14_MASK 16384U +#define CAN0RXTSR_TSR15_MASK 32768U + + +/*** CAN0TXIDR0 - MSCAN 0 Transmit Identifier Register 0; 0x00000170 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; +} CAN0TXIDR0STR; +extern volatile CAN0TXIDR0STR _CAN0TXIDR0 @(REG_BASE + 0x00000170UL); +#define CAN0TXIDR0 _CAN0TXIDR0.Byte +#define CAN0TXIDR0_ID21 _CAN0TXIDR0.Bits.ID21 +#define CAN0TXIDR0_ID22 _CAN0TXIDR0.Bits.ID22 +#define CAN0TXIDR0_ID23 _CAN0TXIDR0.Bits.ID23 +#define CAN0TXIDR0_ID24 _CAN0TXIDR0.Bits.ID24 +#define CAN0TXIDR0_ID25 _CAN0TXIDR0.Bits.ID25 +#define CAN0TXIDR0_ID26 _CAN0TXIDR0.Bits.ID26 +#define CAN0TXIDR0_ID27 _CAN0TXIDR0.Bits.ID27 +#define CAN0TXIDR0_ID28 _CAN0TXIDR0.Bits.ID28 +/* CAN0TXIDR_ARR: Access 4 CAN0TXIDRx registers in an array */ +#define CAN0TXIDR_ARR ((volatile byte *) &CAN0TXIDR0) + +#define CAN0TXIDR0_ID21_MASK 1U +#define CAN0TXIDR0_ID22_MASK 2U +#define CAN0TXIDR0_ID23_MASK 4U +#define CAN0TXIDR0_ID24_MASK 8U +#define CAN0TXIDR0_ID25_MASK 16U +#define CAN0TXIDR0_ID26_MASK 32U +#define CAN0TXIDR0_ID27_MASK 64U +#define CAN0TXIDR0_ID28_MASK 128U + + +/*** CAN0TXIDR1 - MSCAN 0 Transmit Identifier Register 1; 0x00000171 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN0TXIDR1STR; +extern volatile CAN0TXIDR1STR _CAN0TXIDR1 @(REG_BASE + 0x00000171UL); +#define CAN0TXIDR1 _CAN0TXIDR1.Byte +#define CAN0TXIDR1_ID15 _CAN0TXIDR1.Bits.ID15 +#define CAN0TXIDR1_ID16 _CAN0TXIDR1.Bits.ID16 +#define CAN0TXIDR1_ID17 _CAN0TXIDR1.Bits.ID17 +#define CAN0TXIDR1_IDE _CAN0TXIDR1.Bits.IDE +#define CAN0TXIDR1_SRR _CAN0TXIDR1.Bits.SRR +#define CAN0TXIDR1_ID18 _CAN0TXIDR1.Bits.ID18 +#define CAN0TXIDR1_ID19 _CAN0TXIDR1.Bits.ID19 +#define CAN0TXIDR1_ID20 _CAN0TXIDR1.Bits.ID20 +#define CAN0TXIDR1_ID_15 _CAN0TXIDR1.MergedBits.grpID_15 +#define CAN0TXIDR1_ID_18 _CAN0TXIDR1.MergedBits.grpID_18 +#define CAN0TXIDR1_ID CAN0TXIDR1_ID_15 + +#define CAN0TXIDR1_ID15_MASK 1U +#define CAN0TXIDR1_ID16_MASK 2U +#define CAN0TXIDR1_ID17_MASK 4U +#define CAN0TXIDR1_IDE_MASK 8U +#define CAN0TXIDR1_SRR_MASK 16U +#define CAN0TXIDR1_ID18_MASK 32U +#define CAN0TXIDR1_ID19_MASK 64U +#define CAN0TXIDR1_ID20_MASK 128U +#define CAN0TXIDR1_ID_15_MASK 7U +#define CAN0TXIDR1_ID_15_BITNUM 0U +#define CAN0TXIDR1_ID_18_MASK 224U +#define CAN0TXIDR1_ID_18_BITNUM 5U + + +/*** CAN0TXIDR2 - MSCAN 0 Transmit Identifier Register 2; 0x00000172 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; +} CAN0TXIDR2STR; +extern volatile CAN0TXIDR2STR _CAN0TXIDR2 @(REG_BASE + 0x00000172UL); +#define CAN0TXIDR2 _CAN0TXIDR2.Byte +#define CAN0TXIDR2_ID7 _CAN0TXIDR2.Bits.ID7 +#define CAN0TXIDR2_ID8 _CAN0TXIDR2.Bits.ID8 +#define CAN0TXIDR2_ID9 _CAN0TXIDR2.Bits.ID9 +#define CAN0TXIDR2_ID10 _CAN0TXIDR2.Bits.ID10 +#define CAN0TXIDR2_ID11 _CAN0TXIDR2.Bits.ID11 +#define CAN0TXIDR2_ID12 _CAN0TXIDR2.Bits.ID12 +#define CAN0TXIDR2_ID13 _CAN0TXIDR2.Bits.ID13 +#define CAN0TXIDR2_ID14 _CAN0TXIDR2.Bits.ID14 + +#define CAN0TXIDR2_ID7_MASK 1U +#define CAN0TXIDR2_ID8_MASK 2U +#define CAN0TXIDR2_ID9_MASK 4U +#define CAN0TXIDR2_ID10_MASK 8U +#define CAN0TXIDR2_ID11_MASK 16U +#define CAN0TXIDR2_ID12_MASK 32U +#define CAN0TXIDR2_ID13_MASK 64U +#define CAN0TXIDR2_ID14_MASK 128U + + +/*** CAN0TXIDR3 - MSCAN 0 Transmit Identifier Register 3; 0x00000173 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN0TXIDR3STR; +extern volatile CAN0TXIDR3STR _CAN0TXIDR3 @(REG_BASE + 0x00000173UL); +#define CAN0TXIDR3 _CAN0TXIDR3.Byte +#define CAN0TXIDR3_RTR _CAN0TXIDR3.Bits.RTR +#define CAN0TXIDR3_ID0 _CAN0TXIDR3.Bits.ID0 +#define CAN0TXIDR3_ID1 _CAN0TXIDR3.Bits.ID1 +#define CAN0TXIDR3_ID2 _CAN0TXIDR3.Bits.ID2 +#define CAN0TXIDR3_ID3 _CAN0TXIDR3.Bits.ID3 +#define CAN0TXIDR3_ID4 _CAN0TXIDR3.Bits.ID4 +#define CAN0TXIDR3_ID5 _CAN0TXIDR3.Bits.ID5 +#define CAN0TXIDR3_ID6 _CAN0TXIDR3.Bits.ID6 +#define CAN0TXIDR3_ID _CAN0TXIDR3.MergedBits.grpID + +#define CAN0TXIDR3_RTR_MASK 1U +#define CAN0TXIDR3_ID0_MASK 2U +#define CAN0TXIDR3_ID1_MASK 4U +#define CAN0TXIDR3_ID2_MASK 8U +#define CAN0TXIDR3_ID3_MASK 16U +#define CAN0TXIDR3_ID4_MASK 32U +#define CAN0TXIDR3_ID5_MASK 64U +#define CAN0TXIDR3_ID6_MASK 128U +#define CAN0TXIDR3_ID_MASK 254U +#define CAN0TXIDR3_ID_BITNUM 1U + + +/*** CAN0TXDSR0 - MSCAN 0 Transmit Data Segment Register 0; 0x00000174 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR0STR; +extern volatile CAN0TXDSR0STR _CAN0TXDSR0 @(REG_BASE + 0x00000174UL); +#define CAN0TXDSR0 _CAN0TXDSR0.Byte +#define CAN0TXDSR0_DB0 _CAN0TXDSR0.Bits.DB0 +#define CAN0TXDSR0_DB1 _CAN0TXDSR0.Bits.DB1 +#define CAN0TXDSR0_DB2 _CAN0TXDSR0.Bits.DB2 +#define CAN0TXDSR0_DB3 _CAN0TXDSR0.Bits.DB3 +#define CAN0TXDSR0_DB4 _CAN0TXDSR0.Bits.DB4 +#define CAN0TXDSR0_DB5 _CAN0TXDSR0.Bits.DB5 +#define CAN0TXDSR0_DB6 _CAN0TXDSR0.Bits.DB6 +#define CAN0TXDSR0_DB7 _CAN0TXDSR0.Bits.DB7 +/* CAN0TXDSR_ARR: Access 8 CAN0TXDSRx registers in an array */ +#define CAN0TXDSR_ARR ((volatile byte *) &CAN0TXDSR0) + +#define CAN0TXDSR0_DB0_MASK 1U +#define CAN0TXDSR0_DB1_MASK 2U +#define CAN0TXDSR0_DB2_MASK 4U +#define CAN0TXDSR0_DB3_MASK 8U +#define CAN0TXDSR0_DB4_MASK 16U +#define CAN0TXDSR0_DB5_MASK 32U +#define CAN0TXDSR0_DB6_MASK 64U +#define CAN0TXDSR0_DB7_MASK 128U + + +/*** CAN0TXDSR1 - MSCAN 0 Transmit Data Segment Register 1; 0x00000175 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR1STR; +extern volatile CAN0TXDSR1STR _CAN0TXDSR1 @(REG_BASE + 0x00000175UL); +#define CAN0TXDSR1 _CAN0TXDSR1.Byte +#define CAN0TXDSR1_DB0 _CAN0TXDSR1.Bits.DB0 +#define CAN0TXDSR1_DB1 _CAN0TXDSR1.Bits.DB1 +#define CAN0TXDSR1_DB2 _CAN0TXDSR1.Bits.DB2 +#define CAN0TXDSR1_DB3 _CAN0TXDSR1.Bits.DB3 +#define CAN0TXDSR1_DB4 _CAN0TXDSR1.Bits.DB4 +#define CAN0TXDSR1_DB5 _CAN0TXDSR1.Bits.DB5 +#define CAN0TXDSR1_DB6 _CAN0TXDSR1.Bits.DB6 +#define CAN0TXDSR1_DB7 _CAN0TXDSR1.Bits.DB7 + +#define CAN0TXDSR1_DB0_MASK 1U +#define CAN0TXDSR1_DB1_MASK 2U +#define CAN0TXDSR1_DB2_MASK 4U +#define CAN0TXDSR1_DB3_MASK 8U +#define CAN0TXDSR1_DB4_MASK 16U +#define CAN0TXDSR1_DB5_MASK 32U +#define CAN0TXDSR1_DB6_MASK 64U +#define CAN0TXDSR1_DB7_MASK 128U + + +/*** CAN0TXDSR2 - MSCAN 0 Transmit Data Segment Register 2; 0x00000176 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR2STR; +extern volatile CAN0TXDSR2STR _CAN0TXDSR2 @(REG_BASE + 0x00000176UL); +#define CAN0TXDSR2 _CAN0TXDSR2.Byte +#define CAN0TXDSR2_DB0 _CAN0TXDSR2.Bits.DB0 +#define CAN0TXDSR2_DB1 _CAN0TXDSR2.Bits.DB1 +#define CAN0TXDSR2_DB2 _CAN0TXDSR2.Bits.DB2 +#define CAN0TXDSR2_DB3 _CAN0TXDSR2.Bits.DB3 +#define CAN0TXDSR2_DB4 _CAN0TXDSR2.Bits.DB4 +#define CAN0TXDSR2_DB5 _CAN0TXDSR2.Bits.DB5 +#define CAN0TXDSR2_DB6 _CAN0TXDSR2.Bits.DB6 +#define CAN0TXDSR2_DB7 _CAN0TXDSR2.Bits.DB7 + +#define CAN0TXDSR2_DB0_MASK 1U +#define CAN0TXDSR2_DB1_MASK 2U +#define CAN0TXDSR2_DB2_MASK 4U +#define CAN0TXDSR2_DB3_MASK 8U +#define CAN0TXDSR2_DB4_MASK 16U +#define CAN0TXDSR2_DB5_MASK 32U +#define CAN0TXDSR2_DB6_MASK 64U +#define CAN0TXDSR2_DB7_MASK 128U + + +/*** CAN0TXDSR3 - MSCAN 0 Transmit Data Segment Register 3; 0x00000177 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR3STR; +extern volatile CAN0TXDSR3STR _CAN0TXDSR3 @(REG_BASE + 0x00000177UL); +#define CAN0TXDSR3 _CAN0TXDSR3.Byte +#define CAN0TXDSR3_DB0 _CAN0TXDSR3.Bits.DB0 +#define CAN0TXDSR3_DB1 _CAN0TXDSR3.Bits.DB1 +#define CAN0TXDSR3_DB2 _CAN0TXDSR3.Bits.DB2 +#define CAN0TXDSR3_DB3 _CAN0TXDSR3.Bits.DB3 +#define CAN0TXDSR3_DB4 _CAN0TXDSR3.Bits.DB4 +#define CAN0TXDSR3_DB5 _CAN0TXDSR3.Bits.DB5 +#define CAN0TXDSR3_DB6 _CAN0TXDSR3.Bits.DB6 +#define CAN0TXDSR3_DB7 _CAN0TXDSR3.Bits.DB7 + +#define CAN0TXDSR3_DB0_MASK 1U +#define CAN0TXDSR3_DB1_MASK 2U +#define CAN0TXDSR3_DB2_MASK 4U +#define CAN0TXDSR3_DB3_MASK 8U +#define CAN0TXDSR3_DB4_MASK 16U +#define CAN0TXDSR3_DB5_MASK 32U +#define CAN0TXDSR3_DB6_MASK 64U +#define CAN0TXDSR3_DB7_MASK 128U + + +/*** CAN0TXDSR4 - MSCAN 0 Transmit Data Segment Register 4; 0x00000178 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR4STR; +extern volatile CAN0TXDSR4STR _CAN0TXDSR4 @(REG_BASE + 0x00000178UL); +#define CAN0TXDSR4 _CAN0TXDSR4.Byte +#define CAN0TXDSR4_DB0 _CAN0TXDSR4.Bits.DB0 +#define CAN0TXDSR4_DB1 _CAN0TXDSR4.Bits.DB1 +#define CAN0TXDSR4_DB2 _CAN0TXDSR4.Bits.DB2 +#define CAN0TXDSR4_DB3 _CAN0TXDSR4.Bits.DB3 +#define CAN0TXDSR4_DB4 _CAN0TXDSR4.Bits.DB4 +#define CAN0TXDSR4_DB5 _CAN0TXDSR4.Bits.DB5 +#define CAN0TXDSR4_DB6 _CAN0TXDSR4.Bits.DB6 +#define CAN0TXDSR4_DB7 _CAN0TXDSR4.Bits.DB7 + +#define CAN0TXDSR4_DB0_MASK 1U +#define CAN0TXDSR4_DB1_MASK 2U +#define CAN0TXDSR4_DB2_MASK 4U +#define CAN0TXDSR4_DB3_MASK 8U +#define CAN0TXDSR4_DB4_MASK 16U +#define CAN0TXDSR4_DB5_MASK 32U +#define CAN0TXDSR4_DB6_MASK 64U +#define CAN0TXDSR4_DB7_MASK 128U + + +/*** CAN0TXDSR5 - MSCAN 0 Transmit Data Segment Register 5; 0x00000179 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR5STR; +extern volatile CAN0TXDSR5STR _CAN0TXDSR5 @(REG_BASE + 0x00000179UL); +#define CAN0TXDSR5 _CAN0TXDSR5.Byte +#define CAN0TXDSR5_DB0 _CAN0TXDSR5.Bits.DB0 +#define CAN0TXDSR5_DB1 _CAN0TXDSR5.Bits.DB1 +#define CAN0TXDSR5_DB2 _CAN0TXDSR5.Bits.DB2 +#define CAN0TXDSR5_DB3 _CAN0TXDSR5.Bits.DB3 +#define CAN0TXDSR5_DB4 _CAN0TXDSR5.Bits.DB4 +#define CAN0TXDSR5_DB5 _CAN0TXDSR5.Bits.DB5 +#define CAN0TXDSR5_DB6 _CAN0TXDSR5.Bits.DB6 +#define CAN0TXDSR5_DB7 _CAN0TXDSR5.Bits.DB7 + +#define CAN0TXDSR5_DB0_MASK 1U +#define CAN0TXDSR5_DB1_MASK 2U +#define CAN0TXDSR5_DB2_MASK 4U +#define CAN0TXDSR5_DB3_MASK 8U +#define CAN0TXDSR5_DB4_MASK 16U +#define CAN0TXDSR5_DB5_MASK 32U +#define CAN0TXDSR5_DB6_MASK 64U +#define CAN0TXDSR5_DB7_MASK 128U + + +/*** CAN0TXDSR6 - MSCAN 0 Transmit Data Segment Register 6; 0x0000017A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR6STR; +extern volatile CAN0TXDSR6STR _CAN0TXDSR6 @(REG_BASE + 0x0000017AUL); +#define CAN0TXDSR6 _CAN0TXDSR6.Byte +#define CAN0TXDSR6_DB0 _CAN0TXDSR6.Bits.DB0 +#define CAN0TXDSR6_DB1 _CAN0TXDSR6.Bits.DB1 +#define CAN0TXDSR6_DB2 _CAN0TXDSR6.Bits.DB2 +#define CAN0TXDSR6_DB3 _CAN0TXDSR6.Bits.DB3 +#define CAN0TXDSR6_DB4 _CAN0TXDSR6.Bits.DB4 +#define CAN0TXDSR6_DB5 _CAN0TXDSR6.Bits.DB5 +#define CAN0TXDSR6_DB6 _CAN0TXDSR6.Bits.DB6 +#define CAN0TXDSR6_DB7 _CAN0TXDSR6.Bits.DB7 + +#define CAN0TXDSR6_DB0_MASK 1U +#define CAN0TXDSR6_DB1_MASK 2U +#define CAN0TXDSR6_DB2_MASK 4U +#define CAN0TXDSR6_DB3_MASK 8U +#define CAN0TXDSR6_DB4_MASK 16U +#define CAN0TXDSR6_DB5_MASK 32U +#define CAN0TXDSR6_DB6_MASK 64U +#define CAN0TXDSR6_DB7_MASK 128U + + +/*** CAN0TXDSR7 - MSCAN 0 Transmit Data Segment Register 7; 0x0000017B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR7STR; +extern volatile CAN0TXDSR7STR _CAN0TXDSR7 @(REG_BASE + 0x0000017BUL); +#define CAN0TXDSR7 _CAN0TXDSR7.Byte +#define CAN0TXDSR7_DB0 _CAN0TXDSR7.Bits.DB0 +#define CAN0TXDSR7_DB1 _CAN0TXDSR7.Bits.DB1 +#define CAN0TXDSR7_DB2 _CAN0TXDSR7.Bits.DB2 +#define CAN0TXDSR7_DB3 _CAN0TXDSR7.Bits.DB3 +#define CAN0TXDSR7_DB4 _CAN0TXDSR7.Bits.DB4 +#define CAN0TXDSR7_DB5 _CAN0TXDSR7.Bits.DB5 +#define CAN0TXDSR7_DB6 _CAN0TXDSR7.Bits.DB6 +#define CAN0TXDSR7_DB7 _CAN0TXDSR7.Bits.DB7 + +#define CAN0TXDSR7_DB0_MASK 1U +#define CAN0TXDSR7_DB1_MASK 2U +#define CAN0TXDSR7_DB2_MASK 4U +#define CAN0TXDSR7_DB3_MASK 8U +#define CAN0TXDSR7_DB4_MASK 16U +#define CAN0TXDSR7_DB5_MASK 32U +#define CAN0TXDSR7_DB6_MASK 64U +#define CAN0TXDSR7_DB7_MASK 128U + + +/*** CAN0TXDLR - MSCAN 0 Transmit Data Length Register; 0x0000017C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TXDLRSTR; +extern volatile CAN0TXDLRSTR _CAN0TXDLR @(REG_BASE + 0x0000017CUL); +#define CAN0TXDLR _CAN0TXDLR.Byte +#define CAN0TXDLR_DLC0 _CAN0TXDLR.Bits.DLC0 +#define CAN0TXDLR_DLC1 _CAN0TXDLR.Bits.DLC1 +#define CAN0TXDLR_DLC2 _CAN0TXDLR.Bits.DLC2 +#define CAN0TXDLR_DLC3 _CAN0TXDLR.Bits.DLC3 +#define CAN0TXDLR_DLC _CAN0TXDLR.MergedBits.grpDLC + +#define CAN0TXDLR_DLC0_MASK 1U +#define CAN0TXDLR_DLC1_MASK 2U +#define CAN0TXDLR_DLC2_MASK 4U +#define CAN0TXDLR_DLC3_MASK 8U +#define CAN0TXDLR_DLC_MASK 15U +#define CAN0TXDLR_DLC_BITNUM 0U + + +/*** CAN0TXTBPR - MSCAN 0 Transmit Buffer Priority; 0x0000017D ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; +} CAN0TXTBPRSTR; +extern volatile CAN0TXTBPRSTR _CAN0TXTBPR @(REG_BASE + 0x0000017DUL); +#define CAN0TXTBPR _CAN0TXTBPR.Byte +#define CAN0TXTBPR_PRIO0 _CAN0TXTBPR.Bits.PRIO0 +#define CAN0TXTBPR_PRIO1 _CAN0TXTBPR.Bits.PRIO1 +#define CAN0TXTBPR_PRIO2 _CAN0TXTBPR.Bits.PRIO2 +#define CAN0TXTBPR_PRIO3 _CAN0TXTBPR.Bits.PRIO3 +#define CAN0TXTBPR_PRIO4 _CAN0TXTBPR.Bits.PRIO4 +#define CAN0TXTBPR_PRIO5 _CAN0TXTBPR.Bits.PRIO5 +#define CAN0TXTBPR_PRIO6 _CAN0TXTBPR.Bits.PRIO6 +#define CAN0TXTBPR_PRIO7 _CAN0TXTBPR.Bits.PRIO7 + +#define CAN0TXTBPR_PRIO0_MASK 1U +#define CAN0TXTBPR_PRIO1_MASK 2U +#define CAN0TXTBPR_PRIO2_MASK 4U +#define CAN0TXTBPR_PRIO3_MASK 8U +#define CAN0TXTBPR_PRIO4_MASK 16U +#define CAN0TXTBPR_PRIO5_MASK 32U +#define CAN0TXTBPR_PRIO6_MASK 64U +#define CAN0TXTBPR_PRIO7_MASK 128U + + +/*** CAN0TXTSR - MSCAN 0 Transmit Time Stamp Register; 0x0000017E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** CAN0TXTSRH - MSCAN 0 Transmit Time Stamp Register High; 0x0000017E ***/ + union { + byte Byte; + struct { + byte TSR8 :1; /* Time Stamp Bit 8 */ + byte TSR9 :1; /* Time Stamp Bit 9 */ + byte TSR10 :1; /* Time Stamp Bit 10 */ + byte TSR11 :1; /* Time Stamp Bit 11 */ + byte TSR12 :1; /* Time Stamp Bit 12 */ + byte TSR13 :1; /* Time Stamp Bit 13 */ + byte TSR14 :1; /* Time Stamp Bit 14 */ + byte TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; + } CAN0TXTSRHSTR; + #define CAN0TXTSRH _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Byte + #define CAN0TXTSRH_TSR8 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR8 + #define CAN0TXTSRH_TSR9 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR9 + #define CAN0TXTSRH_TSR10 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR10 + #define CAN0TXTSRH_TSR11 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR11 + #define CAN0TXTSRH_TSR12 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR12 + #define CAN0TXTSRH_TSR13 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR13 + #define CAN0TXTSRH_TSR14 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR14 + #define CAN0TXTSRH_TSR15 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR15 + + #define CAN0TXTSRH_TSR8_MASK 1U + #define CAN0TXTSRH_TSR9_MASK 2U + #define CAN0TXTSRH_TSR10_MASK 4U + #define CAN0TXTSRH_TSR11_MASK 8U + #define CAN0TXTSRH_TSR12_MASK 16U + #define CAN0TXTSRH_TSR13_MASK 32U + #define CAN0TXTSRH_TSR14_MASK 64U + #define CAN0TXTSRH_TSR15_MASK 128U + + + /*** CAN0TXTSRL - MSCAN 0 Transmit Time Stamp Register Low; 0x0000017F ***/ + union { + byte Byte; + struct { + byte TSR0 :1; /* Time Stamp Bit 0 */ + byte TSR1 :1; /* Time Stamp Bit 1 */ + byte TSR2 :1; /* Time Stamp Bit 2 */ + byte TSR3 :1; /* Time Stamp Bit 3 */ + byte TSR4 :1; /* Time Stamp Bit 4 */ + byte TSR5 :1; /* Time Stamp Bit 5 */ + byte TSR6 :1; /* Time Stamp Bit 6 */ + byte TSR7 :1; /* Time Stamp Bit 7 */ + } Bits; + } CAN0TXTSRLSTR; + #define CAN0TXTSRL _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Byte + #define CAN0TXTSRL_TSR0 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR0 + #define CAN0TXTSRL_TSR1 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR1 + #define CAN0TXTSRL_TSR2 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR2 + #define CAN0TXTSRL_TSR3 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR3 + #define CAN0TXTSRL_TSR4 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR4 + #define CAN0TXTSRL_TSR5 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR5 + #define CAN0TXTSRL_TSR6 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR6 + #define CAN0TXTSRL_TSR7 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR7 + + #define CAN0TXTSRL_TSR0_MASK 1U + #define CAN0TXTSRL_TSR1_MASK 2U + #define CAN0TXTSRL_TSR2_MASK 4U + #define CAN0TXTSRL_TSR3_MASK 8U + #define CAN0TXTSRL_TSR4_MASK 16U + #define CAN0TXTSRL_TSR5_MASK 32U + #define CAN0TXTSRL_TSR6_MASK 64U + #define CAN0TXTSRL_TSR7_MASK 128U + + } Overlap_STR; + + struct { + word TSR0 :1; /* Time Stamp Bit 0 */ + word TSR1 :1; /* Time Stamp Bit 1 */ + word TSR2 :1; /* Time Stamp Bit 2 */ + word TSR3 :1; /* Time Stamp Bit 3 */ + word TSR4 :1; /* Time Stamp Bit 4 */ + word TSR5 :1; /* Time Stamp Bit 5 */ + word TSR6 :1; /* Time Stamp Bit 6 */ + word TSR7 :1; /* Time Stamp Bit 7 */ + word TSR8 :1; /* Time Stamp Bit 8 */ + word TSR9 :1; /* Time Stamp Bit 9 */ + word TSR10 :1; /* Time Stamp Bit 10 */ + word TSR11 :1; /* Time Stamp Bit 11 */ + word TSR12 :1; /* Time Stamp Bit 12 */ + word TSR13 :1; /* Time Stamp Bit 13 */ + word TSR14 :1; /* Time Stamp Bit 14 */ + word TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; +} CAN0TXTSRSTR; +extern volatile CAN0TXTSRSTR _CAN0TXTSR @(REG_BASE + 0x0000017EUL); +#define CAN0TXTSR _CAN0TXTSR.Word +#define CAN0TXTSR_TSR0 _CAN0TXTSR.Bits.TSR0 +#define CAN0TXTSR_TSR1 _CAN0TXTSR.Bits.TSR1 +#define CAN0TXTSR_TSR2 _CAN0TXTSR.Bits.TSR2 +#define CAN0TXTSR_TSR3 _CAN0TXTSR.Bits.TSR3 +#define CAN0TXTSR_TSR4 _CAN0TXTSR.Bits.TSR4 +#define CAN0TXTSR_TSR5 _CAN0TXTSR.Bits.TSR5 +#define CAN0TXTSR_TSR6 _CAN0TXTSR.Bits.TSR6 +#define CAN0TXTSR_TSR7 _CAN0TXTSR.Bits.TSR7 +#define CAN0TXTSR_TSR8 _CAN0TXTSR.Bits.TSR8 +#define CAN0TXTSR_TSR9 _CAN0TXTSR.Bits.TSR9 +#define CAN0TXTSR_TSR10 _CAN0TXTSR.Bits.TSR10 +#define CAN0TXTSR_TSR11 _CAN0TXTSR.Bits.TSR11 +#define CAN0TXTSR_TSR12 _CAN0TXTSR.Bits.TSR12 +#define CAN0TXTSR_TSR13 _CAN0TXTSR.Bits.TSR13 +#define CAN0TXTSR_TSR14 _CAN0TXTSR.Bits.TSR14 +#define CAN0TXTSR_TSR15 _CAN0TXTSR.Bits.TSR15 + +#define CAN0TXTSR_TSR0_MASK 1U +#define CAN0TXTSR_TSR1_MASK 2U +#define CAN0TXTSR_TSR2_MASK 4U +#define CAN0TXTSR_TSR3_MASK 8U +#define CAN0TXTSR_TSR4_MASK 16U +#define CAN0TXTSR_TSR5_MASK 32U +#define CAN0TXTSR_TSR6_MASK 64U +#define CAN0TXTSR_TSR7_MASK 128U +#define CAN0TXTSR_TSR8_MASK 256U +#define CAN0TXTSR_TSR9_MASK 512U +#define CAN0TXTSR_TSR10_MASK 1024U +#define CAN0TXTSR_TSR11_MASK 2048U +#define CAN0TXTSR_TSR12_MASK 4096U +#define CAN0TXTSR_TSR13_MASK 8192U +#define CAN0TXTSR_TSR14_MASK 16384U +#define CAN0TXTSR_TSR15_MASK 32768U + + +/*** PTT - Port T I/O Register; 0x00000240 ***/ +typedef union { + byte Byte; + struct { + byte PTT0 :1; /* Port T Bit 0 */ + byte PTT1 :1; /* Port T Bit 1 */ + byte PTT2 :1; /* Port T Bit 2 */ + byte PTT3 :1; /* Port T Bit 3 */ + byte PTT4 :1; /* Port T Bit 4 */ + byte PTT5 :1; /* Port T Bit 5 */ + byte PTT6 :1; /* Port T Bit 6 */ + byte PTT7 :1; /* Port T Bit 7 */ + } Bits; +} PTTSTR; +extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240UL); +#define PTT _PTT.Byte +#define PTT_PTT0 _PTT.Bits.PTT0 +#define PTT_PTT1 _PTT.Bits.PTT1 +#define PTT_PTT2 _PTT.Bits.PTT2 +#define PTT_PTT3 _PTT.Bits.PTT3 +#define PTT_PTT4 _PTT.Bits.PTT4 +#define PTT_PTT5 _PTT.Bits.PTT5 +#define PTT_PTT6 _PTT.Bits.PTT6 +#define PTT_PTT7 _PTT.Bits.PTT7 + +#define PTT_PTT0_MASK 1U +#define PTT_PTT1_MASK 2U +#define PTT_PTT2_MASK 4U +#define PTT_PTT3_MASK 8U +#define PTT_PTT4_MASK 16U +#define PTT_PTT5_MASK 32U +#define PTT_PTT6_MASK 64U +#define PTT_PTT7_MASK 128U + + +/*** PTIT - Port T Input Register; 0x00000241 ***/ +typedef union { + byte Byte; + struct { + byte PTIT0 :1; /* Port T Bit 0 */ + byte PTIT1 :1; /* Port T Bit 1 */ + byte PTIT2 :1; /* Port T Bit 2 */ + byte PTIT3 :1; /* Port T Bit 3 */ + byte PTIT4 :1; /* Port T Bit 4 */ + byte PTIT5 :1; /* Port T Bit 5 */ + byte PTIT6 :1; /* Port T Bit 6 */ + byte PTIT7 :1; /* Port T Bit 7 */ + } Bits; +} PTITSTR; +extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241UL); +#define PTIT _PTIT.Byte +#define PTIT_PTIT0 _PTIT.Bits.PTIT0 +#define PTIT_PTIT1 _PTIT.Bits.PTIT1 +#define PTIT_PTIT2 _PTIT.Bits.PTIT2 +#define PTIT_PTIT3 _PTIT.Bits.PTIT3 +#define PTIT_PTIT4 _PTIT.Bits.PTIT4 +#define PTIT_PTIT5 _PTIT.Bits.PTIT5 +#define PTIT_PTIT6 _PTIT.Bits.PTIT6 +#define PTIT_PTIT7 _PTIT.Bits.PTIT7 + +#define PTIT_PTIT0_MASK 1U +#define PTIT_PTIT1_MASK 2U +#define PTIT_PTIT2_MASK 4U +#define PTIT_PTIT3_MASK 8U +#define PTIT_PTIT4_MASK 16U +#define PTIT_PTIT5_MASK 32U +#define PTIT_PTIT6_MASK 64U +#define PTIT_PTIT7_MASK 128U + + +/*** DDRT - Port T Data Direction Register; 0x00000242 ***/ +typedef union { + byte Byte; + struct { + byte DDRT0 :1; /* Data Direction Port T Bit 0 */ + byte DDRT1 :1; /* Data Direction Port T Bit 1 */ + byte DDRT2 :1; /* Data Direction Port T Bit 2 */ + byte DDRT3 :1; /* Data Direction Port T Bit 3 */ + byte DDRT4 :1; /* Data Direction Port T Bit 4 */ + byte DDRT5 :1; /* Data Direction Port T Bit 5 */ + byte DDRT6 :1; /* Data Direction Port T Bit 6 */ + byte DDRT7 :1; /* Data Direction Port T Bit 7 */ + } Bits; +} DDRTSTR; +extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242UL); +#define DDRT _DDRT.Byte +#define DDRT_DDRT0 _DDRT.Bits.DDRT0 +#define DDRT_DDRT1 _DDRT.Bits.DDRT1 +#define DDRT_DDRT2 _DDRT.Bits.DDRT2 +#define DDRT_DDRT3 _DDRT.Bits.DDRT3 +#define DDRT_DDRT4 _DDRT.Bits.DDRT4 +#define DDRT_DDRT5 _DDRT.Bits.DDRT5 +#define DDRT_DDRT6 _DDRT.Bits.DDRT6 +#define DDRT_DDRT7 _DDRT.Bits.DDRT7 + +#define DDRT_DDRT0_MASK 1U +#define DDRT_DDRT1_MASK 2U +#define DDRT_DDRT2_MASK 4U +#define DDRT_DDRT3_MASK 8U +#define DDRT_DDRT4_MASK 16U +#define DDRT_DDRT5_MASK 32U +#define DDRT_DDRT6_MASK 64U +#define DDRT_DDRT7_MASK 128U + + +/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/ +typedef union { + byte Byte; + struct { + byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */ + byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */ + byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */ + byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */ + byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */ + byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */ + byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */ + byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */ + } Bits; +} RDRTSTR; +extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243UL); +#define RDRT _RDRT.Byte +#define RDRT_RDRT0 _RDRT.Bits.RDRT0 +#define RDRT_RDRT1 _RDRT.Bits.RDRT1 +#define RDRT_RDRT2 _RDRT.Bits.RDRT2 +#define RDRT_RDRT3 _RDRT.Bits.RDRT3 +#define RDRT_RDRT4 _RDRT.Bits.RDRT4 +#define RDRT_RDRT5 _RDRT.Bits.RDRT5 +#define RDRT_RDRT6 _RDRT.Bits.RDRT6 +#define RDRT_RDRT7 _RDRT.Bits.RDRT7 + +#define RDRT_RDRT0_MASK 1U +#define RDRT_RDRT1_MASK 2U +#define RDRT_RDRT2_MASK 4U +#define RDRT_RDRT3_MASK 8U +#define RDRT_RDRT4_MASK 16U +#define RDRT_RDRT5_MASK 32U +#define RDRT_RDRT6_MASK 64U +#define RDRT_RDRT7_MASK 128U + + +/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/ +typedef union { + byte Byte; + struct { + byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */ + byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */ + byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */ + byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */ + byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */ + byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */ + byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */ + byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */ + } Bits; +} PERTSTR; +extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244UL); +#define PERT _PERT.Byte +#define PERT_PERT0 _PERT.Bits.PERT0 +#define PERT_PERT1 _PERT.Bits.PERT1 +#define PERT_PERT2 _PERT.Bits.PERT2 +#define PERT_PERT3 _PERT.Bits.PERT3 +#define PERT_PERT4 _PERT.Bits.PERT4 +#define PERT_PERT5 _PERT.Bits.PERT5 +#define PERT_PERT6 _PERT.Bits.PERT6 +#define PERT_PERT7 _PERT.Bits.PERT7 + +#define PERT_PERT0_MASK 1U +#define PERT_PERT1_MASK 2U +#define PERT_PERT2_MASK 4U +#define PERT_PERT3_MASK 8U +#define PERT_PERT4_MASK 16U +#define PERT_PERT5_MASK 32U +#define PERT_PERT6_MASK 64U +#define PERT_PERT7_MASK 128U + + +/*** PPST - Port T Polarity Select Register; 0x00000245 ***/ +typedef union { + byte Byte; + struct { + byte PPST0 :1; /* Pull Select Port T Bit 0 */ + byte PPST1 :1; /* Pull Select Port T Bit 1 */ + byte PPST2 :1; /* Pull Select Port T Bit 2 */ + byte PPST3 :1; /* Pull Select Port T Bit 3 */ + byte PPST4 :1; /* Pull Select Port T Bit 4 */ + byte PPST5 :1; /* Pull Select Port T Bit 5 */ + byte PPST6 :1; /* Pull Select Port T Bit 6 */ + byte PPST7 :1; /* Pull Select Port T Bit 7 */ + } Bits; +} PPSTSTR; +extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245UL); +#define PPST _PPST.Byte +#define PPST_PPST0 _PPST.Bits.PPST0 +#define PPST_PPST1 _PPST.Bits.PPST1 +#define PPST_PPST2 _PPST.Bits.PPST2 +#define PPST_PPST3 _PPST.Bits.PPST3 +#define PPST_PPST4 _PPST.Bits.PPST4 +#define PPST_PPST5 _PPST.Bits.PPST5 +#define PPST_PPST6 _PPST.Bits.PPST6 +#define PPST_PPST7 _PPST.Bits.PPST7 + +#define PPST_PPST0_MASK 1U +#define PPST_PPST1_MASK 2U +#define PPST_PPST2_MASK 4U +#define PPST_PPST3_MASK 8U +#define PPST_PPST4_MASK 16U +#define PPST_PPST5_MASK 32U +#define PPST_PPST6_MASK 64U +#define PPST_PPST7_MASK 128U + + +/*** PTS - Port S I/O Register; 0x00000248 ***/ +typedef union { + byte Byte; + struct { + byte PTS0 :1; /* Port S Bit 0 */ + byte PTS1 :1; /* Port S Bit 1 */ + byte PTS2 :1; /* Port S Bit 2 */ + byte PTS3 :1; /* Port S Bit 3 */ + byte PTS4 :1; /* Port S Bit 4 */ + byte PTS5 :1; /* Port S Bit 5 */ + byte PTS6 :1; /* Port S Bit 6 */ + byte PTS7 :1; /* Port S Bit 7 */ + } Bits; +} PTSSTR; +extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248UL); +#define PTS _PTS.Byte +#define PTS_PTS0 _PTS.Bits.PTS0 +#define PTS_PTS1 _PTS.Bits.PTS1 +#define PTS_PTS2 _PTS.Bits.PTS2 +#define PTS_PTS3 _PTS.Bits.PTS3 +#define PTS_PTS4 _PTS.Bits.PTS4 +#define PTS_PTS5 _PTS.Bits.PTS5 +#define PTS_PTS6 _PTS.Bits.PTS6 +#define PTS_PTS7 _PTS.Bits.PTS7 + +#define PTS_PTS0_MASK 1U +#define PTS_PTS1_MASK 2U +#define PTS_PTS2_MASK 4U +#define PTS_PTS3_MASK 8U +#define PTS_PTS4_MASK 16U +#define PTS_PTS5_MASK 32U +#define PTS_PTS6_MASK 64U +#define PTS_PTS7_MASK 128U + + +/*** PTIS - Port S Input Register; 0x00000249 ***/ +typedef union { + byte Byte; + struct { + byte PTIS0 :1; /* Port S Bit 0 */ + byte PTIS1 :1; /* Port S Bit 1 */ + byte PTIS2 :1; /* Port S Bit 2 */ + byte PTIS3 :1; /* Port S Bit 3 */ + byte PTIS4 :1; /* Port S Bit 4 */ + byte PTIS5 :1; /* Port S Bit 5 */ + byte PTIS6 :1; /* Port S Bit 6 */ + byte PTIS7 :1; /* Port S Bit 7 */ + } Bits; +} PTISSTR; +extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249UL); +#define PTIS _PTIS.Byte +#define PTIS_PTIS0 _PTIS.Bits.PTIS0 +#define PTIS_PTIS1 _PTIS.Bits.PTIS1 +#define PTIS_PTIS2 _PTIS.Bits.PTIS2 +#define PTIS_PTIS3 _PTIS.Bits.PTIS3 +#define PTIS_PTIS4 _PTIS.Bits.PTIS4 +#define PTIS_PTIS5 _PTIS.Bits.PTIS5 +#define PTIS_PTIS6 _PTIS.Bits.PTIS6 +#define PTIS_PTIS7 _PTIS.Bits.PTIS7 + +#define PTIS_PTIS0_MASK 1U +#define PTIS_PTIS1_MASK 2U +#define PTIS_PTIS2_MASK 4U +#define PTIS_PTIS3_MASK 8U +#define PTIS_PTIS4_MASK 16U +#define PTIS_PTIS5_MASK 32U +#define PTIS_PTIS6_MASK 64U +#define PTIS_PTIS7_MASK 128U + + +/*** DDRS - Port S Data Direction Register; 0x0000024A ***/ +typedef union { + byte Byte; + struct { + byte DDRS0 :1; /* Data Direction Port S Bit 0 */ + byte DDRS1 :1; /* Data Direction Port S Bit 1 */ + byte DDRS2 :1; /* Data Direction Port S Bit 2 */ + byte DDRS3 :1; /* Data Direction Port S Bit 3 */ + byte DDRS4 :1; /* Data Direction Port S Bit 4 */ + byte DDRS5 :1; /* Data Direction Port S Bit 5 */ + byte DDRS6 :1; /* Data Direction Port S Bit 6 */ + byte DDRS7 :1; /* Data Direction Port S Bit 7 */ + } Bits; +} DDRSSTR; +extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024AUL); +#define DDRS _DDRS.Byte +#define DDRS_DDRS0 _DDRS.Bits.DDRS0 +#define DDRS_DDRS1 _DDRS.Bits.DDRS1 +#define DDRS_DDRS2 _DDRS.Bits.DDRS2 +#define DDRS_DDRS3 _DDRS.Bits.DDRS3 +#define DDRS_DDRS4 _DDRS.Bits.DDRS4 +#define DDRS_DDRS5 _DDRS.Bits.DDRS5 +#define DDRS_DDRS6 _DDRS.Bits.DDRS6 +#define DDRS_DDRS7 _DDRS.Bits.DDRS7 + +#define DDRS_DDRS0_MASK 1U +#define DDRS_DDRS1_MASK 2U +#define DDRS_DDRS2_MASK 4U +#define DDRS_DDRS3_MASK 8U +#define DDRS_DDRS4_MASK 16U +#define DDRS_DDRS5_MASK 32U +#define DDRS_DDRS6_MASK 64U +#define DDRS_DDRS7_MASK 128U + + +/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/ +typedef union { + byte Byte; + struct { + byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */ + byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */ + byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */ + byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */ + byte RDRS4 :1; /* Reduced Drive Port S Bit 4 */ + byte RDRS5 :1; /* Reduced Drive Port S Bit 5 */ + byte RDRS6 :1; /* Reduced Drive Port S Bit 6 */ + byte RDRS7 :1; /* Reduced Drive Port S Bit 7 */ + } Bits; +} RDRSSTR; +extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024BUL); +#define RDRS _RDRS.Byte +#define RDRS_RDRS0 _RDRS.Bits.RDRS0 +#define RDRS_RDRS1 _RDRS.Bits.RDRS1 +#define RDRS_RDRS2 _RDRS.Bits.RDRS2 +#define RDRS_RDRS3 _RDRS.Bits.RDRS3 +#define RDRS_RDRS4 _RDRS.Bits.RDRS4 +#define RDRS_RDRS5 _RDRS.Bits.RDRS5 +#define RDRS_RDRS6 _RDRS.Bits.RDRS6 +#define RDRS_RDRS7 _RDRS.Bits.RDRS7 + +#define RDRS_RDRS0_MASK 1U +#define RDRS_RDRS1_MASK 2U +#define RDRS_RDRS2_MASK 4U +#define RDRS_RDRS3_MASK 8U +#define RDRS_RDRS4_MASK 16U +#define RDRS_RDRS5_MASK 32U +#define RDRS_RDRS6_MASK 64U +#define RDRS_RDRS7_MASK 128U + + +/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/ +typedef union { + byte Byte; + struct { + byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */ + byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */ + byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */ + byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */ + byte PERS4 :1; /* Pull Device Enable Port S Bit 4 */ + byte PERS5 :1; /* Pull Device Enable Port S Bit 5 */ + byte PERS6 :1; /* Pull Device Enable Port S Bit 6 */ + byte PERS7 :1; /* Pull Device Enable Port S Bit 7 */ + } Bits; +} PERSSTR; +extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024CUL); +#define PERS _PERS.Byte +#define PERS_PERS0 _PERS.Bits.PERS0 +#define PERS_PERS1 _PERS.Bits.PERS1 +#define PERS_PERS2 _PERS.Bits.PERS2 +#define PERS_PERS3 _PERS.Bits.PERS3 +#define PERS_PERS4 _PERS.Bits.PERS4 +#define PERS_PERS5 _PERS.Bits.PERS5 +#define PERS_PERS6 _PERS.Bits.PERS6 +#define PERS_PERS7 _PERS.Bits.PERS7 + +#define PERS_PERS0_MASK 1U +#define PERS_PERS1_MASK 2U +#define PERS_PERS2_MASK 4U +#define PERS_PERS3_MASK 8U +#define PERS_PERS4_MASK 16U +#define PERS_PERS5_MASK 32U +#define PERS_PERS6_MASK 64U +#define PERS_PERS7_MASK 128U + + +/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/ +typedef union { + byte Byte; + struct { + byte PPSS0 :1; /* Pull Select Port S Bit 0 */ + byte PPSS1 :1; /* Pull Select Port S Bit 1 */ + byte PPSS2 :1; /* Pull Select Port S Bit 2 */ + byte PPSS3 :1; /* Pull Select Port S Bit 3 */ + byte PPSS4 :1; /* Pull Select Port S Bit 4 */ + byte PPSS5 :1; /* Pull Select Port S Bit 5 */ + byte PPSS6 :1; /* Pull Select Port S Bit 6 */ + byte PPSS7 :1; /* Pull Select Port S Bit 7 */ + } Bits; +} PPSSSTR; +extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024DUL); +#define PPSS _PPSS.Byte +#define PPSS_PPSS0 _PPSS.Bits.PPSS0 +#define PPSS_PPSS1 _PPSS.Bits.PPSS1 +#define PPSS_PPSS2 _PPSS.Bits.PPSS2 +#define PPSS_PPSS3 _PPSS.Bits.PPSS3 +#define PPSS_PPSS4 _PPSS.Bits.PPSS4 +#define PPSS_PPSS5 _PPSS.Bits.PPSS5 +#define PPSS_PPSS6 _PPSS.Bits.PPSS6 +#define PPSS_PPSS7 _PPSS.Bits.PPSS7 + +#define PPSS_PPSS0_MASK 1U +#define PPSS_PPSS1_MASK 2U +#define PPSS_PPSS2_MASK 4U +#define PPSS_PPSS3_MASK 8U +#define PPSS_PPSS4_MASK 16U +#define PPSS_PPSS5_MASK 32U +#define PPSS_PPSS6_MASK 64U +#define PPSS_PPSS7_MASK 128U + + +/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/ +typedef union { + byte Byte; + struct { + byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */ + byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */ + byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */ + byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */ + byte WOMS4 :1; /* Wired-Or Mode Port S Bit 4 */ + byte WOMS5 :1; /* Wired-Or Mode Port S Bit 5 */ + byte WOMS6 :1; /* Wired-Or Mode Port S Bit 6 */ + byte WOMS7 :1; /* Wired-Or Mode Port S Bit 7 */ + } Bits; +} WOMSSTR; +extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024EUL); +#define WOMS _WOMS.Byte +#define WOMS_WOMS0 _WOMS.Bits.WOMS0 +#define WOMS_WOMS1 _WOMS.Bits.WOMS1 +#define WOMS_WOMS2 _WOMS.Bits.WOMS2 +#define WOMS_WOMS3 _WOMS.Bits.WOMS3 +#define WOMS_WOMS4 _WOMS.Bits.WOMS4 +#define WOMS_WOMS5 _WOMS.Bits.WOMS5 +#define WOMS_WOMS6 _WOMS.Bits.WOMS6 +#define WOMS_WOMS7 _WOMS.Bits.WOMS7 + +#define WOMS_WOMS0_MASK 1U +#define WOMS_WOMS1_MASK 2U +#define WOMS_WOMS2_MASK 4U +#define WOMS_WOMS3_MASK 8U +#define WOMS_WOMS4_MASK 16U +#define WOMS_WOMS5_MASK 32U +#define WOMS_WOMS6_MASK 64U +#define WOMS_WOMS7_MASK 128U + + +/*** PTM - Port M I/O Register; 0x00000250 ***/ +typedef union { + byte Byte; + struct { + byte PTM0 :1; /* Port M Bit 0 */ + byte PTM1 :1; /* Port M Bit 1 */ + byte PTM2 :1; /* Port M Bit 2 */ + byte PTM3 :1; /* Port M Bit 3 */ + byte PTM4 :1; /* Port M Bit 4 */ + byte PTM5 :1; /* Port M Bit 5 */ + byte PTM6 :1; /* Port M Bit 6 */ + byte PTM7 :1; /* Port M Bit 7 */ + } Bits; +} PTMSTR; +extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250UL); +#define PTM _PTM.Byte +#define PTM_PTM0 _PTM.Bits.PTM0 +#define PTM_PTM1 _PTM.Bits.PTM1 +#define PTM_PTM2 _PTM.Bits.PTM2 +#define PTM_PTM3 _PTM.Bits.PTM3 +#define PTM_PTM4 _PTM.Bits.PTM4 +#define PTM_PTM5 _PTM.Bits.PTM5 +#define PTM_PTM6 _PTM.Bits.PTM6 +#define PTM_PTM7 _PTM.Bits.PTM7 + +#define PTM_PTM0_MASK 1U +#define PTM_PTM1_MASK 2U +#define PTM_PTM2_MASK 4U +#define PTM_PTM3_MASK 8U +#define PTM_PTM4_MASK 16U +#define PTM_PTM5_MASK 32U +#define PTM_PTM6_MASK 64U +#define PTM_PTM7_MASK 128U + + +/*** PTIM - Port M Input Register; 0x00000251 ***/ +typedef union { + byte Byte; + struct { + byte PTIM0 :1; /* Port M Bit 0 */ + byte PTIM1 :1; /* Port M Bit 1 */ + byte PTIM2 :1; /* Port M Bit 2 */ + byte PTIM3 :1; /* Port M Bit 3 */ + byte PTIM4 :1; /* Port M Bit 4 */ + byte PTIM5 :1; /* Port M Bit 5 */ + byte PTIM6 :1; /* Port M Bit 6 */ + byte PTIM7 :1; /* Port M Bit 7 */ + } Bits; +} PTIMSTR; +extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251UL); +#define PTIM _PTIM.Byte +#define PTIM_PTIM0 _PTIM.Bits.PTIM0 +#define PTIM_PTIM1 _PTIM.Bits.PTIM1 +#define PTIM_PTIM2 _PTIM.Bits.PTIM2 +#define PTIM_PTIM3 _PTIM.Bits.PTIM3 +#define PTIM_PTIM4 _PTIM.Bits.PTIM4 +#define PTIM_PTIM5 _PTIM.Bits.PTIM5 +#define PTIM_PTIM6 _PTIM.Bits.PTIM6 +#define PTIM_PTIM7 _PTIM.Bits.PTIM7 + +#define PTIM_PTIM0_MASK 1U +#define PTIM_PTIM1_MASK 2U +#define PTIM_PTIM2_MASK 4U +#define PTIM_PTIM3_MASK 8U +#define PTIM_PTIM4_MASK 16U +#define PTIM_PTIM5_MASK 32U +#define PTIM_PTIM6_MASK 64U +#define PTIM_PTIM7_MASK 128U + + +/*** DDRM - Port M Data Direction Register; 0x00000252 ***/ +typedef union { + byte Byte; + struct { + byte DDRM0 :1; /* Data Direction Port M Bit 0 */ + byte DDRM1 :1; /* Data Direction Port M Bit 1 */ + byte DDRM2 :1; /* Data Direction Port M Bit 2 */ + byte DDRM3 :1; /* Data Direction Port M Bit 3 */ + byte DDRM4 :1; /* Data Direction Port M Bit 4 */ + byte DDRM5 :1; /* Data Direction Port M Bit 5 */ + byte DDRM6 :1; /* Data Direction Port M Bit 6 */ + byte DDRM7 :1; /* Data Direction Port M Bit 7 */ + } Bits; +} DDRMSTR; +extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252UL); +#define DDRM _DDRM.Byte +#define DDRM_DDRM0 _DDRM.Bits.DDRM0 +#define DDRM_DDRM1 _DDRM.Bits.DDRM1 +#define DDRM_DDRM2 _DDRM.Bits.DDRM2 +#define DDRM_DDRM3 _DDRM.Bits.DDRM3 +#define DDRM_DDRM4 _DDRM.Bits.DDRM4 +#define DDRM_DDRM5 _DDRM.Bits.DDRM5 +#define DDRM_DDRM6 _DDRM.Bits.DDRM6 +#define DDRM_DDRM7 _DDRM.Bits.DDRM7 + +#define DDRM_DDRM0_MASK 1U +#define DDRM_DDRM1_MASK 2U +#define DDRM_DDRM2_MASK 4U +#define DDRM_DDRM3_MASK 8U +#define DDRM_DDRM4_MASK 16U +#define DDRM_DDRM5_MASK 32U +#define DDRM_DDRM6_MASK 64U +#define DDRM_DDRM7_MASK 128U + + +/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/ +typedef union { + byte Byte; + struct { + byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */ + byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */ + byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */ + byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */ + byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */ + byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */ + byte RDRM6 :1; /* Reduced Drive Port M Bit 6 */ + byte RDRM7 :1; /* Reduced Drive Port M Bit 7 */ + } Bits; +} RDRMSTR; +extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253UL); +#define RDRM _RDRM.Byte +#define RDRM_RDRM0 _RDRM.Bits.RDRM0 +#define RDRM_RDRM1 _RDRM.Bits.RDRM1 +#define RDRM_RDRM2 _RDRM.Bits.RDRM2 +#define RDRM_RDRM3 _RDRM.Bits.RDRM3 +#define RDRM_RDRM4 _RDRM.Bits.RDRM4 +#define RDRM_RDRM5 _RDRM.Bits.RDRM5 +#define RDRM_RDRM6 _RDRM.Bits.RDRM6 +#define RDRM_RDRM7 _RDRM.Bits.RDRM7 + +#define RDRM_RDRM0_MASK 1U +#define RDRM_RDRM1_MASK 2U +#define RDRM_RDRM2_MASK 4U +#define RDRM_RDRM3_MASK 8U +#define RDRM_RDRM4_MASK 16U +#define RDRM_RDRM5_MASK 32U +#define RDRM_RDRM6_MASK 64U +#define RDRM_RDRM7_MASK 128U + + +/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/ +typedef union { + byte Byte; + struct { + byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */ + byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */ + byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */ + byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */ + byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */ + byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */ + byte PERM6 :1; /* Pull Device Enable Port M Bit 6 */ + byte PERM7 :1; /* Pull Device Enable Port M Bit 7 */ + } Bits; +} PERMSTR; +extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254UL); +#define PERM _PERM.Byte +#define PERM_PERM0 _PERM.Bits.PERM0 +#define PERM_PERM1 _PERM.Bits.PERM1 +#define PERM_PERM2 _PERM.Bits.PERM2 +#define PERM_PERM3 _PERM.Bits.PERM3 +#define PERM_PERM4 _PERM.Bits.PERM4 +#define PERM_PERM5 _PERM.Bits.PERM5 +#define PERM_PERM6 _PERM.Bits.PERM6 +#define PERM_PERM7 _PERM.Bits.PERM7 + +#define PERM_PERM0_MASK 1U +#define PERM_PERM1_MASK 2U +#define PERM_PERM2_MASK 4U +#define PERM_PERM3_MASK 8U +#define PERM_PERM4_MASK 16U +#define PERM_PERM5_MASK 32U +#define PERM_PERM6_MASK 64U +#define PERM_PERM7_MASK 128U + + +/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/ +typedef union { + byte Byte; + struct { + byte PPSM0 :1; /* Pull Select Port M Bit 0 */ + byte PPSM1 :1; /* Pull Select Port M Bit 1 */ + byte PPSM2 :1; /* Pull Select Port M Bit 2 */ + byte PPSM3 :1; /* Pull Select Port M Bit 3 */ + byte PPSM4 :1; /* Pull Select Port M Bit 4 */ + byte PPSM5 :1; /* Pull Select Port M Bit 5 */ + byte PPSM6 :1; /* Pull Select Port M Bit 6 */ + byte PPSM7 :1; /* Pull Select Port M Bit 7 */ + } Bits; +} PPSMSTR; +extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255UL); +#define PPSM _PPSM.Byte +#define PPSM_PPSM0 _PPSM.Bits.PPSM0 +#define PPSM_PPSM1 _PPSM.Bits.PPSM1 +#define PPSM_PPSM2 _PPSM.Bits.PPSM2 +#define PPSM_PPSM3 _PPSM.Bits.PPSM3 +#define PPSM_PPSM4 _PPSM.Bits.PPSM4 +#define PPSM_PPSM5 _PPSM.Bits.PPSM5 +#define PPSM_PPSM6 _PPSM.Bits.PPSM6 +#define PPSM_PPSM7 _PPSM.Bits.PPSM7 + +#define PPSM_PPSM0_MASK 1U +#define PPSM_PPSM1_MASK 2U +#define PPSM_PPSM2_MASK 4U +#define PPSM_PPSM3_MASK 8U +#define PPSM_PPSM4_MASK 16U +#define PPSM_PPSM5_MASK 32U +#define PPSM_PPSM6_MASK 64U +#define PPSM_PPSM7_MASK 128U + + +/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/ +typedef union { + byte Byte; + struct { + byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */ + byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */ + byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */ + byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */ + byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */ + byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */ + byte WOMM6 :1; /* Wired-Or Mode Port M Bit 6 */ + byte WOMM7 :1; /* Wired-Or Mode Port M Bit 7 */ + } Bits; +} WOMMSTR; +extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256UL); +#define WOMM _WOMM.Byte +#define WOMM_WOMM0 _WOMM.Bits.WOMM0 +#define WOMM_WOMM1 _WOMM.Bits.WOMM1 +#define WOMM_WOMM2 _WOMM.Bits.WOMM2 +#define WOMM_WOMM3 _WOMM.Bits.WOMM3 +#define WOMM_WOMM4 _WOMM.Bits.WOMM4 +#define WOMM_WOMM5 _WOMM.Bits.WOMM5 +#define WOMM_WOMM6 _WOMM.Bits.WOMM6 +#define WOMM_WOMM7 _WOMM.Bits.WOMM7 + +#define WOMM_WOMM0_MASK 1U +#define WOMM_WOMM1_MASK 2U +#define WOMM_WOMM2_MASK 4U +#define WOMM_WOMM3_MASK 8U +#define WOMM_WOMM4_MASK 16U +#define WOMM_WOMM5_MASK 32U +#define WOMM_WOMM6_MASK 64U +#define WOMM_WOMM7_MASK 128U + + +/*** MODRR - Module Routing Register; 0x00000257 ***/ +typedef union { + byte Byte; + struct { + byte MODRR0 :1; /* CAN0 Routing Bit 0 */ + byte MODRR1 :1; /* CAN0 Routing Bit 1 */ + byte MODRR2 :1; /* CAN4 Routing Bit 0 */ + byte MODRR3 :1; /* CAN4 Routing Bit 1 */ + byte MODRR4 :1; /* SPI0 Routing */ + byte MODRR5 :1; /* SPI1 Routing */ + byte MODRR6 :1; /* SPI2 Routing */ + byte :1; + } Bits; + struct { + byte grpMODRR :7; + byte :1; + } MergedBits; +} MODRRSTR; +extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000257UL); +#define MODRR _MODRR.Byte +#define MODRR_MODRR0 _MODRR.Bits.MODRR0 +#define MODRR_MODRR1 _MODRR.Bits.MODRR1 +#define MODRR_MODRR2 _MODRR.Bits.MODRR2 +#define MODRR_MODRR3 _MODRR.Bits.MODRR3 +#define MODRR_MODRR4 _MODRR.Bits.MODRR4 +#define MODRR_MODRR5 _MODRR.Bits.MODRR5 +#define MODRR_MODRR6 _MODRR.Bits.MODRR6 +#define MODRR_MODRR _MODRR.MergedBits.grpMODRR + +#define MODRR_MODRR0_MASK 1U +#define MODRR_MODRR1_MASK 2U +#define MODRR_MODRR2_MASK 4U +#define MODRR_MODRR3_MASK 8U +#define MODRR_MODRR4_MASK 16U +#define MODRR_MODRR5_MASK 32U +#define MODRR_MODRR6_MASK 64U +#define MODRR_MODRR_MASK 127U +#define MODRR_MODRR_BITNUM 0U + + +/*** PTP - Port P I/O Register; 0x00000258 ***/ +typedef union { + byte Byte; + struct { + byte PTP0 :1; /* Port P Bit 0 */ + byte PTP1 :1; /* Port P Bit 1 */ + byte PTP2 :1; /* Port P Bit 2 */ + byte PTP3 :1; /* Port P Bit 3 */ + byte PTP4 :1; /* Port P Bit 4 */ + byte PTP5 :1; /* Port P Bit 5 */ + byte PTP6 :1; /* Port P Bit 6 */ + byte PTP7 :1; /* Port P Bit 7 */ + } Bits; +} PTPSTR; +extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258UL); +#define PTP _PTP.Byte +#define PTP_PTP0 _PTP.Bits.PTP0 +#define PTP_PTP1 _PTP.Bits.PTP1 +#define PTP_PTP2 _PTP.Bits.PTP2 +#define PTP_PTP3 _PTP.Bits.PTP3 +#define PTP_PTP4 _PTP.Bits.PTP4 +#define PTP_PTP5 _PTP.Bits.PTP5 +#define PTP_PTP6 _PTP.Bits.PTP6 +#define PTP_PTP7 _PTP.Bits.PTP7 + +#define PTP_PTP0_MASK 1U +#define PTP_PTP1_MASK 2U +#define PTP_PTP2_MASK 4U +#define PTP_PTP3_MASK 8U +#define PTP_PTP4_MASK 16U +#define PTP_PTP5_MASK 32U +#define PTP_PTP6_MASK 64U +#define PTP_PTP7_MASK 128U + + +/*** PTIP - Port P Input Register; 0x00000259 ***/ +typedef union { + byte Byte; + struct { + byte PTIP0 :1; /* Port P Bit 0 */ + byte PTIP1 :1; /* Port P Bit 1 */ + byte PTIP2 :1; /* Port P Bit 2 */ + byte PTIP3 :1; /* Port P Bit 3 */ + byte PTIP4 :1; /* Port P Bit 4 */ + byte PTIP5 :1; /* Port P Bit 5 */ + byte PTIP6 :1; /* Port P Bit 6 */ + byte PTIP7 :1; /* Port P Bit 7 */ + } Bits; +} PTIPSTR; +extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259UL); +#define PTIP _PTIP.Byte +#define PTIP_PTIP0 _PTIP.Bits.PTIP0 +#define PTIP_PTIP1 _PTIP.Bits.PTIP1 +#define PTIP_PTIP2 _PTIP.Bits.PTIP2 +#define PTIP_PTIP3 _PTIP.Bits.PTIP3 +#define PTIP_PTIP4 _PTIP.Bits.PTIP4 +#define PTIP_PTIP5 _PTIP.Bits.PTIP5 +#define PTIP_PTIP6 _PTIP.Bits.PTIP6 +#define PTIP_PTIP7 _PTIP.Bits.PTIP7 + +#define PTIP_PTIP0_MASK 1U +#define PTIP_PTIP1_MASK 2U +#define PTIP_PTIP2_MASK 4U +#define PTIP_PTIP3_MASK 8U +#define PTIP_PTIP4_MASK 16U +#define PTIP_PTIP5_MASK 32U +#define PTIP_PTIP6_MASK 64U +#define PTIP_PTIP7_MASK 128U + + +/*** DDRP - Port P Data Direction Register; 0x0000025A ***/ +typedef union { + byte Byte; + struct { + byte DDRP0 :1; /* Data Direction Port P Bit 0 */ + byte DDRP1 :1; /* Data Direction Port P Bit 1 */ + byte DDRP2 :1; /* Data Direction Port P Bit 2 */ + byte DDRP3 :1; /* Data Direction Port P Bit 3 */ + byte DDRP4 :1; /* Data Direction Port P Bit 4 */ + byte DDRP5 :1; /* Data Direction Port P Bit 5 */ + byte DDRP6 :1; /* Data Direction Port P Bit 6 */ + byte DDRP7 :1; /* Data Direction Port P Bit 7 */ + } Bits; +} DDRPSTR; +extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025AUL); +#define DDRP _DDRP.Byte +#define DDRP_DDRP0 _DDRP.Bits.DDRP0 +#define DDRP_DDRP1 _DDRP.Bits.DDRP1 +#define DDRP_DDRP2 _DDRP.Bits.DDRP2 +#define DDRP_DDRP3 _DDRP.Bits.DDRP3 +#define DDRP_DDRP4 _DDRP.Bits.DDRP4 +#define DDRP_DDRP5 _DDRP.Bits.DDRP5 +#define DDRP_DDRP6 _DDRP.Bits.DDRP6 +#define DDRP_DDRP7 _DDRP.Bits.DDRP7 + +#define DDRP_DDRP0_MASK 1U +#define DDRP_DDRP1_MASK 2U +#define DDRP_DDRP2_MASK 4U +#define DDRP_DDRP3_MASK 8U +#define DDRP_DDRP4_MASK 16U +#define DDRP_DDRP5_MASK 32U +#define DDRP_DDRP6_MASK 64U +#define DDRP_DDRP7_MASK 128U + + +/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/ +typedef union { + byte Byte; + struct { + byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */ + byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */ + byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */ + byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */ + byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */ + byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */ + byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */ + byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */ + } Bits; +} RDRPSTR; +extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025BUL); +#define RDRP _RDRP.Byte +#define RDRP_RDRP0 _RDRP.Bits.RDRP0 +#define RDRP_RDRP1 _RDRP.Bits.RDRP1 +#define RDRP_RDRP2 _RDRP.Bits.RDRP2 +#define RDRP_RDRP3 _RDRP.Bits.RDRP3 +#define RDRP_RDRP4 _RDRP.Bits.RDRP4 +#define RDRP_RDRP5 _RDRP.Bits.RDRP5 +#define RDRP_RDRP6 _RDRP.Bits.RDRP6 +#define RDRP_RDRP7 _RDRP.Bits.RDRP7 + +#define RDRP_RDRP0_MASK 1U +#define RDRP_RDRP1_MASK 2U +#define RDRP_RDRP2_MASK 4U +#define RDRP_RDRP3_MASK 8U +#define RDRP_RDRP4_MASK 16U +#define RDRP_RDRP5_MASK 32U +#define RDRP_RDRP6_MASK 64U +#define RDRP_RDRP7_MASK 128U + + +/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/ +typedef union { + byte Byte; + struct { + byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */ + byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */ + byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */ + byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */ + byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */ + byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */ + byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */ + byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */ + } Bits; +} PERPSTR; +extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025CUL); +#define PERP _PERP.Byte +#define PERP_PERP0 _PERP.Bits.PERP0 +#define PERP_PERP1 _PERP.Bits.PERP1 +#define PERP_PERP2 _PERP.Bits.PERP2 +#define PERP_PERP3 _PERP.Bits.PERP3 +#define PERP_PERP4 _PERP.Bits.PERP4 +#define PERP_PERP5 _PERP.Bits.PERP5 +#define PERP_PERP6 _PERP.Bits.PERP6 +#define PERP_PERP7 _PERP.Bits.PERP7 + +#define PERP_PERP0_MASK 1U +#define PERP_PERP1_MASK 2U +#define PERP_PERP2_MASK 4U +#define PERP_PERP3_MASK 8U +#define PERP_PERP4_MASK 16U +#define PERP_PERP5_MASK 32U +#define PERP_PERP6_MASK 64U +#define PERP_PERP7_MASK 128U + + +/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/ +typedef union { + byte Byte; + struct { + byte PPSP0 :1; /* Pull Select Port P Bit 0 */ + byte PPSP1 :1; /* Pull Select Port P Bit 1 */ + byte PPSP2 :1; /* Pull Select Port P Bit 2 */ + byte PPSP3 :1; /* Pull Select Port P Bit 3 */ + byte PPSP4 :1; /* Pull Select Port P Bit 4 */ + byte PPSP5 :1; /* Pull Select Port P Bit 5 */ + byte PPSP6 :1; /* Pull Select Port P Bit 6 */ + byte PPSP7 :1; /* Pull Select Port P Bit 7 */ + } Bits; +} PPSPSTR; +extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025DUL); +#define PPSP _PPSP.Byte +#define PPSP_PPSP0 _PPSP.Bits.PPSP0 +#define PPSP_PPSP1 _PPSP.Bits.PPSP1 +#define PPSP_PPSP2 _PPSP.Bits.PPSP2 +#define PPSP_PPSP3 _PPSP.Bits.PPSP3 +#define PPSP_PPSP4 _PPSP.Bits.PPSP4 +#define PPSP_PPSP5 _PPSP.Bits.PPSP5 +#define PPSP_PPSP6 _PPSP.Bits.PPSP6 +#define PPSP_PPSP7 _PPSP.Bits.PPSP7 + +#define PPSP_PPSP0_MASK 1U +#define PPSP_PPSP1_MASK 2U +#define PPSP_PPSP2_MASK 4U +#define PPSP_PPSP3_MASK 8U +#define PPSP_PPSP4_MASK 16U +#define PPSP_PPSP5_MASK 32U +#define PPSP_PPSP6_MASK 64U +#define PPSP_PPSP7_MASK 128U + + +/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/ +typedef union { + byte Byte; + struct { + byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */ + byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */ + byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */ + byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */ + byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */ + byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */ + byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */ + byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */ + } Bits; +} PIEPSTR; +extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025EUL); +#define PIEP _PIEP.Byte +#define PIEP_PIEP0 _PIEP.Bits.PIEP0 +#define PIEP_PIEP1 _PIEP.Bits.PIEP1 +#define PIEP_PIEP2 _PIEP.Bits.PIEP2 +#define PIEP_PIEP3 _PIEP.Bits.PIEP3 +#define PIEP_PIEP4 _PIEP.Bits.PIEP4 +#define PIEP_PIEP5 _PIEP.Bits.PIEP5 +#define PIEP_PIEP6 _PIEP.Bits.PIEP6 +#define PIEP_PIEP7 _PIEP.Bits.PIEP7 + +#define PIEP_PIEP0_MASK 1U +#define PIEP_PIEP1_MASK 2U +#define PIEP_PIEP2_MASK 4U +#define PIEP_PIEP3_MASK 8U +#define PIEP_PIEP4_MASK 16U +#define PIEP_PIEP5_MASK 32U +#define PIEP_PIEP6_MASK 64U +#define PIEP_PIEP7_MASK 128U + + +/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/ +typedef union { + byte Byte; + struct { + byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */ + byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */ + byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */ + byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */ + byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */ + byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */ + byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */ + byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */ + } Bits; +} PIFPSTR; +extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025FUL); +#define PIFP _PIFP.Byte +#define PIFP_PIFP0 _PIFP.Bits.PIFP0 +#define PIFP_PIFP1 _PIFP.Bits.PIFP1 +#define PIFP_PIFP2 _PIFP.Bits.PIFP2 +#define PIFP_PIFP3 _PIFP.Bits.PIFP3 +#define PIFP_PIFP4 _PIFP.Bits.PIFP4 +#define PIFP_PIFP5 _PIFP.Bits.PIFP5 +#define PIFP_PIFP6 _PIFP.Bits.PIFP6 +#define PIFP_PIFP7 _PIFP.Bits.PIFP7 + +#define PIFP_PIFP0_MASK 1U +#define PIFP_PIFP1_MASK 2U +#define PIFP_PIFP2_MASK 4U +#define PIFP_PIFP3_MASK 8U +#define PIFP_PIFP4_MASK 16U +#define PIFP_PIFP5_MASK 32U +#define PIFP_PIFP6_MASK 64U +#define PIFP_PIFP7_MASK 128U + + +/*** PTH - Port H I/O Register; 0x00000260 ***/ +typedef union { + byte Byte; + struct { + byte PTH0 :1; /* Port H Bit 0 */ + byte PTH1 :1; /* Port H Bit 1 */ + byte PTH2 :1; /* Port H Bit 2 */ + byte PTH3 :1; /* Port H Bit 3 */ + byte PTH4 :1; /* Port H Bit 4 */ + byte PTH5 :1; /* Port H Bit 5 */ + byte PTH6 :1; /* Port H Bit 6 */ + byte PTH7 :1; /* Port H Bit 7 */ + } Bits; +} PTHSTR; +extern volatile PTHSTR _PTH @(REG_BASE + 0x00000260UL); +#define PTH _PTH.Byte +#define PTH_PTH0 _PTH.Bits.PTH0 +#define PTH_PTH1 _PTH.Bits.PTH1 +#define PTH_PTH2 _PTH.Bits.PTH2 +#define PTH_PTH3 _PTH.Bits.PTH3 +#define PTH_PTH4 _PTH.Bits.PTH4 +#define PTH_PTH5 _PTH.Bits.PTH5 +#define PTH_PTH6 _PTH.Bits.PTH6 +#define PTH_PTH7 _PTH.Bits.PTH7 + +#define PTH_PTH0_MASK 1U +#define PTH_PTH1_MASK 2U +#define PTH_PTH2_MASK 4U +#define PTH_PTH3_MASK 8U +#define PTH_PTH4_MASK 16U +#define PTH_PTH5_MASK 32U +#define PTH_PTH6_MASK 64U +#define PTH_PTH7_MASK 128U + + +/*** PTIH - Port H Input Register; 0x00000261 ***/ +typedef union { + byte Byte; + struct { + byte PTIH0 :1; /* Port H Bit 0 */ + byte PTIH1 :1; /* Port H Bit 1 */ + byte PTIH2 :1; /* Port H Bit 2 */ + byte PTIH3 :1; /* Port H Bit 3 */ + byte PTIH4 :1; /* Port H Bit 4 */ + byte PTIH5 :1; /* Port H Bit 5 */ + byte PTIH6 :1; /* Port H Bit 6 */ + byte PTIH7 :1; /* Port H Bit 7 */ + } Bits; +} PTIHSTR; +extern volatile PTIHSTR _PTIH @(REG_BASE + 0x00000261UL); +#define PTIH _PTIH.Byte +#define PTIH_PTIH0 _PTIH.Bits.PTIH0 +#define PTIH_PTIH1 _PTIH.Bits.PTIH1 +#define PTIH_PTIH2 _PTIH.Bits.PTIH2 +#define PTIH_PTIH3 _PTIH.Bits.PTIH3 +#define PTIH_PTIH4 _PTIH.Bits.PTIH4 +#define PTIH_PTIH5 _PTIH.Bits.PTIH5 +#define PTIH_PTIH6 _PTIH.Bits.PTIH6 +#define PTIH_PTIH7 _PTIH.Bits.PTIH7 + +#define PTIH_PTIH0_MASK 1U +#define PTIH_PTIH1_MASK 2U +#define PTIH_PTIH2_MASK 4U +#define PTIH_PTIH3_MASK 8U +#define PTIH_PTIH4_MASK 16U +#define PTIH_PTIH5_MASK 32U +#define PTIH_PTIH6_MASK 64U +#define PTIH_PTIH7_MASK 128U + + +/*** DDRH - Port H Data Direction Register; 0x00000262 ***/ +typedef union { + byte Byte; + struct { + byte DDRH0 :1; /* Data Direction Port H Bit 0 */ + byte DDRH1 :1; /* Data Direction Port H Bit 1 */ + byte DDRH2 :1; /* Data Direction Port H Bit 2 */ + byte DDRH3 :1; /* Data Direction Port H Bit 3 */ + byte DDRH4 :1; /* Data Direction Port H Bit 4 */ + byte DDRH5 :1; /* Data Direction Port H Bit 5 */ + byte DDRH6 :1; /* Data Direction Port H Bit 6 */ + byte DDRH7 :1; /* Data Direction Port H Bit 7 */ + } Bits; +} DDRHSTR; +extern volatile DDRHSTR _DDRH @(REG_BASE + 0x00000262UL); +#define DDRH _DDRH.Byte +#define DDRH_DDRH0 _DDRH.Bits.DDRH0 +#define DDRH_DDRH1 _DDRH.Bits.DDRH1 +#define DDRH_DDRH2 _DDRH.Bits.DDRH2 +#define DDRH_DDRH3 _DDRH.Bits.DDRH3 +#define DDRH_DDRH4 _DDRH.Bits.DDRH4 +#define DDRH_DDRH5 _DDRH.Bits.DDRH5 +#define DDRH_DDRH6 _DDRH.Bits.DDRH6 +#define DDRH_DDRH7 _DDRH.Bits.DDRH7 + +#define DDRH_DDRH0_MASK 1U +#define DDRH_DDRH1_MASK 2U +#define DDRH_DDRH2_MASK 4U +#define DDRH_DDRH3_MASK 8U +#define DDRH_DDRH4_MASK 16U +#define DDRH_DDRH5_MASK 32U +#define DDRH_DDRH6_MASK 64U +#define DDRH_DDRH7_MASK 128U + + +/*** RDRH - Port H Reduced Drive Register; 0x00000263 ***/ +typedef union { + byte Byte; + struct { + byte RDRH0 :1; /* Reduced Drive Port H Bit 0 */ + byte RDRH1 :1; /* Reduced Drive Port H Bit 1 */ + byte RDRH2 :1; /* Reduced Drive Port H Bit 2 */ + byte RDRH3 :1; /* Reduced Drive Port H Bit 3 */ + byte RDRH4 :1; /* Reduced Drive Port H Bit 4 */ + byte RDRH5 :1; /* Reduced Drive Port H Bit 5 */ + byte RDRH6 :1; /* Reduced Drive Port H Bit 6 */ + byte RDRH7 :1; /* Reduced Drive Port H Bit 7 */ + } Bits; +} RDRHSTR; +extern volatile RDRHSTR _RDRH @(REG_BASE + 0x00000263UL); +#define RDRH _RDRH.Byte +#define RDRH_RDRH0 _RDRH.Bits.RDRH0 +#define RDRH_RDRH1 _RDRH.Bits.RDRH1 +#define RDRH_RDRH2 _RDRH.Bits.RDRH2 +#define RDRH_RDRH3 _RDRH.Bits.RDRH3 +#define RDRH_RDRH4 _RDRH.Bits.RDRH4 +#define RDRH_RDRH5 _RDRH.Bits.RDRH5 +#define RDRH_RDRH6 _RDRH.Bits.RDRH6 +#define RDRH_RDRH7 _RDRH.Bits.RDRH7 + +#define RDRH_RDRH0_MASK 1U +#define RDRH_RDRH1_MASK 2U +#define RDRH_RDRH2_MASK 4U +#define RDRH_RDRH3_MASK 8U +#define RDRH_RDRH4_MASK 16U +#define RDRH_RDRH5_MASK 32U +#define RDRH_RDRH6_MASK 64U +#define RDRH_RDRH7_MASK 128U + + +/*** PERH - Port H Pull Device Enable Register; 0x00000264 ***/ +typedef union { + byte Byte; + struct { + byte PERH0 :1; /* Pull Device Enable Port H Bit 0 */ + byte PERH1 :1; /* Pull Device Enable Port H Bit 1 */ + byte PERH2 :1; /* Pull Device Enable Port H Bit 2 */ + byte PERH3 :1; /* Pull Device Enable Port H Bit 3 */ + byte PERH4 :1; /* Pull Device Enable Port H Bit 4 */ + byte PERH5 :1; /* Pull Device Enable Port H Bit 5 */ + byte PERH6 :1; /* Pull Device Enable Port H Bit 6 */ + byte PERH7 :1; /* Pull Device Enable Port H Bit 7 */ + } Bits; +} PERHSTR; +extern volatile PERHSTR _PERH @(REG_BASE + 0x00000264UL); +#define PERH _PERH.Byte +#define PERH_PERH0 _PERH.Bits.PERH0 +#define PERH_PERH1 _PERH.Bits.PERH1 +#define PERH_PERH2 _PERH.Bits.PERH2 +#define PERH_PERH3 _PERH.Bits.PERH3 +#define PERH_PERH4 _PERH.Bits.PERH4 +#define PERH_PERH5 _PERH.Bits.PERH5 +#define PERH_PERH6 _PERH.Bits.PERH6 +#define PERH_PERH7 _PERH.Bits.PERH7 + +#define PERH_PERH0_MASK 1U +#define PERH_PERH1_MASK 2U +#define PERH_PERH2_MASK 4U +#define PERH_PERH3_MASK 8U +#define PERH_PERH4_MASK 16U +#define PERH_PERH5_MASK 32U +#define PERH_PERH6_MASK 64U +#define PERH_PERH7_MASK 128U + + +/*** PPSH - Port H Polarity Select Register; 0x00000265 ***/ +typedef union { + byte Byte; + struct { + byte PPSH0 :1; /* Pull Select Port H Bit 0 */ + byte PPSH1 :1; /* Pull Select Port H Bit 1 */ + byte PPSH2 :1; /* Pull Select Port H Bit 2 */ + byte PPSH3 :1; /* Pull Select Port H Bit 3 */ + byte PPSH4 :1; /* Pull Select Port H Bit 4 */ + byte PPSH5 :1; /* Pull Select Port H Bit 5 */ + byte PPSH6 :1; /* Pull Select Port H Bit 6 */ + byte PPSH7 :1; /* Pull Select Port H Bit 7 */ + } Bits; +} PPSHSTR; +extern volatile PPSHSTR _PPSH @(REG_BASE + 0x00000265UL); +#define PPSH _PPSH.Byte +#define PPSH_PPSH0 _PPSH.Bits.PPSH0 +#define PPSH_PPSH1 _PPSH.Bits.PPSH1 +#define PPSH_PPSH2 _PPSH.Bits.PPSH2 +#define PPSH_PPSH3 _PPSH.Bits.PPSH3 +#define PPSH_PPSH4 _PPSH.Bits.PPSH4 +#define PPSH_PPSH5 _PPSH.Bits.PPSH5 +#define PPSH_PPSH6 _PPSH.Bits.PPSH6 +#define PPSH_PPSH7 _PPSH.Bits.PPSH7 + +#define PPSH_PPSH0_MASK 1U +#define PPSH_PPSH1_MASK 2U +#define PPSH_PPSH2_MASK 4U +#define PPSH_PPSH3_MASK 8U +#define PPSH_PPSH4_MASK 16U +#define PPSH_PPSH5_MASK 32U +#define PPSH_PPSH6_MASK 64U +#define PPSH_PPSH7_MASK 128U + + +/*** PIEH - Port H Interrupt Enable Register; 0x00000266 ***/ +typedef union { + byte Byte; + struct { + byte PIEH0 :1; /* Interrupt Enable Port H Bit 0 */ + byte PIEH1 :1; /* Interrupt Enable Port H Bit 1 */ + byte PIEH2 :1; /* Interrupt Enable Port H Bit 2 */ + byte PIEH3 :1; /* Interrupt Enable Port H Bit 3 */ + byte PIEH4 :1; /* Interrupt Enable Port H Bit 4 */ + byte PIEH5 :1; /* Interrupt Enable Port H Bit 5 */ + byte PIEH6 :1; /* Interrupt Enable Port H Bit 6 */ + byte PIEH7 :1; /* Interrupt Enable Port H Bit 7 */ + } Bits; +} PIEHSTR; +extern volatile PIEHSTR _PIEH @(REG_BASE + 0x00000266UL); +#define PIEH _PIEH.Byte +#define PIEH_PIEH0 _PIEH.Bits.PIEH0 +#define PIEH_PIEH1 _PIEH.Bits.PIEH1 +#define PIEH_PIEH2 _PIEH.Bits.PIEH2 +#define PIEH_PIEH3 _PIEH.Bits.PIEH3 +#define PIEH_PIEH4 _PIEH.Bits.PIEH4 +#define PIEH_PIEH5 _PIEH.Bits.PIEH5 +#define PIEH_PIEH6 _PIEH.Bits.PIEH6 +#define PIEH_PIEH7 _PIEH.Bits.PIEH7 + +#define PIEH_PIEH0_MASK 1U +#define PIEH_PIEH1_MASK 2U +#define PIEH_PIEH2_MASK 4U +#define PIEH_PIEH3_MASK 8U +#define PIEH_PIEH4_MASK 16U +#define PIEH_PIEH5_MASK 32U +#define PIEH_PIEH6_MASK 64U +#define PIEH_PIEH7_MASK 128U + + +/*** PIFH - Port H Interrupt Flag Register; 0x00000267 ***/ +typedef union { + byte Byte; + struct { + byte PIFH0 :1; /* Interrupt Flags Port H Bit 0 */ + byte PIFH1 :1; /* Interrupt Flags Port H Bit 1 */ + byte PIFH2 :1; /* Interrupt Flags Port H Bit 2 */ + byte PIFH3 :1; /* Interrupt Flags Port H Bit 3 */ + byte PIFH4 :1; /* Interrupt Flags Port H Bit 4 */ + byte PIFH5 :1; /* Interrupt Flags Port H Bit 5 */ + byte PIFH6 :1; /* Interrupt Flags Port H Bit 6 */ + byte PIFH7 :1; /* Interrupt Flags Port H Bit 7 */ + } Bits; +} PIFHSTR; +extern volatile PIFHSTR _PIFH @(REG_BASE + 0x00000267UL); +#define PIFH _PIFH.Byte +#define PIFH_PIFH0 _PIFH.Bits.PIFH0 +#define PIFH_PIFH1 _PIFH.Bits.PIFH1 +#define PIFH_PIFH2 _PIFH.Bits.PIFH2 +#define PIFH_PIFH3 _PIFH.Bits.PIFH3 +#define PIFH_PIFH4 _PIFH.Bits.PIFH4 +#define PIFH_PIFH5 _PIFH.Bits.PIFH5 +#define PIFH_PIFH6 _PIFH.Bits.PIFH6 +#define PIFH_PIFH7 _PIFH.Bits.PIFH7 + +#define PIFH_PIFH0_MASK 1U +#define PIFH_PIFH1_MASK 2U +#define PIFH_PIFH2_MASK 4U +#define PIFH_PIFH3_MASK 8U +#define PIFH_PIFH4_MASK 16U +#define PIFH_PIFH5_MASK 32U +#define PIFH_PIFH6_MASK 64U +#define PIFH_PIFH7_MASK 128U + + +/*** PTJ - Port J I/O Register; 0x00000268 ***/ +typedef union { + byte Byte; + struct { + byte PTJ0 :1; /* Port J Bit 0 */ + byte PTJ1 :1; /* Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PTJ6 :1; /* Port J Bit 6 */ + byte PTJ7 :1; /* Port J Bit 7 */ + } Bits; + struct { + byte grpPTJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPTJ_6 :2; + } MergedBits; +} PTJSTR; +extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268UL); +#define PTJ _PTJ.Byte +#define PTJ_PTJ0 _PTJ.Bits.PTJ0 +#define PTJ_PTJ1 _PTJ.Bits.PTJ1 +#define PTJ_PTJ6 _PTJ.Bits.PTJ6 +#define PTJ_PTJ7 _PTJ.Bits.PTJ7 +#define PTJ_PTJ _PTJ.MergedBits.grpPTJ +#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6 + +#define PTJ_PTJ0_MASK 1U +#define PTJ_PTJ1_MASK 2U +#define PTJ_PTJ6_MASK 64U +#define PTJ_PTJ7_MASK 128U +#define PTJ_PTJ_MASK 3U +#define PTJ_PTJ_BITNUM 0U +#define PTJ_PTJ_6_MASK 192U +#define PTJ_PTJ_6_BITNUM 6U + + +/*** PTIJ - Port J Input Register; 0x00000269 ***/ +typedef union { + byte Byte; + struct { + byte PTIJ0 :1; /* Port J Bit 0 */ + byte PTIJ1 :1; /* Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PTIJ6 :1; /* Port J Bit 6 */ + byte PTIJ7 :1; /* Port J Bit 7 */ + } Bits; + struct { + byte grpPTIJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPTIJ_6 :2; + } MergedBits; +} PTIJSTR; +extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269UL); +#define PTIJ _PTIJ.Byte +#define PTIJ_PTIJ0 _PTIJ.Bits.PTIJ0 +#define PTIJ_PTIJ1 _PTIJ.Bits.PTIJ1 +#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6 +#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7 +#define PTIJ_PTIJ _PTIJ.MergedBits.grpPTIJ +#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6 + +#define PTIJ_PTIJ0_MASK 1U +#define PTIJ_PTIJ1_MASK 2U +#define PTIJ_PTIJ6_MASK 64U +#define PTIJ_PTIJ7_MASK 128U +#define PTIJ_PTIJ_MASK 3U +#define PTIJ_PTIJ_BITNUM 0U +#define PTIJ_PTIJ_6_MASK 192U +#define PTIJ_PTIJ_6_BITNUM 6U + + +/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/ +typedef union { + byte Byte; + struct { + byte DDRJ0 :1; /* Data Direction Port J Bit 0 */ + byte DDRJ1 :1; /* Data Direction Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte DDRJ6 :1; /* Data Direction Port J Bit 6 */ + byte DDRJ7 :1; /* Data Direction Port J Bit 7 */ + } Bits; + struct { + byte grpDDRJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpDDRJ_6 :2; + } MergedBits; +} DDRJSTR; +extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026AUL); +#define DDRJ _DDRJ.Byte +#define DDRJ_DDRJ0 _DDRJ.Bits.DDRJ0 +#define DDRJ_DDRJ1 _DDRJ.Bits.DDRJ1 +#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6 +#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7 +#define DDRJ_DDRJ _DDRJ.MergedBits.grpDDRJ +#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6 + +#define DDRJ_DDRJ0_MASK 1U +#define DDRJ_DDRJ1_MASK 2U +#define DDRJ_DDRJ6_MASK 64U +#define DDRJ_DDRJ7_MASK 128U +#define DDRJ_DDRJ_MASK 3U +#define DDRJ_DDRJ_BITNUM 0U +#define DDRJ_DDRJ_6_MASK 192U +#define DDRJ_DDRJ_6_BITNUM 6U + + +/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/ +typedef union { + byte Byte; + struct { + byte RDRJ0 :1; /* Reduced Drive Port J Bit 0 */ + byte RDRJ1 :1; /* Reduced Drive Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */ + byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */ + } Bits; + struct { + byte grpRDRJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpRDRJ_6 :2; + } MergedBits; +} RDRJSTR; +extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026BUL); +#define RDRJ _RDRJ.Byte +#define RDRJ_RDRJ0 _RDRJ.Bits.RDRJ0 +#define RDRJ_RDRJ1 _RDRJ.Bits.RDRJ1 +#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6 +#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7 +#define RDRJ_RDRJ _RDRJ.MergedBits.grpRDRJ +#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6 + +#define RDRJ_RDRJ0_MASK 1U +#define RDRJ_RDRJ1_MASK 2U +#define RDRJ_RDRJ6_MASK 64U +#define RDRJ_RDRJ7_MASK 128U +#define RDRJ_RDRJ_MASK 3U +#define RDRJ_RDRJ_BITNUM 0U +#define RDRJ_RDRJ_6_MASK 192U +#define RDRJ_RDRJ_6_BITNUM 6U + + +/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/ +typedef union { + byte Byte; + struct { + byte PERJ0 :1; /* Pull Device Enable Port J Bit 0 */ + byte PERJ1 :1; /* Pull Device Enable Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */ + byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */ + } Bits; + struct { + byte grpPERJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPERJ_6 :2; + } MergedBits; +} PERJSTR; +extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026CUL); +#define PERJ _PERJ.Byte +#define PERJ_PERJ0 _PERJ.Bits.PERJ0 +#define PERJ_PERJ1 _PERJ.Bits.PERJ1 +#define PERJ_PERJ6 _PERJ.Bits.PERJ6 +#define PERJ_PERJ7 _PERJ.Bits.PERJ7 +#define PERJ_PERJ _PERJ.MergedBits.grpPERJ +#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6 + +#define PERJ_PERJ0_MASK 1U +#define PERJ_PERJ1_MASK 2U +#define PERJ_PERJ6_MASK 64U +#define PERJ_PERJ7_MASK 128U +#define PERJ_PERJ_MASK 3U +#define PERJ_PERJ_BITNUM 0U +#define PERJ_PERJ_6_MASK 192U +#define PERJ_PERJ_6_BITNUM 6U + + +/*** PPSJ - Port J Polarity Select Register; 0x0000026D ***/ +typedef union { + byte Byte; + struct { + byte PPSJ0 :1; /* Pull Select Port J Bit 0 */ + byte PPSJ1 :1; /* Pull Select Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PPSJ6 :1; /* Pull Select Port J Bit 6 */ + byte PPSJ7 :1; /* Pull Select Port J Bit 7 */ + } Bits; + struct { + byte grpPPSJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPPSJ_6 :2; + } MergedBits; +} PPSJSTR; +extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026DUL); +#define PPSJ _PPSJ.Byte +#define PPSJ_PPSJ0 _PPSJ.Bits.PPSJ0 +#define PPSJ_PPSJ1 _PPSJ.Bits.PPSJ1 +#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6 +#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7 +#define PPSJ_PPSJ _PPSJ.MergedBits.grpPPSJ +#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6 + +#define PPSJ_PPSJ0_MASK 1U +#define PPSJ_PPSJ1_MASK 2U +#define PPSJ_PPSJ6_MASK 64U +#define PPSJ_PPSJ7_MASK 128U +#define PPSJ_PPSJ_MASK 3U +#define PPSJ_PPSJ_BITNUM 0U +#define PPSJ_PPSJ_6_MASK 192U +#define PPSJ_PPSJ_6_BITNUM 6U + + +/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/ +typedef union { + byte Byte; + struct { + byte PIEJ0 :1; /* Interrupt Enable Port J Bit 0 */ + byte PIEJ1 :1; /* Interrupt Enable Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */ + byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */ + } Bits; + struct { + byte grpPIEJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPIEJ_6 :2; + } MergedBits; +} PIEJSTR; +extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026EUL); +#define PIEJ _PIEJ.Byte +#define PIEJ_PIEJ0 _PIEJ.Bits.PIEJ0 +#define PIEJ_PIEJ1 _PIEJ.Bits.PIEJ1 +#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6 +#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7 +#define PIEJ_PIEJ _PIEJ.MergedBits.grpPIEJ +#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6 + +#define PIEJ_PIEJ0_MASK 1U +#define PIEJ_PIEJ1_MASK 2U +#define PIEJ_PIEJ6_MASK 64U +#define PIEJ_PIEJ7_MASK 128U +#define PIEJ_PIEJ_MASK 3U +#define PIEJ_PIEJ_BITNUM 0U +#define PIEJ_PIEJ_6_MASK 192U +#define PIEJ_PIEJ_6_BITNUM 6U + + +/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/ +typedef union { + byte Byte; + struct { + byte PIFJ0 :1; /* Interrupt Flags Port J Bit 0 */ + byte PIFJ1 :1; /* Interrupt Flags Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */ + byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */ + } Bits; + struct { + byte grpPIFJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPIFJ_6 :2; + } MergedBits; +} PIFJSTR; +extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026FUL); +#define PIFJ _PIFJ.Byte +#define PIFJ_PIFJ0 _PIFJ.Bits.PIFJ0 +#define PIFJ_PIFJ1 _PIFJ.Bits.PIFJ1 +#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6 +#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7 +#define PIFJ_PIFJ _PIFJ.MergedBits.grpPIFJ +#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6 + +#define PIFJ_PIFJ0_MASK 1U +#define PIFJ_PIFJ1_MASK 2U +#define PIFJ_PIFJ6_MASK 64U +#define PIFJ_PIFJ7_MASK 128U +#define PIFJ_PIFJ_MASK 3U +#define PIFJ_PIFJ_BITNUM 0U +#define PIFJ_PIFJ_6_MASK 192U +#define PIFJ_PIFJ_6_BITNUM 6U + + +/*** CAN4CTL0 - MSCAN4 Control 0 Register; 0x00000280 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN4CTL0STR; +extern volatile CAN4CTL0STR _CAN4CTL0 @(REG_BASE + 0x00000280UL); +#define CAN4CTL0 _CAN4CTL0.Byte +#define CAN4CTL0_INITRQ _CAN4CTL0.Bits.INITRQ +#define CAN4CTL0_SLPRQ _CAN4CTL0.Bits.SLPRQ +#define CAN4CTL0_WUPE _CAN4CTL0.Bits.WUPE +#define CAN4CTL0_TIME _CAN4CTL0.Bits.TIME +#define CAN4CTL0_SYNCH _CAN4CTL0.Bits.SYNCH +#define CAN4CTL0_CSWAI _CAN4CTL0.Bits.CSWAI +#define CAN4CTL0_RXACT _CAN4CTL0.Bits.RXACT +#define CAN4CTL0_RXFRM _CAN4CTL0.Bits.RXFRM +/* CAN4CTL_ARR: Access 2 CAN4CTLx registers in an array */ +#define CAN4CTL_ARR ((volatile byte *) &CAN4CTL0) + +#define CAN4CTL0_INITRQ_MASK 1U +#define CAN4CTL0_SLPRQ_MASK 2U +#define CAN4CTL0_WUPE_MASK 4U +#define CAN4CTL0_TIME_MASK 8U +#define CAN4CTL0_SYNCH_MASK 16U +#define CAN4CTL0_CSWAI_MASK 32U +#define CAN4CTL0_RXACT_MASK 64U +#define CAN4CTL0_RXFRM_MASK 128U + + +/*** CAN4CTL1 - MSCAN4 Control 1 Register; 0x00000281 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN4 Clock Source */ + byte CANE :1; /* MSCAN4 Enable */ + } Bits; +} CAN4CTL1STR; +extern volatile CAN4CTL1STR _CAN4CTL1 @(REG_BASE + 0x00000281UL); +#define CAN4CTL1 _CAN4CTL1.Byte +#define CAN4CTL1_INITAK _CAN4CTL1.Bits.INITAK +#define CAN4CTL1_SLPAK _CAN4CTL1.Bits.SLPAK +#define CAN4CTL1_WUPM _CAN4CTL1.Bits.WUPM +#define CAN4CTL1_LISTEN _CAN4CTL1.Bits.LISTEN +#define CAN4CTL1_LOOPB _CAN4CTL1.Bits.LOOPB +#define CAN4CTL1_CLKSRC _CAN4CTL1.Bits.CLKSRC +#define CAN4CTL1_CANE _CAN4CTL1.Bits.CANE + +#define CAN4CTL1_INITAK_MASK 1U +#define CAN4CTL1_SLPAK_MASK 2U +#define CAN4CTL1_WUPM_MASK 4U +#define CAN4CTL1_LISTEN_MASK 16U +#define CAN4CTL1_LOOPB_MASK 32U +#define CAN4CTL1_CLKSRC_MASK 64U +#define CAN4CTL1_CANE_MASK 128U + + +/*** CAN4BTR0 - MSCAN4 Bus Timing Register 0; 0x00000282 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN4BTR0STR; +extern volatile CAN4BTR0STR _CAN4BTR0 @(REG_BASE + 0x00000282UL); +#define CAN4BTR0 _CAN4BTR0.Byte +#define CAN4BTR0_BRP0 _CAN4BTR0.Bits.BRP0 +#define CAN4BTR0_BRP1 _CAN4BTR0.Bits.BRP1 +#define CAN4BTR0_BRP2 _CAN4BTR0.Bits.BRP2 +#define CAN4BTR0_BRP3 _CAN4BTR0.Bits.BRP3 +#define CAN4BTR0_BRP4 _CAN4BTR0.Bits.BRP4 +#define CAN4BTR0_BRP5 _CAN4BTR0.Bits.BRP5 +#define CAN4BTR0_SJW0 _CAN4BTR0.Bits.SJW0 +#define CAN4BTR0_SJW1 _CAN4BTR0.Bits.SJW1 +/* CAN4BTR_ARR: Access 2 CAN4BTRx registers in an array */ +#define CAN4BTR_ARR ((volatile byte *) &CAN4BTR0) +#define CAN4BTR0_BRP _CAN4BTR0.MergedBits.grpBRP +#define CAN4BTR0_SJW _CAN4BTR0.MergedBits.grpSJW + +#define CAN4BTR0_BRP0_MASK 1U +#define CAN4BTR0_BRP1_MASK 2U +#define CAN4BTR0_BRP2_MASK 4U +#define CAN4BTR0_BRP3_MASK 8U +#define CAN4BTR0_BRP4_MASK 16U +#define CAN4BTR0_BRP5_MASK 32U +#define CAN4BTR0_SJW0_MASK 64U +#define CAN4BTR0_SJW1_MASK 128U +#define CAN4BTR0_BRP_MASK 63U +#define CAN4BTR0_BRP_BITNUM 0U +#define CAN4BTR0_SJW_MASK 192U +#define CAN4BTR0_SJW_BITNUM 6U + + +/*** CAN4BTR1 - MSCAN4 Bus Timing Register 1; 0x00000283 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 10 */ + byte TSEG11 :1; /* Time Segment 11 */ + byte TSEG12 :1; /* Time Segment 12 */ + byte TSEG13 :1; /* Time Segment 13 */ + byte TSEG20 :1; /* Time Segment 20 */ + byte TSEG21 :1; /* Time Segment 21 */ + byte TSEG22 :1; /* Time Segment 22 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN4BTR1STR; +extern volatile CAN4BTR1STR _CAN4BTR1 @(REG_BASE + 0x00000283UL); +#define CAN4BTR1 _CAN4BTR1.Byte +#define CAN4BTR1_TSEG10 _CAN4BTR1.Bits.TSEG10 +#define CAN4BTR1_TSEG11 _CAN4BTR1.Bits.TSEG11 +#define CAN4BTR1_TSEG12 _CAN4BTR1.Bits.TSEG12 +#define CAN4BTR1_TSEG13 _CAN4BTR1.Bits.TSEG13 +#define CAN4BTR1_TSEG20 _CAN4BTR1.Bits.TSEG20 +#define CAN4BTR1_TSEG21 _CAN4BTR1.Bits.TSEG21 +#define CAN4BTR1_TSEG22 _CAN4BTR1.Bits.TSEG22 +#define CAN4BTR1_SAMP _CAN4BTR1.Bits.SAMP +#define CAN4BTR1_TSEG_10 _CAN4BTR1.MergedBits.grpTSEG_10 +#define CAN4BTR1_TSEG_20 _CAN4BTR1.MergedBits.grpTSEG_20 +#define CAN4BTR1_TSEG CAN4BTR1_TSEG_10 + +#define CAN4BTR1_TSEG10_MASK 1U +#define CAN4BTR1_TSEG11_MASK 2U +#define CAN4BTR1_TSEG12_MASK 4U +#define CAN4BTR1_TSEG13_MASK 8U +#define CAN4BTR1_TSEG20_MASK 16U +#define CAN4BTR1_TSEG21_MASK 32U +#define CAN4BTR1_TSEG22_MASK 64U +#define CAN4BTR1_SAMP_MASK 128U +#define CAN4BTR1_TSEG_10_MASK 15U +#define CAN4BTR1_TSEG_10_BITNUM 0U +#define CAN4BTR1_TSEG_20_MASK 112U +#define CAN4BTR1_TSEG_20_BITNUM 4U + + +/*** CAN4RFLG - MSCAN4 Receiver Flag Register; 0x00000284 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN4RFLGSTR; +extern volatile CAN4RFLGSTR _CAN4RFLG @(REG_BASE + 0x00000284UL); +#define CAN4RFLG _CAN4RFLG.Byte +#define CAN4RFLG_RXF _CAN4RFLG.Bits.RXF +#define CAN4RFLG_OVRIF _CAN4RFLG.Bits.OVRIF +#define CAN4RFLG_TSTAT0 _CAN4RFLG.Bits.TSTAT0 +#define CAN4RFLG_TSTAT1 _CAN4RFLG.Bits.TSTAT1 +#define CAN4RFLG_RSTAT0 _CAN4RFLG.Bits.RSTAT0 +#define CAN4RFLG_RSTAT1 _CAN4RFLG.Bits.RSTAT1 +#define CAN4RFLG_CSCIF _CAN4RFLG.Bits.CSCIF +#define CAN4RFLG_WUPIF _CAN4RFLG.Bits.WUPIF +#define CAN4RFLG_TSTAT _CAN4RFLG.MergedBits.grpTSTAT +#define CAN4RFLG_RSTAT _CAN4RFLG.MergedBits.grpRSTAT + +#define CAN4RFLG_RXF_MASK 1U +#define CAN4RFLG_OVRIF_MASK 2U +#define CAN4RFLG_TSTAT0_MASK 4U +#define CAN4RFLG_TSTAT1_MASK 8U +#define CAN4RFLG_RSTAT0_MASK 16U +#define CAN4RFLG_RSTAT1_MASK 32U +#define CAN4RFLG_CSCIF_MASK 64U +#define CAN4RFLG_WUPIF_MASK 128U +#define CAN4RFLG_TSTAT_MASK 12U +#define CAN4RFLG_TSTAT_BITNUM 2U +#define CAN4RFLG_RSTAT_MASK 48U +#define CAN4RFLG_RSTAT_BITNUM 4U + + +/*** CAN4RIER - MSCAN4 Receiver Interrupt Enable Register; 0x00000285 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN4RIERSTR; +extern volatile CAN4RIERSTR _CAN4RIER @(REG_BASE + 0x00000285UL); +#define CAN4RIER _CAN4RIER.Byte +#define CAN4RIER_RXFIE _CAN4RIER.Bits.RXFIE +#define CAN4RIER_OVRIE _CAN4RIER.Bits.OVRIE +#define CAN4RIER_TSTATE0 _CAN4RIER.Bits.TSTATE0 +#define CAN4RIER_TSTATE1 _CAN4RIER.Bits.TSTATE1 +#define CAN4RIER_RSTATE0 _CAN4RIER.Bits.RSTATE0 +#define CAN4RIER_RSTATE1 _CAN4RIER.Bits.RSTATE1 +#define CAN4RIER_CSCIE _CAN4RIER.Bits.CSCIE +#define CAN4RIER_WUPIE _CAN4RIER.Bits.WUPIE +#define CAN4RIER_TSTATE _CAN4RIER.MergedBits.grpTSTATE +#define CAN4RIER_RSTATE _CAN4RIER.MergedBits.grpRSTATE + +#define CAN4RIER_RXFIE_MASK 1U +#define CAN4RIER_OVRIE_MASK 2U +#define CAN4RIER_TSTATE0_MASK 4U +#define CAN4RIER_TSTATE1_MASK 8U +#define CAN4RIER_RSTATE0_MASK 16U +#define CAN4RIER_RSTATE1_MASK 32U +#define CAN4RIER_CSCIE_MASK 64U +#define CAN4RIER_WUPIE_MASK 128U +#define CAN4RIER_TSTATE_MASK 12U +#define CAN4RIER_TSTATE_BITNUM 2U +#define CAN4RIER_RSTATE_MASK 48U +#define CAN4RIER_RSTATE_BITNUM 4U + + +/*** CAN4TFLG - MSCAN4 Transmitter Flag Register; 0x00000286 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TFLGSTR; +extern volatile CAN4TFLGSTR _CAN4TFLG @(REG_BASE + 0x00000286UL); +#define CAN4TFLG _CAN4TFLG.Byte +#define CAN4TFLG_TXE0 _CAN4TFLG.Bits.TXE0 +#define CAN4TFLG_TXE1 _CAN4TFLG.Bits.TXE1 +#define CAN4TFLG_TXE2 _CAN4TFLG.Bits.TXE2 +#define CAN4TFLG_TXE _CAN4TFLG.MergedBits.grpTXE + +#define CAN4TFLG_TXE0_MASK 1U +#define CAN4TFLG_TXE1_MASK 2U +#define CAN4TFLG_TXE2_MASK 4U +#define CAN4TFLG_TXE_MASK 7U +#define CAN4TFLG_TXE_BITNUM 0U + + +/*** CAN4TIER - MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TIERSTR; +extern volatile CAN4TIERSTR _CAN4TIER @(REG_BASE + 0x00000287UL); +#define CAN4TIER _CAN4TIER.Byte +#define CAN4TIER_TXEIE0 _CAN4TIER.Bits.TXEIE0 +#define CAN4TIER_TXEIE1 _CAN4TIER.Bits.TXEIE1 +#define CAN4TIER_TXEIE2 _CAN4TIER.Bits.TXEIE2 +#define CAN4TIER_TXEIE _CAN4TIER.MergedBits.grpTXEIE + +#define CAN4TIER_TXEIE0_MASK 1U +#define CAN4TIER_TXEIE1_MASK 2U +#define CAN4TIER_TXEIE2_MASK 4U +#define CAN4TIER_TXEIE_MASK 7U +#define CAN4TIER_TXEIE_BITNUM 0U + + +/*** CAN4TARQ - MSCAN 4 Transmitter Message Abort Request; 0x00000288 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TARQSTR; +extern volatile CAN4TARQSTR _CAN4TARQ @(REG_BASE + 0x00000288UL); +#define CAN4TARQ _CAN4TARQ.Byte +#define CAN4TARQ_ABTRQ0 _CAN4TARQ.Bits.ABTRQ0 +#define CAN4TARQ_ABTRQ1 _CAN4TARQ.Bits.ABTRQ1 +#define CAN4TARQ_ABTRQ2 _CAN4TARQ.Bits.ABTRQ2 +#define CAN4TARQ_ABTRQ _CAN4TARQ.MergedBits.grpABTRQ + +#define CAN4TARQ_ABTRQ0_MASK 1U +#define CAN4TARQ_ABTRQ1_MASK 2U +#define CAN4TARQ_ABTRQ2_MASK 4U +#define CAN4TARQ_ABTRQ_MASK 7U +#define CAN4TARQ_ABTRQ_BITNUM 0U + + +/*** CAN4TAAK - MSCAN4 Transmitter Message Abort Control; 0x00000289 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TAAKSTR; +extern volatile CAN4TAAKSTR _CAN4TAAK @(REG_BASE + 0x00000289UL); +#define CAN4TAAK _CAN4TAAK.Byte +#define CAN4TAAK_ABTAK0 _CAN4TAAK.Bits.ABTAK0 +#define CAN4TAAK_ABTAK1 _CAN4TAAK.Bits.ABTAK1 +#define CAN4TAAK_ABTAK2 _CAN4TAAK.Bits.ABTAK2 +#define CAN4TAAK_ABTAK _CAN4TAAK.MergedBits.grpABTAK + +#define CAN4TAAK_ABTAK0_MASK 1U +#define CAN4TAAK_ABTAK1_MASK 2U +#define CAN4TAAK_ABTAK2_MASK 4U +#define CAN4TAAK_ABTAK_MASK 7U +#define CAN4TAAK_ABTAK_BITNUM 0U + + +/*** CAN4TBSEL - MSCAN4 Transmit Buffer Selection; 0x0000028A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TBSELSTR; +extern volatile CAN4TBSELSTR _CAN4TBSEL @(REG_BASE + 0x0000028AUL); +#define CAN4TBSEL _CAN4TBSEL.Byte +#define CAN4TBSEL_TX0 _CAN4TBSEL.Bits.TX0 +#define CAN4TBSEL_TX1 _CAN4TBSEL.Bits.TX1 +#define CAN4TBSEL_TX2 _CAN4TBSEL.Bits.TX2 +#define CAN4TBSEL_TX _CAN4TBSEL.MergedBits.grpTX + +#define CAN4TBSEL_TX0_MASK 1U +#define CAN4TBSEL_TX1_MASK 2U +#define CAN4TBSEL_TX2_MASK 4U +#define CAN4TBSEL_TX_MASK 7U +#define CAN4TBSEL_TX_BITNUM 0U + + +/*** CAN4IDAC - MSCAN4 Identifier Acceptance Control Register; 0x0000028B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN4IDACSTR; +extern volatile CAN4IDACSTR _CAN4IDAC @(REG_BASE + 0x0000028BUL); +#define CAN4IDAC _CAN4IDAC.Byte +#define CAN4IDAC_IDHIT0 _CAN4IDAC.Bits.IDHIT0 +#define CAN4IDAC_IDHIT1 _CAN4IDAC.Bits.IDHIT1 +#define CAN4IDAC_IDHIT2 _CAN4IDAC.Bits.IDHIT2 +#define CAN4IDAC_IDAM0 _CAN4IDAC.Bits.IDAM0 +#define CAN4IDAC_IDAM1 _CAN4IDAC.Bits.IDAM1 +#define CAN4IDAC_IDHIT _CAN4IDAC.MergedBits.grpIDHIT +#define CAN4IDAC_IDAM _CAN4IDAC.MergedBits.grpIDAM + +#define CAN4IDAC_IDHIT0_MASK 1U +#define CAN4IDAC_IDHIT1_MASK 2U +#define CAN4IDAC_IDHIT2_MASK 4U +#define CAN4IDAC_IDAM0_MASK 16U +#define CAN4IDAC_IDAM1_MASK 32U +#define CAN4IDAC_IDHIT_MASK 7U +#define CAN4IDAC_IDHIT_BITNUM 0U +#define CAN4IDAC_IDAM_MASK 48U +#define CAN4IDAC_IDAM_BITNUM 4U + + +/*** CAN4RXERR - MSCAN4 Receive Error Counter Register; 0x0000028E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; +} CAN4RXERRSTR; +extern volatile CAN4RXERRSTR _CAN4RXERR @(REG_BASE + 0x0000028EUL); +#define CAN4RXERR _CAN4RXERR.Byte +#define CAN4RXERR_RXERR0 _CAN4RXERR.Bits.RXERR0 +#define CAN4RXERR_RXERR1 _CAN4RXERR.Bits.RXERR1 +#define CAN4RXERR_RXERR2 _CAN4RXERR.Bits.RXERR2 +#define CAN4RXERR_RXERR3 _CAN4RXERR.Bits.RXERR3 +#define CAN4RXERR_RXERR4 _CAN4RXERR.Bits.RXERR4 +#define CAN4RXERR_RXERR5 _CAN4RXERR.Bits.RXERR5 +#define CAN4RXERR_RXERR6 _CAN4RXERR.Bits.RXERR6 +#define CAN4RXERR_RXERR7 _CAN4RXERR.Bits.RXERR7 + +#define CAN4RXERR_RXERR0_MASK 1U +#define CAN4RXERR_RXERR1_MASK 2U +#define CAN4RXERR_RXERR2_MASK 4U +#define CAN4RXERR_RXERR3_MASK 8U +#define CAN4RXERR_RXERR4_MASK 16U +#define CAN4RXERR_RXERR5_MASK 32U +#define CAN4RXERR_RXERR6_MASK 64U +#define CAN4RXERR_RXERR7_MASK 128U + + +/*** CAN4TXERR - MSCAN4 Transmit Error Counter Register; 0x0000028F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; +} CAN4TXERRSTR; +extern volatile CAN4TXERRSTR _CAN4TXERR @(REG_BASE + 0x0000028FUL); +#define CAN4TXERR _CAN4TXERR.Byte +#define CAN4TXERR_TXERR0 _CAN4TXERR.Bits.TXERR0 +#define CAN4TXERR_TXERR1 _CAN4TXERR.Bits.TXERR1 +#define CAN4TXERR_TXERR2 _CAN4TXERR.Bits.TXERR2 +#define CAN4TXERR_TXERR3 _CAN4TXERR.Bits.TXERR3 +#define CAN4TXERR_TXERR4 _CAN4TXERR.Bits.TXERR4 +#define CAN4TXERR_TXERR5 _CAN4TXERR.Bits.TXERR5 +#define CAN4TXERR_TXERR6 _CAN4TXERR.Bits.TXERR6 +#define CAN4TXERR_TXERR7 _CAN4TXERR.Bits.TXERR7 + +#define CAN4TXERR_TXERR0_MASK 1U +#define CAN4TXERR_TXERR1_MASK 2U +#define CAN4TXERR_TXERR2_MASK 4U +#define CAN4TXERR_TXERR3_MASK 8U +#define CAN4TXERR_TXERR4_MASK 16U +#define CAN4TXERR_TXERR5_MASK 32U +#define CAN4TXERR_TXERR6_MASK 64U +#define CAN4TXERR_TXERR7_MASK 128U + + +/*** CAN4IDAR0 - MSCAN4 Identifier Acceptance Register 0; 0x00000290 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR0STR; +extern volatile CAN4IDAR0STR _CAN4IDAR0 @(REG_BASE + 0x00000290UL); +#define CAN4IDAR0 _CAN4IDAR0.Byte +#define CAN4IDAR0_AC0 _CAN4IDAR0.Bits.AC0 +#define CAN4IDAR0_AC1 _CAN4IDAR0.Bits.AC1 +#define CAN4IDAR0_AC2 _CAN4IDAR0.Bits.AC2 +#define CAN4IDAR0_AC3 _CAN4IDAR0.Bits.AC3 +#define CAN4IDAR0_AC4 _CAN4IDAR0.Bits.AC4 +#define CAN4IDAR0_AC5 _CAN4IDAR0.Bits.AC5 +#define CAN4IDAR0_AC6 _CAN4IDAR0.Bits.AC6 +#define CAN4IDAR0_AC7 _CAN4IDAR0.Bits.AC7 +/* CAN4IDAR_ARR: Access 4 CAN4IDARx registers in an array */ +#define CAN4IDAR_ARR ((volatile byte *) &CAN4IDAR0) + +#define CAN4IDAR0_AC0_MASK 1U +#define CAN4IDAR0_AC1_MASK 2U +#define CAN4IDAR0_AC2_MASK 4U +#define CAN4IDAR0_AC3_MASK 8U +#define CAN4IDAR0_AC4_MASK 16U +#define CAN4IDAR0_AC5_MASK 32U +#define CAN4IDAR0_AC6_MASK 64U +#define CAN4IDAR0_AC7_MASK 128U + + +/*** CAN4IDAR1 - MSCAN4 Identifier Acceptance Register 1; 0x00000291 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR1STR; +extern volatile CAN4IDAR1STR _CAN4IDAR1 @(REG_BASE + 0x00000291UL); +#define CAN4IDAR1 _CAN4IDAR1.Byte +#define CAN4IDAR1_AC0 _CAN4IDAR1.Bits.AC0 +#define CAN4IDAR1_AC1 _CAN4IDAR1.Bits.AC1 +#define CAN4IDAR1_AC2 _CAN4IDAR1.Bits.AC2 +#define CAN4IDAR1_AC3 _CAN4IDAR1.Bits.AC3 +#define CAN4IDAR1_AC4 _CAN4IDAR1.Bits.AC4 +#define CAN4IDAR1_AC5 _CAN4IDAR1.Bits.AC5 +#define CAN4IDAR1_AC6 _CAN4IDAR1.Bits.AC6 +#define CAN4IDAR1_AC7 _CAN4IDAR1.Bits.AC7 + +#define CAN4IDAR1_AC0_MASK 1U +#define CAN4IDAR1_AC1_MASK 2U +#define CAN4IDAR1_AC2_MASK 4U +#define CAN4IDAR1_AC3_MASK 8U +#define CAN4IDAR1_AC4_MASK 16U +#define CAN4IDAR1_AC5_MASK 32U +#define CAN4IDAR1_AC6_MASK 64U +#define CAN4IDAR1_AC7_MASK 128U + + +/*** CAN4IDAR2 - MSCAN4 Identifier Acceptance Register 2; 0x00000292 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR2STR; +extern volatile CAN4IDAR2STR _CAN4IDAR2 @(REG_BASE + 0x00000292UL); +#define CAN4IDAR2 _CAN4IDAR2.Byte +#define CAN4IDAR2_AC0 _CAN4IDAR2.Bits.AC0 +#define CAN4IDAR2_AC1 _CAN4IDAR2.Bits.AC1 +#define CAN4IDAR2_AC2 _CAN4IDAR2.Bits.AC2 +#define CAN4IDAR2_AC3 _CAN4IDAR2.Bits.AC3 +#define CAN4IDAR2_AC4 _CAN4IDAR2.Bits.AC4 +#define CAN4IDAR2_AC5 _CAN4IDAR2.Bits.AC5 +#define CAN4IDAR2_AC6 _CAN4IDAR2.Bits.AC6 +#define CAN4IDAR2_AC7 _CAN4IDAR2.Bits.AC7 + +#define CAN4IDAR2_AC0_MASK 1U +#define CAN4IDAR2_AC1_MASK 2U +#define CAN4IDAR2_AC2_MASK 4U +#define CAN4IDAR2_AC3_MASK 8U +#define CAN4IDAR2_AC4_MASK 16U +#define CAN4IDAR2_AC5_MASK 32U +#define CAN4IDAR2_AC6_MASK 64U +#define CAN4IDAR2_AC7_MASK 128U + + +/*** CAN4IDAR3 - MSCAN4 Identifier Acceptance Register 3; 0x00000293 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR3STR; +extern volatile CAN4IDAR3STR _CAN4IDAR3 @(REG_BASE + 0x00000293UL); +#define CAN4IDAR3 _CAN4IDAR3.Byte +#define CAN4IDAR3_AC0 _CAN4IDAR3.Bits.AC0 +#define CAN4IDAR3_AC1 _CAN4IDAR3.Bits.AC1 +#define CAN4IDAR3_AC2 _CAN4IDAR3.Bits.AC2 +#define CAN4IDAR3_AC3 _CAN4IDAR3.Bits.AC3 +#define CAN4IDAR3_AC4 _CAN4IDAR3.Bits.AC4 +#define CAN4IDAR3_AC5 _CAN4IDAR3.Bits.AC5 +#define CAN4IDAR3_AC6 _CAN4IDAR3.Bits.AC6 +#define CAN4IDAR3_AC7 _CAN4IDAR3.Bits.AC7 + +#define CAN4IDAR3_AC0_MASK 1U +#define CAN4IDAR3_AC1_MASK 2U +#define CAN4IDAR3_AC2_MASK 4U +#define CAN4IDAR3_AC3_MASK 8U +#define CAN4IDAR3_AC4_MASK 16U +#define CAN4IDAR3_AC5_MASK 32U +#define CAN4IDAR3_AC6_MASK 64U +#define CAN4IDAR3_AC7_MASK 128U + + +/*** CAN4IDMR0 - MSCAN4 Identifier Mask Register 0; 0x00000294 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR0STR; +extern volatile CAN4IDMR0STR _CAN4IDMR0 @(REG_BASE + 0x00000294UL); +#define CAN4IDMR0 _CAN4IDMR0.Byte +#define CAN4IDMR0_AM0 _CAN4IDMR0.Bits.AM0 +#define CAN4IDMR0_AM1 _CAN4IDMR0.Bits.AM1 +#define CAN4IDMR0_AM2 _CAN4IDMR0.Bits.AM2 +#define CAN4IDMR0_AM3 _CAN4IDMR0.Bits.AM3 +#define CAN4IDMR0_AM4 _CAN4IDMR0.Bits.AM4 +#define CAN4IDMR0_AM5 _CAN4IDMR0.Bits.AM5 +#define CAN4IDMR0_AM6 _CAN4IDMR0.Bits.AM6 +#define CAN4IDMR0_AM7 _CAN4IDMR0.Bits.AM7 +/* CAN4IDMR_ARR: Access 4 CAN4IDMRx registers in an array */ +#define CAN4IDMR_ARR ((volatile byte *) &CAN4IDMR0) + +#define CAN4IDMR0_AM0_MASK 1U +#define CAN4IDMR0_AM1_MASK 2U +#define CAN4IDMR0_AM2_MASK 4U +#define CAN4IDMR0_AM3_MASK 8U +#define CAN4IDMR0_AM4_MASK 16U +#define CAN4IDMR0_AM5_MASK 32U +#define CAN4IDMR0_AM6_MASK 64U +#define CAN4IDMR0_AM7_MASK 128U + + +/*** CAN4IDMR1 - MSCAN4 Identifier Mask Register 1; 0x00000295 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR1STR; +extern volatile CAN4IDMR1STR _CAN4IDMR1 @(REG_BASE + 0x00000295UL); +#define CAN4IDMR1 _CAN4IDMR1.Byte +#define CAN4IDMR1_AM0 _CAN4IDMR1.Bits.AM0 +#define CAN4IDMR1_AM1 _CAN4IDMR1.Bits.AM1 +#define CAN4IDMR1_AM2 _CAN4IDMR1.Bits.AM2 +#define CAN4IDMR1_AM3 _CAN4IDMR1.Bits.AM3 +#define CAN4IDMR1_AM4 _CAN4IDMR1.Bits.AM4 +#define CAN4IDMR1_AM5 _CAN4IDMR1.Bits.AM5 +#define CAN4IDMR1_AM6 _CAN4IDMR1.Bits.AM6 +#define CAN4IDMR1_AM7 _CAN4IDMR1.Bits.AM7 + +#define CAN4IDMR1_AM0_MASK 1U +#define CAN4IDMR1_AM1_MASK 2U +#define CAN4IDMR1_AM2_MASK 4U +#define CAN4IDMR1_AM3_MASK 8U +#define CAN4IDMR1_AM4_MASK 16U +#define CAN4IDMR1_AM5_MASK 32U +#define CAN4IDMR1_AM6_MASK 64U +#define CAN4IDMR1_AM7_MASK 128U + + +/*** CAN4IDMR2 - MSCAN4 Identifier Mask Register 2; 0x00000296 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR2STR; +extern volatile CAN4IDMR2STR _CAN4IDMR2 @(REG_BASE + 0x00000296UL); +#define CAN4IDMR2 _CAN4IDMR2.Byte +#define CAN4IDMR2_AM0 _CAN4IDMR2.Bits.AM0 +#define CAN4IDMR2_AM1 _CAN4IDMR2.Bits.AM1 +#define CAN4IDMR2_AM2 _CAN4IDMR2.Bits.AM2 +#define CAN4IDMR2_AM3 _CAN4IDMR2.Bits.AM3 +#define CAN4IDMR2_AM4 _CAN4IDMR2.Bits.AM4 +#define CAN4IDMR2_AM5 _CAN4IDMR2.Bits.AM5 +#define CAN4IDMR2_AM6 _CAN4IDMR2.Bits.AM6 +#define CAN4IDMR2_AM7 _CAN4IDMR2.Bits.AM7 + +#define CAN4IDMR2_AM0_MASK 1U +#define CAN4IDMR2_AM1_MASK 2U +#define CAN4IDMR2_AM2_MASK 4U +#define CAN4IDMR2_AM3_MASK 8U +#define CAN4IDMR2_AM4_MASK 16U +#define CAN4IDMR2_AM5_MASK 32U +#define CAN4IDMR2_AM6_MASK 64U +#define CAN4IDMR2_AM7_MASK 128U + + +/*** CAN4IDMR3 - MSCAN4 Identifier Mask Register 3; 0x00000297 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR3STR; +extern volatile CAN4IDMR3STR _CAN4IDMR3 @(REG_BASE + 0x00000297UL); +#define CAN4IDMR3 _CAN4IDMR3.Byte +#define CAN4IDMR3_AM0 _CAN4IDMR3.Bits.AM0 +#define CAN4IDMR3_AM1 _CAN4IDMR3.Bits.AM1 +#define CAN4IDMR3_AM2 _CAN4IDMR3.Bits.AM2 +#define CAN4IDMR3_AM3 _CAN4IDMR3.Bits.AM3 +#define CAN4IDMR3_AM4 _CAN4IDMR3.Bits.AM4 +#define CAN4IDMR3_AM5 _CAN4IDMR3.Bits.AM5 +#define CAN4IDMR3_AM6 _CAN4IDMR3.Bits.AM6 +#define CAN4IDMR3_AM7 _CAN4IDMR3.Bits.AM7 + +#define CAN4IDMR3_AM0_MASK 1U +#define CAN4IDMR3_AM1_MASK 2U +#define CAN4IDMR3_AM2_MASK 4U +#define CAN4IDMR3_AM3_MASK 8U +#define CAN4IDMR3_AM4_MASK 16U +#define CAN4IDMR3_AM5_MASK 32U +#define CAN4IDMR3_AM6_MASK 64U +#define CAN4IDMR3_AM7_MASK 128U + + +/*** CAN4IDAR4 - MSCAN4 Identifier Acceptance Register 4; 0x00000298 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR4STR; +extern volatile CAN4IDAR4STR _CAN4IDAR4 @(REG_BASE + 0x00000298UL); +#define CAN4IDAR4 _CAN4IDAR4.Byte +#define CAN4IDAR4_AC0 _CAN4IDAR4.Bits.AC0 +#define CAN4IDAR4_AC1 _CAN4IDAR4.Bits.AC1 +#define CAN4IDAR4_AC2 _CAN4IDAR4.Bits.AC2 +#define CAN4IDAR4_AC3 _CAN4IDAR4.Bits.AC3 +#define CAN4IDAR4_AC4 _CAN4IDAR4.Bits.AC4 +#define CAN4IDAR4_AC5 _CAN4IDAR4.Bits.AC5 +#define CAN4IDAR4_AC6 _CAN4IDAR4.Bits.AC6 +#define CAN4IDAR4_AC7 _CAN4IDAR4.Bits.AC7 + +#define CAN4IDAR4_AC0_MASK 1U +#define CAN4IDAR4_AC1_MASK 2U +#define CAN4IDAR4_AC2_MASK 4U +#define CAN4IDAR4_AC3_MASK 8U +#define CAN4IDAR4_AC4_MASK 16U +#define CAN4IDAR4_AC5_MASK 32U +#define CAN4IDAR4_AC6_MASK 64U +#define CAN4IDAR4_AC7_MASK 128U + + +/*** CAN4IDAR5 - MSCAN4 Identifier Acceptance Register 5; 0x00000299 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR5STR; +extern volatile CAN4IDAR5STR _CAN4IDAR5 @(REG_BASE + 0x00000299UL); +#define CAN4IDAR5 _CAN4IDAR5.Byte +#define CAN4IDAR5_AC0 _CAN4IDAR5.Bits.AC0 +#define CAN4IDAR5_AC1 _CAN4IDAR5.Bits.AC1 +#define CAN4IDAR5_AC2 _CAN4IDAR5.Bits.AC2 +#define CAN4IDAR5_AC3 _CAN4IDAR5.Bits.AC3 +#define CAN4IDAR5_AC4 _CAN4IDAR5.Bits.AC4 +#define CAN4IDAR5_AC5 _CAN4IDAR5.Bits.AC5 +#define CAN4IDAR5_AC6 _CAN4IDAR5.Bits.AC6 +#define CAN4IDAR5_AC7 _CAN4IDAR5.Bits.AC7 + +#define CAN4IDAR5_AC0_MASK 1U +#define CAN4IDAR5_AC1_MASK 2U +#define CAN4IDAR5_AC2_MASK 4U +#define CAN4IDAR5_AC3_MASK 8U +#define CAN4IDAR5_AC4_MASK 16U +#define CAN4IDAR5_AC5_MASK 32U +#define CAN4IDAR5_AC6_MASK 64U +#define CAN4IDAR5_AC7_MASK 128U + + +/*** CAN4IDAR6 - MSCAN4 Identifier Acceptance Register 6; 0x0000029A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR6STR; +extern volatile CAN4IDAR6STR _CAN4IDAR6 @(REG_BASE + 0x0000029AUL); +#define CAN4IDAR6 _CAN4IDAR6.Byte +#define CAN4IDAR6_AC0 _CAN4IDAR6.Bits.AC0 +#define CAN4IDAR6_AC1 _CAN4IDAR6.Bits.AC1 +#define CAN4IDAR6_AC2 _CAN4IDAR6.Bits.AC2 +#define CAN4IDAR6_AC3 _CAN4IDAR6.Bits.AC3 +#define CAN4IDAR6_AC4 _CAN4IDAR6.Bits.AC4 +#define CAN4IDAR6_AC5 _CAN4IDAR6.Bits.AC5 +#define CAN4IDAR6_AC6 _CAN4IDAR6.Bits.AC6 +#define CAN4IDAR6_AC7 _CAN4IDAR6.Bits.AC7 + +#define CAN4IDAR6_AC0_MASK 1U +#define CAN4IDAR6_AC1_MASK 2U +#define CAN4IDAR6_AC2_MASK 4U +#define CAN4IDAR6_AC3_MASK 8U +#define CAN4IDAR6_AC4_MASK 16U +#define CAN4IDAR6_AC5_MASK 32U +#define CAN4IDAR6_AC6_MASK 64U +#define CAN4IDAR6_AC7_MASK 128U + + +/*** CAN4IDAR7 - MSCAN4 Identifier Acceptance Register 7; 0x0000029B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR7STR; +extern volatile CAN4IDAR7STR _CAN4IDAR7 @(REG_BASE + 0x0000029BUL); +#define CAN4IDAR7 _CAN4IDAR7.Byte +#define CAN4IDAR7_AC0 _CAN4IDAR7.Bits.AC0 +#define CAN4IDAR7_AC1 _CAN4IDAR7.Bits.AC1 +#define CAN4IDAR7_AC2 _CAN4IDAR7.Bits.AC2 +#define CAN4IDAR7_AC3 _CAN4IDAR7.Bits.AC3 +#define CAN4IDAR7_AC4 _CAN4IDAR7.Bits.AC4 +#define CAN4IDAR7_AC5 _CAN4IDAR7.Bits.AC5 +#define CAN4IDAR7_AC6 _CAN4IDAR7.Bits.AC6 +#define CAN4IDAR7_AC7 _CAN4IDAR7.Bits.AC7 + +#define CAN4IDAR7_AC0_MASK 1U +#define CAN4IDAR7_AC1_MASK 2U +#define CAN4IDAR7_AC2_MASK 4U +#define CAN4IDAR7_AC3_MASK 8U +#define CAN4IDAR7_AC4_MASK 16U +#define CAN4IDAR7_AC5_MASK 32U +#define CAN4IDAR7_AC6_MASK 64U +#define CAN4IDAR7_AC7_MASK 128U + + +/*** CAN4IDMR4 - MSCAN4 Identifier Mask Register 4; 0x0000029C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR4STR; +extern volatile CAN4IDMR4STR _CAN4IDMR4 @(REG_BASE + 0x0000029CUL); +#define CAN4IDMR4 _CAN4IDMR4.Byte +#define CAN4IDMR4_AM0 _CAN4IDMR4.Bits.AM0 +#define CAN4IDMR4_AM1 _CAN4IDMR4.Bits.AM1 +#define CAN4IDMR4_AM2 _CAN4IDMR4.Bits.AM2 +#define CAN4IDMR4_AM3 _CAN4IDMR4.Bits.AM3 +#define CAN4IDMR4_AM4 _CAN4IDMR4.Bits.AM4 +#define CAN4IDMR4_AM5 _CAN4IDMR4.Bits.AM5 +#define CAN4IDMR4_AM6 _CAN4IDMR4.Bits.AM6 +#define CAN4IDMR4_AM7 _CAN4IDMR4.Bits.AM7 + +#define CAN4IDMR4_AM0_MASK 1U +#define CAN4IDMR4_AM1_MASK 2U +#define CAN4IDMR4_AM2_MASK 4U +#define CAN4IDMR4_AM3_MASK 8U +#define CAN4IDMR4_AM4_MASK 16U +#define CAN4IDMR4_AM5_MASK 32U +#define CAN4IDMR4_AM6_MASK 64U +#define CAN4IDMR4_AM7_MASK 128U + + +/*** CAN4IDMR5 - MSCAN4 Identifier Mask Register 5; 0x0000029D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR5STR; +extern volatile CAN4IDMR5STR _CAN4IDMR5 @(REG_BASE + 0x0000029DUL); +#define CAN4IDMR5 _CAN4IDMR5.Byte +#define CAN4IDMR5_AM0 _CAN4IDMR5.Bits.AM0 +#define CAN4IDMR5_AM1 _CAN4IDMR5.Bits.AM1 +#define CAN4IDMR5_AM2 _CAN4IDMR5.Bits.AM2 +#define CAN4IDMR5_AM3 _CAN4IDMR5.Bits.AM3 +#define CAN4IDMR5_AM4 _CAN4IDMR5.Bits.AM4 +#define CAN4IDMR5_AM5 _CAN4IDMR5.Bits.AM5 +#define CAN4IDMR5_AM6 _CAN4IDMR5.Bits.AM6 +#define CAN4IDMR5_AM7 _CAN4IDMR5.Bits.AM7 + +#define CAN4IDMR5_AM0_MASK 1U +#define CAN4IDMR5_AM1_MASK 2U +#define CAN4IDMR5_AM2_MASK 4U +#define CAN4IDMR5_AM3_MASK 8U +#define CAN4IDMR5_AM4_MASK 16U +#define CAN4IDMR5_AM5_MASK 32U +#define CAN4IDMR5_AM6_MASK 64U +#define CAN4IDMR5_AM7_MASK 128U + + +/*** CAN4IDMR6 - MSCAN4 Identifier Mask Register 6; 0x0000029E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR6STR; +extern volatile CAN4IDMR6STR _CAN4IDMR6 @(REG_BASE + 0x0000029EUL); +#define CAN4IDMR6 _CAN4IDMR6.Byte +#define CAN4IDMR6_AM0 _CAN4IDMR6.Bits.AM0 +#define CAN4IDMR6_AM1 _CAN4IDMR6.Bits.AM1 +#define CAN4IDMR6_AM2 _CAN4IDMR6.Bits.AM2 +#define CAN4IDMR6_AM3 _CAN4IDMR6.Bits.AM3 +#define CAN4IDMR6_AM4 _CAN4IDMR6.Bits.AM4 +#define CAN4IDMR6_AM5 _CAN4IDMR6.Bits.AM5 +#define CAN4IDMR6_AM6 _CAN4IDMR6.Bits.AM6 +#define CAN4IDMR6_AM7 _CAN4IDMR6.Bits.AM7 + +#define CAN4IDMR6_AM0_MASK 1U +#define CAN4IDMR6_AM1_MASK 2U +#define CAN4IDMR6_AM2_MASK 4U +#define CAN4IDMR6_AM3_MASK 8U +#define CAN4IDMR6_AM4_MASK 16U +#define CAN4IDMR6_AM5_MASK 32U +#define CAN4IDMR6_AM6_MASK 64U +#define CAN4IDMR6_AM7_MASK 128U + + +/*** CAN4IDMR7 - MSCAN4 Identifier Mask Register 7; 0x0000029F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR7STR; +extern volatile CAN4IDMR7STR _CAN4IDMR7 @(REG_BASE + 0x0000029FUL); +#define CAN4IDMR7 _CAN4IDMR7.Byte +#define CAN4IDMR7_AM0 _CAN4IDMR7.Bits.AM0 +#define CAN4IDMR7_AM1 _CAN4IDMR7.Bits.AM1 +#define CAN4IDMR7_AM2 _CAN4IDMR7.Bits.AM2 +#define CAN4IDMR7_AM3 _CAN4IDMR7.Bits.AM3 +#define CAN4IDMR7_AM4 _CAN4IDMR7.Bits.AM4 +#define CAN4IDMR7_AM5 _CAN4IDMR7.Bits.AM5 +#define CAN4IDMR7_AM6 _CAN4IDMR7.Bits.AM6 +#define CAN4IDMR7_AM7 _CAN4IDMR7.Bits.AM7 + +#define CAN4IDMR7_AM0_MASK 1U +#define CAN4IDMR7_AM1_MASK 2U +#define CAN4IDMR7_AM2_MASK 4U +#define CAN4IDMR7_AM3_MASK 8U +#define CAN4IDMR7_AM4_MASK 16U +#define CAN4IDMR7_AM5_MASK 32U +#define CAN4IDMR7_AM6_MASK 64U +#define CAN4IDMR7_AM7_MASK 128U + + +/*** CAN4RXIDR0 - MSCAN4 Receive Identifier Register 0; 0x000002A0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; +} CAN4RXIDR0STR; +extern volatile CAN4RXIDR0STR _CAN4RXIDR0 @(REG_BASE + 0x000002A0UL); +#define CAN4RXIDR0 _CAN4RXIDR0.Byte +#define CAN4RXIDR0_ID21 _CAN4RXIDR0.Bits.ID21 +#define CAN4RXIDR0_ID22 _CAN4RXIDR0.Bits.ID22 +#define CAN4RXIDR0_ID23 _CAN4RXIDR0.Bits.ID23 +#define CAN4RXIDR0_ID24 _CAN4RXIDR0.Bits.ID24 +#define CAN4RXIDR0_ID25 _CAN4RXIDR0.Bits.ID25 +#define CAN4RXIDR0_ID26 _CAN4RXIDR0.Bits.ID26 +#define CAN4RXIDR0_ID27 _CAN4RXIDR0.Bits.ID27 +#define CAN4RXIDR0_ID28 _CAN4RXIDR0.Bits.ID28 +/* CAN4RXIDR_ARR: Access 4 CAN4RXIDRx registers in an array */ +#define CAN4RXIDR_ARR ((volatile byte *) &CAN4RXIDR0) + +#define CAN4RXIDR0_ID21_MASK 1U +#define CAN4RXIDR0_ID22_MASK 2U +#define CAN4RXIDR0_ID23_MASK 4U +#define CAN4RXIDR0_ID24_MASK 8U +#define CAN4RXIDR0_ID25_MASK 16U +#define CAN4RXIDR0_ID26_MASK 32U +#define CAN4RXIDR0_ID27_MASK 64U +#define CAN4RXIDR0_ID28_MASK 128U + + +/*** CAN4RXIDR1 - MSCAN4 Receive Identifier Register 1; 0x000002A1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN4RXIDR1STR; +extern volatile CAN4RXIDR1STR _CAN4RXIDR1 @(REG_BASE + 0x000002A1UL); +#define CAN4RXIDR1 _CAN4RXIDR1.Byte +#define CAN4RXIDR1_ID15 _CAN4RXIDR1.Bits.ID15 +#define CAN4RXIDR1_ID16 _CAN4RXIDR1.Bits.ID16 +#define CAN4RXIDR1_ID17 _CAN4RXIDR1.Bits.ID17 +#define CAN4RXIDR1_IDE _CAN4RXIDR1.Bits.IDE +#define CAN4RXIDR1_SRR _CAN4RXIDR1.Bits.SRR +#define CAN4RXIDR1_ID18 _CAN4RXIDR1.Bits.ID18 +#define CAN4RXIDR1_ID19 _CAN4RXIDR1.Bits.ID19 +#define CAN4RXIDR1_ID20 _CAN4RXIDR1.Bits.ID20 +#define CAN4RXIDR1_ID_15 _CAN4RXIDR1.MergedBits.grpID_15 +#define CAN4RXIDR1_ID_18 _CAN4RXIDR1.MergedBits.grpID_18 +#define CAN4RXIDR1_ID CAN4RXIDR1_ID_15 + +#define CAN4RXIDR1_ID15_MASK 1U +#define CAN4RXIDR1_ID16_MASK 2U +#define CAN4RXIDR1_ID17_MASK 4U +#define CAN4RXIDR1_IDE_MASK 8U +#define CAN4RXIDR1_SRR_MASK 16U +#define CAN4RXIDR1_ID18_MASK 32U +#define CAN4RXIDR1_ID19_MASK 64U +#define CAN4RXIDR1_ID20_MASK 128U +#define CAN4RXIDR1_ID_15_MASK 7U +#define CAN4RXIDR1_ID_15_BITNUM 0U +#define CAN4RXIDR1_ID_18_MASK 224U +#define CAN4RXIDR1_ID_18_BITNUM 5U + + +/*** CAN4RXIDR2 - MSCAN4 Receive Identifier Register 2; 0x000002A2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; +} CAN4RXIDR2STR; +extern volatile CAN4RXIDR2STR _CAN4RXIDR2 @(REG_BASE + 0x000002A2UL); +#define CAN4RXIDR2 _CAN4RXIDR2.Byte +#define CAN4RXIDR2_ID7 _CAN4RXIDR2.Bits.ID7 +#define CAN4RXIDR2_ID8 _CAN4RXIDR2.Bits.ID8 +#define CAN4RXIDR2_ID9 _CAN4RXIDR2.Bits.ID9 +#define CAN4RXIDR2_ID10 _CAN4RXIDR2.Bits.ID10 +#define CAN4RXIDR2_ID11 _CAN4RXIDR2.Bits.ID11 +#define CAN4RXIDR2_ID12 _CAN4RXIDR2.Bits.ID12 +#define CAN4RXIDR2_ID13 _CAN4RXIDR2.Bits.ID13 +#define CAN4RXIDR2_ID14 _CAN4RXIDR2.Bits.ID14 + +#define CAN4RXIDR2_ID7_MASK 1U +#define CAN4RXIDR2_ID8_MASK 2U +#define CAN4RXIDR2_ID9_MASK 4U +#define CAN4RXIDR2_ID10_MASK 8U +#define CAN4RXIDR2_ID11_MASK 16U +#define CAN4RXIDR2_ID12_MASK 32U +#define CAN4RXIDR2_ID13_MASK 64U +#define CAN4RXIDR2_ID14_MASK 128U + + +/*** CAN4RXIDR3 - MSCAN4 Receive Identifier Register 3; 0x000002A3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN4RXIDR3STR; +extern volatile CAN4RXIDR3STR _CAN4RXIDR3 @(REG_BASE + 0x000002A3UL); +#define CAN4RXIDR3 _CAN4RXIDR3.Byte +#define CAN4RXIDR3_RTR _CAN4RXIDR3.Bits.RTR +#define CAN4RXIDR3_ID0 _CAN4RXIDR3.Bits.ID0 +#define CAN4RXIDR3_ID1 _CAN4RXIDR3.Bits.ID1 +#define CAN4RXIDR3_ID2 _CAN4RXIDR3.Bits.ID2 +#define CAN4RXIDR3_ID3 _CAN4RXIDR3.Bits.ID3 +#define CAN4RXIDR3_ID4 _CAN4RXIDR3.Bits.ID4 +#define CAN4RXIDR3_ID5 _CAN4RXIDR3.Bits.ID5 +#define CAN4RXIDR3_ID6 _CAN4RXIDR3.Bits.ID6 +#define CAN4RXIDR3_ID _CAN4RXIDR3.MergedBits.grpID + +#define CAN4RXIDR3_RTR_MASK 1U +#define CAN4RXIDR3_ID0_MASK 2U +#define CAN4RXIDR3_ID1_MASK 4U +#define CAN4RXIDR3_ID2_MASK 8U +#define CAN4RXIDR3_ID3_MASK 16U +#define CAN4RXIDR3_ID4_MASK 32U +#define CAN4RXIDR3_ID5_MASK 64U +#define CAN4RXIDR3_ID6_MASK 128U +#define CAN4RXIDR3_ID_MASK 254U +#define CAN4RXIDR3_ID_BITNUM 1U + + +/*** CAN4RXDSR0 - MSCAN4 Receive Data Segment Register 0; 0x000002A4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR0STR; +extern volatile CAN4RXDSR0STR _CAN4RXDSR0 @(REG_BASE + 0x000002A4UL); +#define CAN4RXDSR0 _CAN4RXDSR0.Byte +#define CAN4RXDSR0_DB0 _CAN4RXDSR0.Bits.DB0 +#define CAN4RXDSR0_DB1 _CAN4RXDSR0.Bits.DB1 +#define CAN4RXDSR0_DB2 _CAN4RXDSR0.Bits.DB2 +#define CAN4RXDSR0_DB3 _CAN4RXDSR0.Bits.DB3 +#define CAN4RXDSR0_DB4 _CAN4RXDSR0.Bits.DB4 +#define CAN4RXDSR0_DB5 _CAN4RXDSR0.Bits.DB5 +#define CAN4RXDSR0_DB6 _CAN4RXDSR0.Bits.DB6 +#define CAN4RXDSR0_DB7 _CAN4RXDSR0.Bits.DB7 +/* CAN4RXDSR_ARR: Access 8 CAN4RXDSRx registers in an array */ +#define CAN4RXDSR_ARR ((volatile byte *) &CAN4RXDSR0) + +#define CAN4RXDSR0_DB0_MASK 1U +#define CAN4RXDSR0_DB1_MASK 2U +#define CAN4RXDSR0_DB2_MASK 4U +#define CAN4RXDSR0_DB3_MASK 8U +#define CAN4RXDSR0_DB4_MASK 16U +#define CAN4RXDSR0_DB5_MASK 32U +#define CAN4RXDSR0_DB6_MASK 64U +#define CAN4RXDSR0_DB7_MASK 128U + + +/*** CAN4RXDSR1 - MSCAN4 Receive Data Segment Register 1; 0x000002A5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR1STR; +extern volatile CAN4RXDSR1STR _CAN4RXDSR1 @(REG_BASE + 0x000002A5UL); +#define CAN4RXDSR1 _CAN4RXDSR1.Byte +#define CAN4RXDSR1_DB0 _CAN4RXDSR1.Bits.DB0 +#define CAN4RXDSR1_DB1 _CAN4RXDSR1.Bits.DB1 +#define CAN4RXDSR1_DB2 _CAN4RXDSR1.Bits.DB2 +#define CAN4RXDSR1_DB3 _CAN4RXDSR1.Bits.DB3 +#define CAN4RXDSR1_DB4 _CAN4RXDSR1.Bits.DB4 +#define CAN4RXDSR1_DB5 _CAN4RXDSR1.Bits.DB5 +#define CAN4RXDSR1_DB6 _CAN4RXDSR1.Bits.DB6 +#define CAN4RXDSR1_DB7 _CAN4RXDSR1.Bits.DB7 + +#define CAN4RXDSR1_DB0_MASK 1U +#define CAN4RXDSR1_DB1_MASK 2U +#define CAN4RXDSR1_DB2_MASK 4U +#define CAN4RXDSR1_DB3_MASK 8U +#define CAN4RXDSR1_DB4_MASK 16U +#define CAN4RXDSR1_DB5_MASK 32U +#define CAN4RXDSR1_DB6_MASK 64U +#define CAN4RXDSR1_DB7_MASK 128U + + +/*** CAN4RXDSR2 - MSCAN4 Receive Data Segment Register 2; 0x000002A6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR2STR; +extern volatile CAN4RXDSR2STR _CAN4RXDSR2 @(REG_BASE + 0x000002A6UL); +#define CAN4RXDSR2 _CAN4RXDSR2.Byte +#define CAN4RXDSR2_DB0 _CAN4RXDSR2.Bits.DB0 +#define CAN4RXDSR2_DB1 _CAN4RXDSR2.Bits.DB1 +#define CAN4RXDSR2_DB2 _CAN4RXDSR2.Bits.DB2 +#define CAN4RXDSR2_DB3 _CAN4RXDSR2.Bits.DB3 +#define CAN4RXDSR2_DB4 _CAN4RXDSR2.Bits.DB4 +#define CAN4RXDSR2_DB5 _CAN4RXDSR2.Bits.DB5 +#define CAN4RXDSR2_DB6 _CAN4RXDSR2.Bits.DB6 +#define CAN4RXDSR2_DB7 _CAN4RXDSR2.Bits.DB7 + +#define CAN4RXDSR2_DB0_MASK 1U +#define CAN4RXDSR2_DB1_MASK 2U +#define CAN4RXDSR2_DB2_MASK 4U +#define CAN4RXDSR2_DB3_MASK 8U +#define CAN4RXDSR2_DB4_MASK 16U +#define CAN4RXDSR2_DB5_MASK 32U +#define CAN4RXDSR2_DB6_MASK 64U +#define CAN4RXDSR2_DB7_MASK 128U + + +/*** CAN4RXDSR3 - MSCAN4 Receive Data Segment Register 3; 0x000002A7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR3STR; +extern volatile CAN4RXDSR3STR _CAN4RXDSR3 @(REG_BASE + 0x000002A7UL); +#define CAN4RXDSR3 _CAN4RXDSR3.Byte +#define CAN4RXDSR3_DB0 _CAN4RXDSR3.Bits.DB0 +#define CAN4RXDSR3_DB1 _CAN4RXDSR3.Bits.DB1 +#define CAN4RXDSR3_DB2 _CAN4RXDSR3.Bits.DB2 +#define CAN4RXDSR3_DB3 _CAN4RXDSR3.Bits.DB3 +#define CAN4RXDSR3_DB4 _CAN4RXDSR3.Bits.DB4 +#define CAN4RXDSR3_DB5 _CAN4RXDSR3.Bits.DB5 +#define CAN4RXDSR3_DB6 _CAN4RXDSR3.Bits.DB6 +#define CAN4RXDSR3_DB7 _CAN4RXDSR3.Bits.DB7 + +#define CAN4RXDSR3_DB0_MASK 1U +#define CAN4RXDSR3_DB1_MASK 2U +#define CAN4RXDSR3_DB2_MASK 4U +#define CAN4RXDSR3_DB3_MASK 8U +#define CAN4RXDSR3_DB4_MASK 16U +#define CAN4RXDSR3_DB5_MASK 32U +#define CAN4RXDSR3_DB6_MASK 64U +#define CAN4RXDSR3_DB7_MASK 128U + + +/*** CAN4RXDSR4 - MSCAN4 Receive Data Segment Register 4; 0x000002A8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR4STR; +extern volatile CAN4RXDSR4STR _CAN4RXDSR4 @(REG_BASE + 0x000002A8UL); +#define CAN4RXDSR4 _CAN4RXDSR4.Byte +#define CAN4RXDSR4_DB0 _CAN4RXDSR4.Bits.DB0 +#define CAN4RXDSR4_DB1 _CAN4RXDSR4.Bits.DB1 +#define CAN4RXDSR4_DB2 _CAN4RXDSR4.Bits.DB2 +#define CAN4RXDSR4_DB3 _CAN4RXDSR4.Bits.DB3 +#define CAN4RXDSR4_DB4 _CAN4RXDSR4.Bits.DB4 +#define CAN4RXDSR4_DB5 _CAN4RXDSR4.Bits.DB5 +#define CAN4RXDSR4_DB6 _CAN4RXDSR4.Bits.DB6 +#define CAN4RXDSR4_DB7 _CAN4RXDSR4.Bits.DB7 + +#define CAN4RXDSR4_DB0_MASK 1U +#define CAN4RXDSR4_DB1_MASK 2U +#define CAN4RXDSR4_DB2_MASK 4U +#define CAN4RXDSR4_DB3_MASK 8U +#define CAN4RXDSR4_DB4_MASK 16U +#define CAN4RXDSR4_DB5_MASK 32U +#define CAN4RXDSR4_DB6_MASK 64U +#define CAN4RXDSR4_DB7_MASK 128U + + +/*** CAN4RXDSR5 - MSCAN4 Receive Data Segment Register 5; 0x000002A9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR5STR; +extern volatile CAN4RXDSR5STR _CAN4RXDSR5 @(REG_BASE + 0x000002A9UL); +#define CAN4RXDSR5 _CAN4RXDSR5.Byte +#define CAN4RXDSR5_DB0 _CAN4RXDSR5.Bits.DB0 +#define CAN4RXDSR5_DB1 _CAN4RXDSR5.Bits.DB1 +#define CAN4RXDSR5_DB2 _CAN4RXDSR5.Bits.DB2 +#define CAN4RXDSR5_DB3 _CAN4RXDSR5.Bits.DB3 +#define CAN4RXDSR5_DB4 _CAN4RXDSR5.Bits.DB4 +#define CAN4RXDSR5_DB5 _CAN4RXDSR5.Bits.DB5 +#define CAN4RXDSR5_DB6 _CAN4RXDSR5.Bits.DB6 +#define CAN4RXDSR5_DB7 _CAN4RXDSR5.Bits.DB7 + +#define CAN4RXDSR5_DB0_MASK 1U +#define CAN4RXDSR5_DB1_MASK 2U +#define CAN4RXDSR5_DB2_MASK 4U +#define CAN4RXDSR5_DB3_MASK 8U +#define CAN4RXDSR5_DB4_MASK 16U +#define CAN4RXDSR5_DB5_MASK 32U +#define CAN4RXDSR5_DB6_MASK 64U +#define CAN4RXDSR5_DB7_MASK 128U + + +/*** CAN4RXDSR6 - MSCAN4 Receive Data Segment Register 6; 0x000002AA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR6STR; +extern volatile CAN4RXDSR6STR _CAN4RXDSR6 @(REG_BASE + 0x000002AAUL); +#define CAN4RXDSR6 _CAN4RXDSR6.Byte +#define CAN4RXDSR6_DB0 _CAN4RXDSR6.Bits.DB0 +#define CAN4RXDSR6_DB1 _CAN4RXDSR6.Bits.DB1 +#define CAN4RXDSR6_DB2 _CAN4RXDSR6.Bits.DB2 +#define CAN4RXDSR6_DB3 _CAN4RXDSR6.Bits.DB3 +#define CAN4RXDSR6_DB4 _CAN4RXDSR6.Bits.DB4 +#define CAN4RXDSR6_DB5 _CAN4RXDSR6.Bits.DB5 +#define CAN4RXDSR6_DB6 _CAN4RXDSR6.Bits.DB6 +#define CAN4RXDSR6_DB7 _CAN4RXDSR6.Bits.DB7 + +#define CAN4RXDSR6_DB0_MASK 1U +#define CAN4RXDSR6_DB1_MASK 2U +#define CAN4RXDSR6_DB2_MASK 4U +#define CAN4RXDSR6_DB3_MASK 8U +#define CAN4RXDSR6_DB4_MASK 16U +#define CAN4RXDSR6_DB5_MASK 32U +#define CAN4RXDSR6_DB6_MASK 64U +#define CAN4RXDSR6_DB7_MASK 128U + + +/*** CAN4RXDSR7 - MSCAN4 Receive Data Segment Register 7; 0x000002AB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR7STR; +extern volatile CAN4RXDSR7STR _CAN4RXDSR7 @(REG_BASE + 0x000002ABUL); +#define CAN4RXDSR7 _CAN4RXDSR7.Byte +#define CAN4RXDSR7_DB0 _CAN4RXDSR7.Bits.DB0 +#define CAN4RXDSR7_DB1 _CAN4RXDSR7.Bits.DB1 +#define CAN4RXDSR7_DB2 _CAN4RXDSR7.Bits.DB2 +#define CAN4RXDSR7_DB3 _CAN4RXDSR7.Bits.DB3 +#define CAN4RXDSR7_DB4 _CAN4RXDSR7.Bits.DB4 +#define CAN4RXDSR7_DB5 _CAN4RXDSR7.Bits.DB5 +#define CAN4RXDSR7_DB6 _CAN4RXDSR7.Bits.DB6 +#define CAN4RXDSR7_DB7 _CAN4RXDSR7.Bits.DB7 + +#define CAN4RXDSR7_DB0_MASK 1U +#define CAN4RXDSR7_DB1_MASK 2U +#define CAN4RXDSR7_DB2_MASK 4U +#define CAN4RXDSR7_DB3_MASK 8U +#define CAN4RXDSR7_DB4_MASK 16U +#define CAN4RXDSR7_DB5_MASK 32U +#define CAN4RXDSR7_DB6_MASK 64U +#define CAN4RXDSR7_DB7_MASK 128U + + +/*** CAN4RXDLR - MSCAN4 Receive Data Length Register; 0x000002AC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4RXDLRSTR; +extern volatile CAN4RXDLRSTR _CAN4RXDLR @(REG_BASE + 0x000002ACUL); +#define CAN4RXDLR _CAN4RXDLR.Byte +#define CAN4RXDLR_DLC0 _CAN4RXDLR.Bits.DLC0 +#define CAN4RXDLR_DLC1 _CAN4RXDLR.Bits.DLC1 +#define CAN4RXDLR_DLC2 _CAN4RXDLR.Bits.DLC2 +#define CAN4RXDLR_DLC3 _CAN4RXDLR.Bits.DLC3 +#define CAN4RXDLR_DLC _CAN4RXDLR.MergedBits.grpDLC + +#define CAN4RXDLR_DLC0_MASK 1U +#define CAN4RXDLR_DLC1_MASK 2U +#define CAN4RXDLR_DLC2_MASK 4U +#define CAN4RXDLR_DLC3_MASK 8U +#define CAN4RXDLR_DLC_MASK 15U +#define CAN4RXDLR_DLC_BITNUM 0U + + +/*** CAN4RXTSR - MSCAN 4 Receive Time Stamp Register; 0x000002AE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** CAN4RXTSRH - MSCAN 4 Receive Time Stamp Register High; 0x000002AE ***/ + union { + byte Byte; + struct { + byte TSR8 :1; /* Time Stamp Bit 8 */ + byte TSR9 :1; /* Time Stamp Bit 9 */ + byte TSR10 :1; /* Time Stamp Bit 10 */ + byte TSR11 :1; /* Time Stamp Bit 11 */ + byte TSR12 :1; /* Time Stamp Bit 12 */ + byte TSR13 :1; /* Time Stamp Bit 13 */ + byte TSR14 :1; /* Time Stamp Bit 14 */ + byte TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; + } CAN4RXTSRHSTR; + #define CAN4RXTSRH _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Byte + #define CAN4RXTSRH_TSR8 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR8 + #define CAN4RXTSRH_TSR9 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR9 + #define CAN4RXTSRH_TSR10 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR10 + #define CAN4RXTSRH_TSR11 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR11 + #define CAN4RXTSRH_TSR12 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR12 + #define CAN4RXTSRH_TSR13 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR13 + #define CAN4RXTSRH_TSR14 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR14 + #define CAN4RXTSRH_TSR15 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR15 + + #define CAN4RXTSRH_TSR8_MASK 1U + #define CAN4RXTSRH_TSR9_MASK 2U + #define CAN4RXTSRH_TSR10_MASK 4U + #define CAN4RXTSRH_TSR11_MASK 8U + #define CAN4RXTSRH_TSR12_MASK 16U + #define CAN4RXTSRH_TSR13_MASK 32U + #define CAN4RXTSRH_TSR14_MASK 64U + #define CAN4RXTSRH_TSR15_MASK 128U + + + /*** CAN4RXTSRL - MSCAN 4 Receive Time Stamp Register Low; 0x000002AF ***/ + union { + byte Byte; + struct { + byte TSR0 :1; /* Time Stamp Bit 0 */ + byte TSR1 :1; /* Time Stamp Bit 1 */ + byte TSR2 :1; /* Time Stamp Bit 2 */ + byte TSR3 :1; /* Time Stamp Bit 3 */ + byte TSR4 :1; /* Time Stamp Bit 4 */ + byte TSR5 :1; /* Time Stamp Bit 5 */ + byte TSR6 :1; /* Time Stamp Bit 6 */ + byte TSR7 :1; /* Time Stamp Bit 7 */ + } Bits; + } CAN4RXTSRLSTR; + #define CAN4RXTSRL _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Byte + #define CAN4RXTSRL_TSR0 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR0 + #define CAN4RXTSRL_TSR1 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR1 + #define CAN4RXTSRL_TSR2 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR2 + #define CAN4RXTSRL_TSR3 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR3 + #define CAN4RXTSRL_TSR4 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR4 + #define CAN4RXTSRL_TSR5 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR5 + #define CAN4RXTSRL_TSR6 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR6 + #define CAN4RXTSRL_TSR7 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR7 + + #define CAN4RXTSRL_TSR0_MASK 1U + #define CAN4RXTSRL_TSR1_MASK 2U + #define CAN4RXTSRL_TSR2_MASK 4U + #define CAN4RXTSRL_TSR3_MASK 8U + #define CAN4RXTSRL_TSR4_MASK 16U + #define CAN4RXTSRL_TSR5_MASK 32U + #define CAN4RXTSRL_TSR6_MASK 64U + #define CAN4RXTSRL_TSR7_MASK 128U + + } Overlap_STR; + + struct { + word TSR0 :1; /* Time Stamp Bit 0 */ + word TSR1 :1; /* Time Stamp Bit 1 */ + word TSR2 :1; /* Time Stamp Bit 2 */ + word TSR3 :1; /* Time Stamp Bit 3 */ + word TSR4 :1; /* Time Stamp Bit 4 */ + word TSR5 :1; /* Time Stamp Bit 5 */ + word TSR6 :1; /* Time Stamp Bit 6 */ + word TSR7 :1; /* Time Stamp Bit 7 */ + word TSR8 :1; /* Time Stamp Bit 8 */ + word TSR9 :1; /* Time Stamp Bit 9 */ + word TSR10 :1; /* Time Stamp Bit 10 */ + word TSR11 :1; /* Time Stamp Bit 11 */ + word TSR12 :1; /* Time Stamp Bit 12 */ + word TSR13 :1; /* Time Stamp Bit 13 */ + word TSR14 :1; /* Time Stamp Bit 14 */ + word TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; +} CAN4RXTSRSTR; +extern volatile CAN4RXTSRSTR _CAN4RXTSR @(REG_BASE + 0x000002AEUL); +#define CAN4RXTSR _CAN4RXTSR.Word +#define CAN4RXTSR_TSR0 _CAN4RXTSR.Bits.TSR0 +#define CAN4RXTSR_TSR1 _CAN4RXTSR.Bits.TSR1 +#define CAN4RXTSR_TSR2 _CAN4RXTSR.Bits.TSR2 +#define CAN4RXTSR_TSR3 _CAN4RXTSR.Bits.TSR3 +#define CAN4RXTSR_TSR4 _CAN4RXTSR.Bits.TSR4 +#define CAN4RXTSR_TSR5 _CAN4RXTSR.Bits.TSR5 +#define CAN4RXTSR_TSR6 _CAN4RXTSR.Bits.TSR6 +#define CAN4RXTSR_TSR7 _CAN4RXTSR.Bits.TSR7 +#define CAN4RXTSR_TSR8 _CAN4RXTSR.Bits.TSR8 +#define CAN4RXTSR_TSR9 _CAN4RXTSR.Bits.TSR9 +#define CAN4RXTSR_TSR10 _CAN4RXTSR.Bits.TSR10 +#define CAN4RXTSR_TSR11 _CAN4RXTSR.Bits.TSR11 +#define CAN4RXTSR_TSR12 _CAN4RXTSR.Bits.TSR12 +#define CAN4RXTSR_TSR13 _CAN4RXTSR.Bits.TSR13 +#define CAN4RXTSR_TSR14 _CAN4RXTSR.Bits.TSR14 +#define CAN4RXTSR_TSR15 _CAN4RXTSR.Bits.TSR15 + +#define CAN4RXTSR_TSR0_MASK 1U +#define CAN4RXTSR_TSR1_MASK 2U +#define CAN4RXTSR_TSR2_MASK 4U +#define CAN4RXTSR_TSR3_MASK 8U +#define CAN4RXTSR_TSR4_MASK 16U +#define CAN4RXTSR_TSR5_MASK 32U +#define CAN4RXTSR_TSR6_MASK 64U +#define CAN4RXTSR_TSR7_MASK 128U +#define CAN4RXTSR_TSR8_MASK 256U +#define CAN4RXTSR_TSR9_MASK 512U +#define CAN4RXTSR_TSR10_MASK 1024U +#define CAN4RXTSR_TSR11_MASK 2048U +#define CAN4RXTSR_TSR12_MASK 4096U +#define CAN4RXTSR_TSR13_MASK 8192U +#define CAN4RXTSR_TSR14_MASK 16384U +#define CAN4RXTSR_TSR15_MASK 32768U + + +/*** CAN4TXIDR0 - MSCAN4 Transmit Identifier Register 0; 0x000002B0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; +} CAN4TXIDR0STR; +extern volatile CAN4TXIDR0STR _CAN4TXIDR0 @(REG_BASE + 0x000002B0UL); +#define CAN4TXIDR0 _CAN4TXIDR0.Byte +#define CAN4TXIDR0_ID21 _CAN4TXIDR0.Bits.ID21 +#define CAN4TXIDR0_ID22 _CAN4TXIDR0.Bits.ID22 +#define CAN4TXIDR0_ID23 _CAN4TXIDR0.Bits.ID23 +#define CAN4TXIDR0_ID24 _CAN4TXIDR0.Bits.ID24 +#define CAN4TXIDR0_ID25 _CAN4TXIDR0.Bits.ID25 +#define CAN4TXIDR0_ID26 _CAN4TXIDR0.Bits.ID26 +#define CAN4TXIDR0_ID27 _CAN4TXIDR0.Bits.ID27 +#define CAN4TXIDR0_ID28 _CAN4TXIDR0.Bits.ID28 +/* CAN4TXIDR_ARR: Access 4 CAN4TXIDRx registers in an array */ +#define CAN4TXIDR_ARR ((volatile byte *) &CAN4TXIDR0) + +#define CAN4TXIDR0_ID21_MASK 1U +#define CAN4TXIDR0_ID22_MASK 2U +#define CAN4TXIDR0_ID23_MASK 4U +#define CAN4TXIDR0_ID24_MASK 8U +#define CAN4TXIDR0_ID25_MASK 16U +#define CAN4TXIDR0_ID26_MASK 32U +#define CAN4TXIDR0_ID27_MASK 64U +#define CAN4TXIDR0_ID28_MASK 128U + + +/*** CAN4TXIDR1 - MSCAN4 Transmit Identifier Register 1; 0x000002B1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN4TXIDR1STR; +extern volatile CAN4TXIDR1STR _CAN4TXIDR1 @(REG_BASE + 0x000002B1UL); +#define CAN4TXIDR1 _CAN4TXIDR1.Byte +#define CAN4TXIDR1_ID15 _CAN4TXIDR1.Bits.ID15 +#define CAN4TXIDR1_ID16 _CAN4TXIDR1.Bits.ID16 +#define CAN4TXIDR1_ID17 _CAN4TXIDR1.Bits.ID17 +#define CAN4TXIDR1_IDE _CAN4TXIDR1.Bits.IDE +#define CAN4TXIDR1_SRR _CAN4TXIDR1.Bits.SRR +#define CAN4TXIDR1_ID18 _CAN4TXIDR1.Bits.ID18 +#define CAN4TXIDR1_ID19 _CAN4TXIDR1.Bits.ID19 +#define CAN4TXIDR1_ID20 _CAN4TXIDR1.Bits.ID20 +#define CAN4TXIDR1_ID_15 _CAN4TXIDR1.MergedBits.grpID_15 +#define CAN4TXIDR1_ID_18 _CAN4TXIDR1.MergedBits.grpID_18 +#define CAN4TXIDR1_ID CAN4TXIDR1_ID_15 + +#define CAN4TXIDR1_ID15_MASK 1U +#define CAN4TXIDR1_ID16_MASK 2U +#define CAN4TXIDR1_ID17_MASK 4U +#define CAN4TXIDR1_IDE_MASK 8U +#define CAN4TXIDR1_SRR_MASK 16U +#define CAN4TXIDR1_ID18_MASK 32U +#define CAN4TXIDR1_ID19_MASK 64U +#define CAN4TXIDR1_ID20_MASK 128U +#define CAN4TXIDR1_ID_15_MASK 7U +#define CAN4TXIDR1_ID_15_BITNUM 0U +#define CAN4TXIDR1_ID_18_MASK 224U +#define CAN4TXIDR1_ID_18_BITNUM 5U + + +/*** CAN4TXIDR2 - MSCAN4 Transmit Identifier Register 2; 0x000002B2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; +} CAN4TXIDR2STR; +extern volatile CAN4TXIDR2STR _CAN4TXIDR2 @(REG_BASE + 0x000002B2UL); +#define CAN4TXIDR2 _CAN4TXIDR2.Byte +#define CAN4TXIDR2_ID7 _CAN4TXIDR2.Bits.ID7 +#define CAN4TXIDR2_ID8 _CAN4TXIDR2.Bits.ID8 +#define CAN4TXIDR2_ID9 _CAN4TXIDR2.Bits.ID9 +#define CAN4TXIDR2_ID10 _CAN4TXIDR2.Bits.ID10 +#define CAN4TXIDR2_ID11 _CAN4TXIDR2.Bits.ID11 +#define CAN4TXIDR2_ID12 _CAN4TXIDR2.Bits.ID12 +#define CAN4TXIDR2_ID13 _CAN4TXIDR2.Bits.ID13 +#define CAN4TXIDR2_ID14 _CAN4TXIDR2.Bits.ID14 + +#define CAN4TXIDR2_ID7_MASK 1U +#define CAN4TXIDR2_ID8_MASK 2U +#define CAN4TXIDR2_ID9_MASK 4U +#define CAN4TXIDR2_ID10_MASK 8U +#define CAN4TXIDR2_ID11_MASK 16U +#define CAN4TXIDR2_ID12_MASK 32U +#define CAN4TXIDR2_ID13_MASK 64U +#define CAN4TXIDR2_ID14_MASK 128U + + +/*** CAN4TXIDR3 - MSCAN4 Transmit Identifier Register 3; 0x000002B3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN4TXIDR3STR; +extern volatile CAN4TXIDR3STR _CAN4TXIDR3 @(REG_BASE + 0x000002B3UL); +#define CAN4TXIDR3 _CAN4TXIDR3.Byte +#define CAN4TXIDR3_RTR _CAN4TXIDR3.Bits.RTR +#define CAN4TXIDR3_ID0 _CAN4TXIDR3.Bits.ID0 +#define CAN4TXIDR3_ID1 _CAN4TXIDR3.Bits.ID1 +#define CAN4TXIDR3_ID2 _CAN4TXIDR3.Bits.ID2 +#define CAN4TXIDR3_ID3 _CAN4TXIDR3.Bits.ID3 +#define CAN4TXIDR3_ID4 _CAN4TXIDR3.Bits.ID4 +#define CAN4TXIDR3_ID5 _CAN4TXIDR3.Bits.ID5 +#define CAN4TXIDR3_ID6 _CAN4TXIDR3.Bits.ID6 +#define CAN4TXIDR3_ID _CAN4TXIDR3.MergedBits.grpID + +#define CAN4TXIDR3_RTR_MASK 1U +#define CAN4TXIDR3_ID0_MASK 2U +#define CAN4TXIDR3_ID1_MASK 4U +#define CAN4TXIDR3_ID2_MASK 8U +#define CAN4TXIDR3_ID3_MASK 16U +#define CAN4TXIDR3_ID4_MASK 32U +#define CAN4TXIDR3_ID5_MASK 64U +#define CAN4TXIDR3_ID6_MASK 128U +#define CAN4TXIDR3_ID_MASK 254U +#define CAN4TXIDR3_ID_BITNUM 1U + + +/*** CAN4TXDSR0 - MSCAN4 Transmit Data Segment Register 0; 0x000002B4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR0STR; +extern volatile CAN4TXDSR0STR _CAN4TXDSR0 @(REG_BASE + 0x000002B4UL); +#define CAN4TXDSR0 _CAN4TXDSR0.Byte +#define CAN4TXDSR0_DB0 _CAN4TXDSR0.Bits.DB0 +#define CAN4TXDSR0_DB1 _CAN4TXDSR0.Bits.DB1 +#define CAN4TXDSR0_DB2 _CAN4TXDSR0.Bits.DB2 +#define CAN4TXDSR0_DB3 _CAN4TXDSR0.Bits.DB3 +#define CAN4TXDSR0_DB4 _CAN4TXDSR0.Bits.DB4 +#define CAN4TXDSR0_DB5 _CAN4TXDSR0.Bits.DB5 +#define CAN4TXDSR0_DB6 _CAN4TXDSR0.Bits.DB6 +#define CAN4TXDSR0_DB7 _CAN4TXDSR0.Bits.DB7 +/* CAN4TXDSR_ARR: Access 8 CAN4TXDSRx registers in an array */ +#define CAN4TXDSR_ARR ((volatile byte *) &CAN4TXDSR0) + +#define CAN4TXDSR0_DB0_MASK 1U +#define CAN4TXDSR0_DB1_MASK 2U +#define CAN4TXDSR0_DB2_MASK 4U +#define CAN4TXDSR0_DB3_MASK 8U +#define CAN4TXDSR0_DB4_MASK 16U +#define CAN4TXDSR0_DB5_MASK 32U +#define CAN4TXDSR0_DB6_MASK 64U +#define CAN4TXDSR0_DB7_MASK 128U + + +/*** CAN4TXDSR1 - MSCAN4 Transmit Data Segment Register 1; 0x000002B5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR1STR; +extern volatile CAN4TXDSR1STR _CAN4TXDSR1 @(REG_BASE + 0x000002B5UL); +#define CAN4TXDSR1 _CAN4TXDSR1.Byte +#define CAN4TXDSR1_DB0 _CAN4TXDSR1.Bits.DB0 +#define CAN4TXDSR1_DB1 _CAN4TXDSR1.Bits.DB1 +#define CAN4TXDSR1_DB2 _CAN4TXDSR1.Bits.DB2 +#define CAN4TXDSR1_DB3 _CAN4TXDSR1.Bits.DB3 +#define CAN4TXDSR1_DB4 _CAN4TXDSR1.Bits.DB4 +#define CAN4TXDSR1_DB5 _CAN4TXDSR1.Bits.DB5 +#define CAN4TXDSR1_DB6 _CAN4TXDSR1.Bits.DB6 +#define CAN4TXDSR1_DB7 _CAN4TXDSR1.Bits.DB7 + +#define CAN4TXDSR1_DB0_MASK 1U +#define CAN4TXDSR1_DB1_MASK 2U +#define CAN4TXDSR1_DB2_MASK 4U +#define CAN4TXDSR1_DB3_MASK 8U +#define CAN4TXDSR1_DB4_MASK 16U +#define CAN4TXDSR1_DB5_MASK 32U +#define CAN4TXDSR1_DB6_MASK 64U +#define CAN4TXDSR1_DB7_MASK 128U + + +/*** CAN4TXDSR2 - MSCAN4 Transmit Data Segment Register 2; 0x000002B6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR2STR; +extern volatile CAN4TXDSR2STR _CAN4TXDSR2 @(REG_BASE + 0x000002B6UL); +#define CAN4TXDSR2 _CAN4TXDSR2.Byte +#define CAN4TXDSR2_DB0 _CAN4TXDSR2.Bits.DB0 +#define CAN4TXDSR2_DB1 _CAN4TXDSR2.Bits.DB1 +#define CAN4TXDSR2_DB2 _CAN4TXDSR2.Bits.DB2 +#define CAN4TXDSR2_DB3 _CAN4TXDSR2.Bits.DB3 +#define CAN4TXDSR2_DB4 _CAN4TXDSR2.Bits.DB4 +#define CAN4TXDSR2_DB5 _CAN4TXDSR2.Bits.DB5 +#define CAN4TXDSR2_DB6 _CAN4TXDSR2.Bits.DB6 +#define CAN4TXDSR2_DB7 _CAN4TXDSR2.Bits.DB7 + +#define CAN4TXDSR2_DB0_MASK 1U +#define CAN4TXDSR2_DB1_MASK 2U +#define CAN4TXDSR2_DB2_MASK 4U +#define CAN4TXDSR2_DB3_MASK 8U +#define CAN4TXDSR2_DB4_MASK 16U +#define CAN4TXDSR2_DB5_MASK 32U +#define CAN4TXDSR2_DB6_MASK 64U +#define CAN4TXDSR2_DB7_MASK 128U + + +/*** CAN4TXDSR3 - MSCAN4 Transmit Data Segment Register 3; 0x000002B7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR3STR; +extern volatile CAN4TXDSR3STR _CAN4TXDSR3 @(REG_BASE + 0x000002B7UL); +#define CAN4TXDSR3 _CAN4TXDSR3.Byte +#define CAN4TXDSR3_DB0 _CAN4TXDSR3.Bits.DB0 +#define CAN4TXDSR3_DB1 _CAN4TXDSR3.Bits.DB1 +#define CAN4TXDSR3_DB2 _CAN4TXDSR3.Bits.DB2 +#define CAN4TXDSR3_DB3 _CAN4TXDSR3.Bits.DB3 +#define CAN4TXDSR3_DB4 _CAN4TXDSR3.Bits.DB4 +#define CAN4TXDSR3_DB5 _CAN4TXDSR3.Bits.DB5 +#define CAN4TXDSR3_DB6 _CAN4TXDSR3.Bits.DB6 +#define CAN4TXDSR3_DB7 _CAN4TXDSR3.Bits.DB7 + +#define CAN4TXDSR3_DB0_MASK 1U +#define CAN4TXDSR3_DB1_MASK 2U +#define CAN4TXDSR3_DB2_MASK 4U +#define CAN4TXDSR3_DB3_MASK 8U +#define CAN4TXDSR3_DB4_MASK 16U +#define CAN4TXDSR3_DB5_MASK 32U +#define CAN4TXDSR3_DB6_MASK 64U +#define CAN4TXDSR3_DB7_MASK 128U + + +/*** CAN4TXDSR4 - MSCAN4 Transmit Data Segment Register 4; 0x000002B8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR4STR; +extern volatile CAN4TXDSR4STR _CAN4TXDSR4 @(REG_BASE + 0x000002B8UL); +#define CAN4TXDSR4 _CAN4TXDSR4.Byte +#define CAN4TXDSR4_DB0 _CAN4TXDSR4.Bits.DB0 +#define CAN4TXDSR4_DB1 _CAN4TXDSR4.Bits.DB1 +#define CAN4TXDSR4_DB2 _CAN4TXDSR4.Bits.DB2 +#define CAN4TXDSR4_DB3 _CAN4TXDSR4.Bits.DB3 +#define CAN4TXDSR4_DB4 _CAN4TXDSR4.Bits.DB4 +#define CAN4TXDSR4_DB5 _CAN4TXDSR4.Bits.DB5 +#define CAN4TXDSR4_DB6 _CAN4TXDSR4.Bits.DB6 +#define CAN4TXDSR4_DB7 _CAN4TXDSR4.Bits.DB7 + +#define CAN4TXDSR4_DB0_MASK 1U +#define CAN4TXDSR4_DB1_MASK 2U +#define CAN4TXDSR4_DB2_MASK 4U +#define CAN4TXDSR4_DB3_MASK 8U +#define CAN4TXDSR4_DB4_MASK 16U +#define CAN4TXDSR4_DB5_MASK 32U +#define CAN4TXDSR4_DB6_MASK 64U +#define CAN4TXDSR4_DB7_MASK 128U + + +/*** CAN4TXDSR5 - MSCAN4 Transmit Data Segment Register 5; 0x000002B9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR5STR; +extern volatile CAN4TXDSR5STR _CAN4TXDSR5 @(REG_BASE + 0x000002B9UL); +#define CAN4TXDSR5 _CAN4TXDSR5.Byte +#define CAN4TXDSR5_DB0 _CAN4TXDSR5.Bits.DB0 +#define CAN4TXDSR5_DB1 _CAN4TXDSR5.Bits.DB1 +#define CAN4TXDSR5_DB2 _CAN4TXDSR5.Bits.DB2 +#define CAN4TXDSR5_DB3 _CAN4TXDSR5.Bits.DB3 +#define CAN4TXDSR5_DB4 _CAN4TXDSR5.Bits.DB4 +#define CAN4TXDSR5_DB5 _CAN4TXDSR5.Bits.DB5 +#define CAN4TXDSR5_DB6 _CAN4TXDSR5.Bits.DB6 +#define CAN4TXDSR5_DB7 _CAN4TXDSR5.Bits.DB7 + +#define CAN4TXDSR5_DB0_MASK 1U +#define CAN4TXDSR5_DB1_MASK 2U +#define CAN4TXDSR5_DB2_MASK 4U +#define CAN4TXDSR5_DB3_MASK 8U +#define CAN4TXDSR5_DB4_MASK 16U +#define CAN4TXDSR5_DB5_MASK 32U +#define CAN4TXDSR5_DB6_MASK 64U +#define CAN4TXDSR5_DB7_MASK 128U + + +/*** CAN4TXDSR6 - MSCAN4 Transmit Data Segment Register 6; 0x000002BA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR6STR; +extern volatile CAN4TXDSR6STR _CAN4TXDSR6 @(REG_BASE + 0x000002BAUL); +#define CAN4TXDSR6 _CAN4TXDSR6.Byte +#define CAN4TXDSR6_DB0 _CAN4TXDSR6.Bits.DB0 +#define CAN4TXDSR6_DB1 _CAN4TXDSR6.Bits.DB1 +#define CAN4TXDSR6_DB2 _CAN4TXDSR6.Bits.DB2 +#define CAN4TXDSR6_DB3 _CAN4TXDSR6.Bits.DB3 +#define CAN4TXDSR6_DB4 _CAN4TXDSR6.Bits.DB4 +#define CAN4TXDSR6_DB5 _CAN4TXDSR6.Bits.DB5 +#define CAN4TXDSR6_DB6 _CAN4TXDSR6.Bits.DB6 +#define CAN4TXDSR6_DB7 _CAN4TXDSR6.Bits.DB7 + +#define CAN4TXDSR6_DB0_MASK 1U +#define CAN4TXDSR6_DB1_MASK 2U +#define CAN4TXDSR6_DB2_MASK 4U +#define CAN4TXDSR6_DB3_MASK 8U +#define CAN4TXDSR6_DB4_MASK 16U +#define CAN4TXDSR6_DB5_MASK 32U +#define CAN4TXDSR6_DB6_MASK 64U +#define CAN4TXDSR6_DB7_MASK 128U + + +/*** CAN4TXDSR7 - MSCAN4 Transmit Data Segment Register 7; 0x000002BB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR7STR; +extern volatile CAN4TXDSR7STR _CAN4TXDSR7 @(REG_BASE + 0x000002BBUL); +#define CAN4TXDSR7 _CAN4TXDSR7.Byte +#define CAN4TXDSR7_DB0 _CAN4TXDSR7.Bits.DB0 +#define CAN4TXDSR7_DB1 _CAN4TXDSR7.Bits.DB1 +#define CAN4TXDSR7_DB2 _CAN4TXDSR7.Bits.DB2 +#define CAN4TXDSR7_DB3 _CAN4TXDSR7.Bits.DB3 +#define CAN4TXDSR7_DB4 _CAN4TXDSR7.Bits.DB4 +#define CAN4TXDSR7_DB5 _CAN4TXDSR7.Bits.DB5 +#define CAN4TXDSR7_DB6 _CAN4TXDSR7.Bits.DB6 +#define CAN4TXDSR7_DB7 _CAN4TXDSR7.Bits.DB7 + +#define CAN4TXDSR7_DB0_MASK 1U +#define CAN4TXDSR7_DB1_MASK 2U +#define CAN4TXDSR7_DB2_MASK 4U +#define CAN4TXDSR7_DB3_MASK 8U +#define CAN4TXDSR7_DB4_MASK 16U +#define CAN4TXDSR7_DB5_MASK 32U +#define CAN4TXDSR7_DB6_MASK 64U +#define CAN4TXDSR7_DB7_MASK 128U + + +/*** CAN4TXDLR - MSCAN4 Transmit Data Length Register; 0x000002BC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TXDLRSTR; +extern volatile CAN4TXDLRSTR _CAN4TXDLR @(REG_BASE + 0x000002BCUL); +#define CAN4TXDLR _CAN4TXDLR.Byte +#define CAN4TXDLR_DLC0 _CAN4TXDLR.Bits.DLC0 +#define CAN4TXDLR_DLC1 _CAN4TXDLR.Bits.DLC1 +#define CAN4TXDLR_DLC2 _CAN4TXDLR.Bits.DLC2 +#define CAN4TXDLR_DLC3 _CAN4TXDLR.Bits.DLC3 +#define CAN4TXDLR_DLC _CAN4TXDLR.MergedBits.grpDLC + +#define CAN4TXDLR_DLC0_MASK 1U +#define CAN4TXDLR_DLC1_MASK 2U +#define CAN4TXDLR_DLC2_MASK 4U +#define CAN4TXDLR_DLC3_MASK 8U +#define CAN4TXDLR_DLC_MASK 15U +#define CAN4TXDLR_DLC_BITNUM 0U + + +/*** CAN4TXTBPR - MSCAN4 Transmit Transmit Buffer Priority; 0x000002BD ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; +} CAN4TXTBPRSTR; +extern volatile CAN4TXTBPRSTR _CAN4TXTBPR @(REG_BASE + 0x000002BDUL); +#define CAN4TXTBPR _CAN4TXTBPR.Byte +#define CAN4TXTBPR_PRIO0 _CAN4TXTBPR.Bits.PRIO0 +#define CAN4TXTBPR_PRIO1 _CAN4TXTBPR.Bits.PRIO1 +#define CAN4TXTBPR_PRIO2 _CAN4TXTBPR.Bits.PRIO2 +#define CAN4TXTBPR_PRIO3 _CAN4TXTBPR.Bits.PRIO3 +#define CAN4TXTBPR_PRIO4 _CAN4TXTBPR.Bits.PRIO4 +#define CAN4TXTBPR_PRIO5 _CAN4TXTBPR.Bits.PRIO5 +#define CAN4TXTBPR_PRIO6 _CAN4TXTBPR.Bits.PRIO6 +#define CAN4TXTBPR_PRIO7 _CAN4TXTBPR.Bits.PRIO7 + +#define CAN4TXTBPR_PRIO0_MASK 1U +#define CAN4TXTBPR_PRIO1_MASK 2U +#define CAN4TXTBPR_PRIO2_MASK 4U +#define CAN4TXTBPR_PRIO3_MASK 8U +#define CAN4TXTBPR_PRIO4_MASK 16U +#define CAN4TXTBPR_PRIO5_MASK 32U +#define CAN4TXTBPR_PRIO6_MASK 64U +#define CAN4TXTBPR_PRIO7_MASK 128U + + +/*** CAN4TXTSR - MSCAN 4 Transmit Time Stamp Register; 0x000002BE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** CAN4TXTSRH - MSCAN 4 Transmit Time Stamp Register High; 0x000002BE ***/ + union { + byte Byte; + struct { + byte TSR8 :1; /* Time Stamp Bit 8 */ + byte TSR9 :1; /* Time Stamp Bit 9 */ + byte TSR10 :1; /* Time Stamp Bit 10 */ + byte TSR11 :1; /* Time Stamp Bit 11 */ + byte TSR12 :1; /* Time Stamp Bit 12 */ + byte TSR13 :1; /* Time Stamp Bit 13 */ + byte TSR14 :1; /* Time Stamp Bit 14 */ + byte TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; + } CAN4TXTSRHSTR; + #define CAN4TXTSRH _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Byte + #define CAN4TXTSRH_TSR8 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR8 + #define CAN4TXTSRH_TSR9 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR9 + #define CAN4TXTSRH_TSR10 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR10 + #define CAN4TXTSRH_TSR11 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR11 + #define CAN4TXTSRH_TSR12 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR12 + #define CAN4TXTSRH_TSR13 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR13 + #define CAN4TXTSRH_TSR14 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR14 + #define CAN4TXTSRH_TSR15 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR15 + + #define CAN4TXTSRH_TSR8_MASK 1U + #define CAN4TXTSRH_TSR9_MASK 2U + #define CAN4TXTSRH_TSR10_MASK 4U + #define CAN4TXTSRH_TSR11_MASK 8U + #define CAN4TXTSRH_TSR12_MASK 16U + #define CAN4TXTSRH_TSR13_MASK 32U + #define CAN4TXTSRH_TSR14_MASK 64U + #define CAN4TXTSRH_TSR15_MASK 128U + + + /*** CAN4TXTSRL - MSCAN 4 Transmit Time Stamp Register Low; 0x000002BF ***/ + union { + byte Byte; + struct { + byte TSR0 :1; /* Time Stamp Bit 0 */ + byte TSR1 :1; /* Time Stamp Bit 1 */ + byte TSR2 :1; /* Time Stamp Bit 2 */ + byte TSR3 :1; /* Time Stamp Bit 3 */ + byte TSR4 :1; /* Time Stamp Bit 4 */ + byte TSR5 :1; /* Time Stamp Bit 5 */ + byte TSR6 :1; /* Time Stamp Bit 6 */ + byte TSR7 :1; /* Time Stamp Bit 7 */ + } Bits; + } CAN4TXTSRLSTR; + #define CAN4TXTSRL _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Byte + #define CAN4TXTSRL_TSR0 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR0 + #define CAN4TXTSRL_TSR1 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR1 + #define CAN4TXTSRL_TSR2 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR2 + #define CAN4TXTSRL_TSR3 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR3 + #define CAN4TXTSRL_TSR4 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR4 + #define CAN4TXTSRL_TSR5 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR5 + #define CAN4TXTSRL_TSR6 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR6 + #define CAN4TXTSRL_TSR7 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR7 + + #define CAN4TXTSRL_TSR0_MASK 1U + #define CAN4TXTSRL_TSR1_MASK 2U + #define CAN4TXTSRL_TSR2_MASK 4U + #define CAN4TXTSRL_TSR3_MASK 8U + #define CAN4TXTSRL_TSR4_MASK 16U + #define CAN4TXTSRL_TSR5_MASK 32U + #define CAN4TXTSRL_TSR6_MASK 64U + #define CAN4TXTSRL_TSR7_MASK 128U + + } Overlap_STR; + + struct { + word TSR0 :1; /* Time Stamp Bit 0 */ + word TSR1 :1; /* Time Stamp Bit 1 */ + word TSR2 :1; /* Time Stamp Bit 2 */ + word TSR3 :1; /* Time Stamp Bit 3 */ + word TSR4 :1; /* Time Stamp Bit 4 */ + word TSR5 :1; /* Time Stamp Bit 5 */ + word TSR6 :1; /* Time Stamp Bit 6 */ + word TSR7 :1; /* Time Stamp Bit 7 */ + word TSR8 :1; /* Time Stamp Bit 8 */ + word TSR9 :1; /* Time Stamp Bit 9 */ + word TSR10 :1; /* Time Stamp Bit 10 */ + word TSR11 :1; /* Time Stamp Bit 11 */ + word TSR12 :1; /* Time Stamp Bit 12 */ + word TSR13 :1; /* Time Stamp Bit 13 */ + word TSR14 :1; /* Time Stamp Bit 14 */ + word TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; +} CAN4TXTSRSTR; +extern volatile CAN4TXTSRSTR _CAN4TXTSR @(REG_BASE + 0x000002BEUL); +#define CAN4TXTSR _CAN4TXTSR.Word +#define CAN4TXTSR_TSR0 _CAN4TXTSR.Bits.TSR0 +#define CAN4TXTSR_TSR1 _CAN4TXTSR.Bits.TSR1 +#define CAN4TXTSR_TSR2 _CAN4TXTSR.Bits.TSR2 +#define CAN4TXTSR_TSR3 _CAN4TXTSR.Bits.TSR3 +#define CAN4TXTSR_TSR4 _CAN4TXTSR.Bits.TSR4 +#define CAN4TXTSR_TSR5 _CAN4TXTSR.Bits.TSR5 +#define CAN4TXTSR_TSR6 _CAN4TXTSR.Bits.TSR6 +#define CAN4TXTSR_TSR7 _CAN4TXTSR.Bits.TSR7 +#define CAN4TXTSR_TSR8 _CAN4TXTSR.Bits.TSR8 +#define CAN4TXTSR_TSR9 _CAN4TXTSR.Bits.TSR9 +#define CAN4TXTSR_TSR10 _CAN4TXTSR.Bits.TSR10 +#define CAN4TXTSR_TSR11 _CAN4TXTSR.Bits.TSR11 +#define CAN4TXTSR_TSR12 _CAN4TXTSR.Bits.TSR12 +#define CAN4TXTSR_TSR13 _CAN4TXTSR.Bits.TSR13 +#define CAN4TXTSR_TSR14 _CAN4TXTSR.Bits.TSR14 +#define CAN4TXTSR_TSR15 _CAN4TXTSR.Bits.TSR15 + +#define CAN4TXTSR_TSR0_MASK 1U +#define CAN4TXTSR_TSR1_MASK 2U +#define CAN4TXTSR_TSR2_MASK 4U +#define CAN4TXTSR_TSR3_MASK 8U +#define CAN4TXTSR_TSR4_MASK 16U +#define CAN4TXTSR_TSR5_MASK 32U +#define CAN4TXTSR_TSR6_MASK 64U +#define CAN4TXTSR_TSR7_MASK 128U +#define CAN4TXTSR_TSR8_MASK 256U +#define CAN4TXTSR_TSR9_MASK 512U +#define CAN4TXTSR_TSR10_MASK 1024U +#define CAN4TXTSR_TSR11_MASK 2048U +#define CAN4TXTSR_TSR12_MASK 4096U +#define CAN4TXTSR_TSR13_MASK 8192U +#define CAN4TXTSR_TSR14_MASK 16384U +#define CAN4TXTSR_TSR15_MASK 32768U + + +/*** BAKEY0 - Backdoor Access Key 0; 0x0000FF00 ***/ +typedef union { + word Word; + struct { + word KEY0 :1; /* Backdoor Access Key bits, bit 0 */ + word KEY1 :1; /* Backdoor Access Key bits, bit 1 */ + word KEY2 :1; /* Backdoor Access Key bits, bit 2 */ + word KEY3 :1; /* Backdoor Access Key bits, bit 3 */ + word KEY4 :1; /* Backdoor Access Key bits, bit 4 */ + word KEY5 :1; /* Backdoor Access Key bits, bit 5 */ + word KEY6 :1; /* Backdoor Access Key bits, bit 6 */ + word KEY7 :1; /* Backdoor Access Key bits, bit 7 */ + word KEY8 :1; /* Backdoor Access Key bits, bit 8 */ + word KEY9 :1; /* Backdoor Access Key bits, bit 9 */ + word KEY10 :1; /* Backdoor Access Key bits, bit 10 */ + word KEY11 :1; /* Backdoor Access Key bits, bit 11 */ + word KEY12 :1; /* Backdoor Access Key bits, bit 12 */ + word KEY13 :1; /* Backdoor Access Key bits, bit 13 */ + word KEY14 :1; /* Backdoor Access Key bits, bit 14 */ + word KEY15 :1; /* Backdoor Access Key bits, bit 15 */ + } Bits; +} BAKEY0STR; +/* Tip for register initialization in the user code: const word BAKEY0_INIT @0x0000FF00 = ; */ +#define _BAKEY0 (*(const BAKEY0STR *)0x0000FF00) +#define BAKEY0 _BAKEY0.Word +#define BAKEY0_KEY0 _BAKEY0.Bits.KEY0 +#define BAKEY0_KEY1 _BAKEY0.Bits.KEY1 +#define BAKEY0_KEY2 _BAKEY0.Bits.KEY2 +#define BAKEY0_KEY3 _BAKEY0.Bits.KEY3 +#define BAKEY0_KEY4 _BAKEY0.Bits.KEY4 +#define BAKEY0_KEY5 _BAKEY0.Bits.KEY5 +#define BAKEY0_KEY6 _BAKEY0.Bits.KEY6 +#define BAKEY0_KEY7 _BAKEY0.Bits.KEY7 +#define BAKEY0_KEY8 _BAKEY0.Bits.KEY8 +#define BAKEY0_KEY9 _BAKEY0.Bits.KEY9 +#define BAKEY0_KEY10 _BAKEY0.Bits.KEY10 +#define BAKEY0_KEY11 _BAKEY0.Bits.KEY11 +#define BAKEY0_KEY12 _BAKEY0.Bits.KEY12 +#define BAKEY0_KEY13 _BAKEY0.Bits.KEY13 +#define BAKEY0_KEY14 _BAKEY0.Bits.KEY14 +#define BAKEY0_KEY15 _BAKEY0.Bits.KEY15 +/* BAKEY_ARR: Access 4 BAKEYx registers in an array */ +#define BAKEY_ARR ((volatile word *) &BAKEY0) + +#define BAKEY0_KEY0_MASK 1U +#define BAKEY0_KEY1_MASK 2U +#define BAKEY0_KEY2_MASK 4U +#define BAKEY0_KEY3_MASK 8U +#define BAKEY0_KEY4_MASK 16U +#define BAKEY0_KEY5_MASK 32U +#define BAKEY0_KEY6_MASK 64U +#define BAKEY0_KEY7_MASK 128U +#define BAKEY0_KEY8_MASK 256U +#define BAKEY0_KEY9_MASK 512U +#define BAKEY0_KEY10_MASK 1024U +#define BAKEY0_KEY11_MASK 2048U +#define BAKEY0_KEY12_MASK 4096U +#define BAKEY0_KEY13_MASK 8192U +#define BAKEY0_KEY14_MASK 16384U +#define BAKEY0_KEY15_MASK 32768U + + +/*** BAKEY1 - Backdoor Access Key 1; 0x0000FF02 ***/ +typedef union { + word Word; + struct { + word KEY0 :1; /* Backdoor Access Key bits, bit 0 */ + word KEY1 :1; /* Backdoor Access Key bits, bit 1 */ + word KEY2 :1; /* Backdoor Access Key bits, bit 2 */ + word KEY3 :1; /* Backdoor Access Key bits, bit 3 */ + word KEY4 :1; /* Backdoor Access Key bits, bit 4 */ + word KEY5 :1; /* Backdoor Access Key bits, bit 5 */ + word KEY6 :1; /* Backdoor Access Key bits, bit 6 */ + word KEY7 :1; /* Backdoor Access Key bits, bit 7 */ + word KEY8 :1; /* Backdoor Access Key bits, bit 8 */ + word KEY9 :1; /* Backdoor Access Key bits, bit 9 */ + word KEY10 :1; /* Backdoor Access Key bits, bit 10 */ + word KEY11 :1; /* Backdoor Access Key bits, bit 11 */ + word KEY12 :1; /* Backdoor Access Key bits, bit 12 */ + word KEY13 :1; /* Backdoor Access Key bits, bit 13 */ + word KEY14 :1; /* Backdoor Access Key bits, bit 14 */ + word KEY15 :1; /* Backdoor Access Key bits, bit 15 */ + } Bits; +} BAKEY1STR; +/* Tip for register initialization in the user code: const word BAKEY1_INIT @0x0000FF02 = ; */ +#define _BAKEY1 (*(const BAKEY1STR *)0x0000FF02) +#define BAKEY1 _BAKEY1.Word +#define BAKEY1_KEY0 _BAKEY1.Bits.KEY0 +#define BAKEY1_KEY1 _BAKEY1.Bits.KEY1 +#define BAKEY1_KEY2 _BAKEY1.Bits.KEY2 +#define BAKEY1_KEY3 _BAKEY1.Bits.KEY3 +#define BAKEY1_KEY4 _BAKEY1.Bits.KEY4 +#define BAKEY1_KEY5 _BAKEY1.Bits.KEY5 +#define BAKEY1_KEY6 _BAKEY1.Bits.KEY6 +#define BAKEY1_KEY7 _BAKEY1.Bits.KEY7 +#define BAKEY1_KEY8 _BAKEY1.Bits.KEY8 +#define BAKEY1_KEY9 _BAKEY1.Bits.KEY9 +#define BAKEY1_KEY10 _BAKEY1.Bits.KEY10 +#define BAKEY1_KEY11 _BAKEY1.Bits.KEY11 +#define BAKEY1_KEY12 _BAKEY1.Bits.KEY12 +#define BAKEY1_KEY13 _BAKEY1.Bits.KEY13 +#define BAKEY1_KEY14 _BAKEY1.Bits.KEY14 +#define BAKEY1_KEY15 _BAKEY1.Bits.KEY15 + +#define BAKEY1_KEY0_MASK 1U +#define BAKEY1_KEY1_MASK 2U +#define BAKEY1_KEY2_MASK 4U +#define BAKEY1_KEY3_MASK 8U +#define BAKEY1_KEY4_MASK 16U +#define BAKEY1_KEY5_MASK 32U +#define BAKEY1_KEY6_MASK 64U +#define BAKEY1_KEY7_MASK 128U +#define BAKEY1_KEY8_MASK 256U +#define BAKEY1_KEY9_MASK 512U +#define BAKEY1_KEY10_MASK 1024U +#define BAKEY1_KEY11_MASK 2048U +#define BAKEY1_KEY12_MASK 4096U +#define BAKEY1_KEY13_MASK 8192U +#define BAKEY1_KEY14_MASK 16384U +#define BAKEY1_KEY15_MASK 32768U + + +/*** BAKEY2 - Backdoor Access Key 2; 0x0000FF04 ***/ +typedef union { + word Word; + struct { + word KEY0 :1; /* Backdoor Access Key bits, bit 0 */ + word KEY1 :1; /* Backdoor Access Key bits, bit 1 */ + word KEY2 :1; /* Backdoor Access Key bits, bit 2 */ + word KEY3 :1; /* Backdoor Access Key bits, bit 3 */ + word KEY4 :1; /* Backdoor Access Key bits, bit 4 */ + word KEY5 :1; /* Backdoor Access Key bits, bit 5 */ + word KEY6 :1; /* Backdoor Access Key bits, bit 6 */ + word KEY7 :1; /* Backdoor Access Key bits, bit 7 */ + word KEY8 :1; /* Backdoor Access Key bits, bit 8 */ + word KEY9 :1; /* Backdoor Access Key bits, bit 9 */ + word KEY10 :1; /* Backdoor Access Key bits, bit 10 */ + word KEY11 :1; /* Backdoor Access Key bits, bit 11 */ + word KEY12 :1; /* Backdoor Access Key bits, bit 12 */ + word KEY13 :1; /* Backdoor Access Key bits, bit 13 */ + word KEY14 :1; /* Backdoor Access Key bits, bit 14 */ + word KEY15 :1; /* Backdoor Access Key bits, bit 15 */ + } Bits; +} BAKEY2STR; +/* Tip for register initialization in the user code: const word BAKEY2_INIT @0x0000FF04 = ; */ +#define _BAKEY2 (*(const BAKEY2STR *)0x0000FF04) +#define BAKEY2 _BAKEY2.Word +#define BAKEY2_KEY0 _BAKEY2.Bits.KEY0 +#define BAKEY2_KEY1 _BAKEY2.Bits.KEY1 +#define BAKEY2_KEY2 _BAKEY2.Bits.KEY2 +#define BAKEY2_KEY3 _BAKEY2.Bits.KEY3 +#define BAKEY2_KEY4 _BAKEY2.Bits.KEY4 +#define BAKEY2_KEY5 _BAKEY2.Bits.KEY5 +#define BAKEY2_KEY6 _BAKEY2.Bits.KEY6 +#define BAKEY2_KEY7 _BAKEY2.Bits.KEY7 +#define BAKEY2_KEY8 _BAKEY2.Bits.KEY8 +#define BAKEY2_KEY9 _BAKEY2.Bits.KEY9 +#define BAKEY2_KEY10 _BAKEY2.Bits.KEY10 +#define BAKEY2_KEY11 _BAKEY2.Bits.KEY11 +#define BAKEY2_KEY12 _BAKEY2.Bits.KEY12 +#define BAKEY2_KEY13 _BAKEY2.Bits.KEY13 +#define BAKEY2_KEY14 _BAKEY2.Bits.KEY14 +#define BAKEY2_KEY15 _BAKEY2.Bits.KEY15 + +#define BAKEY2_KEY0_MASK 1U +#define BAKEY2_KEY1_MASK 2U +#define BAKEY2_KEY2_MASK 4U +#define BAKEY2_KEY3_MASK 8U +#define BAKEY2_KEY4_MASK 16U +#define BAKEY2_KEY5_MASK 32U +#define BAKEY2_KEY6_MASK 64U +#define BAKEY2_KEY7_MASK 128U +#define BAKEY2_KEY8_MASK 256U +#define BAKEY2_KEY9_MASK 512U +#define BAKEY2_KEY10_MASK 1024U +#define BAKEY2_KEY11_MASK 2048U +#define BAKEY2_KEY12_MASK 4096U +#define BAKEY2_KEY13_MASK 8192U +#define BAKEY2_KEY14_MASK 16384U +#define BAKEY2_KEY15_MASK 32768U + + +/*** BAKEY3 - Backdoor Access Key 3; 0x0000FF06 ***/ +typedef union { + word Word; + struct { + word KEY0 :1; /* Backdoor Access Key bits, bit 0 */ + word KEY1 :1; /* Backdoor Access Key bits, bit 1 */ + word KEY2 :1; /* Backdoor Access Key bits, bit 2 */ + word KEY3 :1; /* Backdoor Access Key bits, bit 3 */ + word KEY4 :1; /* Backdoor Access Key bits, bit 4 */ + word KEY5 :1; /* Backdoor Access Key bits, bit 5 */ + word KEY6 :1; /* Backdoor Access Key bits, bit 6 */ + word KEY7 :1; /* Backdoor Access Key bits, bit 7 */ + word KEY8 :1; /* Backdoor Access Key bits, bit 8 */ + word KEY9 :1; /* Backdoor Access Key bits, bit 9 */ + word KEY10 :1; /* Backdoor Access Key bits, bit 10 */ + word KEY11 :1; /* Backdoor Access Key bits, bit 11 */ + word KEY12 :1; /* Backdoor Access Key bits, bit 12 */ + word KEY13 :1; /* Backdoor Access Key bits, bit 13 */ + word KEY14 :1; /* Backdoor Access Key bits, bit 14 */ + word KEY15 :1; /* Backdoor Access Key bits, bit 15 */ + } Bits; +} BAKEY3STR; +/* Tip for register initialization in the user code: const word BAKEY3_INIT @0x0000FF06 = ; */ +#define _BAKEY3 (*(const BAKEY3STR *)0x0000FF06) +#define BAKEY3 _BAKEY3.Word +#define BAKEY3_KEY0 _BAKEY3.Bits.KEY0 +#define BAKEY3_KEY1 _BAKEY3.Bits.KEY1 +#define BAKEY3_KEY2 _BAKEY3.Bits.KEY2 +#define BAKEY3_KEY3 _BAKEY3.Bits.KEY3 +#define BAKEY3_KEY4 _BAKEY3.Bits.KEY4 +#define BAKEY3_KEY5 _BAKEY3.Bits.KEY5 +#define BAKEY3_KEY6 _BAKEY3.Bits.KEY6 +#define BAKEY3_KEY7 _BAKEY3.Bits.KEY7 +#define BAKEY3_KEY8 _BAKEY3.Bits.KEY8 +#define BAKEY3_KEY9 _BAKEY3.Bits.KEY9 +#define BAKEY3_KEY10 _BAKEY3.Bits.KEY10 +#define BAKEY3_KEY11 _BAKEY3.Bits.KEY11 +#define BAKEY3_KEY12 _BAKEY3.Bits.KEY12 +#define BAKEY3_KEY13 _BAKEY3.Bits.KEY13 +#define BAKEY3_KEY14 _BAKEY3.Bits.KEY14 +#define BAKEY3_KEY15 _BAKEY3.Bits.KEY15 + +#define BAKEY3_KEY0_MASK 1U +#define BAKEY3_KEY1_MASK 2U +#define BAKEY3_KEY2_MASK 4U +#define BAKEY3_KEY3_MASK 8U +#define BAKEY3_KEY4_MASK 16U +#define BAKEY3_KEY5_MASK 32U +#define BAKEY3_KEY6_MASK 64U +#define BAKEY3_KEY7_MASK 128U +#define BAKEY3_KEY8_MASK 256U +#define BAKEY3_KEY9_MASK 512U +#define BAKEY3_KEY10_MASK 1024U +#define BAKEY3_KEY11_MASK 2048U +#define BAKEY3_KEY12_MASK 4096U +#define BAKEY3_KEY13_MASK 8192U +#define BAKEY3_KEY14_MASK 16384U +#define BAKEY3_KEY15_MASK 32768U + + +/*** NVFPROT3 - Non volatile Block 3 Flash Protection Register; 0x0000FF0A ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} NVFPROT3STR; +/* Tip for register initialization in the user code: const byte NVFPROT3_INIT @0x0000FF0A = ; */ +#define _NVFPROT3 (*(const NVFPROT3STR *)0x0000FF0A) +#define NVFPROT3 _NVFPROT3.Byte +#define NVFPROT3_FPLS0 _NVFPROT3.Bits.FPLS0 +#define NVFPROT3_FPLS1 _NVFPROT3.Bits.FPLS1 +#define NVFPROT3_FPLDIS _NVFPROT3.Bits.FPLDIS +#define NVFPROT3_FPHS0 _NVFPROT3.Bits.FPHS0 +#define NVFPROT3_FPHS1 _NVFPROT3.Bits.FPHS1 +#define NVFPROT3_FPHDIS _NVFPROT3.Bits.FPHDIS +#define NVFPROT3_NV6 _NVFPROT3.Bits.NV6 +#define NVFPROT3_FPOPEN _NVFPROT3.Bits.FPOPEN +#define NVFPROT3_FPLS _NVFPROT3.MergedBits.grpFPLS +#define NVFPROT3_FPHS _NVFPROT3.MergedBits.grpFPHS + +#define NVFPROT3_FPLS0_MASK 1U +#define NVFPROT3_FPLS1_MASK 2U +#define NVFPROT3_FPLDIS_MASK 4U +#define NVFPROT3_FPHS0_MASK 8U +#define NVFPROT3_FPHS1_MASK 16U +#define NVFPROT3_FPHDIS_MASK 32U +#define NVFPROT3_NV6_MASK 64U +#define NVFPROT3_FPOPEN_MASK 128U +#define NVFPROT3_FPLS_MASK 3U +#define NVFPROT3_FPLS_BITNUM 0U +#define NVFPROT3_FPHS_MASK 24U +#define NVFPROT3_FPHS_BITNUM 3U + + +/*** NVFPROT2 - Non volatile Block 2 Flash Protection Register; 0x0000FF0B ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} NVFPROT2STR; +/* Tip for register initialization in the user code: const byte NVFPROT2_INIT @0x0000FF0B = ; */ +#define _NVFPROT2 (*(const NVFPROT2STR *)0x0000FF0B) +#define NVFPROT2 _NVFPROT2.Byte +#define NVFPROT2_FPLS0 _NVFPROT2.Bits.FPLS0 +#define NVFPROT2_FPLS1 _NVFPROT2.Bits.FPLS1 +#define NVFPROT2_FPLDIS _NVFPROT2.Bits.FPLDIS +#define NVFPROT2_FPHS0 _NVFPROT2.Bits.FPHS0 +#define NVFPROT2_FPHS1 _NVFPROT2.Bits.FPHS1 +#define NVFPROT2_FPHDIS _NVFPROT2.Bits.FPHDIS +#define NVFPROT2_NV6 _NVFPROT2.Bits.NV6 +#define NVFPROT2_FPOPEN _NVFPROT2.Bits.FPOPEN +#define NVFPROT2_FPLS _NVFPROT2.MergedBits.grpFPLS +#define NVFPROT2_FPHS _NVFPROT2.MergedBits.grpFPHS + +#define NVFPROT2_FPLS0_MASK 1U +#define NVFPROT2_FPLS1_MASK 2U +#define NVFPROT2_FPLDIS_MASK 4U +#define NVFPROT2_FPHS0_MASK 8U +#define NVFPROT2_FPHS1_MASK 16U +#define NVFPROT2_FPHDIS_MASK 32U +#define NVFPROT2_NV6_MASK 64U +#define NVFPROT2_FPOPEN_MASK 128U +#define NVFPROT2_FPLS_MASK 3U +#define NVFPROT2_FPLS_BITNUM 0U +#define NVFPROT2_FPHS_MASK 24U +#define NVFPROT2_FPHS_BITNUM 3U + + +/*** NVFPROT1 - Non volatile Block 1 Flash Protection Register; 0x0000FF0C ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} NVFPROT1STR; +/* Tip for register initialization in the user code: const byte NVFPROT1_INIT @0x0000FF0C = ; */ +#define _NVFPROT1 (*(const NVFPROT1STR *)0x0000FF0C) +#define NVFPROT1 _NVFPROT1.Byte +#define NVFPROT1_FPLS0 _NVFPROT1.Bits.FPLS0 +#define NVFPROT1_FPLS1 _NVFPROT1.Bits.FPLS1 +#define NVFPROT1_FPLDIS _NVFPROT1.Bits.FPLDIS +#define NVFPROT1_FPHS0 _NVFPROT1.Bits.FPHS0 +#define NVFPROT1_FPHS1 _NVFPROT1.Bits.FPHS1 +#define NVFPROT1_FPHDIS _NVFPROT1.Bits.FPHDIS +#define NVFPROT1_NV6 _NVFPROT1.Bits.NV6 +#define NVFPROT1_FPOPEN _NVFPROT1.Bits.FPOPEN +#define NVFPROT1_FPLS _NVFPROT1.MergedBits.grpFPLS +#define NVFPROT1_FPHS _NVFPROT1.MergedBits.grpFPHS + +#define NVFPROT1_FPLS0_MASK 1U +#define NVFPROT1_FPLS1_MASK 2U +#define NVFPROT1_FPLDIS_MASK 4U +#define NVFPROT1_FPHS0_MASK 8U +#define NVFPROT1_FPHS1_MASK 16U +#define NVFPROT1_FPHDIS_MASK 32U +#define NVFPROT1_NV6_MASK 64U +#define NVFPROT1_FPOPEN_MASK 128U +#define NVFPROT1_FPLS_MASK 3U +#define NVFPROT1_FPLS_BITNUM 0U +#define NVFPROT1_FPHS_MASK 24U +#define NVFPROT1_FPHS_BITNUM 3U + + +/*** NVFPROT0 - Non volatile Block 0 Flash Protection Register; 0x0000FF0D ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} NVFPROT0STR; +/* Tip for register initialization in the user code: const byte NVFPROT0_INIT @0x0000FF0D = ; */ +#define _NVFPROT0 (*(const NVFPROT0STR *)0x0000FF0D) +#define NVFPROT0 _NVFPROT0.Byte +#define NVFPROT0_FPLS0 _NVFPROT0.Bits.FPLS0 +#define NVFPROT0_FPLS1 _NVFPROT0.Bits.FPLS1 +#define NVFPROT0_FPLDIS _NVFPROT0.Bits.FPLDIS +#define NVFPROT0_FPHS0 _NVFPROT0.Bits.FPHS0 +#define NVFPROT0_FPHS1 _NVFPROT0.Bits.FPHS1 +#define NVFPROT0_FPHDIS _NVFPROT0.Bits.FPHDIS +#define NVFPROT0_NV6 _NVFPROT0.Bits.NV6 +#define NVFPROT0_FPOPEN _NVFPROT0.Bits.FPOPEN +#define NVFPROT0_FPLS _NVFPROT0.MergedBits.grpFPLS +#define NVFPROT0_FPHS _NVFPROT0.MergedBits.grpFPHS + +#define NVFPROT0_FPLS0_MASK 1U +#define NVFPROT0_FPLS1_MASK 2U +#define NVFPROT0_FPLDIS_MASK 4U +#define NVFPROT0_FPHS0_MASK 8U +#define NVFPROT0_FPHS1_MASK 16U +#define NVFPROT0_FPHDIS_MASK 32U +#define NVFPROT0_NV6_MASK 64U +#define NVFPROT0_FPOPEN_MASK 128U +#define NVFPROT0_FPLS_MASK 3U +#define NVFPROT0_FPLS_BITNUM 0U +#define NVFPROT0_FPHS_MASK 24U +#define NVFPROT0_FPHS_BITNUM 3U + + +/*** NVFSEC - Non volatile Flash Security Register; 0x0000FF0F ***/ +typedef union { + byte Byte; + struct { + byte SEC0 :1; /* Memory security bit 0 */ + byte SEC1 :1; /* Memory security bit 1 */ + byte NV2 :1; /* Non Volatile flag bit 2 */ + byte NV3 :1; /* Non Volatile flag bit 3 */ + byte NV4 :1; /* Non Volatile flag bit 4 */ + byte NV5 :1; /* Non Volatile flag bit 5 */ + byte KEYEN0 :1; /* Backdoor Key Security Enable Bit 0 */ + byte KEYEN1 :1; /* Backdoor Key Security Enable Bit 1 */ + } Bits; + struct { + byte grpSEC :2; + byte grpNV_2 :4; + byte grpKEYEN :2; + } MergedBits; +} NVFSECSTR; +/* Tip for register initialization in the user code: const byte NVFSEC_INIT @0x0000FF0F = ; */ +#define _NVFSEC (*(const NVFSECSTR *)0x0000FF0F) +#define NVFSEC _NVFSEC.Byte +#define NVFSEC_SEC0 _NVFSEC.Bits.SEC0 +#define NVFSEC_SEC1 _NVFSEC.Bits.SEC1 +#define NVFSEC_NV2 _NVFSEC.Bits.NV2 +#define NVFSEC_NV3 _NVFSEC.Bits.NV3 +#define NVFSEC_NV4 _NVFSEC.Bits.NV4 +#define NVFSEC_NV5 _NVFSEC.Bits.NV5 +#define NVFSEC_KEYEN0 _NVFSEC.Bits.KEYEN0 +#define NVFSEC_KEYEN1 _NVFSEC.Bits.KEYEN1 +#define NVFSEC_SEC _NVFSEC.MergedBits.grpSEC +#define NVFSEC_NV_2 _NVFSEC.MergedBits.grpNV_2 +#define NVFSEC_KEYEN _NVFSEC.MergedBits.grpKEYEN +#define NVFSEC_NV NVFSEC_NV_2 + +#define NVFSEC_SEC0_MASK 1U +#define NVFSEC_SEC1_MASK 2U +#define NVFSEC_NV2_MASK 4U +#define NVFSEC_NV3_MASK 8U +#define NVFSEC_NV4_MASK 16U +#define NVFSEC_NV5_MASK 32U +#define NVFSEC_KEYEN0_MASK 64U +#define NVFSEC_KEYEN1_MASK 128U +#define NVFSEC_SEC_MASK 3U +#define NVFSEC_SEC_BITNUM 0U +#define NVFSEC_NV_2_MASK 60U +#define NVFSEC_NV_2_BITNUM 2U +#define NVFSEC_KEYEN_MASK 192U +#define NVFSEC_KEYEN_BITNUM 6U + + + /* Watchdog reset macro */ +#ifndef __RESET_WATCHDOG +#ifdef _lint + #define __RESET_WATCHDOG() /* empty */ +#else + #define __RESET_WATCHDOG() (void)(ARMCOP = 0x55U, ARMCOP = 0xAAU) +#endif +#endif /* __RESET_WATCHDOG */ + + +/***********************************************/ +/** D E P R E C I A T E D S Y M B O L S **/ +/***********************************************/ +/* --------------------------------------------------------------------------- */ +/* The following symbols were removed, because they were invalid or irrelevant */ +/* --------------------------------------------------------------------------- */ +#define MCCNTlo_BIT0 This_symb_has_been_depreciated +#define MCCNTlo_BIT1 This_symb_has_been_depreciated +#define MCCNTlo_BIT2 This_symb_has_been_depreciated +#define MCCNTlo_BIT3 This_symb_has_been_depreciated +#define MCCNTlo_BIT4 This_symb_has_been_depreciated +#define MCCNTlo_BIT5 This_symb_has_been_depreciated +#define MCCNTlo_BIT6 This_symb_has_been_depreciated +#define MCCNTlo_BIT7 This_symb_has_been_depreciated +#define MCCNThi_BIT8 This_symb_has_been_depreciated +#define MCCNThi_BIT9 This_symb_has_been_depreciated +#define MCCNThi_BIT10 This_symb_has_been_depreciated +#define MCCNThi_BIT11 This_symb_has_been_depreciated +#define MCCNThi_BIT12 This_symb_has_been_depreciated +#define MCCNThi_BIT13 This_symb_has_been_depreciated +#define MCCNThi_BIT14 This_symb_has_been_depreciated +#define MCCNThi_BIT15 This_symb_has_been_depreciated +#define MCCNTlo_BIT0_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT1_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT2_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT3_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT4_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT5_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT6_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT7_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT8_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT9_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT10_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT11_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT12_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT13_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT14_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT15_MASK This_symb_has_been_depreciated + + +#ifndef __V30COMPATIBLE__ +#pragma OPTION DEL V30toV31Compatible +#endif +/*lint -restore +esym(961,18.4) +esym(961,19.7) Enable MISRA rule (1.1,18.4,6.4,19.7) checking. */ + +#endif diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/main.c b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/main.c new file mode 100644 index 00000000..41b3267c --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Boot/main.c @@ -0,0 +1,136 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Boot\main.c +* \brief Bootloader application source file. +* \ingroup Boot_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "derivative.h" /* MCU registers */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static void Init(void); + + +/************************************************************************************//** +** \brief This is the entry point for the bootloader application and is called +** by the reset interrupt vector after the C-startup routines executed. +** \return none. +** +****************************************************************************************/ +void main(void) +{ + /* ##Vg TODO basic bootloader works, including the timed backdoor. next steps: + * - bootloader activation from user program + * - support for CAN + */ + + /* initialize the microcontroller */ + Init(); + + /* initialize the bootloader */ + BootInit(); + + /* start the infinite program loop */ + while (1) + { + /* run the bootloader task */ + BootTask(); + } +} /*** end of main ***/ + + +/************************************************************************************//** +** \brief Initializes the microcontroller. +** \return none. +** +****************************************************************************************/ +static void Init(void) +{ + blt_int8u synrCnt; + blt_int8u refdvCnt; + blt_int32u systemSpeed; + blt_bool found = BLT_FALSE; + + /* disable the global interrupts. the bootloader does not use interrupts and this + * automatically prevents a jump back into the user program in case it was not + * properly uninitialized. + */ + asm("sei"); + /* initialize the system clock to BOOT_CPU_SYSTEM_SPEED_KHZ by configuring the PLL + * subsystem. first default to oscillator clock source. + */ + CLKSEL &= ~0x80; + /* search for the synthesizer and reference divider values. the equation to use is: + * PLLCLK = EXTCLK * ( (synrCnt + 1) / (refdvCnt + 1) ), with synrCnt can be from + * 0..63 and refdvCnt can be from 0..15 + */ + for (refdvCnt = 0; refdvCnt <= 15; refdvCnt++) + { + for (synrCnt = 0; synrCnt <= 63; synrCnt++) + { + /* calculate the system speed with these SYNR and REFDV settings */ + systemSpeed = ((blt_int32u)BOOT_CPU_XTAL_SPEED_KHZ * (synrCnt+1)) / (refdvCnt+1); + /* was a match found? */ + if (systemSpeed == BOOT_CPU_SYSTEM_SPEED_KHZ) + { + /* flag success */ + found = BLT_TRUE; + /* break loop */ + break; + } + } + if (found == BLT_TRUE) + { + /* break this loop as well if a match was already found */ + break; + } + } + /* flag error if no match was found */ + ASSERT_RT(found == BLT_TRUE); + /* set the synthesizer and reference divider values */ + SYNR = synrCnt; + REFDV = refdvCnt; + /* wait for PLL to lock */ + while((CRGFLG & 0x08) == 0) + { + ; + } + /* select PLL as clock source */ + CLKSEL |= 0x80; +} /*** end of Init ***/ + + +/*********************************** end of main.c *************************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/bin/demoprog_evbplus_dragon12p.abs b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/bin/demoprog_evbplus_dragon12p.abs new file mode 100644 index 0000000000000000000000000000000000000000..e41250478d89266e1012c09b54bf32d54606154c GIT binary patch literal 207573 zcmeFa2Yi&((g(cHp525VAQ(_oK&6UEAoQ9FfdoPlswg$|8j4^Aq^R^FMd_$i0TBcN zHBmuDihvCflqRT1Z&JURIdk@z?DKf524|vwB)RZf8}!l@(dGK(*f^Pe=9~;ETEu zsmffqomK60WZAsGM;6Od8FYV?JYR25Ay4SOknF-pU}e?FURB8BN%DB=L}WMGdHY@u5|Ld#Bx@6NHmRYt-FmFq4{;wqp4C1jDalGo81d=2jqxGb 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b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/bin/demoprog_evbplus_dragon12p.map @@ -0,0 +1,1998 @@ +*** EVALUATION *** +PROGRAM "C:\Work\software\OpenBLT\Target\Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\bin\demoprog_evbplus_dragon12p.abs" + +********************************************************************************************* +TARGET SECTION +--------------------------------------------------------------------------------------------- +Processor : Freescale HC12 +Memory Model: SMALL +File Format : ELF\DWARF 2.0 +Linker : SmartLinker V-5.0.40 Build 10203, Jul 23 2010 + +********************************************************************************************* +FILE SECTION +--------------------------------------------------------------------------------------------- +rtshc12.c.o (ansisi.lib) Model: SMALL, Lang: ANSI-C +mc9s12dg256.c.o Model: SMALL, Lang: ANSI-C +boot.c.o Model: SMALL, Lang: ANSI-C +irq.c.o Model: SMALL, Lang: ANSI-C +led.c.o Model: SMALL, Lang: ANSI-C +main.c.o Model: SMALL, Lang: ANSI-C +start12.c.o Model: SMALL, Lang: ANSI-C +time.c.o Model: SMALL, Lang: ANSI-C +vectors.c.o Model: SMALL, Lang: ANSI-C + +********************************************************************************************* +STARTUP SECTION +--------------------------------------------------------------------------------------------- +Entry point: 0xC029 (_Startup) +_startupData is allocated at 0xC031 and uses 6 Bytes +extern struct _tagStartup { + unsigned nofZeroOut 1 + _Range pZeroOut 0x1100 76 + _Copy *toCopyDownBeg 0xC1AC +} _startupData; + +********************************************************************************************* +SECTION-ALLOCATION SECTION +Section Name Size Type From To Segment +--------------------------------------------------------------------------------------------- +.init 49 R 0xC000 0xC030 ROM_C000 +.startData 10 R 0xC031 0xC03A ROM_C000 +.text 339 R 0xC03B 0xC18D ROM_C000 +.copy 2 R 0xC1AC 0xC1AD ROM_C000 +.stack 256 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+.abs_section_2a7 1 N/I 0x2A7 0x2A7 .absSeg262 +.abs_section_2a8 1 N/I 0x2A8 0x2A8 .absSeg263 +.abs_section_2a9 1 N/I 0x2A9 0x2A9 .absSeg264 +.abs_section_2aa 1 N/I 0x2AA 0x2AA .absSeg265 +.abs_section_2ab 1 N/I 0x2AB 0x2AB .absSeg266 +.abs_section_2ac 1 N/I 0x2AC 0x2AC .absSeg267 +.abs_section_2b0 1 N/I 0x2B0 0x2B0 .absSeg268 +.abs_section_2b1 1 N/I 0x2B1 0x2B1 .absSeg269 +.abs_section_2b2 1 N/I 0x2B2 0x2B2 .absSeg270 +.abs_section_2b3 1 N/I 0x2B3 0x2B3 .absSeg271 +.abs_section_2b4 1 N/I 0x2B4 0x2B4 .absSeg272 +.abs_section_2b5 1 N/I 0x2B5 0x2B5 .absSeg273 +.abs_section_2b6 1 N/I 0x2B6 0x2B6 .absSeg274 +.abs_section_2b7 1 N/I 0x2B7 0x2B7 .absSeg275 +.abs_section_2b8 1 N/I 0x2B8 0x2B8 .absSeg276 +.abs_section_2b9 1 N/I 0x2B9 0x2B9 .absSeg277 +.abs_section_2ba 1 N/I 0x2BA 0x2BA .absSeg278 +.abs_section_2bb 1 N/I 0x2BB 0x2BB .absSeg279 +.abs_section_2bc 1 N/I 0x2BC 0x2BC .absSeg280 +.abs_section_2bd 1 N/I 0x2BD 0x2BD .absSeg281 +.abs_section_0 2 N/I 0x0 0x1 .absSeg282 +.abs_section_2 2 N/I 0x2 0x3 .absSeg283 +.abs_section_1a 2 N/I 0x1A 0x1B .absSeg284 +.abs_section_44 2 N/I 0x44 0x45 .absSeg285 +.abs_section_50 2 N/I 0x50 0x51 .absSeg286 +.abs_section_52 2 N/I 0x52 0x53 .absSeg287 +.abs_section_54 2 N/I 0x54 0x55 .absSeg288 +.abs_section_56 2 N/I 0x56 0x57 .absSeg289 +.abs_section_58 2 N/I 0x58 0x59 .absSeg290 +.abs_section_5a 2 N/I 0x5A 0x5B .absSeg291 +.abs_section_5c 2 N/I 0x5C 0x5D .absSeg292 +.abs_section_5e 2 N/I 0x5E 0x5F .absSeg293 +.abs_section_62 2 N/I 0x62 0x63 .absSeg294 +.abs_section_64 2 N/I 0x64 0x65 .absSeg295 +.abs_section_72 2 N/I 0x72 0x73 .absSeg296 +.abs_section_74 2 N/I 0x74 0x75 .absSeg297 +.abs_section_76 2 N/I 0x76 0x77 .absSeg298 +.abs_section_78 2 N/I 0x78 0x79 .absSeg299 +.abs_section_7a 2 N/I 0x7A 0x7B .absSeg300 +.abs_section_7c 2 N/I 0x7C 0x7D .absSeg301 +.abs_section_7e 2 N/I 0x7E 0x7F .absSeg302 +.abs_section_82 2 N/I 0x82 0x83 .absSeg303 +.abs_section_84 2 N/I 0x84 0x85 .absSeg304 +.abs_section_90 2 N/I 0x90 0x91 .absSeg305 +.abs_section_92 2 N/I 0x92 0x93 .absSeg306 +.abs_section_94 2 N/I 0x94 0x95 .absSeg307 +.abs_section_96 2 N/I 0x96 0x97 .absSeg308 +.abs_section_98 2 N/I 0x98 0x99 .absSeg309 +.abs_section_9a 2 N/I 0x9A 0x9B .absSeg310 +.abs_section_9c 2 N/I 0x9C 0x9D .absSeg311 +.abs_section_9e 2 N/I 0x9E 0x9F .absSeg312 +.abs_section_ac 2 N/I 0xAC 0xAD .absSeg313 +.abs_section_ae 2 N/I 0xAE 0xAF .absSeg314 +.abs_section_b0 2 N/I 0xB0 0xB1 .absSeg315 +.abs_section_b2 2 N/I 0xB2 0xB3 .absSeg316 +.abs_section_b4 2 N/I 0xB4 0xB5 .absSeg317 +.abs_section_b6 2 N/I 0xB6 0xB7 .absSeg318 +.abs_section_b8 2 N/I 0xB8 0xB9 .absSeg319 +.abs_section_ba 2 N/I 0xBA 0xBB .absSeg320 +.abs_section_bc 2 N/I 0xBC 0xBD .absSeg321 +.abs_section_be 2 N/I 0xBE 0xBF .absSeg322 +.abs_section_c0 2 N/I 0xC0 0xC1 .absSeg323 +.abs_section_c2 2 N/I 0xC2 0xC3 .absSeg324 +.abs_section_c8 2 N/I 0xC8 0xC9 .absSeg325 +.abs_section_d0 2 N/I 0xD0 0xD1 .absSeg326 +.abs_section_122 2 N/I 0x122 0x123 .absSeg327 +.abs_section_124 2 N/I 0x124 0x125 .absSeg328 +.abs_section_130 2 N/I 0x130 0x131 .absSeg329 +.abs_section_132 2 N/I 0x132 0x133 .absSeg330 +.abs_section_134 2 N/I 0x134 0x135 .absSeg331 +.abs_section_136 2 N/I 0x136 0x137 .absSeg332 +.abs_section_138 2 N/I 0x138 0x139 .absSeg333 +.abs_section_13a 2 N/I 0x13A 0x13B .absSeg334 +.abs_section_13c 2 N/I 0x13C 0x13D .absSeg335 +.abs_section_13e 2 N/I 0x13E 0x13F .absSeg336 +.abs_section_16e 2 N/I 0x16E 0x16F .absSeg337 +.abs_section_17e 2 N/I 0x17E 0x17F .absSeg338 +.abs_section_2ae 2 N/I 0x2AE 0x2AF .absSeg339 +.abs_section_2be 2 N/I 0x2BE 0x2BF .absSeg340 +.abs_section_e77e 130 R 0xE77E 0xE7FF .absSeg341 +.bss 76 R/W 0x1100 0x114B RAM +RUNTIME 30 R 0xC18E 0xC1AB ROM_C000 + +Summary of section sizes per section type: +READ_ONLY (R): 230 (dec: 560) +READ_WRITE (R/W): 14C (dec: 332) +NO_INIT (N/I): 190 (dec: 400) + +********************************************************************************************* +VECTOR-ALLOCATION SECTION + Address InitValue InitFunction +--------------------------------------------------------------------------------------------- + +********************************************************************************************* +OBJECT-ALLOCATION SECTION + Name Module Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- +MODULE: -- rtshc12.c.o (ansisi.lib) -- +- PROCEDURES: + _LCMP C18E 19 25 1 RUNTIME + _LINC C1A7 5 5 1 RUNTIME +- VARIABLES: +MODULE: -- mc9s12dg256.c.o -- +- PROCEDURES: +- VARIABLES: + _PORTE 8 1 1 0 .abs_section_8 + _DDRE 9 1 1 0 .abs_section_9 + _PEAR A 1 1 0 .abs_section_a + _MODE B 1 1 0 .abs_section_b + _PUCR C 1 1 0 .abs_section_c + _RDRIV D 1 1 0 .abs_section_d + _EBICTL E 1 1 0 .abs_section_e + _INITRM 10 1 1 0 .abs_section_10 + _INITRG 11 1 1 0 .abs_section_11 + _INITEE 12 1 1 0 .abs_section_12 + _MISC 13 1 1 0 .abs_section_13 + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _INTCR 1E 1 1 0 .abs_section_1e + _HPRIO 1F 1 1 0 .abs_section_1f + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP1X 2D 1 1 0 .abs_section_2d + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _PPAGE 30 1 1 0 .abs_section_30 + _PORTK 32 1 1 0 .abs_section_32 + _DDRK 33 1 1 0 .abs_section_33 + _SYNR 34 1 1 0 .abs_section_34 + _REFDV 35 1 1 0 .abs_section_35 + _CRGFLG 37 1 1 0 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CLKSEL 39 1 1 0 .abs_section_39 + _PLLCTL 3A 1 1 0 .abs_section_3a + _RTICTL 3B 1 1 0 .abs_section_3b + _COPCTL 3C 1 1 0 .abs_section_3c + _ARMCOP 3F 1 1 0 .abs_section_3f + _TIOS 40 1 1 2 .abs_section_40 + _CFORC 41 1 1 0 .abs_section_41 + _OC7M 42 1 1 0 .abs_section_42 + _OC7D 43 1 1 0 .abs_section_43 + _TSCR1 46 1 1 2 .abs_section_46 + _TTOV 47 1 1 1 .abs_section_47 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 1 .abs_section_4a + _TCTL4 4B 1 1 1 .abs_section_4b + _TIE 4C 1 1 2 .abs_section_4c + _TSCR2 4D 1 1 1 .abs_section_4d + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _MCCTL 66 1 1 0 .abs_section_66 + _MCFLG 67 1 1 0 .abs_section_67 + _ICPAR 68 1 1 0 .abs_section_68 + _DLYCT 69 1 1 0 .abs_section_69 + _ICOVW 6A 1 1 0 .abs_section_6a + _ICSYS 6B 1 1 0 .abs_section_6b + _PBCTL 70 1 1 0 .abs_section_70 + _PBFLG 71 1 1 0 .abs_section_71 + _ATD0STAT0 86 1 1 0 .abs_section_86 + _ATD0TEST1 89 1 1 0 .abs_section_89 + _ATD0STAT1 8B 1 1 0 .abs_section_8b + _ATD0DIEN 8D 1 1 0 .abs_section_8d + _PORTAD0 8F 1 1 0 .abs_section_8f + _PWME A0 1 1 0 .abs_section_a0 + _PWMPOL A1 1 1 0 .abs_section_a1 + _PWMCLK A2 1 1 0 .abs_section_a2 + _PWMPRCLK A3 1 1 0 .abs_section_a3 + _PWMCAE A4 1 1 0 .abs_section_a4 + _PWMCTL A5 1 1 0 .abs_section_a5 + _PWMSCLA A8 1 1 0 .abs_section_a8 + _PWMSCLB A9 1 1 0 .abs_section_a9 + _PWMSDN C4 1 1 0 .abs_section_c4 + _SCI0CR1 CA 1 1 1 .abs_section_ca + _SCI0CR2 CB 1 1 2 .abs_section_cb + _SCI0SR1 CC 1 1 1 .abs_section_cc + _SCI0SR2 CD 1 1 0 .abs_section_cd + _SCI0DRH CE 1 1 0 .abs_section_ce + _SCI0DRL CF 1 1 1 .abs_section_cf + _SCI1CR1 D2 1 1 0 .abs_section_d2 + _SCI1CR2 D3 1 1 0 .abs_section_d3 + _SCI1SR1 D4 1 1 0 .abs_section_d4 + _SCI1SR2 D5 1 1 0 .abs_section_d5 + _SCI1DRH D6 1 1 0 .abs_section_d6 + _SCI1DRL D7 1 1 0 .abs_section_d7 + _SPI0CR1 D8 1 1 0 .abs_section_d8 + _SPI0CR2 D9 1 1 0 .abs_section_d9 + _SPI0BR DA 1 1 0 .abs_section_da + _SPI0SR DB 1 1 0 .abs_section_db + _SPI0DR DD 1 1 0 .abs_section_dd + _IBAD E0 1 1 0 .abs_section_e0 + _IBFD E1 1 1 0 .abs_section_e1 + _IBCR E2 1 1 0 .abs_section_e2 + _IBSR E3 1 1 0 .abs_section_e3 + _IBDR E4 1 1 0 .abs_section_e4 + _SPI1CR1 F0 1 1 0 .abs_section_f0 + _SPI1CR2 F1 1 1 0 .abs_section_f1 + _SPI1BR F2 1 1 0 .abs_section_f2 + _SPI1SR F3 1 1 0 .abs_section_f3 + _SPI1DR F5 1 1 0 .abs_section_f5 + _SPI2CR1 F8 1 1 0 .abs_section_f8 + _SPI2CR2 F9 1 1 0 .abs_section_f9 + _SPI2BR FA 1 1 0 .abs_section_fa + _SPI2SR FB 1 1 0 .abs_section_fb + _SPI2DR FD 1 1 0 .abs_section_fd + _FCLKDIV 100 1 1 0 .abs_section_100 + _FSEC 101 1 1 0 .abs_section_101 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSTAT 105 1 1 0 .abs_section_105 + _FCMD 106 1 1 0 .abs_section_106 + _ECLKDIV 110 1 1 0 .abs_section_110 + _ECNFG 113 1 1 0 .abs_section_113 + _EPROT 114 1 1 0 .abs_section_114 + _ESTAT 115 1 1 0 .abs_section_115 + _ECMD 116 1 1 0 .abs_section_116 + _ATD1STAT0 126 1 1 0 .abs_section_126 + _ATD1TEST1 129 1 1 0 .abs_section_129 + _ATD1STAT1 12B 1 1 0 .abs_section_12b + _ATD1DIEN 12D 1 1 0 .abs_section_12d + _PORTAD1 12F 1 1 0 .abs_section_12f + _CAN0CTL0 140 1 1 0 .abs_section_140 + _CAN0CTL1 141 1 1 0 .abs_section_141 + _CAN0BTR0 142 1 1 0 .abs_section_142 + _CAN0BTR1 143 1 1 0 .abs_section_143 + _CAN0RFLG 144 1 1 0 .abs_section_144 + _CAN0RIER 145 1 1 0 .abs_section_145 + _CAN0TFLG 146 1 1 0 .abs_section_146 + _CAN0TIER 147 1 1 0 .abs_section_147 + _CAN0TARQ 148 1 1 0 .abs_section_148 + _CAN0TAAK 149 1 1 0 .abs_section_149 + _CAN0TBSEL 14A 1 1 0 .abs_section_14a + _CAN0IDAC 14B 1 1 0 .abs_section_14b + _CAN0RXERR 14E 1 1 0 .abs_section_14e + _CAN0TXERR 14F 1 1 0 .abs_section_14f + _CAN0IDAR0 150 1 1 0 .abs_section_150 + _CAN0IDAR1 151 1 1 0 .abs_section_151 + _CAN0IDAR2 152 1 1 0 .abs_section_152 + _CAN0IDAR3 153 1 1 0 .abs_section_153 + _CAN0IDMR0 154 1 1 0 .abs_section_154 + _CAN0IDMR1 155 1 1 0 .abs_section_155 + _CAN0IDMR2 156 1 1 0 .abs_section_156 + _CAN0IDMR3 157 1 1 0 .abs_section_157 + _CAN0IDAR4 158 1 1 0 .abs_section_158 + _CAN0IDAR5 159 1 1 0 .abs_section_159 + _CAN0IDAR6 15A 1 1 0 .abs_section_15a + _CAN0IDAR7 15B 1 1 0 .abs_section_15b + _CAN0IDMR4 15C 1 1 0 .abs_section_15c + _CAN0IDMR5 15D 1 1 0 .abs_section_15d + _CAN0IDMR6 15E 1 1 0 .abs_section_15e + _CAN0IDMR7 15F 1 1 0 .abs_section_15f + _CAN0RXIDR0 160 1 1 0 .abs_section_160 + _CAN0RXIDR1 161 1 1 0 .abs_section_161 + _CAN0RXIDR2 162 1 1 0 .abs_section_162 + _CAN0RXIDR3 163 1 1 0 .abs_section_163 + _CAN0RXDSR0 164 1 1 0 .abs_section_164 + _CAN0RXDSR1 165 1 1 0 .abs_section_165 + _CAN0RXDSR2 166 1 1 0 .abs_section_166 + _CAN0RXDSR3 167 1 1 0 .abs_section_167 + _CAN0RXDSR4 168 1 1 0 .abs_section_168 + _CAN0RXDSR5 169 1 1 0 .abs_section_169 + _CAN0RXDSR6 16A 1 1 0 .abs_section_16a + _CAN0RXDSR7 16B 1 1 0 .abs_section_16b + _CAN0RXDLR 16C 1 1 0 .abs_section_16c + _CAN0TXIDR0 170 1 1 0 .abs_section_170 + _CAN0TXIDR1 171 1 1 0 .abs_section_171 + _CAN0TXIDR2 172 1 1 0 .abs_section_172 + _CAN0TXIDR3 173 1 1 0 .abs_section_173 + _CAN0TXDSR0 174 1 1 0 .abs_section_174 + _CAN0TXDSR1 175 1 1 0 .abs_section_175 + _CAN0TXDSR2 176 1 1 0 .abs_section_176 + _CAN0TXDSR3 177 1 1 0 .abs_section_177 + _CAN0TXDSR4 178 1 1 0 .abs_section_178 + _CAN0TXDSR5 179 1 1 0 .abs_section_179 + _CAN0TXDSR6 17A 1 1 0 .abs_section_17a + _CAN0TXDSR7 17B 1 1 0 .abs_section_17b + _CAN0TXDLR 17C 1 1 0 .abs_section_17c + _CAN0TXTBPR 17D 1 1 0 .abs_section_17d + _PTT 240 1 1 0 .abs_section_240 + _PTIT 241 1 1 0 .abs_section_241 + _DDRT 242 1 1 0 .abs_section_242 + _RDRT 243 1 1 0 .abs_section_243 + _PERT 244 1 1 0 .abs_section_244 + _PPST 245 1 1 0 .abs_section_245 + _PTS 248 1 1 0 .abs_section_248 + _PTIS 249 1 1 0 .abs_section_249 + _DDRS 24A 1 1 0 .abs_section_24a + _RDRS 24B 1 1 0 .abs_section_24b + _PERS 24C 1 1 0 .abs_section_24c + _PPSS 24D 1 1 0 .abs_section_24d + _WOMS 24E 1 1 0 .abs_section_24e + _PTM 250 1 1 0 .abs_section_250 + _PTIM 251 1 1 0 .abs_section_251 + _DDRM 252 1 1 0 .abs_section_252 + _RDRM 253 1 1 0 .abs_section_253 + _PERM 254 1 1 0 .abs_section_254 + _PPSM 255 1 1 0 .abs_section_255 + _WOMM 256 1 1 0 .abs_section_256 + _MODRR 257 1 1 0 .abs_section_257 + _PTP 258 1 1 0 .abs_section_258 + _PTIP 259 1 1 0 .abs_section_259 + _DDRP 25A 1 1 0 .abs_section_25a + _RDRP 25B 1 1 0 .abs_section_25b + _PERP 25C 1 1 0 .abs_section_25c + _PPSP 25D 1 1 0 .abs_section_25d + _PIEP 25E 1 1 0 .abs_section_25e + _PIFP 25F 1 1 0 .abs_section_25f + _PTH 260 1 1 0 .abs_section_260 + _PTIH 261 1 1 0 .abs_section_261 + _DDRH 262 1 1 0 .abs_section_262 + _RDRH 263 1 1 0 .abs_section_263 + _PERH 264 1 1 0 .abs_section_264 + _PPSH 265 1 1 0 .abs_section_265 + _PIEH 266 1 1 0 .abs_section_266 + _PIFH 267 1 1 0 .abs_section_267 + _PTJ 268 1 1 1 .abs_section_268 + _PTIJ 269 1 1 0 .abs_section_269 + _DDRJ 26A 1 1 1 .abs_section_26a + _RDRJ 26B 1 1 0 .abs_section_26b + _PERJ 26C 1 1 0 .abs_section_26c + _PPSJ 26D 1 1 0 .abs_section_26d + _PIEJ 26E 1 1 0 .abs_section_26e + _PIFJ 26F 1 1 0 .abs_section_26f + _CAN4CTL0 280 1 1 0 .abs_section_280 + _CAN4CTL1 281 1 1 0 .abs_section_281 + _CAN4BTR0 282 1 1 0 .abs_section_282 + _CAN4BTR1 283 1 1 0 .abs_section_283 + _CAN4RFLG 284 1 1 0 .abs_section_284 + _CAN4RIER 285 1 1 0 .abs_section_285 + _CAN4TFLG 286 1 1 0 .abs_section_286 + _CAN4TIER 287 1 1 0 .abs_section_287 + _CAN4TARQ 288 1 1 0 .abs_section_288 + _CAN4TAAK 289 1 1 0 .abs_section_289 + _CAN4TBSEL 28A 1 1 0 .abs_section_28a + _CAN4IDAC 28B 1 1 0 .abs_section_28b + _CAN4RXERR 28E 1 1 0 .abs_section_28e + _CAN4TXERR 28F 1 1 0 .abs_section_28f + _CAN4IDAR0 290 1 1 0 .abs_section_290 + _CAN4IDAR1 291 1 1 0 .abs_section_291 + _CAN4IDAR2 292 1 1 0 .abs_section_292 + _CAN4IDAR3 293 1 1 0 .abs_section_293 + _CAN4IDMR0 294 1 1 0 .abs_section_294 + _CAN4IDMR1 295 1 1 0 .abs_section_295 + _CAN4IDMR2 296 1 1 0 .abs_section_296 + _CAN4IDMR3 297 1 1 0 .abs_section_297 + _CAN4IDAR4 298 1 1 0 .abs_section_298 + _CAN4IDAR5 299 1 1 0 .abs_section_299 + _CAN4IDAR6 29A 1 1 0 .abs_section_29a + _CAN4IDAR7 29B 1 1 0 .abs_section_29b + _CAN4IDMR4 29C 1 1 0 .abs_section_29c + _CAN4IDMR5 29D 1 1 0 .abs_section_29d + _CAN4IDMR6 29E 1 1 0 .abs_section_29e + _CAN4IDMR7 29F 1 1 0 .abs_section_29f + _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 + _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 + _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 + _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 + _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 + _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 + _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 + _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 + _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 + _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 + _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa + _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab + _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac + _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 + _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 + _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 + _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 + _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 + _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 + _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 + _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 + _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 + _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 + _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba + _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb + _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc + _CAN4TXTBPR 2BD 1 1 0 .abs_section_2bd + _PORTAB 0 2 2 3 .abs_section_0 + _DDRAB 2 2 2 1 .abs_section_2 + _PARTID 1A 2 2 0 .abs_section_1a + _TCNT 44 2 2 1 .abs_section_44 + _TC0 50 2 2 3 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 0 .abs_section_5e + _PACN32 62 2 2 0 .abs_section_62 + _PACN10 64 2 2 0 .abs_section_64 + _PA32H 72 2 2 0 .abs_section_72 + _PA10H 74 2 2 0 .abs_section_74 + _MCCNT 76 2 2 0 .abs_section_76 + _TC0H 78 2 2 0 .abs_section_78 + _TC1H 7A 2 2 0 .abs_section_7a + _TC2H 7C 2 2 0 .abs_section_7c + _TC3H 7E 2 2 0 .abs_section_7e + _ATD0CTL23 82 2 2 0 .abs_section_82 + _ATD0CTL45 84 2 2 0 .abs_section_84 + _ATD0DR0 90 2 2 0 .abs_section_90 + _ATD0DR1 92 2 2 0 .abs_section_92 + _ATD0DR2 94 2 2 0 .abs_section_94 + _ATD0DR3 96 2 2 0 .abs_section_96 + _ATD0DR4 98 2 2 0 .abs_section_98 + _ATD0DR5 9A 2 2 0 .abs_section_9a + _ATD0DR6 9C 2 2 0 .abs_section_9c + _ATD0DR7 9E 2 2 0 .abs_section_9e + _PWMCNT01 AC 2 2 0 .abs_section_ac + _PWMCNT23 AE 2 2 0 .abs_section_ae + _PWMCNT45 B0 2 2 0 .abs_section_b0 + _PWMCNT67 B2 2 2 0 .abs_section_b2 + _PWMPER01 B4 2 2 0 .abs_section_b4 + _PWMPER23 B6 2 2 0 .abs_section_b6 + _PWMPER45 B8 2 2 0 .abs_section_b8 + _PWMPER67 BA 2 2 0 .abs_section_ba + _PWMDTY01 BC 2 2 0 .abs_section_bc + _PWMDTY23 BE 2 2 0 .abs_section_be + _PWMDTY45 C0 2 2 0 .abs_section_c0 + _PWMDTY67 C2 2 2 0 .abs_section_c2 + _SCI0BD C8 2 2 4 .abs_section_c8 + _SCI1BD D0 2 2 0 .abs_section_d0 + _ATD1CTL23 122 2 2 0 .abs_section_122 + _ATD1CTL45 124 2 2 0 .abs_section_124 + _ATD1DR0 130 2 2 0 .abs_section_130 + _ATD1DR1 132 2 2 0 .abs_section_132 + _ATD1DR2 134 2 2 0 .abs_section_134 + _ATD1DR3 136 2 2 0 .abs_section_136 + _ATD1DR4 138 2 2 0 .abs_section_138 + _ATD1DR5 13A 2 2 0 .abs_section_13a + _ATD1DR6 13C 2 2 0 .abs_section_13c + _ATD1DR7 13E 2 2 0 .abs_section_13e + _CAN0RXTSR 16E 2 2 0 .abs_section_16e + _CAN0TXTSR 17E 2 2 0 .abs_section_17e + _CAN4RXTSR 2AE 2 2 0 .abs_section_2ae + _CAN4TXTSR 2BE 2 2 0 .abs_section_2be +MODULE: -- boot.c.o -- +- PROCEDURES: + BootActivate C03B F 15 1 .text + BootComInit C04A 19 25 1 .text + BootComCheckActivationRequest C063 44 68 1 .text + UartReceiveByte C0A7 11 17 2 .text +- VARIABLES: + xcpCtoRxInProgress.3 1100 1 1 3 .bss + xcpCtoReqPacket.1 1101 41 65 5 .bss + xcpCtoRxLength.2 1142 1 1 4 .bss +MODULE: -- irq.c.o -- +- PROCEDURES: + IrqInterruptEnable C0B8 3 3 1 .text +- VARIABLES: +MODULE: -- led.c.o -- +- PROCEDURES: + LedInit C0BB F 15 1 .text + LedToggle C0CA 48 72 1 .text +- VARIABLES: + led_toggle_state.1 1143 1 1 3 .bss + timer_counter_last.2 1144 4 4 5 .bss +MODULE: -- main.c.o -- +- PROCEDURES: + main C112 E 14 1 .text + Init C120 9 9 1 .text +- VARIABLES: +MODULE: -- start12.c.o -- +- PROCEDURES: + Init C000 29 41 1 .init + _Startup C029 8 8 1 .init +- VARIABLES: + _startupData C031 6 6 3 .startData +- LABELS: + __SEG_END_SSTACK 1100 0 0 1 +MODULE: -- time.c.o -- +- PROCEDURES: + TimeInit C129 1E 30 1 .text + TimeDeinit C147 1C 28 2 .text + TimeSet C163 7 7 1 .text + TimeGet C16A 7 7 1 .text + TimeISRHandler C171 1B 27 1 .text +- VARIABLES: + millisecond_counter 1148 4 4 8 .bss +MODULE: -- vectors.c.o -- +- PROCEDURES: + UnusedISR C18C 2 2 62 .text +- VARIABLES: + _vectab E77E 82 130 0 .abs_section_e77e + +********************************************************************************************* +MODULE STATISTIC + Name Data Code Const +--------------------------------------------------------------------------------------------- + rtshc12.c.o (ansisi.lib) 0 30 0 + mc9s12dg256.c.o 400 0 0 + boot.c.o 67 125 0 + irq.c.o 0 3 0 + led.c.o 5 87 0 + main.c.o 0 23 0 + start12.c.o 0 49 0 + time.c.o 4 99 0 + vectors.c.o 0 2 130 + other 256 10 2 + +********************************************************************************************* +SECTION USE IN OBJECT-ALLOCATION SECTION +--------------------------------------------------------------------------------------------- +SECTION: ".text" + BootActivate BootComInit BootComCheckActivationRequest UartReceiveByte + IrqInterruptEnable LedInit LedToggle main Init TimeInit TimeDeinit TimeSet + TimeGet TimeISRHandler UnusedISR +SECTION: ".bss" + xcpCtoRxInProgress.3 xcpCtoReqPacket.1 xcpCtoRxLength.2 led_toggle_state.1 + timer_counter_last.2 millisecond_counter +SECTION: ".init" + Init _Startup +SECTION: "RUNTIME" + _LCMP _LINC +SECTION: ".abs_section_8" + _PORTE +SECTION: ".abs_section_9" + _DDRE +SECTION: ".abs_section_a" + _PEAR +SECTION: ".abs_section_b" + _MODE +SECTION: ".abs_section_c" + _PUCR +SECTION: ".abs_section_d" + _RDRIV +SECTION: ".abs_section_e" + _EBICTL +SECTION: ".abs_section_10" + _INITRM +SECTION: ".abs_section_11" + _INITRG +SECTION: ".abs_section_12" + _INITEE +SECTION: ".abs_section_13" + _MISC +SECTION: ".abs_section_15" + _ITCR +SECTION: ".abs_section_16" + _ITEST +SECTION: ".abs_section_1c" + _MEMSIZ0 +SECTION: ".abs_section_1d" + _MEMSIZ1 +SECTION: ".abs_section_1e" + _INTCR +SECTION: ".abs_section_1f" + _HPRIO +SECTION: ".abs_section_28" + _BKPCT0 +SECTION: ".abs_section_29" + _BKPCT1 +SECTION: ".abs_section_2a" + _BKP0X +SECTION: ".abs_section_2b" + _BKP0H +SECTION: ".abs_section_2c" + _BKP0L +SECTION: ".abs_section_2d" + _BKP1X +SECTION: ".abs_section_2e" + _BKP1H +SECTION: ".abs_section_2f" + _BKP1L +SECTION: ".abs_section_30" + _PPAGE +SECTION: ".abs_section_32" + _PORTK +SECTION: ".abs_section_33" + _DDRK +SECTION: ".abs_section_34" + _SYNR +SECTION: ".abs_section_35" + _REFDV +SECTION: ".abs_section_37" + _CRGFLG +SECTION: ".abs_section_38" + _CRGINT +SECTION: ".abs_section_39" + _CLKSEL +SECTION: ".abs_section_3a" + _PLLCTL +SECTION: ".abs_section_3b" + _RTICTL +SECTION: ".abs_section_3c" + _COPCTL +SECTION: ".abs_section_3f" + _ARMCOP +SECTION: ".abs_section_40" + _TIOS +SECTION: ".abs_section_41" + _CFORC +SECTION: ".abs_section_42" + _OC7M +SECTION: ".abs_section_43" + _OC7D +SECTION: ".abs_section_46" + _TSCR1 +SECTION: ".abs_section_47" + _TTOV +SECTION: ".abs_section_48" + _TCTL1 +SECTION: ".abs_section_49" + _TCTL2 +SECTION: ".abs_section_4a" + _TCTL3 +SECTION: ".abs_section_4b" + _TCTL4 +SECTION: ".abs_section_4c" + _TIE +SECTION: ".abs_section_4d" + _TSCR2 +SECTION: ".abs_section_4e" + _TFLG1 +SECTION: ".abs_section_4f" + _TFLG2 +SECTION: ".abs_section_60" + _PACTL +SECTION: ".abs_section_61" + _PAFLG +SECTION: ".abs_section_66" + _MCCTL +SECTION: ".abs_section_67" + _MCFLG +SECTION: ".abs_section_68" + _ICPAR +SECTION: ".abs_section_69" + _DLYCT +SECTION: ".abs_section_6a" + _ICOVW +SECTION: ".abs_section_6b" + _ICSYS +SECTION: ".abs_section_70" + _PBCTL +SECTION: ".abs_section_71" + _PBFLG +SECTION: ".abs_section_86" + _ATD0STAT0 +SECTION: ".abs_section_89" + _ATD0TEST1 +SECTION: ".abs_section_8b" + _ATD0STAT1 +SECTION: ".abs_section_8d" + _ATD0DIEN +SECTION: ".abs_section_8f" + _PORTAD0 +SECTION: ".abs_section_a0" + _PWME +SECTION: ".abs_section_a1" + _PWMPOL +SECTION: ".abs_section_a2" + _PWMCLK +SECTION: ".abs_section_a3" + _PWMPRCLK +SECTION: ".abs_section_a4" + _PWMCAE +SECTION: ".abs_section_a5" + _PWMCTL +SECTION: ".abs_section_a8" + _PWMSCLA +SECTION: ".abs_section_a9" + _PWMSCLB +SECTION: ".abs_section_c4" + _PWMSDN +SECTION: ".abs_section_ca" + _SCI0CR1 +SECTION: ".abs_section_cb" + _SCI0CR2 +SECTION: ".abs_section_cc" + _SCI0SR1 +SECTION: ".abs_section_cd" + _SCI0SR2 +SECTION: ".abs_section_ce" + _SCI0DRH +SECTION: ".abs_section_cf" + _SCI0DRL +SECTION: ".abs_section_d2" + _SCI1CR1 +SECTION: ".abs_section_d3" + _SCI1CR2 +SECTION: ".abs_section_d4" + _SCI1SR1 +SECTION: ".abs_section_d5" + _SCI1SR2 +SECTION: ".abs_section_d6" + _SCI1DRH +SECTION: ".abs_section_d7" + _SCI1DRL +SECTION: ".abs_section_d8" + _SPI0CR1 +SECTION: ".abs_section_d9" + _SPI0CR2 +SECTION: ".abs_section_da" + _SPI0BR +SECTION: ".abs_section_db" + _SPI0SR +SECTION: ".abs_section_dd" + _SPI0DR +SECTION: ".abs_section_e0" + _IBAD +SECTION: ".abs_section_e1" + _IBFD +SECTION: ".abs_section_e2" + _IBCR +SECTION: ".abs_section_e3" + _IBSR +SECTION: ".abs_section_e4" + _IBDR +SECTION: ".abs_section_f0" + _SPI1CR1 +SECTION: ".abs_section_f1" + _SPI1CR2 +SECTION: ".abs_section_f2" + _SPI1BR +SECTION: ".abs_section_f3" + _SPI1SR +SECTION: ".abs_section_f5" + _SPI1DR +SECTION: ".abs_section_f8" + _SPI2CR1 +SECTION: ".abs_section_f9" + _SPI2CR2 +SECTION: ".abs_section_fa" + _SPI2BR +SECTION: ".abs_section_fb" + _SPI2SR +SECTION: ".abs_section_fd" + _SPI2DR +SECTION: ".abs_section_100" + _FCLKDIV +SECTION: ".abs_section_101" + _FSEC +SECTION: ".abs_section_103" + _FCNFG +SECTION: ".abs_section_104" + _FPROT +SECTION: ".abs_section_105" + _FSTAT +SECTION: ".abs_section_106" + _FCMD +SECTION: ".abs_section_110" + _ECLKDIV +SECTION: ".abs_section_113" + _ECNFG +SECTION: ".abs_section_114" + _EPROT +SECTION: ".abs_section_115" + _ESTAT +SECTION: ".abs_section_116" + _ECMD +SECTION: ".abs_section_126" + _ATD1STAT0 +SECTION: ".abs_section_129" + _ATD1TEST1 +SECTION: ".abs_section_12b" + _ATD1STAT1 +SECTION: ".abs_section_12d" + _ATD1DIEN +SECTION: ".abs_section_12f" + _PORTAD1 +SECTION: ".abs_section_140" + _CAN0CTL0 +SECTION: ".abs_section_141" + _CAN0CTL1 +SECTION: ".abs_section_142" + _CAN0BTR0 +SECTION: ".abs_section_143" + _CAN0BTR1 +SECTION: ".abs_section_144" + _CAN0RFLG +SECTION: ".abs_section_145" + _CAN0RIER +SECTION: ".abs_section_146" + _CAN0TFLG +SECTION: ".abs_section_147" + _CAN0TIER +SECTION: ".abs_section_148" + _CAN0TARQ +SECTION: ".abs_section_149" + _CAN0TAAK +SECTION: ".abs_section_14a" + _CAN0TBSEL +SECTION: ".abs_section_14b" + _CAN0IDAC +SECTION: ".abs_section_14e" + _CAN0RXERR +SECTION: ".abs_section_14f" + _CAN0TXERR +SECTION: ".abs_section_150" + _CAN0IDAR0 +SECTION: ".abs_section_151" + _CAN0IDAR1 +SECTION: ".abs_section_152" + _CAN0IDAR2 +SECTION: ".abs_section_153" + _CAN0IDAR3 +SECTION: ".abs_section_154" + _CAN0IDMR0 +SECTION: ".abs_section_155" + _CAN0IDMR1 +SECTION: ".abs_section_156" + _CAN0IDMR2 +SECTION: ".abs_section_157" + _CAN0IDMR3 +SECTION: ".abs_section_158" + _CAN0IDAR4 +SECTION: ".abs_section_159" + _CAN0IDAR5 +SECTION: ".abs_section_15a" + _CAN0IDAR6 +SECTION: ".abs_section_15b" + _CAN0IDAR7 +SECTION: ".abs_section_15c" + _CAN0IDMR4 +SECTION: ".abs_section_15d" + _CAN0IDMR5 +SECTION: ".abs_section_15e" + _CAN0IDMR6 +SECTION: ".abs_section_15f" + _CAN0IDMR7 +SECTION: ".abs_section_160" + _CAN0RXIDR0 +SECTION: ".abs_section_161" + _CAN0RXIDR1 +SECTION: ".abs_section_162" + _CAN0RXIDR2 +SECTION: ".abs_section_163" + _CAN0RXIDR3 +SECTION: ".abs_section_164" + _CAN0RXDSR0 +SECTION: ".abs_section_165" + _CAN0RXDSR1 +SECTION: ".abs_section_166" + _CAN0RXDSR2 +SECTION: ".abs_section_167" + _CAN0RXDSR3 +SECTION: ".abs_section_168" + _CAN0RXDSR4 +SECTION: ".abs_section_169" + _CAN0RXDSR5 +SECTION: ".abs_section_16a" + _CAN0RXDSR6 +SECTION: ".abs_section_16b" + _CAN0RXDSR7 +SECTION: ".abs_section_16c" + _CAN0RXDLR +SECTION: ".abs_section_170" + _CAN0TXIDR0 +SECTION: ".abs_section_171" + _CAN0TXIDR1 +SECTION: ".abs_section_172" + _CAN0TXIDR2 +SECTION: ".abs_section_173" + _CAN0TXIDR3 +SECTION: ".abs_section_174" + _CAN0TXDSR0 +SECTION: ".abs_section_175" + _CAN0TXDSR1 +SECTION: ".abs_section_176" + _CAN0TXDSR2 +SECTION: ".abs_section_177" + _CAN0TXDSR3 +SECTION: ".abs_section_178" + _CAN0TXDSR4 +SECTION: ".abs_section_179" + _CAN0TXDSR5 +SECTION: ".abs_section_17a" + _CAN0TXDSR6 +SECTION: ".abs_section_17b" + _CAN0TXDSR7 +SECTION: ".abs_section_17c" + _CAN0TXDLR +SECTION: ".abs_section_17d" + _CAN0TXTBPR +SECTION: ".abs_section_240" + _PTT +SECTION: ".abs_section_241" + _PTIT +SECTION: ".abs_section_242" + _DDRT +SECTION: ".abs_section_243" + _RDRT +SECTION: ".abs_section_244" + _PERT +SECTION: ".abs_section_245" + _PPST +SECTION: ".abs_section_248" + _PTS +SECTION: ".abs_section_249" + _PTIS +SECTION: ".abs_section_24a" + _DDRS +SECTION: ".abs_section_24b" + _RDRS +SECTION: ".abs_section_24c" + _PERS +SECTION: ".abs_section_24d" + _PPSS +SECTION: ".abs_section_24e" + _WOMS +SECTION: ".abs_section_250" + _PTM +SECTION: ".abs_section_251" + _PTIM +SECTION: ".abs_section_252" + _DDRM +SECTION: ".abs_section_253" + _RDRM +SECTION: ".abs_section_254" + _PERM +SECTION: ".abs_section_255" + _PPSM +SECTION: ".abs_section_256" + _WOMM +SECTION: ".abs_section_257" + _MODRR +SECTION: ".abs_section_258" + _PTP +SECTION: ".abs_section_259" + _PTIP +SECTION: ".abs_section_25a" + _DDRP +SECTION: ".abs_section_25b" + _RDRP +SECTION: ".abs_section_25c" + _PERP +SECTION: ".abs_section_25d" + _PPSP +SECTION: ".abs_section_25e" + _PIEP +SECTION: ".abs_section_25f" + _PIFP +SECTION: ".abs_section_260" + _PTH +SECTION: ".abs_section_261" + _PTIH +SECTION: ".abs_section_262" + _DDRH +SECTION: ".abs_section_263" + _RDRH +SECTION: ".abs_section_264" + _PERH +SECTION: ".abs_section_265" + _PPSH +SECTION: ".abs_section_266" + _PIEH +SECTION: ".abs_section_267" + _PIFH +SECTION: ".abs_section_268" + _PTJ +SECTION: ".abs_section_269" + _PTIJ +SECTION: ".abs_section_26a" + _DDRJ +SECTION: ".abs_section_26b" + _RDRJ +SECTION: ".abs_section_26c" + _PERJ +SECTION: ".abs_section_26d" + _PPSJ +SECTION: ".abs_section_26e" + _PIEJ +SECTION: ".abs_section_26f" + _PIFJ +SECTION: ".abs_section_280" + _CAN4CTL0 +SECTION: ".abs_section_281" + _CAN4CTL1 +SECTION: ".abs_section_282" + _CAN4BTR0 +SECTION: ".abs_section_283" + _CAN4BTR1 +SECTION: ".abs_section_284" + _CAN4RFLG +SECTION: ".abs_section_285" + _CAN4RIER +SECTION: ".abs_section_286" + _CAN4TFLG +SECTION: ".abs_section_287" + _CAN4TIER +SECTION: ".abs_section_288" + _CAN4TARQ +SECTION: ".abs_section_289" + _CAN4TAAK +SECTION: ".abs_section_28a" + _CAN4TBSEL +SECTION: ".abs_section_28b" + _CAN4IDAC +SECTION: ".abs_section_28e" + _CAN4RXERR +SECTION: ".abs_section_28f" + _CAN4TXERR +SECTION: ".abs_section_290" + _CAN4IDAR0 +SECTION: ".abs_section_291" + _CAN4IDAR1 +SECTION: ".abs_section_292" + _CAN4IDAR2 +SECTION: ".abs_section_293" + _CAN4IDAR3 +SECTION: ".abs_section_294" + _CAN4IDMR0 +SECTION: ".abs_section_295" + _CAN4IDMR1 +SECTION: ".abs_section_296" + _CAN4IDMR2 +SECTION: ".abs_section_297" + _CAN4IDMR3 +SECTION: ".abs_section_298" + _CAN4IDAR4 +SECTION: ".abs_section_299" + _CAN4IDAR5 +SECTION: ".abs_section_29a" + _CAN4IDAR6 +SECTION: ".abs_section_29b" + _CAN4IDAR7 +SECTION: ".abs_section_29c" + _CAN4IDMR4 +SECTION: ".abs_section_29d" + _CAN4IDMR5 +SECTION: ".abs_section_29e" + _CAN4IDMR6 +SECTION: ".abs_section_29f" + _CAN4IDMR7 +SECTION: ".abs_section_2a0" + _CAN4RXIDR0 +SECTION: ".abs_section_2a1" + _CAN4RXIDR1 +SECTION: ".abs_section_2a2" + _CAN4RXIDR2 +SECTION: ".abs_section_2a3" + _CAN4RXIDR3 +SECTION: ".abs_section_2a4" + _CAN4RXDSR0 +SECTION: ".abs_section_2a5" + _CAN4RXDSR1 +SECTION: ".abs_section_2a6" + _CAN4RXDSR2 +SECTION: ".abs_section_2a7" + _CAN4RXDSR3 +SECTION: ".abs_section_2a8" + _CAN4RXDSR4 +SECTION: ".abs_section_2a9" + _CAN4RXDSR5 +SECTION: ".abs_section_2aa" + _CAN4RXDSR6 +SECTION: ".abs_section_2ab" + _CAN4RXDSR7 +SECTION: ".abs_section_2ac" + _CAN4RXDLR +SECTION: ".abs_section_2b0" + _CAN4TXIDR0 +SECTION: ".abs_section_2b1" + _CAN4TXIDR1 +SECTION: ".abs_section_2b2" + _CAN4TXIDR2 +SECTION: ".abs_section_2b3" + _CAN4TXIDR3 +SECTION: ".abs_section_2b4" + _CAN4TXDSR0 +SECTION: ".abs_section_2b5" + _CAN4TXDSR1 +SECTION: ".abs_section_2b6" + _CAN4TXDSR2 +SECTION: ".abs_section_2b7" + _CAN4TXDSR3 +SECTION: ".abs_section_2b8" + _CAN4TXDSR4 +SECTION: ".abs_section_2b9" + _CAN4TXDSR5 +SECTION: ".abs_section_2ba" + _CAN4TXDSR6 +SECTION: ".abs_section_2bb" + _CAN4TXDSR7 +SECTION: ".abs_section_2bc" + _CAN4TXDLR +SECTION: ".abs_section_2bd" + _CAN4TXTBPR +SECTION: ".abs_section_0" + _PORTAB +SECTION: ".abs_section_2" + _DDRAB +SECTION: ".abs_section_1a" + _PARTID +SECTION: ".abs_section_44" + _TCNT +SECTION: ".abs_section_50" + _TC0 +SECTION: ".abs_section_52" + _TC1 +SECTION: ".abs_section_54" + _TC2 +SECTION: ".abs_section_56" + _TC3 +SECTION: ".abs_section_58" + _TC4 +SECTION: ".abs_section_5a" + _TC5 +SECTION: ".abs_section_5c" + _TC6 +SECTION: ".abs_section_5e" + _TC7 +SECTION: ".abs_section_62" + _PACN32 +SECTION: ".abs_section_64" + _PACN10 +SECTION: ".abs_section_72" + _PA32H +SECTION: ".abs_section_74" + _PA10H +SECTION: ".abs_section_76" + _MCCNT +SECTION: ".abs_section_78" + _TC0H +SECTION: ".abs_section_7a" + _TC1H +SECTION: ".abs_section_7c" + _TC2H +SECTION: ".abs_section_7e" + _TC3H +SECTION: ".abs_section_82" + _ATD0CTL23 +SECTION: ".abs_section_84" + _ATD0CTL45 +SECTION: ".abs_section_90" + _ATD0DR0 +SECTION: ".abs_section_92" + _ATD0DR1 +SECTION: ".abs_section_94" + _ATD0DR2 +SECTION: ".abs_section_96" + _ATD0DR3 +SECTION: ".abs_section_98" + _ATD0DR4 +SECTION: ".abs_section_9a" + _ATD0DR5 +SECTION: ".abs_section_9c" + _ATD0DR6 +SECTION: ".abs_section_9e" + _ATD0DR7 +SECTION: ".abs_section_ac" + _PWMCNT01 +SECTION: ".abs_section_ae" + _PWMCNT23 +SECTION: ".abs_section_b0" + _PWMCNT45 +SECTION: ".abs_section_b2" + _PWMCNT67 +SECTION: ".abs_section_b4" + _PWMPER01 +SECTION: ".abs_section_b6" + _PWMPER23 +SECTION: ".abs_section_b8" + _PWMPER45 +SECTION: ".abs_section_ba" + _PWMPER67 +SECTION: ".abs_section_bc" + _PWMDTY01 +SECTION: ".abs_section_be" + _PWMDTY23 +SECTION: ".abs_section_c0" + _PWMDTY45 +SECTION: ".abs_section_c2" + _PWMDTY67 +SECTION: ".abs_section_c8" + _SCI0BD +SECTION: ".abs_section_d0" + _SCI1BD +SECTION: ".abs_section_122" + _ATD1CTL23 +SECTION: ".abs_section_124" + _ATD1CTL45 +SECTION: ".abs_section_130" + _ATD1DR0 +SECTION: ".abs_section_132" + _ATD1DR1 +SECTION: ".abs_section_134" + _ATD1DR2 +SECTION: ".abs_section_136" + _ATD1DR3 +SECTION: ".abs_section_138" + _ATD1DR4 +SECTION: ".abs_section_13a" + _ATD1DR5 +SECTION: ".abs_section_13c" + _ATD1DR6 +SECTION: ".abs_section_13e" + _ATD1DR7 +SECTION: ".abs_section_16e" + _CAN0RXTSR +SECTION: ".abs_section_17e" + _CAN0TXTSR +SECTION: ".abs_section_2ae" + _CAN4RXTSR +SECTION: ".abs_section_2be" + _CAN4TXTSR +SECTION: ".abs_section_e77e" + _vectab + +********************************************************************************************* +OBJECT LIST SORTED BY ADDRESS + Name Addr hSize dSize Ref Section RLIB +--------------------------------------------------------------------------------------------- + _PORTAB 0 2 2 3 .abs_section_0 + _DDRAB 2 2 2 1 .abs_section_2 + _PORTE 8 1 1 0 .abs_section_8 + _DDRE 9 1 1 0 .abs_section_9 + _PEAR A 1 1 0 .abs_section_a + _MODE B 1 1 0 .abs_section_b + _PUCR C 1 1 0 .abs_section_c + _RDRIV D 1 1 0 .abs_section_d + _EBICTL E 1 1 0 .abs_section_e + _INITRM 10 1 1 0 .abs_section_10 + _INITRG 11 1 1 0 .abs_section_11 + _INITEE 12 1 1 0 .abs_section_12 + _MISC 13 1 1 0 .abs_section_13 + _ITCR 15 1 1 0 .abs_section_15 + _ITEST 16 1 1 0 .abs_section_16 + _PARTID 1A 2 2 0 .abs_section_1a + _MEMSIZ0 1C 1 1 0 .abs_section_1c + _MEMSIZ1 1D 1 1 0 .abs_section_1d + _INTCR 1E 1 1 0 .abs_section_1e + _HPRIO 1F 1 1 0 .abs_section_1f + _BKPCT0 28 1 1 0 .abs_section_28 + _BKPCT1 29 1 1 0 .abs_section_29 + _BKP0X 2A 1 1 0 .abs_section_2a + _BKP0H 2B 1 1 0 .abs_section_2b + _BKP0L 2C 1 1 0 .abs_section_2c + _BKP1X 2D 1 1 0 .abs_section_2d + _BKP1H 2E 1 1 0 .abs_section_2e + _BKP1L 2F 1 1 0 .abs_section_2f + _PPAGE 30 1 1 0 .abs_section_30 + _PORTK 32 1 1 0 .abs_section_32 + _DDRK 33 1 1 0 .abs_section_33 + _SYNR 34 1 1 0 .abs_section_34 + _REFDV 35 1 1 0 .abs_section_35 + _CRGFLG 37 1 1 0 .abs_section_37 + _CRGINT 38 1 1 0 .abs_section_38 + _CLKSEL 39 1 1 0 .abs_section_39 + _PLLCTL 3A 1 1 0 .abs_section_3a + _RTICTL 3B 1 1 0 .abs_section_3b + _COPCTL 3C 1 1 0 .abs_section_3c + _ARMCOP 3F 1 1 0 .abs_section_3f + _TIOS 40 1 1 2 .abs_section_40 + _CFORC 41 1 1 0 .abs_section_41 + _OC7M 42 1 1 0 .abs_section_42 + _OC7D 43 1 1 0 .abs_section_43 + _TCNT 44 2 2 1 .abs_section_44 + _TSCR1 46 1 1 2 .abs_section_46 + _TTOV 47 1 1 1 .abs_section_47 + _TCTL1 48 1 1 1 .abs_section_48 + _TCTL2 49 1 1 1 .abs_section_49 + _TCTL3 4A 1 1 1 .abs_section_4a + _TCTL4 4B 1 1 1 .abs_section_4b + _TIE 4C 1 1 2 .abs_section_4c + _TSCR2 4D 1 1 1 .abs_section_4d + _TFLG1 4E 1 1 2 .abs_section_4e + _TFLG2 4F 1 1 0 .abs_section_4f + _TC0 50 2 2 3 .abs_section_50 + _TC1 52 2 2 0 .abs_section_52 + _TC2 54 2 2 0 .abs_section_54 + _TC3 56 2 2 0 .abs_section_56 + _TC4 58 2 2 0 .abs_section_58 + _TC5 5A 2 2 0 .abs_section_5a + _TC6 5C 2 2 0 .abs_section_5c + _TC7 5E 2 2 0 .abs_section_5e + _PACTL 60 1 1 0 .abs_section_60 + _PAFLG 61 1 1 0 .abs_section_61 + _PACN32 62 2 2 0 .abs_section_62 + _PACN10 64 2 2 0 .abs_section_64 + _MCCTL 66 1 1 0 .abs_section_66 + _MCFLG 67 1 1 0 .abs_section_67 + _ICPAR 68 1 1 0 .abs_section_68 + _DLYCT 69 1 1 0 .abs_section_69 + _ICOVW 6A 1 1 0 .abs_section_6a + _ICSYS 6B 1 1 0 .abs_section_6b + _PBCTL 70 1 1 0 .abs_section_70 + _PBFLG 71 1 1 0 .abs_section_71 + _PA32H 72 2 2 0 .abs_section_72 + _PA10H 74 2 2 0 .abs_section_74 + _MCCNT 76 2 2 0 .abs_section_76 + _TC0H 78 2 2 0 .abs_section_78 + _TC1H 7A 2 2 0 .abs_section_7a + _TC2H 7C 2 2 0 .abs_section_7c + _TC3H 7E 2 2 0 .abs_section_7e + _ATD0CTL23 82 2 2 0 .abs_section_82 + _ATD0CTL45 84 2 2 0 .abs_section_84 + _ATD0STAT0 86 1 1 0 .abs_section_86 + _ATD0TEST1 89 1 1 0 .abs_section_89 + _ATD0STAT1 8B 1 1 0 .abs_section_8b + _ATD0DIEN 8D 1 1 0 .abs_section_8d + _PORTAD0 8F 1 1 0 .abs_section_8f + _ATD0DR0 90 2 2 0 .abs_section_90 + _ATD0DR1 92 2 2 0 .abs_section_92 + _ATD0DR2 94 2 2 0 .abs_section_94 + _ATD0DR3 96 2 2 0 .abs_section_96 + _ATD0DR4 98 2 2 0 .abs_section_98 + _ATD0DR5 9A 2 2 0 .abs_section_9a + _ATD0DR6 9C 2 2 0 .abs_section_9c + _ATD0DR7 9E 2 2 0 .abs_section_9e + _PWME A0 1 1 0 .abs_section_a0 + _PWMPOL A1 1 1 0 .abs_section_a1 + _PWMCLK A2 1 1 0 .abs_section_a2 + _PWMPRCLK A3 1 1 0 .abs_section_a3 + _PWMCAE A4 1 1 0 .abs_section_a4 + _PWMCTL A5 1 1 0 .abs_section_a5 + _PWMSCLA A8 1 1 0 .abs_section_a8 + _PWMSCLB A9 1 1 0 .abs_section_a9 + _PWMCNT01 AC 2 2 0 .abs_section_ac + _PWMCNT23 AE 2 2 0 .abs_section_ae + _PWMCNT45 B0 2 2 0 .abs_section_b0 + _PWMCNT67 B2 2 2 0 .abs_section_b2 + _PWMPER01 B4 2 2 0 .abs_section_b4 + _PWMPER23 B6 2 2 0 .abs_section_b6 + _PWMPER45 B8 2 2 0 .abs_section_b8 + _PWMPER67 BA 2 2 0 .abs_section_ba + _PWMDTY01 BC 2 2 0 .abs_section_bc + _PWMDTY23 BE 2 2 0 .abs_section_be + _PWMDTY45 C0 2 2 0 .abs_section_c0 + _PWMDTY67 C2 2 2 0 .abs_section_c2 + _PWMSDN C4 1 1 0 .abs_section_c4 + _SCI0BD C8 2 2 4 .abs_section_c8 + _SCI0CR1 CA 1 1 1 .abs_section_ca + _SCI0CR2 CB 1 1 2 .abs_section_cb + _SCI0SR1 CC 1 1 1 .abs_section_cc + _SCI0SR2 CD 1 1 0 .abs_section_cd + _SCI0DRH CE 1 1 0 .abs_section_ce + _SCI0DRL CF 1 1 1 .abs_section_cf + _SCI1BD D0 2 2 0 .abs_section_d0 + _SCI1CR1 D2 1 1 0 .abs_section_d2 + _SCI1CR2 D3 1 1 0 .abs_section_d3 + _SCI1SR1 D4 1 1 0 .abs_section_d4 + _SCI1SR2 D5 1 1 0 .abs_section_d5 + _SCI1DRH D6 1 1 0 .abs_section_d6 + _SCI1DRL D7 1 1 0 .abs_section_d7 + _SPI0CR1 D8 1 1 0 .abs_section_d8 + _SPI0CR2 D9 1 1 0 .abs_section_d9 + _SPI0BR DA 1 1 0 .abs_section_da + _SPI0SR DB 1 1 0 .abs_section_db + _SPI0DR DD 1 1 0 .abs_section_dd + _IBAD E0 1 1 0 .abs_section_e0 + _IBFD E1 1 1 0 .abs_section_e1 + _IBCR E2 1 1 0 .abs_section_e2 + _IBSR E3 1 1 0 .abs_section_e3 + _IBDR E4 1 1 0 .abs_section_e4 + _SPI1CR1 F0 1 1 0 .abs_section_f0 + _SPI1CR2 F1 1 1 0 .abs_section_f1 + _SPI1BR F2 1 1 0 .abs_section_f2 + _SPI1SR F3 1 1 0 .abs_section_f3 + _SPI1DR F5 1 1 0 .abs_section_f5 + _SPI2CR1 F8 1 1 0 .abs_section_f8 + _SPI2CR2 F9 1 1 0 .abs_section_f9 + _SPI2BR FA 1 1 0 .abs_section_fa + _SPI2SR FB 1 1 0 .abs_section_fb + _SPI2DR FD 1 1 0 .abs_section_fd + _FCLKDIV 100 1 1 0 .abs_section_100 + _FSEC 101 1 1 0 .abs_section_101 + _FCNFG 103 1 1 0 .abs_section_103 + _FPROT 104 1 1 0 .abs_section_104 + _FSTAT 105 1 1 0 .abs_section_105 + _FCMD 106 1 1 0 .abs_section_106 + _ECLKDIV 110 1 1 0 .abs_section_110 + _ECNFG 113 1 1 0 .abs_section_113 + _EPROT 114 1 1 0 .abs_section_114 + _ESTAT 115 1 1 0 .abs_section_115 + _ECMD 116 1 1 0 .abs_section_116 + _ATD1CTL23 122 2 2 0 .abs_section_122 + _ATD1CTL45 124 2 2 0 .abs_section_124 + _ATD1STAT0 126 1 1 0 .abs_section_126 + _ATD1TEST1 129 1 1 0 .abs_section_129 + _ATD1STAT1 12B 1 1 0 .abs_section_12b + _ATD1DIEN 12D 1 1 0 .abs_section_12d + _PORTAD1 12F 1 1 0 .abs_section_12f + _ATD1DR0 130 2 2 0 .abs_section_130 + _ATD1DR1 132 2 2 0 .abs_section_132 + _ATD1DR2 134 2 2 0 .abs_section_134 + _ATD1DR3 136 2 2 0 .abs_section_136 + _ATD1DR4 138 2 2 0 .abs_section_138 + _ATD1DR5 13A 2 2 0 .abs_section_13a + _ATD1DR6 13C 2 2 0 .abs_section_13c + _ATD1DR7 13E 2 2 0 .abs_section_13e + _CAN0CTL0 140 1 1 0 .abs_section_140 + _CAN0CTL1 141 1 1 0 .abs_section_141 + _CAN0BTR0 142 1 1 0 .abs_section_142 + _CAN0BTR1 143 1 1 0 .abs_section_143 + _CAN0RFLG 144 1 1 0 .abs_section_144 + _CAN0RIER 145 1 1 0 .abs_section_145 + _CAN0TFLG 146 1 1 0 .abs_section_146 + _CAN0TIER 147 1 1 0 .abs_section_147 + _CAN0TARQ 148 1 1 0 .abs_section_148 + _CAN0TAAK 149 1 1 0 .abs_section_149 + _CAN0TBSEL 14A 1 1 0 .abs_section_14a + _CAN0IDAC 14B 1 1 0 .abs_section_14b + _CAN0RXERR 14E 1 1 0 .abs_section_14e + _CAN0TXERR 14F 1 1 0 .abs_section_14f + _CAN0IDAR0 150 1 1 0 .abs_section_150 + _CAN0IDAR1 151 1 1 0 .abs_section_151 + _CAN0IDAR2 152 1 1 0 .abs_section_152 + _CAN0IDAR3 153 1 1 0 .abs_section_153 + _CAN0IDMR0 154 1 1 0 .abs_section_154 + _CAN0IDMR1 155 1 1 0 .abs_section_155 + _CAN0IDMR2 156 1 1 0 .abs_section_156 + _CAN0IDMR3 157 1 1 0 .abs_section_157 + _CAN0IDAR4 158 1 1 0 .abs_section_158 + _CAN0IDAR5 159 1 1 0 .abs_section_159 + _CAN0IDAR6 15A 1 1 0 .abs_section_15a + _CAN0IDAR7 15B 1 1 0 .abs_section_15b + _CAN0IDMR4 15C 1 1 0 .abs_section_15c + _CAN0IDMR5 15D 1 1 0 .abs_section_15d + _CAN0IDMR6 15E 1 1 0 .abs_section_15e + _CAN0IDMR7 15F 1 1 0 .abs_section_15f + _CAN0RXIDR0 160 1 1 0 .abs_section_160 + _CAN0RXIDR1 161 1 1 0 .abs_section_161 + _CAN0RXIDR2 162 1 1 0 .abs_section_162 + _CAN0RXIDR3 163 1 1 0 .abs_section_163 + _CAN0RXDSR0 164 1 1 0 .abs_section_164 + _CAN0RXDSR1 165 1 1 0 .abs_section_165 + _CAN0RXDSR2 166 1 1 0 .abs_section_166 + _CAN0RXDSR3 167 1 1 0 .abs_section_167 + _CAN0RXDSR4 168 1 1 0 .abs_section_168 + _CAN0RXDSR5 169 1 1 0 .abs_section_169 + _CAN0RXDSR6 16A 1 1 0 .abs_section_16a + _CAN0RXDSR7 16B 1 1 0 .abs_section_16b + _CAN0RXDLR 16C 1 1 0 .abs_section_16c + _CAN0RXTSR 16E 2 2 0 .abs_section_16e + _CAN0TXIDR0 170 1 1 0 .abs_section_170 + _CAN0TXIDR1 171 1 1 0 .abs_section_171 + _CAN0TXIDR2 172 1 1 0 .abs_section_172 + _CAN0TXIDR3 173 1 1 0 .abs_section_173 + _CAN0TXDSR0 174 1 1 0 .abs_section_174 + _CAN0TXDSR1 175 1 1 0 .abs_section_175 + _CAN0TXDSR2 176 1 1 0 .abs_section_176 + _CAN0TXDSR3 177 1 1 0 .abs_section_177 + _CAN0TXDSR4 178 1 1 0 .abs_section_178 + _CAN0TXDSR5 179 1 1 0 .abs_section_179 + _CAN0TXDSR6 17A 1 1 0 .abs_section_17a + _CAN0TXDSR7 17B 1 1 0 .abs_section_17b + _CAN0TXDLR 17C 1 1 0 .abs_section_17c + _CAN0TXTBPR 17D 1 1 0 .abs_section_17d + _CAN0TXTSR 17E 2 2 0 .abs_section_17e + _PTT 240 1 1 0 .abs_section_240 + _PTIT 241 1 1 0 .abs_section_241 + _DDRT 242 1 1 0 .abs_section_242 + _RDRT 243 1 1 0 .abs_section_243 + _PERT 244 1 1 0 .abs_section_244 + _PPST 245 1 1 0 .abs_section_245 + _PTS 248 1 1 0 .abs_section_248 + _PTIS 249 1 1 0 .abs_section_249 + _DDRS 24A 1 1 0 .abs_section_24a + _RDRS 24B 1 1 0 .abs_section_24b + _PERS 24C 1 1 0 .abs_section_24c + _PPSS 24D 1 1 0 .abs_section_24d + _WOMS 24E 1 1 0 .abs_section_24e + _PTM 250 1 1 0 .abs_section_250 + _PTIM 251 1 1 0 .abs_section_251 + _DDRM 252 1 1 0 .abs_section_252 + _RDRM 253 1 1 0 .abs_section_253 + _PERM 254 1 1 0 .abs_section_254 + _PPSM 255 1 1 0 .abs_section_255 + _WOMM 256 1 1 0 .abs_section_256 + _MODRR 257 1 1 0 .abs_section_257 + _PTP 258 1 1 0 .abs_section_258 + _PTIP 259 1 1 0 .abs_section_259 + _DDRP 25A 1 1 0 .abs_section_25a + _RDRP 25B 1 1 0 .abs_section_25b + _PERP 25C 1 1 0 .abs_section_25c + _PPSP 25D 1 1 0 .abs_section_25d + _PIEP 25E 1 1 0 .abs_section_25e + _PIFP 25F 1 1 0 .abs_section_25f + _PTH 260 1 1 0 .abs_section_260 + _PTIH 261 1 1 0 .abs_section_261 + _DDRH 262 1 1 0 .abs_section_262 + _RDRH 263 1 1 0 .abs_section_263 + _PERH 264 1 1 0 .abs_section_264 + _PPSH 265 1 1 0 .abs_section_265 + _PIEH 266 1 1 0 .abs_section_266 + _PIFH 267 1 1 0 .abs_section_267 + _PTJ 268 1 1 1 .abs_section_268 + _PTIJ 269 1 1 0 .abs_section_269 + _DDRJ 26A 1 1 1 .abs_section_26a + _RDRJ 26B 1 1 0 .abs_section_26b + _PERJ 26C 1 1 0 .abs_section_26c + _PPSJ 26D 1 1 0 .abs_section_26d + _PIEJ 26E 1 1 0 .abs_section_26e + _PIFJ 26F 1 1 0 .abs_section_26f + _CAN4CTL0 280 1 1 0 .abs_section_280 + _CAN4CTL1 281 1 1 0 .abs_section_281 + _CAN4BTR0 282 1 1 0 .abs_section_282 + _CAN4BTR1 283 1 1 0 .abs_section_283 + _CAN4RFLG 284 1 1 0 .abs_section_284 + _CAN4RIER 285 1 1 0 .abs_section_285 + _CAN4TFLG 286 1 1 0 .abs_section_286 + _CAN4TIER 287 1 1 0 .abs_section_287 + _CAN4TARQ 288 1 1 0 .abs_section_288 + _CAN4TAAK 289 1 1 0 .abs_section_289 + _CAN4TBSEL 28A 1 1 0 .abs_section_28a + _CAN4IDAC 28B 1 1 0 .abs_section_28b + _CAN4RXERR 28E 1 1 0 .abs_section_28e + _CAN4TXERR 28F 1 1 0 .abs_section_28f + _CAN4IDAR0 290 1 1 0 .abs_section_290 + _CAN4IDAR1 291 1 1 0 .abs_section_291 + _CAN4IDAR2 292 1 1 0 .abs_section_292 + _CAN4IDAR3 293 1 1 0 .abs_section_293 + _CAN4IDMR0 294 1 1 0 .abs_section_294 + _CAN4IDMR1 295 1 1 0 .abs_section_295 + _CAN4IDMR2 296 1 1 0 .abs_section_296 + _CAN4IDMR3 297 1 1 0 .abs_section_297 + _CAN4IDAR4 298 1 1 0 .abs_section_298 + _CAN4IDAR5 299 1 1 0 .abs_section_299 + _CAN4IDAR6 29A 1 1 0 .abs_section_29a + _CAN4IDAR7 29B 1 1 0 .abs_section_29b + _CAN4IDMR4 29C 1 1 0 .abs_section_29c + _CAN4IDMR5 29D 1 1 0 .abs_section_29d + _CAN4IDMR6 29E 1 1 0 .abs_section_29e + _CAN4IDMR7 29F 1 1 0 .abs_section_29f + _CAN4RXIDR0 2A0 1 1 0 .abs_section_2a0 + _CAN4RXIDR1 2A1 1 1 0 .abs_section_2a1 + _CAN4RXIDR2 2A2 1 1 0 .abs_section_2a2 + _CAN4RXIDR3 2A3 1 1 0 .abs_section_2a3 + _CAN4RXDSR0 2A4 1 1 0 .abs_section_2a4 + _CAN4RXDSR1 2A5 1 1 0 .abs_section_2a5 + _CAN4RXDSR2 2A6 1 1 0 .abs_section_2a6 + _CAN4RXDSR3 2A7 1 1 0 .abs_section_2a7 + _CAN4RXDSR4 2A8 1 1 0 .abs_section_2a8 + _CAN4RXDSR5 2A9 1 1 0 .abs_section_2a9 + _CAN4RXDSR6 2AA 1 1 0 .abs_section_2aa + _CAN4RXDSR7 2AB 1 1 0 .abs_section_2ab + _CAN4RXDLR 2AC 1 1 0 .abs_section_2ac + _CAN4RXTSR 2AE 2 2 0 .abs_section_2ae + _CAN4TXIDR0 2B0 1 1 0 .abs_section_2b0 + _CAN4TXIDR1 2B1 1 1 0 .abs_section_2b1 + _CAN4TXIDR2 2B2 1 1 0 .abs_section_2b2 + _CAN4TXIDR3 2B3 1 1 0 .abs_section_2b3 + _CAN4TXDSR0 2B4 1 1 0 .abs_section_2b4 + _CAN4TXDSR1 2B5 1 1 0 .abs_section_2b5 + _CAN4TXDSR2 2B6 1 1 0 .abs_section_2b6 + _CAN4TXDSR3 2B7 1 1 0 .abs_section_2b7 + _CAN4TXDSR4 2B8 1 1 0 .abs_section_2b8 + _CAN4TXDSR5 2B9 1 1 0 .abs_section_2b9 + _CAN4TXDSR6 2BA 1 1 0 .abs_section_2ba + _CAN4TXDSR7 2BB 1 1 0 .abs_section_2bb + _CAN4TXDLR 2BC 1 1 0 .abs_section_2bc + _CAN4TXTBPR 2BD 1 1 0 .abs_section_2bd + _CAN4TXTSR 2BE 2 2 0 .abs_section_2be + xcpCtoRxInProgress.3 1100 1 1 3 .bss + xcpCtoReqPacket.1 1101 41 65 5 .bss + xcpCtoRxLength.2 1142 1 1 4 .bss + led_toggle_state.1 1143 1 1 3 .bss + timer_counter_last.2 1144 4 4 5 .bss + millisecond_counter 1148 4 4 8 .bss + Init C000 29 41 1 .init + _Startup C029 8 8 1 .init + BootActivate C03B F 15 1 .text + BootComInit C04A 19 25 1 .text + BootComCheckActivationRequest C063 44 68 1 .text + UartReceiveByte C0A7 11 17 2 .text + IrqInterruptEnable C0B8 3 3 1 .text + LedInit C0BB F 15 1 .text + LedToggle C0CA 48 72 1 .text + main C112 E 14 1 .text + Init C120 9 9 1 .text + TimeInit C129 1E 30 1 .text + TimeDeinit C147 1C 28 2 .text + TimeSet C163 7 7 1 .text + TimeGet C16A 7 7 1 .text + TimeISRHandler C171 1B 27 1 .text + UnusedISR C18C 2 2 62 .text + _LCMP C18E 19 25 1 RUNTIME + _LINC C1A7 5 5 1 RUNTIME + _vectab E77E 82 130 0 .abs_section_e77e + +********************************************************************************************* +UNUSED-OBJECTS SECTION +--------------------------------------------------------------------------------------------- +NOT USED PROCEDURES +rtshc12.c.o (ansisi.lib): + _BSHL _BSHRS _BSHRU _BDIVMODU _BDIVMODS _ISHL _ISHRU _ISHRS _LSHL _LSHRU + _LSHRS _LADD _LSUB _LAND _LOR _LXOR _LCMP_P _LCMP_PP _LNEG _LCOM _LDEC _LMUL + _LMULU16x32 _LMULS16x32 _lDivMod _LDIVU _NEG_P _LDIVS _LMODU _LMODS _ILSEXT + _COPY _CASE_DIRECT _CASE_DIRECT_BYTE _CASE_CHECKED _CASE_CHECKED_BYTE + _CASE_SEARCH _CASE_SEARCH_BYTE _CASE_SEARCH_8 _CASE_SEARCH_8_BYTE _FCALL + _FPCMP +irq.c.o: + IrqInterruptDisable IrqInterruptRestore +NOT USED VARIABLES +rtshc12.c.o (ansisi.lib): + _PowOfTwo_8 _PowOfTwo_16 _PowOfTwo_32 errno +irq.c.o: + irqNesting irqCCRregSave + +********************************************************************************************* +COPYDOWN SECTION +--------------------------------------------------------------------------------------------- +------- ROM-ADDRESS: 0xC1AC ---- SIZE 2 --- +Filling bytes inserted + 0000 + +********************************************************************************************* +OBJECT-DEPENDENCIES SECTION +--------------------------------------------------------------------------------------------- +Init USES _startupData +_Startup USES __SEG_END_SSTACK Init main +BootActivate USES TimeDeinit +BootComInit USES _SCI0CR2 _SCI0CR1 _SCI0BD +BootComCheckActivationRequest USES xcpCtoRxInProgress.3 xcpCtoReqPacket.1 + UartReceiveByte xcpCtoRxLength.2 BootActivate +UartReceiveByte USES _SCI0SR1 _SCI0DRL +LedInit USES _DDRJ _PTJ _DDRAB _PORTAB +LedToggle USES TimeGet timer_counter_last.2 _LCMP + led_toggle_state.1 _PORTAB +main USES Init BootComInit LedToggle + BootComCheckActivationRequest +Init USES LedInit TimeInit IrqInterruptEnable +TimeInit USES TimeDeinit _TIOS _TFLG1 _TCNT _TC0 _TIE _TSCR1 + TimeSet +TimeDeinit USES _TIE _TSCR1 _TSCR2 _TIOS _TTOV _TCTL1 _TCTL2 + _TCTL3 _TCTL4 +TimeSet USES millisecond_counter +TimeGet USES millisecond_counter +TimeISRHandler USES _TFLG1 _TC0 millisecond_counter _LINC +_vectab USES UnusedISR TimeISRHandler _Startup + +********************************************************************************************* +DEPENDENCY TREE +********************************************************************************************* + main and _Startup Group + | + +- main + | | + | +- Init + | | | + | | +- LedInit + | | | + | | +- TimeInit + | | | | + | | | +- TimeDeinit + | | | | + | | | +- TimeSet + | | | + | | +- IrqInterruptEnable + | | + | +- BootComInit + | | + | +- LedToggle + | | | + | | +- TimeGet + | | | + | | +- _LCMP + | | + | +- BootComCheckActivationRequest + | | + | +- UartReceiveByte + | | + | +- BootActivate + | | + | +- TimeDeinit (see above) + | + +- _Startup + | + +- Init + | + +- main (see above) + + _vectab + | + +- UnusedISR + | + +- TimeISRHandler + | | + | +- _LINC + | + +- _Startup (see above) + +********************************************************************************************* +STATISTIC SECTION +--------------------------------------------------------------------------------------------- + +ExeFile: +-------- +Number of blocks to be downloaded: 6 +Total size of all blocks to be downloaded: 560 + diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/boot.c b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/boot.c new file mode 100644 index 00000000..845f449e --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/boot.c @@ -0,0 +1,169 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\boot.c +* \brief Demo program bootloader interface source file. +* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/************************************************************************************//** +** \brief Bootloader activation function. +** \return none. +** +****************************************************************************************/ +static void BootActivate(void) +{ + void (*near pEntryFromProgFnc)(void); + + /* stop the timer from generating interrupts */ + TimeDeinit(); + /* set pointer to the address of function reset_connected_handler in the bootloader. */ + pEntryFromProgFnc = (void(*)(void))(0xfef0); + /* call EntryFromProg to activate the bootloader. */ + pEntryFromProgFnc(); +} /*** end of BootActivate ***/ + + +#if (BOOT_COM_UART_ENABLE > 0) +/**************************************************************************************** +* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E +****************************************************************************************/ + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static unsigned char UartReceiveByte(unsigned char *data); + + +/************************************************************************************//** +** \brief Initializes the UART communication interface. +** \return none. +** +****************************************************************************************/ +void BootComInit(void) +{ + unsigned short baudrate_sbr0_12; + + /* reset the SCI subsystem's configuration, which automatically configures it for + * 8,n,1 communication mode. + */ + SCI0CR2 = 0; + SCI0CR1 = 0; + SCI0BDH = 0; + SCI0BDL = 0; + /* configure the baudrate from BOOT_COM_UART_BAUDRATE */ + baudrate_sbr0_12 = (BOOT_CPU_SYSTEM_SPEED_KHZ * 1000ul) / 16 / BOOT_COM_UART_BAUDRATE; + baudrate_sbr0_12 &= SCI0BD_SBR_MASK; + /* write first MSB then LSB for the baudrate to latch */ + SCI0BDH = (unsigned char)(baudrate_sbr0_12 >> 8); + SCI0BDL = (unsigned char)baudrate_sbr0_12; + /* enable the receiver */ + SCI0CR2 |= (SCI0CR2_RE_MASK); +} /*** end of BootComInit ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +void BootComCheckActivationRequest(void) +{ + static unsigned char xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1]; + static unsigned char xcpCtoRxLength; + static unsigned char xcpCtoRxInProgress = 0; + + /* start of cto packet received? */ + if (xcpCtoRxInProgress == 0) + { + /* store the message length when received */ + if (UartReceiveByte(&xcpCtoReqPacket[0]) == 1) + { + /* indicate that a cto packet is being received */ + xcpCtoRxInProgress = 1; + + /* reset packet data count */ + xcpCtoRxLength = 0; + } + } + else + { + /* store the next packet byte */ + if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1) + { + /* increment the packet data count */ + xcpCtoRxLength++; + + /* check to see if the entire packet was received */ + if (xcpCtoRxLength == xcpCtoReqPacket[0]) + { + /* done with cto packet reception */ + xcpCtoRxInProgress = 0; + + /* check if this was an XCP CONNECT command */ + if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00)) + { + /* connection request received so start the bootloader */ + BootActivate(); + } + } + } + } +} /*** end of BootComCheckActivationRequest ***/ + + +/************************************************************************************//** +** \brief Receives a communication interface byte if one is present. +** \param data Pointer to byte where the data is to be stored. +** \return 1 if a byte was received, 0 otherwise. +** +****************************************************************************************/ +static unsigned char UartReceiveByte(unsigned char *data) +{ + /* check if a new byte was received by means of the RDRF-bit */ + if((SCI0SR1 & SCI0SR1_RDRF_MASK) != 0) + { + /* store the received byte */ + data[0] = SCI0DRL; + /* inform caller of the newly received byte */ + return 1; + } + /* inform caller that no new data was received */ + return 0; +} /*** end of UartReceiveByte ***/ +#endif /* BOOT_COM_UART_ENABLE > 0 */ + + +/*********************************** end of boot.c *************************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/boot.h b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/boot.h new file mode 100644 index 00000000..2c13183b --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/boot.h @@ -0,0 +1,44 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\boot.h +* \brief Demo program bootloader interface header file. +* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef BOOT_H +#define BOOT_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void BootComInit(void); +void BootComCheckActivationRequest(void); + + +#endif /* BOOT_H */ +/*********************************** end of boot.h *************************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Erase_unsecure_hcs12.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Erase_unsecure_hcs12.cmd new file mode 100644 index 00000000..ca4f6c92 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Erase_unsecure_hcs12.cmd @@ -0,0 +1,78 @@ +// ver 1.1 (7/7/04) +// HCS12X Core erasing + unsecuring command file: +// These commands mass erase the chip then program the security byte to 0xFE (unsecured state). + +// Evaluate the clock divider to set in ECLKDIV/FCLKDIV registers: + +DEFINEVALUEDLG "Information required to unsecure the device" "CLKDIV" 0x49 "To unsecure the device, the command script needs \nthe correct value for ECLKDIV/FCLKDIV onchip\nregisters.\nIf the bus frequency is less than 10 MHz, the value\nto store in ECLKDIV/FCLKDIV is equal to:\n \"bus frequency (kHz) / 175\"\n\nIf the bus frequency is higher than 10 MHz, the value\nto store in ECLKDIV/FCLKDIV is equal to:\n \" bus frequency (kHz) / 1400 + 64\"\n(+64 (0x40) is to set PRDIV8 flag)\n\nDatasheet proposed values:\n\nbus frequency\t\tE/FCLKDIV value (decimal)\n\n 16 \tMHz\t\t73\n 8 \tMHz\t\t39\n 4 \tMHz\t\t19\n 2 \tMHz\t\t9\n 1 \tMHz\t\t4\n" + +// An average programming clock of 175 kHz is chosen. + +// If the oscillator frequency is less than 10 MHz, the value to store +// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 175 ". + +// If the oscillator frequency is higher than 10 MHz, the value to store +// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 1400 + 0x40 (to set PRDIV8 flag)". + +// Datasheet proposed values: +// +// oscillator frequency ECLKDIV/FCLKDIV value (hexadecimal) +// +// 16 MHz $49 +// 8 MHz $27 +// 4 MHz $13 +// 2 MHz $9 +// 1 MHz $4 + + +FLASH RELEASE // do not interact with regular flash programming monitor + +//mass erase flash +reset +wb 0x03c 0x00 //disable cop +wait 20 +wb 0x100 CLKDIV // set FCLKDIV clock divider +wb 0x104 0xFF // FPROT all protection disabled +wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register +wb 0x102 0x00 // clear the WRALL bit in FTSTMOD +wb 0x105 0x02 +wb 0x102 0x10 // set the WRALL bit in FTSTMOD to affect all blocks +ww 0x108 0xFFFE +ww 0x10A 0xFFFF +wb 0x106 0x41 // write MASS ERASE command in FCMD register +wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command +wait 20 // wait for command to complete + +//mass erase eeprom +wb 0x110 CLKDIV // set ECLKDV clock divider +wb 0x114 0xFF // EPROT all protection disabled +wb 0x115 0x30 // clear PVIOL and ACCERR in ESTAT register +wb 0x112 0x00 // clear the WRALL bit in FTSTMOD +wb 0x115 0x02 +ww 0x118 0x0C00 // write to EADDR eeprom address register +ww 0x11A 0x0000 // write to EDATA eeprom data register +wb 0x116 0x41 // write MASS ERASE command in ECMD register +wb 0x115 0x80 // clear CBEIF in ESTAT register to execute the command +wait 20 // wait for command to complete + +//reprogram Security byte to Unsecure state +reset +wb 0x03c 0x00 //disable cop +wait 20 +wb 0x102 0x00 // clear the WRALL bit in FTSTMOD +wb 0x105 0x02 +wb 0x100 CLKDIV // set FCLKDIV clock divider +wb 0x100 CLKDIV // set FCLKDIV clock divider +wb 0x104 0xFF // FPROT all protection disabled +wb 0x105 0x30 // clear PVIOL and ACCERR in FSTAT register +wb 0x102 0x00 // clear the WRALL bit in FTSTMOD +wb 0x105 0x02 +ww 0xFF0E 0xFFFE // write security byte to "Unsecured" state +wb 0x106 0x20 // write MEMORY PROGRAM command in FCMD register +wb 0x105 0x80 // clear CBEIF in FSTAT register to execute the command +wait 20 // wait for command to complete + +reset + +undef CLKDIV // undefine variable + diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Postload.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Postload.cmd new file mode 100644 index 00000000..eb00f379 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Postload.cmd @@ -0,0 +1 @@ +// After load the commands written below will be executed diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Preload.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Preload.cmd new file mode 100644 index 00000000..691c5eed --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Preload.cmd @@ -0,0 +1 @@ +// Before load the commands written below will be executed diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Reset.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Reset.cmd new file mode 100644 index 00000000..f0fc8744 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Reset.cmd @@ -0,0 +1 @@ +// After reset the commands written below will be executed diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Startup.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Startup.cmd new file mode 100644 index 00000000..5f2b5a56 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Startup.cmd @@ -0,0 +1 @@ +// At startup the commands written below will be executed diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Vppoff.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Vppoff.cmd new file mode 100644 index 00000000..52e399a6 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Vppoff.cmd @@ -0,0 +1 @@ +// After programming the flash, the commands written below will be executed diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Vppon.cmd b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Vppon.cmd new file mode 100644 index 00000000..048a6d94 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/P&E_Multilink_USB_Vppon.cmd @@ -0,0 +1 @@ +// Before programming the flash, the commands written below will be executed diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/burner.bbl b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/burner.bbl new file mode 100644 index 00000000..f553723e --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/cmd/burner.bbl @@ -0,0 +1,115 @@ +/* s-record file with linear addresses for MicroBoot/OpenBLT */ +OPENFILE "%ABS_FILE%.sx" +format = motorola +busWidth = 1 +len = 0x4000 + +/* logical non banked flash at $4000 and $C000 to physical */ +origin = 0x004000 +destination = 0x0F8000 +SENDBYTE 1 "%ABS_FILE%" + +origin = 0x00C000 +destination = 0x0FC000 +SENDBYTE 1 "%ABS_FILE%" + +/* 512 kB banked flash addresses to linear */ +origin = 0x208000 +destination = 0x080000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x218000 +destination = 0x084000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x228000 +destination = 0x088000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x238000 +destination = 0x08C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x248000 +destination = 0x090000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x258000 +destination = 0x094000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x268000 +destination = 0x098000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x278000 +destination = 0x09C000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x288000 +destination = 0x0A0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x298000 +destination = 0x0A4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x2A8000 +destination = 0x0A8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x2B8000 +destination = 0x0AC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x2C8000 +destination = 0x0B0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x2D8000 +destination = 0x0B4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x2E8000 +destination = 0x0B8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x2F8000 +destination = 0x0BC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x308000 +destination = 0x0C0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x318000 +destination = 0x0C4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x328000 +destination = 0x0C8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x338000 +destination = 0x0CC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x348000 +destination = 0x0D0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x358000 +destination = 0x0D4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x368000 +destination = 0x0D8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x378000 +destination = 0x0DC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x388000 +destination = 0x0E0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x398000 +destination = 0x0E4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3A8000 +destination = 0x0E8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3B8000 +destination = 0x0EC000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3C8000 +destination = 0x0F0000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3D8000 +destination = 0x0F4000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3E8000 +destination = 0x0F8000 +SENDBYTE 1 "%ABS_FILE%" +origin = 0x3F8000 +destination = 0x0FC000 +SENDBYTE 1 "%ABS_FILE%" + +CLOSE + diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/header.h b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/header.h new file mode 100644 index 00000000..e1a62323 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/header.h @@ -0,0 +1,49 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\header.h +* \brief Generic header file. +* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef HEADER_H +#define HEADER_H + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "../Boot/blt_conf.h" /* bootloader configuration */ +#include "boot.h" /* bootloader interface driver */ +#include "irq.h" /* IRQ driver */ +#include "led.h" /* LED driver */ +#include "time.h" /* Timer driver */ +#include "derivative.h" /* MCU registers */ + + + +#endif /* HEADER_H */ +/*********************************** end of header.h ***********************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/C_Layout.hwl b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/C_Layout.hwl new file mode 100644 index 00000000..3b16d98a --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/C_Layout.hwl @@ -0,0 +1,20 @@ +OPEN source 0 0 60 39 +Source < attributes MARKS off +OPEN assembly 60 0 40 31 +Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C +OPEN procedure 0 39 60 17 +Procedure < attributes VALUES on,TYPES off +OPEN register 60 31 40 25 +Register < attributes FORMAT AUTO,COMPLEMENT None +OPEN memory 60 56 40 22 +Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80 +OPEN data 0 56 60 22 +Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 +OPEN data 0 78 60 22 +Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16 +OPEN command 60 78 40 22 +Command < attributes CACHESIZE 1000 +bckcolor 50331647 +font 'Courier New' 9 BLACK +AUTOSIZE on +ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/Default.mem b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/Default.mem new file mode 100644 index 0000000000000000000000000000000000000000..d0bbb2e4d27ec9e58f5004d60ac5c4b6e68fec3e GIT binary patch literal 161 zcmX>ckl4`d7#iZQ;Opwk5aj5~(9qB@0f_N}#>OtNo*;jq9v}uPCPGgSL=Vso;_c}M E0JXYCwEzGB literal 0 HcmV?d00001 diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/P&E_Multilink_USB.ini b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/P&E_Multilink_USB.ini new file mode 100644 index 00000000..eb4d0554 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/ide/P&E_Multilink_USB.ini @@ -0,0 +1,84 @@ +[STARTUP] +CPUTARGETTYPE=0 +USE_CYCLONEPRO_RELAYS=0 +PORT=21 +interface_selection=1 +SHOWDIALOG=0 +IO_DELAY_SET=1 +frequency_has_changed_old_io_delay_cnt=29 +CyclonePro_poweroffonexit=0 +CyclonePro_currentvoltage=255 +CyclonePro_PowerDownDelay=250 +CyclonePro_PowerUpDelay=250 +IO_DELAY_CNT=29 +PCI_DELAY=0 +RESET_DELAY=0 + + + + + + + + + + +[Environment Variables] +GENPATH={Project}..\src;{Compiler}lib\hc12c\src;{Compiler}lib\hc12c\include;{Compiler}lib\hc12c\lib;{Compiler}lib\xgatec\src;{Compiler}lib\xgatec\include;{Compiler}lib\xgatec\lib +LIBPATH={Compiler}lib\hc12c\include;{Compiler}lib\xgatec\include +OBJPATH={Project}..\bin +TEXTPATH={Project}..\bin +ABSPATH={Project}..\bin + +[HI-WAVE] +Target=icd12 +Layout=C_layout.hwl +LoadDialogOptions=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main" +CPU=HC12 +MainFrame=2,3,-1,-1,-1,-1,200,200,1640,967 +TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806 +AEFWarningDialog=FALSE + + + + +[HC12MultilinkCyclonePro_GDI_SETTINGS] +CMDFILE0=CMDFILE STARTUP ON ".\..\cmd\P&E_Multilink_USB_startup.cmd" +CMDFILE1=CMDFILE RESET ON ".\..\cmd\P&E_Multilink_USB_reset.cmd" +CMDFILE2=CMDFILE PRELOAD ON ".\..\cmd\P&E_Multilink_USB_preload.cmd" +CMDFILE3=CMDFILE POSTLOAD ON ".\..\cmd\P&E_Multilink_USB_postload.cmd" +CMDFILE4=CMDFILE VPPON ON ".\..\cmd\P&E_Multilink_USB_vppon.cmd" +CMDFILE5=CMDFILE VPPOFF ON ".\..\cmd\P&E_Multilink_USB_vppoff.cmd" +CMDFILE6=CMDFILE UNSECURE ON ".\..\cmd\P&E_Multilink_USB_erase_unsecure_hcs12.cmd" +MCUID=0x03D9 +NV_PARAMETER_FILE=C:\Program Files (x86)\Freescale\CWS12v5.1\prog\FPP\mcu03D9.fpp +NV_SAVE_WSP=0 +NV_AUTO_ID=1 +CHIPSECURE=CHIPSECURE SETUP 0xFF0F 0x3 0x2 +HWBPD_MCUID03D9_HWBPM0=HWBPM MODE AUTOMATIC BPM22BITS 0x28 SKIP_OFF +HWBPD_MCUID03D9_BKPT_REMAP0=HWBPM REMAP_22BITS RANGE 0x4000 0x7FFF 0x3E +HWBPD_MCUID03D9_BKPT_REMAP1=HWBPM REMAP_22BITS RANGE 0xC000 0xFFFF 0x3F +HWBPD_MCUID03D9_HWBPM1=HWBPM SET16BITS 0x0 0x0 0x0 0x0 +HWBPD_MCUID03D9_HWBPM2=HWBPM SET22BITS 0x0 0x0 0x0 0x0 + + + + + + + + + + +[ICD12] +COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL +SETCLKSW=0 +HOTPLUGGING=0 +DETECTRUNNING=0 +RESYNCONCOPRESET=0 +BDMAutoSpeed=0 +BDMClockSpeed=29 +HIGHIODELAYCONSTFORPLL=40 + +[PORT] +IP= diff --git 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components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Local data definitions +****************************************************************************************/ +/** \brief IRQ nesting counter . */ +static volatile unsigned long irqNesting=0; +/** \brief Copy of CCR register. */ +static volatile unsigned char irqCCRregSave; + + +/************************************************************************************//** +** \brief Enables the generation IRQ interrupts. Typically called once during +** software startup after completion of the initialization. +** \return none. +** +****************************************************************************************/ +void IrqInterruptEnable(void) +{ + /* enable the global interrupts */ + asm("cli"); +} /*** end of IrqInterruptEnable ***/ + + +/************************************************************************************//** +** \brief Disables the generation IRQ interrupts and stores information on +** whether or not the interrupts were already disabled before explicitly +** disabling them with this function. Normally used as a pair together +** with IrqInterruptRestore during a critical section. +** \return none. +** +****************************************************************************************/ +void IrqInterruptDisable(void) +{ + if (irqNesting == 0) + { + asm + { + tpa + sei + staa irqCCRregSave + } + } + irqNesting++; +} /*** end of IrqInterruptDisable ***/ + + +/************************************************************************************//** +** \brief Restore the generation IRQ interrupts to the setting it had prior to +** calling IrqInterruptDisable. Normally used as a pair together with +** IrqInterruptDisable during a critical section. +** \return none. +** +****************************************************************************************/ +void IrqInterruptRestore(void) +{ + irqNesting--; + if (irqNesting == 0) + { + asm + { + ldaa irqCCRregSave + tap + } + } +} /*** end of IrqInterruptRestore ***/ + + +/*********************************** end of irq.c **************************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/irq.h b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/irq.h new file mode 100644 index 00000000..0ff70af8 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/irq.h @@ -0,0 +1,45 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\irq.h +* \brief IRQ driver header file. +* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef IRQ_H +#define IRQ_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void IrqInterruptEnable(void); +void IrqInterruptDisable(void); +void IrqInterruptRestore(void); + + +#endif /* IRQ_H */ +/*********************************** end of irq.h **************************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/led.c b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/led.c new file mode 100644 index 00000000..e60b18ed --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/led.c @@ -0,0 +1,104 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\led.c +* \brief LED driver source file. +* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Toggle interval time in milliseconds. */ +#define LED_TOGGLE_MS (500) + + +/************************************************************************************//** +** \brief Initializes the LED. The board doesn't have a dedicted LED so an +** indicator on the LCD is used instead. +** \return none. +** +****************************************************************************************/ +void LedInit(void) +{ + /* enable LEDs connected to PORTB */ + DDRJ_DDRJ1 = 1; + PTJ_PTJ1 = 0; + /* configure PB0 as a digital output */ + DDRB_BIT0 = 1; + /* turn off the LED by default */ + PORTB_BIT0 = 0; +} /*** end of LedInit ***/ + + +/************************************************************************************//** +** \brief Toggles the LED at a fixed time interval. +** \return none. +** +****************************************************************************************/ +void LedToggle(void) +{ + static unsigned char led_toggle_state = 0; + static unsigned long timer_counter_last = 0; + unsigned long timer_counter_now; + + /* check if toggle interval time passed */ + timer_counter_now = TimeGet(); + if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS) + { + /* not yet time to toggle */ + return; + } + + /* determine toggle action */ + if (led_toggle_state == 0) + { + led_toggle_state = 1; + /* turn the LED on */ + PORTB_BIT0 = 1; + + } + else + { + led_toggle_state = 0; + /* turn the LED off */ + PORTB_BIT0 = 0; + } + + /* store toggle time to determine next toggle interval */ + timer_counter_last = timer_counter_now; +} /*** end of LedToggle ***/ + + +/*********************************** end of led.c **************************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/led.h b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/led.h new file mode 100644 index 00000000..b37ee8f8 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/led.h @@ -0,0 +1,44 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\led.h +* \brief LED driver header file. +* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef LED_H +#define LED_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void LedInit(void); +void LedToggle(void); + + +#endif /* LED_H */ +/*********************************** end of led.h **************************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/datapage.c b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/datapage.c new file mode 100644 index 00000000..00246a94 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/datapage.c @@ -0,0 +1,1981 @@ +/****************************************************************************** + FILE : datapage.c + PURPOSE : paged data access runtime routines + MACHINE : Freescale 68HC12 (Target) + LANGUAGE : ANSI-C + HISTORY : 21.7.96 first version created +******************************************************************************/ + +#include "hidef.h" + +#include "non_bank.sgm" +#include "runtime.sgm" + +/*lint --e{957} , MISRA 8.1 REQ, these are runtime support functions and, as such, are not meant to be called in user code; they are only invoked via jumps, in compiler-generated code */ +/*lint -estring(553, __OPTION_ACTIVE__) , MISRA 19.11 REQ , __OPTION_ACTIVE__ is a built-in compiler construct to check for active compiler options */ + +#ifndef __HCS12X__ /* it's different for the HCS12X. See the text below at the #else // __HCS12X__ */ + +/* + According to the -Cp option of the compiler the + __DPAGE__, __PPAGE__ and __EPAGE__ macros are defined. + If none of them is given as argument, then no page accesses should occur and + this runtime routine should not be used ! + To be on the save side, the runtime routines are created anyway. +*/ + +/* Compile with option -DHCS12 to activate this code */ +#if defined(HCS12) || defined(_HCS12) || defined(__HCS12__) +#ifndef PPAGE_ADDR +#ifdef __PPAGE_ADR__ +#define PPAGE_ADDR __PPAGE_ADR__ +#else +#define PPAGE_ADDR (0x30 + REGISTER_BASE) +#endif +#endif +#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ +#define __PPAGE__ +#endif +/* Compile with option -DDG128 to activate this code */ +#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */ +#ifndef PPAGE_ADDR +#define PPAGE_ADDR (0xFF+REGISTER_BASE) +#endif +#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */ +#define __PPAGE__ +#endif +#elif defined(HC812A4) +/* all setting default to A4 already */ +#endif + + +#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__) +/* as default use all page registers */ +#define __DPAGE__ +#define __EPAGE__ +#define __PPAGE__ +#endif + +/* modify the following defines to your memory configuration */ + +#define EPAGE_LOW_BOUND 0x400u +#define EPAGE_HIGH_BOUND 0x7ffu + +#define DPAGE_LOW_BOUND 0x7000u +#define DPAGE_HIGH_BOUND 0x7fffu + +#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1u) +#define PPAGE_HIGH_BOUND 0xBFFFu + +#ifndef REGISTER_BASE +#define REGISTER_BASE 0x0u +#endif + +#ifndef DPAGE_ADDR +#define DPAGE_ADDR (0x34u+REGISTER_BASE) +#endif +#ifndef EPAGE_ADDR +#define EPAGE_ADDR (0x36u+REGISTER_BASE) +#endif +#ifndef PPAGE_ADDR +#define PPAGE_ADDR (0x35u+REGISTER_BASE) +#endif + +/* + The following parts about the defines are assumed in the code of _GET_PAGE_REG : + - the memory region controlled by DPAGE is above the area controlled by the EPAGE and + below the area controlled by the PPAGE. + - the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1 +*/ +#if (EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND) || (EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND) || (DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND) || (DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND) || (PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND) +#error /* please adapt _GET_PAGE_REG for this non default page configuration */ +#endif + +#if (DPAGE_HIGH_BOUND+1u) != PPAGE_LOW_BOUND +#error /* please adapt _GET_PAGE_REG for this non default page configuration */ +#endif + + +/* this module does either control if any access is in the bounds of the specified page or */ +/* ,if only one page is specified, just use this page. */ +/* This behavior is controlled by the define USE_SEVERAL_PAGES. */ +/* If !USE_SEVERAL_PAGES does increase the performance significantly */ +/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */ +/* by this single page. But this is should not cause problems because the page is restored to the old value before any other access could occur */ + +#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__) +/* no page at all is specified */ +/* only specifying the right pages will speed up these functions a lot */ +#define USE_SEVERAL_PAGES 1 +#elif (defined(__DPAGE__) && defined(__EPAGE__)) || (defined(__DPAGE__) && defined(__PPAGE__)) || (defined(__EPAGE__) && defined(__PPAGE__)) +/* more than one page register is used */ +#define USE_SEVERAL_PAGES 1 +#else + +#define USE_SEVERAL_PAGES 0 + +#if defined(__DPAGE__) /* check which pages are used */ +#define PAGE_ADDR PPAGE_ADDR +#elif defined(__EPAGE__) +#define PAGE_ADDR EPAGE_ADDR +#elif defined(__PPAGE__) +#define PAGE_ADDR PPAGE_ADDR +#else /* we do not know which page, decide it at runtime */ +#error /* must not happen */ +#endif + +#endif + + +#if USE_SEVERAL_PAGES /* only needed for several pages support */ +/*--------------------------- _GET_PAGE_REG -------------------------------- + Runtime routine to detect the right register depending on the 16 bit offset part + of an address. + This function is only used by the functions below. + + Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced. + + Arguments : + - Y : offset part of an address + + Result : + if address Y is controlled by a page register : + - X : address of page register if Y is controlled by an page register + - Zero flag cleared + - all other registers remain unchanged + + if address Y is not controlled by a page register : + - Zero flag is set + - all registers remain unchanged + + --------------------------- _GET_PAGE_REG ----------------------------------*/ + +#if defined(__DPAGE__) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_DPAGE: + CPY #DPAGE_LOW_BOUND ;/* test of lower bound of DPAGE */ +#if defined(__EPAGE__) + BLO L_EPAGE ;/* EPAGE accesses are possible */ +#else + BLO L_NOPAGE ;/* no paged memory below accesses */ +#endif + CPY #DPAGE_HIGH_BOUND ;/* test of higher bound DPAGE/lower bound PPAGE */ +#if defined(__PPAGE__) + BHI L_PPAGE ;/* EPAGE accesses are possible */ +#else + BHI L_NOPAGE ;/* no paged memory above accesses */ +#endif +FOUND_DPAGE: + LDX #DPAGE_ADDR ;/* load page register address and clear zero flag */ + RTS + +#if defined(__PPAGE__) +L_PPAGE: + CPY #PPAGE_HIGH_BOUND ;/* test of higher bound of PPAGE */ + BHI L_NOPAGE +FOUND_PPAGE: + LDX #PPAGE_ADDR ;/* load page register address and clear zero flag */ + RTS +#endif + +#if defined(__EPAGE__) +L_EPAGE: + CPY #EPAGE_LOW_BOUND ;/* test of lower bound of EPAGE */ + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ;/* test of higher bound of EPAGE */ + BHI L_NOPAGE + +FOUND_EPAGE: + LDX #EPAGE_ADDR ;/* load page register address and clear zero flag */ + RTS +#endif + +L_NOPAGE: + ORCC #0x04 ;/* sets zero flag */ + RTS + } +} + +#else /* !defined(__DPAGE__) */ + +#if defined( __PPAGE__ ) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_PPAGE: + CPY #PPAGE_LOW_BOUND ;/* test of lower bound of PPAGE */ +#if defined( __EPAGE__ ) + BLO L_EPAGE +#else + BLO L_NOPAGE ;/* no paged memory below */ +#endif + CPY #PPAGE_HIGH_BOUND ;/* test of higher bound PPAGE */ + BHI L_NOPAGE +FOUND_PPAGE: + LDX #PPAGE_ADDR ;/* load page register address and clear zero flag */ + RTS +#if defined( __EPAGE__ ) +L_EPAGE: + CPY #EPAGE_LOW_BOUND ;/* test of lower bound of EPAGE */ + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ;/* test of higher bound of EPAGE */ + BHI L_NOPAGE +FOUND_EPAGE: + LDX #EPAGE_ADDR ;/* load page register address and clear zero flag */ + RTS +#endif + +L_NOPAGE: ;/* not in any allowed page area */ + ;/* its a far access to a non paged variable */ + ORCC #0x04 ;/* sets zero flag */ + RTS + } +} + +#else /* !defined(__DPAGE__ ) && !defined( __PPAGE__) */ +#if defined(__EPAGE__) + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */ + asm { +L_EPAGE: + CPY #EPAGE_LOW_BOUND ;/* test of lower bound of EPAGE */ + BLO L_NOPAGE + CPY #EPAGE_HIGH_BOUND ;/* test of higher bound of EPAGE */ + BHI L_NOPAGE +FOUND_EPAGE: + LDX #EPAGE_ADDR ;/* load page register address and clear zero flag */ + RTS + +L_NOPAGE: ;/* not in any allowed page area */ + ;/* its a far access to a non paged variable */ + ORCC #0x04 ;/* sets zero flag */ + RTS + } +} + +#endif /* defined(__EPAGE__) */ +#endif /* defined(__PPAGE__) */ +#endif /* defined(__DPAGE__) */ + +#endif /* USE_SEVERAL_PAGES */ + +/*--------------------------- _SET_PAGE -------------------------------- + Runtime routine to set the right page register. This routine is used if the compiler + does not know the right page register, i.e. if the option -Cp is used for more than + one page register or if the runtime option is used for one of the -Cp options. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - page part written into the correct page register. + - the old page register content is destroyed + - all processor registers remains unchanged + --------------------------- _SET_PAGE ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _SET_PAGE(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + STAB 0,X ;/* set page register */ +L_NOPAGE: + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + STAB PAGE_ADDR ;/* set page register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _LOAD_FAR_8 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the B register + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_8 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_8(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ;/* save A register */ + LDAA 0,X ;/* save page register */ + STAB 0,X ;/* set page register */ + LDAB 0,Y ;/* actual load, overwrites page */ + STAA 0,X ;/* restore page register */ + PULA ;/* restore A register */ + PULX ;/* restore X register */ + RTS +L_NOPAGE: + LDAB 0,Y ;/* actual load, overwrites page */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ;/* save A register */ + LDAA PAGE_ADDR ;/* save page register */ + STAB PAGE_ADDR ;/* set page register */ + LDAB 0,Y ;/* actual load, overwrites page */ + STAA PAGE_ADDR ;/* restore page register */ + PULA ;/* restore A register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _LOAD_FAR_16 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the Y register + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_16 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_16(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ;/* save A register */ + LDAA 0,X ;/* save page register */ + STAB 0,X ;/* set page register */ + LDY 0,Y ;/* actual load, overwrites address */ + STAA 0,X ;/* restore page register */ + PULA ;/* restore A register */ + PULX ;/* restore X register */ + RTS +L_NOPAGE: + LDY 0,Y ;/* actual load, overwrites address */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ;/* save A register */ + LDAA PAGE_ADDR ;/* save page register */ + STAB PAGE_ADDR ;/* set page register */ + LDY 0,Y ;/* actual load, overwrites address */ + STAA PAGE_ADDR ;/* restore page register */ + PULA ;/* restore A register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _LOAD_FAR_24 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - value to be read in the Y:B registers + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_24 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_24(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHA ;/* save A register */ + LDAA 0,X ;/* save page register */ + STAB 0,X ;/* set page register */ + LDAB 0,Y ;/* actual load, overwrites page of address */ + LDY 1,Y ;/* actual load, overwrites offset of address */ + STAA 0,X ;/* restore page register */ + PULA ;/* restore A register */ + PULX ;/* restore X register */ + RTS +L_NOPAGE: + LDAB 0,Y ;/* actual load, overwrites page of address */ + LDY 1,Y ;/* actual load, overwrites offset of address */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ;/* save A register */ + LDAA PAGE_ADDR ;/* save page register */ + STAB PAGE_ADDR ;/* set page register */ + LDAB 0,Y ;/* actual load, overwrites page of address */ + LDY 1,Y ;/* actual load, overwrites offset of address */ + STAA PAGE_ADDR ;/* restore page register */ + PULA ;/* restore A register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ + +} + +/*--------------------------- _LOAD_FAR_32 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + + Result : + - low 16 bit of value to be read in the D registers + - high 16 bit of value to be read in the Y registers + - all other registers remains unchanged + - all page register still contain the same value + --------------------------- _LOAD_FAR_32 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _LOAD_FAR_32(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + LDAA 0,X ;/* save page register */ + PSHA ;/* put it onto the stack */ + STAB 0,X ;/* set page register */ + LDD 2,Y ;/* actual load, low word */ + LDY 0,Y ;/* actual load, high word */ + MOVB 1,SP+,0,X ;/* restore page register */ + PULX ;/* restore X register */ + RTS +L_NOPAGE: + LDD 2,Y ;/* actual load, low word */ + LDY 0,Y ;/* actual load, high word */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + LDAA PAGE_ADDR ;/* save page register */ + PSHA ;/* put it onto the stack */ + STAB PAGE_ADDR ;/* set page register */ + LDD 2,Y ;/* actual load, low word */ + LDY 0,Y ;/* actual load, high word */ + MOVB 1,SP+,PAGE_ADDR ;/* restore page register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _STORE_FAR_8 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the B register + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_8 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_8(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + PSHB ;/* save B register */ + LDAB 0,X ;/* save page register */ + MOVB 0,SP, 0,X ;/* set page register */ + STAA 0,Y ;/* store the value passed in A */ + STAB 0,X ;/* restore page register */ + PULB ;/* restore B register */ + PULX ;/* restore X register */ + RTS +L_NOPAGE: + STAA 0,Y ;/* store the value passed in A */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHB ;/* save A register */ + LDAB PAGE_ADDR ;/* save page register */ + MOVB 0,SP,PAGE_ADDR ;/* set page register */ + STAA 0,Y ;/* store the value passed in A */ + STAB PAGE_ADDR ;/* restore page register */ + PULB ;/* restore B register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _STORE_FAR_16 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the X register + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_16 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_16(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHA + LDAA 0,X ;/* save page register */ + STAB 0,X ;/* set page register */ + MOVW 1,SP,0,Y ;/* store the value passed in X */ + STAA 0,X ;/* restore page register */ + PULA ;/* restore A register */ + PULX ;/* restore X register */ + RTS + +L_NOPAGE: + STX 0,Y ;/* store the value passed in X */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ;/* save A register */ + LDAA PAGE_ADDR ;/* save page register */ + STAB PAGE_ADDR ;/* set page register */ + STX 0,Y ;/* store the value passed in X */ + STAA PAGE_ADDR ;/* restore page register */ + PULA ;/* restore A register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _STORE_FAR_24 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address in the B register + - value to be stored in the X:A registers (X : low 16 bit, A : high 8 bit) + + Result : + - value stored at the address + - all registers remains unchanged + - all page register still contain the same value + --------------------------- _STORE_FAR_24 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_24(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHA + LDAA 0,X ;/* save page register */ + STAB 0,X ;/* set page register */ + MOVW 1,SP, 1,Y ;/* store the value passed in X */ + MOVB 0,SP, 0,Y ;/* store the value passed in A */ + STAA 0,X ;/* restore page register */ + PULA ;/* restore A register */ + PULX ;/* restore X register */ + RTS + +L_NOPAGE: + STX 1,Y ;/* store the value passed in X */ + STAA 0,Y ;/* store the value passed in X */ + PULX ;/* restore X register */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHA ;/* save A register */ + LDAA PAGE_ADDR ;/* save page register */ + STAB PAGE_ADDR ;/* set page register */ + MOVB 0,SP, 0,Y ;/* store the value passed in A */ + STX 1,Y ;/* store the value passed in X */ + STAA PAGE_ADDR ;/* restore page register */ + PULA ;/* restore A register */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} +/*--------------------------- _STORE_FAR_32 -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of an address in the Y register + - page part of an address is on the stack at 3,SP (just below the return address) + - value to be stored in the X:D registers (D : low 16 bit, X : high 16 bit) + + Result : + - value stored at the address + - all registers remains unchanged + - the page part is removed from the stack + - all page register still contain the same value + --------------------------- _STORE_FAR_32 ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _STORE_FAR_32(void) { +#if USE_SEVERAL_PAGES + asm { + PSHX ;/* save X register */ + __PIC_JSR(_GET_PAGE_REG) + BEQ L_NOPAGE + + PSHD + LDAA 0,X ;/* save page register */ + MOVB 6,SP, 0,X ;/* set page register */ + MOVW 2,SP, 0,Y ;/* store the value passed in X (high word) */ + MOVW 0,SP, 2,Y ;/* store the value passed in D (low word) */ + STAA 0,X ;/* restore page register */ + PULD ;/* restore A register */ + BRA done + +L_NOPAGE: + MOVW 0,SP, 0,Y ;/* store the value passed in X (high word) */ + STD 2,Y ;/* store the value passed in D (low word) */ +done: + PULX ;/* restore X register */ + MOVW 0,SP, 1,+SP ;/* move return address */ + RTS + } +#else /* USE_SEVERAL_PAGES */ + asm { + PSHD ;/* save D register */ + LDAA PAGE_ADDR ;/* save page register */ + LDAB 4,SP ;/* load page part of address */ + STAB PAGE_ADDR ;/* set page register */ + STX 0,Y ;/* store the value passed in X */ + MOVW 0,SP, 2,Y ;/* store the value passed in D (low word) */ + STAA PAGE_ADDR ;/* restore page register */ + PULD ;/* restore D register */ + MOVW 0,SP, 1,+SP ;/* move return address */ + RTS + } +#endif /* USE_SEVERAL_PAGES */ +} + +/*--------------------------- _FAR_COPY_RC -------------------------------- + This runtime routine is used to access paged memory via a runtime function. + It may also be used if the compiler option -Cp is not used with the runtime argument. + + Arguments : + - offset part of the source int the X register + - page part of the source in the A register + - offset part of the dest int the Y register + - page part of the dest in the B register + - number of bytes to be copied is defined by the next 2 bytes after the return address. + + Result : + - memory area copied + - no registers are saved, i.e. all registers may be destroyed + - all page register still contain the same value as before the call + - the function returns after the constant defining the number of bytes to be copied + + + stack-structure at the loop-label: + 0,SP : destination offset + 2,SP : source page + 3,SP : destination page + 4,SP : source offset + 6,SP : points to length to be copied. This function returns after the size + + A usual call to this function looks like: + + struct Huge src, dest; + ; ... + LDX #src + LDAA #PAGE(src) + LDY #dest + LDAB #PAGE(dest) + JSR _FAR_COPY_RC + DC.W sizeof(struct Huge) + ; ... + + --------------------------- _FAR_COPY_RC ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_RC(void) { +#if USE_SEVERAL_PAGES + asm { + DEX ;/* source addr-=1, because loop counter ends at 1 */ + PSHX ;/* save source offset */ + PSHD ;/* save both pages */ + DEY ;/* destination addr-=1, because loop counter ends at 1 */ + PSHY ;/* save destination offset */ + LDY 6,SP ;/* Load Return address */ + LDX 2,Y+ ;/* Load Size to copy */ + STY 6,SP ;/* Store adjusted return address */ +loop: + LDD 4,SP ;/* load source offset */ + LEAY D,X ;/* calculate actual source address */ + LDAB 2,SP ;/* load source page */ + __PIC_JSR(_LOAD_FAR_8) ;/* load 1 source byte */ + PSHB ;/* save value */ + LDD 0+1,SP ;/* load destination offset */ + LEAY D,X ;/* calculate actual destination address */ + PULA ;/* restore value */ + LDAB 3,SP ;/* load destination page */ + __PIC_JSR(_STORE_FAR_8) ;/* store one byte */ + DEX + BNE loop + LEAS 6,SP ;/* release stack */ + _SRET ;/* debug info only: This is the last instr of a function with a special return */ + RTS ;/* return */ + } +#else + asm { + PSHD ;/* store page registers */ + TFR X,D + PSHY ;/* temporary space */ + LDY 4,SP ;/* load return address */ + ADDD 2,Y+ ;/* calculate source end address. Increment return address */ + STY 4,SP + PULY + PSHD ;/* store src end address */ + LDAB 2,SP ;/* reload source page */ + LDAA PAGE_ADDR ;/* save page register */ + PSHA +loop: + STAB PAGE_ADDR ;/* set source page */ + LDAA 1,X+ ;/* load value */ + MOVB 4,SP, PAGE_ADDR ;/* set destination page */ + STAA 1,Y+ + CPX 1,SP + BNE loop + + LDAA 5,SP+ ;/* restore old page value and release stack */ + STAA PAGE_ADDR ;/* store it into page register */ + _SRET ;/* debug info only: This is the last instr of a function with a special return */ + RTS + } +#endif +} + +/*--------------------------- _FAR_COPY -------------------------------- + + The _FAR_COPY runtime routine was used to copied large memory blocks in previous compiler releases. + However this release now does use _FAR_COPY_RC instead. The only difference is how the size of + the area to be copied is passed into the function. For _FAR_COPY the size is passed on the stack just + above the return address. _FAR_COPY_RC does expect the return address just after the JSR _FAR_COPY_RC call + in the code of the caller. This allows for denser code calling _FAR_COPY_RC but does also need a slightly + larger runtime routine and it is slightly slower. + The _FAR_COPY routine is here now mainly for compatibility with previous releases. + The current compiler does not use it. + +--------------------------- _FAR_COPY ----------------------------------*/ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY(void) { +#if USE_SEVERAL_PAGES + asm { + DEX ;/* source addr-=1, because loop counter ends at 1 */ + PSHX ;/* save source offset */ + PSHD ;/* save both pages */ + DEY ;/* destination addr-=1, because loop counter ends at 1 */ + PSHY ;/* save destination offset */ + LDX 8,SP ;/* load counter, assuming counter > 0 */ + +loop: + LDD 4,SP ;/* load source offset */ + LEAY D,X ;/* calculate actual source address */ + LDAB 2,SP ;/* load source page */ + __PIC_JSR(_LOAD_FAR_8) ;/* load 1 source byte */ + PSHB ;/* save value */ + LDD 0+1,SP ;/* load destination offset */ + LEAY D,X ;/* calculate actual destination address */ + PULA ;/* restore value */ + LDAB 3,SP ;/* load destination page */ + __PIC_JSR(_STORE_FAR_8) ;/* store one byte */ + DEX + BNE loop + LDX 6,SP ;/* load return address */ + LEAS 10,SP ;/* release stack */ + JMP 0,X ;/* return */ + } +#else + asm { + PSHD ;/* store page registers */ + TFR X,D + ADDD 4,SP ;/* calculate source end address */ + STD 4,SP + PULB ;/* reload source page */ + LDAA PAGE_ADDR ;/* save page register */ + PSHA +loop: + STAB PAGE_ADDR ;/* set source page */ + LDAA 1,X+ ;/* load value */ + MOVB 1,SP, PAGE_ADDR ;/* set destination page */ + STAA 1,Y+ + CPX 4,SP + BNE loop + + LDAA 2,SP+ ;/* restore old page value and release stack */ + STAA PAGE_ADDR ;/* store it into page register */ + LDX 4,SP+ ;/* release stack and load return address */ + JMP 0,X ;/* return */ + } +#endif +} + +#else /* __HCS12X__ */ + +/* + The HCS12X knows two different kind of addresses: + - Logical addresses. E.g. + MOVB #page(var),RPAGE + INC var + + - Global addresses E.g. + MOVB #page(var),GPAGE + GLDAA var + INCA + GSTAA var + + Global addresses are used with G-Load's and G-Store's, logical addresses are used for all the other instructions + and occasions. As HC12's or HCS12's do not have the G-Load and G-Store instructions, + global addresses are not used with these processor families. + They are only used with HCS12X chips (and maybe future ones deriving from a HCS12X). + + Logical and Global addresses can point to the same object, however the global and logical address of an object + are different for most objects (actually for all except the registers from 0 to 0x7FF). + Therefore the compiler needs to transform in between them. + + HCS12X Pointer types: + + The following are logical addresses: + - all 16 bit pointers + - "char* __near": always. + - "char *" in the small and banked memory model + - 24 bit dpage, epage, ppage or rpage pointers (*1) (note: the first HCS12X compilers may not support these pointer types) + - "char *__dpage": Note this type only exists for + orthogonality with the HC12 A4 chip which has a DPAGE reg. + It does not apply to the HCS12X. + - "char *__epage": 24 bit pointer using the EPAGE register + - "char *__ppage": 24 bit pointer using the PPAGE register. + As the PPAGE is also used for BANKED code, + using this pointer type is only legal from non banked code. + - "char *__rpage": 24 bit pointer using the RPAGE register + + + The following are global addresses: + "char*": in the large memory model (only HCS12X) + "char* __far": always for HCS12X. + + (*1): For the HC12 and HCS12 "char* __far" and "char*" in the large memory model are also logical. + + Some notes for the HC12/HCS12 programmers. + + The address of a far object for a HC12 and for a HCS12X is different, even if they are at the same place in the memory map. + For the HC12, a far address is using the logical addresses, for the HCS12X however, far addresses are using global addresses. + This does cause troubles for the unaware! + + The conversion routines implemented in this file support the special HCS12XE RAM mapping (when RAMHM is set). + To enable this mapping compile this file with the "-MapRAM" compiler option. + + HCS12X Logical Memory map + + Logical Addresses Used for shadowed at page register Global Address + + 0x000000 .. 0x0007FF Peripheral Registers Not Paged 0x000000 + 0x??0800 .. 0x??0BFF Paged EEPROM EPAGE (@0x17) 0x100000+EPAGE*0x0400 + 0x000C00 .. 0x000FFF Non Paged EEPROM 0xFF0800..0xFF0FFF Not Paged 0x13FC00 + 0x??1000 .. 0x??1FFF Paged RAM RPAGE (@0x16) 0x000000+RPAGE*0x1000 + 0x002000 .. 0x003FFF Non Paged RAM 0xFE1000..0xFF1FFF Not Paged 0x0FE000 + 0x004000 .. 0x007FFF Non Paged FLASH 0xFC8000..0xFCBFFF Not Paged 0x7F4000 + 0x??8000 .. 0x00BFFF Paged FLASH PPAGE (@0x30) 0x400000+PPAGE*0x4000 + 0x00C000 .. 0x00FFFF Non Paged FLASH 0xFF8000..0xFFBFFF Not Paged 0x7FC000 + + NA: Not Applicable + + HCS12X Global Memory map + + Global Addresses Used for Logical mapped at + + 0x000000 .. 0x0007FF Peripheral Registers 0x000000 .. 0x0007FF + 0x000800 .. 0x000FFF DMA registers Not mapped + 0x001000 .. 0x0FFFFF RAM 0x??1000 .. 0x??1FFF + 0x0FE000 .. 0x0FFFFF RAM, Log non paged 0x002000 .. 0x003FFF + 0x100000 .. 0x13FFFF EEPROM 0x??0800 .. 0x??0BFF + 0x13FC00 .. 0x13FFFF EEPROM non paged 0x000C00 .. 0x000FFF + 0x140000 .. 0x3FFFFF External Space Not mapped + 0x400000 .. 0x7FFFFF FLASH 0x??8000 .. 0x??BFFF + 0x7F4000 .. 0x7F7FFF FLASH, Log non paged 0x004000 .. 0x007FFF + 0x7FC000 .. 0x7FFFFF FLASH, Log non paged 0x00C000 .. 0x00FFFF + + HCS12XE Logical Memory map (with RAMHM set) + + Logical Addresses Used for shadowed at page register Global Address + + 0x000000 .. 0x0007FF Peripheral Registers Not Paged 0x000000 + 0x??0800 .. 0x??0BFF Paged EEPROM EPAGE 0x100000+EPAGE*0x0400 + 0x000C00 .. 0x000FFF Non Paged EEPROM 0xFF0800..0xFF0FFF Not Paged 0x13FC00 + 0x??1000 .. 0x??1FFF Paged RAM RPAGE 0x000000+RPAGE*0x1000 + 0x002000 .. 0x003FFF Non Paged RAM 0xFA1000..0xFB1FFF Not Paged 0x0FA000 + 0x004000 .. 0x007FFF Non Paged RAM 0xFC1000..0xFF1FFF Not Paged 0x0FC000 + 0x??8000 .. 0x00BFFF Paged FLASH PPAGE 0x400000+PPAGE*0x4000 + 0x00C000 .. 0x00FFFF Non Paged FLASH 0xFF8000..0xFFBFFF Not Paged 0x7FC000 + + NA: Not Applicable + + HCS12X Global Memory map (with RAMHM set) + + Global Addresses Used for Logical mapped at + + 0x000000 .. 0x0007FF Peripheral Registers 0x000000 .. 0x0007FF + 0x000800 .. 0x000FFF DMA registers Not mapped + 0x001000 .. 0x0FFFFF RAM 0x??1000 .. 0x??1FFF + 0x0FA000 .. 0x0FFFFF RAM, Log non paged 0x002000 .. 0x007FFF + 0x100000 .. 0x13FFFF EEPROM 0x??0800 .. 0x??0BFF + 0x13FC00 .. 0x13FFFF EEPROM non paged 0x000C00 .. 0x000FFF + 0x140000 .. 0x3FFFFF External Space Not mapped + 0x400000 .. 0x7FFFFF FLASH 0x??8000 .. 0x??BFFF + 0x7F4000 .. 0x7F7FFF FLASH, Log non paged Not mapped + 0x7FC000 .. 0x7FFFFF FLASH, Log non paged 0x00C000 .. 0x00FFFF + + + How to read this table: + For logical addresses, the lower 16 bits of the address do determine in which area the address is, + if this address is paged, then this entry also controls and which of the EPAGE, PPAGE or RPAGE + page register is controlling the bits 16 to 23 of the address. + For global addresses, the bits 16 to 23 have to be in the GPAGE register and the lower 16 bits + have to be used with the special G load or store instructions (e.g. GLDAA). + As example the logical address 0x123456 is invalid. Because its lower bits 0x3456 are in a + non paged area, so the page 0x12 does not exist. + The address 0xFE1020 however does exist. To access it, the RPAGE has to contain 0xFE and the + offset 0x1020 has to be used. + + ORG $7000 + MOVB #0xFE, 0x16 ; RPAGE + LDAA 0x1020 ; reads at the logical address 0xFE1020 + + Because the last two RAM pages are also accessible directly from 0x2000 to 0x3FFF, the + following shorter code does read the same memory location: + + ORG $7000 + LDAA 0x2020 ; reads at the logical address 0x2020 + ; which maps to the same memory as 0xFE1020 + + This memory location also has a global address. For logical 0xFE1020 the global address is 0x0FE020. + So the following code does once more access the same memory location: + + ORG $7000 + MOVB #0x0F, 0x10 ; GPAGE + GLDAA 0xE020 ; reads at the global address 0x0FE020 + ; which maps to the same memory as the logical addr. 0xFE1020 + + Therefore every memory location for the HCS12X has up to 3 different addresses. + Up to two logical and one global. + Notes. + - Not every address has a logical equivalent. The external space is only available in the global address space. + + - The PPAGE must only be set if the code is outside of the 0x8000 to 0xBFFF range. + If not, the next code fetch will be from the new wrong PPAGE value. + + - Inside of the paged area, the highest pages are allocated first. So all HCS12X's do have the FF pages + (if they have this memory type at all). + + - For RPAGE, the value 0 is illegal. Otherwise the global addresses would overlap with the registers. + +*/ + +/*lint -e10, -e106, -e30 */ +#if __OPTION_ACTIVE__("-MapRAM") +#define __HCS12XE_RAMHM_SET__ +#endif +/*lint +e10, +e106, +e30 */ + +/*--------------------------- pointer conversion operations -------------------------------*/ + +/*--------------------------- _CONV_GLOBAL_TO_LOGICAL -------------------------------- + Convert 24 bit logical to 24 bit global pointer + ("char*__far" to "char*__gpage") + + Arguments : + - B : page part of global address + - X : 16 offset part of global address + + Postcondition : + - B == page of returned logical address + - X == offset of returned logical address + - Y remains unchanged + - A remains unchanged +*/ +/*--------------------------- Convert 24 bit global to 24 bit logical pointer ----------------------------------*/ + +/* B:X = Logical(B:X) */ +#ifdef __cplusplus +extern "C" +#endif + +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +void NEAR _CONV_GLOBAL_TO_LOGICAL(void) { + asm { + CMPB #0x40 ;/* flash (0x400000..0x7FFFFF) or not? */ + BLO Below400000 +/* from 0x400000 to 0x7FFFFF */ + CMPB #0x7F ;/* check for Unpaged areas 0x7FC000..0x7FFFFF and 0x7F4000..0x7F7FFF */ + BNE PAGED_FLASH_AREA +#ifndef __HCS12XE_RAMHM_SET__ + BITX #0x4000 + BEQ PAGED_FLASH_AREA +#else + CPX #0xC000 + BLO PAGED_FLASH_AREA +#endif +/* from 0x7F4000 to 0x7F7FFF or 0x7FC000 to 0x7FFFFF */ + ;/* Note: offset in X is already OK. */ + CLRB ;/* logical page == 0 */ + RTS +PAGED_FLASH_AREA: ;/* paged flash. Map to 0x8000..0xBFFF */ +/* from 0x400000 to 0x7F3FFF or 0x7F8000 to 0x7FBFFF */ + LSLX ; /* shift 24 bit address 2 bits to the left to get correct page in B */ + ROLB + LSLX + ROLB + LSRX ; /* shift back to get offset from 0x8000 to 0xBFFF */ + SEC + RORX + RTS ;/* done */ + +Below400000: +/* from 0x000000 to 0x3FFFFF */ +#if 0 /* How should we handle mapping to External Space. There is no logical equivalent. This is an error case! */ + CMPB #0x14 ;/* check if above 0x140000. If so, its in the external space */ + BLO Below140000 + ERROR !!!! ;/* this mapping is not possible! What should we do? */ + RTS +Below140000: +/* from 0x000000 to 0x13FFFF */ +#endif + CMPB #0x10 ;/* if >= 0x100000 it's EEPROM */ + BLO Below100000 +/* from 0x100000 to 0x13FFFF (or 0x3FFFFF) */ + CMPB #0x13 ;/* check if its is in the non paged EEPROM area at 0x13FC00..0x13FFFF */ + BLO Below13FC00 + CPX #0xFC00 + BLO Below13FC00 +/* from 0x13FC00 to 0x13FFFF (or 0x3FFFFF) */ + LEAX 0x1000,X ;/* same as SUBX #0xF000 // map from 0xFC00 to 0x0C00 */ + CLRB + RTS +Below13FC00: +/* from 0x100000 to 0x13FBFF */ + PSHA + TFR XH,A ;/* calculate logical page */ + EXG A,B + LSRD + LSRD + PULA + ANDX #0x03FF + LEAX 0x0800,X ;/* same as ORX #0x0800 */ + RTS + +Below100000: +/* from 0x000000 to 0x0FFFFF */ + TSTB + BNE RAM_AREA + CPX #0x1000 + BLO Below001000 +RAM_AREA: +/* from 0x001000 to 0x0FFFFF */ + CMPB #0x0F + BNE PagedRAM_AREA +#ifndef __HCS12XE_RAMHM_SET__ + CPX #0xE000 + BLO PagedRAM_AREA +/* from 0x0FE000 to 0x0FFFFF */ + SUBX #(0xE000-0x2000) ;/* map 0xE000 to 0x2000 */ +#else + CPX #0xA000 + BLO PagedRAM_AREA +/* from 0x0FA000 to 0x0FFFFF */ + SUBX #(0xA000-0x2000) ;/* map 0xA000 to 0x2000 */ +#endif + CLRB ;/* Page is 0 */ + RTS +PagedRAM_AREA: +/* from 0x001000 to 0x0FDFFF */ + PSHA + TFR XH, A ;/* calculate logical page */ + EXG A,B + LSRD + LSRD + LSRD + LSRD + PULA + + ANDX #0x0FFF + LEAX 0x1000,X ;/* same as ORX #0x1000 */ + RTS + +Below001000: +/* from 0x000000 to 0x000FFF */ +#if 0 + CMPA #0x08 + BLO Below000800 +/* from 0x000800 to 0x000FFF */ + /* ??? DMA Regs? */ + RTS +Below000800: +/* from 0x000000 to 0x0007FF */ +#endif + CLRB + RTS + } +} + +/*--------------------------- _CONV_GLOBAL_TO_NEAR -------------------------------- + Convert 24 bit global to 16 bit logical pointer + ("char*__far" to "char*") + + Arguments : + - B : page part of global address + - X : 16 offset part of global address + + Postcondition : + - B is undefined + - A remains unchanged + - X == offset of returned logical address + - Y remains unchanged +*/ +/*--------------------------- Convert 24 bit global to 16 bit logical pointer ----------------------------------*/ + +/* X = Logical(B:X) */ + +#ifdef __cplusplus +extern "C" +#endif + +#define _REUSE_CONV_GLOBAL_TO_LOGICAL 1 + +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +void NEAR _CONV_GLOBAL_TO_NEAR(void){ +#if _REUSE_CONV_GLOBAL_TO_LOGICAL /* do we want an optimized version? */ + __asm JMP _CONV_GLOBAL_TO_LOGICAL; /* offset for NEAR is same as for LOGICAL. */ +#else + asm { + CMPB #0x40 ;/* flash (0x400000..0x7FFFFF) or not? */ + BLO Below400000 +/* from 0x400000 to 0x7FFFFF */ +#ifndef __HCS12XE_RAMHM_SET__ + CMPB #0x7F ;/* check for Unpaged areas 0x7FC000..0x7FFFFF and 0x7F4000..0x7F7FFF */ + BNE PAGED_FLASH_AREA + CPX #0x4000 + BLO PAGED_FLASH_AREA +/* from 0x7F4000 to 0x7FFFFF */ +#else + CMPB #0x7F ;/* check for Unpaged area 0x7FC000..0x7FFFFF */ + BNE PAGED_FLASH_AREA + CPX #0xC000 + BLO PAGED_FLASH_AREA +/* from 0x7FC000 to 0x7FFFFF */ +#endif + ;/* note non PAGED flash areas or paged area 0x7F8000..0x7FBFFF which are mapping all correctly */ + RTS +PAGED_FLASH_AREA: ;/* paged flash. Map to 0x8000..0xBFFF */ +/* from 0x400000 to 0x7F3FFF */ + ANDX #0x3F00 ;/* cut to 0.. 0x3FFF */ + LEAX 0x8000,X ;/* same as ORX #0x8000 ;// move to 0x8000..0xBFFF */ + RTS ;/* done */ + +Below400000: +/* from 0x000000 to 0x3FFFFF */ +#if 0 /* How should we handle mapping to External Space. There is no logical equivalent. This is an error case! */ + CMPB #0x14 ;/* check if above 0x140000. If so, its in the external space */ + BLO Below140000 + ERROR !!!! ;/* this mapping is not possible! What should we do? */ + RTS +Below140000: +/* from 0x000000 to 0x13FFFF */ +#endif + CMPB #0x10 ;/* if >= 0x100000 it's EEPROM */ + BLO Below100000 +/* from 0x100000 to 0x13FFFF (or 0x3FFFFF) */ + CMPB #0x13 ;/* check if its is in the non paged EEPROM area at 0x13FC00..0x13FFFF */ + BNE Below13FC00 + CPX #0xFC00 + BLO Below13FC00 +/* from 0x13FC00 to 0x13FFFF (or 0x3FFFFF) */ + SUBX #0xF000 ;/* map from 0xFC00 to 0x0C00 */ + RTS +Below13FC00: +/* from 0x100000 to 0x13FBFF */ + ANDX #0x03FF + LEAX 0x800,X ;/* same as ORX #0x0800 */ + RTS + +Below100000: +/* from 0x000000 to 0x0FFFFF */ + TBNE B,RAM_AREA + CPX #0x1000 + BLO Below001000 +RAM_AREA: +/* from 0x001000 to 0x0FFFFF */ + CMPB #0x0F + BNE PagedRAM_AREA +#ifndef __HCS12XE_RAMHM_SET__ + CPX #0xE000 + BLO PagedRAM_AREA +/* from 0x0FE000 to 0x0FFFFF */ + SUBX #(0xE000-0x2000) ;/* map 0xE000 to 0x2000 */ +#else + CPX #0xA000 + BLO PagedRAM_AREA +/* from 0x0FA000 to 0x0FFFFF */ + SUBX #(0xA000-0x2000) ;/* map 0xA000 to 0x2000 */ +#endif + RTS +PagedRAM_AREA: +/* from 0x001000 to 0x0FDFFF (0x001000 to 0x0F9FFF if HCS12XE RAM mapping is enabled) */ + ANDX #0x0FFF + LEAX 0x1000,X ;/* same as ORX #0x1000 */ + RTS + +Below001000: +/* from 0x000000 to 0x000FFF */ + RTS + } +#endif +} + +/*--------------------------- _CONV_NEAR_TO_GLOBAL -------------------------------- + Convert 16 bit logical to 24 bit global pointer + ("char*__near" to "char*__far") + + Arguments : + - X : 16 bit near pointer + + Postcondition : + - B == page of returned global address + - X == offset of returned global address + - Y remains unchanged + - A is unspecified +*/ +/*--------------------------- Convert 16 bit logical to 24 bit global pointer ----------------------------------*/ + +/* B:X = Global(X) */ + +#ifdef __cplusplus +extern "C" +#endif + +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +void NEAR _CONV_NEAR_TO_GLOBAL(void){ + asm { + /* syntax: */ + /* input 16 bit offset is bit15..bit0 */ + /* ppage values: ppage7..ppage0 */ + /* epage values: epage7..epage0 */ + /* dpage values: dpage7..dpage0 */ + /* rpage values: rpage7..rpage0 */ + PSHX ;/* D contains bit15..bit0 */ + TFR X,D ;/* D is cheaper to shift */ + LSLD ;/* D contains 0 bit14..bit0, C contains bit15 */ + BCC Below8000 ;/* bit15 == 0? */ + /* from 0x8000 to 0xFFFF */ + LSLD ;/* D contains 00 bit13..bit0, C contains bit14 */ + BCC BelowC000 + LDAB #0x7F + PULX + RTS ;/* returns 0b0111 1111 11 bit13...bit0 */ +BelowC000: ;/* from 0x8000 to 0xBFFF */ + TFR D,X + LDAB __PPAGE_ADR__ + SEC + RORB + RORX + LSRB + RORX + LEAS 2,SP + RTS ;/* returns 0b01 ppage7..ppage0 bit13...bit0 */ +Below8000: + LSLD ;/* D contains 00 bit13..bit0, C contains bit14 */ + BCC Below4000 + /* from 0x4000 to 0x7FFF */ + PULX +#ifndef __HCS12XE_RAMHM_SET__ + LDAB #0x7F +#else + LEAX (0xC000-0x4000),X + LDAB #0x0F +#endif + RTS ;/* returns 0b0111 1111 01 bit13...bit0 */ + +Below4000: + LSLD ;/* D contains 000 bit12..bit0, C contains bit13 */ + BCC Below2000 + /* from 0x2000 to 0x3FFF */ + PULX +#ifndef __HCS12XE_RAMHM_SET__ + LEAX (0xE000-0x2000),X +#else + LEAX (0xA000-0x2000),X +#endif + LDAB #0x0F + RTS ;/* returns 0b0000 1111 111 bit12...bit0 */ + +Below2000: + LSLD ;/* D contains 0000 bit11..bit0, C contains bit12 */ + BCC Below1000 + /* from 0x1000 to 0x1FFF */ + LDAB __RPAGE_ADR__ + LDAA #0x10 + MUL + EORB 0,SP + EORB #0x10 ;/* clear 1 bit */ + STAB 0,SP + TFR A,B + PULX + RTS + +Below1000: + LSLD ;/* D contains 0000 0 bit10..bit0, C contains bit11 */ + BCC Below0800 + /* from 0x0800 to 0x0FFF */ + LSLD ;/* D contains 0000 00 bit9..bit0, C contains bit10 */ + BCC Below0C00 + /* from 0x0C00 to 0x0FFF */ + LDAB #0x13 + PULX + LEAX 0xF000,X + RTS ;/* returns 0b0001 0011 1111 11 bit9...bit0 */ +Below0C00: + /* from 0x0800 to 0x0BFF */ + LDAB __EPAGE_ADR__ + LDAA #0x04 + MUL + EORB 0,SP + EORB #0x08 + STAB 0,SP + TFR A,B + ORAB #0b00010000 + PULX + RTS +Below0800: + PULX + CLRB + RTS + } +} + +/*--------------------------- _CONV_STACK_NEAR_TO_GLOBAL -------------------------------- + Convert 16 bit logical of address on the stack 24 bit global pointer + ("char*__near" to "char*__far") + + Arguments : + - X : 16 bit near pointer + + Postcondition : + - B == page of returned global address + - X == offset of returned global address + - Y remains unchanged + - A is unspecified +*/ +/*--------------------------- Convert 16 bit logical stack address to 24 bit global pointer ----------------------------------*/ + +/* B:X = Global(D) */ + +#ifdef __cplusplus +extern "C" +#endif + +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +void NEAR _CONV_STACK_NEAR_TO_GLOBAL(void){ + asm { + /* syntax: */ + /* input 16 bit offset is bit15..bit0 */ + /* ppage values: ppage7..ppage0 */ + /* epage values: epage7..epage0 */ + /* dpage values: dpage7..dpage0 */ + /* rpage values: rpage7..rpage0 */ + /* stack must be between $1000 and $3FFF. */ + /* actually placing the stack at $1000 implies that the RPAGE register is not set (and correctly initialized) */ + CPX #0x2000 + BLO PAGED_RAM + /* Map 0x2000 to 0x0FE000 (0x0FA000 for HCS12XE RAM mapping is enabled) */ + LDAB #0x0F +#ifndef __HCS12XE_RAMHM_SET__ + LEAX (0xE000-0x2000),X ;/* LEAX is one cycle faster than ADDX # */ +#else + LEAX (0xA000-0x2000),X ;/* LEAX is one cycle faster than ADDX # */ +#endif + RTS +PAGED_RAM: + PSHX + LDAB __RPAGE_ADR__ + LDAA #0x20 + MUL + EORB 0,SP + EORB #0x10 ;/* clear 1 bit */ + STAB 0,SP + TFR A,B + PULX + RTS + } +} + + + +/*--------------------------- _CONV_LOGICAL_TO_GLOBAL -------------------------------- + Convert 24 bit global to 24 bit logical pointer + ("char*__far" to "char*__gpage") + + Arguments : + - B : page part of logical address + - X : 16 offset part of logical address + + Postcondition : + - B == page of returned global address + - X == offset of returned global address + - Y remains unchanged + - A remains unchanged +*/ +/*--------------------------- Convert 24 bit logical to 24 bit global pointer ----------------------------------*/ + +/* B:X = Logical(B:X) */ + +#ifdef __cplusplus +extern "C" +#endif + +#pragma NO_FRAME +#pragma NO_ENTRY +#pragma NO_EXIT + +void NEAR _CONV_LOGICAL_TO_GLOBAL(void) { + + asm { + /* syntax: */ + /* input 16 bit offset is bit15..bit0 */ + /* ppage values: ppage7..ppage0 */ + /* epage values: epage7..epage0 */ + /* dpage values: dpage7..dpage0 */ + /* rpage values: rpage7..rpage0 */ + PSHA ;/* save A across this routine. */ + PSHX ;/* D contains bit15..bit0 */ + PSHB ;/* store page */ + TFR X,D ;/* D is cheaper to shift */ + LSLD ;/* D contains 0 bit14..bit0, C contains bit15 */ + BCC Below8000 ;/* bit15 == 0? */ + /* from 0x8000 to 0xFFFF */ + LSLD ;/* D contains 00 bit13..bit0, C contains bit14 */ + BCC BelowC000 + PULB ;/* cleanup stack */ + LDAB #0x7F + PULX + PULA + RTS ;/* returns 0b0111 1111 11 bit13...bit0 */ +BelowC000: ;/* from 0x8000 to 0xBFFF */ + TFR D,X + PULB ;/* cleanup stack */ + SEC + RORB + RORX + LSRB + RORX + LEAS 2,SP + PULA + RTS ;/* returns 0b01 ppage7..ppage0 bit13...bit0 */ +Below8000: + LSLD ;/* D contains 00 bit13..bit0, C contains bit14 */ + BCC Below4000 + ;/* from 0x4000 to 0x7FFF */ + PULB ;/* cleanup stack */ + PULX +#ifndef __HCS12XE_RAMHM_SET__ + LDAB #0x7F +#else + LEAX (0xC000-0x4000),X + LDAB #0x0F +#endif + PULA + RTS ;/* returns 0b0111 1111 01 bit13...bit0 */ + +Below4000: + LSLD ;/* D contains 000 bit12..bit0, C contains bit13 */ + BCC Below2000 + /* from 0x2000 to 0x3FFF */ + PULB ;/* cleanup stack */ + PULX +#ifndef __HCS12XE_RAMHM_SET__ + LEAX (0xE000-0x2000),X +#else + LEAX (0xA000-0x2000),X +#endif + LDAB #0x0F + PULA + RTS ;/* returns 0b0000 1111 111 bit12...bit0 */ + +Below2000: + LSLD ;/* D contains 0000 bit11..bit0, C contains bit12 */ + BCC Below1000 + /* from 0x1000 to 0x1FFF */ + PULB + LDAA #0x10 + MUL + EORB 0,SP + EORB #0x10 ;/* clear 1 bit */ + STAB 0,SP + TFR A,B + PULX + PULA + RTS + +Below1000: + LSLD ;/* D contains 0000 0 bit10..bit0, C contains bit11 */ + BCC Below0800 + /* from 0x0800 to 0x0FFF */ + LSLD ;/* D contains 0000 00 bit9..bit0, C contains bit10 */ + BCC Below0C00 + /* from 0x0C00 to 0x0FFF */ + PULB ;/* cleanup stack */ + LDAB #0x13 + PULX + LEAX 0xF000,X + PULA + RTS ;/* returns 0b0001 0011 1111 11 bit9...bit0 */ +Below0C00: + /* from 0x0800 to 0x0BFF */ + PULB + LDAA #0x04 + MUL + EORB 0,SP + EORB #0x08 + STAB 0,SP + TFR A,B + ORAB #0b00010000 + PULX + PULA + RTS +Below0800: + PULB + PULX + PULA + CLRB + RTS + } +} + +/*--------------------------- _FAR_COPY_RC HCS12X Routines -------------------------------- + copy larger far memory blocks + There are the following memory block copy routines: + _COPY : 16 bit logical copies. + Src and dest are both near. Note: implemented in rtshc12.c and not here. + _FAR_COPY_RC HC12/HCS12 struct copy routine. + Expects HC12/HCS12 logical 24 bit address. + Note: Does not exist for the HCS12X. + The HC12/HCS12 implementation is implemented above. + _FAR_COPY_GLOBAL_GLOBAL_RC: + _FAR_COPY_GLOBAL_LOGICAL_RC: + _FAR_COPY_LOGICAL_GLOBAL_RC: + _FAR_COPY_LOGICAL_LOGICAL_RC: + _FAR_COPY_NEAR_GLOBAL_RC: + _FAR_COPY_NEAR_LOGICAL_RC: + _FAR_COPY_GLOBAL_NEAR_RC: + _FAR_COPY_LOGICAL_NEAR_RC: HCS12X specific far copy routine. The name describes what the src/dest address format are. + All near src arguments are passed in X, all 24 bit src in X/B. + All near dest arguments are passed in Y, all 24 bit src in Y/A. + (Note: HC12 _FAR_COPY_RC is using X/A as src and Y/B as dest, so the register usage is not the same!) + + Arguments : + - B:X : src address (for NEAR/_COPY: only X) + - A:Y : dest address (for NEAR/_COPY: only Y) + - number of bytes to be copied behind return address (for _COPY: in D register). The number of bytes is always > 0 + + Result : + - memory area copied + - no registers are saved, i.e. all registers may be destroyed + - for _COPY: D contains 0. + - for HCS12X _FAR_COPY_... routines: GPAGE state is unknown +*/ + + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_GLOBAL_GLOBAL_RC(void) { + asm { + PSHD + PSHY + LDY 4,SP ;/* load return address */ + LDD 2,Y+ ;/* load size */ + STY 4,SP ;/* store return address */ + PULY + PSHD + LDAB 3,SP +Loop: + STAB __GPAGE_ADR__ + GLDAA 1,X+ + MOVB 2,SP,__GPAGE_ADR__ + GSTAA 1,Y+ + DECW 0,SP + BNE Loop + LEAS 4,SP + _SRET ;/* debug info only: This is the last instr of a function with a special return */ + RTS + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _SET_PAGE_REG_HCS12X(void) { + /* Sets the page contained in A to the register controlling the logical addr contained in X. */ + /* saves the old page before and returns it in A together with the page address just below the return address. */ + /* X/Y both remain valid. */ + asm { + PSHX + /* 0000..FFFF */ + CPX #0x8000 + BLO _LO8000 + LDX #__PPAGE_ADR__ + BRA Handle +_LO8000: + /* 0000..7FFF */ + CPX #0x1000 + BLO _LO1000 + LDX #__RPAGE_ADR__ + BRA Handle +_LO1000: + LDX #__EPAGE_ADR__ +Handle: + LDAA 0,X ;/* load old page register content */ + STAB 0,X ;/* set new page register */ + STX 4,SP + PULX + RTS + } +} + + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_GLOBAL_LOGICAL_RC(void) { + asm { + STAB __GPAGE_ADR__ + EXG X,Y + TFR A,B + PSHY ;/* space to store size */ + PSHX ;/* allocate some space where _SET_PAGE_REG_HCS12X can return the page */ + LDY 4,SP ;/* load return address */ + LDX 2,Y+ ;/* load size */ + STY 4,SP + LDY 2,SP ;/* restore dest pointer */ + STX 2,SP ;/* store size */ + LDX 0,SP ;/* reload src pointer */ + __PIC_JSR(_SET_PAGE_REG_HCS12X) + +Loop: GLDAB 1,Y+ + STAB 1,X+ + DECW 2,SP + BNE Loop + + PULX ;/* reload page register address */ + STAA 0,X ;/* restore old page content (necessary if it was PPAGE) */ + PULX ;/* clean up stack */ + _SRET ;/* debug info only: This is the last instr of a function with a special return */ + RTS + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_LOGICAL_GLOBAL_RC(void) { + asm { + STAA __GPAGE_ADR__ + PSHY ;/* space to store size */ + PSHX ;/* allocate some space where _SET_PAGE_REG_HCS12X can return the page */ + LDY 4,SP ;/* load return address */ + LDX 2,Y+ ;/* load size */ + STY 4,SP + LDY 2,SP ;/* restore dest pointer */ + STX 2,SP ;/* store size */ + LDX 0,SP ;/* reload src pointer */ + + __PIC_JSR(_SET_PAGE_REG_HCS12X) + +Loop: LDAB 1,X+ + GSTAB 1,Y+ + DECW 2,SP + BNE Loop + + PULX + STAA 0,X ;/* restore old page content (necessary if it was PPAGE) */ + PULX ;/* clean up stack */ + _SRET ;/* debug info only: This is the last instr of a function with a special return */ + RTS + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_LOGICAL_LOGICAL_RC(void) { + asm { + PSHA + __PIC_JSR(_CONV_LOGICAL_TO_GLOBAL); + PULA + __PIC_JMP(_FAR_COPY_GLOBAL_LOGICAL_RC); + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_NEAR_GLOBAL_RC(void) { + asm { + CLRB + __PIC_JMP(_FAR_COPY_LOGICAL_GLOBAL_RC); + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_NEAR_LOGICAL_RC(void) { + asm { + PSHA + __PIC_JSR(_CONV_NEAR_TO_GLOBAL); + PULA + __PIC_JMP(_FAR_COPY_GLOBAL_LOGICAL_RC); + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_GLOBAL_NEAR_RC(void) { + asm { + CLRA /* near to logical (we may have to use another runtime if this gets non trivial as well :-( */ + __PIC_JMP(_FAR_COPY_GLOBAL_LOGICAL_RC); + } +} + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_LOGICAL_NEAR_RC(void) { + asm { + EXG A,B + EXG X,Y + PSHA + __PIC_JSR(_CONV_NEAR_TO_GLOBAL); + PULA + EXG A,B + EXG X,Y + __PIC_JMP(_FAR_COPY_LOGICAL_GLOBAL_RC); + } +} + +/* _FAR_COPY_LOGICAL_GLOBAL: is used by some old wizard generated projects. Not used by current setup anymore */ + +#ifdef __cplusplus +extern "C" +#endif +#pragma NO_ENTRY +#pragma NO_EXIT +#pragma NO_FRAME + +void NEAR _FAR_COPY_LOGICAL_GLOBAL(void) { + asm { + STAA __GPAGE_ADR__ + PSHX ;/* allocate some space where _SET_PAGE_REG_HCS12X can return the page */ + __PIC_JSR(_SET_PAGE_REG_HCS12X) + +Loop: LDAB 1,X+ + GSTAB 1,Y+ + DECW 4,SP + BNE Loop + + PULX + STAA 0,X ;/* restore old page content (necessary if it was PPAGE) */ + + LDX 4,SP+ ;/* load return address and clean stack */ + JMP 0,X + } +} + + +#endif /* __HCS12X__ */ + + +/*----------------- end of code ------------------------------------------------*/ +/*lint --e{766} , runtime.sgm is not a regular header file, it contains a conditionally compiled CODE_SEG pragma */ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/derivative.h b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/derivative.h new file mode 100644 index 00000000..6e1bf282 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/derivative.h @@ -0,0 +1,10 @@ +/* + * Note: This file is recreated by the project wizard whenever the MCU is + * changed and should not be edited by hand + */ + +/* Include the derivative-specific header file */ +#include + +#pragma LINK_INFO DERIVATIVE "mc9s12dg256" + diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/mc9s12dg256.c b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/mc9s12dg256.c new file mode 100644 index 00000000..e3ef8a19 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/mc9s12dg256.c @@ -0,0 +1,366 @@ +/* Based on CPU DB MC9S12DG256_112, version 2.87.346 (RegistersPrg V2.28) */ +/* DataSheet : 9S12DT256DGV3/D V03.04 */ + +#include + +/*lint -save -esym(765, *) */ + + +/* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ +volatile PORTESTR _PORTE; /* Port E Register; 0x00000008 */ +volatile DDRESTR _DDRE; /* Port E Data Direction Register; 0x00000009 */ +volatile PEARSTR _PEAR; /* Port E Assignment Register; 0x0000000A */ +volatile MODESTR _MODE; /* Mode Register; 0x0000000B */ +volatile PUCRSTR _PUCR; /* Pull-Up Control Register; 0x0000000C */ +volatile RDRIVSTR _RDRIV; /* Reduced Drive of I/O Lines; 0x0000000D */ +volatile EBICTLSTR _EBICTL; /* External Bus Interface Control; 0x0000000E */ +volatile INITRMSTR _INITRM; /* Initialization of Internal RAM Position Register; 0x00000010 */ +volatile INITRGSTR _INITRG; /* Initialization of Internal Registers Position Register; 0x00000011 */ +volatile INITEESTR _INITEE; /* Initialization of Internal EEPROM Position Register; 0x00000012 */ +volatile MISCSTR _MISC; /* Miscellaneous System Control Register; 0x00000013 */ +volatile ITCRSTR _ITCR; /* Interrupt Test Control Register; 0x00000015 */ +volatile ITESTSTR _ITEST; /* Interrupt Test Register; 0x00000016 */ +volatile MEMSIZ0STR _MEMSIZ0; /* Memory Size Register Zero; 0x0000001C */ +volatile MEMSIZ1STR _MEMSIZ1; /* Memory Size Register One; 0x0000001D */ +volatile INTCRSTR _INTCR; /* Interrupt Control Register; 0x0000001E */ +volatile HPRIOSTR _HPRIO; /* Highest Priority I Interrupt; 0x0000001F */ +volatile BKPCT0STR _BKPCT0; /* Breakpoint Control Register 0; 0x00000028 */ +volatile BKPCT1STR _BKPCT1; /* Breakpoint Control Register 1; 0x00000029 */ +volatile BKP0XSTR _BKP0X; /* First Address Memory Expansion Breakpoint Register; 0x0000002A */ +volatile BKP0HSTR _BKP0H; /* First Address High Byte Breakpoint Register; 0x0000002B */ +volatile BKP0LSTR _BKP0L; /* First Address Low Byte Breakpoint Register; 0x0000002C */ +volatile BKP1XSTR _BKP1X; /* Second Address Memory Expansion Breakpoint Register; 0x0000002D */ +volatile BKP1HSTR _BKP1H; /* Data (Second Address) High Byte Breakpoint Register; 0x0000002E */ +volatile BKP1LSTR _BKP1L; /* Data (Second Address) Low Byte Breakpoint Register; 0x0000002F */ +volatile PPAGESTR _PPAGE; /* Page Index Register; 0x00000030 */ +volatile PORTKSTR _PORTK; /* Port K Data Register; 0x00000032 */ +volatile DDRKSTR _DDRK; /* Port K Data Direction Register; 0x00000033 */ +volatile SYNRSTR _SYNR; /* CRG Synthesizer Register; 0x00000034 */ +volatile REFDVSTR _REFDV; /* CRG Reference Divider Register; 0x00000035 */ +volatile CRGFLGSTR _CRGFLG; /* CRG Flags Register; 0x00000037 */ +volatile CRGINTSTR _CRGINT; /* CRG Interrupt Enable Register; 0x00000038 */ +volatile CLKSELSTR _CLKSEL; /* CRG Clock Select Register; 0x00000039 */ +volatile PLLCTLSTR _PLLCTL; /* CRG PLL Control Register; 0x0000003A */ +volatile RTICTLSTR _RTICTL; /* CRG RTI Control Register; 0x0000003B */ +volatile COPCTLSTR _COPCTL; /* CRG COP Control Register; 0x0000003C */ +volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register; 0x0000003F */ +volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select; 0x00000040 */ +volatile CFORCSTR _CFORC; /* Timer Compare Force Register; 0x00000041 */ +volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register; 0x00000042 */ +volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register; 0x00000043 */ +volatile TSCR1STR _TSCR1; /* Timer System Control Register1; 0x00000046 */ +volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register; 0x00000047 */ +volatile TCTL1STR _TCTL1; /* Timer Control Register 1; 0x00000048 */ +volatile TCTL2STR _TCTL2; /* Timer Control Register 2; 0x00000049 */ +volatile TCTL3STR _TCTL3; /* Timer Control Register 3; 0x0000004A */ +volatile TCTL4STR _TCTL4; /* Timer Control Register 4; 0x0000004B */ +volatile TIESTR _TIE; /* Timer Interrupt Enable Register; 0x0000004C */ +volatile TSCR2STR _TSCR2; /* Timer System Control Register 2; 0x0000004D */ +volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1; 0x0000004E */ +volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2; 0x0000004F */ +volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register; 0x00000060 */ +volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register; 0x00000061 */ +volatile MCCTLSTR _MCCTL; /* Modulus Down Counter underflow; 0x00000066 */ +volatile MCFLGSTR _MCFLG; /* 16-Bit Modulus Down Counter Flag Register; 0x00000067 */ +volatile ICPARSTR _ICPAR; /* Input Control Pulse Accumulator Register; 0x00000068 */ +volatile DLYCTSTR _DLYCT; /* Delay Counter Control Register; 0x00000069 */ +volatile ICOVWSTR _ICOVW; /* Input Control Overwrite Register; 0x0000006A */ +volatile ICSYSSTR _ICSYS; /* Input Control System Control Register; 0x0000006B */ +volatile PBCTLSTR _PBCTL; /* 16-Bit Pulse Accumulator B Control Register; 0x00000070 */ +volatile PBFLGSTR _PBFLG; /* Pulse Accumulator B Flag Register; 0x00000071 */ +volatile ATD0STAT0STR _ATD0STAT0; /* ATD 0 Status Register 0; 0x00000086 */ +volatile ATD0TEST1STR _ATD0TEST1; /* ATD0 Test Register; 0x00000089 */ +volatile ATD0STAT1STR _ATD0STAT1; /* ATD 0 Status Register 1; 0x0000008B */ +volatile ATD0DIENSTR _ATD0DIEN; /* ATD 0 Input Enable Register; 0x0000008D */ +volatile PORTAD0STR _PORTAD0; /* Port AD0 Register; 0x0000008F */ +volatile PWMESTR _PWME; /* PWM Enable Register; 0x000000A0 */ +volatile PWMPOLSTR _PWMPOL; /* PWM Polarity Register; 0x000000A1 */ +volatile PWMCLKSTR _PWMCLK; /* PWM Clock Select Register; 0x000000A2 */ +volatile PWMPRCLKSTR _PWMPRCLK; /* PWM Prescale Clock Select Register; 0x000000A3 */ +volatile PWMCAESTR _PWMCAE; /* PWM Center Align Enable Register; 0x000000A4 */ +volatile PWMCTLSTR _PWMCTL; /* PWM Control Register; 0x000000A5 */ +volatile PWMSCLASTR _PWMSCLA; /* PWM Scale A Register; 0x000000A8 */ +volatile PWMSCLBSTR _PWMSCLB; /* PWM Scale B Register; 0x000000A9 */ +volatile PWMSDNSTR _PWMSDN; /* PWM Shutdown Register; 0x000000C4 */ +volatile SCI0CR1STR _SCI0CR1; /* SCI 0 Control Register 1; 0x000000CA */ +volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2; 0x000000CB */ +volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1; 0x000000CC */ +volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2; 0x000000CD */ +volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High; 0x000000CE */ +volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low; 0x000000CF */ +volatile SCI1CR1STR _SCI1CR1; /* SCI 1 Control Register 1; 0x000000D2 */ +volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2; 0x000000D3 */ +volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1; 0x000000D4 */ +volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2; 0x000000D5 */ +volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High; 0x000000D6 */ +volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low; 0x000000D7 */ +volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register; 0x000000D8 */ +volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2; 0x000000D9 */ +volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register; 0x000000DA */ +volatile SPI0SRSTR _SPI0SR; /* SPI 0 Status Register; 0x000000DB */ +volatile SPI0DRSTR _SPI0DR; /* SPI 0 Data Register; 0x000000DD */ +volatile IBADSTR _IBAD; /* IIC Address Register; 0x000000E0 */ +volatile IBFDSTR _IBFD; /* IIC Frequency Divider Register; 0x000000E1 */ +volatile IBCRSTR _IBCR; /* IIC Control Register; 0x000000E2 */ +volatile IBSRSTR _IBSR; /* IIC Status Register; 0x000000E3 */ +volatile IBDRSTR _IBDR; /* IIC Data I/O Register; 0x000000E4 */ +volatile SPI1CR1STR _SPI1CR1; /* SPI 1 Control Register; 0x000000F0 */ +volatile SPI1CR2STR _SPI1CR2; /* SPI 1 Control Register 2; 0x000000F1 */ +volatile SPI1BRSTR _SPI1BR; /* SPI 1 Baud Rate Register; 0x000000F2 */ +volatile SPI1SRSTR _SPI1SR; /* SPI 1 Status Register; 0x000000F3 */ +volatile SPI1DRSTR _SPI1DR; /* SPI 1 Data Register; 0x000000F5 */ +volatile SPI2CR1STR _SPI2CR1; /* SPI 2 Control Register; 0x000000F8 */ +volatile SPI2CR2STR _SPI2CR2; /* SPI 2 Control Register 2; 0x000000F9 */ +volatile SPI2BRSTR _SPI2BR; /* SPI 2 Baud Rate Register; 0x000000FA */ +volatile SPI2SRSTR _SPI2SR; /* SPI 2 Status Register; 0x000000FB */ +volatile SPI2DRSTR _SPI2DR; /* SPI 2 Data Register; 0x000000FD */ +volatile FCLKDIVSTR _FCLKDIV; /* Flash Clock Divider Register; 0x00000100 */ +volatile FSECSTR _FSEC; /* Flash Security Register; 0x00000101 */ +volatile FCNFGSTR _FCNFG; /* Flash Configuration Register; 0x00000103 */ +volatile FPROTSTR _FPROT; /* Flash Protection Register; 0x00000104 */ +volatile FSTATSTR _FSTAT; /* Flash Status Register; 0x00000105 */ +volatile FCMDSTR _FCMD; /* Flash Command Buffer and Register; 0x00000106 */ +volatile ECLKDIVSTR _ECLKDIV; /* EEPROM Clock Divider Register; 0x00000110 */ +volatile ECNFGSTR _ECNFG; /* EEPROM Configuration Register; 0x00000113 */ +volatile EPROTSTR _EPROT; /* EEPROM Protection Register; 0x00000114 */ +volatile ESTATSTR _ESTAT; /* EEPROM Status Register; 0x00000115 */ +volatile ECMDSTR _ECMD; /* EEPROM Command Buffer and Register; 0x00000116 */ +volatile ATD1STAT0STR _ATD1STAT0; /* ATD 1 Status Register 0; 0x00000126 */ +volatile ATD1TEST1STR _ATD1TEST1; /* ATD1 Test Register; 0x00000129 */ +volatile ATD1STAT1STR _ATD1STAT1; /* ATD 1 Status Register 1; 0x0000012B */ +volatile ATD1DIENSTR _ATD1DIEN; /* ATD 1 Input Enable Register; 0x0000012D */ +volatile PORTAD1STR _PORTAD1; /* Port AD1 Register; 0x0000012F */ +volatile CAN0CTL0STR _CAN0CTL0; /* MSCAN 0 Control 0 Register; 0x00000140 */ +volatile CAN0CTL1STR _CAN0CTL1; /* MSCAN 0 Control 1 Register; 0x00000141 */ +volatile CAN0BTR0STR _CAN0BTR0; /* MSCAN 0 Bus Timing Register 0; 0x00000142 */ +volatile CAN0BTR1STR _CAN0BTR1; /* MSCAN 0 Bus Timing Register 1; 0x00000143 */ +volatile CAN0RFLGSTR _CAN0RFLG; /* MSCAN 0 Receiver Flag Register; 0x00000144 */ +volatile CAN0RIERSTR _CAN0RIER; /* MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 */ +volatile CAN0TFLGSTR _CAN0TFLG; /* MSCAN 0 Transmitter Flag Register; 0x00000146 */ +volatile CAN0TIERSTR _CAN0TIER; /* MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 */ +volatile CAN0TARQSTR _CAN0TARQ; /* MSCAN 0 Transmitter Message Abort Request; 0x00000148 */ +volatile CAN0TAAKSTR _CAN0TAAK; /* MSCAN 0 Transmitter Message Abort Control; 0x00000149 */ +volatile CAN0TBSELSTR _CAN0TBSEL; /* MSCAN 0 Transmit Buffer Selection; 0x0000014A */ +volatile CAN0IDACSTR _CAN0IDAC; /* MSCAN 0 Identifier Acceptance Control Register; 0x0000014B */ +volatile CAN0RXERRSTR _CAN0RXERR; /* MSCAN 0 Receive Error Counter Register; 0x0000014E */ +volatile CAN0TXERRSTR _CAN0TXERR; /* MSCAN 0 Transmit Error Counter Register; 0x0000014F */ +volatile CAN0IDAR0STR _CAN0IDAR0; /* MSCAN 0 Identifier Acceptance Register 0; 0x00000150 */ +volatile CAN0IDAR1STR _CAN0IDAR1; /* MSCAN 0 Identifier Acceptance Register 1; 0x00000151 */ +volatile CAN0IDAR2STR _CAN0IDAR2; /* MSCAN 0 Identifier Acceptance Register 2; 0x00000152 */ +volatile CAN0IDAR3STR _CAN0IDAR3; /* MSCAN 0 Identifier Acceptance Register 3; 0x00000153 */ +volatile CAN0IDMR0STR _CAN0IDMR0; /* MSCAN 0 Identifier Mask Register 0; 0x00000154 */ +volatile CAN0IDMR1STR _CAN0IDMR1; /* MSCAN 0 Identifier Mask Register 1; 0x00000155 */ +volatile CAN0IDMR2STR _CAN0IDMR2; /* MSCAN 0 Identifier Mask Register 2; 0x00000156 */ +volatile CAN0IDMR3STR _CAN0IDMR3; /* MSCAN 0 Identifier Mask Register 3; 0x00000157 */ +volatile CAN0IDAR4STR _CAN0IDAR4; /* MSCAN 0 Identifier Acceptance Register 4; 0x00000158 */ +volatile CAN0IDAR5STR _CAN0IDAR5; /* MSCAN 0 Identifier Acceptance Register 5; 0x00000159 */ +volatile CAN0IDAR6STR _CAN0IDAR6; /* MSCAN 0 Identifier Acceptance Register 6; 0x0000015A */ +volatile CAN0IDAR7STR _CAN0IDAR7; /* MSCAN 0 Identifier Acceptance Register 7; 0x0000015B */ +volatile CAN0IDMR4STR _CAN0IDMR4; /* MSCAN 0 Identifier Mask Register 4; 0x0000015C */ +volatile CAN0IDMR5STR _CAN0IDMR5; /* MSCAN 0 Identifier Mask Register 5; 0x0000015D */ +volatile CAN0IDMR6STR _CAN0IDMR6; /* MSCAN 0 Identifier Mask Register 6; 0x0000015E */ +volatile CAN0IDMR7STR _CAN0IDMR7; /* MSCAN 0 Identifier Mask Register 7; 0x0000015F */ +volatile CAN0RXIDR0STR _CAN0RXIDR0; /* MSCAN 0 Receive Identifier Register 0; 0x00000160 */ +volatile CAN0RXIDR1STR _CAN0RXIDR1; /* MSCAN 0 Receive Identifier Register 1; 0x00000161 */ +volatile CAN0RXIDR2STR _CAN0RXIDR2; /* MSCAN 0 Receive Identifier Register 2; 0x00000162 */ +volatile CAN0RXIDR3STR _CAN0RXIDR3; /* MSCAN 0 Receive Identifier Register 3; 0x00000163 */ +volatile CAN0RXDSR0STR _CAN0RXDSR0; /* MSCAN 0 Receive Data Segment Register 0; 0x00000164 */ +volatile CAN0RXDSR1STR _CAN0RXDSR1; /* MSCAN 0 Receive Data Segment Register 1; 0x00000165 */ +volatile CAN0RXDSR2STR _CAN0RXDSR2; /* MSCAN 0 Receive Data Segment Register 2; 0x00000166 */ +volatile CAN0RXDSR3STR _CAN0RXDSR3; /* MSCAN 0 Receive Data Segment Register 3; 0x00000167 */ +volatile CAN0RXDSR4STR _CAN0RXDSR4; /* MSCAN 0 Receive Data Segment Register 4; 0x00000168 */ +volatile CAN0RXDSR5STR _CAN0RXDSR5; /* MSCAN 0 Receive Data Segment Register 5; 0x00000169 */ +volatile CAN0RXDSR6STR _CAN0RXDSR6; /* MSCAN 0 Receive Data Segment Register 6; 0x0000016A */ +volatile CAN0RXDSR7STR _CAN0RXDSR7; /* MSCAN 0 Receive Data Segment Register 7; 0x0000016B */ +volatile CAN0RXDLRSTR _CAN0RXDLR; /* MSCAN 0 Receive Data Length Register; 0x0000016C */ +volatile CAN0TXIDR0STR _CAN0TXIDR0; /* MSCAN 0 Transmit Identifier Register 0; 0x00000170 */ +volatile CAN0TXIDR1STR _CAN0TXIDR1; /* MSCAN 0 Transmit Identifier Register 1; 0x00000171 */ +volatile CAN0TXIDR2STR _CAN0TXIDR2; /* MSCAN 0 Transmit Identifier Register 2; 0x00000172 */ +volatile CAN0TXIDR3STR _CAN0TXIDR3; /* MSCAN 0 Transmit Identifier Register 3; 0x00000173 */ +volatile CAN0TXDSR0STR _CAN0TXDSR0; /* MSCAN 0 Transmit Data Segment Register 0; 0x00000174 */ +volatile CAN0TXDSR1STR _CAN0TXDSR1; /* MSCAN 0 Transmit Data Segment Register 1; 0x00000175 */ +volatile CAN0TXDSR2STR _CAN0TXDSR2; /* MSCAN 0 Transmit Data Segment Register 2; 0x00000176 */ +volatile CAN0TXDSR3STR _CAN0TXDSR3; /* MSCAN 0 Transmit Data Segment Register 3; 0x00000177 */ +volatile CAN0TXDSR4STR _CAN0TXDSR4; /* MSCAN 0 Transmit Data Segment Register 4; 0x00000178 */ +volatile CAN0TXDSR5STR _CAN0TXDSR5; /* MSCAN 0 Transmit Data Segment Register 5; 0x00000179 */ +volatile CAN0TXDSR6STR _CAN0TXDSR6; /* MSCAN 0 Transmit Data Segment Register 6; 0x0000017A */ +volatile CAN0TXDSR7STR _CAN0TXDSR7; /* MSCAN 0 Transmit Data Segment Register 7; 0x0000017B */ +volatile CAN0TXDLRSTR _CAN0TXDLR; /* MSCAN 0 Transmit Data Length Register; 0x0000017C */ +volatile CAN0TXTBPRSTR _CAN0TXTBPR; /* MSCAN 0 Transmit Buffer Priority; 0x0000017D */ +volatile PTTSTR _PTT; /* Port T I/O Register; 0x00000240 */ +volatile PTITSTR _PTIT; /* Port T Input Register; 0x00000241 */ +volatile DDRTSTR _DDRT; /* Port T Data Direction Register; 0x00000242 */ +volatile RDRTSTR _RDRT; /* Port T Reduced Drive Register; 0x00000243 */ +volatile PERTSTR _PERT; /* Port T Pull Device Enable Register; 0x00000244 */ +volatile PPSTSTR _PPST; /* Port T Polarity Select Register; 0x00000245 */ +volatile PTSSTR _PTS; /* Port S I/O Register; 0x00000248 */ +volatile PTISSTR _PTIS; /* Port S Input Register; 0x00000249 */ +volatile DDRSSTR _DDRS; /* Port S Data Direction Register; 0x0000024A */ +volatile RDRSSTR _RDRS; /* Port S Reduced Drive Register; 0x0000024B */ +volatile PERSSTR _PERS; /* Port S Pull Device Enable Register; 0x0000024C */ +volatile PPSSSTR _PPSS; /* Port S Polarity Select Register; 0x0000024D */ +volatile WOMSSTR _WOMS; /* Port S Wired-Or Mode Register; 0x0000024E */ +volatile PTMSTR _PTM; /* Port M I/O Register; 0x00000250 */ +volatile PTIMSTR _PTIM; /* Port M Input Register; 0x00000251 */ +volatile DDRMSTR _DDRM; /* Port M Data Direction Register; 0x00000252 */ +volatile RDRMSTR _RDRM; /* Port M Reduced Drive Register; 0x00000253 */ +volatile PERMSTR _PERM; /* Port M Pull Device Enable Register; 0x00000254 */ +volatile PPSMSTR _PPSM; /* Port M Polarity Select Register; 0x00000255 */ +volatile WOMMSTR _WOMM; /* Port M Wired-Or Mode Register; 0x00000256 */ +volatile MODRRSTR _MODRR; /* Module Routing Register; 0x00000257 */ +volatile PTPSTR _PTP; /* Port P I/O Register; 0x00000258 */ +volatile PTIPSTR _PTIP; /* Port P Input Register; 0x00000259 */ +volatile DDRPSTR _DDRP; /* Port P Data Direction Register; 0x0000025A */ +volatile RDRPSTR _RDRP; /* Port P Reduced Drive Register; 0x0000025B */ +volatile PERPSTR _PERP; /* Port P Pull Device Enable Register; 0x0000025C */ +volatile PPSPSTR _PPSP; /* Port P Polarity Select Register; 0x0000025D */ +volatile PIEPSTR _PIEP; /* Port P Interrupt Enable Register; 0x0000025E */ +volatile PIFPSTR _PIFP; /* Port P Interrupt Flag Register; 0x0000025F */ +volatile PTHSTR _PTH; /* Port H I/O Register; 0x00000260 */ +volatile PTIHSTR _PTIH; /* Port H Input Register; 0x00000261 */ +volatile DDRHSTR _DDRH; /* Port H Data Direction Register; 0x00000262 */ +volatile RDRHSTR _RDRH; /* Port H Reduced Drive Register; 0x00000263 */ +volatile PERHSTR _PERH; /* Port H Pull Device Enable Register; 0x00000264 */ +volatile PPSHSTR _PPSH; /* Port H Polarity Select Register; 0x00000265 */ +volatile PIEHSTR _PIEH; /* Port H Interrupt Enable Register; 0x00000266 */ +volatile PIFHSTR _PIFH; /* Port H Interrupt Flag Register; 0x00000267 */ +volatile PTJSTR _PTJ; /* Port J I/O Register; 0x00000268 */ +volatile PTIJSTR _PTIJ; /* Port J Input Register; 0x00000269 */ +volatile DDRJSTR _DDRJ; /* Port J Data Direction Register; 0x0000026A */ +volatile RDRJSTR _RDRJ; /* Port J Reduced Drive Register; 0x0000026B */ +volatile PERJSTR _PERJ; /* Port J Pull Device Enable Register; 0x0000026C */ +volatile PPSJSTR _PPSJ; /* Port J Polarity Select Register; 0x0000026D */ +volatile PIEJSTR _PIEJ; /* Port J Interrupt Enable Register; 0x0000026E */ +volatile PIFJSTR _PIFJ; /* Port J Interrupt Flag Register; 0x0000026F */ +volatile CAN4CTL0STR _CAN4CTL0; /* MSCAN4 Control 0 Register; 0x00000280 */ +volatile CAN4CTL1STR _CAN4CTL1; /* MSCAN4 Control 1 Register; 0x00000281 */ +volatile CAN4BTR0STR _CAN4BTR0; /* MSCAN4 Bus Timing Register 0; 0x00000282 */ +volatile CAN4BTR1STR _CAN4BTR1; /* MSCAN4 Bus Timing Register 1; 0x00000283 */ +volatile CAN4RFLGSTR _CAN4RFLG; /* MSCAN4 Receiver Flag Register; 0x00000284 */ +volatile CAN4RIERSTR _CAN4RIER; /* MSCAN4 Receiver Interrupt Enable Register; 0x00000285 */ +volatile CAN4TFLGSTR _CAN4TFLG; /* MSCAN4 Transmitter Flag Register; 0x00000286 */ +volatile CAN4TIERSTR _CAN4TIER; /* MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 */ +volatile CAN4TARQSTR _CAN4TARQ; /* MSCAN 4 Transmitter Message Abort Request; 0x00000288 */ +volatile CAN4TAAKSTR _CAN4TAAK; /* MSCAN4 Transmitter Message Abort Control; 0x00000289 */ +volatile CAN4TBSELSTR _CAN4TBSEL; /* MSCAN4 Transmit Buffer Selection; 0x0000028A */ +volatile CAN4IDACSTR _CAN4IDAC; /* MSCAN4 Identifier Acceptance Control Register; 0x0000028B */ +volatile CAN4RXERRSTR _CAN4RXERR; /* MSCAN4 Receive Error Counter Register; 0x0000028E */ +volatile CAN4TXERRSTR _CAN4TXERR; /* MSCAN4 Transmit Error Counter Register; 0x0000028F */ +volatile CAN4IDAR0STR _CAN4IDAR0; /* MSCAN4 Identifier Acceptance Register 0; 0x00000290 */ +volatile CAN4IDAR1STR _CAN4IDAR1; /* MSCAN4 Identifier Acceptance Register 1; 0x00000291 */ +volatile CAN4IDAR2STR _CAN4IDAR2; /* MSCAN4 Identifier Acceptance Register 2; 0x00000292 */ +volatile CAN4IDAR3STR _CAN4IDAR3; /* MSCAN4 Identifier Acceptance Register 3; 0x00000293 */ +volatile CAN4IDMR0STR _CAN4IDMR0; /* MSCAN4 Identifier Mask Register 0; 0x00000294 */ +volatile CAN4IDMR1STR _CAN4IDMR1; /* MSCAN4 Identifier Mask Register 1; 0x00000295 */ +volatile CAN4IDMR2STR _CAN4IDMR2; /* MSCAN4 Identifier Mask Register 2; 0x00000296 */ +volatile CAN4IDMR3STR _CAN4IDMR3; /* MSCAN4 Identifier Mask Register 3; 0x00000297 */ +volatile CAN4IDAR4STR _CAN4IDAR4; /* MSCAN4 Identifier Acceptance Register 4; 0x00000298 */ +volatile CAN4IDAR5STR _CAN4IDAR5; /* MSCAN4 Identifier Acceptance Register 5; 0x00000299 */ +volatile CAN4IDAR6STR _CAN4IDAR6; /* MSCAN4 Identifier Acceptance Register 6; 0x0000029A */ +volatile CAN4IDAR7STR _CAN4IDAR7; /* MSCAN4 Identifier Acceptance Register 7; 0x0000029B */ +volatile CAN4IDMR4STR _CAN4IDMR4; /* MSCAN4 Identifier Mask Register 4; 0x0000029C */ +volatile CAN4IDMR5STR _CAN4IDMR5; /* MSCAN4 Identifier Mask Register 5; 0x0000029D */ +volatile CAN4IDMR6STR _CAN4IDMR6; /* MSCAN4 Identifier Mask Register 6; 0x0000029E */ +volatile CAN4IDMR7STR _CAN4IDMR7; /* MSCAN4 Identifier Mask Register 7; 0x0000029F */ +volatile CAN4RXIDR0STR _CAN4RXIDR0; /* MSCAN4 Receive Identifier Register 0; 0x000002A0 */ +volatile CAN4RXIDR1STR _CAN4RXIDR1; /* MSCAN4 Receive Identifier Register 1; 0x000002A1 */ +volatile CAN4RXIDR2STR _CAN4RXIDR2; /* MSCAN4 Receive Identifier Register 2; 0x000002A2 */ +volatile CAN4RXIDR3STR _CAN4RXIDR3; /* MSCAN4 Receive Identifier Register 3; 0x000002A3 */ +volatile CAN4RXDSR0STR _CAN4RXDSR0; /* MSCAN4 Receive Data Segment Register 0; 0x000002A4 */ +volatile CAN4RXDSR1STR _CAN4RXDSR1; /* MSCAN4 Receive Data Segment Register 1; 0x000002A5 */ +volatile CAN4RXDSR2STR _CAN4RXDSR2; /* MSCAN4 Receive Data Segment Register 2; 0x000002A6 */ +volatile CAN4RXDSR3STR _CAN4RXDSR3; /* MSCAN4 Receive Data Segment Register 3; 0x000002A7 */ +volatile CAN4RXDSR4STR _CAN4RXDSR4; /* MSCAN4 Receive Data Segment Register 4; 0x000002A8 */ +volatile CAN4RXDSR5STR _CAN4RXDSR5; /* MSCAN4 Receive Data Segment Register 5; 0x000002A9 */ +volatile CAN4RXDSR6STR _CAN4RXDSR6; /* MSCAN4 Receive Data Segment Register 6; 0x000002AA */ +volatile CAN4RXDSR7STR _CAN4RXDSR7; /* MSCAN4 Receive Data Segment Register 7; 0x000002AB */ +volatile CAN4RXDLRSTR _CAN4RXDLR; /* MSCAN4 Receive Data Length Register; 0x000002AC */ +volatile CAN4TXIDR0STR _CAN4TXIDR0; /* MSCAN4 Transmit Identifier Register 0; 0x000002B0 */ +volatile CAN4TXIDR1STR _CAN4TXIDR1; /* MSCAN4 Transmit Identifier Register 1; 0x000002B1 */ +volatile CAN4TXIDR2STR _CAN4TXIDR2; /* MSCAN4 Transmit Identifier Register 2; 0x000002B2 */ +volatile CAN4TXIDR3STR _CAN4TXIDR3; /* MSCAN4 Transmit Identifier Register 3; 0x000002B3 */ +volatile CAN4TXDSR0STR _CAN4TXDSR0; /* MSCAN4 Transmit Data Segment Register 0; 0x000002B4 */ +volatile CAN4TXDSR1STR _CAN4TXDSR1; /* MSCAN4 Transmit Data Segment Register 1; 0x000002B5 */ +volatile CAN4TXDSR2STR _CAN4TXDSR2; /* MSCAN4 Transmit Data Segment Register 2; 0x000002B6 */ +volatile CAN4TXDSR3STR _CAN4TXDSR3; /* MSCAN4 Transmit Data Segment Register 3; 0x000002B7 */ +volatile CAN4TXDSR4STR _CAN4TXDSR4; /* MSCAN4 Transmit Data Segment Register 4; 0x000002B8 */ +volatile CAN4TXDSR5STR _CAN4TXDSR5; /* MSCAN4 Transmit Data Segment Register 5; 0x000002B9 */ +volatile CAN4TXDSR6STR _CAN4TXDSR6; /* MSCAN4 Transmit Data Segment Register 6; 0x000002BA */ +volatile CAN4TXDSR7STR _CAN4TXDSR7; /* MSCAN4 Transmit Data Segment Register 7; 0x000002BB */ +volatile CAN4TXDLRSTR _CAN4TXDLR; /* MSCAN4 Transmit Data Length Register; 0x000002BC */ +volatile CAN4TXTBPRSTR _CAN4TXTBPR; /* MSCAN4 Transmit Transmit Buffer Priority; 0x000002BD */ +/* NVFPROT3 - macro for reading non volatile register Non volatile Block 3 Flash Protection Register; 0x0000FF0A */ +/* NVFPROT2 - macro for reading non volatile register Non volatile Block 2 Flash Protection Register; 0x0000FF0B */ +/* NVFPROT1 - macro for reading non volatile register Non volatile Block 1 Flash Protection Register; 0x0000FF0C */ +/* NVFPROT0 - macro for reading non volatile register Non volatile Block 0 Flash Protection Register; 0x0000FF0D */ +/* NVFSEC - macro for reading non volatile register Non volatile Flash Security Register; 0x0000FF0F */ + + +/* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ +volatile PORTABSTR _PORTAB; /* Port AB Register; 0x00000000 */ +volatile DDRABSTR _DDRAB; /* Port AB Data Direction Register; 0x00000002 */ +volatile PARTIDSTR _PARTID; /* Part ID Register; 0x0000001A */ +volatile TCNTSTR _TCNT; /* Timer Count Register; 0x00000044 */ +volatile TC0STR _TC0; /* Timer Input Capture/Output Compare Register 0; 0x00000050 */ +volatile TC1STR _TC1; /* Timer Input Capture/Output Compare Register 1; 0x00000052 */ +volatile TC2STR _TC2; /* Timer Input Capture/Output Compare Register 2; 0x00000054 */ +volatile TC3STR _TC3; /* Timer Input Capture/Output Compare Register 3; 0x00000056 */ +volatile TC4STR _TC4; /* Timer Input Capture/Output Compare Register 4; 0x00000058 */ +volatile TC5STR _TC5; /* Timer Input Capture/Output Compare Register 5; 0x0000005A */ +volatile TC6STR _TC6; /* Timer Input Capture/Output Compare Register 6; 0x0000005C */ +volatile TC7STR _TC7; /* Timer Input Capture/Output Compare Register 7; 0x0000005E */ +volatile PACN32STR _PACN32; /* Pulse Accumulators Count 32 Register; 0x00000062 */ +volatile PACN10STR _PACN10; /* Pulse Accumulators Count 10 Register; 0x00000064 */ +volatile PA32HSTR _PA32H; /* 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 */ +volatile PA10HSTR _PA10H; /* 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 */ +volatile MCCNTSTR _MCCNT; /* Modulus Down-Counter Count Register; 0x00000076 */ +volatile TC0HSTR _TC0H; /* Timer Input Capture Holding Registers 0; 0x00000078 */ +volatile TC1HSTR _TC1H; /* Timer Input Capture Holding Registers 1; 0x0000007A */ +volatile TC2HSTR _TC2H; /* Timer Input Capture Holding Registers 2; 0x0000007C */ +volatile TC3HSTR _TC3H; /* Timer Input Capture Holding Registers 3; 0x0000007E */ +volatile ATD0CTL23STR _ATD0CTL23; /* ATD 0 Control Register 23; 0x00000082 */ +volatile ATD0CTL45STR _ATD0CTL45; /* ATD 0 Control Register 45; 0x00000084 */ +volatile ATD0DR0STR _ATD0DR0; /* ATD 0 Conversion Result Register 0; 0x00000090 */ +volatile ATD0DR1STR _ATD0DR1; /* ATD 0 Conversion Result Register 1; 0x00000092 */ +volatile ATD0DR2STR _ATD0DR2; /* ATD 0 Conversion Result Register 2; 0x00000094 */ +volatile ATD0DR3STR _ATD0DR3; /* ATD 0 Conversion Result Register 3; 0x00000096 */ +volatile ATD0DR4STR _ATD0DR4; /* ATD 0 Conversion Result Register 4; 0x00000098 */ +volatile ATD0DR5STR _ATD0DR5; /* ATD 0 Conversion Result Register 5; 0x0000009A */ +volatile ATD0DR6STR _ATD0DR6; /* ATD 0 Conversion Result Register 6; 0x0000009C */ +volatile ATD0DR7STR _ATD0DR7; /* ATD 0 Conversion Result Register 7; 0x0000009E */ +volatile PWMCNT01STR _PWMCNT01; /* PWM Channel Counter 01 Register; 0x000000AC */ +volatile PWMCNT23STR _PWMCNT23; /* PWM Channel Counter 23 Register; 0x000000AE */ +volatile PWMCNT45STR _PWMCNT45; /* PWM Channel Counter 45 Register; 0x000000B0 */ +volatile PWMCNT67STR _PWMCNT67; /* PWM Channel Counter 67 Register; 0x000000B2 */ +volatile PWMPER01STR _PWMPER01; /* PWM Channel Period 01 Register; 0x000000B4 */ +volatile PWMPER23STR _PWMPER23; /* PWM Channel Period 23 Register; 0x000000B6 */ +volatile PWMPER45STR _PWMPER45; /* PWM Channel Period 45 Register; 0x000000B8 */ +volatile PWMPER67STR _PWMPER67; /* PWM Channel Period 67 Register; 0x000000BA */ +volatile PWMDTY01STR _PWMDTY01; /* PWM Channel Duty 01 Register; 0x000000BC */ +volatile PWMDTY23STR _PWMDTY23; /* PWM Channel Duty 23 Register; 0x000000BE */ +volatile PWMDTY45STR _PWMDTY45; /* PWM Channel Duty 45 Register; 0x000000C0 */ +volatile PWMDTY67STR _PWMDTY67; /* PWM Channel Duty 67 Register; 0x000000C2 */ +volatile SCI0BDSTR _SCI0BD; /* SCI 0 Baud Rate Register; 0x000000C8 */ +volatile SCI1BDSTR _SCI1BD; /* SCI 1 Baud Rate Register; 0x000000D0 */ +volatile ATD1CTL23STR _ATD1CTL23; /* ATD 1 Control Register 23; 0x00000122 */ +volatile ATD1CTL45STR _ATD1CTL45; /* ATD 1 Control Register 45; 0x00000124 */ +volatile ATD1DR0STR _ATD1DR0; /* ATD 1 Conversion Result Register 0; 0x00000130 */ +volatile ATD1DR1STR _ATD1DR1; /* ATD 1 Conversion Result Register 1; 0x00000132 */ +volatile ATD1DR2STR _ATD1DR2; /* ATD 1 Conversion Result Register 2; 0x00000134 */ +volatile ATD1DR3STR _ATD1DR3; /* ATD 1 Conversion Result Register 3; 0x00000136 */ +volatile ATD1DR4STR _ATD1DR4; /* ATD 1 Conversion Result Register 4; 0x00000138 */ +volatile ATD1DR5STR _ATD1DR5; /* ATD 1 Conversion Result Register 5; 0x0000013A */ +volatile ATD1DR6STR _ATD1DR6; /* ATD 1 Conversion Result Register 6; 0x0000013C */ +volatile ATD1DR7STR _ATD1DR7; /* ATD 1 Conversion Result Register 7; 0x0000013E */ +volatile CAN0RXTSRSTR _CAN0RXTSR; /* MSCAN 0 Receive Time Stamp Register; 0x0000016E */ +volatile CAN0TXTSRSTR _CAN0TXTSR; /* MSCAN 0 Transmit Time Stamp Register; 0x0000017E */ +volatile CAN4RXTSRSTR _CAN4RXTSR; /* MSCAN 4 Receive Time Stamp Register; 0x000002AE */ +volatile CAN4TXTSRSTR _CAN4TXTSR; /* MSCAN 4 Transmit Time Stamp Register; 0x000002BE */ +/* BAKEY0 - macro for reading non volatile register Backdoor Access Key 0; 0x0000FF00 */ +/* BAKEY1 - macro for reading non volatile register Backdoor Access Key 1; 0x0000FF02 */ +/* BAKEY2 - macro for reading non volatile register Backdoor Access Key 2; 0x0000FF04 */ +/* BAKEY3 - macro for reading non volatile register Backdoor Access Key 3; 0x0000FF06 */ + +/*lint -restore */ + +/* EOF */ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/mc9s12dg256.h b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/mc9s12dg256.h new file mode 100644 index 00000000..d62524d9 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/lib/mc9s12dg256.h @@ -0,0 +1,16197 @@ +/* Based on CPU DB MC9S12DG256_112, version 2.87.347 (RegistersPrg V2.32) */ +/* +** ################################################################### +** Filename : mc9s12dg256.h +** Processor : MC9S12DG256CPV +** FileFormat: V2.32 +** DataSheet : 9S12DT256DGV3/D V03.04 +** Compiler : CodeWarrior compiler +** Date/Time : 8.6.2010, 9:00 +** Abstract : +** This header implements the mapping of I/O devices. +** +** Copyright : 1997 - 2010 Freescale Semiconductor, Inc. All Rights Reserved. +** +** http : www.freescale.com +** mail : support@freescale.com +** +** CPU Registers Revisions: +** - 24.05.2006, V2.87.285: +** - Removed bits MCCNTlo_BIT0..MCCNTlo_BIT7 and MCCNThi_BIT8.. MCCNThi_BIT15. REASON: Bug-fix (#3166 in Issue Manager) +** +** File-Format-Revisions: +** - 14.11.2005, V2.00 : +** - Deprecated symbols added for backward compatibility (section at the end of this file) +** - 15.11.2005, V2.01 : +** - Fixed invalid instruction in macro __RESET_WATCHDOG for HCS12 family. +** - 17.12.2005, V2.02 : +** - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778 +** - 16.01.2006, V2.03 : +** - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920. +** - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const") +** - 08.03.2006, V2.04 : +** - Support for bit(s) names duplicated with any register name in .h header files +** - 24.03.2006, V2.05 : +** - Fixed macro __RESET_WATCHDOG for HCS12 family - address and correct write order. +** - 26.04.2006, V2.06 : +** - Changes have not affected this file (because they are related to another family) +** - 27.04.2006, V2.07 : +** - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA). +** - 07.06.2006, V2.08 : +** - Changes have not affected this file (because they are related to another family) +** - 03.07.2006, V2.09 : +** - Changes have not affected this file (because they are related to another family) +** - 27.10.2006, V2.10 : +** - __RESET_WATCHDOG improved formating and re-definition +** - 23.11.2006, V2.11 : +** - Changes have not affected this file (because they are related to another family) +** - 22.01.2007, V2.12 : +** - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #4086. +** - 01.03.2007, V2.13 : +** - Flash commands constants values converted to HEX format +** - 02.03.2007, V2.14 : +** - Interrupt vector numbers added into .H, see VectorNumber_* +** - 26.03.2007, V2.15 : +** - Changes have not affected this file (because they are related to another family) +** - 10.05.2007, V2.16 : +** - Changes have not affected this file (because they are related to another family) +** - 05.06.2007, V2.17 : +** - Changes have not affected this file (because they are related to another family) +** - 19.07.2007, V2.18 : +** - Improved number of blanked lines inside register structures +** - 06.08.2007, V2.19 : +** - CPUDB revisions generated ahead of the file-format revisions. +** - 11.09.2007, V2.20 : +** - Added comment about initialization of unbonded pins. +** - 02.01.2008, V2.21 : +** - Changes have not affected this file (because they are related to another family) +** - 13.02.2008, V2.22 : +** - Changes have not affected this file (because they are related to another family) +** - 20.02.2008, V2.23 : +** - Termination of pragma V30toV31Compatible added, #5708 +** - 03.07.2008, V2.24 : +** - Added support for bits with name starting with number (like "1HZ") +** - 28.11.2008, V2.25 : +** - StandBy RAM array declaration for ANSI-C added +** - 1.12.2008, V2.26 : +** - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map. +** - 17.3.2009, V2.27 : +** - Merged bit-group is not generated, if the name matches with another bit name in the register +** - 6.4.2009, V2.28 : +** - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB +** - 3.8.2009, V2.29 : +** - If there is just one bits group matching register name, single bits are not generated +** - 10.9.2009, V2.30 : +** - Fixed generation of registers arrays. +** - 15.10.2009, V2.31 : +** - Changes have not affected this file (because they are related to another family) +** - 18.05.2010, V2.32 : +** - MISRA compliance: U/UL suffixes added to all numbers (_MASK,_BITNUM and addresses) +** +** Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific +** derivative device. To avoid extra current drain from floating input pins, the user’s reset +** initialization routine in the application program must either enable on-chip pull-up devices +** or change the direction of unconnected pins to outputs so the pins do not float. +** ################################################################### +*/ + +#ifndef _MC9S12DG256_H +#define _MC9S12DG256_H + +/*lint -save -e950 -esym(960,18.4) -e46 -esym(961,19.7) Disable MISRA rule (1.1,18.4,6.4,19.7) checking. */ +/* Types definition */ +typedef unsigned char byte; +typedef unsigned int word; +typedef unsigned long dword; +typedef unsigned long dlong[2]; + +#define REG_BASE 0x0000 /* Base address for the I/O register block */ + + +#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */ +#pragma OPTION ADD V30toV31Compatible "-BfaGapLimitBits4294967295" /*this guarantee correct bitfield positions*/ + +/**************** interrupt vector numbers ****************/ +#define VectorNumber_VReserved63 63U +#define VectorNumber_VReserved62 62U +#define VectorNumber_VReserved61 61U +#define VectorNumber_VReserved60 60U +#define VectorNumber_VReserved59 59U +#define VectorNumber_VReserved58 58U +#define VectorNumber_Vpwmesdn 57U +#define VectorNumber_Vportp 56U +#define VectorNumber_Vcan4tx 55U +#define VectorNumber_Vcan4rx 54U +#define VectorNumber_Vcan4err 53U +#define VectorNumber_Vcan4wkup 52U +#define VectorNumber_VReserved51 51U +#define VectorNumber_VReserved50 50U +#define VectorNumber_VReserved49 49U +#define VectorNumber_VReserved48 48U +#define VectorNumber_VReserved47 47U +#define VectorNumber_VReserved46 46U +#define VectorNumber_VReserved45 45U +#define VectorNumber_VReserved44 44U +#define VectorNumber_VReserved43 43U +#define VectorNumber_VReserved42 42U +#define VectorNumber_VReserved41 41U +#define VectorNumber_VReserved40 40U +#define VectorNumber_Vcan0tx 39U +#define VectorNumber_Vcan0rx 38U +#define VectorNumber_Vcan0err 37U +#define VectorNumber_Vcan0wkup 36U +#define VectorNumber_Vflash 35U +#define VectorNumber_Veeprom 34U +#define VectorNumber_Vspi2 33U +#define VectorNumber_Vspi1 32U +#define VectorNumber_Viic 31U +#define VectorNumber_VReserved30 30U +#define VectorNumber_Vcrgscm 29U +#define VectorNumber_Vcrgplllck 28U +#define VectorNumber_Vtimpabovf 27U +#define VectorNumber_Vtimmdcu 26U +#define VectorNumber_Vporth 25U +#define VectorNumber_Vportj 24U +#define VectorNumber_Vatd1 23U +#define VectorNumber_Vatd0 22U +#define VectorNumber_Vsci1 21U +#define VectorNumber_Vsci0 20U +#define VectorNumber_Vspi0 19U +#define VectorNumber_Vtimpaie 18U +#define VectorNumber_Vtimpaaovf 17U +#define VectorNumber_Vtimovf 16U +#define VectorNumber_Vtimch7 15U +#define VectorNumber_Vtimch6 14U +#define VectorNumber_Vtimch5 13U +#define VectorNumber_Vtimch4 12U +#define VectorNumber_Vtimch3 11U +#define VectorNumber_Vtimch2 10U +#define VectorNumber_Vtimch1 9U +#define VectorNumber_Vtimch0 8U +#define VectorNumber_Vrti 7U +#define VectorNumber_Virq 6U +#define VectorNumber_Vxirq 5U +#define VectorNumber_Vswi 4U +#define VectorNumber_Vtrap 3U +#define VectorNumber_Vcop 2U +#define VectorNumber_Vclkmon 1U +#define VectorNumber_Vreset 0U + +/**************** interrupt vector table ****************/ +#define VReserved63 0xFF80U +#define VReserved62 0xFF82U +#define VReserved61 0xFF84U +#define VReserved60 0xFF86U +#define VReserved59 0xFF88U +#define VReserved58 0xFF8AU +#define Vpwmesdn 0xFF8CU +#define Vportp 0xFF8EU +#define Vcan4tx 0xFF90U +#define Vcan4rx 0xFF92U +#define Vcan4err 0xFF94U +#define Vcan4wkup 0xFF96U +#define VReserved51 0xFF98U +#define VReserved50 0xFF9AU +#define VReserved49 0xFF9CU +#define VReserved48 0xFF9EU +#define VReserved47 0xFFA0U +#define VReserved46 0xFFA2U +#define VReserved45 0xFFA4U +#define VReserved44 0xFFA6U +#define VReserved43 0xFFA8U +#define VReserved42 0xFFAAU +#define VReserved41 0xFFACU +#define VReserved40 0xFFAEU +#define Vcan0tx 0xFFB0U +#define Vcan0rx 0xFFB2U +#define Vcan0err 0xFFB4U +#define Vcan0wkup 0xFFB6U +#define Vflash 0xFFB8U +#define Veeprom 0xFFBAU +#define Vspi2 0xFFBCU +#define Vspi1 0xFFBEU +#define Viic 0xFFC0U +#define VReserved30 0xFFC2U +#define Vcrgscm 0xFFC4U +#define Vcrgplllck 0xFFC6U +#define Vtimpabovf 0xFFC8U +#define Vtimmdcu 0xFFCAU +#define Vporth 0xFFCCU +#define Vportj 0xFFCEU +#define Vatd1 0xFFD0U +#define Vatd0 0xFFD2U +#define Vsci1 0xFFD4U +#define Vsci0 0xFFD6U +#define Vspi0 0xFFD8U +#define Vtimpaie 0xFFDAU +#define Vtimpaaovf 0xFFDCU +#define Vtimovf 0xFFDEU +#define Vtimch7 0xFFE0U +#define Vtimch6 0xFFE2U +#define Vtimch5 0xFFE4U +#define Vtimch4 0xFFE6U +#define Vtimch3 0xFFE8U +#define Vtimch2 0xFFEAU +#define Vtimch1 0xFFECU +#define Vtimch0 0xFFEEU +#define Vrti 0xFFF0U +#define Virq 0xFFF2U +#define Vxirq 0xFFF4U +#define Vswi 0xFFF6U +#define Vtrap 0xFFF8U +#define Vcop 0xFFFAU +#define Vclkmon 0xFFFCU +#define Vreset 0xFFFEU + +/**************** registers I/O map ****************/ + +/*** PORTAB - Port AB Register; 0x00000000 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PORTA - Port A Register; 0x00000000 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Port A Bit 0 */ + byte BIT1 :1; /* Port A Bit 1 */ + byte BIT2 :1; /* Port A Bit 2 */ + byte BIT3 :1; /* Port A Bit 3 */ + byte BIT4 :1; /* Port A Bit 4 */ + byte BIT5 :1; /* Port A Bit 5 */ + byte BIT6 :1; /* Port A Bit 6 */ + byte BIT7 :1; /* Port A Bit 7 */ + } Bits; + } PORTASTR; + #define PORTA _PORTAB.Overlap_STR.PORTASTR.Byte + #define PORTA_BIT0 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT0 + #define PORTA_BIT1 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT1 + #define PORTA_BIT2 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT2 + #define PORTA_BIT3 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT3 + #define PORTA_BIT4 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT4 + #define PORTA_BIT5 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT5 + #define PORTA_BIT6 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT6 + #define PORTA_BIT7 _PORTAB.Overlap_STR.PORTASTR.Bits.BIT7 + + #define PORTA_BIT0_MASK 1U + #define PORTA_BIT1_MASK 2U + #define PORTA_BIT2_MASK 4U + #define PORTA_BIT3_MASK 8U + #define PORTA_BIT4_MASK 16U + #define PORTA_BIT5_MASK 32U + #define PORTA_BIT6_MASK 64U + #define PORTA_BIT7_MASK 128U + + + /*** PORTB - Port B Register; 0x00000001 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Port B Bit 0 */ + byte BIT1 :1; /* Port B Bit 1 */ + byte BIT2 :1; /* Port B Bit 2 */ + byte BIT3 :1; /* Port B Bit 3 */ + byte BIT4 :1; /* Port B Bit 4 */ + byte BIT5 :1; /* Port B Bit 5 */ + byte BIT6 :1; /* Port B Bit 6 */ + byte BIT7 :1; /* Port B Bit 7 */ + } Bits; + } PORTBSTR; + #define PORTB _PORTAB.Overlap_STR.PORTBSTR.Byte + #define PORTB_BIT0 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT0 + #define PORTB_BIT1 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT1 + #define PORTB_BIT2 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT2 + #define PORTB_BIT3 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT3 + #define PORTB_BIT4 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT4 + #define PORTB_BIT5 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT5 + #define PORTB_BIT6 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT6 + #define PORTB_BIT7 _PORTAB.Overlap_STR.PORTBSTR.Bits.BIT7 + + #define PORTB_BIT0_MASK 1U + #define PORTB_BIT1_MASK 2U + #define PORTB_BIT2_MASK 4U + #define PORTB_BIT3_MASK 8U + #define PORTB_BIT4_MASK 16U + #define PORTB_BIT5_MASK 32U + #define PORTB_BIT6_MASK 64U + #define PORTB_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Port AB Bit 0 */ + word BIT1 :1; /* Port AB Bit 1 */ + word BIT2 :1; /* Port AB Bit 2 */ + word BIT3 :1; /* Port AB Bit 3 */ + word BIT4 :1; /* Port AB Bit 4 */ + word BIT5 :1; /* Port AB Bit 5 */ + word BIT6 :1; /* Port AB Bit 6 */ + word BIT7 :1; /* Port AB Bit 7 */ + word BIT8 :1; /* Port AB Bit 8 */ + word BIT9 :1; /* Port AB Bit 9 */ + word BIT10 :1; /* Port AB Bit 10 */ + word BIT11 :1; /* Port AB Bit 11 */ + word BIT12 :1; /* Port AB Bit 12 */ + word BIT13 :1; /* Port AB Bit 13 */ + word BIT14 :1; /* Port AB Bit 14 */ + word BIT15 :1; /* Port AB Bit 15 */ + } Bits; +} PORTABSTR; +extern volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000UL); +#define PORTAB _PORTAB.Word +#define PORTAB_BIT0 _PORTAB.Bits.BIT0 +#define PORTAB_BIT1 _PORTAB.Bits.BIT1 +#define PORTAB_BIT2 _PORTAB.Bits.BIT2 +#define PORTAB_BIT3 _PORTAB.Bits.BIT3 +#define PORTAB_BIT4 _PORTAB.Bits.BIT4 +#define PORTAB_BIT5 _PORTAB.Bits.BIT5 +#define PORTAB_BIT6 _PORTAB.Bits.BIT6 +#define PORTAB_BIT7 _PORTAB.Bits.BIT7 +#define PORTAB_BIT8 _PORTAB.Bits.BIT8 +#define PORTAB_BIT9 _PORTAB.Bits.BIT9 +#define PORTAB_BIT10 _PORTAB.Bits.BIT10 +#define PORTAB_BIT11 _PORTAB.Bits.BIT11 +#define PORTAB_BIT12 _PORTAB.Bits.BIT12 +#define PORTAB_BIT13 _PORTAB.Bits.BIT13 +#define PORTAB_BIT14 _PORTAB.Bits.BIT14 +#define PORTAB_BIT15 _PORTAB.Bits.BIT15 + +#define PORTAB_BIT0_MASK 1U +#define PORTAB_BIT1_MASK 2U +#define PORTAB_BIT2_MASK 4U +#define PORTAB_BIT3_MASK 8U +#define PORTAB_BIT4_MASK 16U +#define PORTAB_BIT5_MASK 32U +#define PORTAB_BIT6_MASK 64U +#define PORTAB_BIT7_MASK 128U +#define PORTAB_BIT8_MASK 256U +#define PORTAB_BIT9_MASK 512U +#define PORTAB_BIT10_MASK 1024U +#define PORTAB_BIT11_MASK 2048U +#define PORTAB_BIT12_MASK 4096U +#define PORTAB_BIT13_MASK 8192U +#define PORTAB_BIT14_MASK 16384U +#define PORTAB_BIT15_MASK 32768U + + +/*** DDRAB - Port AB Data Direction Register; 0x00000002 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** DDRA - Port A Data Direction Register; 0x00000002 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port A Bit 0 */ + byte BIT1 :1; /* Data Direction Port A Bit 1 */ + byte BIT2 :1; /* Data Direction Port A Bit 2 */ + byte BIT3 :1; /* Data Direction Port A Bit 3 */ + byte BIT4 :1; /* Data Direction Port A Bit 4 */ + byte BIT5 :1; /* Data Direction Port A Bit 5 */ + byte BIT6 :1; /* Data Direction Port A Bit 6 */ + byte BIT7 :1; /* Data Direction Port A Bit 7 */ + } Bits; + } DDRASTR; + #define DDRA _DDRAB.Overlap_STR.DDRASTR.Byte + #define DDRA_BIT0 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT0 + #define DDRA_BIT1 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT1 + #define DDRA_BIT2 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT2 + #define DDRA_BIT3 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT3 + #define DDRA_BIT4 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT4 + #define DDRA_BIT5 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT5 + #define DDRA_BIT6 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT6 + #define DDRA_BIT7 _DDRAB.Overlap_STR.DDRASTR.Bits.BIT7 + + #define DDRA_BIT0_MASK 1U + #define DDRA_BIT1_MASK 2U + #define DDRA_BIT2_MASK 4U + #define DDRA_BIT3_MASK 8U + #define DDRA_BIT4_MASK 16U + #define DDRA_BIT5_MASK 32U + #define DDRA_BIT6_MASK 64U + #define DDRA_BIT7_MASK 128U + + + /*** DDRB - Port B Data Direction Register; 0x00000003 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Data Direction Port B Bit 0 */ + byte BIT1 :1; /* Data Direction Port B Bit 1 */ + byte BIT2 :1; /* Data Direction Port B Bit 2 */ + byte BIT3 :1; /* Data Direction Port B Bit 3 */ + byte BIT4 :1; /* Data Direction Port B Bit 4 */ + byte BIT5 :1; /* Data Direction Port B Bit 5 */ + byte BIT6 :1; /* Data Direction Port B Bit 6 */ + byte BIT7 :1; /* Data Direction Port B Bit 7 */ + } Bits; + } DDRBSTR; + #define DDRB _DDRAB.Overlap_STR.DDRBSTR.Byte + #define DDRB_BIT0 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT0 + #define DDRB_BIT1 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT1 + #define DDRB_BIT2 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT2 + #define DDRB_BIT3 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT3 + #define DDRB_BIT4 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT4 + #define DDRB_BIT5 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT5 + #define DDRB_BIT6 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT6 + #define DDRB_BIT7 _DDRAB.Overlap_STR.DDRBSTR.Bits.BIT7 + + #define DDRB_BIT0_MASK 1U + #define DDRB_BIT1_MASK 2U + #define DDRB_BIT2_MASK 4U + #define DDRB_BIT3_MASK 8U + #define DDRB_BIT4_MASK 16U + #define DDRB_BIT5_MASK 32U + #define DDRB_BIT6_MASK 64U + #define DDRB_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Data Direction Port AB Bit 0 */ + word BIT1 :1; /* Data Direction Port AB Bit 1 */ + word BIT2 :1; /* Data Direction Port AB Bit 2 */ + word BIT3 :1; /* Data Direction Port AB Bit 3 */ + word BIT4 :1; /* Data Direction Port AB Bit 4 */ + word BIT5 :1; /* Data Direction Port AB Bit 5 */ + word BIT6 :1; /* Data Direction Port AB Bit 6 */ + word BIT7 :1; /* Data Direction Port AB Bit 7 */ + word BIT8 :1; /* Data Direction Port AB Bit 8 */ + word BIT9 :1; /* Data Direction Port AB Bit 9 */ + word BIT10 :1; /* Data Direction Port AB Bit 10 */ + word BIT11 :1; /* Data Direction Port AB Bit 11 */ + word BIT12 :1; /* Data Direction Port AB Bit 12 */ + word BIT13 :1; /* Data Direction Port AB Bit 13 */ + word BIT14 :1; /* Data Direction Port AB Bit 14 */ + word BIT15 :1; /* Data Direction Port AB Bit 15 */ + } Bits; +} DDRABSTR; +extern volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002UL); +#define DDRAB _DDRAB.Word +#define DDRAB_BIT0 _DDRAB.Bits.BIT0 +#define DDRAB_BIT1 _DDRAB.Bits.BIT1 +#define DDRAB_BIT2 _DDRAB.Bits.BIT2 +#define DDRAB_BIT3 _DDRAB.Bits.BIT3 +#define DDRAB_BIT4 _DDRAB.Bits.BIT4 +#define DDRAB_BIT5 _DDRAB.Bits.BIT5 +#define DDRAB_BIT6 _DDRAB.Bits.BIT6 +#define DDRAB_BIT7 _DDRAB.Bits.BIT7 +#define DDRAB_BIT8 _DDRAB.Bits.BIT8 +#define DDRAB_BIT9 _DDRAB.Bits.BIT9 +#define DDRAB_BIT10 _DDRAB.Bits.BIT10 +#define DDRAB_BIT11 _DDRAB.Bits.BIT11 +#define DDRAB_BIT12 _DDRAB.Bits.BIT12 +#define DDRAB_BIT13 _DDRAB.Bits.BIT13 +#define DDRAB_BIT14 _DDRAB.Bits.BIT14 +#define DDRAB_BIT15 _DDRAB.Bits.BIT15 + +#define DDRAB_BIT0_MASK 1U +#define DDRAB_BIT1_MASK 2U +#define DDRAB_BIT2_MASK 4U +#define DDRAB_BIT3_MASK 8U +#define DDRAB_BIT4_MASK 16U +#define DDRAB_BIT5_MASK 32U +#define DDRAB_BIT6_MASK 64U +#define DDRAB_BIT7_MASK 128U +#define DDRAB_BIT8_MASK 256U +#define DDRAB_BIT9_MASK 512U +#define DDRAB_BIT10_MASK 1024U +#define DDRAB_BIT11_MASK 2048U +#define DDRAB_BIT12_MASK 4096U +#define DDRAB_BIT13_MASK 8192U +#define DDRAB_BIT14_MASK 16384U +#define DDRAB_BIT15_MASK 32768U + + +/*** PORTE - Port E Register; 0x00000008 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port E Bit 0 */ + byte BIT1 :1; /* Port E Bit 1 */ + byte BIT2 :1; /* Port E Bit 2 */ + byte BIT3 :1; /* Port E Bit 3 */ + byte BIT4 :1; /* Port E Bit 4 */ + byte BIT5 :1; /* Port E Bit 5 */ + byte BIT6 :1; /* Port E Bit 6 */ + byte BIT7 :1; /* Port E Bit 7 */ + } Bits; +} PORTESTR; +extern volatile PORTESTR _PORTE @(REG_BASE + 0x00000008UL); +#define PORTE _PORTE.Byte +#define PORTE_BIT0 _PORTE.Bits.BIT0 +#define PORTE_BIT1 _PORTE.Bits.BIT1 +#define PORTE_BIT2 _PORTE.Bits.BIT2 +#define PORTE_BIT3 _PORTE.Bits.BIT3 +#define PORTE_BIT4 _PORTE.Bits.BIT4 +#define PORTE_BIT5 _PORTE.Bits.BIT5 +#define PORTE_BIT6 _PORTE.Bits.BIT6 +#define PORTE_BIT7 _PORTE.Bits.BIT7 + +#define PORTE_BIT0_MASK 1U +#define PORTE_BIT1_MASK 2U +#define PORTE_BIT2_MASK 4U +#define PORTE_BIT3_MASK 8U +#define PORTE_BIT4_MASK 16U +#define PORTE_BIT5_MASK 32U +#define PORTE_BIT6_MASK 64U +#define PORTE_BIT7_MASK 128U + + +/*** DDRE - Port E Data Direction Register; 0x00000009 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BIT2 :1; /* Data Direction Port E Bit 2 */ + byte BIT3 :1; /* Data Direction Port E Bit 3 */ + byte BIT4 :1; /* Data Direction Port E Bit 4 */ + byte BIT5 :1; /* Data Direction Port E Bit 5 */ + byte BIT6 :1; /* Data Direction Port E Bit 6 */ + byte BIT7 :1; /* Data Direction Port E Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte grpBIT_2 :6; + } MergedBits; +} DDRESTR; +extern volatile DDRESTR _DDRE @(REG_BASE + 0x00000009UL); +#define DDRE _DDRE.Byte +#define DDRE_BIT2 _DDRE.Bits.BIT2 +#define DDRE_BIT3 _DDRE.Bits.BIT3 +#define DDRE_BIT4 _DDRE.Bits.BIT4 +#define DDRE_BIT5 _DDRE.Bits.BIT5 +#define DDRE_BIT6 _DDRE.Bits.BIT6 +#define DDRE_BIT7 _DDRE.Bits.BIT7 +#define DDRE_BIT_2 _DDRE.MergedBits.grpBIT_2 +#define DDRE_BIT DDRE_BIT_2 + +#define DDRE_BIT2_MASK 4U +#define DDRE_BIT3_MASK 8U +#define DDRE_BIT4_MASK 16U +#define DDRE_BIT5_MASK 32U +#define DDRE_BIT6_MASK 64U +#define DDRE_BIT7_MASK 128U +#define DDRE_BIT_2_MASK 252U +#define DDRE_BIT_2_BITNUM 2U + + +/*** PEAR - Port E Assignment Register; 0x0000000A ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte RDWE :1; /* Read / Write Enable */ + byte LSTRE :1; /* Low Strobe (LSTRB) Enable */ + byte NECLK :1; /* No External E Clock */ + byte PIPOE :1; /* Pipe Status Signal Output Enable */ + byte :1; + byte NOACCE :1; /* CPU No Access Output Enable */ + } Bits; +} PEARSTR; +extern volatile PEARSTR _PEAR @(REG_BASE + 0x0000000AUL); +#define PEAR _PEAR.Byte +#define PEAR_RDWE _PEAR.Bits.RDWE +#define PEAR_LSTRE _PEAR.Bits.LSTRE +#define PEAR_NECLK _PEAR.Bits.NECLK +#define PEAR_PIPOE _PEAR.Bits.PIPOE +#define PEAR_NOACCE _PEAR.Bits.NOACCE + +#define PEAR_RDWE_MASK 4U +#define PEAR_LSTRE_MASK 8U +#define PEAR_NECLK_MASK 16U +#define PEAR_PIPOE_MASK 32U +#define PEAR_NOACCE_MASK 128U + + +/*** MODE - Mode Register; 0x0000000B ***/ +typedef union { + byte Byte; + struct { + byte EME :1; /* Emulate Port E */ + byte EMK :1; /* Emulate Port K */ + byte :1; + byte IVIS :1; /* Internal Visibility */ + byte :1; + byte MODA :1; /* Mode Select Bit A */ + byte MODB :1; /* Mode Select Bit B */ + byte MODC :1; /* Mode Select Bit C */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpMODx :3; + } MergedBits; +} MODESTR; +extern volatile MODESTR _MODE @(REG_BASE + 0x0000000BUL); +#define MODE _MODE.Byte +#define MODE_EME _MODE.Bits.EME +#define MODE_EMK _MODE.Bits.EMK +#define MODE_IVIS _MODE.Bits.IVIS +#define MODE_MODA _MODE.Bits.MODA +#define MODE_MODB _MODE.Bits.MODB +#define MODE_MODC _MODE.Bits.MODC +#define MODE_MODx _MODE.MergedBits.grpMODx + +#define MODE_EME_MASK 1U +#define MODE_EMK_MASK 2U +#define MODE_IVIS_MASK 8U +#define MODE_MODA_MASK 32U +#define MODE_MODB_MASK 64U +#define MODE_MODC_MASK 128U +#define MODE_MODx_MASK 224U +#define MODE_MODx_BITNUM 5U + + +/*** PUCR - Pull-Up Control Register; 0x0000000C ***/ +typedef union { + byte Byte; + struct { + byte PUPAE :1; /* Pull-Up Port A Enable */ + byte PUPBE :1; /* Pull-Up Port B Enable */ + byte :1; + byte :1; + byte PUPEE :1; /* Pull-Up Port E Enable */ + byte :1; + byte :1; + byte PUPKE :1; /* Pull-Up Port K Enable */ + } Bits; +} PUCRSTR; +extern volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000CUL); +#define PUCR _PUCR.Byte +#define PUCR_PUPAE _PUCR.Bits.PUPAE +#define PUCR_PUPBE _PUCR.Bits.PUPBE +#define PUCR_PUPEE _PUCR.Bits.PUPEE +#define PUCR_PUPKE _PUCR.Bits.PUPKE + +#define PUCR_PUPAE_MASK 1U +#define PUCR_PUPBE_MASK 2U +#define PUCR_PUPEE_MASK 16U +#define PUCR_PUPKE_MASK 128U + + +/*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***/ +typedef union { + byte Byte; + struct { + byte RDPA :1; /* Reduced Drive of Port A */ + byte RDPB :1; /* Reduced Drive of Port B */ + byte :1; + byte :1; + byte RDPE :1; /* Reduced Drive of Port E */ + byte :1; + byte :1; + byte RDPK :1; /* Reduced Drive of Port K */ + } Bits; + struct { + byte grpRDPx :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} RDRIVSTR; +extern volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000DUL); +#define RDRIV _RDRIV.Byte +#define RDRIV_RDPA _RDRIV.Bits.RDPA +#define RDRIV_RDPB _RDRIV.Bits.RDPB +#define RDRIV_RDPE _RDRIV.Bits.RDPE +#define RDRIV_RDPK _RDRIV.Bits.RDPK +#define RDRIV_RDPx _RDRIV.MergedBits.grpRDPx + +#define RDRIV_RDPA_MASK 1U +#define RDRIV_RDPB_MASK 2U +#define RDRIV_RDPE_MASK 16U +#define RDRIV_RDPK_MASK 128U +#define RDRIV_RDPx_MASK 3U +#define RDRIV_RDPx_BITNUM 0U + + +/*** EBICTL - External Bus Interface Control; 0x0000000E ***/ +typedef union { + byte Byte; + struct { + byte ESTR :1; /* E Stretches */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} EBICTLSTR; +extern volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000EUL); +#define EBICTL _EBICTL.Byte +#define EBICTL_ESTR _EBICTL.Bits.ESTR + +#define EBICTL_ESTR_MASK 1U + + +/*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***/ +typedef union { + byte Byte; + struct { + byte RAMHAL :1; /* Internal RAM map alignment */ + byte :1; + byte :1; + byte RAM11 :1; /* Internal RAM map position Bit 11 */ + byte RAM12 :1; /* Internal RAM map position Bit 12 */ + byte RAM13 :1; /* Internal RAM map position Bit 13 */ + byte RAM14 :1; /* Internal RAM map position Bit 14 */ + byte RAM15 :1; /* Internal RAM map position Bit 15 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpRAM_11 :5; + } MergedBits; +} INITRMSTR; +extern volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010UL); +#define INITRM _INITRM.Byte +#define INITRM_RAMHAL _INITRM.Bits.RAMHAL +#define INITRM_RAM11 _INITRM.Bits.RAM11 +#define INITRM_RAM12 _INITRM.Bits.RAM12 +#define INITRM_RAM13 _INITRM.Bits.RAM13 +#define INITRM_RAM14 _INITRM.Bits.RAM14 +#define INITRM_RAM15 _INITRM.Bits.RAM15 +#define INITRM_RAM_11 _INITRM.MergedBits.grpRAM_11 +#define INITRM_RAM INITRM_RAM_11 + +#define INITRM_RAMHAL_MASK 1U +#define INITRM_RAM11_MASK 8U +#define INITRM_RAM12_MASK 16U +#define INITRM_RAM13_MASK 32U +#define INITRM_RAM14_MASK 64U +#define INITRM_RAM15_MASK 128U +#define INITRM_RAM_11_MASK 248U +#define INITRM_RAM_11_BITNUM 3U + + +/*** INITRG - Initialization of Internal Registers Position Register; 0x00000011 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte REG11 :1; /* Internal Registers Map Position Bit 11 */ + byte REG12 :1; /* Internal Registers Map Position Bit 12 */ + byte REG13 :1; /* Internal Registers Map Position Bit 13 */ + byte REG14 :1; /* Internal Registers Map Position Bit 14 */ + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte grpREG_11 :4; + byte :1; + } MergedBits; +} INITRGSTR; +extern volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011UL); +#define INITRG _INITRG.Byte +#define INITRG_REG11 _INITRG.Bits.REG11 +#define INITRG_REG12 _INITRG.Bits.REG12 +#define INITRG_REG13 _INITRG.Bits.REG13 +#define INITRG_REG14 _INITRG.Bits.REG14 +#define INITRG_REG_11 _INITRG.MergedBits.grpREG_11 +#define INITRG_REG INITRG_REG_11 + +#define INITRG_REG11_MASK 8U +#define INITRG_REG12_MASK 16U +#define INITRG_REG13_MASK 32U +#define INITRG_REG14_MASK 64U +#define INITRG_REG_11_MASK 120U +#define INITRG_REG_11_BITNUM 3U + + +/*** INITEE - Initialization of Internal EEPROM Position Register; 0x00000012 ***/ +typedef union { + byte Byte; + struct { + byte EEON :1; /* Internal EEPROM On */ + byte :1; + byte :1; + byte :1; + byte EE12 :1; /* Internal EEPROM map position Bit 12 */ + byte EE13 :1; /* Internal EEPROM map position Bit 13 */ + byte EE14 :1; /* Internal EEPROM map position Bit 14 */ + byte EE15 :1; /* Internal EEPROM map position Bit 15 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte grpEE_12 :4; + } MergedBits; +} INITEESTR; +extern volatile INITEESTR _INITEE @(REG_BASE + 0x00000012UL); +#define INITEE _INITEE.Byte +#define INITEE_EEON _INITEE.Bits.EEON +#define INITEE_EE12 _INITEE.Bits.EE12 +#define INITEE_EE13 _INITEE.Bits.EE13 +#define INITEE_EE14 _INITEE.Bits.EE14 +#define INITEE_EE15 _INITEE.Bits.EE15 +#define INITEE_EE_12 _INITEE.MergedBits.grpEE_12 +#define INITEE_EE INITEE_EE_12 + +#define INITEE_EEON_MASK 1U +#define INITEE_EE12_MASK 16U +#define INITEE_EE13_MASK 32U +#define INITEE_EE14_MASK 64U +#define INITEE_EE15_MASK 128U +#define INITEE_EE_12_MASK 240U +#define INITEE_EE_12_BITNUM 4U + + +/*** MISC - Miscellaneous System Control Register; 0x00000013 ***/ +typedef union { + byte Byte; + struct { + byte ROMON :1; /* Enable Flash EEPROM */ + byte ROMHM :1; /* Flash EEPROM only in second half of memory map */ + byte EXSTR0 :1; /* External Access Stretch Bit 0 */ + byte EXSTR1 :1; /* External Access Stretch Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpEXSTR :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MISCSTR; +extern volatile MISCSTR _MISC @(REG_BASE + 0x00000013UL); +#define MISC _MISC.Byte +#define MISC_ROMON _MISC.Bits.ROMON +#define MISC_ROMHM _MISC.Bits.ROMHM +#define MISC_EXSTR0 _MISC.Bits.EXSTR0 +#define MISC_EXSTR1 _MISC.Bits.EXSTR1 +#define MISC_EXSTR _MISC.MergedBits.grpEXSTR + +#define MISC_ROMON_MASK 1U +#define MISC_ROMHM_MASK 2U +#define MISC_EXSTR0_MASK 4U +#define MISC_EXSTR1_MASK 8U +#define MISC_EXSTR_MASK 12U +#define MISC_EXSTR_BITNUM 2U + + +/*** ITCR - Interrupt Test Control Register; 0x00000015 ***/ +typedef union { + byte Byte; + struct { + byte ADR0 :1; /* Test register select Bit 0 */ + byte ADR1 :1; /* Test register select Bit 1 */ + byte ADR2 :1; /* Test register select Bit 2 */ + byte ADR3 :1; /* Test register select Bit 3 */ + byte WRTINT :1; /* Write to the Interrupt Test Registers */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpADR :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ITCRSTR; +extern volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015UL); +#define ITCR _ITCR.Byte +#define ITCR_ADR0 _ITCR.Bits.ADR0 +#define ITCR_ADR1 _ITCR.Bits.ADR1 +#define ITCR_ADR2 _ITCR.Bits.ADR2 +#define ITCR_ADR3 _ITCR.Bits.ADR3 +#define ITCR_WRTINT _ITCR.Bits.WRTINT +#define ITCR_ADR _ITCR.MergedBits.grpADR + +#define ITCR_ADR0_MASK 1U +#define ITCR_ADR1_MASK 2U +#define ITCR_ADR2_MASK 4U +#define ITCR_ADR3_MASK 8U +#define ITCR_WRTINT_MASK 16U +#define ITCR_ADR_MASK 15U +#define ITCR_ADR_BITNUM 0U + + +/*** ITEST - Interrupt Test Register; 0x00000016 ***/ +typedef union { + byte Byte; + struct { + byte INT0 :1; /* Interrupt Test Register Bit 0 */ + byte INT2 :1; /* Interrupt Test Register Bit 1 */ + byte INT4 :1; /* Interrupt Test Register Bit 2 */ + byte INT6 :1; /* Interrupt Test Register Bit 3 */ + byte INT8 :1; /* Interrupt Test Register Bit 4 */ + byte INTA :1; /* Interrupt Test Register Bit 5 */ + byte INTC :1; /* Interrupt Test Register Bit 6 */ + byte INTE :1; /* Interrupt Test Register Bit 7 */ + } Bits; +} ITESTSTR; +extern volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016UL); +#define ITEST _ITEST.Byte +#define ITEST_INT0 _ITEST.Bits.INT0 +#define ITEST_INT2 _ITEST.Bits.INT2 +#define ITEST_INT4 _ITEST.Bits.INT4 +#define ITEST_INT6 _ITEST.Bits.INT6 +#define ITEST_INT8 _ITEST.Bits.INT8 +#define ITEST_INTA _ITEST.Bits.INTA +#define ITEST_INTC _ITEST.Bits.INTC +#define ITEST_INTE _ITEST.Bits.INTE + +#define ITEST_INT0_MASK 1U +#define ITEST_INT2_MASK 2U +#define ITEST_INT4_MASK 4U +#define ITEST_INT6_MASK 8U +#define ITEST_INT8_MASK 16U +#define ITEST_INTA_MASK 32U +#define ITEST_INTC_MASK 64U +#define ITEST_INTE_MASK 128U + + +/*** PARTID - Part ID Register; 0x0000001A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PARTIDH - Part ID Register High; 0x0000001A ***/ + union { + byte Byte; + struct { + byte ID8 :1; /* Part ID Register Bit 8 */ + byte ID9 :1; /* Part ID Register Bit 9 */ + byte ID10 :1; /* Part ID Register Bit 10 */ + byte ID11 :1; /* Part ID Register Bit 11 */ + byte ID12 :1; /* Part ID Register Bit 12 */ + byte ID13 :1; /* Part ID Register Bit 13 */ + byte ID14 :1; /* Part ID Register Bit 14 */ + byte ID15 :1; /* Part ID Register Bit 15 */ + } Bits; + } PARTIDHSTR; + #define PARTIDH _PARTID.Overlap_STR.PARTIDHSTR.Byte + #define PARTIDH_ID8 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID8 + #define PARTIDH_ID9 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID9 + #define PARTIDH_ID10 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID10 + #define PARTIDH_ID11 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID11 + #define PARTIDH_ID12 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID12 + #define PARTIDH_ID13 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID13 + #define PARTIDH_ID14 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID14 + #define PARTIDH_ID15 _PARTID.Overlap_STR.PARTIDHSTR.Bits.ID15 + + #define PARTIDH_ID8_MASK 1U + #define PARTIDH_ID9_MASK 2U + #define PARTIDH_ID10_MASK 4U + #define PARTIDH_ID11_MASK 8U + #define PARTIDH_ID12_MASK 16U + #define PARTIDH_ID13_MASK 32U + #define PARTIDH_ID14_MASK 64U + #define PARTIDH_ID15_MASK 128U + + + /*** PARTIDL - Part ID Register Low; 0x0000001B ***/ + union { + byte Byte; + struct { + byte ID0 :1; /* Part ID Register Bit 0 */ + byte ID1 :1; /* Part ID Register Bit 1 */ + byte ID2 :1; /* Part ID Register Bit 2 */ + byte ID3 :1; /* Part ID Register Bit 3 */ + byte ID4 :1; /* Part ID Register Bit 4 */ + byte ID5 :1; /* Part ID Register Bit 5 */ + byte ID6 :1; /* Part ID Register Bit 6 */ + byte ID7 :1; /* Part ID Register Bit 7 */ + } Bits; + } PARTIDLSTR; + #define PARTIDL _PARTID.Overlap_STR.PARTIDLSTR.Byte + #define PARTIDL_ID0 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID0 + #define PARTIDL_ID1 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID1 + #define PARTIDL_ID2 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID2 + #define PARTIDL_ID3 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID3 + #define PARTIDL_ID4 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID4 + #define PARTIDL_ID5 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID5 + #define PARTIDL_ID6 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID6 + #define PARTIDL_ID7 _PARTID.Overlap_STR.PARTIDLSTR.Bits.ID7 + + #define PARTIDL_ID0_MASK 1U + #define PARTIDL_ID1_MASK 2U + #define PARTIDL_ID2_MASK 4U + #define PARTIDL_ID3_MASK 8U + #define PARTIDL_ID4_MASK 16U + #define PARTIDL_ID5_MASK 32U + #define PARTIDL_ID6_MASK 64U + #define PARTIDL_ID7_MASK 128U + + } Overlap_STR; + + struct { + word ID0 :1; /* Part ID Register Bit 0 */ + word ID1 :1; /* Part ID Register Bit 1 */ + word ID2 :1; /* Part ID Register Bit 2 */ + word ID3 :1; /* Part ID Register Bit 3 */ + word ID4 :1; /* Part ID Register Bit 4 */ + word ID5 :1; /* Part ID Register Bit 5 */ + word ID6 :1; /* Part ID Register Bit 6 */ + word ID7 :1; /* Part ID Register Bit 7 */ + word ID8 :1; /* Part ID Register Bit 8 */ + word ID9 :1; /* Part ID Register Bit 9 */ + word ID10 :1; /* Part ID Register Bit 10 */ + word ID11 :1; /* Part ID Register Bit 11 */ + word ID12 :1; /* Part ID Register Bit 12 */ + word ID13 :1; /* Part ID Register Bit 13 */ + word ID14 :1; /* Part ID Register Bit 14 */ + word ID15 :1; /* Part ID Register Bit 15 */ + } Bits; +} PARTIDSTR; +extern volatile PARTIDSTR _PARTID @(REG_BASE + 0x0000001AUL); +#define PARTID _PARTID.Word +#define PARTID_ID0 _PARTID.Bits.ID0 +#define PARTID_ID1 _PARTID.Bits.ID1 +#define PARTID_ID2 _PARTID.Bits.ID2 +#define PARTID_ID3 _PARTID.Bits.ID3 +#define PARTID_ID4 _PARTID.Bits.ID4 +#define PARTID_ID5 _PARTID.Bits.ID5 +#define PARTID_ID6 _PARTID.Bits.ID6 +#define PARTID_ID7 _PARTID.Bits.ID7 +#define PARTID_ID8 _PARTID.Bits.ID8 +#define PARTID_ID9 _PARTID.Bits.ID9 +#define PARTID_ID10 _PARTID.Bits.ID10 +#define PARTID_ID11 _PARTID.Bits.ID11 +#define PARTID_ID12 _PARTID.Bits.ID12 +#define PARTID_ID13 _PARTID.Bits.ID13 +#define PARTID_ID14 _PARTID.Bits.ID14 +#define PARTID_ID15 _PARTID.Bits.ID15 + +#define PARTID_ID0_MASK 1U +#define PARTID_ID1_MASK 2U +#define PARTID_ID2_MASK 4U +#define PARTID_ID3_MASK 8U +#define PARTID_ID4_MASK 16U +#define PARTID_ID5_MASK 32U +#define PARTID_ID6_MASK 64U +#define PARTID_ID7_MASK 128U +#define PARTID_ID8_MASK 256U +#define PARTID_ID9_MASK 512U +#define PARTID_ID10_MASK 1024U +#define PARTID_ID11_MASK 2048U +#define PARTID_ID12_MASK 4096U +#define PARTID_ID13_MASK 8192U +#define PARTID_ID14_MASK 16384U +#define PARTID_ID15_MASK 32768U + + +/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/ +typedef union { + byte Byte; + struct { + byte ram_sw0 :1; /* Allocated System RAM Memory Space Bit 0 */ + byte ram_sw1 :1; /* Allocated System RAM Memory Space Bit 1 */ + byte ram_sw2 :1; /* Allocated System RAM Memory Space Bit 2 */ + byte :1; + byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */ + byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */ + byte :1; + byte reg_sw0 :1; /* Allocated System Register Space */ + } Bits; + struct { + byte grpram_sw :3; + byte :1; + byte grpeep_sw :2; + byte :1; + byte grpreg_sw :1; + } MergedBits; +} MEMSIZ0STR; +extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001CUL); +#define MEMSIZ0 _MEMSIZ0.Byte +#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0 +#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1 +#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2 +#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0 +#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1 +#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0 +/* MEMSIZ_ARR: Access 2 MEMSIZx registers in an array */ +#define MEMSIZ_ARR ((volatile byte *) &MEMSIZ0) +#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw +#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw + +#define MEMSIZ0_ram_sw0_MASK 1U +#define MEMSIZ0_ram_sw1_MASK 2U +#define MEMSIZ0_ram_sw2_MASK 4U +#define MEMSIZ0_eep_sw0_MASK 16U +#define MEMSIZ0_eep_sw1_MASK 32U +#define MEMSIZ0_reg_sw0_MASK 128U +#define MEMSIZ0_ram_sw_MASK 7U +#define MEMSIZ0_ram_sw_BITNUM 0U +#define MEMSIZ0_eep_sw_MASK 48U +#define MEMSIZ0_eep_sw_BITNUM 4U + + +/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/ +typedef union { + byte Byte; + struct { + byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */ + byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */ + byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */ + } Bits; + struct { + byte grppag_sw :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grprom_sw :2; + } MergedBits; +} MEMSIZ1STR; +extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001DUL); +#define MEMSIZ1 _MEMSIZ1.Byte +#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0 +#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1 +#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0 +#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1 +#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw +#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw + +#define MEMSIZ1_pag_sw0_MASK 1U +#define MEMSIZ1_pag_sw1_MASK 2U +#define MEMSIZ1_rom_sw0_MASK 64U +#define MEMSIZ1_rom_sw1_MASK 128U +#define MEMSIZ1_pag_sw_MASK 3U +#define MEMSIZ1_pag_sw_BITNUM 0U +#define MEMSIZ1_rom_sw_MASK 192U +#define MEMSIZ1_rom_sw_BITNUM 6U + + +/*** INTCR - Interrupt Control Register; 0x0000001E ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte IRQEN :1; /* External IRQ Enable */ + byte IRQE :1; /* IRQ Select Edge Sensitive Only */ + } Bits; +} INTCRSTR; +extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001EUL); +#define INTCR _INTCR.Byte +#define INTCR_IRQEN _INTCR.Bits.IRQEN +#define INTCR_IRQE _INTCR.Bits.IRQE + +#define INTCR_IRQEN_MASK 64U +#define INTCR_IRQE_MASK 128U + + +/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */ + byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */ + byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */ + byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */ + byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */ + byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */ + byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */ + } Bits; + struct { + byte :1; + byte grpPSEL_1 :7; + } MergedBits; +} HPRIOSTR; +extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001FUL); +#define HPRIO _HPRIO.Byte +#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1 +#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2 +#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3 +#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4 +#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5 +#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6 +#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7 +#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1 +#define HPRIO_PSEL HPRIO_PSEL_1 + +#define HPRIO_PSEL1_MASK 2U +#define HPRIO_PSEL2_MASK 4U +#define HPRIO_PSEL3_MASK 8U +#define HPRIO_PSEL4_MASK 16U +#define HPRIO_PSEL5_MASK 32U +#define HPRIO_PSEL6_MASK 64U +#define HPRIO_PSEL7_MASK 128U +#define HPRIO_PSEL_1_MASK 254U +#define HPRIO_PSEL_1_BITNUM 1U + + +/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte BKTAG :1; /* Breakpoint on Tag */ + byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */ + byte BKFULL :1; /* Full Breakpoint Mode Enable */ + byte BKEN :1; /* Breakpoint Enable */ + } Bits; +} BKPCT0STR; +extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028UL); +#define BKPCT0 _BKPCT0.Byte +#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG +#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM +#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL +#define BKPCT0_BKEN _BKPCT0.Bits.BKEN +/* BKPCT_ARR: Access 2 BKPCTx registers in an array */ +#define BKPCT_ARR ((volatile byte *) &BKPCT0) + +#define BKPCT0_BKTAG_MASK 16U +#define BKPCT0_BKBDM_MASK 32U +#define BKPCT0_BKFULL_MASK 64U +#define BKPCT0_BKEN_MASK 128U + + +/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/ +typedef union { + byte Byte; + struct { + byte BK1RW :1; /* R/W Compare Value 1 */ + byte BK1RWE :1; /* R/W Compare Enable 1 */ + byte BK0RW :1; /* R/W Compare Value 0 */ + byte BK0RWE :1; /* R/W Compare Enable 0 */ + byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */ + byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */ + byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */ + byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */ + } Bits; +} BKPCT1STR; +extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029UL); +#define BKPCT1 _BKPCT1.Byte +#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW +#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE +#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW +#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE +#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL +#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH +#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL +#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH + +#define BKPCT1_BK1RW_MASK 1U +#define BKPCT1_BK1RWE_MASK 2U +#define BKPCT1_BK0RW_MASK 4U +#define BKPCT1_BK0RWE_MASK 8U +#define BKPCT1_BK1MBL_MASK 16U +#define BKPCT1_BK1MBH_MASK 32U +#define BKPCT1_BK0MBL_MASK 64U +#define BKPCT1_BK0MBH_MASK 128U + + +/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/ +typedef union { + byte Byte; + struct { + byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */ + byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */ + byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */ + byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */ + byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */ + byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpBK0V :6; + byte :1; + byte :1; + } MergedBits; +} BKP0XSTR; +extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002AUL); +#define BKP0X _BKP0X.Byte +#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0 +#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1 +#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2 +#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3 +#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4 +#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5 +#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V + +#define BKP0X_BK0V0_MASK 1U +#define BKP0X_BK0V1_MASK 2U +#define BKP0X_BK0V2_MASK 4U +#define BKP0X_BK0V3_MASK 8U +#define BKP0X_BK0V4_MASK 16U +#define BKP0X_BK0V5_MASK 32U +#define BKP0X_BK0V_MASK 63U +#define BKP0X_BK0V_BITNUM 0U + + +/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */ + byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */ + byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */ + byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */ + byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */ + byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */ + byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */ + byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */ + } Bits; +} BKP0HSTR; +extern volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002BUL); +#define BKP0H _BKP0H.Byte +#define BKP0H_BIT8 _BKP0H.Bits.BIT8 +#define BKP0H_BIT9 _BKP0H.Bits.BIT9 +#define BKP0H_BIT10 _BKP0H.Bits.BIT10 +#define BKP0H_BIT11 _BKP0H.Bits.BIT11 +#define BKP0H_BIT12 _BKP0H.Bits.BIT12 +#define BKP0H_BIT13 _BKP0H.Bits.BIT13 +#define BKP0H_BIT14 _BKP0H.Bits.BIT14 +#define BKP0H_BIT15 _BKP0H.Bits.BIT15 + +#define BKP0H_BIT8_MASK 1U +#define BKP0H_BIT9_MASK 2U +#define BKP0H_BIT10_MASK 4U +#define BKP0H_BIT11_MASK 8U +#define BKP0H_BIT12_MASK 16U +#define BKP0H_BIT13_MASK 32U +#define BKP0H_BIT14_MASK 64U +#define BKP0H_BIT15_MASK 128U + + +/*** BKP0L - First Address Low Byte Breakpoint Register; 0x0000002C ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* First Address Breakpoint Register Bit 0 */ + byte BIT1 :1; /* First Address Breakpoint Register Bit 1 */ + byte BIT2 :1; /* First Address Breakpoint Register Bit 2 */ + byte BIT3 :1; /* First Address Breakpoint Register Bit 3 */ + byte BIT4 :1; /* First Address Breakpoint Register Bit 4 */ + byte BIT5 :1; /* First Address Breakpoint Register Bit 5 */ + byte BIT6 :1; /* First Address Breakpoint Register Bit 6 */ + byte BIT7 :1; /* First Address Breakpoint Register Bit 7 */ + } Bits; +} BKP0LSTR; +extern volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002CUL); +#define BKP0L _BKP0L.Byte +#define BKP0L_BIT0 _BKP0L.Bits.BIT0 +#define BKP0L_BIT1 _BKP0L.Bits.BIT1 +#define BKP0L_BIT2 _BKP0L.Bits.BIT2 +#define BKP0L_BIT3 _BKP0L.Bits.BIT3 +#define BKP0L_BIT4 _BKP0L.Bits.BIT4 +#define BKP0L_BIT5 _BKP0L.Bits.BIT5 +#define BKP0L_BIT6 _BKP0L.Bits.BIT6 +#define BKP0L_BIT7 _BKP0L.Bits.BIT7 + +#define BKP0L_BIT0_MASK 1U +#define BKP0L_BIT1_MASK 2U +#define BKP0L_BIT2_MASK 4U +#define BKP0L_BIT3_MASK 8U +#define BKP0L_BIT4_MASK 16U +#define BKP0L_BIT5_MASK 32U +#define BKP0L_BIT6_MASK 64U +#define BKP0L_BIT7_MASK 128U + + +/*** BKP1X - Second Address Memory Expansion Breakpoint Register; 0x0000002D ***/ +typedef union { + byte Byte; + struct { + byte BK1V0 :1; /* Second Address Breakpoint Expansion Address Value Bit 0 */ + byte BK1V1 :1; /* Second Address Breakpoint Expansion Address Value Bit 1 */ + byte BK1V2 :1; /* Second Address Breakpoint Expansion Address Value Bit 2 */ + byte BK1V3 :1; /* Second Address Breakpoint Expansion Address Value Bit 3 */ + byte BK1V4 :1; /* Second Address Breakpoint Expansion Address Value Bit 4 */ + byte BK1V5 :1; /* Second Address Breakpoint Expansion Address Value Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpBK1V :6; + byte :1; + byte :1; + } MergedBits; +} BKP1XSTR; +extern volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002DUL); +#define BKP1X _BKP1X.Byte +#define BKP1X_BK1V0 _BKP1X.Bits.BK1V0 +#define BKP1X_BK1V1 _BKP1X.Bits.BK1V1 +#define BKP1X_BK1V2 _BKP1X.Bits.BK1V2 +#define BKP1X_BK1V3 _BKP1X.Bits.BK1V3 +#define BKP1X_BK1V4 _BKP1X.Bits.BK1V4 +#define BKP1X_BK1V5 _BKP1X.Bits.BK1V5 +#define BKP1X_BK1V _BKP1X.MergedBits.grpBK1V + +#define BKP1X_BK1V0_MASK 1U +#define BKP1X_BK1V1_MASK 2U +#define BKP1X_BK1V2_MASK 4U +#define BKP1X_BK1V3_MASK 8U +#define BKP1X_BK1V4_MASK 16U +#define BKP1X_BK1V5_MASK 32U +#define BKP1X_BK1V_MASK 63U +#define BKP1X_BK1V_BITNUM 0U + + +/*** BKP1H - Data (Second Address) High Byte Breakpoint Register; 0x0000002E ***/ +typedef union { + byte Byte; + struct { + byte BIT8 :1; /* Data (Second Address) Breakpoint Register Bit 8 */ + byte BIT9 :1; /* Data (Second Address) Breakpoint Register Bit 9 */ + byte BIT10 :1; /* Data (Second Address) Breakpoint Register Bit 10 */ + byte BIT11 :1; /* Data (Second Address) Breakpoint Register Bit 11 */ + byte BIT12 :1; /* Data (Second Address) Breakpoint Register Bit 12 */ + byte BIT13 :1; /* Data (Second Address) Breakpoint Register Bit 13 */ + byte BIT14 :1; /* Data (Second Address) Breakpoint Register Bit 14 */ + byte BIT15 :1; /* Data (Second Address) Breakpoint Register Bit 15 */ + } Bits; +} BKP1HSTR; +extern volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002EUL); +#define BKP1H _BKP1H.Byte +#define BKP1H_BIT8 _BKP1H.Bits.BIT8 +#define BKP1H_BIT9 _BKP1H.Bits.BIT9 +#define BKP1H_BIT10 _BKP1H.Bits.BIT10 +#define BKP1H_BIT11 _BKP1H.Bits.BIT11 +#define BKP1H_BIT12 _BKP1H.Bits.BIT12 +#define BKP1H_BIT13 _BKP1H.Bits.BIT13 +#define BKP1H_BIT14 _BKP1H.Bits.BIT14 +#define BKP1H_BIT15 _BKP1H.Bits.BIT15 + +#define BKP1H_BIT8_MASK 1U +#define BKP1H_BIT9_MASK 2U +#define BKP1H_BIT10_MASK 4U +#define BKP1H_BIT11_MASK 8U +#define BKP1H_BIT12_MASK 16U +#define BKP1H_BIT13_MASK 32U +#define BKP1H_BIT14_MASK 64U +#define BKP1H_BIT15_MASK 128U + + +/*** BKP1L - Data (Second Address) Low Byte Breakpoint Register; 0x0000002F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Data (Second Address) Breakpoint Register Bit 0 */ + byte BIT1 :1; /* Data (Second Address) Breakpoint Register Bit 1 */ + byte BIT2 :1; /* Data (Second Address) Breakpoint Register Bit 2 */ + byte BIT3 :1; /* Data (Second Address) Breakpoint Register Bit 3 */ + byte BIT4 :1; /* Data (Second Address) Breakpoint Register Bit 4 */ + byte BIT5 :1; /* Data (Second Address) Breakpoint Register Bit 5 */ + byte BIT6 :1; /* Data (Second Address) Breakpoint Register Bit 6 */ + byte BIT7 :1; /* Data (Second Address) Breakpoint Register Bit 7 */ + } Bits; +} BKP1LSTR; +extern volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002FUL); +#define BKP1L _BKP1L.Byte +#define BKP1L_BIT0 _BKP1L.Bits.BIT0 +#define BKP1L_BIT1 _BKP1L.Bits.BIT1 +#define BKP1L_BIT2 _BKP1L.Bits.BIT2 +#define BKP1L_BIT3 _BKP1L.Bits.BIT3 +#define BKP1L_BIT4 _BKP1L.Bits.BIT4 +#define BKP1L_BIT5 _BKP1L.Bits.BIT5 +#define BKP1L_BIT6 _BKP1L.Bits.BIT6 +#define BKP1L_BIT7 _BKP1L.Bits.BIT7 + +#define BKP1L_BIT0_MASK 1U +#define BKP1L_BIT1_MASK 2U +#define BKP1L_BIT2_MASK 4U +#define BKP1L_BIT3_MASK 8U +#define BKP1L_BIT4_MASK 16U +#define BKP1L_BIT5_MASK 32U +#define BKP1L_BIT6_MASK 64U +#define BKP1L_BIT7_MASK 128U + + +/*** PPAGE - Page Index Register; 0x00000030 ***/ +typedef union { + byte Byte; + struct { + byte PIX0 :1; /* Page Index Register Bit 0 */ + byte PIX1 :1; /* Page Index Register Bit 1 */ + byte PIX2 :1; /* Page Index Register Bit 2 */ + byte PIX3 :1; /* Page Index Register Bit 3 */ + byte PIX4 :1; /* Page Index Register Bit 4 */ + byte PIX5 :1; /* Page Index Register Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpPIX :6; + byte :1; + byte :1; + } MergedBits; +} PPAGESTR; +extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030UL); +#define PPAGE _PPAGE.Byte +#define PPAGE_PIX0 _PPAGE.Bits.PIX0 +#define PPAGE_PIX1 _PPAGE.Bits.PIX1 +#define PPAGE_PIX2 _PPAGE.Bits.PIX2 +#define PPAGE_PIX3 _PPAGE.Bits.PIX3 +#define PPAGE_PIX4 _PPAGE.Bits.PIX4 +#define PPAGE_PIX5 _PPAGE.Bits.PIX5 +#define PPAGE_PIX _PPAGE.MergedBits.grpPIX + +#define PPAGE_PIX0_MASK 1U +#define PPAGE_PIX1_MASK 2U +#define PPAGE_PIX2_MASK 4U +#define PPAGE_PIX3_MASK 8U +#define PPAGE_PIX4_MASK 16U +#define PPAGE_PIX5_MASK 32U +#define PPAGE_PIX_MASK 63U +#define PPAGE_PIX_BITNUM 0U + + +/*** PORTK - Port K Data Register; 0x00000032 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port K Bit 0 */ + byte BIT1 :1; /* Port K Bit 1 */ + byte BIT2 :1; /* Port K Bit 2 */ + byte BIT3 :1; /* Port K Bit 3 */ + byte BIT4 :1; /* Port K Bit 4 */ + byte BIT5 :1; /* Port K Bit 5 */ + byte :1; + byte BIT7 :1; /* Port K Bit 7 */ + } Bits; + struct { + byte grpBIT :6; + byte :1; + byte grpBIT_7 :1; + } MergedBits; +} PORTKSTR; +extern volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032UL); +#define PORTK _PORTK.Byte +#define PORTK_BIT0 _PORTK.Bits.BIT0 +#define PORTK_BIT1 _PORTK.Bits.BIT1 +#define PORTK_BIT2 _PORTK.Bits.BIT2 +#define PORTK_BIT3 _PORTK.Bits.BIT3 +#define PORTK_BIT4 _PORTK.Bits.BIT4 +#define PORTK_BIT5 _PORTK.Bits.BIT5 +#define PORTK_BIT7 _PORTK.Bits.BIT7 +#define PORTK_BIT _PORTK.MergedBits.grpBIT + +#define PORTK_BIT0_MASK 1U +#define PORTK_BIT1_MASK 2U +#define PORTK_BIT2_MASK 4U +#define PORTK_BIT3_MASK 8U +#define PORTK_BIT4_MASK 16U +#define PORTK_BIT5_MASK 32U +#define PORTK_BIT7_MASK 128U +#define PORTK_BIT_MASK 63U +#define PORTK_BIT_BITNUM 0U + + +/*** DDRK - Port K Data Direction Register; 0x00000033 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* Port K Data Direction Bit 0 */ + byte BIT1 :1; /* Port K Data Direction Bit 1 */ + byte BIT2 :1; /* Port K Data Direction Bit 2 */ + byte BIT3 :1; /* Port K Data Direction Bit 3 */ + byte BIT4 :1; /* Port K Data Direction Bit 4 */ + byte BIT5 :1; /* Port K Data Direction Bit 5 */ + byte :1; + byte BIT7 :1; /* Port K Data Direction Bit 7 */ + } Bits; + struct { + byte grpBIT :6; + byte :1; + byte grpBIT_7 :1; + } MergedBits; +} DDRKSTR; +extern volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033UL); +#define DDRK _DDRK.Byte +#define DDRK_BIT0 _DDRK.Bits.BIT0 +#define DDRK_BIT1 _DDRK.Bits.BIT1 +#define DDRK_BIT2 _DDRK.Bits.BIT2 +#define DDRK_BIT3 _DDRK.Bits.BIT3 +#define DDRK_BIT4 _DDRK.Bits.BIT4 +#define DDRK_BIT5 _DDRK.Bits.BIT5 +#define DDRK_BIT7 _DDRK.Bits.BIT7 +#define DDRK_BIT _DDRK.MergedBits.grpBIT + +#define DDRK_BIT0_MASK 1U +#define DDRK_BIT1_MASK 2U +#define DDRK_BIT2_MASK 4U +#define DDRK_BIT3_MASK 8U +#define DDRK_BIT4_MASK 16U +#define DDRK_BIT5_MASK 32U +#define DDRK_BIT7_MASK 128U +#define DDRK_BIT_MASK 63U +#define DDRK_BIT_BITNUM 0U + + +/*** SYNR - CRG Synthesizer Register; 0x00000034 ***/ +typedef union { + byte Byte; + struct { + byte SYN0 :1; /* CRG Synthesizer Bit 0 */ + byte SYN1 :1; /* CRG Synthesizer Bit 1 */ + byte SYN2 :1; /* CRG Synthesizer Bit 2 */ + byte SYN3 :1; /* CRG Synthesizer Bit 3 */ + byte SYN4 :1; /* CRG Synthesizer Bit 4 */ + byte SYN5 :1; /* CRG Synthesizer Bit 5 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpSYN :6; + byte :1; + byte :1; + } MergedBits; +} SYNRSTR; +extern volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034UL); +#define SYNR _SYNR.Byte +#define SYNR_SYN0 _SYNR.Bits.SYN0 +#define SYNR_SYN1 _SYNR.Bits.SYN1 +#define SYNR_SYN2 _SYNR.Bits.SYN2 +#define SYNR_SYN3 _SYNR.Bits.SYN3 +#define SYNR_SYN4 _SYNR.Bits.SYN4 +#define SYNR_SYN5 _SYNR.Bits.SYN5 +#define SYNR_SYN _SYNR.MergedBits.grpSYN + +#define SYNR_SYN0_MASK 1U +#define SYNR_SYN1_MASK 2U +#define SYNR_SYN2_MASK 4U +#define SYNR_SYN3_MASK 8U +#define SYNR_SYN4_MASK 16U +#define SYNR_SYN5_MASK 32U +#define SYNR_SYN_MASK 63U +#define SYNR_SYN_BITNUM 0U + + +/*** REFDV - CRG Reference Divider Register; 0x00000035 ***/ +typedef union { + byte Byte; + struct { + byte REFDV0 :1; /* CRG Reference Divider Bit 0 */ + byte REFDV1 :1; /* CRG Reference Divider Bit 1 */ + byte REFDV2 :1; /* CRG Reference Divider Bit 2 */ + byte REFDV3 :1; /* CRG Reference Divider Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpREFDV :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} REFDVSTR; +extern volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035UL); +#define REFDV _REFDV.Byte +#define REFDV_REFDV0 _REFDV.Bits.REFDV0 +#define REFDV_REFDV1 _REFDV.Bits.REFDV1 +#define REFDV_REFDV2 _REFDV.Bits.REFDV2 +#define REFDV_REFDV3 _REFDV.Bits.REFDV3 +#define REFDV_REFDV _REFDV.MergedBits.grpREFDV + +#define REFDV_REFDV0_MASK 1U +#define REFDV_REFDV1_MASK 2U +#define REFDV_REFDV2_MASK 4U +#define REFDV_REFDV3_MASK 8U +#define REFDV_REFDV_MASK 15U +#define REFDV_REFDV_BITNUM 0U + + +/*** CRGFLG - CRG Flags Register; 0x00000037 ***/ +typedef union { + byte Byte; + struct { + byte SCM :1; /* Self-clock mode Status */ + byte SCMIF :1; /* Self-clock mode Interrupt Flag */ + byte TRACK :1; /* Track Status */ + byte LOCK :1; /* Lock Status */ + byte LOCKIF :1; /* PLL Lock Interrupt Flag */ + byte :1; + byte PORF :1; /* Power on Reset Flag */ + byte RTIF :1; /* Real Time Interrupt Flag */ + } Bits; +} CRGFLGSTR; +extern volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037UL); +#define CRGFLG _CRGFLG.Byte +#define CRGFLG_SCM _CRGFLG.Bits.SCM +#define CRGFLG_SCMIF _CRGFLG.Bits.SCMIF +#define CRGFLG_TRACK _CRGFLG.Bits.TRACK +#define CRGFLG_LOCK _CRGFLG.Bits.LOCK +#define CRGFLG_LOCKIF _CRGFLG.Bits.LOCKIF +#define CRGFLG_PORF _CRGFLG.Bits.PORF +#define CRGFLG_RTIF _CRGFLG.Bits.RTIF + +#define CRGFLG_SCM_MASK 1U +#define CRGFLG_SCMIF_MASK 2U +#define CRGFLG_TRACK_MASK 4U +#define CRGFLG_LOCK_MASK 8U +#define CRGFLG_LOCKIF_MASK 16U +#define CRGFLG_PORF_MASK 64U +#define CRGFLG_RTIF_MASK 128U + + +/*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte SCMIE :1; /* Self-clock mode Interrupt Enable */ + byte :1; + byte :1; + byte LOCKIE :1; /* Lock Interrupt Enable */ + byte :1; + byte :1; + byte RTIE :1; /* Real Time Interrupt Enable */ + } Bits; +} CRGINTSTR; +extern volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038UL); +#define CRGINT _CRGINT.Byte +#define CRGINT_SCMIE _CRGINT.Bits.SCMIE +#define CRGINT_LOCKIE _CRGINT.Bits.LOCKIE +#define CRGINT_RTIE _CRGINT.Bits.RTIE + +#define CRGINT_SCMIE_MASK 2U +#define CRGINT_LOCKIE_MASK 16U +#define CRGINT_RTIE_MASK 128U + + +/*** CLKSEL - CRG Clock Select Register; 0x00000039 ***/ +typedef union { + byte Byte; + struct { + byte COPWAI :1; /* COP stops in WAIT mode */ + byte RTIWAI :1; /* RTI stops in WAIT mode */ + byte CWAI :1; /* CLK24 and CLK23 stop in WAIT mode */ + byte PLLWAI :1; /* PLL stops in WAIT mode */ + byte ROAWAI :1; /* Reduced Oscillator Amplitude in WAIT mode */ + byte SYSWAI :1; /* System clocks stop in WAIT mode */ + byte PSTP :1; /* Pseudo Stop */ + byte PLLSEL :1; /* PLL selected for system clock */ + } Bits; +} CLKSELSTR; +extern volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039UL); +#define CLKSEL _CLKSEL.Byte +#define CLKSEL_COPWAI _CLKSEL.Bits.COPWAI +#define CLKSEL_RTIWAI _CLKSEL.Bits.RTIWAI +#define CLKSEL_CWAI _CLKSEL.Bits.CWAI +#define CLKSEL_PLLWAI _CLKSEL.Bits.PLLWAI +#define CLKSEL_ROAWAI _CLKSEL.Bits.ROAWAI +#define CLKSEL_SYSWAI _CLKSEL.Bits.SYSWAI +#define CLKSEL_PSTP _CLKSEL.Bits.PSTP +#define CLKSEL_PLLSEL _CLKSEL.Bits.PLLSEL + +#define CLKSEL_COPWAI_MASK 1U +#define CLKSEL_RTIWAI_MASK 2U +#define CLKSEL_CWAI_MASK 4U +#define CLKSEL_PLLWAI_MASK 8U +#define CLKSEL_ROAWAI_MASK 16U +#define CLKSEL_SYSWAI_MASK 32U +#define CLKSEL_PSTP_MASK 64U +#define CLKSEL_PLLSEL_MASK 128U + + +/*** PLLCTL - CRG PLL Control Register; 0x0000003A ***/ +typedef union { + byte Byte; + struct { + byte SCME :1; /* Self-clock mode enable */ + byte PCE :1; /* COP Enable during Pseudo Stop Bit */ + byte PRE :1; /* RTI Enable during Pseudo Stop Bit */ + byte :1; + byte ACQ :1; /* Acquisition */ + byte AUTO :1; /* Automatic Bandwidth Control */ + byte PLLON :1; /* Phase Lock Loop On */ + byte CME :1; /* Clock Monitor Enable */ + } Bits; +} PLLCTLSTR; +extern volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003AUL); +#define PLLCTL _PLLCTL.Byte +#define PLLCTL_SCME _PLLCTL.Bits.SCME +#define PLLCTL_PCE _PLLCTL.Bits.PCE +#define PLLCTL_PRE _PLLCTL.Bits.PRE +#define PLLCTL_ACQ _PLLCTL.Bits.ACQ +#define PLLCTL_AUTO _PLLCTL.Bits.AUTO +#define PLLCTL_PLLON _PLLCTL.Bits.PLLON +#define PLLCTL_CME _PLLCTL.Bits.CME + +#define PLLCTL_SCME_MASK 1U +#define PLLCTL_PCE_MASK 2U +#define PLLCTL_PRE_MASK 4U +#define PLLCTL_ACQ_MASK 16U +#define PLLCTL_AUTO_MASK 32U +#define PLLCTL_PLLON_MASK 64U +#define PLLCTL_CME_MASK 128U + + +/*** RTICTL - CRG RTI Control Register; 0x0000003B ***/ +typedef union { + byte Byte; + struct { + byte RTR0 :1; /* Real Time Interrupt Modulus Counter Select Bit 0 */ + byte RTR1 :1; /* Real Time Interrupt Modulus Counter Select Bit 1 */ + byte RTR2 :1; /* Real Time Interrupt Modulus Counter Select Bit 2 */ + byte RTR3 :1; /* Real Time Interrupt Modulus Counter Select Bit 3 */ + byte RTR4 :1; /* Real Time Interrupt Prescale Rate Select Bit 4 */ + byte RTR5 :1; /* Real Time Interrupt Prescale Rate Select Bit 5 */ + byte RTR6 :1; /* Real Time Interrupt Prescale Rate Select Bit 6 */ + byte :1; + } Bits; + struct { + byte grpRTR :7; + byte :1; + } MergedBits; +} RTICTLSTR; +extern volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003BUL); +#define RTICTL _RTICTL.Byte +#define RTICTL_RTR0 _RTICTL.Bits.RTR0 +#define RTICTL_RTR1 _RTICTL.Bits.RTR1 +#define RTICTL_RTR2 _RTICTL.Bits.RTR2 +#define RTICTL_RTR3 _RTICTL.Bits.RTR3 +#define RTICTL_RTR4 _RTICTL.Bits.RTR4 +#define RTICTL_RTR5 _RTICTL.Bits.RTR5 +#define RTICTL_RTR6 _RTICTL.Bits.RTR6 +#define RTICTL_RTR _RTICTL.MergedBits.grpRTR + +#define RTICTL_RTR0_MASK 1U +#define RTICTL_RTR1_MASK 2U +#define RTICTL_RTR2_MASK 4U +#define RTICTL_RTR3_MASK 8U +#define RTICTL_RTR4_MASK 16U +#define RTICTL_RTR5_MASK 32U +#define RTICTL_RTR6_MASK 64U +#define RTICTL_RTR_MASK 127U +#define RTICTL_RTR_BITNUM 0U + + +/*** COPCTL - CRG COP Control Register; 0x0000003C ***/ +typedef union { + byte Byte; + struct { + byte CR0 :1; /* COP Watchdog Timer Rate select Bit 0 */ + byte CR1 :1; /* COP Watchdog Timer Rate select Bit 1 */ + byte CR2 :1; /* COP Watchdog Timer Rate select Bit 2 */ + byte :1; + byte :1; + byte :1; + byte RSBCK :1; /* COP and RTI stop in Active BDM mode Bit */ + byte WCOP :1; /* Window COP mode */ + } Bits; + struct { + byte grpCR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} COPCTLSTR; +extern volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003CUL); +#define COPCTL _COPCTL.Byte +#define COPCTL_CR0 _COPCTL.Bits.CR0 +#define COPCTL_CR1 _COPCTL.Bits.CR1 +#define COPCTL_CR2 _COPCTL.Bits.CR2 +#define COPCTL_RSBCK _COPCTL.Bits.RSBCK +#define COPCTL_WCOP _COPCTL.Bits.WCOP +#define COPCTL_CR _COPCTL.MergedBits.grpCR + +#define COPCTL_CR0_MASK 1U +#define COPCTL_CR1_MASK 2U +#define COPCTL_CR2_MASK 4U +#define COPCTL_RSBCK_MASK 64U +#define COPCTL_WCOP_MASK 128U +#define COPCTL_CR_MASK 7U +#define COPCTL_CR_BITNUM 0U + + +/*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* CRG COP Timer Arm/Reset Bit 0 */ + byte BIT1 :1; /* CRG COP Timer Arm/Reset Bit 1 */ + byte BIT2 :1; /* CRG COP Timer Arm/Reset Bit 2 */ + byte BIT3 :1; /* CRG COP Timer Arm/Reset Bit 3 */ + byte BIT4 :1; /* CRG COP Timer Arm/Reset Bit 4 */ + byte BIT5 :1; /* CRG COP Timer Arm/Reset Bit 5 */ + byte BIT6 :1; /* CRG COP Timer Arm/Reset Bit 6 */ + byte BIT7 :1; /* CRG COP Timer Arm/Reset Bit 7 */ + } Bits; +} ARMCOPSTR; +extern volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003FUL); +#define ARMCOP _ARMCOP.Byte +#define ARMCOP_BIT0 _ARMCOP.Bits.BIT0 +#define ARMCOP_BIT1 _ARMCOP.Bits.BIT1 +#define ARMCOP_BIT2 _ARMCOP.Bits.BIT2 +#define ARMCOP_BIT3 _ARMCOP.Bits.BIT3 +#define ARMCOP_BIT4 _ARMCOP.Bits.BIT4 +#define ARMCOP_BIT5 _ARMCOP.Bits.BIT5 +#define ARMCOP_BIT6 _ARMCOP.Bits.BIT6 +#define ARMCOP_BIT7 _ARMCOP.Bits.BIT7 + +#define ARMCOP_BIT0_MASK 1U +#define ARMCOP_BIT1_MASK 2U +#define ARMCOP_BIT2_MASK 4U +#define ARMCOP_BIT3_MASK 8U +#define ARMCOP_BIT4_MASK 16U +#define ARMCOP_BIT5_MASK 32U +#define ARMCOP_BIT6_MASK 64U +#define ARMCOP_BIT7_MASK 128U + + +/*** TIOS - Timer Input Capture/Output Compare Select; 0x00000040 ***/ +typedef union { + byte Byte; + struct { + byte IOS0 :1; /* Input Capture or Output Compare Channel Configuration Bit 0 */ + byte IOS1 :1; /* Input Capture or Output Compare Channel Configuration Bit 1 */ + byte IOS2 :1; /* Input Capture or Output Compare Channel Configuration Bit 2 */ + byte IOS3 :1; /* Input Capture or Output Compare Channel Configuration Bit 3 */ + byte IOS4 :1; /* Input Capture or Output Compare Channel Configuration Bit 4 */ + byte IOS5 :1; /* Input Capture or Output Compare Channel Configuration Bit 5 */ + byte IOS6 :1; /* Input Capture or Output Compare Channel Configuration Bit 6 */ + byte IOS7 :1; /* Input Capture or Output Compare Channel Configuration Bit 7 */ + } Bits; +} TIOSSTR; +extern volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040UL); +#define TIOS _TIOS.Byte +#define TIOS_IOS0 _TIOS.Bits.IOS0 +#define TIOS_IOS1 _TIOS.Bits.IOS1 +#define TIOS_IOS2 _TIOS.Bits.IOS2 +#define TIOS_IOS3 _TIOS.Bits.IOS3 +#define TIOS_IOS4 _TIOS.Bits.IOS4 +#define TIOS_IOS5 _TIOS.Bits.IOS5 +#define TIOS_IOS6 _TIOS.Bits.IOS6 +#define TIOS_IOS7 _TIOS.Bits.IOS7 + +#define TIOS_IOS0_MASK 1U +#define TIOS_IOS1_MASK 2U +#define TIOS_IOS2_MASK 4U +#define TIOS_IOS3_MASK 8U +#define TIOS_IOS4_MASK 16U +#define TIOS_IOS5_MASK 32U +#define TIOS_IOS6_MASK 64U +#define TIOS_IOS7_MASK 128U + + +/*** CFORC - Timer Compare Force Register; 0x00000041 ***/ +typedef union { + byte Byte; + struct { + byte FOC0 :1; /* Force Output Compare Action for Channel 0 */ + byte FOC1 :1; /* Force Output Compare Action for Channel 1 */ + byte FOC2 :1; /* Force Output Compare Action for Channel 2 */ + byte FOC3 :1; /* Force Output Compare Action for Channel 3 */ + byte FOC4 :1; /* Force Output Compare Action for Channel 4 */ + byte FOC5 :1; /* Force Output Compare Action for Channel 5 */ + byte FOC6 :1; /* Force Output Compare Action for Channel 6 */ + byte FOC7 :1; /* Force Output Compare Action for Channel 7 */ + } Bits; +} CFORCSTR; +extern volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041UL); +#define CFORC _CFORC.Byte +#define CFORC_FOC0 _CFORC.Bits.FOC0 +#define CFORC_FOC1 _CFORC.Bits.FOC1 +#define CFORC_FOC2 _CFORC.Bits.FOC2 +#define CFORC_FOC3 _CFORC.Bits.FOC3 +#define CFORC_FOC4 _CFORC.Bits.FOC4 +#define CFORC_FOC5 _CFORC.Bits.FOC5 +#define CFORC_FOC6 _CFORC.Bits.FOC6 +#define CFORC_FOC7 _CFORC.Bits.FOC7 + +#define CFORC_FOC0_MASK 1U +#define CFORC_FOC1_MASK 2U +#define CFORC_FOC2_MASK 4U +#define CFORC_FOC3_MASK 8U +#define CFORC_FOC4_MASK 16U +#define CFORC_FOC5_MASK 32U +#define CFORC_FOC6_MASK 64U +#define CFORC_FOC7_MASK 128U + + +/*** OC7M - Output Compare 7 Mask Register; 0x00000042 ***/ +typedef union { + byte Byte; + struct { + byte OC7M0 :1; /* Output Compare 7 Mask Bit 0 */ + byte OC7M1 :1; /* Output Compare 7 Mask Bit 1 */ + byte OC7M2 :1; /* Output Compare 7 Mask Bit 2 */ + byte OC7M3 :1; /* Output Compare 7 Mask Bit 3 */ + byte OC7M4 :1; /* Output Compare 7 Mask Bit 4 */ + byte OC7M5 :1; /* Output Compare 7 Mask Bit 5 */ + byte OC7M6 :1; /* Output Compare 7 Mask Bit 6 */ + byte OC7M7 :1; /* Output Compare 7 Mask Bit 7 */ + } Bits; +} OC7MSTR; +extern volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042UL); +#define OC7M _OC7M.Byte +#define OC7M_OC7M0 _OC7M.Bits.OC7M0 +#define OC7M_OC7M1 _OC7M.Bits.OC7M1 +#define OC7M_OC7M2 _OC7M.Bits.OC7M2 +#define OC7M_OC7M3 _OC7M.Bits.OC7M3 +#define OC7M_OC7M4 _OC7M.Bits.OC7M4 +#define OC7M_OC7M5 _OC7M.Bits.OC7M5 +#define OC7M_OC7M6 _OC7M.Bits.OC7M6 +#define OC7M_OC7M7 _OC7M.Bits.OC7M7 + +#define OC7M_OC7M0_MASK 1U +#define OC7M_OC7M1_MASK 2U +#define OC7M_OC7M2_MASK 4U +#define OC7M_OC7M3_MASK 8U +#define OC7M_OC7M4_MASK 16U +#define OC7M_OC7M5_MASK 32U +#define OC7M_OC7M6_MASK 64U +#define OC7M_OC7M7_MASK 128U + + +/*** OC7D - Output Compare 7 Data Register; 0x00000043 ***/ +typedef union { + byte Byte; +} OC7DSTR; +extern volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043UL); +#define OC7D _OC7D.Byte + + +/*** TCNT - Timer Count Register; 0x00000044 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TCNTHi - Timer Count Register High; 0x00000044 ***/ + union { + byte Byte; + } TCNTHiSTR; + #define TCNTHi _TCNT.Overlap_STR.TCNTHiSTR.Byte + + + /*** TCNTLo - Timer Count Register Low; 0x00000045 ***/ + union { + byte Byte; + } TCNTLoSTR; + #define TCNTLo _TCNT.Overlap_STR.TCNTLoSTR.Byte + + } Overlap_STR; + +} TCNTSTR; +extern volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044UL); +#define TCNT _TCNT.Word + + +/*** TSCR1 - Timer System Control Register1; 0x00000046 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte TFFCA :1; /* Timer Fast Flag Clear All */ + byte TSFRZ :1; /* Timer and Modulus Counter Stop While in Freeze Mode */ + byte TSWAI :1; /* Timer Module Stops While in Wait */ + byte TEN :1; /* Timer Enable */ + } Bits; +} TSCR1STR; +extern volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046UL); +#define TSCR1 _TSCR1.Byte +#define TSCR1_TFFCA _TSCR1.Bits.TFFCA +#define TSCR1_TSFRZ _TSCR1.Bits.TSFRZ +#define TSCR1_TSWAI _TSCR1.Bits.TSWAI +#define TSCR1_TEN _TSCR1.Bits.TEN + +#define TSCR1_TFFCA_MASK 16U +#define TSCR1_TSFRZ_MASK 32U +#define TSCR1_TSWAI_MASK 64U +#define TSCR1_TEN_MASK 128U + + +/*** TTOV - Timer Toggle On Overflow Register; 0x00000047 ***/ +typedef union { + byte Byte; + struct { + byte TOV0 :1; /* Toggle On Overflow Bit 0 */ + byte TOV1 :1; /* Toggle On Overflow Bit 1 */ + byte TOV2 :1; /* Toggle On Overflow Bit 2 */ + byte TOV3 :1; /* Toggle On Overflow Bit 3 */ + byte TOV4 :1; /* Toggle On Overflow Bit 4 */ + byte TOV5 :1; /* Toggle On Overflow Bit 5 */ + byte TOV6 :1; /* Toggle On Overflow Bit 6 */ + byte TOV7 :1; /* Toggle On Overflow Bit 7 */ + } Bits; +} TTOVSTR; +extern volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047UL); +#define TTOV _TTOV.Byte +#define TTOV_TOV0 _TTOV.Bits.TOV0 +#define TTOV_TOV1 _TTOV.Bits.TOV1 +#define TTOV_TOV2 _TTOV.Bits.TOV2 +#define TTOV_TOV3 _TTOV.Bits.TOV3 +#define TTOV_TOV4 _TTOV.Bits.TOV4 +#define TTOV_TOV5 _TTOV.Bits.TOV5 +#define TTOV_TOV6 _TTOV.Bits.TOV6 +#define TTOV_TOV7 _TTOV.Bits.TOV7 + +#define TTOV_TOV0_MASK 1U +#define TTOV_TOV1_MASK 2U +#define TTOV_TOV2_MASK 4U +#define TTOV_TOV3_MASK 8U +#define TTOV_TOV4_MASK 16U +#define TTOV_TOV5_MASK 32U +#define TTOV_TOV6_MASK 64U +#define TTOV_TOV7_MASK 128U + + +/*** TCTL1 - Timer Control Register 1; 0x00000048 ***/ +typedef union { + byte Byte; + struct { + byte OL4 :1; /* Output Level Bit 4 */ + byte OM4 :1; /* Output Mode Bit 4 */ + byte OL5 :1; /* Output Level Bit 5 */ + byte OM5 :1; /* Output Mode Bit 5 */ + byte OL6 :1; /* Output Level Bit 6 */ + byte OM6 :1; /* Output Mode Bit 6 */ + byte OL7 :1; /* Output Level Bit 7 */ + byte OM7 :1; /* Output Mode Bit 7 */ + } Bits; +} TCTL1STR; +extern volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048UL); +#define TCTL1 _TCTL1.Byte +#define TCTL1_OL4 _TCTL1.Bits.OL4 +#define TCTL1_OM4 _TCTL1.Bits.OM4 +#define TCTL1_OL5 _TCTL1.Bits.OL5 +#define TCTL1_OM5 _TCTL1.Bits.OM5 +#define TCTL1_OL6 _TCTL1.Bits.OL6 +#define TCTL1_OM6 _TCTL1.Bits.OM6 +#define TCTL1_OL7 _TCTL1.Bits.OL7 +#define TCTL1_OM7 _TCTL1.Bits.OM7 + +#define TCTL1_OL4_MASK 1U +#define TCTL1_OM4_MASK 2U +#define TCTL1_OL5_MASK 4U +#define TCTL1_OM5_MASK 8U +#define TCTL1_OL6_MASK 16U +#define TCTL1_OM6_MASK 32U +#define TCTL1_OL7_MASK 64U +#define TCTL1_OM7_MASK 128U + + +/*** TCTL2 - Timer Control Register 2; 0x00000049 ***/ +typedef union { + byte Byte; + struct { + byte OL0 :1; /* Output Level Bit 0 */ + byte OM0 :1; /* Output Mode Bit 0 */ + byte OL1 :1; /* Output Level Bit 1 */ + byte OM1 :1; /* Output Mode Bit 1 */ + byte OL2 :1; /* Output Level Bit 2 */ + byte OM2 :1; /* Output Mode Bit 2 */ + byte OL3 :1; /* Output Level Bit 3 */ + byte OM3 :1; /* Output Mode Bit 3 */ + } Bits; +} TCTL2STR; +extern volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049UL); +#define TCTL2 _TCTL2.Byte +#define TCTL2_OL0 _TCTL2.Bits.OL0 +#define TCTL2_OM0 _TCTL2.Bits.OM0 +#define TCTL2_OL1 _TCTL2.Bits.OL1 +#define TCTL2_OM1 _TCTL2.Bits.OM1 +#define TCTL2_OL2 _TCTL2.Bits.OL2 +#define TCTL2_OM2 _TCTL2.Bits.OM2 +#define TCTL2_OL3 _TCTL2.Bits.OL3 +#define TCTL2_OM3 _TCTL2.Bits.OM3 + +#define TCTL2_OL0_MASK 1U +#define TCTL2_OM0_MASK 2U +#define TCTL2_OL1_MASK 4U +#define TCTL2_OM1_MASK 8U +#define TCTL2_OL2_MASK 16U +#define TCTL2_OM2_MASK 32U +#define TCTL2_OL3_MASK 64U +#define TCTL2_OM3_MASK 128U + + +/*** TCTL3 - Timer Control Register 3; 0x0000004A ***/ +typedef union { + byte Byte; + struct { + byte EDG4A :1; /* Input Capture Edge Control 4A */ + byte EDG4B :1; /* Input Capture Edge Control 4B */ + byte EDG5A :1; /* Input Capture Edge Control 5A */ + byte EDG5B :1; /* Input Capture Edge Control 5B */ + byte EDG6A :1; /* Input Capture Edge Control 6A */ + byte EDG6B :1; /* Input Capture Edge Control 6B */ + byte EDG7A :1; /* Input Capture Edge Control 7A */ + byte EDG7B :1; /* Input Capture Edge Control 7B */ + } Bits; + struct { + byte grpEDG4x :2; + byte grpEDG5x :2; + byte grpEDG6x :2; + byte grpEDG7x :2; + } MergedBits; +} TCTL3STR; +extern volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004AUL); +#define TCTL3 _TCTL3.Byte +#define TCTL3_EDG4A _TCTL3.Bits.EDG4A +#define TCTL3_EDG4B _TCTL3.Bits.EDG4B +#define TCTL3_EDG5A _TCTL3.Bits.EDG5A +#define TCTL3_EDG5B _TCTL3.Bits.EDG5B +#define TCTL3_EDG6A _TCTL3.Bits.EDG6A +#define TCTL3_EDG6B _TCTL3.Bits.EDG6B +#define TCTL3_EDG7A _TCTL3.Bits.EDG7A +#define TCTL3_EDG7B _TCTL3.Bits.EDG7B +#define TCTL3_EDG4x _TCTL3.MergedBits.grpEDG4x +#define TCTL3_EDG5x _TCTL3.MergedBits.grpEDG5x +#define TCTL3_EDG6x _TCTL3.MergedBits.grpEDG6x +#define TCTL3_EDG7x _TCTL3.MergedBits.grpEDG7x + +#define TCTL3_EDG4A_MASK 1U +#define TCTL3_EDG4B_MASK 2U +#define TCTL3_EDG5A_MASK 4U +#define TCTL3_EDG5B_MASK 8U +#define TCTL3_EDG6A_MASK 16U +#define TCTL3_EDG6B_MASK 32U +#define TCTL3_EDG7A_MASK 64U +#define TCTL3_EDG7B_MASK 128U +#define TCTL3_EDG4x_MASK 3U +#define TCTL3_EDG4x_BITNUM 0U +#define TCTL3_EDG5x_MASK 12U +#define TCTL3_EDG5x_BITNUM 2U +#define TCTL3_EDG6x_MASK 48U +#define TCTL3_EDG6x_BITNUM 4U +#define TCTL3_EDG7x_MASK 192U +#define TCTL3_EDG7x_BITNUM 6U + + +/*** TCTL4 - Timer Control Register 4; 0x0000004B ***/ +typedef union { + byte Byte; + struct { + byte EDG0A :1; /* Input Capture Edge Control 0A */ + byte EDG0B :1; /* Input Capture Edge Control 0B */ + byte EDG1A :1; /* Input Capture Edge Control 1A */ + byte EDG1B :1; /* Input Capture Edge Control 1B */ + byte EDG2A :1; /* Input Capture Edge Control 2A */ + byte EDG2B :1; /* Input Capture Edge Control 2B */ + byte EDG3A :1; /* Input Capture Edge Control 3A */ + byte EDG3B :1; /* Input Capture Edge Control 3B */ + } Bits; + struct { + byte grpEDG0x :2; + byte grpEDG1x :2; + byte grpEDG2x :2; + byte grpEDG3x :2; + } MergedBits; +} TCTL4STR; +extern volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004BUL); +#define TCTL4 _TCTL4.Byte +#define TCTL4_EDG0A _TCTL4.Bits.EDG0A +#define TCTL4_EDG0B _TCTL4.Bits.EDG0B +#define TCTL4_EDG1A _TCTL4.Bits.EDG1A +#define TCTL4_EDG1B _TCTL4.Bits.EDG1B +#define TCTL4_EDG2A _TCTL4.Bits.EDG2A +#define TCTL4_EDG2B _TCTL4.Bits.EDG2B +#define TCTL4_EDG3A _TCTL4.Bits.EDG3A +#define TCTL4_EDG3B _TCTL4.Bits.EDG3B +#define TCTL4_EDG0x _TCTL4.MergedBits.grpEDG0x +#define TCTL4_EDG1x _TCTL4.MergedBits.grpEDG1x +#define TCTL4_EDG2x _TCTL4.MergedBits.grpEDG2x +#define TCTL4_EDG3x _TCTL4.MergedBits.grpEDG3x + +#define TCTL4_EDG0A_MASK 1U +#define TCTL4_EDG0B_MASK 2U +#define TCTL4_EDG1A_MASK 4U +#define TCTL4_EDG1B_MASK 8U +#define TCTL4_EDG2A_MASK 16U +#define TCTL4_EDG2B_MASK 32U +#define TCTL4_EDG3A_MASK 64U +#define TCTL4_EDG3B_MASK 128U +#define TCTL4_EDG0x_MASK 3U +#define TCTL4_EDG0x_BITNUM 0U +#define TCTL4_EDG1x_MASK 12U +#define TCTL4_EDG1x_BITNUM 2U +#define TCTL4_EDG2x_MASK 48U +#define TCTL4_EDG2x_BITNUM 4U +#define TCTL4_EDG3x_MASK 192U +#define TCTL4_EDG3x_BITNUM 6U + + +/*** TIE - Timer Interrupt Enable Register; 0x0000004C ***/ +typedef union { + byte Byte; + struct { + byte C0I :1; /* Input Capture/Output Compare Interrupt Enable Bit 0 */ + byte C1I :1; /* Input Capture/Output Compare Interrupt Enable Bit 1 */ + byte C2I :1; /* Input Capture/Output Compare Interrupt Enable Bit 2 */ + byte C3I :1; /* Input Capture/Output Compare Interrupt Enable Bit 3 */ + byte C4I :1; /* Input Capture/Output Compare Interrupt Enable Bit 4 */ + byte C5I :1; /* Input Capture/Output Compare Interrupt Enable Bit 5 */ + byte C6I :1; /* Input Capture/Output Compare Interrupt Enable Bit 6 */ + byte C7I :1; /* Input Capture/Output Compare Interrupt Enable Bit 7 */ + } Bits; +} TIESTR; +extern volatile TIESTR _TIE @(REG_BASE + 0x0000004CUL); +#define TIE _TIE.Byte +#define TIE_C0I _TIE.Bits.C0I +#define TIE_C1I _TIE.Bits.C1I +#define TIE_C2I _TIE.Bits.C2I +#define TIE_C3I _TIE.Bits.C3I +#define TIE_C4I _TIE.Bits.C4I +#define TIE_C5I _TIE.Bits.C5I +#define TIE_C6I _TIE.Bits.C6I +#define TIE_C7I _TIE.Bits.C7I + +#define TIE_C0I_MASK 1U +#define TIE_C1I_MASK 2U +#define TIE_C2I_MASK 4U +#define TIE_C3I_MASK 8U +#define TIE_C4I_MASK 16U +#define TIE_C5I_MASK 32U +#define TIE_C6I_MASK 64U +#define TIE_C7I_MASK 128U + + +/*** TSCR2 - Timer System Control Register 2; 0x0000004D ***/ +typedef union { + byte Byte; + struct { + byte PR0 :1; /* Timer Prescaler Select Bit 0 */ + byte PR1 :1; /* Timer Prescaler Select Bit 1 */ + byte PR2 :1; /* Timer Prescaler Select Bit 2 */ + byte TCRE :1; /* Timer Counter Reset Enable */ + byte :1; + byte :1; + byte :1; + byte TOI :1; /* Timer Overflow Interrupt Enable */ + } Bits; + struct { + byte grpPR :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} TSCR2STR; +extern volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004DUL); +#define TSCR2 _TSCR2.Byte +#define TSCR2_PR0 _TSCR2.Bits.PR0 +#define TSCR2_PR1 _TSCR2.Bits.PR1 +#define TSCR2_PR2 _TSCR2.Bits.PR2 +#define TSCR2_TCRE _TSCR2.Bits.TCRE +#define TSCR2_TOI _TSCR2.Bits.TOI +#define TSCR2_PR _TSCR2.MergedBits.grpPR + +#define TSCR2_PR0_MASK 1U +#define TSCR2_PR1_MASK 2U +#define TSCR2_PR2_MASK 4U +#define TSCR2_TCRE_MASK 8U +#define TSCR2_TOI_MASK 128U +#define TSCR2_PR_MASK 7U +#define TSCR2_PR_BITNUM 0U + + +/*** TFLG1 - Main Timer Interrupt Flag 1; 0x0000004E ***/ +typedef union { + byte Byte; + struct { + byte C0F :1; /* Input Capture/Output Compare Channel Flag 0 */ + byte C1F :1; /* Input Capture/Output Compare Channel Flag 1 */ + byte C2F :1; /* Input Capture/Output Compare Channel Flag 2 */ + byte C3F :1; /* Input Capture/Output Compare Channel Flag 3 */ + byte C4F :1; /* Input Capture/Output Compare Channel Flag 4 */ + byte C5F :1; /* Input Capture/Output Compare Channel Flag 5 */ + byte C6F :1; /* Input Capture/Output Compare Channel Flag 6 */ + byte C7F :1; /* Input Capture/Output Compare Channel Flag 7 */ + } Bits; +} TFLG1STR; +extern volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004EUL); +#define TFLG1 _TFLG1.Byte +#define TFLG1_C0F _TFLG1.Bits.C0F +#define TFLG1_C1F _TFLG1.Bits.C1F +#define TFLG1_C2F _TFLG1.Bits.C2F +#define TFLG1_C3F _TFLG1.Bits.C3F +#define TFLG1_C4F _TFLG1.Bits.C4F +#define TFLG1_C5F _TFLG1.Bits.C5F +#define TFLG1_C6F _TFLG1.Bits.C6F +#define TFLG1_C7F _TFLG1.Bits.C7F + +#define TFLG1_C0F_MASK 1U +#define TFLG1_C1F_MASK 2U +#define TFLG1_C2F_MASK 4U +#define TFLG1_C3F_MASK 8U +#define TFLG1_C4F_MASK 16U +#define TFLG1_C5F_MASK 32U +#define TFLG1_C6F_MASK 64U +#define TFLG1_C7F_MASK 128U + + +/*** TFLG2 - Main Timer Interrupt Flag 2; 0x0000004F ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte TOF :1; /* Timer Overflow Flag */ + } Bits; +} TFLG2STR; +extern volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004FUL); +#define TFLG2 _TFLG2.Byte +#define TFLG2_TOF _TFLG2.Bits.TOF + +#define TFLG2_TOF_MASK 128U + + +/*** TC0 - Timer Input Capture/Output Compare Register 0; 0x00000050 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC0Hi - Timer Input Capture/Output Compare Register 0 High; 0x00000050 ***/ + union { + byte Byte; + } TC0HiSTR; + #define TC0Hi _TC0.Overlap_STR.TC0HiSTR.Byte + + + /*** TC0Lo - Timer Input Capture/Output Compare Register 0 Low; 0x00000051 ***/ + union { + byte Byte; + } TC0LoSTR; + #define TC0Lo _TC0.Overlap_STR.TC0LoSTR.Byte + + } Overlap_STR; + +} TC0STR; +extern volatile TC0STR _TC0 @(REG_BASE + 0x00000050UL); +#define TC0 _TC0.Word +/* TC_ARR: Access 8 TCx registers in an array */ +#define TC_ARR ((volatile word *) &TC0) + + +/*** TC1 - Timer Input Capture/Output Compare Register 1; 0x00000052 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC1Hi - Timer Input Capture/Output Compare Register 1 High; 0x00000052 ***/ + union { + byte Byte; + } TC1HiSTR; + #define TC1Hi _TC1.Overlap_STR.TC1HiSTR.Byte + + + /*** TC1Lo - Timer Input Capture/Output Compare Register 1 Low; 0x00000053 ***/ + union { + byte Byte; + } TC1LoSTR; + #define TC1Lo _TC1.Overlap_STR.TC1LoSTR.Byte + + } Overlap_STR; + +} TC1STR; +extern volatile TC1STR _TC1 @(REG_BASE + 0x00000052UL); +#define TC1 _TC1.Word + + +/*** TC2 - Timer Input Capture/Output Compare Register 2; 0x00000054 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC2Hi - Timer Input Capture/Output Compare Register 2 High; 0x00000054 ***/ + union { + byte Byte; + } TC2HiSTR; + #define TC2Hi _TC2.Overlap_STR.TC2HiSTR.Byte + + + /*** TC2Lo - Timer Input Capture/Output Compare Register 2 Low; 0x00000055 ***/ + union { + byte Byte; + } TC2LoSTR; + #define TC2Lo _TC2.Overlap_STR.TC2LoSTR.Byte + + } Overlap_STR; + +} TC2STR; +extern volatile TC2STR _TC2 @(REG_BASE + 0x00000054UL); +#define TC2 _TC2.Word + + +/*** TC3 - Timer Input Capture/Output Compare Register 3; 0x00000056 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC3Hi - Timer Input Capture/Output Compare Register 3 High; 0x00000056 ***/ + union { + byte Byte; + } TC3HiSTR; + #define TC3Hi _TC3.Overlap_STR.TC3HiSTR.Byte + + + /*** TC3Lo - Timer Input Capture/Output Compare Register 3 Low; 0x00000057 ***/ + union { + byte Byte; + } TC3LoSTR; + #define TC3Lo _TC3.Overlap_STR.TC3LoSTR.Byte + + } Overlap_STR; + +} TC3STR; +extern volatile TC3STR _TC3 @(REG_BASE + 0x00000056UL); +#define TC3 _TC3.Word + + +/*** TC4 - Timer Input Capture/Output Compare Register 4; 0x00000058 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC4Hi - Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***/ + union { + byte Byte; + } TC4HiSTR; + #define TC4Hi _TC4.Overlap_STR.TC4HiSTR.Byte + + + /*** TC4Lo - Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***/ + union { + byte Byte; + } TC4LoSTR; + #define TC4Lo _TC4.Overlap_STR.TC4LoSTR.Byte + + } Overlap_STR; + +} TC4STR; +extern volatile TC4STR _TC4 @(REG_BASE + 0x00000058UL); +#define TC4 _TC4.Word + + +/*** TC5 - Timer Input Capture/Output Compare Register 5; 0x0000005A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC5Hi - Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***/ + union { + byte Byte; + } TC5HiSTR; + #define TC5Hi _TC5.Overlap_STR.TC5HiSTR.Byte + + + /*** TC5Lo - Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***/ + union { + byte Byte; + } TC5LoSTR; + #define TC5Lo _TC5.Overlap_STR.TC5LoSTR.Byte + + } Overlap_STR; + +} TC5STR; +extern volatile TC5STR _TC5 @(REG_BASE + 0x0000005AUL); +#define TC5 _TC5.Word + + +/*** TC6 - Timer Input Capture/Output Compare Register 6; 0x0000005C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC6Hi - Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***/ + union { + byte Byte; + } TC6HiSTR; + #define TC6Hi _TC6.Overlap_STR.TC6HiSTR.Byte + + + /*** TC6Lo - Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***/ + union { + byte Byte; + } TC6LoSTR; + #define TC6Lo _TC6.Overlap_STR.TC6LoSTR.Byte + + } Overlap_STR; + +} TC6STR; +extern volatile TC6STR _TC6 @(REG_BASE + 0x0000005CUL); +#define TC6 _TC6.Word + + +/*** TC7 - Timer Input Capture/Output Compare Register 7; 0x0000005E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC7Hi - Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***/ + union { + byte Byte; + } TC7HiSTR; + #define TC7Hi _TC7.Overlap_STR.TC7HiSTR.Byte + + + /*** TC7Lo - Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***/ + union { + byte Byte; + } TC7LoSTR; + #define TC7Lo _TC7.Overlap_STR.TC7LoSTR.Byte + + } Overlap_STR; + +} TC7STR; +extern volatile TC7STR _TC7 @(REG_BASE + 0x0000005EUL); +#define TC7 _TC7.Word + + +/*** PACTL - 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***/ +typedef union { + byte Byte; + struct { + byte PAI :1; /* Pulse Accumulator Input Interrupt enable */ + byte PAOVI :1; /* Pulse Accumulator A Overflow Interrupt enable */ + byte CLK0 :1; /* Clock Select Bit 0 */ + byte CLK1 :1; /* Clock Select Bit 1 */ + byte PEDGE :1; /* Pulse Accumulator Edge Control */ + byte PAMOD :1; /* Pulse Accumulator Mode */ + byte PAEN :1; /* Pulse Accumulator A System Enable */ + byte :1; + } Bits; + struct { + byte :1; + byte :1; + byte grpCLK :2; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} PACTLSTR; +extern volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060UL); +#define PACTL _PACTL.Byte +#define PACTL_PAI _PACTL.Bits.PAI +#define PACTL_PAOVI _PACTL.Bits.PAOVI +#define PACTL_CLK0 _PACTL.Bits.CLK0 +#define PACTL_CLK1 _PACTL.Bits.CLK1 +#define PACTL_PEDGE _PACTL.Bits.PEDGE +#define PACTL_PAMOD _PACTL.Bits.PAMOD +#define PACTL_PAEN _PACTL.Bits.PAEN +#define PACTL_CLK _PACTL.MergedBits.grpCLK + +#define PACTL_PAI_MASK 1U +#define PACTL_PAOVI_MASK 2U +#define PACTL_CLK0_MASK 4U +#define PACTL_CLK1_MASK 8U +#define PACTL_PEDGE_MASK 16U +#define PACTL_PAMOD_MASK 32U +#define PACTL_PAEN_MASK 64U +#define PACTL_CLK_MASK 12U +#define PACTL_CLK_BITNUM 2U + + +/*** PAFLG - Pulse Accumulator A Flag Register; 0x00000061 ***/ +typedef union { + byte Byte; + struct { + byte PAIF :1; /* Pulse Accumulator Input edge Flag */ + byte PAOVF :1; /* Pulse Accumulator A Overflow Flag */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PAFLGSTR; +extern volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061UL); +#define PAFLG _PAFLG.Byte +#define PAFLG_PAIF _PAFLG.Bits.PAIF +#define PAFLG_PAOVF _PAFLG.Bits.PAOVF + +#define PAFLG_PAIF_MASK 1U +#define PAFLG_PAOVF_MASK 2U + + +/*** PACN32 - Pulse Accumulators Count 32 Register; 0x00000062 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PACN3 - Pulse Accumulators Count 3 Register; 0x00000062 ***/ + union { + byte Byte; + } PACN3STR; + #define PACN3 _PACN32.Overlap_STR.PACN3STR.Byte + + + /*** PACN2 - Pulse Accumulators Count 2 Register; 0x00000063 ***/ + union { + byte Byte; + } PACN2STR; + #define PACN2 _PACN32.Overlap_STR.PACN2STR.Byte + + } Overlap_STR; + +} PACN32STR; +extern volatile PACN32STR _PACN32 @(REG_BASE + 0x00000062UL); +#define PACN32 _PACN32.Word + + +/*** PACN10 - Pulse Accumulators Count 10 Register; 0x00000064 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PACN1 - Pulse Accumulators Count 1 Register; 0x00000064 ***/ + union { + byte Byte; + } PACN1STR; + #define PACN1 _PACN10.Overlap_STR.PACN1STR.Byte + + + /*** PACN0 - Pulse Accumulators Count 0 Register; 0x00000065 ***/ + union { + byte Byte; + } PACN0STR; + #define PACN0 _PACN10.Overlap_STR.PACN0STR.Byte + + } Overlap_STR; + +} PACN10STR; +extern volatile PACN10STR _PACN10 @(REG_BASE + 0x00000064UL); +#define PACN10 _PACN10.Word + + +/*** MCCTL - Modulus Down Counter underflow; 0x00000066 ***/ +typedef union { + byte Byte; + struct { + byte MCPR0 :1; /* Modulus Counter Prescaler select 0 */ + byte MCPR1 :1; /* Modulus Counter Prescaler select 1 */ + byte MCEN :1; /* Modulus Down-Counter Enable */ + byte FLMC :1; /* Force Load Register into the Modulus Counter Count Register */ + byte ICLAT :1; /* Input Capture Force Latch Action */ + byte RDMCL :1; /* Read Modulus Down-Counter Load */ + byte MODMC :1; /* Modulus Mode Enable */ + byte MCZI :1; /* Modulus Counter Underflow Interrupt Enable */ + } Bits; + struct { + byte grpMCPR :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MCCTLSTR; +extern volatile MCCTLSTR _MCCTL @(REG_BASE + 0x00000066UL); +#define MCCTL _MCCTL.Byte +#define MCCTL_MCPR0 _MCCTL.Bits.MCPR0 +#define MCCTL_MCPR1 _MCCTL.Bits.MCPR1 +#define MCCTL_MCEN _MCCTL.Bits.MCEN +#define MCCTL_FLMC _MCCTL.Bits.FLMC +#define MCCTL_ICLAT _MCCTL.Bits.ICLAT +#define MCCTL_RDMCL _MCCTL.Bits.RDMCL +#define MCCTL_MODMC _MCCTL.Bits.MODMC +#define MCCTL_MCZI _MCCTL.Bits.MCZI +#define MCCTL_MCPR _MCCTL.MergedBits.grpMCPR + +#define MCCTL_MCPR0_MASK 1U +#define MCCTL_MCPR1_MASK 2U +#define MCCTL_MCEN_MASK 4U +#define MCCTL_FLMC_MASK 8U +#define MCCTL_ICLAT_MASK 16U +#define MCCTL_RDMCL_MASK 32U +#define MCCTL_MODMC_MASK 64U +#define MCCTL_MCZI_MASK 128U +#define MCCTL_MCPR_MASK 3U +#define MCCTL_MCPR_BITNUM 0U + + +/*** MCFLG - 16-Bit Modulus Down Counter Flag Register; 0x00000067 ***/ +typedef union { + byte Byte; + struct { + byte POLF0 :1; /* First Input Capture Polarity Status 0 */ + byte POLF1 :1; /* First Input Capture Polarity Status 1 */ + byte POLF2 :1; /* First Input Capture Polarity Status 2 */ + byte POLF3 :1; /* First Input Capture Polarity Status 3 */ + byte :1; + byte :1; + byte :1; + byte MCZF :1; /* Modulus Counter Underflow Flag */ + } Bits; + struct { + byte grpPOLF :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} MCFLGSTR; +extern volatile MCFLGSTR _MCFLG @(REG_BASE + 0x00000067UL); +#define MCFLG _MCFLG.Byte +#define MCFLG_POLF0 _MCFLG.Bits.POLF0 +#define MCFLG_POLF1 _MCFLG.Bits.POLF1 +#define MCFLG_POLF2 _MCFLG.Bits.POLF2 +#define MCFLG_POLF3 _MCFLG.Bits.POLF3 +#define MCFLG_MCZF _MCFLG.Bits.MCZF +#define MCFLG_POLF _MCFLG.MergedBits.grpPOLF + +#define MCFLG_POLF0_MASK 1U +#define MCFLG_POLF1_MASK 2U +#define MCFLG_POLF2_MASK 4U +#define MCFLG_POLF3_MASK 8U +#define MCFLG_MCZF_MASK 128U +#define MCFLG_POLF_MASK 15U +#define MCFLG_POLF_BITNUM 0U + + +/*** ICPAR - Input Control Pulse Accumulator Register; 0x00000068 ***/ +typedef union { + byte Byte; + struct { + byte PA0EN :1; /* 8-Bit Pulse Accumulator 0 Enable */ + byte PA1EN :1; /* 8-Bit Pulse Accumulator 1 Enable */ + byte PA2EN :1; /* 8-Bit Pulse Accumulator 2 Enable */ + byte PA3EN :1; /* 8-Bit Pulse Accumulator 3 Enable */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} ICPARSTR; +extern volatile ICPARSTR _ICPAR @(REG_BASE + 0x00000068UL); +#define ICPAR _ICPAR.Byte +#define ICPAR_PA0EN _ICPAR.Bits.PA0EN +#define ICPAR_PA1EN _ICPAR.Bits.PA1EN +#define ICPAR_PA2EN _ICPAR.Bits.PA2EN +#define ICPAR_PA3EN _ICPAR.Bits.PA3EN + +#define ICPAR_PA0EN_MASK 1U +#define ICPAR_PA1EN_MASK 2U +#define ICPAR_PA2EN_MASK 4U +#define ICPAR_PA3EN_MASK 8U + + +/*** DLYCT - Delay Counter Control Register; 0x00000069 ***/ +typedef union { + byte Byte; + struct { + byte DLY0 :1; /* Delay Counter Select 0 */ + byte DLY1 :1; /* Delay Counter Select 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLY :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} DLYCTSTR; +extern volatile DLYCTSTR _DLYCT @(REG_BASE + 0x00000069UL); +#define DLYCT _DLYCT.Byte +#define DLYCT_DLY0 _DLYCT.Bits.DLY0 +#define DLYCT_DLY1 _DLYCT.Bits.DLY1 +#define DLYCT_DLY _DLYCT.MergedBits.grpDLY + +#define DLYCT_DLY0_MASK 1U +#define DLYCT_DLY1_MASK 2U +#define DLYCT_DLY_MASK 3U +#define DLYCT_DLY_BITNUM 0U + + +/*** ICOVW - Input Control Overwrite Register; 0x0000006A ***/ +typedef union { + byte Byte; + struct { + byte NOVW0 :1; /* No Input Capture Overwrite 0 */ + byte NOVW1 :1; /* No Input Capture Overwrite 1 */ + byte NOVW2 :1; /* No Input Capture Overwrite 2 */ + byte NOVW3 :1; /* No Input Capture Overwrite 3 */ + byte NOVW4 :1; /* No Input Capture Overwrite 4 */ + byte NOVW5 :1; /* No Input Capture Overwrite 5 */ + byte NOVW6 :1; /* No Input Capture Overwrite 6 */ + byte NOVW7 :1; /* No Input Capture Overwrite 7 */ + } Bits; +} ICOVWSTR; +extern volatile ICOVWSTR _ICOVW @(REG_BASE + 0x0000006AUL); +#define ICOVW _ICOVW.Byte +#define ICOVW_NOVW0 _ICOVW.Bits.NOVW0 +#define ICOVW_NOVW1 _ICOVW.Bits.NOVW1 +#define ICOVW_NOVW2 _ICOVW.Bits.NOVW2 +#define ICOVW_NOVW3 _ICOVW.Bits.NOVW3 +#define ICOVW_NOVW4 _ICOVW.Bits.NOVW4 +#define ICOVW_NOVW5 _ICOVW.Bits.NOVW5 +#define ICOVW_NOVW6 _ICOVW.Bits.NOVW6 +#define ICOVW_NOVW7 _ICOVW.Bits.NOVW7 + +#define ICOVW_NOVW0_MASK 1U +#define ICOVW_NOVW1_MASK 2U +#define ICOVW_NOVW2_MASK 4U +#define ICOVW_NOVW3_MASK 8U +#define ICOVW_NOVW4_MASK 16U +#define ICOVW_NOVW5_MASK 32U +#define ICOVW_NOVW6_MASK 64U +#define ICOVW_NOVW7_MASK 128U + + +/*** ICSYS - Input Control System Control Register; 0x0000006B ***/ +typedef union { + byte Byte; + struct { + byte LATQ :1; /* Input Control Latch or Queue Mode Enable */ + byte BUFEN :1; /* IC Buffer Enable */ + byte PACMX :1; /* 8-Bit Pulse Accumulators Maximum Count */ + byte TFMOD :1; /* Timer Flag-setting Mode */ + byte SH04 :1; /* Share Input action of Input Capture Channels 0 and 4 */ + byte SH15 :1; /* Share Input action of Input Capture Channels 1 and 5 */ + byte SH26 :1; /* Share Input action of Input Capture Channels 2 and 6 */ + byte SH37 :1; /* Share Input action of Input Capture Channels 3 and 7 */ + } Bits; +} ICSYSSTR; +extern volatile ICSYSSTR _ICSYS @(REG_BASE + 0x0000006BUL); +#define ICSYS _ICSYS.Byte +#define ICSYS_LATQ _ICSYS.Bits.LATQ +#define ICSYS_BUFEN _ICSYS.Bits.BUFEN +#define ICSYS_PACMX _ICSYS.Bits.PACMX +#define ICSYS_TFMOD _ICSYS.Bits.TFMOD +#define ICSYS_SH04 _ICSYS.Bits.SH04 +#define ICSYS_SH15 _ICSYS.Bits.SH15 +#define ICSYS_SH26 _ICSYS.Bits.SH26 +#define ICSYS_SH37 _ICSYS.Bits.SH37 + +#define ICSYS_LATQ_MASK 1U +#define ICSYS_BUFEN_MASK 2U +#define ICSYS_PACMX_MASK 4U +#define ICSYS_TFMOD_MASK 8U +#define ICSYS_SH04_MASK 16U +#define ICSYS_SH15_MASK 32U +#define ICSYS_SH26_MASK 64U +#define ICSYS_SH37_MASK 128U + + +/*** PBCTL - 16-Bit Pulse Accumulator B Control Register; 0x00000070 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PBOVI :1; /* Pulse Accumulator B Overflow Interrupt enable */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PBEN :1; /* Pulse Accumulator B System Enable */ + byte :1; + } Bits; +} PBCTLSTR; +extern volatile PBCTLSTR _PBCTL @(REG_BASE + 0x00000070UL); +#define PBCTL _PBCTL.Byte +#define PBCTL_PBOVI _PBCTL.Bits.PBOVI +#define PBCTL_PBEN _PBCTL.Bits.PBEN + +#define PBCTL_PBOVI_MASK 2U +#define PBCTL_PBEN_MASK 64U + + +/*** PBFLG - Pulse Accumulator B Flag Register; 0x00000071 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte PBOVF :1; /* Pulse Accumulator B Overflow Flag */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} PBFLGSTR; +extern volatile PBFLGSTR _PBFLG @(REG_BASE + 0x00000071UL); +#define PBFLG _PBFLG.Byte +#define PBFLG_PBOVF _PBFLG.Bits.PBOVF + +#define PBFLG_PBOVF_MASK 2U + + +/*** PA32H - 8-Bit Pulse Accumulators Holding 32 Register; 0x00000072 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PA3H - 8-Bit Pulse Accumulators Holding 3 Register; 0x00000072 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + } PA3HSTR; + #define PA3H _PA32H.Overlap_STR.PA3HSTR.Byte + #define PA3H_BIT0 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT0 + #define PA3H_BIT1 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT1 + #define PA3H_BIT2 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT2 + #define PA3H_BIT3 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT3 + #define PA3H_BIT4 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT4 + #define PA3H_BIT5 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT5 + #define PA3H_BIT6 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT6 + #define PA3H_BIT7 _PA32H.Overlap_STR.PA3HSTR.Bits.BIT7 + + #define PA3H_BIT0_MASK 1U + #define PA3H_BIT1_MASK 2U + #define PA3H_BIT2_MASK 4U + #define PA3H_BIT3_MASK 8U + #define PA3H_BIT4_MASK 16U + #define PA3H_BIT5_MASK 32U + #define PA3H_BIT6_MASK 64U + #define PA3H_BIT7_MASK 128U + + + /*** PA2H - 8-Bit Pulse Accumulators Holding 2 Register; 0x00000073 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + } PA2HSTR; + #define PA2H _PA32H.Overlap_STR.PA2HSTR.Byte + #define PA2H_BIT0 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT0 + #define PA2H_BIT1 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT1 + #define PA2H_BIT2 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT2 + #define PA2H_BIT3 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT3 + #define PA2H_BIT4 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT4 + #define PA2H_BIT5 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT5 + #define PA2H_BIT6 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT6 + #define PA2H_BIT7 _PA32H.Overlap_STR.PA2HSTR.Bits.BIT7 + + #define PA2H_BIT0_MASK 1U + #define PA2H_BIT1_MASK 2U + #define PA2H_BIT2_MASK 4U + #define PA2H_BIT3_MASK 8U + #define PA2H_BIT4_MASK 16U + #define PA2H_BIT5_MASK 32U + #define PA2H_BIT6_MASK 64U + #define PA2H_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Pulse Accumulator Bit 0 */ + word BIT1 :1; /* Pulse Accumulator Bit 1 */ + word BIT2 :1; /* Pulse Accumulator Bit 2 */ + word BIT3 :1; /* Pulse Accumulator Bit 3 */ + word BIT4 :1; /* Pulse Accumulator Bit 4 */ + word BIT5 :1; /* Pulse Accumulator Bit 5 */ + word BIT6 :1; /* Pulse Accumulator Bit 6 */ + word BIT7 :1; /* Pulse Accumulator Bit 7 */ + word BIT8 :1; /* Pulse Accumulator Bit 8 */ + word BIT9 :1; /* Pulse Accumulator Bit 9 */ + word BIT10 :1; /* Pulse Accumulator Bit 10 */ + word BIT11 :1; /* Pulse Accumulator Bit 11 */ + word BIT12 :1; /* Pulse Accumulator Bit 12 */ + word BIT13 :1; /* Pulse Accumulator Bit 13 */ + word BIT14 :1; /* Pulse Accumulator Bit 14 */ + word BIT15 :1; /* Pulse Accumulator Bit 15 */ + } Bits; +} PA32HSTR; +extern volatile PA32HSTR _PA32H @(REG_BASE + 0x00000072UL); +#define PA32H _PA32H.Word +#define PA32H_BIT0 _PA32H.Bits.BIT0 +#define PA32H_BIT1 _PA32H.Bits.BIT1 +#define PA32H_BIT2 _PA32H.Bits.BIT2 +#define PA32H_BIT3 _PA32H.Bits.BIT3 +#define PA32H_BIT4 _PA32H.Bits.BIT4 +#define PA32H_BIT5 _PA32H.Bits.BIT5 +#define PA32H_BIT6 _PA32H.Bits.BIT6 +#define PA32H_BIT7 _PA32H.Bits.BIT7 +#define PA32H_BIT8 _PA32H.Bits.BIT8 +#define PA32H_BIT9 _PA32H.Bits.BIT9 +#define PA32H_BIT10 _PA32H.Bits.BIT10 +#define PA32H_BIT11 _PA32H.Bits.BIT11 +#define PA32H_BIT12 _PA32H.Bits.BIT12 +#define PA32H_BIT13 _PA32H.Bits.BIT13 +#define PA32H_BIT14 _PA32H.Bits.BIT14 +#define PA32H_BIT15 _PA32H.Bits.BIT15 + +#define PA32H_BIT0_MASK 1U +#define PA32H_BIT1_MASK 2U +#define PA32H_BIT2_MASK 4U +#define PA32H_BIT3_MASK 8U +#define PA32H_BIT4_MASK 16U +#define PA32H_BIT5_MASK 32U +#define PA32H_BIT6_MASK 64U +#define PA32H_BIT7_MASK 128U +#define PA32H_BIT8_MASK 256U +#define PA32H_BIT9_MASK 512U +#define PA32H_BIT10_MASK 1024U +#define PA32H_BIT11_MASK 2048U +#define PA32H_BIT12_MASK 4096U +#define PA32H_BIT13_MASK 8192U +#define PA32H_BIT14_MASK 16384U +#define PA32H_BIT15_MASK 32768U + + +/*** PA10H - 8-Bit Pulse Accumulators Holding 10 Register; 0x00000074 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PA1H - 8-Bit Pulse Accumulators Holding 1 Register; 0x00000074 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + } PA1HSTR; + #define PA1H _PA10H.Overlap_STR.PA1HSTR.Byte + #define PA1H_BIT0 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT0 + #define PA1H_BIT1 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT1 + #define PA1H_BIT2 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT2 + #define PA1H_BIT3 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT3 + #define PA1H_BIT4 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT4 + #define PA1H_BIT5 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT5 + #define PA1H_BIT6 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT6 + #define PA1H_BIT7 _PA10H.Overlap_STR.PA1HSTR.Bits.BIT7 + + #define PA1H_BIT0_MASK 1U + #define PA1H_BIT1_MASK 2U + #define PA1H_BIT2_MASK 4U + #define PA1H_BIT3_MASK 8U + #define PA1H_BIT4_MASK 16U + #define PA1H_BIT5_MASK 32U + #define PA1H_BIT6_MASK 64U + #define PA1H_BIT7_MASK 128U + + + /*** PA0H - 8-Bit Pulse Accumulators Holding 0 Register; 0x00000075 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Pulse Accumulator Bit 0 */ + byte BIT1 :1; /* Pulse Accumulator Bit 1 */ + byte BIT2 :1; /* Pulse Accumulator Bit 2 */ + byte BIT3 :1; /* Pulse Accumulator Bit 3 */ + byte BIT4 :1; /* Pulse Accumulator Bit 4 */ + byte BIT5 :1; /* Pulse Accumulator Bit 5 */ + byte BIT6 :1; /* Pulse Accumulator Bit 6 */ + byte BIT7 :1; /* Pulse Accumulator Bit 7 */ + } Bits; + } PA0HSTR; + #define PA0H _PA10H.Overlap_STR.PA0HSTR.Byte + #define PA0H_BIT0 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT0 + #define PA0H_BIT1 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT1 + #define PA0H_BIT2 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT2 + #define PA0H_BIT3 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT3 + #define PA0H_BIT4 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT4 + #define PA0H_BIT5 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT5 + #define PA0H_BIT6 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT6 + #define PA0H_BIT7 _PA10H.Overlap_STR.PA0HSTR.Bits.BIT7 + + #define PA0H_BIT0_MASK 1U + #define PA0H_BIT1_MASK 2U + #define PA0H_BIT2_MASK 4U + #define PA0H_BIT3_MASK 8U + #define PA0H_BIT4_MASK 16U + #define PA0H_BIT5_MASK 32U + #define PA0H_BIT6_MASK 64U + #define PA0H_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Pulse Accumulator Bit 0 */ + word BIT1 :1; /* Pulse Accumulator Bit 1 */ + word BIT2 :1; /* Pulse Accumulator Bit 2 */ + word BIT3 :1; /* Pulse Accumulator Bit 3 */ + word BIT4 :1; /* Pulse Accumulator Bit 4 */ + word BIT5 :1; /* Pulse Accumulator Bit 5 */ + word BIT6 :1; /* Pulse Accumulator Bit 6 */ + word BIT7 :1; /* Pulse Accumulator Bit 7 */ + word BIT8 :1; /* Pulse Accumulator Bit 8 */ + word BIT9 :1; /* Pulse Accumulator Bit 9 */ + word BIT10 :1; /* Pulse Accumulator Bit 10 */ + word BIT11 :1; /* Pulse Accumulator Bit 11 */ + word BIT12 :1; /* Pulse Accumulator Bit 12 */ + word BIT13 :1; /* Pulse Accumulator Bit 13 */ + word BIT14 :1; /* Pulse Accumulator Bit 14 */ + word BIT15 :1; /* Pulse Accumulator Bit 15 */ + } Bits; +} PA10HSTR; +extern volatile PA10HSTR _PA10H @(REG_BASE + 0x00000074UL); +#define PA10H _PA10H.Word +#define PA10H_BIT0 _PA10H.Bits.BIT0 +#define PA10H_BIT1 _PA10H.Bits.BIT1 +#define PA10H_BIT2 _PA10H.Bits.BIT2 +#define PA10H_BIT3 _PA10H.Bits.BIT3 +#define PA10H_BIT4 _PA10H.Bits.BIT4 +#define PA10H_BIT5 _PA10H.Bits.BIT5 +#define PA10H_BIT6 _PA10H.Bits.BIT6 +#define PA10H_BIT7 _PA10H.Bits.BIT7 +#define PA10H_BIT8 _PA10H.Bits.BIT8 +#define PA10H_BIT9 _PA10H.Bits.BIT9 +#define PA10H_BIT10 _PA10H.Bits.BIT10 +#define PA10H_BIT11 _PA10H.Bits.BIT11 +#define PA10H_BIT12 _PA10H.Bits.BIT12 +#define PA10H_BIT13 _PA10H.Bits.BIT13 +#define PA10H_BIT14 _PA10H.Bits.BIT14 +#define PA10H_BIT15 _PA10H.Bits.BIT15 + +#define PA10H_BIT0_MASK 1U +#define PA10H_BIT1_MASK 2U +#define PA10H_BIT2_MASK 4U +#define PA10H_BIT3_MASK 8U +#define PA10H_BIT4_MASK 16U +#define PA10H_BIT5_MASK 32U +#define PA10H_BIT6_MASK 64U +#define PA10H_BIT7_MASK 128U +#define PA10H_BIT8_MASK 256U +#define PA10H_BIT9_MASK 512U +#define PA10H_BIT10_MASK 1024U +#define PA10H_BIT11_MASK 2048U +#define PA10H_BIT12_MASK 4096U +#define PA10H_BIT13_MASK 8192U +#define PA10H_BIT14_MASK 16384U +#define PA10H_BIT15_MASK 32768U + + +/*** MCCNT - Modulus Down-Counter Count Register; 0x00000076 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** MCCNThi - Modulus Down-Counter Count Register High; 0x00000076 ***/ + union { + byte Byte; + } MCCNThiSTR; + #define MCCNThi _MCCNT.Overlap_STR.MCCNThiSTR.Byte + + + /*** MCCNTlo - Modulus Down-Counter Count Register Low; 0x00000077 ***/ + union { + byte Byte; + } MCCNTloSTR; + #define MCCNTlo _MCCNT.Overlap_STR.MCCNTloSTR.Byte + + } Overlap_STR; + +} MCCNTSTR; +extern volatile MCCNTSTR _MCCNT @(REG_BASE + 0x00000076UL); +#define MCCNT _MCCNT.Word + + +/*** TC0H - Timer Input Capture Holding Registers 0; 0x00000078 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC0Hhi - Timer Input Capture Holding Registers 0 High; 0x00000078 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + } TC0HhiSTR; + #define TC0Hhi _TC0H.Overlap_STR.TC0HhiSTR.Byte + #define TC0Hhi_BIT8 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT8 + #define TC0Hhi_BIT9 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT9 + #define TC0Hhi_BIT10 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT10 + #define TC0Hhi_BIT11 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT11 + #define TC0Hhi_BIT12 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT12 + #define TC0Hhi_BIT13 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT13 + #define TC0Hhi_BIT14 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT14 + #define TC0Hhi_BIT15 _TC0H.Overlap_STR.TC0HhiSTR.Bits.BIT15 + + #define TC0Hhi_BIT8_MASK 1U + #define TC0Hhi_BIT9_MASK 2U + #define TC0Hhi_BIT10_MASK 4U + #define TC0Hhi_BIT11_MASK 8U + #define TC0Hhi_BIT12_MASK 16U + #define TC0Hhi_BIT13_MASK 32U + #define TC0Hhi_BIT14_MASK 64U + #define TC0Hhi_BIT15_MASK 128U + + + /*** TC0Hlo - Timer Input Capture Holding Registers 0 Low; 0x00000079 ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + } TC0HloSTR; + #define TC0Hlo _TC0H.Overlap_STR.TC0HloSTR.Byte + #define TC0Hlo_BIT0 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT0 + #define TC0Hlo_BIT1 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT1 + #define TC0Hlo_BIT2 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT2 + #define TC0Hlo_BIT3 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT3 + #define TC0Hlo_BIT4 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT4 + #define TC0Hlo_BIT5 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT5 + #define TC0Hlo_BIT6 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT6 + #define TC0Hlo_BIT7 _TC0H.Overlap_STR.TC0HloSTR.Bits.BIT7 + + #define TC0Hlo_BIT0_MASK 1U + #define TC0Hlo_BIT1_MASK 2U + #define TC0Hlo_BIT2_MASK 4U + #define TC0Hlo_BIT3_MASK 8U + #define TC0Hlo_BIT4_MASK 16U + #define TC0Hlo_BIT5_MASK 32U + #define TC0Hlo_BIT6_MASK 64U + #define TC0Hlo_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; +} TC0HSTR; +extern volatile TC0HSTR _TC0H @(REG_BASE + 0x00000078UL); +#define TC0H _TC0H.Word +#define TC0H_BIT0 _TC0H.Bits.BIT0 +#define TC0H_BIT1 _TC0H.Bits.BIT1 +#define TC0H_BIT2 _TC0H.Bits.BIT2 +#define TC0H_BIT3 _TC0H.Bits.BIT3 +#define TC0H_BIT4 _TC0H.Bits.BIT4 +#define TC0H_BIT5 _TC0H.Bits.BIT5 +#define TC0H_BIT6 _TC0H.Bits.BIT6 +#define TC0H_BIT7 _TC0H.Bits.BIT7 +#define TC0H_BIT8 _TC0H.Bits.BIT8 +#define TC0H_BIT9 _TC0H.Bits.BIT9 +#define TC0H_BIT10 _TC0H.Bits.BIT10 +#define TC0H_BIT11 _TC0H.Bits.BIT11 +#define TC0H_BIT12 _TC0H.Bits.BIT12 +#define TC0H_BIT13 _TC0H.Bits.BIT13 +#define TC0H_BIT14 _TC0H.Bits.BIT14 +#define TC0H_BIT15 _TC0H.Bits.BIT15 + +#define TC0H_BIT0_MASK 1U +#define TC0H_BIT1_MASK 2U +#define TC0H_BIT2_MASK 4U +#define TC0H_BIT3_MASK 8U +#define TC0H_BIT4_MASK 16U +#define TC0H_BIT5_MASK 32U +#define TC0H_BIT6_MASK 64U +#define TC0H_BIT7_MASK 128U +#define TC0H_BIT8_MASK 256U +#define TC0H_BIT9_MASK 512U +#define TC0H_BIT10_MASK 1024U +#define TC0H_BIT11_MASK 2048U +#define TC0H_BIT12_MASK 4096U +#define TC0H_BIT13_MASK 8192U +#define TC0H_BIT14_MASK 16384U +#define TC0H_BIT15_MASK 32768U + + +/*** TC1H - Timer Input Capture Holding Registers 1; 0x0000007A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC1Hhi - Timer Input Capture Holding Registers 1 High; 0x0000007A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + } TC1HhiSTR; + #define TC1Hhi _TC1H.Overlap_STR.TC1HhiSTR.Byte + #define TC1Hhi_BIT8 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT8 + #define TC1Hhi_BIT9 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT9 + #define TC1Hhi_BIT10 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT10 + #define TC1Hhi_BIT11 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT11 + #define TC1Hhi_BIT12 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT12 + #define TC1Hhi_BIT13 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT13 + #define TC1Hhi_BIT14 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT14 + #define TC1Hhi_BIT15 _TC1H.Overlap_STR.TC1HhiSTR.Bits.BIT15 + + #define TC1Hhi_BIT8_MASK 1U + #define TC1Hhi_BIT9_MASK 2U + #define TC1Hhi_BIT10_MASK 4U + #define TC1Hhi_BIT11_MASK 8U + #define TC1Hhi_BIT12_MASK 16U + #define TC1Hhi_BIT13_MASK 32U + #define TC1Hhi_BIT14_MASK 64U + #define TC1Hhi_BIT15_MASK 128U + + + /*** TC1Hlo - Timer Input Capture Holding Registers 1 Low; 0x0000007B ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + } TC1HloSTR; + #define TC1Hlo _TC1H.Overlap_STR.TC1HloSTR.Byte + #define TC1Hlo_BIT0 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT0 + #define TC1Hlo_BIT1 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT1 + #define TC1Hlo_BIT2 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT2 + #define TC1Hlo_BIT3 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT3 + #define TC1Hlo_BIT4 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT4 + #define TC1Hlo_BIT5 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT5 + #define TC1Hlo_BIT6 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT6 + #define TC1Hlo_BIT7 _TC1H.Overlap_STR.TC1HloSTR.Bits.BIT7 + + #define TC1Hlo_BIT0_MASK 1U + #define TC1Hlo_BIT1_MASK 2U + #define TC1Hlo_BIT2_MASK 4U + #define TC1Hlo_BIT3_MASK 8U + #define TC1Hlo_BIT4_MASK 16U + #define TC1Hlo_BIT5_MASK 32U + #define TC1Hlo_BIT6_MASK 64U + #define TC1Hlo_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; +} TC1HSTR; +extern volatile TC1HSTR _TC1H @(REG_BASE + 0x0000007AUL); +#define TC1H _TC1H.Word +#define TC1H_BIT0 _TC1H.Bits.BIT0 +#define TC1H_BIT1 _TC1H.Bits.BIT1 +#define TC1H_BIT2 _TC1H.Bits.BIT2 +#define TC1H_BIT3 _TC1H.Bits.BIT3 +#define TC1H_BIT4 _TC1H.Bits.BIT4 +#define TC1H_BIT5 _TC1H.Bits.BIT5 +#define TC1H_BIT6 _TC1H.Bits.BIT6 +#define TC1H_BIT7 _TC1H.Bits.BIT7 +#define TC1H_BIT8 _TC1H.Bits.BIT8 +#define TC1H_BIT9 _TC1H.Bits.BIT9 +#define TC1H_BIT10 _TC1H.Bits.BIT10 +#define TC1H_BIT11 _TC1H.Bits.BIT11 +#define TC1H_BIT12 _TC1H.Bits.BIT12 +#define TC1H_BIT13 _TC1H.Bits.BIT13 +#define TC1H_BIT14 _TC1H.Bits.BIT14 +#define TC1H_BIT15 _TC1H.Bits.BIT15 + +#define TC1H_BIT0_MASK 1U +#define TC1H_BIT1_MASK 2U +#define TC1H_BIT2_MASK 4U +#define TC1H_BIT3_MASK 8U +#define TC1H_BIT4_MASK 16U +#define TC1H_BIT5_MASK 32U +#define TC1H_BIT6_MASK 64U +#define TC1H_BIT7_MASK 128U +#define TC1H_BIT8_MASK 256U +#define TC1H_BIT9_MASK 512U +#define TC1H_BIT10_MASK 1024U +#define TC1H_BIT11_MASK 2048U +#define TC1H_BIT12_MASK 4096U +#define TC1H_BIT13_MASK 8192U +#define TC1H_BIT14_MASK 16384U +#define TC1H_BIT15_MASK 32768U + + +/*** TC2H - Timer Input Capture Holding Registers 2; 0x0000007C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC2Hhi - Timer Input Capture Holding Registers 2 High; 0x0000007C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + } TC2HhiSTR; + #define TC2Hhi _TC2H.Overlap_STR.TC2HhiSTR.Byte + #define TC2Hhi_BIT8 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT8 + #define TC2Hhi_BIT9 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT9 + #define TC2Hhi_BIT10 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT10 + #define TC2Hhi_BIT11 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT11 + #define TC2Hhi_BIT12 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT12 + #define TC2Hhi_BIT13 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT13 + #define TC2Hhi_BIT14 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT14 + #define TC2Hhi_BIT15 _TC2H.Overlap_STR.TC2HhiSTR.Bits.BIT15 + + #define TC2Hhi_BIT8_MASK 1U + #define TC2Hhi_BIT9_MASK 2U + #define TC2Hhi_BIT10_MASK 4U + #define TC2Hhi_BIT11_MASK 8U + #define TC2Hhi_BIT12_MASK 16U + #define TC2Hhi_BIT13_MASK 32U + #define TC2Hhi_BIT14_MASK 64U + #define TC2Hhi_BIT15_MASK 128U + + + /*** TC2Hlo - Timer Input Capture Holding Registers 2 Low; 0x0000007D ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + } TC2HloSTR; + #define TC2Hlo _TC2H.Overlap_STR.TC2HloSTR.Byte + #define TC2Hlo_BIT0 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT0 + #define TC2Hlo_BIT1 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT1 + #define TC2Hlo_BIT2 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT2 + #define TC2Hlo_BIT3 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT3 + #define TC2Hlo_BIT4 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT4 + #define TC2Hlo_BIT5 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT5 + #define TC2Hlo_BIT6 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT6 + #define TC2Hlo_BIT7 _TC2H.Overlap_STR.TC2HloSTR.Bits.BIT7 + + #define TC2Hlo_BIT0_MASK 1U + #define TC2Hlo_BIT1_MASK 2U + #define TC2Hlo_BIT2_MASK 4U + #define TC2Hlo_BIT3_MASK 8U + #define TC2Hlo_BIT4_MASK 16U + #define TC2Hlo_BIT5_MASK 32U + #define TC2Hlo_BIT6_MASK 64U + #define TC2Hlo_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; +} TC2HSTR; +extern volatile TC2HSTR _TC2H @(REG_BASE + 0x0000007CUL); +#define TC2H _TC2H.Word +#define TC2H_BIT0 _TC2H.Bits.BIT0 +#define TC2H_BIT1 _TC2H.Bits.BIT1 +#define TC2H_BIT2 _TC2H.Bits.BIT2 +#define TC2H_BIT3 _TC2H.Bits.BIT3 +#define TC2H_BIT4 _TC2H.Bits.BIT4 +#define TC2H_BIT5 _TC2H.Bits.BIT5 +#define TC2H_BIT6 _TC2H.Bits.BIT6 +#define TC2H_BIT7 _TC2H.Bits.BIT7 +#define TC2H_BIT8 _TC2H.Bits.BIT8 +#define TC2H_BIT9 _TC2H.Bits.BIT9 +#define TC2H_BIT10 _TC2H.Bits.BIT10 +#define TC2H_BIT11 _TC2H.Bits.BIT11 +#define TC2H_BIT12 _TC2H.Bits.BIT12 +#define TC2H_BIT13 _TC2H.Bits.BIT13 +#define TC2H_BIT14 _TC2H.Bits.BIT14 +#define TC2H_BIT15 _TC2H.Bits.BIT15 + +#define TC2H_BIT0_MASK 1U +#define TC2H_BIT1_MASK 2U +#define TC2H_BIT2_MASK 4U +#define TC2H_BIT3_MASK 8U +#define TC2H_BIT4_MASK 16U +#define TC2H_BIT5_MASK 32U +#define TC2H_BIT6_MASK 64U +#define TC2H_BIT7_MASK 128U +#define TC2H_BIT8_MASK 256U +#define TC2H_BIT9_MASK 512U +#define TC2H_BIT10_MASK 1024U +#define TC2H_BIT11_MASK 2048U +#define TC2H_BIT12_MASK 4096U +#define TC2H_BIT13_MASK 8192U +#define TC2H_BIT14_MASK 16384U +#define TC2H_BIT15_MASK 32768U + + +/*** TC3H - Timer Input Capture Holding Registers 3; 0x0000007E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** TC3Hhi - Timer Input Capture Holding Registers 3 High; 0x0000007E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + byte BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + byte BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + byte BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + byte BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + byte BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + byte BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + byte BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; + } TC3HhiSTR; + #define TC3Hhi _TC3H.Overlap_STR.TC3HhiSTR.Byte + #define TC3Hhi_BIT8 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT8 + #define TC3Hhi_BIT9 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT9 + #define TC3Hhi_BIT10 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT10 + #define TC3Hhi_BIT11 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT11 + #define TC3Hhi_BIT12 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT12 + #define TC3Hhi_BIT13 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT13 + #define TC3Hhi_BIT14 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT14 + #define TC3Hhi_BIT15 _TC3H.Overlap_STR.TC3HhiSTR.Bits.BIT15 + + #define TC3Hhi_BIT8_MASK 1U + #define TC3Hhi_BIT9_MASK 2U + #define TC3Hhi_BIT10_MASK 4U + #define TC3Hhi_BIT11_MASK 8U + #define TC3Hhi_BIT12_MASK 16U + #define TC3Hhi_BIT13_MASK 32U + #define TC3Hhi_BIT14_MASK 64U + #define TC3Hhi_BIT15_MASK 128U + + + /*** TC3Hlo - Timer Input Capture Holding Registers 3 Low; 0x0000007F ***/ + union { + byte Byte; + struct { + byte BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + byte BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + byte BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + byte BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + byte BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + byte BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + byte BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + byte BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + } Bits; + } TC3HloSTR; + #define TC3Hlo _TC3H.Overlap_STR.TC3HloSTR.Byte + #define TC3Hlo_BIT0 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT0 + #define TC3Hlo_BIT1 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT1 + #define TC3Hlo_BIT2 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT2 + #define TC3Hlo_BIT3 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT3 + #define TC3Hlo_BIT4 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT4 + #define TC3Hlo_BIT5 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT5 + #define TC3Hlo_BIT6 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT6 + #define TC3Hlo_BIT7 _TC3H.Overlap_STR.TC3HloSTR.Bits.BIT7 + + #define TC3Hlo_BIT0_MASK 1U + #define TC3Hlo_BIT1_MASK 2U + #define TC3Hlo_BIT2_MASK 4U + #define TC3Hlo_BIT3_MASK 8U + #define TC3Hlo_BIT4_MASK 16U + #define TC3Hlo_BIT5_MASK 32U + #define TC3Hlo_BIT6_MASK 64U + #define TC3Hlo_BIT7_MASK 128U + + } Overlap_STR; + + struct { + word BIT0 :1; /* Timer Input Capture Holding Bit 0 */ + word BIT1 :1; /* Timer Input Capture Holding Bit 1 */ + word BIT2 :1; /* Timer Input Capture Holding Bit 2 */ + word BIT3 :1; /* Timer Input Capture Holding Bit 3 */ + word BIT4 :1; /* Timer Input Capture Holding Bit 4 */ + word BIT5 :1; /* Timer Input Capture Holding Bit 5 */ + word BIT6 :1; /* Timer Input Capture Holding Bit 6 */ + word BIT7 :1; /* Timer Input Capture Holding Bit 7 */ + word BIT8 :1; /* Timer Input Capture Holding Bit 8 */ + word BIT9 :1; /* Timer Input Capture Holding Bit 9 */ + word BIT10 :1; /* Timer Input Capture Holding Bit 10 */ + word BIT11 :1; /* Timer Input Capture Holding Bit 11 */ + word BIT12 :1; /* Timer Input Capture Holding Bit 12 */ + word BIT13 :1; /* Timer Input Capture Holding Bit 13 */ + word BIT14 :1; /* Timer Input Capture Holding Bit 14 */ + word BIT15 :1; /* Timer Input Capture Holding Bit 15 */ + } Bits; +} TC3HSTR; +extern volatile TC3HSTR _TC3H @(REG_BASE + 0x0000007EUL); +#define TC3H _TC3H.Word +#define TC3H_BIT0 _TC3H.Bits.BIT0 +#define TC3H_BIT1 _TC3H.Bits.BIT1 +#define TC3H_BIT2 _TC3H.Bits.BIT2 +#define TC3H_BIT3 _TC3H.Bits.BIT3 +#define TC3H_BIT4 _TC3H.Bits.BIT4 +#define TC3H_BIT5 _TC3H.Bits.BIT5 +#define TC3H_BIT6 _TC3H.Bits.BIT6 +#define TC3H_BIT7 _TC3H.Bits.BIT7 +#define TC3H_BIT8 _TC3H.Bits.BIT8 +#define TC3H_BIT9 _TC3H.Bits.BIT9 +#define TC3H_BIT10 _TC3H.Bits.BIT10 +#define TC3H_BIT11 _TC3H.Bits.BIT11 +#define TC3H_BIT12 _TC3H.Bits.BIT12 +#define TC3H_BIT13 _TC3H.Bits.BIT13 +#define TC3H_BIT14 _TC3H.Bits.BIT14 +#define TC3H_BIT15 _TC3H.Bits.BIT15 + +#define TC3H_BIT0_MASK 1U +#define TC3H_BIT1_MASK 2U +#define TC3H_BIT2_MASK 4U +#define TC3H_BIT3_MASK 8U +#define TC3H_BIT4_MASK 16U +#define TC3H_BIT5_MASK 32U +#define TC3H_BIT6_MASK 64U +#define TC3H_BIT7_MASK 128U +#define TC3H_BIT8_MASK 256U +#define TC3H_BIT9_MASK 512U +#define TC3H_BIT10_MASK 1024U +#define TC3H_BIT11_MASK 2048U +#define TC3H_BIT12_MASK 4096U +#define TC3H_BIT13_MASK 8192U +#define TC3H_BIT14_MASK 16384U +#define TC3H_BIT15_MASK 32768U + + +/*** ATD0CTL23 - ATD 0 Control Register 23; 0x00000082 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0CTL2 - ATD 0 Control Register 2; 0x00000082 ***/ + union { + byte Byte; + struct { + byte ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */ + byte ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */ + byte ETRIGE :1; /* External Trigger Mode enable */ + byte ETRIGP :1; /* External Trigger Polarity */ + byte ETRIGLE :1; /* External Trigger Level/Edge control */ + byte AWAI :1; /* ATD Power Down in Wait Mode */ + byte AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ + byte ADPU :1; /* ATD Disable / Power Down */ + } Bits; + } ATD0CTL2STR; + #define ATD0CTL2 _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Byte + #define ATD0CTL2_ASCIF _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIF + #define ATD0CTL2_ASCIE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIE + #define ATD0CTL2_ETRIGE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGE + #define ATD0CTL2_ETRIGP _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGP + #define ATD0CTL2_ETRIGLE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGLE + #define ATD0CTL2_AWAI _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AWAI + #define ATD0CTL2_AFFC _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AFFC + #define ATD0CTL2_ADPU _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ADPU + + #define ATD0CTL2_ASCIF_MASK 1U + #define ATD0CTL2_ASCIE_MASK 2U + #define ATD0CTL2_ETRIGE_MASK 4U + #define ATD0CTL2_ETRIGP_MASK 8U + #define ATD0CTL2_ETRIGLE_MASK 16U + #define ATD0CTL2_AWAI_MASK 32U + #define ATD0CTL2_AFFC_MASK 64U + #define ATD0CTL2_ADPU_MASK 128U + + + /*** ATD0CTL3 - ATD 0 Control Register 3; 0x00000083 ***/ + union { + byte Byte; + struct { + byte FRZ0 :1; /* Background Debug Freeze Enable Bit 0 */ + byte FRZ1 :1; /* Background Debug Freeze Enable Bit 1 */ + byte FIFO :1; /* Result Register FIFO Mode */ + byte S1C :1; /* Conversion Sequence Length 1 */ + byte S2C :1; /* Conversion Sequence Length 2 */ + byte S4C :1; /* Conversion Sequence Length 4 */ + byte S8C :1; /* Conversion Sequence Length 8 */ + byte :1; + } Bits; + struct { + byte grpFRZ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATD0CTL3STR; + #define ATD0CTL3 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Byte + #define ATD0CTL3_FRZ0 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ0 + #define ATD0CTL3_FRZ1 _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FRZ1 + #define ATD0CTL3_FIFO _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.FIFO + #define ATD0CTL3_S1C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S1C + #define ATD0CTL3_S2C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S2C + #define ATD0CTL3_S4C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S4C + #define ATD0CTL3_S8C _ATD0CTL23.Overlap_STR.ATD0CTL3STR.Bits.S8C + #define ATD0CTL3_FRZ _ATD0CTL23.Overlap_STR.ATD0CTL3STR.MergedBits.grpFRZ + + #define ATD0CTL3_FRZ0_MASK 1U + #define ATD0CTL3_FRZ1_MASK 2U + #define ATD0CTL3_FIFO_MASK 4U + #define ATD0CTL3_S1C_MASK 8U + #define ATD0CTL3_S2C_MASK 16U + #define ATD0CTL3_S4C_MASK 32U + #define ATD0CTL3_S8C_MASK 64U + #define ATD0CTL3_FRZ_MASK 3U + #define ATD0CTL3_FRZ_BITNUM 0U + + } Overlap_STR; + + struct { + word FRZ0 :1; /* Background Debug Freeze Enable Bit 0 */ + word FRZ1 :1; /* Background Debug Freeze Enable Bit 1 */ + word FIFO :1; /* Result Register FIFO Mode */ + word S1C :1; /* Conversion Sequence Length 1 */ + word S2C :1; /* Conversion Sequence Length 2 */ + word S4C :1; /* Conversion Sequence Length 4 */ + word S8C :1; /* Conversion Sequence Length 8 */ + word :1; + word ASCIF :1; /* ATD 0 Sequence Complete Interrupt Flag */ + word ASCIE :1; /* ATD 0 Sequence Complete Interrupt Enable */ + word ETRIGE :1; /* External Trigger Mode enable */ + word ETRIGP :1; /* External Trigger Polarity */ + word ETRIGLE :1; /* External Trigger Level/Edge control */ + word AWAI :1; /* ATD Power Down in Wait Mode */ + word AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ + word ADPU :1; /* ATD Disable / Power Down */ + } Bits; + struct { + word grpFRZ :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} ATD0CTL23STR; +extern volatile ATD0CTL23STR _ATD0CTL23 @(REG_BASE + 0x00000082UL); +#define ATD0CTL23 _ATD0CTL23.Word +#define ATD0CTL23_FRZ0 _ATD0CTL23.Bits.FRZ0 +#define ATD0CTL23_FRZ1 _ATD0CTL23.Bits.FRZ1 +#define ATD0CTL23_FIFO _ATD0CTL23.Bits.FIFO +#define ATD0CTL23_S1C _ATD0CTL23.Bits.S1C +#define ATD0CTL23_S2C _ATD0CTL23.Bits.S2C +#define ATD0CTL23_S4C _ATD0CTL23.Bits.S4C +#define ATD0CTL23_S8C _ATD0CTL23.Bits.S8C +#define ATD0CTL23_ASCIF _ATD0CTL23.Bits.ASCIF +#define ATD0CTL23_ASCIE _ATD0CTL23.Bits.ASCIE +#define ATD0CTL23_ETRIGE _ATD0CTL23.Bits.ETRIGE +#define ATD0CTL23_ETRIGP _ATD0CTL23.Bits.ETRIGP +#define ATD0CTL23_ETRIGLE _ATD0CTL23.Bits.ETRIGLE +#define ATD0CTL23_AWAI _ATD0CTL23.Bits.AWAI +#define ATD0CTL23_AFFC _ATD0CTL23.Bits.AFFC +#define ATD0CTL23_ADPU _ATD0CTL23.Bits.ADPU +#define ATD0CTL23_FRZ _ATD0CTL23.MergedBits.grpFRZ + +#define ATD0CTL23_FRZ0_MASK 1U +#define ATD0CTL23_FRZ1_MASK 2U +#define ATD0CTL23_FIFO_MASK 4U +#define ATD0CTL23_S1C_MASK 8U +#define ATD0CTL23_S2C_MASK 16U +#define ATD0CTL23_S4C_MASK 32U +#define ATD0CTL23_S8C_MASK 64U +#define ATD0CTL23_ASCIF_MASK 256U +#define ATD0CTL23_ASCIE_MASK 512U +#define ATD0CTL23_ETRIGE_MASK 1024U +#define ATD0CTL23_ETRIGP_MASK 2048U +#define ATD0CTL23_ETRIGLE_MASK 4096U +#define ATD0CTL23_AWAI_MASK 8192U +#define ATD0CTL23_AFFC_MASK 16384U +#define ATD0CTL23_ADPU_MASK 32768U +#define ATD0CTL23_FRZ_MASK 3U +#define ATD0CTL23_FRZ_BITNUM 0U + + +/*** ATD0CTL45 - ATD 0 Control Register 45; 0x00000084 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0CTL4 - ATD 0 Control Register 4; 0x00000084 ***/ + union { + byte Byte; + struct { + byte PRS0 :1; /* ATD Clock Prescaler 0 */ + byte PRS1 :1; /* ATD Clock Prescaler 1 */ + byte PRS2 :1; /* ATD Clock Prescaler 2 */ + byte PRS3 :1; /* ATD Clock Prescaler 3 */ + byte PRS4 :1; /* ATD Clock Prescaler 4 */ + byte SMP0 :1; /* Sample Time Select 0 */ + byte SMP1 :1; /* Sample Time Select 1 */ + byte SRES8 :1; /* ATD Resolution Select */ + } Bits; + struct { + byte grpPRS :5; + byte grpSMP :2; + byte grpSRES_8 :1; + } MergedBits; + } ATD0CTL4STR; + #define ATD0CTL4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Byte + #define ATD0CTL4_PRS0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS0 + #define ATD0CTL4_PRS1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS1 + #define ATD0CTL4_PRS2 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS2 + #define ATD0CTL4_PRS3 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS3 + #define ATD0CTL4_PRS4 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.PRS4 + #define ATD0CTL4_SMP0 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP0 + #define ATD0CTL4_SMP1 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SMP1 + #define ATD0CTL4_SRES8 _ATD0CTL45.Overlap_STR.ATD0CTL4STR.Bits.SRES8 + #define ATD0CTL4_PRS _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpPRS + #define ATD0CTL4_SMP _ATD0CTL45.Overlap_STR.ATD0CTL4STR.MergedBits.grpSMP + + #define ATD0CTL4_PRS0_MASK 1U + #define ATD0CTL4_PRS1_MASK 2U + #define ATD0CTL4_PRS2_MASK 4U + #define ATD0CTL4_PRS3_MASK 8U + #define ATD0CTL4_PRS4_MASK 16U + #define ATD0CTL4_SMP0_MASK 32U + #define ATD0CTL4_SMP1_MASK 64U + #define ATD0CTL4_SRES8_MASK 128U + #define ATD0CTL4_PRS_MASK 31U + #define ATD0CTL4_PRS_BITNUM 0U + #define ATD0CTL4_SMP_MASK 96U + #define ATD0CTL4_SMP_BITNUM 5U + + + /*** ATD0CTL5 - ATD 0 Control Register 5; 0x00000085 ***/ + union { + byte Byte; + struct { + byte CA :1; /* Analog Input Channel Select Code A */ + byte CB :1; /* Analog Input Channel Select Code B */ + byte CC :1; /* Analog Input Channel Select Code C */ + byte :1; + byte MULT :1; /* Multi-Channel Sample Mode */ + byte SCAN :1; /* Continuous Conversion Sequence Mode */ + byte DSGN :1; /* Signed/Unsigned Result Data Mode */ + byte DJM :1; /* Result Register Data Justification Mode */ + } Bits; + struct { + byte grpCx :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATD0CTL5STR; + #define ATD0CTL5 _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Byte + #define ATD0CTL5_CA _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CA + #define ATD0CTL5_CB _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CB + #define ATD0CTL5_CC _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.CC + #define ATD0CTL5_MULT _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.MULT + #define ATD0CTL5_SCAN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.SCAN + #define ATD0CTL5_DSGN _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DSGN + #define ATD0CTL5_DJM _ATD0CTL45.Overlap_STR.ATD0CTL5STR.Bits.DJM + #define ATD0CTL5_Cx _ATD0CTL45.Overlap_STR.ATD0CTL5STR.MergedBits.grpCx + + #define ATD0CTL5_CA_MASK 1U + #define ATD0CTL5_CB_MASK 2U + #define ATD0CTL5_CC_MASK 4U + #define ATD0CTL5_MULT_MASK 16U + #define ATD0CTL5_SCAN_MASK 32U + #define ATD0CTL5_DSGN_MASK 64U + #define ATD0CTL5_DJM_MASK 128U + #define ATD0CTL5_Cx_MASK 7U + #define ATD0CTL5_Cx_BITNUM 0U + + } Overlap_STR; + + struct { + word CA :1; /* Analog Input Channel Select Code A */ + word CB :1; /* Analog Input Channel Select Code B */ + word CC :1; /* Analog Input Channel Select Code C */ + word :1; + word MULT :1; /* Multi-Channel Sample Mode */ + word SCAN :1; /* Continuous Conversion Sequence Mode */ + word DSGN :1; /* Signed/Unsigned Result Data Mode */ + word DJM :1; /* Result Register Data Justification Mode */ + word PRS0 :1; /* ATD Clock Prescaler 0 */ + word PRS1 :1; /* ATD Clock Prescaler 1 */ + word PRS2 :1; /* ATD Clock Prescaler 2 */ + word PRS3 :1; /* ATD Clock Prescaler 3 */ + word PRS4 :1; /* ATD Clock Prescaler 4 */ + word SMP0 :1; /* Sample Time Select 0 */ + word SMP1 :1; /* Sample Time Select 1 */ + word SRES8 :1; /* ATD Resolution Select */ + } Bits; + struct { + word grpCx :3; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpPRS :5; + word grpSMP :2; + word grpSRES_8 :1; + } MergedBits; +} ATD0CTL45STR; +extern volatile ATD0CTL45STR _ATD0CTL45 @(REG_BASE + 0x00000084UL); +#define ATD0CTL45 _ATD0CTL45.Word +#define ATD0CTL45_CA _ATD0CTL45.Bits.CA +#define ATD0CTL45_CB _ATD0CTL45.Bits.CB +#define ATD0CTL45_CC _ATD0CTL45.Bits.CC +#define ATD0CTL45_MULT _ATD0CTL45.Bits.MULT +#define ATD0CTL45_SCAN _ATD0CTL45.Bits.SCAN +#define ATD0CTL45_DSGN _ATD0CTL45.Bits.DSGN +#define ATD0CTL45_DJM _ATD0CTL45.Bits.DJM +#define ATD0CTL45_PRS0 _ATD0CTL45.Bits.PRS0 +#define ATD0CTL45_PRS1 _ATD0CTL45.Bits.PRS1 +#define ATD0CTL45_PRS2 _ATD0CTL45.Bits.PRS2 +#define ATD0CTL45_PRS3 _ATD0CTL45.Bits.PRS3 +#define ATD0CTL45_PRS4 _ATD0CTL45.Bits.PRS4 +#define ATD0CTL45_SMP0 _ATD0CTL45.Bits.SMP0 +#define ATD0CTL45_SMP1 _ATD0CTL45.Bits.SMP1 +#define ATD0CTL45_SRES8 _ATD0CTL45.Bits.SRES8 +#define ATD0CTL45_Cx _ATD0CTL45.MergedBits.grpCx +#define ATD0CTL45_PRS _ATD0CTL45.MergedBits.grpPRS +#define ATD0CTL45_SMP _ATD0CTL45.MergedBits.grpSMP + +#define ATD0CTL45_CA_MASK 1U +#define ATD0CTL45_CB_MASK 2U +#define ATD0CTL45_CC_MASK 4U +#define ATD0CTL45_MULT_MASK 16U +#define ATD0CTL45_SCAN_MASK 32U +#define ATD0CTL45_DSGN_MASK 64U +#define ATD0CTL45_DJM_MASK 128U +#define ATD0CTL45_PRS0_MASK 256U +#define ATD0CTL45_PRS1_MASK 512U +#define ATD0CTL45_PRS2_MASK 1024U +#define ATD0CTL45_PRS3_MASK 2048U +#define ATD0CTL45_PRS4_MASK 4096U +#define ATD0CTL45_SMP0_MASK 8192U +#define ATD0CTL45_SMP1_MASK 16384U +#define ATD0CTL45_SRES8_MASK 32768U +#define ATD0CTL45_Cx_MASK 7U +#define ATD0CTL45_Cx_BITNUM 0U +#define ATD0CTL45_PRS_MASK 7936U +#define ATD0CTL45_PRS_BITNUM 8U +#define ATD0CTL45_SMP_MASK 24576U +#define ATD0CTL45_SMP_BITNUM 13U + + +/*** ATD0STAT0 - ATD 0 Status Register 0; 0x00000086 ***/ +typedef union { + byte Byte; + struct { + byte CC0 :1; /* Conversion Counter 0 */ + byte CC1 :1; /* Conversion Counter 1 */ + byte CC2 :1; /* Conversion Counter 2 */ + byte :1; + byte FIFOR :1; /* FIFO Over Run Flag */ + byte ETORF :1; /* External Trigger Overrun Flag */ + byte :1; + byte SCF :1; /* Sequence Complete Flag */ + } Bits; + struct { + byte grpCC :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ATD0STAT0STR; +extern volatile ATD0STAT0STR _ATD0STAT0 @(REG_BASE + 0x00000086UL); +#define ATD0STAT0 _ATD0STAT0.Byte +#define ATD0STAT0_CC0 _ATD0STAT0.Bits.CC0 +#define ATD0STAT0_CC1 _ATD0STAT0.Bits.CC1 +#define ATD0STAT0_CC2 _ATD0STAT0.Bits.CC2 +#define ATD0STAT0_FIFOR _ATD0STAT0.Bits.FIFOR +#define ATD0STAT0_ETORF _ATD0STAT0.Bits.ETORF +#define ATD0STAT0_SCF _ATD0STAT0.Bits.SCF +#define ATD0STAT0_CC _ATD0STAT0.MergedBits.grpCC + +#define ATD0STAT0_CC0_MASK 1U +#define ATD0STAT0_CC1_MASK 2U +#define ATD0STAT0_CC2_MASK 4U +#define ATD0STAT0_FIFOR_MASK 16U +#define ATD0STAT0_ETORF_MASK 32U +#define ATD0STAT0_SCF_MASK 128U +#define ATD0STAT0_CC_MASK 7U +#define ATD0STAT0_CC_BITNUM 0U + + +/*** ATD0TEST1 - ATD0 Test Register; 0x00000089 ***/ +typedef union { + byte Byte; + struct { + byte SC :1; /* Special Channel Conversion Bit */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} ATD0TEST1STR; +extern volatile ATD0TEST1STR _ATD0TEST1 @(REG_BASE + 0x00000089UL); +#define ATD0TEST1 _ATD0TEST1.Byte +#define ATD0TEST1_SC _ATD0TEST1.Bits.SC + +#define ATD0TEST1_SC_MASK 1U + + +/*** ATD0STAT1 - ATD 0 Status Register 1; 0x0000008B ***/ +typedef union { + byte Byte; + struct { + byte CCF0 :1; /* Conversion Complete Flag 0 */ + byte CCF1 :1; /* Conversion Complete Flag 1 */ + byte CCF2 :1; /* Conversion Complete Flag 2 */ + byte CCF3 :1; /* Conversion Complete Flag 3 */ + byte CCF4 :1; /* Conversion Complete Flag 4 */ + byte CCF5 :1; /* Conversion Complete Flag 5 */ + byte CCF6 :1; /* Conversion Complete Flag 6 */ + byte CCF7 :1; /* Conversion Complete Flag 7 */ + } Bits; +} ATD0STAT1STR; +extern volatile ATD0STAT1STR _ATD0STAT1 @(REG_BASE + 0x0000008BUL); +#define ATD0STAT1 _ATD0STAT1.Byte +#define ATD0STAT1_CCF0 _ATD0STAT1.Bits.CCF0 +#define ATD0STAT1_CCF1 _ATD0STAT1.Bits.CCF1 +#define ATD0STAT1_CCF2 _ATD0STAT1.Bits.CCF2 +#define ATD0STAT1_CCF3 _ATD0STAT1.Bits.CCF3 +#define ATD0STAT1_CCF4 _ATD0STAT1.Bits.CCF4 +#define ATD0STAT1_CCF5 _ATD0STAT1.Bits.CCF5 +#define ATD0STAT1_CCF6 _ATD0STAT1.Bits.CCF6 +#define ATD0STAT1_CCF7 _ATD0STAT1.Bits.CCF7 + +#define ATD0STAT1_CCF0_MASK 1U +#define ATD0STAT1_CCF1_MASK 2U +#define ATD0STAT1_CCF2_MASK 4U +#define ATD0STAT1_CCF3_MASK 8U +#define ATD0STAT1_CCF4_MASK 16U +#define ATD0STAT1_CCF5_MASK 32U +#define ATD0STAT1_CCF6_MASK 64U +#define ATD0STAT1_CCF7_MASK 128U + + +/*** ATD0DIEN - ATD 0 Input Enable Register; 0x0000008D ***/ +typedef union { + byte Byte; + struct { + byte IEN0 :1; /* ATD Digital Input Enable on channel 0 */ + byte IEN1 :1; /* ATD Digital Input Enable on channel 1 */ + byte IEN2 :1; /* ATD Digital Input Enable on channel 2 */ + byte IEN3 :1; /* ATD Digital Input Enable on channel 3 */ + byte IEN4 :1; /* ATD Digital Input Enable on channel 4 */ + byte IEN5 :1; /* ATD Digital Input Enable on channel 5 */ + byte IEN6 :1; /* ATD Digital Input Enable on channel 6 */ + byte IEN7 :1; /* ATD Digital Input Enable on channel 7 */ + } Bits; +} ATD0DIENSTR; +extern volatile ATD0DIENSTR _ATD0DIEN @(REG_BASE + 0x0000008DUL); +#define ATD0DIEN _ATD0DIEN.Byte +#define ATD0DIEN_IEN0 _ATD0DIEN.Bits.IEN0 +#define ATD0DIEN_IEN1 _ATD0DIEN.Bits.IEN1 +#define ATD0DIEN_IEN2 _ATD0DIEN.Bits.IEN2 +#define ATD0DIEN_IEN3 _ATD0DIEN.Bits.IEN3 +#define ATD0DIEN_IEN4 _ATD0DIEN.Bits.IEN4 +#define ATD0DIEN_IEN5 _ATD0DIEN.Bits.IEN5 +#define ATD0DIEN_IEN6 _ATD0DIEN.Bits.IEN6 +#define ATD0DIEN_IEN7 _ATD0DIEN.Bits.IEN7 + +#define ATD0DIEN_IEN0_MASK 1U +#define ATD0DIEN_IEN1_MASK 2U +#define ATD0DIEN_IEN2_MASK 4U +#define ATD0DIEN_IEN3_MASK 8U +#define ATD0DIEN_IEN4_MASK 16U +#define ATD0DIEN_IEN5_MASK 32U +#define ATD0DIEN_IEN6_MASK 64U +#define ATD0DIEN_IEN7_MASK 128U + + +/*** PORTAD0 - Port AD0 Register; 0x0000008F ***/ +typedef union { + byte Byte; + struct { + byte PTAD0 :1; /* A/D Channel 0 (AN0) Digital Input */ + byte PTAD1 :1; /* A/D Channel 1 (AN1) Digital Input */ + byte PTAD2 :1; /* A/D Channel 2 (AN2) Digital Input */ + byte PTAD3 :1; /* A/D Channel 3 (AN3) Digital Input */ + byte PTAD4 :1; /* A/D Channel 4 (AN4) Digital Input */ + byte PTAD5 :1; /* A/D Channel 5 (AN5) Digital Input */ + byte PTAD6 :1; /* A/D Channel 6 (AN6) Digital Input */ + byte PTAD7 :1; /* A/D Channel 7 (AN7) Digital Input */ + } Bits; +} PORTAD0STR; +extern volatile PORTAD0STR _PORTAD0 @(REG_BASE + 0x0000008FUL); +#define PORTAD0 _PORTAD0.Byte +#define PORTAD0_PTAD0 _PORTAD0.Bits.PTAD0 +#define PORTAD0_PTAD1 _PORTAD0.Bits.PTAD1 +#define PORTAD0_PTAD2 _PORTAD0.Bits.PTAD2 +#define PORTAD0_PTAD3 _PORTAD0.Bits.PTAD3 +#define PORTAD0_PTAD4 _PORTAD0.Bits.PTAD4 +#define PORTAD0_PTAD5 _PORTAD0.Bits.PTAD5 +#define PORTAD0_PTAD6 _PORTAD0.Bits.PTAD6 +#define PORTAD0_PTAD7 _PORTAD0.Bits.PTAD7 + +#define PORTAD0_PTAD0_MASK 1U +#define PORTAD0_PTAD1_MASK 2U +#define PORTAD0_PTAD2_MASK 4U +#define PORTAD0_PTAD3_MASK 8U +#define PORTAD0_PTAD4_MASK 16U +#define PORTAD0_PTAD5_MASK 32U +#define PORTAD0_PTAD6_MASK 64U +#define PORTAD0_PTAD7_MASK 128U + + +/*** ATD0DR0 - ATD 0 Conversion Result Register 0; 0x00000090 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR0H - ATD 0 Conversion Result Register 0 High; 0x00000090 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR0HSTR; + #define ATD0DR0H _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Byte + #define ATD0DR0H_BIT8 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT8 + #define ATD0DR0H_BIT9 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT9 + #define ATD0DR0H_BIT10 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT10 + #define ATD0DR0H_BIT11 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT11 + #define ATD0DR0H_BIT12 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT12 + #define ATD0DR0H_BIT13 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT13 + #define ATD0DR0H_BIT14 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT14 + #define ATD0DR0H_BIT15 _ATD0DR0.Overlap_STR.ATD0DR0HSTR.Bits.BIT15 + + #define ATD0DR0H_BIT8_MASK 1U + #define ATD0DR0H_BIT9_MASK 2U + #define ATD0DR0H_BIT10_MASK 4U + #define ATD0DR0H_BIT11_MASK 8U + #define ATD0DR0H_BIT12_MASK 16U + #define ATD0DR0H_BIT13_MASK 32U + #define ATD0DR0H_BIT14_MASK 64U + #define ATD0DR0H_BIT15_MASK 128U + + + /*** ATD0DR0L - ATD 0 Conversion Result Register 0 Low; 0x00000091 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR0LSTR; + #define ATD0DR0L _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Byte + #define ATD0DR0L_BIT6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT6 + #define ATD0DR0L_BIT7 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.Bits.BIT7 + #define ATD0DR0L_BIT_6 _ATD0DR0.Overlap_STR.ATD0DR0LSTR.MergedBits.grpBIT_6 + #define ATD0DR0L_BIT ATD0DR0L_BIT_6 + + #define ATD0DR0L_BIT6_MASK 64U + #define ATD0DR0L_BIT7_MASK 128U + #define ATD0DR0L_BIT_6_MASK 192U + #define ATD0DR0L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR0STR; +extern volatile ATD0DR0STR _ATD0DR0 @(REG_BASE + 0x00000090UL); +#define ATD0DR0 _ATD0DR0.Word +#define ATD0DR0_BIT6 _ATD0DR0.Bits.BIT6 +#define ATD0DR0_BIT7 _ATD0DR0.Bits.BIT7 +#define ATD0DR0_BIT8 _ATD0DR0.Bits.BIT8 +#define ATD0DR0_BIT9 _ATD0DR0.Bits.BIT9 +#define ATD0DR0_BIT10 _ATD0DR0.Bits.BIT10 +#define ATD0DR0_BIT11 _ATD0DR0.Bits.BIT11 +#define ATD0DR0_BIT12 _ATD0DR0.Bits.BIT12 +#define ATD0DR0_BIT13 _ATD0DR0.Bits.BIT13 +#define ATD0DR0_BIT14 _ATD0DR0.Bits.BIT14 +#define ATD0DR0_BIT15 _ATD0DR0.Bits.BIT15 +/* ATD0DR_ARR: Access 8 ATD0DRx registers in an array */ +#define ATD0DR_ARR ((volatile word *) &ATD0DR0) +#define ATD0DR0_BIT_6 _ATD0DR0.MergedBits.grpBIT_6 +#define ATD0DR0_BIT ATD0DR0_BIT_6 + +#define ATD0DR0_BIT6_MASK 64U +#define ATD0DR0_BIT7_MASK 128U +#define ATD0DR0_BIT8_MASK 256U +#define ATD0DR0_BIT9_MASK 512U +#define ATD0DR0_BIT10_MASK 1024U +#define ATD0DR0_BIT11_MASK 2048U +#define ATD0DR0_BIT12_MASK 4096U +#define ATD0DR0_BIT13_MASK 8192U +#define ATD0DR0_BIT14_MASK 16384U +#define ATD0DR0_BIT15_MASK 32768U +#define ATD0DR0_BIT_6_MASK 65472U +#define ATD0DR0_BIT_6_BITNUM 6U + + +/*** ATD0DR1 - ATD 0 Conversion Result Register 1; 0x00000092 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR1H - ATD 0 Conversion Result Register 1 High; 0x00000092 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR1HSTR; + #define ATD0DR1H _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Byte + #define ATD0DR1H_BIT8 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT8 + #define ATD0DR1H_BIT9 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT9 + #define ATD0DR1H_BIT10 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT10 + #define ATD0DR1H_BIT11 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT11 + #define ATD0DR1H_BIT12 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT12 + #define ATD0DR1H_BIT13 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT13 + #define ATD0DR1H_BIT14 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT14 + #define ATD0DR1H_BIT15 _ATD0DR1.Overlap_STR.ATD0DR1HSTR.Bits.BIT15 + + #define ATD0DR1H_BIT8_MASK 1U + #define ATD0DR1H_BIT9_MASK 2U + #define ATD0DR1H_BIT10_MASK 4U + #define ATD0DR1H_BIT11_MASK 8U + #define ATD0DR1H_BIT12_MASK 16U + #define ATD0DR1H_BIT13_MASK 32U + #define ATD0DR1H_BIT14_MASK 64U + #define ATD0DR1H_BIT15_MASK 128U + + + /*** ATD0DR1L - ATD 0 Conversion Result Register 1 Low; 0x00000093 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR1LSTR; + #define ATD0DR1L _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Byte + #define ATD0DR1L_BIT6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT6 + #define ATD0DR1L_BIT7 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.Bits.BIT7 + #define ATD0DR1L_BIT_6 _ATD0DR1.Overlap_STR.ATD0DR1LSTR.MergedBits.grpBIT_6 + #define ATD0DR1L_BIT ATD0DR1L_BIT_6 + + #define ATD0DR1L_BIT6_MASK 64U + #define ATD0DR1L_BIT7_MASK 128U + #define ATD0DR1L_BIT_6_MASK 192U + #define ATD0DR1L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR1STR; +extern volatile ATD0DR1STR _ATD0DR1 @(REG_BASE + 0x00000092UL); +#define ATD0DR1 _ATD0DR1.Word +#define ATD0DR1_BIT6 _ATD0DR1.Bits.BIT6 +#define ATD0DR1_BIT7 _ATD0DR1.Bits.BIT7 +#define ATD0DR1_BIT8 _ATD0DR1.Bits.BIT8 +#define ATD0DR1_BIT9 _ATD0DR1.Bits.BIT9 +#define ATD0DR1_BIT10 _ATD0DR1.Bits.BIT10 +#define ATD0DR1_BIT11 _ATD0DR1.Bits.BIT11 +#define ATD0DR1_BIT12 _ATD0DR1.Bits.BIT12 +#define ATD0DR1_BIT13 _ATD0DR1.Bits.BIT13 +#define ATD0DR1_BIT14 _ATD0DR1.Bits.BIT14 +#define ATD0DR1_BIT15 _ATD0DR1.Bits.BIT15 +#define ATD0DR1_BIT_6 _ATD0DR1.MergedBits.grpBIT_6 +#define ATD0DR1_BIT ATD0DR1_BIT_6 + +#define ATD0DR1_BIT6_MASK 64U +#define ATD0DR1_BIT7_MASK 128U +#define ATD0DR1_BIT8_MASK 256U +#define ATD0DR1_BIT9_MASK 512U +#define ATD0DR1_BIT10_MASK 1024U +#define ATD0DR1_BIT11_MASK 2048U +#define ATD0DR1_BIT12_MASK 4096U +#define ATD0DR1_BIT13_MASK 8192U +#define ATD0DR1_BIT14_MASK 16384U +#define ATD0DR1_BIT15_MASK 32768U +#define ATD0DR1_BIT_6_MASK 65472U +#define ATD0DR1_BIT_6_BITNUM 6U + + +/*** ATD0DR2 - ATD 0 Conversion Result Register 2; 0x00000094 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR2H - ATD 0 Conversion Result Register 2 High; 0x00000094 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR2HSTR; + #define ATD0DR2H _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Byte + #define ATD0DR2H_BIT8 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT8 + #define ATD0DR2H_BIT9 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT9 + #define ATD0DR2H_BIT10 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT10 + #define ATD0DR2H_BIT11 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT11 + #define ATD0DR2H_BIT12 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT12 + #define ATD0DR2H_BIT13 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT13 + #define ATD0DR2H_BIT14 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT14 + #define ATD0DR2H_BIT15 _ATD0DR2.Overlap_STR.ATD0DR2HSTR.Bits.BIT15 + + #define ATD0DR2H_BIT8_MASK 1U + #define ATD0DR2H_BIT9_MASK 2U + #define ATD0DR2H_BIT10_MASK 4U + #define ATD0DR2H_BIT11_MASK 8U + #define ATD0DR2H_BIT12_MASK 16U + #define ATD0DR2H_BIT13_MASK 32U + #define ATD0DR2H_BIT14_MASK 64U + #define ATD0DR2H_BIT15_MASK 128U + + + /*** ATD0DR2L - ATD 0 Conversion Result Register 2 Low; 0x00000095 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR2LSTR; + #define ATD0DR2L _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Byte + #define ATD0DR2L_BIT6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT6 + #define ATD0DR2L_BIT7 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.Bits.BIT7 + #define ATD0DR2L_BIT_6 _ATD0DR2.Overlap_STR.ATD0DR2LSTR.MergedBits.grpBIT_6 + #define ATD0DR2L_BIT ATD0DR2L_BIT_6 + + #define ATD0DR2L_BIT6_MASK 64U + #define ATD0DR2L_BIT7_MASK 128U + #define ATD0DR2L_BIT_6_MASK 192U + #define ATD0DR2L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR2STR; +extern volatile ATD0DR2STR _ATD0DR2 @(REG_BASE + 0x00000094UL); +#define ATD0DR2 _ATD0DR2.Word +#define ATD0DR2_BIT6 _ATD0DR2.Bits.BIT6 +#define ATD0DR2_BIT7 _ATD0DR2.Bits.BIT7 +#define ATD0DR2_BIT8 _ATD0DR2.Bits.BIT8 +#define ATD0DR2_BIT9 _ATD0DR2.Bits.BIT9 +#define ATD0DR2_BIT10 _ATD0DR2.Bits.BIT10 +#define ATD0DR2_BIT11 _ATD0DR2.Bits.BIT11 +#define ATD0DR2_BIT12 _ATD0DR2.Bits.BIT12 +#define ATD0DR2_BIT13 _ATD0DR2.Bits.BIT13 +#define ATD0DR2_BIT14 _ATD0DR2.Bits.BIT14 +#define ATD0DR2_BIT15 _ATD0DR2.Bits.BIT15 +#define ATD0DR2_BIT_6 _ATD0DR2.MergedBits.grpBIT_6 +#define ATD0DR2_BIT ATD0DR2_BIT_6 + +#define ATD0DR2_BIT6_MASK 64U +#define ATD0DR2_BIT7_MASK 128U +#define ATD0DR2_BIT8_MASK 256U +#define ATD0DR2_BIT9_MASK 512U +#define ATD0DR2_BIT10_MASK 1024U +#define ATD0DR2_BIT11_MASK 2048U +#define ATD0DR2_BIT12_MASK 4096U +#define ATD0DR2_BIT13_MASK 8192U +#define ATD0DR2_BIT14_MASK 16384U +#define ATD0DR2_BIT15_MASK 32768U +#define ATD0DR2_BIT_6_MASK 65472U +#define ATD0DR2_BIT_6_BITNUM 6U + + +/*** ATD0DR3 - ATD 0 Conversion Result Register 3; 0x00000096 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR3H - ATD 0 Conversion Result Register 3 High; 0x00000096 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR3HSTR; + #define ATD0DR3H _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Byte + #define ATD0DR3H_BIT8 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT8 + #define ATD0DR3H_BIT9 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT9 + #define ATD0DR3H_BIT10 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT10 + #define ATD0DR3H_BIT11 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT11 + #define ATD0DR3H_BIT12 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT12 + #define ATD0DR3H_BIT13 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT13 + #define ATD0DR3H_BIT14 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT14 + #define ATD0DR3H_BIT15 _ATD0DR3.Overlap_STR.ATD0DR3HSTR.Bits.BIT15 + + #define ATD0DR3H_BIT8_MASK 1U + #define ATD0DR3H_BIT9_MASK 2U + #define ATD0DR3H_BIT10_MASK 4U + #define ATD0DR3H_BIT11_MASK 8U + #define ATD0DR3H_BIT12_MASK 16U + #define ATD0DR3H_BIT13_MASK 32U + #define ATD0DR3H_BIT14_MASK 64U + #define ATD0DR3H_BIT15_MASK 128U + + + /*** ATD0DR3L - ATD 0 Conversion Result Register 3 Low; 0x00000097 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR3LSTR; + #define ATD0DR3L _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Byte + #define ATD0DR3L_BIT6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT6 + #define ATD0DR3L_BIT7 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.Bits.BIT7 + #define ATD0DR3L_BIT_6 _ATD0DR3.Overlap_STR.ATD0DR3LSTR.MergedBits.grpBIT_6 + #define ATD0DR3L_BIT ATD0DR3L_BIT_6 + + #define ATD0DR3L_BIT6_MASK 64U + #define ATD0DR3L_BIT7_MASK 128U + #define ATD0DR3L_BIT_6_MASK 192U + #define ATD0DR3L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR3STR; +extern volatile ATD0DR3STR _ATD0DR3 @(REG_BASE + 0x00000096UL); +#define ATD0DR3 _ATD0DR3.Word +#define ATD0DR3_BIT6 _ATD0DR3.Bits.BIT6 +#define ATD0DR3_BIT7 _ATD0DR3.Bits.BIT7 +#define ATD0DR3_BIT8 _ATD0DR3.Bits.BIT8 +#define ATD0DR3_BIT9 _ATD0DR3.Bits.BIT9 +#define ATD0DR3_BIT10 _ATD0DR3.Bits.BIT10 +#define ATD0DR3_BIT11 _ATD0DR3.Bits.BIT11 +#define ATD0DR3_BIT12 _ATD0DR3.Bits.BIT12 +#define ATD0DR3_BIT13 _ATD0DR3.Bits.BIT13 +#define ATD0DR3_BIT14 _ATD0DR3.Bits.BIT14 +#define ATD0DR3_BIT15 _ATD0DR3.Bits.BIT15 +#define ATD0DR3_BIT_6 _ATD0DR3.MergedBits.grpBIT_6 +#define ATD0DR3_BIT ATD0DR3_BIT_6 + +#define ATD0DR3_BIT6_MASK 64U +#define ATD0DR3_BIT7_MASK 128U +#define ATD0DR3_BIT8_MASK 256U +#define ATD0DR3_BIT9_MASK 512U +#define ATD0DR3_BIT10_MASK 1024U +#define ATD0DR3_BIT11_MASK 2048U +#define ATD0DR3_BIT12_MASK 4096U +#define ATD0DR3_BIT13_MASK 8192U +#define ATD0DR3_BIT14_MASK 16384U +#define ATD0DR3_BIT15_MASK 32768U +#define ATD0DR3_BIT_6_MASK 65472U +#define ATD0DR3_BIT_6_BITNUM 6U + + +/*** ATD0DR4 - ATD 0 Conversion Result Register 4; 0x00000098 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR4H - ATD 0 Conversion Result Register 4 High; 0x00000098 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR4HSTR; + #define ATD0DR4H _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Byte + #define ATD0DR4H_BIT8 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT8 + #define ATD0DR4H_BIT9 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT9 + #define ATD0DR4H_BIT10 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT10 + #define ATD0DR4H_BIT11 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT11 + #define ATD0DR4H_BIT12 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT12 + #define ATD0DR4H_BIT13 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT13 + #define ATD0DR4H_BIT14 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT14 + #define ATD0DR4H_BIT15 _ATD0DR4.Overlap_STR.ATD0DR4HSTR.Bits.BIT15 + + #define ATD0DR4H_BIT8_MASK 1U + #define ATD0DR4H_BIT9_MASK 2U + #define ATD0DR4H_BIT10_MASK 4U + #define ATD0DR4H_BIT11_MASK 8U + #define ATD0DR4H_BIT12_MASK 16U + #define ATD0DR4H_BIT13_MASK 32U + #define ATD0DR4H_BIT14_MASK 64U + #define ATD0DR4H_BIT15_MASK 128U + + + /*** ATD0DR4L - ATD 0 Conversion Result Register 4 Low; 0x00000099 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR4LSTR; + #define ATD0DR4L _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Byte + #define ATD0DR4L_BIT6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT6 + #define ATD0DR4L_BIT7 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.Bits.BIT7 + #define ATD0DR4L_BIT_6 _ATD0DR4.Overlap_STR.ATD0DR4LSTR.MergedBits.grpBIT_6 + #define ATD0DR4L_BIT ATD0DR4L_BIT_6 + + #define ATD0DR4L_BIT6_MASK 64U + #define ATD0DR4L_BIT7_MASK 128U + #define ATD0DR4L_BIT_6_MASK 192U + #define ATD0DR4L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR4STR; +extern volatile ATD0DR4STR _ATD0DR4 @(REG_BASE + 0x00000098UL); +#define ATD0DR4 _ATD0DR4.Word +#define ATD0DR4_BIT6 _ATD0DR4.Bits.BIT6 +#define ATD0DR4_BIT7 _ATD0DR4.Bits.BIT7 +#define ATD0DR4_BIT8 _ATD0DR4.Bits.BIT8 +#define ATD0DR4_BIT9 _ATD0DR4.Bits.BIT9 +#define ATD0DR4_BIT10 _ATD0DR4.Bits.BIT10 +#define ATD0DR4_BIT11 _ATD0DR4.Bits.BIT11 +#define ATD0DR4_BIT12 _ATD0DR4.Bits.BIT12 +#define ATD0DR4_BIT13 _ATD0DR4.Bits.BIT13 +#define ATD0DR4_BIT14 _ATD0DR4.Bits.BIT14 +#define ATD0DR4_BIT15 _ATD0DR4.Bits.BIT15 +#define ATD0DR4_BIT_6 _ATD0DR4.MergedBits.grpBIT_6 +#define ATD0DR4_BIT ATD0DR4_BIT_6 + +#define ATD0DR4_BIT6_MASK 64U +#define ATD0DR4_BIT7_MASK 128U +#define ATD0DR4_BIT8_MASK 256U +#define ATD0DR4_BIT9_MASK 512U +#define ATD0DR4_BIT10_MASK 1024U +#define ATD0DR4_BIT11_MASK 2048U +#define ATD0DR4_BIT12_MASK 4096U +#define ATD0DR4_BIT13_MASK 8192U +#define ATD0DR4_BIT14_MASK 16384U +#define ATD0DR4_BIT15_MASK 32768U +#define ATD0DR4_BIT_6_MASK 65472U +#define ATD0DR4_BIT_6_BITNUM 6U + + +/*** ATD0DR5 - ATD 0 Conversion Result Register 5; 0x0000009A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR5H - ATD 0 Conversion Result Register 5 High; 0x0000009A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR5HSTR; + #define ATD0DR5H _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Byte + #define ATD0DR5H_BIT8 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT8 + #define ATD0DR5H_BIT9 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT9 + #define ATD0DR5H_BIT10 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT10 + #define ATD0DR5H_BIT11 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT11 + #define ATD0DR5H_BIT12 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT12 + #define ATD0DR5H_BIT13 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT13 + #define ATD0DR5H_BIT14 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT14 + #define ATD0DR5H_BIT15 _ATD0DR5.Overlap_STR.ATD0DR5HSTR.Bits.BIT15 + + #define ATD0DR5H_BIT8_MASK 1U + #define ATD0DR5H_BIT9_MASK 2U + #define ATD0DR5H_BIT10_MASK 4U + #define ATD0DR5H_BIT11_MASK 8U + #define ATD0DR5H_BIT12_MASK 16U + #define ATD0DR5H_BIT13_MASK 32U + #define ATD0DR5H_BIT14_MASK 64U + #define ATD0DR5H_BIT15_MASK 128U + + + /*** ATD0DR5L - ATD 0 Conversion Result Register 5 Low; 0x0000009B ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR5LSTR; + #define ATD0DR5L _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Byte + #define ATD0DR5L_BIT6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT6 + #define ATD0DR5L_BIT7 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.Bits.BIT7 + #define ATD0DR5L_BIT_6 _ATD0DR5.Overlap_STR.ATD0DR5LSTR.MergedBits.grpBIT_6 + #define ATD0DR5L_BIT ATD0DR5L_BIT_6 + + #define ATD0DR5L_BIT6_MASK 64U + #define ATD0DR5L_BIT7_MASK 128U + #define ATD0DR5L_BIT_6_MASK 192U + #define ATD0DR5L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR5STR; +extern volatile ATD0DR5STR _ATD0DR5 @(REG_BASE + 0x0000009AUL); +#define ATD0DR5 _ATD0DR5.Word +#define ATD0DR5_BIT6 _ATD0DR5.Bits.BIT6 +#define ATD0DR5_BIT7 _ATD0DR5.Bits.BIT7 +#define ATD0DR5_BIT8 _ATD0DR5.Bits.BIT8 +#define ATD0DR5_BIT9 _ATD0DR5.Bits.BIT9 +#define ATD0DR5_BIT10 _ATD0DR5.Bits.BIT10 +#define ATD0DR5_BIT11 _ATD0DR5.Bits.BIT11 +#define ATD0DR5_BIT12 _ATD0DR5.Bits.BIT12 +#define ATD0DR5_BIT13 _ATD0DR5.Bits.BIT13 +#define ATD0DR5_BIT14 _ATD0DR5.Bits.BIT14 +#define ATD0DR5_BIT15 _ATD0DR5.Bits.BIT15 +#define ATD0DR5_BIT_6 _ATD0DR5.MergedBits.grpBIT_6 +#define ATD0DR5_BIT ATD0DR5_BIT_6 + +#define ATD0DR5_BIT6_MASK 64U +#define ATD0DR5_BIT7_MASK 128U +#define ATD0DR5_BIT8_MASK 256U +#define ATD0DR5_BIT9_MASK 512U +#define ATD0DR5_BIT10_MASK 1024U +#define ATD0DR5_BIT11_MASK 2048U +#define ATD0DR5_BIT12_MASK 4096U +#define ATD0DR5_BIT13_MASK 8192U +#define ATD0DR5_BIT14_MASK 16384U +#define ATD0DR5_BIT15_MASK 32768U +#define ATD0DR5_BIT_6_MASK 65472U +#define ATD0DR5_BIT_6_BITNUM 6U + + +/*** ATD0DR6 - ATD 0 Conversion Result Register 6; 0x0000009C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR6H - ATD 0 Conversion Result Register 6 High; 0x0000009C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR6HSTR; + #define ATD0DR6H _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Byte + #define ATD0DR6H_BIT8 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT8 + #define ATD0DR6H_BIT9 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT9 + #define ATD0DR6H_BIT10 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT10 + #define ATD0DR6H_BIT11 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT11 + #define ATD0DR6H_BIT12 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT12 + #define ATD0DR6H_BIT13 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT13 + #define ATD0DR6H_BIT14 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT14 + #define ATD0DR6H_BIT15 _ATD0DR6.Overlap_STR.ATD0DR6HSTR.Bits.BIT15 + + #define ATD0DR6H_BIT8_MASK 1U + #define ATD0DR6H_BIT9_MASK 2U + #define ATD0DR6H_BIT10_MASK 4U + #define ATD0DR6H_BIT11_MASK 8U + #define ATD0DR6H_BIT12_MASK 16U + #define ATD0DR6H_BIT13_MASK 32U + #define ATD0DR6H_BIT14_MASK 64U + #define ATD0DR6H_BIT15_MASK 128U + + + /*** ATD0DR6L - ATD 0 Conversion Result Register 6 Low; 0x0000009D ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR6LSTR; + #define ATD0DR6L _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Byte + #define ATD0DR6L_BIT6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT6 + #define ATD0DR6L_BIT7 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.Bits.BIT7 + #define ATD0DR6L_BIT_6 _ATD0DR6.Overlap_STR.ATD0DR6LSTR.MergedBits.grpBIT_6 + #define ATD0DR6L_BIT ATD0DR6L_BIT_6 + + #define ATD0DR6L_BIT6_MASK 64U + #define ATD0DR6L_BIT7_MASK 128U + #define ATD0DR6L_BIT_6_MASK 192U + #define ATD0DR6L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR6STR; +extern volatile ATD0DR6STR _ATD0DR6 @(REG_BASE + 0x0000009CUL); +#define ATD0DR6 _ATD0DR6.Word +#define ATD0DR6_BIT6 _ATD0DR6.Bits.BIT6 +#define ATD0DR6_BIT7 _ATD0DR6.Bits.BIT7 +#define ATD0DR6_BIT8 _ATD0DR6.Bits.BIT8 +#define ATD0DR6_BIT9 _ATD0DR6.Bits.BIT9 +#define ATD0DR6_BIT10 _ATD0DR6.Bits.BIT10 +#define ATD0DR6_BIT11 _ATD0DR6.Bits.BIT11 +#define ATD0DR6_BIT12 _ATD0DR6.Bits.BIT12 +#define ATD0DR6_BIT13 _ATD0DR6.Bits.BIT13 +#define ATD0DR6_BIT14 _ATD0DR6.Bits.BIT14 +#define ATD0DR6_BIT15 _ATD0DR6.Bits.BIT15 +#define ATD0DR6_BIT_6 _ATD0DR6.MergedBits.grpBIT_6 +#define ATD0DR6_BIT ATD0DR6_BIT_6 + +#define ATD0DR6_BIT6_MASK 64U +#define ATD0DR6_BIT7_MASK 128U +#define ATD0DR6_BIT8_MASK 256U +#define ATD0DR6_BIT9_MASK 512U +#define ATD0DR6_BIT10_MASK 1024U +#define ATD0DR6_BIT11_MASK 2048U +#define ATD0DR6_BIT12_MASK 4096U +#define ATD0DR6_BIT13_MASK 8192U +#define ATD0DR6_BIT14_MASK 16384U +#define ATD0DR6_BIT15_MASK 32768U +#define ATD0DR6_BIT_6_MASK 65472U +#define ATD0DR6_BIT_6_BITNUM 6U + + +/*** ATD0DR7 - ATD 0 Conversion Result Register 7; 0x0000009E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD0DR7H - ATD 0 Conversion Result Register 7 High; 0x0000009E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD0DR7HSTR; + #define ATD0DR7H _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Byte + #define ATD0DR7H_BIT8 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT8 + #define ATD0DR7H_BIT9 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT9 + #define ATD0DR7H_BIT10 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT10 + #define ATD0DR7H_BIT11 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT11 + #define ATD0DR7H_BIT12 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT12 + #define ATD0DR7H_BIT13 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT13 + #define ATD0DR7H_BIT14 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT14 + #define ATD0DR7H_BIT15 _ATD0DR7.Overlap_STR.ATD0DR7HSTR.Bits.BIT15 + + #define ATD0DR7H_BIT8_MASK 1U + #define ATD0DR7H_BIT9_MASK 2U + #define ATD0DR7H_BIT10_MASK 4U + #define ATD0DR7H_BIT11_MASK 8U + #define ATD0DR7H_BIT12_MASK 16U + #define ATD0DR7H_BIT13_MASK 32U + #define ATD0DR7H_BIT14_MASK 64U + #define ATD0DR7H_BIT15_MASK 128U + + + /*** ATD0DR7L - ATD 0 Conversion Result Register 7 Low; 0x0000009F ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD0DR7LSTR; + #define ATD0DR7L _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Byte + #define ATD0DR7L_BIT6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT6 + #define ATD0DR7L_BIT7 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.Bits.BIT7 + #define ATD0DR7L_BIT_6 _ATD0DR7.Overlap_STR.ATD0DR7LSTR.MergedBits.grpBIT_6 + #define ATD0DR7L_BIT ATD0DR7L_BIT_6 + + #define ATD0DR7L_BIT6_MASK 64U + #define ATD0DR7L_BIT7_MASK 128U + #define ATD0DR7L_BIT_6_MASK 192U + #define ATD0DR7L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD0DR7STR; +extern volatile ATD0DR7STR _ATD0DR7 @(REG_BASE + 0x0000009EUL); +#define ATD0DR7 _ATD0DR7.Word +#define ATD0DR7_BIT6 _ATD0DR7.Bits.BIT6 +#define ATD0DR7_BIT7 _ATD0DR7.Bits.BIT7 +#define ATD0DR7_BIT8 _ATD0DR7.Bits.BIT8 +#define ATD0DR7_BIT9 _ATD0DR7.Bits.BIT9 +#define ATD0DR7_BIT10 _ATD0DR7.Bits.BIT10 +#define ATD0DR7_BIT11 _ATD0DR7.Bits.BIT11 +#define ATD0DR7_BIT12 _ATD0DR7.Bits.BIT12 +#define ATD0DR7_BIT13 _ATD0DR7.Bits.BIT13 +#define ATD0DR7_BIT14 _ATD0DR7.Bits.BIT14 +#define ATD0DR7_BIT15 _ATD0DR7.Bits.BIT15 +#define ATD0DR7_BIT_6 _ATD0DR7.MergedBits.grpBIT_6 +#define ATD0DR7_BIT ATD0DR7_BIT_6 + +#define ATD0DR7_BIT6_MASK 64U +#define ATD0DR7_BIT7_MASK 128U +#define ATD0DR7_BIT8_MASK 256U +#define ATD0DR7_BIT9_MASK 512U +#define ATD0DR7_BIT10_MASK 1024U +#define ATD0DR7_BIT11_MASK 2048U +#define ATD0DR7_BIT12_MASK 4096U +#define ATD0DR7_BIT13_MASK 8192U +#define ATD0DR7_BIT14_MASK 16384U +#define ATD0DR7_BIT15_MASK 32768U +#define ATD0DR7_BIT_6_MASK 65472U +#define ATD0DR7_BIT_6_BITNUM 6U + + +/*** PWME - PWM Enable Register; 0x000000A0 ***/ +typedef union { + byte Byte; + struct { + byte PWME0 :1; /* Pulse Width Channel 0 Enable */ + byte PWME1 :1; /* Pulse Width Channel 1 Enable */ + byte PWME2 :1; /* Pulse Width Channel 2 Enable */ + byte PWME3 :1; /* Pulse Width Channel 3 Enable */ + byte PWME4 :1; /* Pulse Width Channel 4 Enable */ + byte PWME5 :1; /* Pulse Width Channel 5 Enable */ + byte PWME6 :1; /* Pulse Width Channel 6 Enable */ + byte PWME7 :1; /* Pulse Width Channel 7 Enable */ + } Bits; +} PWMESTR; +extern volatile PWMESTR _PWME @(REG_BASE + 0x000000A0UL); +#define PWME _PWME.Byte +#define PWME_PWME0 _PWME.Bits.PWME0 +#define PWME_PWME1 _PWME.Bits.PWME1 +#define PWME_PWME2 _PWME.Bits.PWME2 +#define PWME_PWME3 _PWME.Bits.PWME3 +#define PWME_PWME4 _PWME.Bits.PWME4 +#define PWME_PWME5 _PWME.Bits.PWME5 +#define PWME_PWME6 _PWME.Bits.PWME6 +#define PWME_PWME7 _PWME.Bits.PWME7 + +#define PWME_PWME0_MASK 1U +#define PWME_PWME1_MASK 2U +#define PWME_PWME2_MASK 4U +#define PWME_PWME3_MASK 8U +#define PWME_PWME4_MASK 16U +#define PWME_PWME5_MASK 32U +#define PWME_PWME6_MASK 64U +#define PWME_PWME7_MASK 128U + + +/*** PWMPOL - PWM Polarity Register; 0x000000A1 ***/ +typedef union { + byte Byte; + struct { + byte PPOL0 :1; /* Pulse Width Channel 0 Polarity */ + byte PPOL1 :1; /* Pulse Width Channel 1 Polarity */ + byte PPOL2 :1; /* Pulse Width Channel 2 Polarity */ + byte PPOL3 :1; /* Pulse Width Channel 3 Polarity */ + byte PPOL4 :1; /* Pulse Width Channel 4 Polarity */ + byte PPOL5 :1; /* Pulse Width Channel 5 Polarity */ + byte PPOL6 :1; /* Pulse Width Channel 6 Polarity */ + byte PPOL7 :1; /* Pulse Width Channel 7 Polarity */ + } Bits; +} PWMPOLSTR; +extern volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000A1UL); +#define PWMPOL _PWMPOL.Byte +#define PWMPOL_PPOL0 _PWMPOL.Bits.PPOL0 +#define PWMPOL_PPOL1 _PWMPOL.Bits.PPOL1 +#define PWMPOL_PPOL2 _PWMPOL.Bits.PPOL2 +#define PWMPOL_PPOL3 _PWMPOL.Bits.PPOL3 +#define PWMPOL_PPOL4 _PWMPOL.Bits.PPOL4 +#define PWMPOL_PPOL5 _PWMPOL.Bits.PPOL5 +#define PWMPOL_PPOL6 _PWMPOL.Bits.PPOL6 +#define PWMPOL_PPOL7 _PWMPOL.Bits.PPOL7 + +#define PWMPOL_PPOL0_MASK 1U +#define PWMPOL_PPOL1_MASK 2U +#define PWMPOL_PPOL2_MASK 4U +#define PWMPOL_PPOL3_MASK 8U +#define PWMPOL_PPOL4_MASK 16U +#define PWMPOL_PPOL5_MASK 32U +#define PWMPOL_PPOL6_MASK 64U +#define PWMPOL_PPOL7_MASK 128U + + +/*** PWMCLK - PWM Clock Select Register; 0x000000A2 ***/ +typedef union { + byte Byte; + struct { + byte PCLK0 :1; /* Pulse Width Channel 0 Clock Select */ + byte PCLK1 :1; /* Pulse Width Channel 1 Clock Select */ + byte PCLK2 :1; /* Pulse Width Channel 2 Clock Select */ + byte PCLK3 :1; /* Pulse Width Channel 3 Clock Select */ + byte PCLK4 :1; /* Pulse Width Channel 4 Clock Select */ + byte PCLK5 :1; /* Pulse Width Channel 5 Clock Select */ + byte PCLK6 :1; /* Pulse Width Channel 6 Clock Select */ + byte PCLK7 :1; /* Pulse Width Channel 7 Clock Select */ + } Bits; +} PWMCLKSTR; +extern volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000A2UL); +#define PWMCLK _PWMCLK.Byte +#define PWMCLK_PCLK0 _PWMCLK.Bits.PCLK0 +#define PWMCLK_PCLK1 _PWMCLK.Bits.PCLK1 +#define PWMCLK_PCLK2 _PWMCLK.Bits.PCLK2 +#define PWMCLK_PCLK3 _PWMCLK.Bits.PCLK3 +#define PWMCLK_PCLK4 _PWMCLK.Bits.PCLK4 +#define PWMCLK_PCLK5 _PWMCLK.Bits.PCLK5 +#define PWMCLK_PCLK6 _PWMCLK.Bits.PCLK6 +#define PWMCLK_PCLK7 _PWMCLK.Bits.PCLK7 + +#define PWMCLK_PCLK0_MASK 1U +#define PWMCLK_PCLK1_MASK 2U +#define PWMCLK_PCLK2_MASK 4U +#define PWMCLK_PCLK3_MASK 8U +#define PWMCLK_PCLK4_MASK 16U +#define PWMCLK_PCLK5_MASK 32U +#define PWMCLK_PCLK6_MASK 64U +#define PWMCLK_PCLK7_MASK 128U + + +/*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000000A3 ***/ +typedef union { + byte Byte; + struct { + byte PCKA0 :1; /* Prescaler Select for Clock A 0 */ + byte PCKA1 :1; /* Prescaler Select for Clock A 1 */ + byte PCKA2 :1; /* Prescaler Select for Clock A 2 */ + byte :1; + byte PCKB0 :1; /* Prescaler Select for Clock B 0 */ + byte PCKB1 :1; /* Prescaler Select for Clock B 1 */ + byte PCKB2 :1; /* Prescaler Select for Clock B 2 */ + byte :1; + } Bits; + struct { + byte grpPCKA :3; + byte :1; + byte grpPCKB :3; + byte :1; + } MergedBits; +} PWMPRCLKSTR; +extern volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000A3UL); +#define PWMPRCLK _PWMPRCLK.Byte +#define PWMPRCLK_PCKA0 _PWMPRCLK.Bits.PCKA0 +#define PWMPRCLK_PCKA1 _PWMPRCLK.Bits.PCKA1 +#define PWMPRCLK_PCKA2 _PWMPRCLK.Bits.PCKA2 +#define PWMPRCLK_PCKB0 _PWMPRCLK.Bits.PCKB0 +#define PWMPRCLK_PCKB1 _PWMPRCLK.Bits.PCKB1 +#define PWMPRCLK_PCKB2 _PWMPRCLK.Bits.PCKB2 +#define PWMPRCLK_PCKA _PWMPRCLK.MergedBits.grpPCKA +#define PWMPRCLK_PCKB _PWMPRCLK.MergedBits.grpPCKB + +#define PWMPRCLK_PCKA0_MASK 1U +#define PWMPRCLK_PCKA1_MASK 2U +#define PWMPRCLK_PCKA2_MASK 4U +#define PWMPRCLK_PCKB0_MASK 16U +#define PWMPRCLK_PCKB1_MASK 32U +#define PWMPRCLK_PCKB2_MASK 64U +#define PWMPRCLK_PCKA_MASK 7U +#define PWMPRCLK_PCKA_BITNUM 0U +#define PWMPRCLK_PCKB_MASK 112U +#define PWMPRCLK_PCKB_BITNUM 4U + + +/*** PWMCAE - PWM Center Align Enable Register; 0x000000A4 ***/ +typedef union { + byte Byte; + struct { + byte CAE0 :1; /* Center Aligned Output Mode on channel 0 */ + byte CAE1 :1; /* Center Aligned Output Mode on channel 1 */ + byte CAE2 :1; /* Center Aligned Output Mode on channel 2 */ + byte CAE3 :1; /* Center Aligned Output Mode on channel 3 */ + byte CAE4 :1; /* Center Aligned Output Mode on channel 4 */ + byte CAE5 :1; /* Center Aligned Output Mode on channel 5 */ + byte CAE6 :1; /* Center Aligned Output Mode on channel 6 */ + byte CAE7 :1; /* Center Aligned Output Mode on channel 7 */ + } Bits; +} PWMCAESTR; +extern volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000A4UL); +#define PWMCAE _PWMCAE.Byte +#define PWMCAE_CAE0 _PWMCAE.Bits.CAE0 +#define PWMCAE_CAE1 _PWMCAE.Bits.CAE1 +#define PWMCAE_CAE2 _PWMCAE.Bits.CAE2 +#define PWMCAE_CAE3 _PWMCAE.Bits.CAE3 +#define PWMCAE_CAE4 _PWMCAE.Bits.CAE4 +#define PWMCAE_CAE5 _PWMCAE.Bits.CAE5 +#define PWMCAE_CAE6 _PWMCAE.Bits.CAE6 +#define PWMCAE_CAE7 _PWMCAE.Bits.CAE7 + +#define PWMCAE_CAE0_MASK 1U +#define PWMCAE_CAE1_MASK 2U +#define PWMCAE_CAE2_MASK 4U +#define PWMCAE_CAE3_MASK 8U +#define PWMCAE_CAE4_MASK 16U +#define PWMCAE_CAE5_MASK 32U +#define PWMCAE_CAE6_MASK 64U +#define PWMCAE_CAE7_MASK 128U + + +/*** PWMCTL - PWM Control Register; 0x000000A5 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte PFRZ :1; /* PWM Counters Stop in Freeze Mode */ + byte PSWAI :1; /* PWM Stops in Wait Mode */ + byte CON01 :1; /* Concatenate channels 0 and 1 */ + byte CON23 :1; /* Concatenate channels 2 and 3 */ + byte CON45 :1; /* Concatenate channels 4 and 5 */ + byte CON67 :1; /* Concatenate channels 6 and 7 */ + } Bits; +} PWMCTLSTR; +extern volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000A5UL); +#define PWMCTL _PWMCTL.Byte +#define PWMCTL_PFRZ _PWMCTL.Bits.PFRZ +#define PWMCTL_PSWAI _PWMCTL.Bits.PSWAI +#define PWMCTL_CON01 _PWMCTL.Bits.CON01 +#define PWMCTL_CON23 _PWMCTL.Bits.CON23 +#define PWMCTL_CON45 _PWMCTL.Bits.CON45 +#define PWMCTL_CON67 _PWMCTL.Bits.CON67 + +#define PWMCTL_PFRZ_MASK 4U +#define PWMCTL_PSWAI_MASK 8U +#define PWMCTL_CON01_MASK 16U +#define PWMCTL_CON23_MASK 32U +#define PWMCTL_CON45_MASK 64U +#define PWMCTL_CON67_MASK 128U + + +/*** PWMSCLA - PWM Scale A Register; 0x000000A8 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale A Bit 0 */ + byte BIT1 :1; /* PWM Scale A Bit 1 */ + byte BIT2 :1; /* PWM Scale A Bit 2 */ + byte BIT3 :1; /* PWM Scale A Bit 3 */ + byte BIT4 :1; /* PWM Scale A Bit 4 */ + byte BIT5 :1; /* PWM Scale A Bit 5 */ + byte BIT6 :1; /* PWM Scale A Bit 6 */ + byte BIT7 :1; /* PWM Scale A Bit 7 */ + } Bits; +} PWMSCLASTR; +extern volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000A8UL); +#define PWMSCLA _PWMSCLA.Byte +#define PWMSCLA_BIT0 _PWMSCLA.Bits.BIT0 +#define PWMSCLA_BIT1 _PWMSCLA.Bits.BIT1 +#define PWMSCLA_BIT2 _PWMSCLA.Bits.BIT2 +#define PWMSCLA_BIT3 _PWMSCLA.Bits.BIT3 +#define PWMSCLA_BIT4 _PWMSCLA.Bits.BIT4 +#define PWMSCLA_BIT5 _PWMSCLA.Bits.BIT5 +#define PWMSCLA_BIT6 _PWMSCLA.Bits.BIT6 +#define PWMSCLA_BIT7 _PWMSCLA.Bits.BIT7 + +#define PWMSCLA_BIT0_MASK 1U +#define PWMSCLA_BIT1_MASK 2U +#define PWMSCLA_BIT2_MASK 4U +#define PWMSCLA_BIT3_MASK 8U +#define PWMSCLA_BIT4_MASK 16U +#define PWMSCLA_BIT5_MASK 32U +#define PWMSCLA_BIT6_MASK 64U +#define PWMSCLA_BIT7_MASK 128U + + +/*** PWMSCLB - PWM Scale B Register; 0x000000A9 ***/ +typedef union { + byte Byte; + struct { + byte BIT0 :1; /* PWM Scale B Bit 0 */ + byte BIT1 :1; /* PWM Scale B Bit 1 */ + byte BIT2 :1; /* PWM Scale B Bit 2 */ + byte BIT3 :1; /* PWM Scale B Bit 3 */ + byte BIT4 :1; /* PWM Scale B Bit 4 */ + byte BIT5 :1; /* PWM Scale B Bit 5 */ + byte BIT6 :1; /* PWM Scale B Bit 6 */ + byte BIT7 :1; /* PWM Scale B Bit 7 */ + } Bits; +} PWMSCLBSTR; +extern volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000A9UL); +#define PWMSCLB _PWMSCLB.Byte +#define PWMSCLB_BIT0 _PWMSCLB.Bits.BIT0 +#define PWMSCLB_BIT1 _PWMSCLB.Bits.BIT1 +#define PWMSCLB_BIT2 _PWMSCLB.Bits.BIT2 +#define PWMSCLB_BIT3 _PWMSCLB.Bits.BIT3 +#define PWMSCLB_BIT4 _PWMSCLB.Bits.BIT4 +#define PWMSCLB_BIT5 _PWMSCLB.Bits.BIT5 +#define PWMSCLB_BIT6 _PWMSCLB.Bits.BIT6 +#define PWMSCLB_BIT7 _PWMSCLB.Bits.BIT7 + +#define PWMSCLB_BIT0_MASK 1U +#define PWMSCLB_BIT1_MASK 2U +#define PWMSCLB_BIT2_MASK 4U +#define PWMSCLB_BIT3_MASK 8U +#define PWMSCLB_BIT4_MASK 16U +#define PWMSCLB_BIT5_MASK 32U +#define PWMSCLB_BIT6_MASK 64U +#define PWMSCLB_BIT7_MASK 128U + + +/*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000000AC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000000AC ***/ + union { + byte Byte; + } PWMCNT0STR; + #define PWMCNT0 _PWMCNT01.Overlap_STR.PWMCNT0STR.Byte + /* PWMCNT_ARR: Access 8 PWMCNTx registers in an array */ + #define PWMCNT_ARR ((volatile byte *) &PWMCNT0) + + + /*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000000AD ***/ + union { + byte Byte; + } PWMCNT1STR; + #define PWMCNT1 _PWMCNT01.Overlap_STR.PWMCNT1STR.Byte + + } Overlap_STR; + +} PWMCNT01STR; +extern volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000ACUL); +#define PWMCNT01 _PWMCNT01.Word + + +/*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000000AE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000000AE ***/ + union { + byte Byte; + } PWMCNT2STR; + #define PWMCNT2 _PWMCNT23.Overlap_STR.PWMCNT2STR.Byte + + + /*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000000AF ***/ + union { + byte Byte; + } PWMCNT3STR; + #define PWMCNT3 _PWMCNT23.Overlap_STR.PWMCNT3STR.Byte + + } Overlap_STR; + +} PWMCNT23STR; +extern volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000AEUL); +#define PWMCNT23 _PWMCNT23.Word + + +/*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000000B0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000000B0 ***/ + union { + byte Byte; + } PWMCNT4STR; + #define PWMCNT4 _PWMCNT45.Overlap_STR.PWMCNT4STR.Byte + + + /*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000000B1 ***/ + union { + byte Byte; + } PWMCNT5STR; + #define PWMCNT5 _PWMCNT45.Overlap_STR.PWMCNT5STR.Byte + + } Overlap_STR; + +} PWMCNT45STR; +extern volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000B0UL); +#define PWMCNT45 _PWMCNT45.Word + + +/*** PWMCNT67 - PWM Channel Counter 67 Register; 0x000000B2 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMCNT6 - PWM Channel Counter 6 Register; 0x000000B2 ***/ + union { + byte Byte; + } PWMCNT6STR; + #define PWMCNT6 _PWMCNT67.Overlap_STR.PWMCNT6STR.Byte + + + /*** PWMCNT7 - PWM Channel Counter 7 Register; 0x000000B3 ***/ + union { + byte Byte; + } PWMCNT7STR; + #define PWMCNT7 _PWMCNT67.Overlap_STR.PWMCNT7STR.Byte + + } Overlap_STR; + +} PWMCNT67STR; +extern volatile PWMCNT67STR _PWMCNT67 @(REG_BASE + 0x000000B2UL); +#define PWMCNT67 _PWMCNT67.Word + + +/*** PWMPER01 - PWM Channel Period 01 Register; 0x000000B4 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER0 - PWM Channel Period 0 Register; 0x000000B4 ***/ + union { + byte Byte; + } PWMPER0STR; + #define PWMPER0 _PWMPER01.Overlap_STR.PWMPER0STR.Byte + /* PWMPER_ARR: Access 8 PWMPERx registers in an array */ + #define PWMPER_ARR ((volatile byte *) &PWMPER0) + + + /*** PWMPER1 - PWM Channel Period 1 Register; 0x000000B5 ***/ + union { + byte Byte; + } PWMPER1STR; + #define PWMPER1 _PWMPER01.Overlap_STR.PWMPER1STR.Byte + + } Overlap_STR; + +} PWMPER01STR; +extern volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000B4UL); +#define PWMPER01 _PWMPER01.Word + + +/*** PWMPER23 - PWM Channel Period 23 Register; 0x000000B6 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER2 - PWM Channel Period 2 Register; 0x000000B6 ***/ + union { + byte Byte; + } PWMPER2STR; + #define PWMPER2 _PWMPER23.Overlap_STR.PWMPER2STR.Byte + + + /*** PWMPER3 - PWM Channel Period 3 Register; 0x000000B7 ***/ + union { + byte Byte; + } PWMPER3STR; + #define PWMPER3 _PWMPER23.Overlap_STR.PWMPER3STR.Byte + + } Overlap_STR; + +} PWMPER23STR; +extern volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000B6UL); +#define PWMPER23 _PWMPER23.Word + + +/*** PWMPER45 - PWM Channel Period 45 Register; 0x000000B8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER4 - PWM Channel Period 4 Register; 0x000000B8 ***/ + union { + byte Byte; + } PWMPER4STR; + #define PWMPER4 _PWMPER45.Overlap_STR.PWMPER4STR.Byte + + + /*** PWMPER5 - PWM Channel Period 5 Register; 0x000000B9 ***/ + union { + byte Byte; + } PWMPER5STR; + #define PWMPER5 _PWMPER45.Overlap_STR.PWMPER5STR.Byte + + } Overlap_STR; + +} PWMPER45STR; +extern volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000B8UL); +#define PWMPER45 _PWMPER45.Word + + +/*** PWMPER67 - PWM Channel Period 67 Register; 0x000000BA ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMPER6 - PWM Channel Period 6 Register; 0x000000BA ***/ + union { + byte Byte; + } PWMPER6STR; + #define PWMPER6 _PWMPER67.Overlap_STR.PWMPER6STR.Byte + + + /*** PWMPER7 - PWM Channel Period 7 Register; 0x000000BB ***/ + union { + byte Byte; + } PWMPER7STR; + #define PWMPER7 _PWMPER67.Overlap_STR.PWMPER7STR.Byte + + } Overlap_STR; + +} PWMPER67STR; +extern volatile PWMPER67STR _PWMPER67 @(REG_BASE + 0x000000BAUL); +#define PWMPER67 _PWMPER67.Word + + +/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000000BC ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000000BC ***/ + union { + byte Byte; + } PWMDTY0STR; + #define PWMDTY0 _PWMDTY01.Overlap_STR.PWMDTY0STR.Byte + /* PWMDTY_ARR: Access 8 PWMDTYx registers in an array */ + #define PWMDTY_ARR ((volatile byte *) &PWMDTY0) + + + /*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000000BD ***/ + union { + byte Byte; + } PWMDTY1STR; + #define PWMDTY1 _PWMDTY01.Overlap_STR.PWMDTY1STR.Byte + + } Overlap_STR; + +} PWMDTY01STR; +extern volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000BCUL); +#define PWMDTY01 _PWMDTY01.Word + + +/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000000BE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000000BE ***/ + union { + byte Byte; + } PWMDTY2STR; + #define PWMDTY2 _PWMDTY23.Overlap_STR.PWMDTY2STR.Byte + + + /*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000000BF ***/ + union { + byte Byte; + } PWMDTY3STR; + #define PWMDTY3 _PWMDTY23.Overlap_STR.PWMDTY3STR.Byte + + } Overlap_STR; + +} PWMDTY23STR; +extern volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000BEUL); +#define PWMDTY23 _PWMDTY23.Word + + +/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000000C0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000000C0 ***/ + union { + byte Byte; + } PWMDTY4STR; + #define PWMDTY4 _PWMDTY45.Overlap_STR.PWMDTY4STR.Byte + + + /*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000000C1 ***/ + union { + byte Byte; + } PWMDTY5STR; + #define PWMDTY5 _PWMDTY45.Overlap_STR.PWMDTY5STR.Byte + + } Overlap_STR; + +} PWMDTY45STR; +extern volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000C0UL); +#define PWMDTY45 _PWMDTY45.Word + + +/*** PWMDTY67 - PWM Channel Duty 67 Register; 0x000000C2 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** PWMDTY6 - PWM Channel Duty 6 Register; 0x000000C2 ***/ + union { + byte Byte; + } PWMDTY6STR; + #define PWMDTY6 _PWMDTY67.Overlap_STR.PWMDTY6STR.Byte + + + /*** PWMDTY7 - PWM Channel Duty 7 Register; 0x000000C3 ***/ + union { + byte Byte; + } PWMDTY7STR; + #define PWMDTY7 _PWMDTY67.Overlap_STR.PWMDTY7STR.Byte + + } Overlap_STR; + +} PWMDTY67STR; +extern volatile PWMDTY67STR _PWMDTY67 @(REG_BASE + 0x000000C2UL); +#define PWMDTY67 _PWMDTY67.Word + + +/*** PWMSDN - PWM Shutdown Register; 0x000000C4 ***/ +typedef union { + byte Byte; + struct { + byte PWM7ENA :1; /* PWM emergency shutdown Enable */ + byte PWM7INL :1; /* PWM shutdown active input level for ch. 7 */ + byte PWM7IN :1; /* PWM channel 7 input status */ + byte :1; + byte PWMLVL :1; /* PWM shutdown output Level */ + byte PWMRSTRT :1; /* PWM Restart */ + byte PWMIE :1; /* PWM Interrupt Enable */ + byte PWMIF :1; /* PWM Interrupt Flag */ + } Bits; +} PWMSDNSTR; +extern volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000C4UL); +#define PWMSDN _PWMSDN.Byte +#define PWMSDN_PWM7ENA _PWMSDN.Bits.PWM7ENA +#define PWMSDN_PWM7INL _PWMSDN.Bits.PWM7INL +#define PWMSDN_PWM7IN _PWMSDN.Bits.PWM7IN +#define PWMSDN_PWMLVL _PWMSDN.Bits.PWMLVL +#define PWMSDN_PWMRSTRT _PWMSDN.Bits.PWMRSTRT +#define PWMSDN_PWMIE _PWMSDN.Bits.PWMIE +#define PWMSDN_PWMIF _PWMSDN.Bits.PWMIF + +#define PWMSDN_PWM7ENA_MASK 1U +#define PWMSDN_PWM7INL_MASK 2U +#define PWMSDN_PWM7IN_MASK 4U +#define PWMSDN_PWMLVL_MASK 16U +#define PWMSDN_PWMRSTRT_MASK 32U +#define PWMSDN_PWMIE_MASK 64U +#define PWMSDN_PWMIF_MASK 128U + + +/*** SCI0BD - SCI 0 Baud Rate Register; 0x000000C8 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SCI0BDH - SCI 0 Baud Rate Register High; 0x000000C8 ***/ + union { + byte Byte; + struct { + byte SBR8 :1; /* SCI Baud Rate Bit 8 */ + byte SBR9 :1; /* SCI Baud Rate Bit 9 */ + byte SBR10 :1; /* SCI Baud Rate Bit 10 */ + byte SBR11 :1; /* SCI Baud Rate Bit 11 */ + byte SBR12 :1; /* SCI Baud Rate Bit 12 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpSBR_8 :5; + byte :1; + byte :1; + byte :1; + } MergedBits; + } SCI0BDHSTR; + #define SCI0BDH _SCI0BD.Overlap_STR.SCI0BDHSTR.Byte + #define SCI0BDH_SBR8 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR8 + #define SCI0BDH_SBR9 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR9 + #define SCI0BDH_SBR10 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR10 + #define SCI0BDH_SBR11 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR11 + #define SCI0BDH_SBR12 _SCI0BD.Overlap_STR.SCI0BDHSTR.Bits.SBR12 + #define SCI0BDH_SBR_8 _SCI0BD.Overlap_STR.SCI0BDHSTR.MergedBits.grpSBR_8 + #define SCI0BDH_SBR SCI0BDH_SBR_8 + + #define SCI0BDH_SBR8_MASK 1U + #define SCI0BDH_SBR9_MASK 2U + #define SCI0BDH_SBR10_MASK 4U + #define SCI0BDH_SBR11_MASK 8U + #define SCI0BDH_SBR12_MASK 16U + #define SCI0BDH_SBR_8_MASK 31U + #define SCI0BDH_SBR_8_BITNUM 0U + + + /*** SCI0BDL - SCI 0 Baud Rate Register Low; 0x000000C9 ***/ + union { + byte Byte; + struct { + byte SBR0 :1; /* SCI Baud Rate Bit 0 */ + byte SBR1 :1; /* SCI Baud Rate Bit 1 */ + byte SBR2 :1; /* SCI Baud Rate Bit 2 */ + byte SBR3 :1; /* SCI Baud Rate Bit 3 */ + byte SBR4 :1; /* SCI Baud Rate Bit 4 */ + byte SBR5 :1; /* SCI Baud Rate Bit 5 */ + byte SBR6 :1; /* SCI Baud Rate Bit 6 */ + byte SBR7 :1; /* SCI Baud Rate Bit 7 */ + } Bits; + } SCI0BDLSTR; + #define SCI0BDL _SCI0BD.Overlap_STR.SCI0BDLSTR.Byte + #define SCI0BDL_SBR0 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR0 + #define SCI0BDL_SBR1 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR1 + #define SCI0BDL_SBR2 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR2 + #define SCI0BDL_SBR3 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR3 + #define SCI0BDL_SBR4 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR4 + #define SCI0BDL_SBR5 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR5 + #define SCI0BDL_SBR6 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR6 + #define SCI0BDL_SBR7 _SCI0BD.Overlap_STR.SCI0BDLSTR.Bits.SBR7 + + #define SCI0BDL_SBR0_MASK 1U + #define SCI0BDL_SBR1_MASK 2U + #define SCI0BDL_SBR2_MASK 4U + #define SCI0BDL_SBR3_MASK 8U + #define SCI0BDL_SBR4_MASK 16U + #define SCI0BDL_SBR5_MASK 32U + #define SCI0BDL_SBR6_MASK 64U + #define SCI0BDL_SBR7_MASK 128U + + } Overlap_STR; + + struct { + word SBR0 :1; /* SCI Baud Rate Bit 0 */ + word SBR1 :1; /* SCI Baud Rate Bit 1 */ + word SBR2 :1; /* SCI Baud Rate Bit 2 */ + word SBR3 :1; /* SCI Baud Rate Bit 3 */ + word SBR4 :1; /* SCI Baud Rate Bit 4 */ + word SBR5 :1; /* SCI Baud Rate Bit 5 */ + word SBR6 :1; /* SCI Baud Rate Bit 6 */ + word SBR7 :1; /* SCI Baud Rate Bit 7 */ + word SBR8 :1; /* SCI Baud Rate Bit 8 */ + word SBR9 :1; /* SCI Baud Rate Bit 9 */ + word SBR10 :1; /* SCI Baud Rate Bit 10 */ + word SBR11 :1; /* SCI Baud Rate Bit 11 */ + word SBR12 :1; /* SCI Baud Rate Bit 12 */ + word :1; + word :1; + word :1; + } Bits; + struct { + word grpSBR :13; + word :1; + word :1; + word :1; + } MergedBits; +} SCI0BDSTR; +extern volatile SCI0BDSTR _SCI0BD @(REG_BASE + 0x000000C8UL); +#define SCI0BD _SCI0BD.Word +#define SCI0BD_SBR0 _SCI0BD.Bits.SBR0 +#define SCI0BD_SBR1 _SCI0BD.Bits.SBR1 +#define SCI0BD_SBR2 _SCI0BD.Bits.SBR2 +#define SCI0BD_SBR3 _SCI0BD.Bits.SBR3 +#define SCI0BD_SBR4 _SCI0BD.Bits.SBR4 +#define SCI0BD_SBR5 _SCI0BD.Bits.SBR5 +#define SCI0BD_SBR6 _SCI0BD.Bits.SBR6 +#define SCI0BD_SBR7 _SCI0BD.Bits.SBR7 +#define SCI0BD_SBR8 _SCI0BD.Bits.SBR8 +#define SCI0BD_SBR9 _SCI0BD.Bits.SBR9 +#define SCI0BD_SBR10 _SCI0BD.Bits.SBR10 +#define SCI0BD_SBR11 _SCI0BD.Bits.SBR11 +#define SCI0BD_SBR12 _SCI0BD.Bits.SBR12 +#define SCI0BD_SBR _SCI0BD.MergedBits.grpSBR + +#define SCI0BD_SBR0_MASK 1U +#define SCI0BD_SBR1_MASK 2U +#define SCI0BD_SBR2_MASK 4U +#define SCI0BD_SBR3_MASK 8U +#define SCI0BD_SBR4_MASK 16U +#define SCI0BD_SBR5_MASK 32U +#define SCI0BD_SBR6_MASK 64U +#define SCI0BD_SBR7_MASK 128U +#define SCI0BD_SBR8_MASK 256U +#define SCI0BD_SBR9_MASK 512U +#define SCI0BD_SBR10_MASK 1024U +#define SCI0BD_SBR11_MASK 2048U +#define SCI0BD_SBR12_MASK 4096U +#define SCI0BD_SBR_MASK 8191U +#define SCI0BD_SBR_BITNUM 0U + + +/*** SCI0CR1 - SCI 0 Control Register 1; 0x000000CA ***/ +typedef union { + byte Byte; + struct { + byte PT :1; /* Parity Type Bit */ + byte PE :1; /* Parity Enable Bit */ + byte ILT :1; /* Idle Line Type Bit */ + byte WAKE :1; /* Wakeup Condition Bit */ + byte M :1; /* Data Format Mode Bit */ + byte RSRC :1; /* Receiver Source Bit */ + byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */ + byte LOOPS :1; /* Loop Select Bit */ + } Bits; +} SCI0CR1STR; +extern volatile SCI0CR1STR _SCI0CR1 @(REG_BASE + 0x000000CAUL); +#define SCI0CR1 _SCI0CR1.Byte +#define SCI0CR1_PT _SCI0CR1.Bits.PT +#define SCI0CR1_PE _SCI0CR1.Bits.PE +#define SCI0CR1_ILT _SCI0CR1.Bits.ILT +#define SCI0CR1_WAKE _SCI0CR1.Bits.WAKE +#define SCI0CR1_M _SCI0CR1.Bits.M +#define SCI0CR1_RSRC _SCI0CR1.Bits.RSRC +#define SCI0CR1_SCISWAI _SCI0CR1.Bits.SCISWAI +#define SCI0CR1_LOOPS _SCI0CR1.Bits.LOOPS + +#define SCI0CR1_PT_MASK 1U +#define SCI0CR1_PE_MASK 2U +#define SCI0CR1_ILT_MASK 4U +#define SCI0CR1_WAKE_MASK 8U +#define SCI0CR1_M_MASK 16U +#define SCI0CR1_RSRC_MASK 32U +#define SCI0CR1_SCISWAI_MASK 64U +#define SCI0CR1_LOOPS_MASK 128U + + +/*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB ***/ +typedef union { + byte Byte; + struct { + byte SBK :1; /* Send Break Bit */ + byte RWU :1; /* Receiver Wakeup Bit */ + byte RE :1; /* Receiver Enable Bit */ + byte TE :1; /* Transmitter Enable Bit */ + byte ILIE :1; /* Idle Line Interrupt Enable Bit */ + byte RIE :1; /* Receiver Full Interrupt Enable Bit */ + byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ + byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ + } Bits; +} SCI0CR2STR; +extern volatile SCI0CR2STR _SCI0CR2 @(REG_BASE + 0x000000CBUL); +#define SCI0CR2 _SCI0CR2.Byte +#define SCI0CR2_SBK _SCI0CR2.Bits.SBK +#define SCI0CR2_RWU _SCI0CR2.Bits.RWU +#define SCI0CR2_RE _SCI0CR2.Bits.RE +#define SCI0CR2_TE _SCI0CR2.Bits.TE +#define SCI0CR2_ILIE _SCI0CR2.Bits.ILIE +#define SCI0CR2_RIE _SCI0CR2.Bits.RIE +#define SCI0CR2_TCIE _SCI0CR2.Bits.TCIE +#define SCI0CR2_SCTIE _SCI0CR2.Bits.SCTIE + +#define SCI0CR2_SBK_MASK 1U +#define SCI0CR2_RWU_MASK 2U +#define SCI0CR2_RE_MASK 4U +#define SCI0CR2_TE_MASK 8U +#define SCI0CR2_ILIE_MASK 16U +#define SCI0CR2_RIE_MASK 32U +#define SCI0CR2_TCIE_MASK 64U +#define SCI0CR2_SCTIE_MASK 128U + + +/*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC ***/ +typedef union { + byte Byte; + struct { + byte PF :1; /* Parity Error Flag */ + byte FE :1; /* Framing Error Flag */ + byte NF :1; /* Noise Flag */ + byte OR :1; /* Overrun Flag */ + byte IDLE :1; /* Idle Line Flag */ + byte RDRF :1; /* Receive Data Register Full Flag */ + byte TC :1; /* Transmit Complete Flag */ + byte TDRE :1; /* Transmit Data Register Empty Flag */ + } Bits; +} SCI0SR1STR; +extern volatile SCI0SR1STR _SCI0SR1 @(REG_BASE + 0x000000CCUL); +#define SCI0SR1 _SCI0SR1.Byte +#define SCI0SR1_PF _SCI0SR1.Bits.PF +#define SCI0SR1_FE _SCI0SR1.Bits.FE +#define SCI0SR1_NF _SCI0SR1.Bits.NF +#define SCI0SR1_OR _SCI0SR1.Bits.OR +#define SCI0SR1_IDLE _SCI0SR1.Bits.IDLE +#define SCI0SR1_RDRF _SCI0SR1.Bits.RDRF +#define SCI0SR1_TC _SCI0SR1.Bits.TC +#define SCI0SR1_TDRE _SCI0SR1.Bits.TDRE + +#define SCI0SR1_PF_MASK 1U +#define SCI0SR1_FE_MASK 2U +#define SCI0SR1_NF_MASK 4U +#define SCI0SR1_OR_MASK 8U +#define SCI0SR1_IDLE_MASK 16U +#define SCI0SR1_RDRF_MASK 32U +#define SCI0SR1_TC_MASK 64U +#define SCI0SR1_TDRE_MASK 128U + + +/*** SCI0SR2 - SCI 0 Status Register 2; 0x000000CD ***/ +typedef union { + byte Byte; + struct { + byte RAF :1; /* Receiver Active Flag */ + byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ + byte BRK13 :1; /* Break Transmit character length */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} SCI0SR2STR; +extern volatile SCI0SR2STR _SCI0SR2 @(REG_BASE + 0x000000CDUL); +#define SCI0SR2 _SCI0SR2.Byte +#define SCI0SR2_RAF _SCI0SR2.Bits.RAF +#define SCI0SR2_TXDIR _SCI0SR2.Bits.TXDIR +#define SCI0SR2_BRK13 _SCI0SR2.Bits.BRK13 + +#define SCI0SR2_RAF_MASK 1U +#define SCI0SR2_TXDIR_MASK 2U +#define SCI0SR2_BRK13_MASK 4U + + +/*** SCI0DRH - SCI 0 Data Register High; 0x000000CE ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte T8 :1; /* Transmit Bit 8 */ + byte R8 :1; /* Received Bit 8 */ + } Bits; +} SCI0DRHSTR; +extern volatile SCI0DRHSTR _SCI0DRH @(REG_BASE + 0x000000CEUL); +#define SCI0DRH _SCI0DRH.Byte +#define SCI0DRH_T8 _SCI0DRH.Bits.T8 +#define SCI0DRH_R8 _SCI0DRH.Bits.R8 + +#define SCI0DRH_T8_MASK 64U +#define SCI0DRH_R8_MASK 128U + + +/*** SCI0DRL - SCI 0 Data Register Low; 0x000000CF ***/ +typedef union { + byte Byte; + struct { + byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ + byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ + byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ + byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ + byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ + byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ + byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ + byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ + } Bits; +} SCI0DRLSTR; +extern volatile SCI0DRLSTR _SCI0DRL @(REG_BASE + 0x000000CFUL); +#define SCI0DRL _SCI0DRL.Byte +#define SCI0DRL_R0_T0 _SCI0DRL.Bits.R0_T0 +#define SCI0DRL_R1_T1 _SCI0DRL.Bits.R1_T1 +#define SCI0DRL_R2_T2 _SCI0DRL.Bits.R2_T2 +#define SCI0DRL_R3_T3 _SCI0DRL.Bits.R3_T3 +#define SCI0DRL_R4_T4 _SCI0DRL.Bits.R4_T4 +#define SCI0DRL_R5_T5 _SCI0DRL.Bits.R5_T5 +#define SCI0DRL_R6_T6 _SCI0DRL.Bits.R6_T6 +#define SCI0DRL_R7_T7 _SCI0DRL.Bits.R7_T7 + +#define SCI0DRL_R0_T0_MASK 1U +#define SCI0DRL_R1_T1_MASK 2U +#define SCI0DRL_R2_T2_MASK 4U +#define SCI0DRL_R3_T3_MASK 8U +#define SCI0DRL_R4_T4_MASK 16U +#define SCI0DRL_R5_T5_MASK 32U +#define SCI0DRL_R6_T6_MASK 64U +#define SCI0DRL_R7_T7_MASK 128U + + +/*** SCI1BD - SCI 1 Baud Rate Register; 0x000000D0 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** SCI1BDH - SCI 1 Baud Rate Register High; 0x000000D0 ***/ + union { + byte Byte; + struct { + byte SBR8 :1; /* SCI Baud Rate Bit 8 */ + byte SBR9 :1; /* SCI Baud Rate Bit 9 */ + byte SBR10 :1; /* SCI Baud Rate Bit 10 */ + byte SBR11 :1; /* SCI Baud Rate Bit 11 */ + byte SBR12 :1; /* SCI Baud Rate Bit 12 */ + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpSBR_8 :5; + byte :1; + byte :1; + byte :1; + } MergedBits; + } SCI1BDHSTR; + #define SCI1BDH _SCI1BD.Overlap_STR.SCI1BDHSTR.Byte + #define SCI1BDH_SBR8 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR8 + #define SCI1BDH_SBR9 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR9 + #define SCI1BDH_SBR10 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR10 + #define SCI1BDH_SBR11 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR11 + #define SCI1BDH_SBR12 _SCI1BD.Overlap_STR.SCI1BDHSTR.Bits.SBR12 + #define SCI1BDH_SBR_8 _SCI1BD.Overlap_STR.SCI1BDHSTR.MergedBits.grpSBR_8 + #define SCI1BDH_SBR SCI1BDH_SBR_8 + + #define SCI1BDH_SBR8_MASK 1U + #define SCI1BDH_SBR9_MASK 2U + #define SCI1BDH_SBR10_MASK 4U + #define SCI1BDH_SBR11_MASK 8U + #define SCI1BDH_SBR12_MASK 16U + #define SCI1BDH_SBR_8_MASK 31U + #define SCI1BDH_SBR_8_BITNUM 0U + + + /*** SCI1BDL - SCI 1 Baud Rate Register Low; 0x000000D1 ***/ + union { + byte Byte; + struct { + byte SBR0 :1; /* SCI Baud Rate Bit 0 */ + byte SBR1 :1; /* SCI Baud Rate Bit 1 */ + byte SBR2 :1; /* SCI Baud Rate Bit 2 */ + byte SBR3 :1; /* SCI Baud Rate Bit 3 */ + byte SBR4 :1; /* SCI Baud Rate Bit 4 */ + byte SBR5 :1; /* SCI Baud Rate Bit 5 */ + byte SBR6 :1; /* SCI Baud Rate Bit 6 */ + byte SBR7 :1; /* SCI Baud Rate Bit 7 */ + } Bits; + } SCI1BDLSTR; + #define SCI1BDL _SCI1BD.Overlap_STR.SCI1BDLSTR.Byte + #define SCI1BDL_SBR0 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR0 + #define SCI1BDL_SBR1 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR1 + #define SCI1BDL_SBR2 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR2 + #define SCI1BDL_SBR3 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR3 + #define SCI1BDL_SBR4 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR4 + #define SCI1BDL_SBR5 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR5 + #define SCI1BDL_SBR6 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR6 + #define SCI1BDL_SBR7 _SCI1BD.Overlap_STR.SCI1BDLSTR.Bits.SBR7 + + #define SCI1BDL_SBR0_MASK 1U + #define SCI1BDL_SBR1_MASK 2U + #define SCI1BDL_SBR2_MASK 4U + #define SCI1BDL_SBR3_MASK 8U + #define SCI1BDL_SBR4_MASK 16U + #define SCI1BDL_SBR5_MASK 32U + #define SCI1BDL_SBR6_MASK 64U + #define SCI1BDL_SBR7_MASK 128U + + } Overlap_STR; + + struct { + word SBR0 :1; /* SCI Baud Rate Bit 0 */ + word SBR1 :1; /* SCI Baud Rate Bit 1 */ + word SBR2 :1; /* SCI Baud Rate Bit 2 */ + word SBR3 :1; /* SCI Baud Rate Bit 3 */ + word SBR4 :1; /* SCI Baud Rate Bit 4 */ + word SBR5 :1; /* SCI Baud Rate Bit 5 */ + word SBR6 :1; /* SCI Baud Rate Bit 6 */ + word SBR7 :1; /* SCI Baud Rate Bit 7 */ + word SBR8 :1; /* SCI Baud Rate Bit 8 */ + word SBR9 :1; /* SCI Baud Rate Bit 9 */ + word SBR10 :1; /* SCI Baud Rate Bit 10 */ + word SBR11 :1; /* SCI Baud Rate Bit 11 */ + word SBR12 :1; /* SCI Baud Rate Bit 12 */ + word :1; + word :1; + word :1; + } Bits; + struct { + word grpSBR :13; + word :1; + word :1; + word :1; + } MergedBits; +} SCI1BDSTR; +extern volatile SCI1BDSTR _SCI1BD @(REG_BASE + 0x000000D0UL); +#define SCI1BD _SCI1BD.Word +#define SCI1BD_SBR0 _SCI1BD.Bits.SBR0 +#define SCI1BD_SBR1 _SCI1BD.Bits.SBR1 +#define SCI1BD_SBR2 _SCI1BD.Bits.SBR2 +#define SCI1BD_SBR3 _SCI1BD.Bits.SBR3 +#define SCI1BD_SBR4 _SCI1BD.Bits.SBR4 +#define SCI1BD_SBR5 _SCI1BD.Bits.SBR5 +#define SCI1BD_SBR6 _SCI1BD.Bits.SBR6 +#define SCI1BD_SBR7 _SCI1BD.Bits.SBR7 +#define SCI1BD_SBR8 _SCI1BD.Bits.SBR8 +#define SCI1BD_SBR9 _SCI1BD.Bits.SBR9 +#define SCI1BD_SBR10 _SCI1BD.Bits.SBR10 +#define SCI1BD_SBR11 _SCI1BD.Bits.SBR11 +#define SCI1BD_SBR12 _SCI1BD.Bits.SBR12 +#define SCI1BD_SBR _SCI1BD.MergedBits.grpSBR + +#define SCI1BD_SBR0_MASK 1U +#define SCI1BD_SBR1_MASK 2U +#define SCI1BD_SBR2_MASK 4U +#define SCI1BD_SBR3_MASK 8U +#define SCI1BD_SBR4_MASK 16U +#define SCI1BD_SBR5_MASK 32U +#define SCI1BD_SBR6_MASK 64U +#define SCI1BD_SBR7_MASK 128U +#define SCI1BD_SBR8_MASK 256U +#define SCI1BD_SBR9_MASK 512U +#define SCI1BD_SBR10_MASK 1024U +#define SCI1BD_SBR11_MASK 2048U +#define SCI1BD_SBR12_MASK 4096U +#define SCI1BD_SBR_MASK 8191U +#define SCI1BD_SBR_BITNUM 0U + + +/*** SCI1CR1 - SCI 1 Control Register 1; 0x000000D2 ***/ +typedef union { + byte Byte; + struct { + byte PT :1; /* Parity Type Bit */ + byte PE :1; /* Parity Enable Bit */ + byte ILT :1; /* Idle Line Type Bit */ + byte WAKE :1; /* Wakeup Condition Bit */ + byte M :1; /* Data Format Mode Bit */ + byte RSRC :1; /* Receiver Source Bit */ + byte SCISWAI :1; /* SCI Stop in Wait Mode Bit */ + byte LOOPS :1; /* Loop Select Bit */ + } Bits; +} SCI1CR1STR; +extern volatile SCI1CR1STR _SCI1CR1 @(REG_BASE + 0x000000D2UL); +#define SCI1CR1 _SCI1CR1.Byte +#define SCI1CR1_PT _SCI1CR1.Bits.PT +#define SCI1CR1_PE _SCI1CR1.Bits.PE +#define SCI1CR1_ILT _SCI1CR1.Bits.ILT +#define SCI1CR1_WAKE _SCI1CR1.Bits.WAKE +#define SCI1CR1_M _SCI1CR1.Bits.M +#define SCI1CR1_RSRC _SCI1CR1.Bits.RSRC +#define SCI1CR1_SCISWAI _SCI1CR1.Bits.SCISWAI +#define SCI1CR1_LOOPS _SCI1CR1.Bits.LOOPS + +#define SCI1CR1_PT_MASK 1U +#define SCI1CR1_PE_MASK 2U +#define SCI1CR1_ILT_MASK 4U +#define SCI1CR1_WAKE_MASK 8U +#define SCI1CR1_M_MASK 16U +#define SCI1CR1_RSRC_MASK 32U +#define SCI1CR1_SCISWAI_MASK 64U +#define SCI1CR1_LOOPS_MASK 128U + + +/*** SCI1CR2 - SCI 1 Control Register 2; 0x000000D3 ***/ +typedef union { + byte Byte; + struct { + byte SBK :1; /* Send Break Bit */ + byte RWU :1; /* Receiver Wakeup Bit */ + byte RE :1; /* Receiver Enable Bit */ + byte TE :1; /* Transmitter Enable Bit */ + byte ILIE :1; /* Idle Line Interrupt Enable Bit */ + byte RIE :1; /* Receiver Full Interrupt Enable Bit */ + byte TCIE :1; /* Transmission Complete Interrupt Enable Bit */ + byte SCTIE :1; /* Transmitter Interrupt Enable Bit */ + } Bits; +} SCI1CR2STR; +extern volatile SCI1CR2STR _SCI1CR2 @(REG_BASE + 0x000000D3UL); +#define SCI1CR2 _SCI1CR2.Byte +#define SCI1CR2_SBK _SCI1CR2.Bits.SBK +#define SCI1CR2_RWU _SCI1CR2.Bits.RWU +#define SCI1CR2_RE _SCI1CR2.Bits.RE +#define SCI1CR2_TE _SCI1CR2.Bits.TE +#define SCI1CR2_ILIE _SCI1CR2.Bits.ILIE +#define SCI1CR2_RIE _SCI1CR2.Bits.RIE +#define SCI1CR2_TCIE _SCI1CR2.Bits.TCIE +#define SCI1CR2_SCTIE _SCI1CR2.Bits.SCTIE + +#define SCI1CR2_SBK_MASK 1U +#define SCI1CR2_RWU_MASK 2U +#define SCI1CR2_RE_MASK 4U +#define SCI1CR2_TE_MASK 8U +#define SCI1CR2_ILIE_MASK 16U +#define SCI1CR2_RIE_MASK 32U +#define SCI1CR2_TCIE_MASK 64U +#define SCI1CR2_SCTIE_MASK 128U + + +/*** SCI1SR1 - SCI 1 Status Register 1; 0x000000D4 ***/ +typedef union { + byte Byte; + struct { + byte PF :1; /* Parity Error Flag */ + byte FE :1; /* Framing Error Flag */ + byte NF :1; /* Noise Flag */ + byte OR :1; /* Overrun Flag */ + byte IDLE :1; /* Idle Line Flag */ + byte RDRF :1; /* Receive Data Register Full Flag */ + byte TC :1; /* Transmit Complete Flag */ + byte TDRE :1; /* Transmit Data Register Empty Flag */ + } Bits; +} SCI1SR1STR; +extern volatile SCI1SR1STR _SCI1SR1 @(REG_BASE + 0x000000D4UL); +#define SCI1SR1 _SCI1SR1.Byte +#define SCI1SR1_PF _SCI1SR1.Bits.PF +#define SCI1SR1_FE _SCI1SR1.Bits.FE +#define SCI1SR1_NF _SCI1SR1.Bits.NF +#define SCI1SR1_OR _SCI1SR1.Bits.OR +#define SCI1SR1_IDLE _SCI1SR1.Bits.IDLE +#define SCI1SR1_RDRF _SCI1SR1.Bits.RDRF +#define SCI1SR1_TC _SCI1SR1.Bits.TC +#define SCI1SR1_TDRE _SCI1SR1.Bits.TDRE + +#define SCI1SR1_PF_MASK 1U +#define SCI1SR1_FE_MASK 2U +#define SCI1SR1_NF_MASK 4U +#define SCI1SR1_OR_MASK 8U +#define SCI1SR1_IDLE_MASK 16U +#define SCI1SR1_RDRF_MASK 32U +#define SCI1SR1_TC_MASK 64U +#define SCI1SR1_TDRE_MASK 128U + + +/*** SCI1SR2 - SCI 1 Status Register 2; 0x000000D5 ***/ +typedef union { + byte Byte; + struct { + byte RAF :1; /* Receiver Active Flag */ + byte TXDIR :1; /* Transmitter pin data direction in Single-Wire mode */ + byte BRK13 :1; /* Break Transmit character length */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} SCI1SR2STR; +extern volatile SCI1SR2STR _SCI1SR2 @(REG_BASE + 0x000000D5UL); +#define SCI1SR2 _SCI1SR2.Byte +#define SCI1SR2_RAF _SCI1SR2.Bits.RAF +#define SCI1SR2_TXDIR _SCI1SR2.Bits.TXDIR +#define SCI1SR2_BRK13 _SCI1SR2.Bits.BRK13 + +#define SCI1SR2_RAF_MASK 1U +#define SCI1SR2_TXDIR_MASK 2U +#define SCI1SR2_BRK13_MASK 4U + + +/*** SCI1DRH - SCI 1 Data Register High; 0x000000D6 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte T8 :1; /* Transmit Bit 8 */ + byte R8 :1; /* Received Bit 8 */ + } Bits; +} SCI1DRHSTR; +extern volatile SCI1DRHSTR _SCI1DRH @(REG_BASE + 0x000000D6UL); +#define SCI1DRH _SCI1DRH.Byte +#define SCI1DRH_T8 _SCI1DRH.Bits.T8 +#define SCI1DRH_R8 _SCI1DRH.Bits.R8 + +#define SCI1DRH_T8_MASK 64U +#define SCI1DRH_R8_MASK 128U + + +/*** SCI1DRL - SCI 1 Data Register Low; 0x000000D7 ***/ +typedef union { + byte Byte; + struct { + byte R0_T0 :1; /* Received bit 0 or Transmit bit 0 */ + byte R1_T1 :1; /* Received bit 1 or Transmit bit 1 */ + byte R2_T2 :1; /* Received bit 2 or Transmit bit 2 */ + byte R3_T3 :1; /* Received bit 3 or Transmit bit 3 */ + byte R4_T4 :1; /* Received bit 4 or Transmit bit 4 */ + byte R5_T5 :1; /* Received bit 5 or Transmit bit 5 */ + byte R6_T6 :1; /* Received bit 6 or Transmit bit 6 */ + byte R7_T7 :1; /* Received bit 7 or Transmit bit 7 */ + } Bits; +} SCI1DRLSTR; +extern volatile SCI1DRLSTR _SCI1DRL @(REG_BASE + 0x000000D7UL); +#define SCI1DRL _SCI1DRL.Byte +#define SCI1DRL_R0_T0 _SCI1DRL.Bits.R0_T0 +#define SCI1DRL_R1_T1 _SCI1DRL.Bits.R1_T1 +#define SCI1DRL_R2_T2 _SCI1DRL.Bits.R2_T2 +#define SCI1DRL_R3_T3 _SCI1DRL.Bits.R3_T3 +#define SCI1DRL_R4_T4 _SCI1DRL.Bits.R4_T4 +#define SCI1DRL_R5_T5 _SCI1DRL.Bits.R5_T5 +#define SCI1DRL_R6_T6 _SCI1DRL.Bits.R6_T6 +#define SCI1DRL_R7_T7 _SCI1DRL.Bits.R7_T7 + +#define SCI1DRL_R0_T0_MASK 1U +#define SCI1DRL_R1_T1_MASK 2U +#define SCI1DRL_R2_T2_MASK 4U +#define SCI1DRL_R3_T3_MASK 8U +#define SCI1DRL_R4_T4_MASK 16U +#define SCI1DRL_R5_T5_MASK 32U +#define SCI1DRL_R6_T6_MASK 64U +#define SCI1DRL_R7_T7_MASK 128U + + +/*** SPI0CR1 - SPI 0 Control Register; 0x000000D8 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI Clock Phase Bit */ + byte CPOL :1; /* SPI Clock Polarity Bit */ + byte MSTR :1; /* SPI Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI Transmit Interrupt Enable */ + byte SPE :1; /* SPI System Enable Bit */ + byte SPIE :1; /* SPI Interrupt Enable Bit */ + } Bits; +} SPI0CR1STR; +extern volatile SPI0CR1STR _SPI0CR1 @(REG_BASE + 0x000000D8UL); +#define SPI0CR1 _SPI0CR1.Byte +#define SPI0CR1_LSBFE _SPI0CR1.Bits.LSBFE +#define SPI0CR1_SSOE _SPI0CR1.Bits.SSOE +#define SPI0CR1_CPHA _SPI0CR1.Bits.CPHA +#define SPI0CR1_CPOL _SPI0CR1.Bits.CPOL +#define SPI0CR1_MSTR _SPI0CR1.Bits.MSTR +#define SPI0CR1_SPTIE _SPI0CR1.Bits.SPTIE +#define SPI0CR1_SPE _SPI0CR1.Bits.SPE +#define SPI0CR1_SPIE _SPI0CR1.Bits.SPIE + +#define SPI0CR1_LSBFE_MASK 1U +#define SPI0CR1_SSOE_MASK 2U +#define SPI0CR1_CPHA_MASK 4U +#define SPI0CR1_CPOL_MASK 8U +#define SPI0CR1_MSTR_MASK 16U +#define SPI0CR1_SPTIE_MASK 32U +#define SPI0CR1_SPE_MASK 64U +#define SPI0CR1_SPIE_MASK 128U + + +/*** SPI0CR2 - SPI 0 Control Register 2; 0x000000D9 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPI0CR2STR; +extern volatile SPI0CR2STR _SPI0CR2 @(REG_BASE + 0x000000D9UL); +#define SPI0CR2 _SPI0CR2.Byte +#define SPI0CR2_SPC0 _SPI0CR2.Bits.SPC0 +#define SPI0CR2_SPISWAI _SPI0CR2.Bits.SPISWAI +#define SPI0CR2_BIDIROE _SPI0CR2.Bits.BIDIROE +#define SPI0CR2_MODFEN _SPI0CR2.Bits.MODFEN + +#define SPI0CR2_SPC0_MASK 1U +#define SPI0CR2_SPISWAI_MASK 2U +#define SPI0CR2_BIDIROE_MASK 8U +#define SPI0CR2_MODFEN_MASK 16U + + +/*** SPI0BR - SPI 0 Baud Rate Register; 0x000000DA ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI0BRSTR; +extern volatile SPI0BRSTR _SPI0BR @(REG_BASE + 0x000000DAUL); +#define SPI0BR _SPI0BR.Byte +#define SPI0BR_SPR0 _SPI0BR.Bits.SPR0 +#define SPI0BR_SPR1 _SPI0BR.Bits.SPR1 +#define SPI0BR_SPR2 _SPI0BR.Bits.SPR2 +#define SPI0BR_SPPR0 _SPI0BR.Bits.SPPR0 +#define SPI0BR_SPPR1 _SPI0BR.Bits.SPPR1 +#define SPI0BR_SPPR2 _SPI0BR.Bits.SPPR2 +#define SPI0BR_SPR _SPI0BR.MergedBits.grpSPR +#define SPI0BR_SPPR _SPI0BR.MergedBits.grpSPPR + +#define SPI0BR_SPR0_MASK 1U +#define SPI0BR_SPR1_MASK 2U +#define SPI0BR_SPR2_MASK 4U +#define SPI0BR_SPPR0_MASK 16U +#define SPI0BR_SPPR1_MASK 32U +#define SPI0BR_SPPR2_MASK 64U +#define SPI0BR_SPR_MASK 7U +#define SPI0BR_SPR_BITNUM 0U +#define SPI0BR_SPPR_MASK 112U +#define SPI0BR_SPPR_BITNUM 4U + + +/*** SPI0SR - SPI 0 Status Register; 0x000000DB ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI0SRSTR; +extern volatile SPI0SRSTR _SPI0SR @(REG_BASE + 0x000000DBUL); +#define SPI0SR _SPI0SR.Byte +#define SPI0SR_MODF _SPI0SR.Bits.MODF +#define SPI0SR_SPTEF _SPI0SR.Bits.SPTEF +#define SPI0SR_SPIF _SPI0SR.Bits.SPIF + +#define SPI0SR_MODF_MASK 16U +#define SPI0SR_SPTEF_MASK 32U +#define SPI0SR_SPIF_MASK 128U + + +/*** SPI0DR - SPI 0 Data Register; 0x000000DD ***/ +typedef union { + byte Byte; +} SPI0DRSTR; +extern volatile SPI0DRSTR _SPI0DR @(REG_BASE + 0x000000DDUL); +#define SPI0DR _SPI0DR.Byte + + +/*** IBAD - IIC Address Register; 0x000000E0 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte ADR1 :1; /* Slave Address Bit 1 */ + byte ADR2 :1; /* Slave Address Bit 2 */ + byte ADR3 :1; /* Slave Address Bit 3 */ + byte ADR4 :1; /* Slave Address Bit 4 */ + byte ADR5 :1; /* Slave Address Bit 5 */ + byte ADR6 :1; /* Slave Address Bit 6 */ + byte ADR7 :1; /* Slave Address Bit 7 */ + } Bits; + struct { + byte :1; + byte grpADR_1 :7; + } MergedBits; +} IBADSTR; +extern volatile IBADSTR _IBAD @(REG_BASE + 0x000000E0UL); +#define IBAD _IBAD.Byte +#define IBAD_ADR1 _IBAD.Bits.ADR1 +#define IBAD_ADR2 _IBAD.Bits.ADR2 +#define IBAD_ADR3 _IBAD.Bits.ADR3 +#define IBAD_ADR4 _IBAD.Bits.ADR4 +#define IBAD_ADR5 _IBAD.Bits.ADR5 +#define IBAD_ADR6 _IBAD.Bits.ADR6 +#define IBAD_ADR7 _IBAD.Bits.ADR7 +#define IBAD_ADR_1 _IBAD.MergedBits.grpADR_1 +#define IBAD_ADR IBAD_ADR_1 + +#define IBAD_ADR1_MASK 2U +#define IBAD_ADR2_MASK 4U +#define IBAD_ADR3_MASK 8U +#define IBAD_ADR4_MASK 16U +#define IBAD_ADR5_MASK 32U +#define IBAD_ADR6_MASK 64U +#define IBAD_ADR7_MASK 128U +#define IBAD_ADR_1_MASK 254U +#define IBAD_ADR_1_BITNUM 1U + + +/*** IBFD - IIC Frequency Divider Register; 0x000000E1 ***/ +typedef union { + byte Byte; + struct { + byte IBC0 :1; /* I-Bus Clock Rate 0 */ + byte IBC1 :1; /* I-Bus Clock Rate 1 */ + byte IBC2 :1; /* I-Bus Clock Rate 2 */ + byte IBC3 :1; /* I-Bus Clock Rate 3 */ + byte IBC4 :1; /* I-Bus Clock Rate 4 */ + byte IBC5 :1; /* I-Bus Clock Rate 5 */ + byte IBC6 :1; /* I-Bus Clock Rate 6 */ + byte IBC7 :1; /* I-Bus Clock Rate 7 */ + } Bits; +} IBFDSTR; +extern volatile IBFDSTR _IBFD @(REG_BASE + 0x000000E1UL); +#define IBFD _IBFD.Byte +#define IBFD_IBC0 _IBFD.Bits.IBC0 +#define IBFD_IBC1 _IBFD.Bits.IBC1 +#define IBFD_IBC2 _IBFD.Bits.IBC2 +#define IBFD_IBC3 _IBFD.Bits.IBC3 +#define IBFD_IBC4 _IBFD.Bits.IBC4 +#define IBFD_IBC5 _IBFD.Bits.IBC5 +#define IBFD_IBC6 _IBFD.Bits.IBC6 +#define IBFD_IBC7 _IBFD.Bits.IBC7 + +#define IBFD_IBC0_MASK 1U +#define IBFD_IBC1_MASK 2U +#define IBFD_IBC2_MASK 4U +#define IBFD_IBC3_MASK 8U +#define IBFD_IBC4_MASK 16U +#define IBFD_IBC5_MASK 32U +#define IBFD_IBC6_MASK 64U +#define IBFD_IBC7_MASK 128U + + +/*** IBCR - IIC Control Register; 0x000000E2 ***/ +typedef union { + byte Byte; + struct { + byte IBSWAI :1; /* I-Bus Interface Stop in WAIT mode */ + byte :1; + byte RSTA :1; /* Repeat Start */ + byte TXAK :1; /* Transmit Acknowledge enable */ + byte TX_RX :1; /* Transmit/Receive mode select bit */ + byte MS_SL :1; /* Master/Slave mode select bit */ + byte IBIE :1; /* I-Bus Interrupt Enable */ + byte IBEN :1; /* I-Bus Enable */ + } Bits; +} IBCRSTR; +extern volatile IBCRSTR _IBCR @(REG_BASE + 0x000000E2UL); +#define IBCR _IBCR.Byte +#define IBCR_IBSWAI _IBCR.Bits.IBSWAI +#define IBCR_RSTA _IBCR.Bits.RSTA +#define IBCR_TXAK _IBCR.Bits.TXAK +#define IBCR_TX_RX _IBCR.Bits.TX_RX +#define IBCR_MS_SL _IBCR.Bits.MS_SL +#define IBCR_IBIE _IBCR.Bits.IBIE +#define IBCR_IBEN _IBCR.Bits.IBEN + +#define IBCR_IBSWAI_MASK 1U +#define IBCR_RSTA_MASK 4U +#define IBCR_TXAK_MASK 8U +#define IBCR_TX_RX_MASK 16U +#define IBCR_MS_SL_MASK 32U +#define IBCR_IBIE_MASK 64U +#define IBCR_IBEN_MASK 128U + + +/*** IBSR - IIC Status Register; 0x000000E3 ***/ +typedef union { + byte Byte; + struct { + byte RXAK :1; /* Received Acknowledge */ + byte IBIF :1; /* I-Bus Interrupt */ + byte SRW :1; /* Slave Read/Write */ + byte :1; + byte IBAL :1; /* Arbitration Lost */ + byte IBB :1; /* Bus busy bit */ + byte IAAS :1; /* Addressed as a slave bit */ + byte TCF :1; /* Data transferring bit */ + } Bits; +} IBSRSTR; +extern volatile IBSRSTR _IBSR @(REG_BASE + 0x000000E3UL); +#define IBSR _IBSR.Byte +#define IBSR_RXAK _IBSR.Bits.RXAK +#define IBSR_IBIF _IBSR.Bits.IBIF +#define IBSR_SRW _IBSR.Bits.SRW +#define IBSR_IBAL _IBSR.Bits.IBAL +#define IBSR_IBB _IBSR.Bits.IBB +#define IBSR_IAAS _IBSR.Bits.IAAS +#define IBSR_TCF _IBSR.Bits.TCF + +#define IBSR_RXAK_MASK 1U +#define IBSR_IBIF_MASK 2U +#define IBSR_SRW_MASK 4U +#define IBSR_IBAL_MASK 16U +#define IBSR_IBB_MASK 32U +#define IBSR_IAAS_MASK 64U +#define IBSR_TCF_MASK 128U + + +/*** IBDR - IIC Data I/O Register; 0x000000E4 ***/ +typedef union { + byte Byte; + struct { + byte D0 :1; /* IIC Data Bit 0 */ + byte D1 :1; /* IIC Data Bit 1 */ + byte D2 :1; /* IIC Data Bit 2 */ + byte D3 :1; /* IIC Data Bit 3 */ + byte D4 :1; /* IIC Data Bit 4 */ + byte D5 :1; /* IIC Data Bit 5 */ + byte D6 :1; /* IIC Data Bit 6 */ + byte D7 :1; /* IIC Data Bit 7 */ + } Bits; +} IBDRSTR; +extern volatile IBDRSTR _IBDR @(REG_BASE + 0x000000E4UL); +#define IBDR _IBDR.Byte +#define IBDR_D0 _IBDR.Bits.D0 +#define IBDR_D1 _IBDR.Bits.D1 +#define IBDR_D2 _IBDR.Bits.D2 +#define IBDR_D3 _IBDR.Bits.D3 +#define IBDR_D4 _IBDR.Bits.D4 +#define IBDR_D5 _IBDR.Bits.D5 +#define IBDR_D6 _IBDR.Bits.D6 +#define IBDR_D7 _IBDR.Bits.D7 + +#define IBDR_D0_MASK 1U +#define IBDR_D1_MASK 2U +#define IBDR_D2_MASK 4U +#define IBDR_D3_MASK 8U +#define IBDR_D4_MASK 16U +#define IBDR_D5_MASK 32U +#define IBDR_D6_MASK 64U +#define IBDR_D7_MASK 128U + + +/*** SPI1CR1 - SPI 1 Control Register; 0x000000F0 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI Clock Phase Bit */ + byte CPOL :1; /* SPI Clock Polarity Bit */ + byte MSTR :1; /* SPI Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI Transmit Interrupt Enable */ + byte SPE :1; /* SPI System Enable Bit */ + byte SPIE :1; /* SPI Interrupt Enable Bit */ + } Bits; +} SPI1CR1STR; +extern volatile SPI1CR1STR _SPI1CR1 @(REG_BASE + 0x000000F0UL); +#define SPI1CR1 _SPI1CR1.Byte +#define SPI1CR1_LSBFE _SPI1CR1.Bits.LSBFE +#define SPI1CR1_SSOE _SPI1CR1.Bits.SSOE +#define SPI1CR1_CPHA _SPI1CR1.Bits.CPHA +#define SPI1CR1_CPOL _SPI1CR1.Bits.CPOL +#define SPI1CR1_MSTR _SPI1CR1.Bits.MSTR +#define SPI1CR1_SPTIE _SPI1CR1.Bits.SPTIE +#define SPI1CR1_SPE _SPI1CR1.Bits.SPE +#define SPI1CR1_SPIE _SPI1CR1.Bits.SPIE + +#define SPI1CR1_LSBFE_MASK 1U +#define SPI1CR1_SSOE_MASK 2U +#define SPI1CR1_CPHA_MASK 4U +#define SPI1CR1_CPOL_MASK 8U +#define SPI1CR1_MSTR_MASK 16U +#define SPI1CR1_SPTIE_MASK 32U +#define SPI1CR1_SPE_MASK 64U +#define SPI1CR1_SPIE_MASK 128U + + +/*** SPI1CR2 - SPI 1 Control Register 2; 0x000000F1 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPI1CR2STR; +extern volatile SPI1CR2STR _SPI1CR2 @(REG_BASE + 0x000000F1UL); +#define SPI1CR2 _SPI1CR2.Byte +#define SPI1CR2_SPC0 _SPI1CR2.Bits.SPC0 +#define SPI1CR2_SPISWAI _SPI1CR2.Bits.SPISWAI +#define SPI1CR2_BIDIROE _SPI1CR2.Bits.BIDIROE +#define SPI1CR2_MODFEN _SPI1CR2.Bits.MODFEN + +#define SPI1CR2_SPC0_MASK 1U +#define SPI1CR2_SPISWAI_MASK 2U +#define SPI1CR2_BIDIROE_MASK 8U +#define SPI1CR2_MODFEN_MASK 16U + + +/*** SPI1BR - SPI 1 Baud Rate Register; 0x000000F2 ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI1BRSTR; +extern volatile SPI1BRSTR _SPI1BR @(REG_BASE + 0x000000F2UL); +#define SPI1BR _SPI1BR.Byte +#define SPI1BR_SPR0 _SPI1BR.Bits.SPR0 +#define SPI1BR_SPR1 _SPI1BR.Bits.SPR1 +#define SPI1BR_SPR2 _SPI1BR.Bits.SPR2 +#define SPI1BR_SPPR0 _SPI1BR.Bits.SPPR0 +#define SPI1BR_SPPR1 _SPI1BR.Bits.SPPR1 +#define SPI1BR_SPPR2 _SPI1BR.Bits.SPPR2 +#define SPI1BR_SPR _SPI1BR.MergedBits.grpSPR +#define SPI1BR_SPPR _SPI1BR.MergedBits.grpSPPR + +#define SPI1BR_SPR0_MASK 1U +#define SPI1BR_SPR1_MASK 2U +#define SPI1BR_SPR2_MASK 4U +#define SPI1BR_SPPR0_MASK 16U +#define SPI1BR_SPPR1_MASK 32U +#define SPI1BR_SPPR2_MASK 64U +#define SPI1BR_SPR_MASK 7U +#define SPI1BR_SPR_BITNUM 0U +#define SPI1BR_SPPR_MASK 112U +#define SPI1BR_SPPR_BITNUM 4U + + +/*** SPI1SR - SPI 1 Status Register; 0x000000F3 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI1SRSTR; +extern volatile SPI1SRSTR _SPI1SR @(REG_BASE + 0x000000F3UL); +#define SPI1SR _SPI1SR.Byte +#define SPI1SR_MODF _SPI1SR.Bits.MODF +#define SPI1SR_SPTEF _SPI1SR.Bits.SPTEF +#define SPI1SR_SPIF _SPI1SR.Bits.SPIF + +#define SPI1SR_MODF_MASK 16U +#define SPI1SR_SPTEF_MASK 32U +#define SPI1SR_SPIF_MASK 128U + + +/*** SPI1DR - SPI 1 Data Register; 0x000000F5 ***/ +typedef union { + byte Byte; +} SPI1DRSTR; +extern volatile SPI1DRSTR _SPI1DR @(REG_BASE + 0x000000F5UL); +#define SPI1DR _SPI1DR.Byte + + +/*** SPI2CR1 - SPI 2 Control Register; 0x000000F8 ***/ +typedef union { + byte Byte; + struct { + byte LSBFE :1; /* SPI LSB-First Enable */ + byte SSOE :1; /* Slave Select Output Enable */ + byte CPHA :1; /* SPI Clock Phase Bit */ + byte CPOL :1; /* SPI Clock Polarity Bit */ + byte MSTR :1; /* SPI Master/Slave Mode Select Bit */ + byte SPTIE :1; /* SPI Transmit Interrupt Enable */ + byte SPE :1; /* SPI System Enable Bit */ + byte SPIE :1; /* SPI Interrupt Enable Bit */ + } Bits; +} SPI2CR1STR; +extern volatile SPI2CR1STR _SPI2CR1 @(REG_BASE + 0x000000F8UL); +#define SPI2CR1 _SPI2CR1.Byte +#define SPI2CR1_LSBFE _SPI2CR1.Bits.LSBFE +#define SPI2CR1_SSOE _SPI2CR1.Bits.SSOE +#define SPI2CR1_CPHA _SPI2CR1.Bits.CPHA +#define SPI2CR1_CPOL _SPI2CR1.Bits.CPOL +#define SPI2CR1_MSTR _SPI2CR1.Bits.MSTR +#define SPI2CR1_SPTIE _SPI2CR1.Bits.SPTIE +#define SPI2CR1_SPE _SPI2CR1.Bits.SPE +#define SPI2CR1_SPIE _SPI2CR1.Bits.SPIE + +#define SPI2CR1_LSBFE_MASK 1U +#define SPI2CR1_SSOE_MASK 2U +#define SPI2CR1_CPHA_MASK 4U +#define SPI2CR1_CPOL_MASK 8U +#define SPI2CR1_MSTR_MASK 16U +#define SPI2CR1_SPTIE_MASK 32U +#define SPI2CR1_SPE_MASK 64U +#define SPI2CR1_SPIE_MASK 128U + + +/*** SPI2CR2 - SPI 2 Control Register 2; 0x000000F9 ***/ +typedef union { + byte Byte; + struct { + byte SPC0 :1; /* Serial Pin Control Bit 0 */ + byte SPISWAI :1; /* SPI Stop in Wait Mode Bit */ + byte :1; + byte BIDIROE :1; /* Output enable in the Bidirectional mode of operation */ + byte MODFEN :1; /* Mode Fault Enable Bit */ + byte :1; + byte :1; + byte :1; + } Bits; +} SPI2CR2STR; +extern volatile SPI2CR2STR _SPI2CR2 @(REG_BASE + 0x000000F9UL); +#define SPI2CR2 _SPI2CR2.Byte +#define SPI2CR2_SPC0 _SPI2CR2.Bits.SPC0 +#define SPI2CR2_SPISWAI _SPI2CR2.Bits.SPISWAI +#define SPI2CR2_BIDIROE _SPI2CR2.Bits.BIDIROE +#define SPI2CR2_MODFEN _SPI2CR2.Bits.MODFEN + +#define SPI2CR2_SPC0_MASK 1U +#define SPI2CR2_SPISWAI_MASK 2U +#define SPI2CR2_BIDIROE_MASK 8U +#define SPI2CR2_MODFEN_MASK 16U + + +/*** SPI2BR - SPI 2 Baud Rate Register; 0x000000FA ***/ +typedef union { + byte Byte; + struct { + byte SPR0 :1; /* SPI Baud Rate Selection Bit 0 */ + byte SPR1 :1; /* SPI Baud Rate Selection Bit 1 */ + byte SPR2 :1; /* SPI Baud Rate Selection Bit 2 */ + byte :1; + byte SPPR0 :1; /* SPI Baud Rate Preselection Bits 0 */ + byte SPPR1 :1; /* SPI Baud Rate Preselection Bits 1 */ + byte SPPR2 :1; /* SPI Baud Rate Preselection Bits 2 */ + byte :1; + } Bits; + struct { + byte grpSPR :3; + byte :1; + byte grpSPPR :3; + byte :1; + } MergedBits; +} SPI2BRSTR; +extern volatile SPI2BRSTR _SPI2BR @(REG_BASE + 0x000000FAUL); +#define SPI2BR _SPI2BR.Byte +#define SPI2BR_SPR0 _SPI2BR.Bits.SPR0 +#define SPI2BR_SPR1 _SPI2BR.Bits.SPR1 +#define SPI2BR_SPR2 _SPI2BR.Bits.SPR2 +#define SPI2BR_SPPR0 _SPI2BR.Bits.SPPR0 +#define SPI2BR_SPPR1 _SPI2BR.Bits.SPPR1 +#define SPI2BR_SPPR2 _SPI2BR.Bits.SPPR2 +#define SPI2BR_SPR _SPI2BR.MergedBits.grpSPR +#define SPI2BR_SPPR _SPI2BR.MergedBits.grpSPPR + +#define SPI2BR_SPR0_MASK 1U +#define SPI2BR_SPR1_MASK 2U +#define SPI2BR_SPR2_MASK 4U +#define SPI2BR_SPPR0_MASK 16U +#define SPI2BR_SPPR1_MASK 32U +#define SPI2BR_SPPR2_MASK 64U +#define SPI2BR_SPR_MASK 7U +#define SPI2BR_SPR_BITNUM 0U +#define SPI2BR_SPPR_MASK 112U +#define SPI2BR_SPPR_BITNUM 4U + + +/*** SPI2SR - SPI 2 Status Register; 0x000000FB ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte MODF :1; /* Mode Fault Flag */ + byte SPTEF :1; /* SPI Transmit Empty Interrupt Flag */ + byte :1; + byte SPIF :1; /* SPIF Receive Interrupt Flag */ + } Bits; +} SPI2SRSTR; +extern volatile SPI2SRSTR _SPI2SR @(REG_BASE + 0x000000FBUL); +#define SPI2SR _SPI2SR.Byte +#define SPI2SR_MODF _SPI2SR.Bits.MODF +#define SPI2SR_SPTEF _SPI2SR.Bits.SPTEF +#define SPI2SR_SPIF _SPI2SR.Bits.SPIF + +#define SPI2SR_MODF_MASK 16U +#define SPI2SR_SPTEF_MASK 32U +#define SPI2SR_SPIF_MASK 128U + + +/*** SPI2DR - SPI 2 Data Register; 0x000000FD ***/ +typedef union { + byte Byte; +} SPI2DRSTR; +extern volatile SPI2DRSTR _SPI2DR @(REG_BASE + 0x000000FDUL); +#define SPI2DR _SPI2DR.Byte + + +/*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***/ +typedef union { + byte Byte; + struct { + byte FDIV0 :1; /* Flash Clock Divider Bit 0 */ + byte FDIV1 :1; /* Flash Clock Divider Bit 1 */ + byte FDIV2 :1; /* Flash Clock Divider Bit 2 */ + byte FDIV3 :1; /* Flash Clock Divider Bit 3 */ + byte FDIV4 :1; /* Flash Clock Divider Bit 4 */ + byte FDIV5 :1; /* Flash Clock Divider Bit 5 */ + byte PRDIV8 :1; /* Enable Prescaler by 8 */ + byte FDIVLD :1; /* Flash Clock Divider Loaded */ + } Bits; + struct { + byte grpFDIV :6; + byte grpPRDIV_8 :1; + byte :1; + } MergedBits; +} FCLKDIVSTR; +extern volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100UL); +#define FCLKDIV _FCLKDIV.Byte +#define FCLKDIV_FDIV0 _FCLKDIV.Bits.FDIV0 +#define FCLKDIV_FDIV1 _FCLKDIV.Bits.FDIV1 +#define FCLKDIV_FDIV2 _FCLKDIV.Bits.FDIV2 +#define FCLKDIV_FDIV3 _FCLKDIV.Bits.FDIV3 +#define FCLKDIV_FDIV4 _FCLKDIV.Bits.FDIV4 +#define FCLKDIV_FDIV5 _FCLKDIV.Bits.FDIV5 +#define FCLKDIV_PRDIV8 _FCLKDIV.Bits.PRDIV8 +#define FCLKDIV_FDIVLD _FCLKDIV.Bits.FDIVLD +#define FCLKDIV_FDIV _FCLKDIV.MergedBits.grpFDIV + +#define FCLKDIV_FDIV0_MASK 1U +#define FCLKDIV_FDIV1_MASK 2U +#define FCLKDIV_FDIV2_MASK 4U +#define FCLKDIV_FDIV3_MASK 8U +#define FCLKDIV_FDIV4_MASK 16U +#define FCLKDIV_FDIV5_MASK 32U +#define FCLKDIV_PRDIV8_MASK 64U +#define FCLKDIV_FDIVLD_MASK 128U +#define FCLKDIV_FDIV_MASK 63U +#define FCLKDIV_FDIV_BITNUM 0U + + +/*** FSEC - Flash Security Register; 0x00000101 ***/ +typedef union { + byte Byte; + struct { + byte SEC0 :1; /* Memory security bit 0 */ + byte SEC1 :1; /* Memory security bit 1 */ + byte NV2 :1; /* Non Volatile flag bit 2 */ + byte NV3 :1; /* Non Volatile flag bit 3 */ + byte NV4 :1; /* Non Volatile flag bit 4 */ + byte NV5 :1; /* Non Volatile flag bit 5 */ + byte KEYEN0 :1; /* Backdoor Key Security Enable Bit 0 */ + byte KEYEN1 :1; /* Backdoor Key Security Enable Bit 1 */ + } Bits; + struct { + byte grpSEC :2; + byte grpNV_2 :4; + byte grpKEYEN :2; + } MergedBits; +} FSECSTR; +extern volatile FSECSTR _FSEC @(REG_BASE + 0x00000101UL); +#define FSEC _FSEC.Byte +#define FSEC_SEC0 _FSEC.Bits.SEC0 +#define FSEC_SEC1 _FSEC.Bits.SEC1 +#define FSEC_NV2 _FSEC.Bits.NV2 +#define FSEC_NV3 _FSEC.Bits.NV3 +#define FSEC_NV4 _FSEC.Bits.NV4 +#define FSEC_NV5 _FSEC.Bits.NV5 +#define FSEC_KEYEN0 _FSEC.Bits.KEYEN0 +#define FSEC_KEYEN1 _FSEC.Bits.KEYEN1 +#define FSEC_SEC _FSEC.MergedBits.grpSEC +#define FSEC_NV_2 _FSEC.MergedBits.grpNV_2 +#define FSEC_KEYEN _FSEC.MergedBits.grpKEYEN +#define FSEC_NV FSEC_NV_2 + +#define FSEC_SEC0_MASK 1U +#define FSEC_SEC1_MASK 2U +#define FSEC_NV2_MASK 4U +#define FSEC_NV3_MASK 8U +#define FSEC_NV4_MASK 16U +#define FSEC_NV5_MASK 32U +#define FSEC_KEYEN0_MASK 64U +#define FSEC_KEYEN1_MASK 128U +#define FSEC_SEC_MASK 3U +#define FSEC_SEC_BITNUM 0U +#define FSEC_NV_2_MASK 60U +#define FSEC_NV_2_BITNUM 2U +#define FSEC_KEYEN_MASK 192U +#define FSEC_KEYEN_BITNUM 6U + + +/*** FCNFG - Flash Configuration Register; 0x00000103 ***/ +typedef union { + byte Byte; + struct { + byte BKSEL0 :1; /* Register bank select 0 */ + byte BKSEL1 :1; /* Register bank select 1 */ + byte :1; + byte :1; + byte :1; + byte KEYACC :1; /* Enable Security Key Writing */ + byte CCIE :1; /* Command Complete Interrupt Enable */ + byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ + } Bits; + struct { + byte grpBKSEL :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} FCNFGSTR; +extern volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103UL); +#define FCNFG _FCNFG.Byte +#define FCNFG_BKSEL0 _FCNFG.Bits.BKSEL0 +#define FCNFG_BKSEL1 _FCNFG.Bits.BKSEL1 +#define FCNFG_KEYACC _FCNFG.Bits.KEYACC +#define FCNFG_CCIE _FCNFG.Bits.CCIE +#define FCNFG_CBEIE _FCNFG.Bits.CBEIE +#define FCNFG_BKSEL _FCNFG.MergedBits.grpBKSEL + +#define FCNFG_BKSEL0_MASK 1U +#define FCNFG_BKSEL1_MASK 2U +#define FCNFG_KEYACC_MASK 32U +#define FCNFG_CCIE_MASK 64U +#define FCNFG_CBEIE_MASK 128U +#define FCNFG_BKSEL_MASK 3U +#define FCNFG_BKSEL_BITNUM 0U + + +/*** FPROT - Flash Protection Register; 0x00000104 ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} FPROTSTR; +extern volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104UL); +#define FPROT _FPROT.Byte +#define FPROT_FPLS0 _FPROT.Bits.FPLS0 +#define FPROT_FPLS1 _FPROT.Bits.FPLS1 +#define FPROT_FPLDIS _FPROT.Bits.FPLDIS +#define FPROT_FPHS0 _FPROT.Bits.FPHS0 +#define FPROT_FPHS1 _FPROT.Bits.FPHS1 +#define FPROT_FPHDIS _FPROT.Bits.FPHDIS +#define FPROT_NV6 _FPROT.Bits.NV6 +#define FPROT_FPOPEN _FPROT.Bits.FPOPEN +#define FPROT_FPLS _FPROT.MergedBits.grpFPLS +#define FPROT_FPHS _FPROT.MergedBits.grpFPHS + +#define FPROT_FPLS0_MASK 1U +#define FPROT_FPLS1_MASK 2U +#define FPROT_FPLDIS_MASK 4U +#define FPROT_FPHS0_MASK 8U +#define FPROT_FPHS1_MASK 16U +#define FPROT_FPHDIS_MASK 32U +#define FPROT_NV6_MASK 64U +#define FPROT_FPOPEN_MASK 128U +#define FPROT_FPLS_MASK 3U +#define FPROT_FPLS_BITNUM 0U +#define FPROT_FPHS_MASK 24U +#define FPROT_FPHS_BITNUM 3U + + +/*** FSTAT - Flash Status Register; 0x00000105 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BLANK :1; /* Blank Verify Flag */ + byte :1; + byte ACCERR :1; /* Access error */ + byte PVIOL :1; /* Protection violation */ + byte CCIF :1; /* Command Complete Interrupt Flag */ + byte CBEIF :1; /* Command Buffers Empty Interrupt Flag */ + } Bits; +} FSTATSTR; +extern volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105UL); +#define FSTAT _FSTAT.Byte +#define FSTAT_BLANK _FSTAT.Bits.BLANK +#define FSTAT_ACCERR _FSTAT.Bits.ACCERR +#define FSTAT_PVIOL _FSTAT.Bits.PVIOL +#define FSTAT_CCIF _FSTAT.Bits.CCIF +#define FSTAT_CBEIF _FSTAT.Bits.CBEIF + +#define FSTAT_BLANK_MASK 4U +#define FSTAT_ACCERR_MASK 16U +#define FSTAT_PVIOL_MASK 32U +#define FSTAT_CCIF_MASK 64U +#define FSTAT_CBEIF_MASK 128U + + +/*** FCMD - Flash Command Buffer and Register; 0x00000106 ***/ +typedef union { + byte Byte; + struct { + byte CMDB0 :1; /* NVM User Mode Command Bit 0 */ + byte :1; + byte CMDB2 :1; /* NVM User Mode Command Bit 2 */ + byte :1; + byte :1; + byte CMDB5 :1; /* NVM User Mode Command Bit 5 */ + byte CMDB6 :1; /* NVM User Mode Command Bit 6 */ + byte :1; + } Bits; + struct { + byte grpCMDB :1; + byte :1; + byte grpCMDB_2 :1; + byte :1; + byte :1; + byte grpCMDB_5 :2; + byte :1; + } MergedBits; +} FCMDSTR; +extern volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106UL); +#define FCMD _FCMD.Byte +#define FCMD_CMDB0 _FCMD.Bits.CMDB0 +#define FCMD_CMDB2 _FCMD.Bits.CMDB2 +#define FCMD_CMDB5 _FCMD.Bits.CMDB5 +#define FCMD_CMDB6 _FCMD.Bits.CMDB6 +#define FCMD_CMDB_5 _FCMD.MergedBits.grpCMDB_5 +#define FCMD_CMDB FCMD_CMDB_5 + +#define FCMD_CMDB0_MASK 1U +#define FCMD_CMDB2_MASK 4U +#define FCMD_CMDB5_MASK 32U +#define FCMD_CMDB6_MASK 64U +#define FCMD_CMDB_5_MASK 96U +#define FCMD_CMDB_5_BITNUM 5U + + +/*** ECLKDIV - EEPROM Clock Divider Register; 0x00000110 ***/ +typedef union { + byte Byte; + struct { + byte EDIV0 :1; /* EEPROM Clock Divider 0 */ + byte EDIV1 :1; /* EEPROM Clock Divider 1 */ + byte EDIV2 :1; /* EEPROM Clock Divider 2 */ + byte EDIV3 :1; /* EEPROM Clock Divider 3 */ + byte EDIV4 :1; /* EEPROM Clock Divider 4 */ + byte EDIV5 :1; /* EEPROM Clock Divider 5 */ + byte PRDIV8 :1; /* Enable Prescaler by 8 */ + byte EDIVLD :1; /* EEPROM Clock Divider Loaded */ + } Bits; + struct { + byte grpEDIV :6; + byte grpPRDIV_8 :1; + byte :1; + } MergedBits; +} ECLKDIVSTR; +extern volatile ECLKDIVSTR _ECLKDIV @(REG_BASE + 0x00000110UL); +#define ECLKDIV _ECLKDIV.Byte +#define ECLKDIV_EDIV0 _ECLKDIV.Bits.EDIV0 +#define ECLKDIV_EDIV1 _ECLKDIV.Bits.EDIV1 +#define ECLKDIV_EDIV2 _ECLKDIV.Bits.EDIV2 +#define ECLKDIV_EDIV3 _ECLKDIV.Bits.EDIV3 +#define ECLKDIV_EDIV4 _ECLKDIV.Bits.EDIV4 +#define ECLKDIV_EDIV5 _ECLKDIV.Bits.EDIV5 +#define ECLKDIV_PRDIV8 _ECLKDIV.Bits.PRDIV8 +#define ECLKDIV_EDIVLD _ECLKDIV.Bits.EDIVLD +#define ECLKDIV_EDIV _ECLKDIV.MergedBits.grpEDIV + +#define ECLKDIV_EDIV0_MASK 1U +#define ECLKDIV_EDIV1_MASK 2U +#define ECLKDIV_EDIV2_MASK 4U +#define ECLKDIV_EDIV3_MASK 8U +#define ECLKDIV_EDIV4_MASK 16U +#define ECLKDIV_EDIV5_MASK 32U +#define ECLKDIV_PRDIV8_MASK 64U +#define ECLKDIV_EDIVLD_MASK 128U +#define ECLKDIV_EDIV_MASK 63U +#define ECLKDIV_EDIV_BITNUM 0U + + +/*** ECNFG - EEPROM Configuration Register; 0x00000113 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte CCIE :1; /* Command Complete Interrupt Enable */ + byte CBEIE :1; /* Command Buffers Empty Interrupt Enable */ + } Bits; +} ECNFGSTR; +extern volatile ECNFGSTR _ECNFG @(REG_BASE + 0x00000113UL); +#define ECNFG _ECNFG.Byte +#define ECNFG_CCIE _ECNFG.Bits.CCIE +#define ECNFG_CBEIE _ECNFG.Bits.CBEIE + +#define ECNFG_CCIE_MASK 64U +#define ECNFG_CBEIE_MASK 128U + + +/*** EPROT - EEPROM Protection Register; 0x00000114 ***/ +typedef union { + byte Byte; + struct { + byte EP0 :1; /* EEPROM Protection address size 0 */ + byte EP1 :1; /* EEPROM Protection address size 1 */ + byte EP2 :1; /* EEPROM Protection address size 2 */ + byte EPDIS :1; /* EEPROM Protection disable */ + byte NV4 :1; /* Non Volatile Flag Bit 4 */ + byte NV5 :1; /* Non Volatile Flag Bit 5 */ + byte NV6 :1; /* Non Volatile Flag Bit 6 */ + byte EPOPEN :1; /* Opens the EEPROM block or a subsection of it for program or erase */ + } Bits; + struct { + byte grpEP :3; + byte :1; + byte grpNV_4 :3; + byte :1; + } MergedBits; +} EPROTSTR; +extern volatile EPROTSTR _EPROT @(REG_BASE + 0x00000114UL); +#define EPROT _EPROT.Byte +#define EPROT_EP0 _EPROT.Bits.EP0 +#define EPROT_EP1 _EPROT.Bits.EP1 +#define EPROT_EP2 _EPROT.Bits.EP2 +#define EPROT_EPDIS _EPROT.Bits.EPDIS +#define EPROT_NV4 _EPROT.Bits.NV4 +#define EPROT_NV5 _EPROT.Bits.NV5 +#define EPROT_NV6 _EPROT.Bits.NV6 +#define EPROT_EPOPEN _EPROT.Bits.EPOPEN +#define EPROT_EP _EPROT.MergedBits.grpEP +#define EPROT_NV_4 _EPROT.MergedBits.grpNV_4 +#define EPROT_NV EPROT_NV_4 + +#define EPROT_EP0_MASK 1U +#define EPROT_EP1_MASK 2U +#define EPROT_EP2_MASK 4U +#define EPROT_EPDIS_MASK 8U +#define EPROT_NV4_MASK 16U +#define EPROT_NV5_MASK 32U +#define EPROT_NV6_MASK 64U +#define EPROT_EPOPEN_MASK 128U +#define EPROT_EP_MASK 7U +#define EPROT_EP_BITNUM 0U +#define EPROT_NV_4_MASK 112U +#define EPROT_NV_4_BITNUM 4U + + +/*** ESTAT - EEPROM Status Register; 0x00000115 ***/ +typedef union { + byte Byte; + struct { + byte :1; + byte :1; + byte BLANK :1; /* Blank Verify Flag */ + byte :1; + byte ACCERR :1; /* Access error */ + byte PVIOL :1; /* Protection violation */ + byte CCIF :1; /* Command Complete Interrupt Flag */ + byte CBEIF :1; /* Command Buffer Empty Interrupt Flag */ + } Bits; +} ESTATSTR; +extern volatile ESTATSTR _ESTAT @(REG_BASE + 0x00000115UL); +#define ESTAT _ESTAT.Byte +#define ESTAT_BLANK _ESTAT.Bits.BLANK +#define ESTAT_ACCERR _ESTAT.Bits.ACCERR +#define ESTAT_PVIOL _ESTAT.Bits.PVIOL +#define ESTAT_CCIF _ESTAT.Bits.CCIF +#define ESTAT_CBEIF _ESTAT.Bits.CBEIF + +#define ESTAT_BLANK_MASK 4U +#define ESTAT_ACCERR_MASK 16U +#define ESTAT_PVIOL_MASK 32U +#define ESTAT_CCIF_MASK 64U +#define ESTAT_CBEIF_MASK 128U + + +/*** ECMD - EEPROM Command Buffer and Register; 0x00000116 ***/ +typedef union { + byte Byte; + struct { + byte CMDB0 :1; /* EEPROM User Mode Command 0 */ + byte :1; + byte CMDB2 :1; /* EEPROM User Mode Command 2 */ + byte :1; + byte :1; + byte CMDB5 :1; /* EEPROM User Mode Command 5 */ + byte CMDB6 :1; /* EEPROM User Mode Command 6 */ + byte :1; + } Bits; + struct { + byte grpCMDB :1; + byte :1; + byte grpCMDB_2 :1; + byte :1; + byte :1; + byte grpCMDB_5 :2; + byte :1; + } MergedBits; +} ECMDSTR; +extern volatile ECMDSTR _ECMD @(REG_BASE + 0x00000116UL); +#define ECMD _ECMD.Byte +#define ECMD_CMDB0 _ECMD.Bits.CMDB0 +#define ECMD_CMDB2 _ECMD.Bits.CMDB2 +#define ECMD_CMDB5 _ECMD.Bits.CMDB5 +#define ECMD_CMDB6 _ECMD.Bits.CMDB6 +#define ECMD_CMDB_5 _ECMD.MergedBits.grpCMDB_5 +#define ECMD_CMDB ECMD_CMDB_5 + +#define ECMD_CMDB0_MASK 1U +#define ECMD_CMDB2_MASK 4U +#define ECMD_CMDB5_MASK 32U +#define ECMD_CMDB6_MASK 64U +#define ECMD_CMDB_5_MASK 96U +#define ECMD_CMDB_5_BITNUM 5U + + +/*** ATD1CTL23 - ATD 1 Control Register 23; 0x00000122 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1CTL2 - ATD 1 Control Register 2; 0x00000122 ***/ + union { + byte Byte; + struct { + byte ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */ + byte ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */ + byte ETRIGE :1; /* External Trigger Mode enable */ + byte ETRIGP :1; /* External Trigger Polarity */ + byte ETRIGLE :1; /* External Trigger Level/Edge control */ + byte AWAI :1; /* ATD Power Down in Wait Mode */ + byte AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ + byte ADPU :1; /* ATD Disable / Power Down */ + } Bits; + } ATD1CTL2STR; + #define ATD1CTL2 _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Byte + #define ATD1CTL2_ASCIF _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIF + #define ATD1CTL2_ASCIE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ASCIE + #define ATD1CTL2_ETRIGE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGE + #define ATD1CTL2_ETRIGP _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGP + #define ATD1CTL2_ETRIGLE _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ETRIGLE + #define ATD1CTL2_AWAI _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AWAI + #define ATD1CTL2_AFFC _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.AFFC + #define ATD1CTL2_ADPU _ATD1CTL23.Overlap_STR.ATD1CTL2STR.Bits.ADPU + + #define ATD1CTL2_ASCIF_MASK 1U + #define ATD1CTL2_ASCIE_MASK 2U + #define ATD1CTL2_ETRIGE_MASK 4U + #define ATD1CTL2_ETRIGP_MASK 8U + #define ATD1CTL2_ETRIGLE_MASK 16U + #define ATD1CTL2_AWAI_MASK 32U + #define ATD1CTL2_AFFC_MASK 64U + #define ATD1CTL2_ADPU_MASK 128U + + + /*** ATD1CTL3 - ATD 1 Control Register 3; 0x00000123 ***/ + union { + byte Byte; + struct { + byte FRZ0 :1; /* Background Debug Freeze Enable Bit 0 */ + byte FRZ1 :1; /* Background Debug Freeze Enable Bit 1 */ + byte FIFO :1; /* Result Register FIFO Mode */ + byte S1C :1; /* Conversion Sequence Length 1 */ + byte S2C :1; /* Conversion Sequence Length 2 */ + byte S4C :1; /* Conversion Sequence Length 4 */ + byte S8C :1; /* Conversion Sequence Length 8 */ + byte :1; + } Bits; + struct { + byte grpFRZ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATD1CTL3STR; + #define ATD1CTL3 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Byte + #define ATD1CTL3_FRZ0 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ0 + #define ATD1CTL3_FRZ1 _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FRZ1 + #define ATD1CTL3_FIFO _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.FIFO + #define ATD1CTL3_S1C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S1C + #define ATD1CTL3_S2C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S2C + #define ATD1CTL3_S4C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S4C + #define ATD1CTL3_S8C _ATD1CTL23.Overlap_STR.ATD1CTL3STR.Bits.S8C + #define ATD1CTL3_FRZ _ATD1CTL23.Overlap_STR.ATD1CTL3STR.MergedBits.grpFRZ + + #define ATD1CTL3_FRZ0_MASK 1U + #define ATD1CTL3_FRZ1_MASK 2U + #define ATD1CTL3_FIFO_MASK 4U + #define ATD1CTL3_S1C_MASK 8U + #define ATD1CTL3_S2C_MASK 16U + #define ATD1CTL3_S4C_MASK 32U + #define ATD1CTL3_S8C_MASK 64U + #define ATD1CTL3_FRZ_MASK 3U + #define ATD1CTL3_FRZ_BITNUM 0U + + } Overlap_STR; + + struct { + word FRZ0 :1; /* Background Debug Freeze Enable Bit 0 */ + word FRZ1 :1; /* Background Debug Freeze Enable Bit 1 */ + word FIFO :1; /* Result Register FIFO Mode */ + word S1C :1; /* Conversion Sequence Length 1 */ + word S2C :1; /* Conversion Sequence Length 2 */ + word S4C :1; /* Conversion Sequence Length 4 */ + word S8C :1; /* Conversion Sequence Length 8 */ + word :1; + word ASCIF :1; /* ATD 1 Sequence Complete Interrupt Flag */ + word ASCIE :1; /* ATD 1 Sequence Complete Interrupt Enable */ + word ETRIGE :1; /* External Trigger Mode enable */ + word ETRIGP :1; /* External Trigger Polarity */ + word ETRIGLE :1; /* External Trigger Level/Edge control */ + word AWAI :1; /* ATD Power Down in Wait Mode */ + word AFFC :1; /* ATD Fast Conversion Complete Flag Clear */ + word ADPU :1; /* ATD Disable / Power Down */ + } Bits; + struct { + word grpFRZ :2; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + } MergedBits; +} ATD1CTL23STR; +extern volatile ATD1CTL23STR _ATD1CTL23 @(REG_BASE + 0x00000122UL); +#define ATD1CTL23 _ATD1CTL23.Word +#define ATD1CTL23_FRZ0 _ATD1CTL23.Bits.FRZ0 +#define ATD1CTL23_FRZ1 _ATD1CTL23.Bits.FRZ1 +#define ATD1CTL23_FIFO _ATD1CTL23.Bits.FIFO +#define ATD1CTL23_S1C _ATD1CTL23.Bits.S1C +#define ATD1CTL23_S2C _ATD1CTL23.Bits.S2C +#define ATD1CTL23_S4C _ATD1CTL23.Bits.S4C +#define ATD1CTL23_S8C _ATD1CTL23.Bits.S8C +#define ATD1CTL23_ASCIF _ATD1CTL23.Bits.ASCIF +#define ATD1CTL23_ASCIE _ATD1CTL23.Bits.ASCIE +#define ATD1CTL23_ETRIGE _ATD1CTL23.Bits.ETRIGE +#define ATD1CTL23_ETRIGP _ATD1CTL23.Bits.ETRIGP +#define ATD1CTL23_ETRIGLE _ATD1CTL23.Bits.ETRIGLE +#define ATD1CTL23_AWAI _ATD1CTL23.Bits.AWAI +#define ATD1CTL23_AFFC _ATD1CTL23.Bits.AFFC +#define ATD1CTL23_ADPU _ATD1CTL23.Bits.ADPU +#define ATD1CTL23_FRZ _ATD1CTL23.MergedBits.grpFRZ + +#define ATD1CTL23_FRZ0_MASK 1U +#define ATD1CTL23_FRZ1_MASK 2U +#define ATD1CTL23_FIFO_MASK 4U +#define ATD1CTL23_S1C_MASK 8U +#define ATD1CTL23_S2C_MASK 16U +#define ATD1CTL23_S4C_MASK 32U +#define ATD1CTL23_S8C_MASK 64U +#define ATD1CTL23_ASCIF_MASK 256U +#define ATD1CTL23_ASCIE_MASK 512U +#define ATD1CTL23_ETRIGE_MASK 1024U +#define ATD1CTL23_ETRIGP_MASK 2048U +#define ATD1CTL23_ETRIGLE_MASK 4096U +#define ATD1CTL23_AWAI_MASK 8192U +#define ATD1CTL23_AFFC_MASK 16384U +#define ATD1CTL23_ADPU_MASK 32768U +#define ATD1CTL23_FRZ_MASK 3U +#define ATD1CTL23_FRZ_BITNUM 0U + + +/*** ATD1CTL45 - ATD 1 Control Register 45; 0x00000124 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1CTL4 - ATD 1 Control Register 4; 0x00000124 ***/ + union { + byte Byte; + struct { + byte PRS0 :1; /* ATD Clock Prescaler 0 */ + byte PRS1 :1; /* ATD Clock Prescaler 1 */ + byte PRS2 :1; /* ATD Clock Prescaler 2 */ + byte PRS3 :1; /* ATD Clock Prescaler 3 */ + byte PRS4 :1; /* ATD Clock Prescaler 4 */ + byte SMP0 :1; /* Sample Time Select 0 */ + byte SMP1 :1; /* Sample Time Select 1 */ + byte SRES8 :1; /* ATD Resolution Select */ + } Bits; + struct { + byte grpPRS :5; + byte grpSMP :2; + byte grpSRES_8 :1; + } MergedBits; + } ATD1CTL4STR; + #define ATD1CTL4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Byte + #define ATD1CTL4_PRS0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS0 + #define ATD1CTL4_PRS1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS1 + #define ATD1CTL4_PRS2 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS2 + #define ATD1CTL4_PRS3 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS3 + #define ATD1CTL4_PRS4 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.PRS4 + #define ATD1CTL4_SMP0 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP0 + #define ATD1CTL4_SMP1 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SMP1 + #define ATD1CTL4_SRES8 _ATD1CTL45.Overlap_STR.ATD1CTL4STR.Bits.SRES8 + #define ATD1CTL4_PRS _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpPRS + #define ATD1CTL4_SMP _ATD1CTL45.Overlap_STR.ATD1CTL4STR.MergedBits.grpSMP + + #define ATD1CTL4_PRS0_MASK 1U + #define ATD1CTL4_PRS1_MASK 2U + #define ATD1CTL4_PRS2_MASK 4U + #define ATD1CTL4_PRS3_MASK 8U + #define ATD1CTL4_PRS4_MASK 16U + #define ATD1CTL4_SMP0_MASK 32U + #define ATD1CTL4_SMP1_MASK 64U + #define ATD1CTL4_SRES8_MASK 128U + #define ATD1CTL4_PRS_MASK 31U + #define ATD1CTL4_PRS_BITNUM 0U + #define ATD1CTL4_SMP_MASK 96U + #define ATD1CTL4_SMP_BITNUM 5U + + + /*** ATD1CTL5 - ATD 1 Control Register 5; 0x00000125 ***/ + union { + byte Byte; + struct { + byte CA :1; /* Analog Input Channel Select Code A */ + byte CB :1; /* Analog Input Channel Select Code B */ + byte CC :1; /* Analog Input Channel Select Code C */ + byte :1; + byte MULT :1; /* Multi-Channel Sample Mode */ + byte SCAN :1; /* Continuous Conversion Sequence Mode */ + byte DSGN :1; /* Signed/Unsigned Result Data Mode */ + byte DJM :1; /* Result Register Data Justification Mode */ + } Bits; + struct { + byte grpCx :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; + } ATD1CTL5STR; + #define ATD1CTL5 _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Byte + #define ATD1CTL5_CA _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CA + #define ATD1CTL5_CB _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CB + #define ATD1CTL5_CC _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.CC + #define ATD1CTL5_MULT _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.MULT + #define ATD1CTL5_SCAN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.SCAN + #define ATD1CTL5_DSGN _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DSGN + #define ATD1CTL5_DJM _ATD1CTL45.Overlap_STR.ATD1CTL5STR.Bits.DJM + #define ATD1CTL5_Cx _ATD1CTL45.Overlap_STR.ATD1CTL5STR.MergedBits.grpCx + + #define ATD1CTL5_CA_MASK 1U + #define ATD1CTL5_CB_MASK 2U + #define ATD1CTL5_CC_MASK 4U + #define ATD1CTL5_MULT_MASK 16U + #define ATD1CTL5_SCAN_MASK 32U + #define ATD1CTL5_DSGN_MASK 64U + #define ATD1CTL5_DJM_MASK 128U + #define ATD1CTL5_Cx_MASK 7U + #define ATD1CTL5_Cx_BITNUM 0U + + } Overlap_STR; + + struct { + word CA :1; /* Analog Input Channel Select Code A */ + word CB :1; /* Analog Input Channel Select Code B */ + word CC :1; /* Analog Input Channel Select Code C */ + word :1; + word MULT :1; /* Multi-Channel Sample Mode */ + word SCAN :1; /* Continuous Conversion Sequence Mode */ + word DSGN :1; /* Signed/Unsigned Result Data Mode */ + word DJM :1; /* Result Register Data Justification Mode */ + word PRS0 :1; /* ATD Clock Prescaler 0 */ + word PRS1 :1; /* ATD Clock Prescaler 1 */ + word PRS2 :1; /* ATD Clock Prescaler 2 */ + word PRS3 :1; /* ATD Clock Prescaler 3 */ + word PRS4 :1; /* ATD Clock Prescaler 4 */ + word SMP0 :1; /* Sample Time Select 0 */ + word SMP1 :1; /* Sample Time Select 1 */ + word SRES8 :1; /* ATD Resolution Select */ + } Bits; + struct { + word grpCx :3; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpPRS :5; + word grpSMP :2; + word grpSRES_8 :1; + } MergedBits; +} ATD1CTL45STR; +extern volatile ATD1CTL45STR _ATD1CTL45 @(REG_BASE + 0x00000124UL); +#define ATD1CTL45 _ATD1CTL45.Word +#define ATD1CTL45_CA _ATD1CTL45.Bits.CA +#define ATD1CTL45_CB _ATD1CTL45.Bits.CB +#define ATD1CTL45_CC _ATD1CTL45.Bits.CC +#define ATD1CTL45_MULT _ATD1CTL45.Bits.MULT +#define ATD1CTL45_SCAN _ATD1CTL45.Bits.SCAN +#define ATD1CTL45_DSGN _ATD1CTL45.Bits.DSGN +#define ATD1CTL45_DJM _ATD1CTL45.Bits.DJM +#define ATD1CTL45_PRS0 _ATD1CTL45.Bits.PRS0 +#define ATD1CTL45_PRS1 _ATD1CTL45.Bits.PRS1 +#define ATD1CTL45_PRS2 _ATD1CTL45.Bits.PRS2 +#define ATD1CTL45_PRS3 _ATD1CTL45.Bits.PRS3 +#define ATD1CTL45_PRS4 _ATD1CTL45.Bits.PRS4 +#define ATD1CTL45_SMP0 _ATD1CTL45.Bits.SMP0 +#define ATD1CTL45_SMP1 _ATD1CTL45.Bits.SMP1 +#define ATD1CTL45_SRES8 _ATD1CTL45.Bits.SRES8 +#define ATD1CTL45_Cx _ATD1CTL45.MergedBits.grpCx +#define ATD1CTL45_PRS _ATD1CTL45.MergedBits.grpPRS +#define ATD1CTL45_SMP _ATD1CTL45.MergedBits.grpSMP + +#define ATD1CTL45_CA_MASK 1U +#define ATD1CTL45_CB_MASK 2U +#define ATD1CTL45_CC_MASK 4U +#define ATD1CTL45_MULT_MASK 16U +#define ATD1CTL45_SCAN_MASK 32U +#define ATD1CTL45_DSGN_MASK 64U +#define ATD1CTL45_DJM_MASK 128U +#define ATD1CTL45_PRS0_MASK 256U +#define ATD1CTL45_PRS1_MASK 512U +#define ATD1CTL45_PRS2_MASK 1024U +#define ATD1CTL45_PRS3_MASK 2048U +#define ATD1CTL45_PRS4_MASK 4096U +#define ATD1CTL45_SMP0_MASK 8192U +#define ATD1CTL45_SMP1_MASK 16384U +#define ATD1CTL45_SRES8_MASK 32768U +#define ATD1CTL45_Cx_MASK 7U +#define ATD1CTL45_Cx_BITNUM 0U +#define ATD1CTL45_PRS_MASK 7936U +#define ATD1CTL45_PRS_BITNUM 8U +#define ATD1CTL45_SMP_MASK 24576U +#define ATD1CTL45_SMP_BITNUM 13U + + +/*** ATD1STAT0 - ATD 1 Status Register 0; 0x00000126 ***/ +typedef union { + byte Byte; + struct { + byte CC0 :1; /* Conversion Counter 0 */ + byte CC1 :1; /* Conversion Counter 1 */ + byte CC2 :1; /* Conversion Counter 2 */ + byte :1; + byte FIFOR :1; /* FIFO Over Run Flag */ + byte ETORF :1; /* External Trigger Overrun Flag */ + byte :1; + byte SCF :1; /* Sequence Complete Flag */ + } Bits; + struct { + byte grpCC :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} ATD1STAT0STR; +extern volatile ATD1STAT0STR _ATD1STAT0 @(REG_BASE + 0x00000126UL); +#define ATD1STAT0 _ATD1STAT0.Byte +#define ATD1STAT0_CC0 _ATD1STAT0.Bits.CC0 +#define ATD1STAT0_CC1 _ATD1STAT0.Bits.CC1 +#define ATD1STAT0_CC2 _ATD1STAT0.Bits.CC2 +#define ATD1STAT0_FIFOR _ATD1STAT0.Bits.FIFOR +#define ATD1STAT0_ETORF _ATD1STAT0.Bits.ETORF +#define ATD1STAT0_SCF _ATD1STAT0.Bits.SCF +#define ATD1STAT0_CC _ATD1STAT0.MergedBits.grpCC + +#define ATD1STAT0_CC0_MASK 1U +#define ATD1STAT0_CC1_MASK 2U +#define ATD1STAT0_CC2_MASK 4U +#define ATD1STAT0_FIFOR_MASK 16U +#define ATD1STAT0_ETORF_MASK 32U +#define ATD1STAT0_SCF_MASK 128U +#define ATD1STAT0_CC_MASK 7U +#define ATD1STAT0_CC_BITNUM 0U + + +/*** ATD1TEST1 - ATD1 Test Register; 0x00000129 ***/ +typedef union { + byte Byte; + struct { + byte SC :1; /* Special Channel Conversion Bit */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; +} ATD1TEST1STR; +extern volatile ATD1TEST1STR _ATD1TEST1 @(REG_BASE + 0x00000129UL); +#define ATD1TEST1 _ATD1TEST1.Byte +#define ATD1TEST1_SC _ATD1TEST1.Bits.SC + +#define ATD1TEST1_SC_MASK 1U + + +/*** ATD1STAT1 - ATD 1 Status Register 1; 0x0000012B ***/ +typedef union { + byte Byte; + struct { + byte CCF0 :1; /* Conversion Complete Flag 0 */ + byte CCF1 :1; /* Conversion Complete Flag 1 */ + byte CCF2 :1; /* Conversion Complete Flag 2 */ + byte CCF3 :1; /* Conversion Complete Flag 3 */ + byte CCF4 :1; /* Conversion Complete Flag 4 */ + byte CCF5 :1; /* Conversion Complete Flag 5 */ + byte CCF6 :1; /* Conversion Complete Flag 6 */ + byte CCF7 :1; /* Conversion Complete Flag 7 */ + } Bits; +} ATD1STAT1STR; +extern volatile ATD1STAT1STR _ATD1STAT1 @(REG_BASE + 0x0000012BUL); +#define ATD1STAT1 _ATD1STAT1.Byte +#define ATD1STAT1_CCF0 _ATD1STAT1.Bits.CCF0 +#define ATD1STAT1_CCF1 _ATD1STAT1.Bits.CCF1 +#define ATD1STAT1_CCF2 _ATD1STAT1.Bits.CCF2 +#define ATD1STAT1_CCF3 _ATD1STAT1.Bits.CCF3 +#define ATD1STAT1_CCF4 _ATD1STAT1.Bits.CCF4 +#define ATD1STAT1_CCF5 _ATD1STAT1.Bits.CCF5 +#define ATD1STAT1_CCF6 _ATD1STAT1.Bits.CCF6 +#define ATD1STAT1_CCF7 _ATD1STAT1.Bits.CCF7 + +#define ATD1STAT1_CCF0_MASK 1U +#define ATD1STAT1_CCF1_MASK 2U +#define ATD1STAT1_CCF2_MASK 4U +#define ATD1STAT1_CCF3_MASK 8U +#define ATD1STAT1_CCF4_MASK 16U +#define ATD1STAT1_CCF5_MASK 32U +#define ATD1STAT1_CCF6_MASK 64U +#define ATD1STAT1_CCF7_MASK 128U + + +/*** ATD1DIEN - ATD 1 Input Enable Register; 0x0000012D ***/ +typedef union { + byte Byte; + struct { + byte IEN0 :1; /* ATD Digital Input Enable on channel 0 */ + byte IEN1 :1; /* ATD Digital Input Enable on channel 1 */ + byte IEN2 :1; /* ATD Digital Input Enable on channel 2 */ + byte IEN3 :1; /* ATD Digital Input Enable on channel 3 */ + byte IEN4 :1; /* ATD Digital Input Enable on channel 4 */ + byte IEN5 :1; /* ATD Digital Input Enable on channel 5 */ + byte IEN6 :1; /* ATD Digital Input Enable on channel 6 */ + byte IEN7 :1; /* ATD Digital Input Enable on channel 7 */ + } Bits; +} ATD1DIENSTR; +extern volatile ATD1DIENSTR _ATD1DIEN @(REG_BASE + 0x0000012DUL); +#define ATD1DIEN _ATD1DIEN.Byte +#define ATD1DIEN_IEN0 _ATD1DIEN.Bits.IEN0 +#define ATD1DIEN_IEN1 _ATD1DIEN.Bits.IEN1 +#define ATD1DIEN_IEN2 _ATD1DIEN.Bits.IEN2 +#define ATD1DIEN_IEN3 _ATD1DIEN.Bits.IEN3 +#define ATD1DIEN_IEN4 _ATD1DIEN.Bits.IEN4 +#define ATD1DIEN_IEN5 _ATD1DIEN.Bits.IEN5 +#define ATD1DIEN_IEN6 _ATD1DIEN.Bits.IEN6 +#define ATD1DIEN_IEN7 _ATD1DIEN.Bits.IEN7 + +#define ATD1DIEN_IEN0_MASK 1U +#define ATD1DIEN_IEN1_MASK 2U +#define ATD1DIEN_IEN2_MASK 4U +#define ATD1DIEN_IEN3_MASK 8U +#define ATD1DIEN_IEN4_MASK 16U +#define ATD1DIEN_IEN5_MASK 32U +#define ATD1DIEN_IEN6_MASK 64U +#define ATD1DIEN_IEN7_MASK 128U + + +/*** PORTAD1 - Port AD1 Register; 0x0000012F ***/ +typedef union { + byte Byte; + struct { + byte PTAD0 :1; /* A/D Channel 0 (AN0) Digital Input */ + byte PTAD1 :1; /* A/D Channel 1 (AN1) Digital Input */ + byte PTAD2 :1; /* A/D Channel 2 (AN2) Digital Input */ + byte PTAD3 :1; /* A/D Channel 3 (AN3) Digital Input */ + byte PTAD4 :1; /* A/D Channel 4 (AN4) Digital Input */ + byte PTAD5 :1; /* A/D Channel 5 (AN5) Digital Input */ + byte PTAD6 :1; /* A/D Channel 6 (AN6) Digital Input */ + byte PTAD7 :1; /* A/D Channel 7 (AN7) Digital Input */ + } Bits; +} PORTAD1STR; +extern volatile PORTAD1STR _PORTAD1 @(REG_BASE + 0x0000012FUL); +#define PORTAD1 _PORTAD1.Byte +#define PORTAD1_PTAD0 _PORTAD1.Bits.PTAD0 +#define PORTAD1_PTAD1 _PORTAD1.Bits.PTAD1 +#define PORTAD1_PTAD2 _PORTAD1.Bits.PTAD2 +#define PORTAD1_PTAD3 _PORTAD1.Bits.PTAD3 +#define PORTAD1_PTAD4 _PORTAD1.Bits.PTAD4 +#define PORTAD1_PTAD5 _PORTAD1.Bits.PTAD5 +#define PORTAD1_PTAD6 _PORTAD1.Bits.PTAD6 +#define PORTAD1_PTAD7 _PORTAD1.Bits.PTAD7 + +#define PORTAD1_PTAD0_MASK 1U +#define PORTAD1_PTAD1_MASK 2U +#define PORTAD1_PTAD2_MASK 4U +#define PORTAD1_PTAD3_MASK 8U +#define PORTAD1_PTAD4_MASK 16U +#define PORTAD1_PTAD5_MASK 32U +#define PORTAD1_PTAD6_MASK 64U +#define PORTAD1_PTAD7_MASK 128U + + +/*** ATD1DR0 - ATD 1 Conversion Result Register 0; 0x00000130 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR0H - ATD 1 Conversion Result Register 0 High; 0x00000130 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR0HSTR; + #define ATD1DR0H _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Byte + #define ATD1DR0H_BIT8 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT8 + #define ATD1DR0H_BIT9 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT9 + #define ATD1DR0H_BIT10 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT10 + #define ATD1DR0H_BIT11 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT11 + #define ATD1DR0H_BIT12 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT12 + #define ATD1DR0H_BIT13 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT13 + #define ATD1DR0H_BIT14 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT14 + #define ATD1DR0H_BIT15 _ATD1DR0.Overlap_STR.ATD1DR0HSTR.Bits.BIT15 + + #define ATD1DR0H_BIT8_MASK 1U + #define ATD1DR0H_BIT9_MASK 2U + #define ATD1DR0H_BIT10_MASK 4U + #define ATD1DR0H_BIT11_MASK 8U + #define ATD1DR0H_BIT12_MASK 16U + #define ATD1DR0H_BIT13_MASK 32U + #define ATD1DR0H_BIT14_MASK 64U + #define ATD1DR0H_BIT15_MASK 128U + + + /*** ATD1DR0L - ATD 1 Conversion Result Register 0 Low; 0x00000131 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR0LSTR; + #define ATD1DR0L _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Byte + #define ATD1DR0L_BIT6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT6 + #define ATD1DR0L_BIT7 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.Bits.BIT7 + #define ATD1DR0L_BIT_6 _ATD1DR0.Overlap_STR.ATD1DR0LSTR.MergedBits.grpBIT_6 + #define ATD1DR0L_BIT ATD1DR0L_BIT_6 + + #define ATD1DR0L_BIT6_MASK 64U + #define ATD1DR0L_BIT7_MASK 128U + #define ATD1DR0L_BIT_6_MASK 192U + #define ATD1DR0L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR0STR; +extern volatile ATD1DR0STR _ATD1DR0 @(REG_BASE + 0x00000130UL); +#define ATD1DR0 _ATD1DR0.Word +#define ATD1DR0_BIT6 _ATD1DR0.Bits.BIT6 +#define ATD1DR0_BIT7 _ATD1DR0.Bits.BIT7 +#define ATD1DR0_BIT8 _ATD1DR0.Bits.BIT8 +#define ATD1DR0_BIT9 _ATD1DR0.Bits.BIT9 +#define ATD1DR0_BIT10 _ATD1DR0.Bits.BIT10 +#define ATD1DR0_BIT11 _ATD1DR0.Bits.BIT11 +#define ATD1DR0_BIT12 _ATD1DR0.Bits.BIT12 +#define ATD1DR0_BIT13 _ATD1DR0.Bits.BIT13 +#define ATD1DR0_BIT14 _ATD1DR0.Bits.BIT14 +#define ATD1DR0_BIT15 _ATD1DR0.Bits.BIT15 +/* ATD1DR_ARR: Access 8 ATD1DRx registers in an array */ +#define ATD1DR_ARR ((volatile word *) &ATD1DR0) +#define ATD1DR0_BIT_6 _ATD1DR0.MergedBits.grpBIT_6 +#define ATD1DR0_BIT ATD1DR0_BIT_6 + +#define ATD1DR0_BIT6_MASK 64U +#define ATD1DR0_BIT7_MASK 128U +#define ATD1DR0_BIT8_MASK 256U +#define ATD1DR0_BIT9_MASK 512U +#define ATD1DR0_BIT10_MASK 1024U +#define ATD1DR0_BIT11_MASK 2048U +#define ATD1DR0_BIT12_MASK 4096U +#define ATD1DR0_BIT13_MASK 8192U +#define ATD1DR0_BIT14_MASK 16384U +#define ATD1DR0_BIT15_MASK 32768U +#define ATD1DR0_BIT_6_MASK 65472U +#define ATD1DR0_BIT_6_BITNUM 6U + + +/*** ATD1DR1 - ATD 1 Conversion Result Register 1; 0x00000132 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR1H - ATD 1 Conversion Result Register 1 High; 0x00000132 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR1HSTR; + #define ATD1DR1H _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Byte + #define ATD1DR1H_BIT8 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT8 + #define ATD1DR1H_BIT9 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT9 + #define ATD1DR1H_BIT10 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT10 + #define ATD1DR1H_BIT11 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT11 + #define ATD1DR1H_BIT12 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT12 + #define ATD1DR1H_BIT13 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT13 + #define ATD1DR1H_BIT14 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT14 + #define ATD1DR1H_BIT15 _ATD1DR1.Overlap_STR.ATD1DR1HSTR.Bits.BIT15 + + #define ATD1DR1H_BIT8_MASK 1U + #define ATD1DR1H_BIT9_MASK 2U + #define ATD1DR1H_BIT10_MASK 4U + #define ATD1DR1H_BIT11_MASK 8U + #define ATD1DR1H_BIT12_MASK 16U + #define ATD1DR1H_BIT13_MASK 32U + #define ATD1DR1H_BIT14_MASK 64U + #define ATD1DR1H_BIT15_MASK 128U + + + /*** ATD1DR1L - ATD 1 Conversion Result Register 1 Low; 0x00000133 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR1LSTR; + #define ATD1DR1L _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Byte + #define ATD1DR1L_BIT6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT6 + #define ATD1DR1L_BIT7 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.Bits.BIT7 + #define ATD1DR1L_BIT_6 _ATD1DR1.Overlap_STR.ATD1DR1LSTR.MergedBits.grpBIT_6 + #define ATD1DR1L_BIT ATD1DR1L_BIT_6 + + #define ATD1DR1L_BIT6_MASK 64U + #define ATD1DR1L_BIT7_MASK 128U + #define ATD1DR1L_BIT_6_MASK 192U + #define ATD1DR1L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR1STR; +extern volatile ATD1DR1STR _ATD1DR1 @(REG_BASE + 0x00000132UL); +#define ATD1DR1 _ATD1DR1.Word +#define ATD1DR1_BIT6 _ATD1DR1.Bits.BIT6 +#define ATD1DR1_BIT7 _ATD1DR1.Bits.BIT7 +#define ATD1DR1_BIT8 _ATD1DR1.Bits.BIT8 +#define ATD1DR1_BIT9 _ATD1DR1.Bits.BIT9 +#define ATD1DR1_BIT10 _ATD1DR1.Bits.BIT10 +#define ATD1DR1_BIT11 _ATD1DR1.Bits.BIT11 +#define ATD1DR1_BIT12 _ATD1DR1.Bits.BIT12 +#define ATD1DR1_BIT13 _ATD1DR1.Bits.BIT13 +#define ATD1DR1_BIT14 _ATD1DR1.Bits.BIT14 +#define ATD1DR1_BIT15 _ATD1DR1.Bits.BIT15 +#define ATD1DR1_BIT_6 _ATD1DR1.MergedBits.grpBIT_6 +#define ATD1DR1_BIT ATD1DR1_BIT_6 + +#define ATD1DR1_BIT6_MASK 64U +#define ATD1DR1_BIT7_MASK 128U +#define ATD1DR1_BIT8_MASK 256U +#define ATD1DR1_BIT9_MASK 512U +#define ATD1DR1_BIT10_MASK 1024U +#define ATD1DR1_BIT11_MASK 2048U +#define ATD1DR1_BIT12_MASK 4096U +#define ATD1DR1_BIT13_MASK 8192U +#define ATD1DR1_BIT14_MASK 16384U +#define ATD1DR1_BIT15_MASK 32768U +#define ATD1DR1_BIT_6_MASK 65472U +#define ATD1DR1_BIT_6_BITNUM 6U + + +/*** ATD1DR2 - ATD 1 Conversion Result Register 2; 0x00000134 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR2H - ATD 1 Conversion Result Register 2 High; 0x00000134 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR2HSTR; + #define ATD1DR2H _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Byte + #define ATD1DR2H_BIT8 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT8 + #define ATD1DR2H_BIT9 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT9 + #define ATD1DR2H_BIT10 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT10 + #define ATD1DR2H_BIT11 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT11 + #define ATD1DR2H_BIT12 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT12 + #define ATD1DR2H_BIT13 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT13 + #define ATD1DR2H_BIT14 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT14 + #define ATD1DR2H_BIT15 _ATD1DR2.Overlap_STR.ATD1DR2HSTR.Bits.BIT15 + + #define ATD1DR2H_BIT8_MASK 1U + #define ATD1DR2H_BIT9_MASK 2U + #define ATD1DR2H_BIT10_MASK 4U + #define ATD1DR2H_BIT11_MASK 8U + #define ATD1DR2H_BIT12_MASK 16U + #define ATD1DR2H_BIT13_MASK 32U + #define ATD1DR2H_BIT14_MASK 64U + #define ATD1DR2H_BIT15_MASK 128U + + + /*** ATD1DR2L - ATD 1 Conversion Result Register 2 Low; 0x00000135 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR2LSTR; + #define ATD1DR2L _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Byte + #define ATD1DR2L_BIT6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT6 + #define ATD1DR2L_BIT7 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.Bits.BIT7 + #define ATD1DR2L_BIT_6 _ATD1DR2.Overlap_STR.ATD1DR2LSTR.MergedBits.grpBIT_6 + #define ATD1DR2L_BIT ATD1DR2L_BIT_6 + + #define ATD1DR2L_BIT6_MASK 64U + #define ATD1DR2L_BIT7_MASK 128U + #define ATD1DR2L_BIT_6_MASK 192U + #define ATD1DR2L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR2STR; +extern volatile ATD1DR2STR _ATD1DR2 @(REG_BASE + 0x00000134UL); +#define ATD1DR2 _ATD1DR2.Word +#define ATD1DR2_BIT6 _ATD1DR2.Bits.BIT6 +#define ATD1DR2_BIT7 _ATD1DR2.Bits.BIT7 +#define ATD1DR2_BIT8 _ATD1DR2.Bits.BIT8 +#define ATD1DR2_BIT9 _ATD1DR2.Bits.BIT9 +#define ATD1DR2_BIT10 _ATD1DR2.Bits.BIT10 +#define ATD1DR2_BIT11 _ATD1DR2.Bits.BIT11 +#define ATD1DR2_BIT12 _ATD1DR2.Bits.BIT12 +#define ATD1DR2_BIT13 _ATD1DR2.Bits.BIT13 +#define ATD1DR2_BIT14 _ATD1DR2.Bits.BIT14 +#define ATD1DR2_BIT15 _ATD1DR2.Bits.BIT15 +#define ATD1DR2_BIT_6 _ATD1DR2.MergedBits.grpBIT_6 +#define ATD1DR2_BIT ATD1DR2_BIT_6 + +#define ATD1DR2_BIT6_MASK 64U +#define ATD1DR2_BIT7_MASK 128U +#define ATD1DR2_BIT8_MASK 256U +#define ATD1DR2_BIT9_MASK 512U +#define ATD1DR2_BIT10_MASK 1024U +#define ATD1DR2_BIT11_MASK 2048U +#define ATD1DR2_BIT12_MASK 4096U +#define ATD1DR2_BIT13_MASK 8192U +#define ATD1DR2_BIT14_MASK 16384U +#define ATD1DR2_BIT15_MASK 32768U +#define ATD1DR2_BIT_6_MASK 65472U +#define ATD1DR2_BIT_6_BITNUM 6U + + +/*** ATD1DR3 - ATD 1 Conversion Result Register 3; 0x00000136 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR3H - ATD 1 Conversion Result Register 3 High; 0x00000136 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR3HSTR; + #define ATD1DR3H _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Byte + #define ATD1DR3H_BIT8 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT8 + #define ATD1DR3H_BIT9 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT9 + #define ATD1DR3H_BIT10 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT10 + #define ATD1DR3H_BIT11 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT11 + #define ATD1DR3H_BIT12 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT12 + #define ATD1DR3H_BIT13 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT13 + #define ATD1DR3H_BIT14 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT14 + #define ATD1DR3H_BIT15 _ATD1DR3.Overlap_STR.ATD1DR3HSTR.Bits.BIT15 + + #define ATD1DR3H_BIT8_MASK 1U + #define ATD1DR3H_BIT9_MASK 2U + #define ATD1DR3H_BIT10_MASK 4U + #define ATD1DR3H_BIT11_MASK 8U + #define ATD1DR3H_BIT12_MASK 16U + #define ATD1DR3H_BIT13_MASK 32U + #define ATD1DR3H_BIT14_MASK 64U + #define ATD1DR3H_BIT15_MASK 128U + + + /*** ATD1DR3L - ATD 1 Conversion Result Register 3 Low; 0x00000137 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR3LSTR; + #define ATD1DR3L _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Byte + #define ATD1DR3L_BIT6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT6 + #define ATD1DR3L_BIT7 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.Bits.BIT7 + #define ATD1DR3L_BIT_6 _ATD1DR3.Overlap_STR.ATD1DR3LSTR.MergedBits.grpBIT_6 + #define ATD1DR3L_BIT ATD1DR3L_BIT_6 + + #define ATD1DR3L_BIT6_MASK 64U + #define ATD1DR3L_BIT7_MASK 128U + #define ATD1DR3L_BIT_6_MASK 192U + #define ATD1DR3L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR3STR; +extern volatile ATD1DR3STR _ATD1DR3 @(REG_BASE + 0x00000136UL); +#define ATD1DR3 _ATD1DR3.Word +#define ATD1DR3_BIT6 _ATD1DR3.Bits.BIT6 +#define ATD1DR3_BIT7 _ATD1DR3.Bits.BIT7 +#define ATD1DR3_BIT8 _ATD1DR3.Bits.BIT8 +#define ATD1DR3_BIT9 _ATD1DR3.Bits.BIT9 +#define ATD1DR3_BIT10 _ATD1DR3.Bits.BIT10 +#define ATD1DR3_BIT11 _ATD1DR3.Bits.BIT11 +#define ATD1DR3_BIT12 _ATD1DR3.Bits.BIT12 +#define ATD1DR3_BIT13 _ATD1DR3.Bits.BIT13 +#define ATD1DR3_BIT14 _ATD1DR3.Bits.BIT14 +#define ATD1DR3_BIT15 _ATD1DR3.Bits.BIT15 +#define ATD1DR3_BIT_6 _ATD1DR3.MergedBits.grpBIT_6 +#define ATD1DR3_BIT ATD1DR3_BIT_6 + +#define ATD1DR3_BIT6_MASK 64U +#define ATD1DR3_BIT7_MASK 128U +#define ATD1DR3_BIT8_MASK 256U +#define ATD1DR3_BIT9_MASK 512U +#define ATD1DR3_BIT10_MASK 1024U +#define ATD1DR3_BIT11_MASK 2048U +#define ATD1DR3_BIT12_MASK 4096U +#define ATD1DR3_BIT13_MASK 8192U +#define ATD1DR3_BIT14_MASK 16384U +#define ATD1DR3_BIT15_MASK 32768U +#define ATD1DR3_BIT_6_MASK 65472U +#define ATD1DR3_BIT_6_BITNUM 6U + + +/*** ATD1DR4 - ATD 1 Conversion Result Register 4; 0x00000138 ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR4H - ATD 1 Conversion Result Register 4 High; 0x00000138 ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR4HSTR; + #define ATD1DR4H _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Byte + #define ATD1DR4H_BIT8 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT8 + #define ATD1DR4H_BIT9 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT9 + #define ATD1DR4H_BIT10 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT10 + #define ATD1DR4H_BIT11 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT11 + #define ATD1DR4H_BIT12 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT12 + #define ATD1DR4H_BIT13 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT13 + #define ATD1DR4H_BIT14 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT14 + #define ATD1DR4H_BIT15 _ATD1DR4.Overlap_STR.ATD1DR4HSTR.Bits.BIT15 + + #define ATD1DR4H_BIT8_MASK 1U + #define ATD1DR4H_BIT9_MASK 2U + #define ATD1DR4H_BIT10_MASK 4U + #define ATD1DR4H_BIT11_MASK 8U + #define ATD1DR4H_BIT12_MASK 16U + #define ATD1DR4H_BIT13_MASK 32U + #define ATD1DR4H_BIT14_MASK 64U + #define ATD1DR4H_BIT15_MASK 128U + + + /*** ATD1DR4L - ATD 1 Conversion Result Register 4 Low; 0x00000139 ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR4LSTR; + #define ATD1DR4L _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Byte + #define ATD1DR4L_BIT6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT6 + #define ATD1DR4L_BIT7 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.Bits.BIT7 + #define ATD1DR4L_BIT_6 _ATD1DR4.Overlap_STR.ATD1DR4LSTR.MergedBits.grpBIT_6 + #define ATD1DR4L_BIT ATD1DR4L_BIT_6 + + #define ATD1DR4L_BIT6_MASK 64U + #define ATD1DR4L_BIT7_MASK 128U + #define ATD1DR4L_BIT_6_MASK 192U + #define ATD1DR4L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR4STR; +extern volatile ATD1DR4STR _ATD1DR4 @(REG_BASE + 0x00000138UL); +#define ATD1DR4 _ATD1DR4.Word +#define ATD1DR4_BIT6 _ATD1DR4.Bits.BIT6 +#define ATD1DR4_BIT7 _ATD1DR4.Bits.BIT7 +#define ATD1DR4_BIT8 _ATD1DR4.Bits.BIT8 +#define ATD1DR4_BIT9 _ATD1DR4.Bits.BIT9 +#define ATD1DR4_BIT10 _ATD1DR4.Bits.BIT10 +#define ATD1DR4_BIT11 _ATD1DR4.Bits.BIT11 +#define ATD1DR4_BIT12 _ATD1DR4.Bits.BIT12 +#define ATD1DR4_BIT13 _ATD1DR4.Bits.BIT13 +#define ATD1DR4_BIT14 _ATD1DR4.Bits.BIT14 +#define ATD1DR4_BIT15 _ATD1DR4.Bits.BIT15 +#define ATD1DR4_BIT_6 _ATD1DR4.MergedBits.grpBIT_6 +#define ATD1DR4_BIT ATD1DR4_BIT_6 + +#define ATD1DR4_BIT6_MASK 64U +#define ATD1DR4_BIT7_MASK 128U +#define ATD1DR4_BIT8_MASK 256U +#define ATD1DR4_BIT9_MASK 512U +#define ATD1DR4_BIT10_MASK 1024U +#define ATD1DR4_BIT11_MASK 2048U +#define ATD1DR4_BIT12_MASK 4096U +#define ATD1DR4_BIT13_MASK 8192U +#define ATD1DR4_BIT14_MASK 16384U +#define ATD1DR4_BIT15_MASK 32768U +#define ATD1DR4_BIT_6_MASK 65472U +#define ATD1DR4_BIT_6_BITNUM 6U + + +/*** ATD1DR5 - ATD 1 Conversion Result Register 5; 0x0000013A ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR5H - ATD 1 Conversion Result Register 5 High; 0x0000013A ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR5HSTR; + #define ATD1DR5H _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Byte + #define ATD1DR5H_BIT8 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT8 + #define ATD1DR5H_BIT9 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT9 + #define ATD1DR5H_BIT10 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT10 + #define ATD1DR5H_BIT11 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT11 + #define ATD1DR5H_BIT12 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT12 + #define ATD1DR5H_BIT13 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT13 + #define ATD1DR5H_BIT14 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT14 + #define ATD1DR5H_BIT15 _ATD1DR5.Overlap_STR.ATD1DR5HSTR.Bits.BIT15 + + #define ATD1DR5H_BIT8_MASK 1U + #define ATD1DR5H_BIT9_MASK 2U + #define ATD1DR5H_BIT10_MASK 4U + #define ATD1DR5H_BIT11_MASK 8U + #define ATD1DR5H_BIT12_MASK 16U + #define ATD1DR5H_BIT13_MASK 32U + #define ATD1DR5H_BIT14_MASK 64U + #define ATD1DR5H_BIT15_MASK 128U + + + /*** ATD1DR5L - ATD 1 Conversion Result Register 5 Low; 0x0000013B ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR5LSTR; + #define ATD1DR5L _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Byte + #define ATD1DR5L_BIT6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT6 + #define ATD1DR5L_BIT7 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.Bits.BIT7 + #define ATD1DR5L_BIT_6 _ATD1DR5.Overlap_STR.ATD1DR5LSTR.MergedBits.grpBIT_6 + #define ATD1DR5L_BIT ATD1DR5L_BIT_6 + + #define ATD1DR5L_BIT6_MASK 64U + #define ATD1DR5L_BIT7_MASK 128U + #define ATD1DR5L_BIT_6_MASK 192U + #define ATD1DR5L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR5STR; +extern volatile ATD1DR5STR _ATD1DR5 @(REG_BASE + 0x0000013AUL); +#define ATD1DR5 _ATD1DR5.Word +#define ATD1DR5_BIT6 _ATD1DR5.Bits.BIT6 +#define ATD1DR5_BIT7 _ATD1DR5.Bits.BIT7 +#define ATD1DR5_BIT8 _ATD1DR5.Bits.BIT8 +#define ATD1DR5_BIT9 _ATD1DR5.Bits.BIT9 +#define ATD1DR5_BIT10 _ATD1DR5.Bits.BIT10 +#define ATD1DR5_BIT11 _ATD1DR5.Bits.BIT11 +#define ATD1DR5_BIT12 _ATD1DR5.Bits.BIT12 +#define ATD1DR5_BIT13 _ATD1DR5.Bits.BIT13 +#define ATD1DR5_BIT14 _ATD1DR5.Bits.BIT14 +#define ATD1DR5_BIT15 _ATD1DR5.Bits.BIT15 +#define ATD1DR5_BIT_6 _ATD1DR5.MergedBits.grpBIT_6 +#define ATD1DR5_BIT ATD1DR5_BIT_6 + +#define ATD1DR5_BIT6_MASK 64U +#define ATD1DR5_BIT7_MASK 128U +#define ATD1DR5_BIT8_MASK 256U +#define ATD1DR5_BIT9_MASK 512U +#define ATD1DR5_BIT10_MASK 1024U +#define ATD1DR5_BIT11_MASK 2048U +#define ATD1DR5_BIT12_MASK 4096U +#define ATD1DR5_BIT13_MASK 8192U +#define ATD1DR5_BIT14_MASK 16384U +#define ATD1DR5_BIT15_MASK 32768U +#define ATD1DR5_BIT_6_MASK 65472U +#define ATD1DR5_BIT_6_BITNUM 6U + + +/*** ATD1DR6 - ATD 1 Conversion Result Register 6; 0x0000013C ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR6H - ATD 1 Conversion Result Register 6 High; 0x0000013C ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR6HSTR; + #define ATD1DR6H _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Byte + #define ATD1DR6H_BIT8 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT8 + #define ATD1DR6H_BIT9 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT9 + #define ATD1DR6H_BIT10 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT10 + #define ATD1DR6H_BIT11 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT11 + #define ATD1DR6H_BIT12 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT12 + #define ATD1DR6H_BIT13 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT13 + #define ATD1DR6H_BIT14 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT14 + #define ATD1DR6H_BIT15 _ATD1DR6.Overlap_STR.ATD1DR6HSTR.Bits.BIT15 + + #define ATD1DR6H_BIT8_MASK 1U + #define ATD1DR6H_BIT9_MASK 2U + #define ATD1DR6H_BIT10_MASK 4U + #define ATD1DR6H_BIT11_MASK 8U + #define ATD1DR6H_BIT12_MASK 16U + #define ATD1DR6H_BIT13_MASK 32U + #define ATD1DR6H_BIT14_MASK 64U + #define ATD1DR6H_BIT15_MASK 128U + + + /*** ATD1DR6L - ATD 1 Conversion Result Register 6 Low; 0x0000013D ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR6LSTR; + #define ATD1DR6L _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Byte + #define ATD1DR6L_BIT6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT6 + #define ATD1DR6L_BIT7 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.Bits.BIT7 + #define ATD1DR6L_BIT_6 _ATD1DR6.Overlap_STR.ATD1DR6LSTR.MergedBits.grpBIT_6 + #define ATD1DR6L_BIT ATD1DR6L_BIT_6 + + #define ATD1DR6L_BIT6_MASK 64U + #define ATD1DR6L_BIT7_MASK 128U + #define ATD1DR6L_BIT_6_MASK 192U + #define ATD1DR6L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR6STR; +extern volatile ATD1DR6STR _ATD1DR6 @(REG_BASE + 0x0000013CUL); +#define ATD1DR6 _ATD1DR6.Word +#define ATD1DR6_BIT6 _ATD1DR6.Bits.BIT6 +#define ATD1DR6_BIT7 _ATD1DR6.Bits.BIT7 +#define ATD1DR6_BIT8 _ATD1DR6.Bits.BIT8 +#define ATD1DR6_BIT9 _ATD1DR6.Bits.BIT9 +#define ATD1DR6_BIT10 _ATD1DR6.Bits.BIT10 +#define ATD1DR6_BIT11 _ATD1DR6.Bits.BIT11 +#define ATD1DR6_BIT12 _ATD1DR6.Bits.BIT12 +#define ATD1DR6_BIT13 _ATD1DR6.Bits.BIT13 +#define ATD1DR6_BIT14 _ATD1DR6.Bits.BIT14 +#define ATD1DR6_BIT15 _ATD1DR6.Bits.BIT15 +#define ATD1DR6_BIT_6 _ATD1DR6.MergedBits.grpBIT_6 +#define ATD1DR6_BIT ATD1DR6_BIT_6 + +#define ATD1DR6_BIT6_MASK 64U +#define ATD1DR6_BIT7_MASK 128U +#define ATD1DR6_BIT8_MASK 256U +#define ATD1DR6_BIT9_MASK 512U +#define ATD1DR6_BIT10_MASK 1024U +#define ATD1DR6_BIT11_MASK 2048U +#define ATD1DR6_BIT12_MASK 4096U +#define ATD1DR6_BIT13_MASK 8192U +#define ATD1DR6_BIT14_MASK 16384U +#define ATD1DR6_BIT15_MASK 32768U +#define ATD1DR6_BIT_6_MASK 65472U +#define ATD1DR6_BIT_6_BITNUM 6U + + +/*** ATD1DR7 - ATD 1 Conversion Result Register 7; 0x0000013E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** ATD1DR7H - ATD 1 Conversion Result Register 7 High; 0x0000013E ***/ + union { + byte Byte; + struct { + byte BIT8 :1; /* Bit 8 */ + byte BIT9 :1; /* Bit 9 */ + byte BIT10 :1; /* Bit 10 */ + byte BIT11 :1; /* Bit 11 */ + byte BIT12 :1; /* Bit 12 */ + byte BIT13 :1; /* Bit 13 */ + byte BIT14 :1; /* Bit 14 */ + byte BIT15 :1; /* Bit 15 */ + } Bits; + } ATD1DR7HSTR; + #define ATD1DR7H _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Byte + #define ATD1DR7H_BIT8 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT8 + #define ATD1DR7H_BIT9 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT9 + #define ATD1DR7H_BIT10 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT10 + #define ATD1DR7H_BIT11 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT11 + #define ATD1DR7H_BIT12 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT12 + #define ATD1DR7H_BIT13 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT13 + #define ATD1DR7H_BIT14 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT14 + #define ATD1DR7H_BIT15 _ATD1DR7.Overlap_STR.ATD1DR7HSTR.Bits.BIT15 + + #define ATD1DR7H_BIT8_MASK 1U + #define ATD1DR7H_BIT9_MASK 2U + #define ATD1DR7H_BIT10_MASK 4U + #define ATD1DR7H_BIT11_MASK 8U + #define ATD1DR7H_BIT12_MASK 16U + #define ATD1DR7H_BIT13_MASK 32U + #define ATD1DR7H_BIT14_MASK 64U + #define ATD1DR7H_BIT15_MASK 128U + + + /*** ATD1DR7L - ATD 1 Conversion Result Register 7 Low; 0x0000013F ***/ + union { + byte Byte; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte BIT6 :1; /* Bit 6 */ + byte BIT7 :1; /* Bit 7 */ + } Bits; + struct { + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpBIT_6 :2; + } MergedBits; + } ATD1DR7LSTR; + #define ATD1DR7L _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Byte + #define ATD1DR7L_BIT6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT6 + #define ATD1DR7L_BIT7 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.Bits.BIT7 + #define ATD1DR7L_BIT_6 _ATD1DR7.Overlap_STR.ATD1DR7LSTR.MergedBits.grpBIT_6 + #define ATD1DR7L_BIT ATD1DR7L_BIT_6 + + #define ATD1DR7L_BIT6_MASK 64U + #define ATD1DR7L_BIT7_MASK 128U + #define ATD1DR7L_BIT_6_MASK 192U + #define ATD1DR7L_BIT_6_BITNUM 6U + + } Overlap_STR; + + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word BIT6 :1; /* Bit 6 */ + word BIT7 :1; /* Bit 7 */ + word BIT8 :1; /* Bit 8 */ + word BIT9 :1; /* Bit 9 */ + word BIT10 :1; /* Bit 10 */ + word BIT11 :1; /* Bit 11 */ + word BIT12 :1; /* Bit 12 */ + word BIT13 :1; /* Bit 13 */ + word BIT14 :1; /* Bit 14 */ + word BIT15 :1; /* Bit 15 */ + } Bits; + struct { + word :1; + word :1; + word :1; + word :1; + word :1; + word :1; + word grpBIT_6 :10; + } MergedBits; +} ATD1DR7STR; +extern volatile ATD1DR7STR _ATD1DR7 @(REG_BASE + 0x0000013EUL); +#define ATD1DR7 _ATD1DR7.Word +#define ATD1DR7_BIT6 _ATD1DR7.Bits.BIT6 +#define ATD1DR7_BIT7 _ATD1DR7.Bits.BIT7 +#define ATD1DR7_BIT8 _ATD1DR7.Bits.BIT8 +#define ATD1DR7_BIT9 _ATD1DR7.Bits.BIT9 +#define ATD1DR7_BIT10 _ATD1DR7.Bits.BIT10 +#define ATD1DR7_BIT11 _ATD1DR7.Bits.BIT11 +#define ATD1DR7_BIT12 _ATD1DR7.Bits.BIT12 +#define ATD1DR7_BIT13 _ATD1DR7.Bits.BIT13 +#define ATD1DR7_BIT14 _ATD1DR7.Bits.BIT14 +#define ATD1DR7_BIT15 _ATD1DR7.Bits.BIT15 +#define ATD1DR7_BIT_6 _ATD1DR7.MergedBits.grpBIT_6 +#define ATD1DR7_BIT ATD1DR7_BIT_6 + +#define ATD1DR7_BIT6_MASK 64U +#define ATD1DR7_BIT7_MASK 128U +#define ATD1DR7_BIT8_MASK 256U +#define ATD1DR7_BIT9_MASK 512U +#define ATD1DR7_BIT10_MASK 1024U +#define ATD1DR7_BIT11_MASK 2048U +#define ATD1DR7_BIT12_MASK 4096U +#define ATD1DR7_BIT13_MASK 8192U +#define ATD1DR7_BIT14_MASK 16384U +#define ATD1DR7_BIT15_MASK 32768U +#define ATD1DR7_BIT_6_MASK 65472U +#define ATD1DR7_BIT_6_BITNUM 6U + + +/*** CAN0CTL0 - MSCAN 0 Control 0 Register; 0x00000140 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN0CTL0STR; +extern volatile CAN0CTL0STR _CAN0CTL0 @(REG_BASE + 0x00000140UL); +#define CAN0CTL0 _CAN0CTL0.Byte +#define CAN0CTL0_INITRQ _CAN0CTL0.Bits.INITRQ +#define CAN0CTL0_SLPRQ _CAN0CTL0.Bits.SLPRQ +#define CAN0CTL0_WUPE _CAN0CTL0.Bits.WUPE +#define CAN0CTL0_TIME _CAN0CTL0.Bits.TIME +#define CAN0CTL0_SYNCH _CAN0CTL0.Bits.SYNCH +#define CAN0CTL0_CSWAI _CAN0CTL0.Bits.CSWAI +#define CAN0CTL0_RXACT _CAN0CTL0.Bits.RXACT +#define CAN0CTL0_RXFRM _CAN0CTL0.Bits.RXFRM +/* CAN0CTL_ARR: Access 2 CAN0CTLx registers in an array */ +#define CAN0CTL_ARR ((volatile byte *) &CAN0CTL0) + +#define CAN0CTL0_INITRQ_MASK 1U +#define CAN0CTL0_SLPRQ_MASK 2U +#define CAN0CTL0_WUPE_MASK 4U +#define CAN0CTL0_TIME_MASK 8U +#define CAN0CTL0_SYNCH_MASK 16U +#define CAN0CTL0_CSWAI_MASK 32U +#define CAN0CTL0_RXACT_MASK 64U +#define CAN0CTL0_RXFRM_MASK 128U + + +/*** CAN0CTL1 - MSCAN 0 Control 1 Register; 0x00000141 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN 0 Clock Source */ + byte CANE :1; /* MSCAN 0 Enable */ + } Bits; +} CAN0CTL1STR; +extern volatile CAN0CTL1STR _CAN0CTL1 @(REG_BASE + 0x00000141UL); +#define CAN0CTL1 _CAN0CTL1.Byte +#define CAN0CTL1_INITAK _CAN0CTL1.Bits.INITAK +#define CAN0CTL1_SLPAK _CAN0CTL1.Bits.SLPAK +#define CAN0CTL1_WUPM _CAN0CTL1.Bits.WUPM +#define CAN0CTL1_LISTEN _CAN0CTL1.Bits.LISTEN +#define CAN0CTL1_LOOPB _CAN0CTL1.Bits.LOOPB +#define CAN0CTL1_CLKSRC _CAN0CTL1.Bits.CLKSRC +#define CAN0CTL1_CANE _CAN0CTL1.Bits.CANE + +#define CAN0CTL1_INITAK_MASK 1U +#define CAN0CTL1_SLPAK_MASK 2U +#define CAN0CTL1_WUPM_MASK 4U +#define CAN0CTL1_LISTEN_MASK 16U +#define CAN0CTL1_LOOPB_MASK 32U +#define CAN0CTL1_CLKSRC_MASK 64U +#define CAN0CTL1_CANE_MASK 128U + + +/*** CAN0BTR0 - MSCAN 0 Bus Timing Register 0; 0x00000142 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN0BTR0STR; +extern volatile CAN0BTR0STR _CAN0BTR0 @(REG_BASE + 0x00000142UL); +#define CAN0BTR0 _CAN0BTR0.Byte +#define CAN0BTR0_BRP0 _CAN0BTR0.Bits.BRP0 +#define CAN0BTR0_BRP1 _CAN0BTR0.Bits.BRP1 +#define CAN0BTR0_BRP2 _CAN0BTR0.Bits.BRP2 +#define CAN0BTR0_BRP3 _CAN0BTR0.Bits.BRP3 +#define CAN0BTR0_BRP4 _CAN0BTR0.Bits.BRP4 +#define CAN0BTR0_BRP5 _CAN0BTR0.Bits.BRP5 +#define CAN0BTR0_SJW0 _CAN0BTR0.Bits.SJW0 +#define CAN0BTR0_SJW1 _CAN0BTR0.Bits.SJW1 +/* CAN0BTR_ARR: Access 2 CAN0BTRx registers in an array */ +#define CAN0BTR_ARR ((volatile byte *) &CAN0BTR0) +#define CAN0BTR0_BRP _CAN0BTR0.MergedBits.grpBRP +#define CAN0BTR0_SJW _CAN0BTR0.MergedBits.grpSJW + +#define CAN0BTR0_BRP0_MASK 1U +#define CAN0BTR0_BRP1_MASK 2U +#define CAN0BTR0_BRP2_MASK 4U +#define CAN0BTR0_BRP3_MASK 8U +#define CAN0BTR0_BRP4_MASK 16U +#define CAN0BTR0_BRP5_MASK 32U +#define CAN0BTR0_SJW0_MASK 64U +#define CAN0BTR0_SJW1_MASK 128U +#define CAN0BTR0_BRP_MASK 63U +#define CAN0BTR0_BRP_BITNUM 0U +#define CAN0BTR0_SJW_MASK 192U +#define CAN0BTR0_SJW_BITNUM 6U + + +/*** CAN0BTR1 - MSCAN 0 Bus Timing Register 1; 0x00000143 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 10 */ + byte TSEG11 :1; /* Time Segment 11 */ + byte TSEG12 :1; /* Time Segment 12 */ + byte TSEG13 :1; /* Time Segment 13 */ + byte TSEG20 :1; /* Time Segment 20 */ + byte TSEG21 :1; /* Time Segment 21 */ + byte TSEG22 :1; /* Time Segment 22 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN0BTR1STR; +extern volatile CAN0BTR1STR _CAN0BTR1 @(REG_BASE + 0x00000143UL); +#define CAN0BTR1 _CAN0BTR1.Byte +#define CAN0BTR1_TSEG10 _CAN0BTR1.Bits.TSEG10 +#define CAN0BTR1_TSEG11 _CAN0BTR1.Bits.TSEG11 +#define CAN0BTR1_TSEG12 _CAN0BTR1.Bits.TSEG12 +#define CAN0BTR1_TSEG13 _CAN0BTR1.Bits.TSEG13 +#define CAN0BTR1_TSEG20 _CAN0BTR1.Bits.TSEG20 +#define CAN0BTR1_TSEG21 _CAN0BTR1.Bits.TSEG21 +#define CAN0BTR1_TSEG22 _CAN0BTR1.Bits.TSEG22 +#define CAN0BTR1_SAMP _CAN0BTR1.Bits.SAMP +#define CAN0BTR1_TSEG_10 _CAN0BTR1.MergedBits.grpTSEG_10 +#define CAN0BTR1_TSEG_20 _CAN0BTR1.MergedBits.grpTSEG_20 +#define CAN0BTR1_TSEG CAN0BTR1_TSEG_10 + +#define CAN0BTR1_TSEG10_MASK 1U +#define CAN0BTR1_TSEG11_MASK 2U +#define CAN0BTR1_TSEG12_MASK 4U +#define CAN0BTR1_TSEG13_MASK 8U +#define CAN0BTR1_TSEG20_MASK 16U +#define CAN0BTR1_TSEG21_MASK 32U +#define CAN0BTR1_TSEG22_MASK 64U +#define CAN0BTR1_SAMP_MASK 128U +#define CAN0BTR1_TSEG_10_MASK 15U +#define CAN0BTR1_TSEG_10_BITNUM 0U +#define CAN0BTR1_TSEG_20_MASK 112U +#define CAN0BTR1_TSEG_20_BITNUM 4U + + +/*** CAN0RFLG - MSCAN 0 Receiver Flag Register; 0x00000144 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN0RFLGSTR; +extern volatile CAN0RFLGSTR _CAN0RFLG @(REG_BASE + 0x00000144UL); +#define CAN0RFLG _CAN0RFLG.Byte +#define CAN0RFLG_RXF _CAN0RFLG.Bits.RXF +#define CAN0RFLG_OVRIF _CAN0RFLG.Bits.OVRIF +#define CAN0RFLG_TSTAT0 _CAN0RFLG.Bits.TSTAT0 +#define CAN0RFLG_TSTAT1 _CAN0RFLG.Bits.TSTAT1 +#define CAN0RFLG_RSTAT0 _CAN0RFLG.Bits.RSTAT0 +#define CAN0RFLG_RSTAT1 _CAN0RFLG.Bits.RSTAT1 +#define CAN0RFLG_CSCIF _CAN0RFLG.Bits.CSCIF +#define CAN0RFLG_WUPIF _CAN0RFLG.Bits.WUPIF +#define CAN0RFLG_TSTAT _CAN0RFLG.MergedBits.grpTSTAT +#define CAN0RFLG_RSTAT _CAN0RFLG.MergedBits.grpRSTAT + +#define CAN0RFLG_RXF_MASK 1U +#define CAN0RFLG_OVRIF_MASK 2U +#define CAN0RFLG_TSTAT0_MASK 4U +#define CAN0RFLG_TSTAT1_MASK 8U +#define CAN0RFLG_RSTAT0_MASK 16U +#define CAN0RFLG_RSTAT1_MASK 32U +#define CAN0RFLG_CSCIF_MASK 64U +#define CAN0RFLG_WUPIF_MASK 128U +#define CAN0RFLG_TSTAT_MASK 12U +#define CAN0RFLG_TSTAT_BITNUM 2U +#define CAN0RFLG_RSTAT_MASK 48U +#define CAN0RFLG_RSTAT_BITNUM 4U + + +/*** CAN0RIER - MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN0RIERSTR; +extern volatile CAN0RIERSTR _CAN0RIER @(REG_BASE + 0x00000145UL); +#define CAN0RIER _CAN0RIER.Byte +#define CAN0RIER_RXFIE _CAN0RIER.Bits.RXFIE +#define CAN0RIER_OVRIE _CAN0RIER.Bits.OVRIE +#define CAN0RIER_TSTATE0 _CAN0RIER.Bits.TSTATE0 +#define CAN0RIER_TSTATE1 _CAN0RIER.Bits.TSTATE1 +#define CAN0RIER_RSTATE0 _CAN0RIER.Bits.RSTATE0 +#define CAN0RIER_RSTATE1 _CAN0RIER.Bits.RSTATE1 +#define CAN0RIER_CSCIE _CAN0RIER.Bits.CSCIE +#define CAN0RIER_WUPIE _CAN0RIER.Bits.WUPIE +#define CAN0RIER_TSTATE _CAN0RIER.MergedBits.grpTSTATE +#define CAN0RIER_RSTATE _CAN0RIER.MergedBits.grpRSTATE + +#define CAN0RIER_RXFIE_MASK 1U +#define CAN0RIER_OVRIE_MASK 2U +#define CAN0RIER_TSTATE0_MASK 4U +#define CAN0RIER_TSTATE1_MASK 8U +#define CAN0RIER_RSTATE0_MASK 16U +#define CAN0RIER_RSTATE1_MASK 32U +#define CAN0RIER_CSCIE_MASK 64U +#define CAN0RIER_WUPIE_MASK 128U +#define CAN0RIER_TSTATE_MASK 12U +#define CAN0RIER_TSTATE_BITNUM 2U +#define CAN0RIER_RSTATE_MASK 48U +#define CAN0RIER_RSTATE_BITNUM 4U + + +/*** CAN0TFLG - MSCAN 0 Transmitter Flag Register; 0x00000146 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TFLGSTR; +extern volatile CAN0TFLGSTR _CAN0TFLG @(REG_BASE + 0x00000146UL); +#define CAN0TFLG _CAN0TFLG.Byte +#define CAN0TFLG_TXE0 _CAN0TFLG.Bits.TXE0 +#define CAN0TFLG_TXE1 _CAN0TFLG.Bits.TXE1 +#define CAN0TFLG_TXE2 _CAN0TFLG.Bits.TXE2 +#define CAN0TFLG_TXE _CAN0TFLG.MergedBits.grpTXE + +#define CAN0TFLG_TXE0_MASK 1U +#define CAN0TFLG_TXE1_MASK 2U +#define CAN0TFLG_TXE2_MASK 4U +#define CAN0TFLG_TXE_MASK 7U +#define CAN0TFLG_TXE_BITNUM 0U + + +/*** CAN0TIER - MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TIERSTR; +extern volatile CAN0TIERSTR _CAN0TIER @(REG_BASE + 0x00000147UL); +#define CAN0TIER _CAN0TIER.Byte +#define CAN0TIER_TXEIE0 _CAN0TIER.Bits.TXEIE0 +#define CAN0TIER_TXEIE1 _CAN0TIER.Bits.TXEIE1 +#define CAN0TIER_TXEIE2 _CAN0TIER.Bits.TXEIE2 +#define CAN0TIER_TXEIE _CAN0TIER.MergedBits.grpTXEIE + +#define CAN0TIER_TXEIE0_MASK 1U +#define CAN0TIER_TXEIE1_MASK 2U +#define CAN0TIER_TXEIE2_MASK 4U +#define CAN0TIER_TXEIE_MASK 7U +#define CAN0TIER_TXEIE_BITNUM 0U + + +/*** CAN0TARQ - MSCAN 0 Transmitter Message Abort Request; 0x00000148 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TARQSTR; +extern volatile CAN0TARQSTR _CAN0TARQ @(REG_BASE + 0x00000148UL); +#define CAN0TARQ _CAN0TARQ.Byte +#define CAN0TARQ_ABTRQ0 _CAN0TARQ.Bits.ABTRQ0 +#define CAN0TARQ_ABTRQ1 _CAN0TARQ.Bits.ABTRQ1 +#define CAN0TARQ_ABTRQ2 _CAN0TARQ.Bits.ABTRQ2 +#define CAN0TARQ_ABTRQ _CAN0TARQ.MergedBits.grpABTRQ + +#define CAN0TARQ_ABTRQ0_MASK 1U +#define CAN0TARQ_ABTRQ1_MASK 2U +#define CAN0TARQ_ABTRQ2_MASK 4U +#define CAN0TARQ_ABTRQ_MASK 7U +#define CAN0TARQ_ABTRQ_BITNUM 0U + + +/*** CAN0TAAK - MSCAN 0 Transmitter Message Abort Control; 0x00000149 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TAAKSTR; +extern volatile CAN0TAAKSTR _CAN0TAAK @(REG_BASE + 0x00000149UL); +#define CAN0TAAK _CAN0TAAK.Byte +#define CAN0TAAK_ABTAK0 _CAN0TAAK.Bits.ABTAK0 +#define CAN0TAAK_ABTAK1 _CAN0TAAK.Bits.ABTAK1 +#define CAN0TAAK_ABTAK2 _CAN0TAAK.Bits.ABTAK2 +#define CAN0TAAK_ABTAK _CAN0TAAK.MergedBits.grpABTAK + +#define CAN0TAAK_ABTAK0_MASK 1U +#define CAN0TAAK_ABTAK1_MASK 2U +#define CAN0TAAK_ABTAK2_MASK 4U +#define CAN0TAAK_ABTAK_MASK 7U +#define CAN0TAAK_ABTAK_BITNUM 0U + + +/*** CAN0TBSEL - MSCAN 0 Transmit Buffer Selection; 0x0000014A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TBSELSTR; +extern volatile CAN0TBSELSTR _CAN0TBSEL @(REG_BASE + 0x0000014AUL); +#define CAN0TBSEL _CAN0TBSEL.Byte +#define CAN0TBSEL_TX0 _CAN0TBSEL.Bits.TX0 +#define CAN0TBSEL_TX1 _CAN0TBSEL.Bits.TX1 +#define CAN0TBSEL_TX2 _CAN0TBSEL.Bits.TX2 +#define CAN0TBSEL_TX _CAN0TBSEL.MergedBits.grpTX + +#define CAN0TBSEL_TX0_MASK 1U +#define CAN0TBSEL_TX1_MASK 2U +#define CAN0TBSEL_TX2_MASK 4U +#define CAN0TBSEL_TX_MASK 7U +#define CAN0TBSEL_TX_BITNUM 0U + + +/*** CAN0IDAC - MSCAN 0 Identifier Acceptance Control Register; 0x0000014B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN0IDACSTR; +extern volatile CAN0IDACSTR _CAN0IDAC @(REG_BASE + 0x0000014BUL); +#define CAN0IDAC _CAN0IDAC.Byte +#define CAN0IDAC_IDHIT0 _CAN0IDAC.Bits.IDHIT0 +#define CAN0IDAC_IDHIT1 _CAN0IDAC.Bits.IDHIT1 +#define CAN0IDAC_IDHIT2 _CAN0IDAC.Bits.IDHIT2 +#define CAN0IDAC_IDAM0 _CAN0IDAC.Bits.IDAM0 +#define CAN0IDAC_IDAM1 _CAN0IDAC.Bits.IDAM1 +#define CAN0IDAC_IDHIT _CAN0IDAC.MergedBits.grpIDHIT +#define CAN0IDAC_IDAM _CAN0IDAC.MergedBits.grpIDAM + +#define CAN0IDAC_IDHIT0_MASK 1U +#define CAN0IDAC_IDHIT1_MASK 2U +#define CAN0IDAC_IDHIT2_MASK 4U +#define CAN0IDAC_IDAM0_MASK 16U +#define CAN0IDAC_IDAM1_MASK 32U +#define CAN0IDAC_IDHIT_MASK 7U +#define CAN0IDAC_IDHIT_BITNUM 0U +#define CAN0IDAC_IDAM_MASK 48U +#define CAN0IDAC_IDAM_BITNUM 4U + + +/*** CAN0RXERR - MSCAN 0 Receive Error Counter Register; 0x0000014E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; +} CAN0RXERRSTR; +extern volatile CAN0RXERRSTR _CAN0RXERR @(REG_BASE + 0x0000014EUL); +#define CAN0RXERR _CAN0RXERR.Byte +#define CAN0RXERR_RXERR0 _CAN0RXERR.Bits.RXERR0 +#define CAN0RXERR_RXERR1 _CAN0RXERR.Bits.RXERR1 +#define CAN0RXERR_RXERR2 _CAN0RXERR.Bits.RXERR2 +#define CAN0RXERR_RXERR3 _CAN0RXERR.Bits.RXERR3 +#define CAN0RXERR_RXERR4 _CAN0RXERR.Bits.RXERR4 +#define CAN0RXERR_RXERR5 _CAN0RXERR.Bits.RXERR5 +#define CAN0RXERR_RXERR6 _CAN0RXERR.Bits.RXERR6 +#define CAN0RXERR_RXERR7 _CAN0RXERR.Bits.RXERR7 + +#define CAN0RXERR_RXERR0_MASK 1U +#define CAN0RXERR_RXERR1_MASK 2U +#define CAN0RXERR_RXERR2_MASK 4U +#define CAN0RXERR_RXERR3_MASK 8U +#define CAN0RXERR_RXERR4_MASK 16U +#define CAN0RXERR_RXERR5_MASK 32U +#define CAN0RXERR_RXERR6_MASK 64U +#define CAN0RXERR_RXERR7_MASK 128U + + +/*** CAN0TXERR - MSCAN 0 Transmit Error Counter Register; 0x0000014F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; +} CAN0TXERRSTR; +extern volatile CAN0TXERRSTR _CAN0TXERR @(REG_BASE + 0x0000014FUL); +#define CAN0TXERR _CAN0TXERR.Byte +#define CAN0TXERR_TXERR0 _CAN0TXERR.Bits.TXERR0 +#define CAN0TXERR_TXERR1 _CAN0TXERR.Bits.TXERR1 +#define CAN0TXERR_TXERR2 _CAN0TXERR.Bits.TXERR2 +#define CAN0TXERR_TXERR3 _CAN0TXERR.Bits.TXERR3 +#define CAN0TXERR_TXERR4 _CAN0TXERR.Bits.TXERR4 +#define CAN0TXERR_TXERR5 _CAN0TXERR.Bits.TXERR5 +#define CAN0TXERR_TXERR6 _CAN0TXERR.Bits.TXERR6 +#define CAN0TXERR_TXERR7 _CAN0TXERR.Bits.TXERR7 + +#define CAN0TXERR_TXERR0_MASK 1U +#define CAN0TXERR_TXERR1_MASK 2U +#define CAN0TXERR_TXERR2_MASK 4U +#define CAN0TXERR_TXERR3_MASK 8U +#define CAN0TXERR_TXERR4_MASK 16U +#define CAN0TXERR_TXERR5_MASK 32U +#define CAN0TXERR_TXERR6_MASK 64U +#define CAN0TXERR_TXERR7_MASK 128U + + +/*** CAN0IDAR0 - MSCAN 0 Identifier Acceptance Register 0; 0x00000150 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR0STR; +extern volatile CAN0IDAR0STR _CAN0IDAR0 @(REG_BASE + 0x00000150UL); +#define CAN0IDAR0 _CAN0IDAR0.Byte +#define CAN0IDAR0_AC0 _CAN0IDAR0.Bits.AC0 +#define CAN0IDAR0_AC1 _CAN0IDAR0.Bits.AC1 +#define CAN0IDAR0_AC2 _CAN0IDAR0.Bits.AC2 +#define CAN0IDAR0_AC3 _CAN0IDAR0.Bits.AC3 +#define CAN0IDAR0_AC4 _CAN0IDAR0.Bits.AC4 +#define CAN0IDAR0_AC5 _CAN0IDAR0.Bits.AC5 +#define CAN0IDAR0_AC6 _CAN0IDAR0.Bits.AC6 +#define CAN0IDAR0_AC7 _CAN0IDAR0.Bits.AC7 +/* CAN0IDAR_ARR: Access 4 CAN0IDARx registers in an array */ +#define CAN0IDAR_ARR ((volatile byte *) &CAN0IDAR0) + +#define CAN0IDAR0_AC0_MASK 1U +#define CAN0IDAR0_AC1_MASK 2U +#define CAN0IDAR0_AC2_MASK 4U +#define CAN0IDAR0_AC3_MASK 8U +#define CAN0IDAR0_AC4_MASK 16U +#define CAN0IDAR0_AC5_MASK 32U +#define CAN0IDAR0_AC6_MASK 64U +#define CAN0IDAR0_AC7_MASK 128U + + +/*** CAN0IDAR1 - MSCAN 0 Identifier Acceptance Register 1; 0x00000151 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR1STR; +extern volatile CAN0IDAR1STR _CAN0IDAR1 @(REG_BASE + 0x00000151UL); +#define CAN0IDAR1 _CAN0IDAR1.Byte +#define CAN0IDAR1_AC0 _CAN0IDAR1.Bits.AC0 +#define CAN0IDAR1_AC1 _CAN0IDAR1.Bits.AC1 +#define CAN0IDAR1_AC2 _CAN0IDAR1.Bits.AC2 +#define CAN0IDAR1_AC3 _CAN0IDAR1.Bits.AC3 +#define CAN0IDAR1_AC4 _CAN0IDAR1.Bits.AC4 +#define CAN0IDAR1_AC5 _CAN0IDAR1.Bits.AC5 +#define CAN0IDAR1_AC6 _CAN0IDAR1.Bits.AC6 +#define CAN0IDAR1_AC7 _CAN0IDAR1.Bits.AC7 + +#define CAN0IDAR1_AC0_MASK 1U +#define CAN0IDAR1_AC1_MASK 2U +#define CAN0IDAR1_AC2_MASK 4U +#define CAN0IDAR1_AC3_MASK 8U +#define CAN0IDAR1_AC4_MASK 16U +#define CAN0IDAR1_AC5_MASK 32U +#define CAN0IDAR1_AC6_MASK 64U +#define CAN0IDAR1_AC7_MASK 128U + + +/*** CAN0IDAR2 - MSCAN 0 Identifier Acceptance Register 2; 0x00000152 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR2STR; +extern volatile CAN0IDAR2STR _CAN0IDAR2 @(REG_BASE + 0x00000152UL); +#define CAN0IDAR2 _CAN0IDAR2.Byte +#define CAN0IDAR2_AC0 _CAN0IDAR2.Bits.AC0 +#define CAN0IDAR2_AC1 _CAN0IDAR2.Bits.AC1 +#define CAN0IDAR2_AC2 _CAN0IDAR2.Bits.AC2 +#define CAN0IDAR2_AC3 _CAN0IDAR2.Bits.AC3 +#define CAN0IDAR2_AC4 _CAN0IDAR2.Bits.AC4 +#define CAN0IDAR2_AC5 _CAN0IDAR2.Bits.AC5 +#define CAN0IDAR2_AC6 _CAN0IDAR2.Bits.AC6 +#define CAN0IDAR2_AC7 _CAN0IDAR2.Bits.AC7 + +#define CAN0IDAR2_AC0_MASK 1U +#define CAN0IDAR2_AC1_MASK 2U +#define CAN0IDAR2_AC2_MASK 4U +#define CAN0IDAR2_AC3_MASK 8U +#define CAN0IDAR2_AC4_MASK 16U +#define CAN0IDAR2_AC5_MASK 32U +#define CAN0IDAR2_AC6_MASK 64U +#define CAN0IDAR2_AC7_MASK 128U + + +/*** CAN0IDAR3 - MSCAN 0 Identifier Acceptance Register 3; 0x00000153 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR3STR; +extern volatile CAN0IDAR3STR _CAN0IDAR3 @(REG_BASE + 0x00000153UL); +#define CAN0IDAR3 _CAN0IDAR3.Byte +#define CAN0IDAR3_AC0 _CAN0IDAR3.Bits.AC0 +#define CAN0IDAR3_AC1 _CAN0IDAR3.Bits.AC1 +#define CAN0IDAR3_AC2 _CAN0IDAR3.Bits.AC2 +#define CAN0IDAR3_AC3 _CAN0IDAR3.Bits.AC3 +#define CAN0IDAR3_AC4 _CAN0IDAR3.Bits.AC4 +#define CAN0IDAR3_AC5 _CAN0IDAR3.Bits.AC5 +#define CAN0IDAR3_AC6 _CAN0IDAR3.Bits.AC6 +#define CAN0IDAR3_AC7 _CAN0IDAR3.Bits.AC7 + +#define CAN0IDAR3_AC0_MASK 1U +#define CAN0IDAR3_AC1_MASK 2U +#define CAN0IDAR3_AC2_MASK 4U +#define CAN0IDAR3_AC3_MASK 8U +#define CAN0IDAR3_AC4_MASK 16U +#define CAN0IDAR3_AC5_MASK 32U +#define CAN0IDAR3_AC6_MASK 64U +#define CAN0IDAR3_AC7_MASK 128U + + +/*** CAN0IDMR0 - MSCAN 0 Identifier Mask Register 0; 0x00000154 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR0STR; +extern volatile CAN0IDMR0STR _CAN0IDMR0 @(REG_BASE + 0x00000154UL); +#define CAN0IDMR0 _CAN0IDMR0.Byte +#define CAN0IDMR0_AM0 _CAN0IDMR0.Bits.AM0 +#define CAN0IDMR0_AM1 _CAN0IDMR0.Bits.AM1 +#define CAN0IDMR0_AM2 _CAN0IDMR0.Bits.AM2 +#define CAN0IDMR0_AM3 _CAN0IDMR0.Bits.AM3 +#define CAN0IDMR0_AM4 _CAN0IDMR0.Bits.AM4 +#define CAN0IDMR0_AM5 _CAN0IDMR0.Bits.AM5 +#define CAN0IDMR0_AM6 _CAN0IDMR0.Bits.AM6 +#define CAN0IDMR0_AM7 _CAN0IDMR0.Bits.AM7 +/* CAN0IDMR_ARR: Access 4 CAN0IDMRx registers in an array */ +#define CAN0IDMR_ARR ((volatile byte *) &CAN0IDMR0) + +#define CAN0IDMR0_AM0_MASK 1U +#define CAN0IDMR0_AM1_MASK 2U +#define CAN0IDMR0_AM2_MASK 4U +#define CAN0IDMR0_AM3_MASK 8U +#define CAN0IDMR0_AM4_MASK 16U +#define CAN0IDMR0_AM5_MASK 32U +#define CAN0IDMR0_AM6_MASK 64U +#define CAN0IDMR0_AM7_MASK 128U + + +/*** CAN0IDMR1 - MSCAN 0 Identifier Mask Register 1; 0x00000155 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR1STR; +extern volatile CAN0IDMR1STR _CAN0IDMR1 @(REG_BASE + 0x00000155UL); +#define CAN0IDMR1 _CAN0IDMR1.Byte +#define CAN0IDMR1_AM0 _CAN0IDMR1.Bits.AM0 +#define CAN0IDMR1_AM1 _CAN0IDMR1.Bits.AM1 +#define CAN0IDMR1_AM2 _CAN0IDMR1.Bits.AM2 +#define CAN0IDMR1_AM3 _CAN0IDMR1.Bits.AM3 +#define CAN0IDMR1_AM4 _CAN0IDMR1.Bits.AM4 +#define CAN0IDMR1_AM5 _CAN0IDMR1.Bits.AM5 +#define CAN0IDMR1_AM6 _CAN0IDMR1.Bits.AM6 +#define CAN0IDMR1_AM7 _CAN0IDMR1.Bits.AM7 + +#define CAN0IDMR1_AM0_MASK 1U +#define CAN0IDMR1_AM1_MASK 2U +#define CAN0IDMR1_AM2_MASK 4U +#define CAN0IDMR1_AM3_MASK 8U +#define CAN0IDMR1_AM4_MASK 16U +#define CAN0IDMR1_AM5_MASK 32U +#define CAN0IDMR1_AM6_MASK 64U +#define CAN0IDMR1_AM7_MASK 128U + + +/*** CAN0IDMR2 - MSCAN 0 Identifier Mask Register 2; 0x00000156 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR2STR; +extern volatile CAN0IDMR2STR _CAN0IDMR2 @(REG_BASE + 0x00000156UL); +#define CAN0IDMR2 _CAN0IDMR2.Byte +#define CAN0IDMR2_AM0 _CAN0IDMR2.Bits.AM0 +#define CAN0IDMR2_AM1 _CAN0IDMR2.Bits.AM1 +#define CAN0IDMR2_AM2 _CAN0IDMR2.Bits.AM2 +#define CAN0IDMR2_AM3 _CAN0IDMR2.Bits.AM3 +#define CAN0IDMR2_AM4 _CAN0IDMR2.Bits.AM4 +#define CAN0IDMR2_AM5 _CAN0IDMR2.Bits.AM5 +#define CAN0IDMR2_AM6 _CAN0IDMR2.Bits.AM6 +#define CAN0IDMR2_AM7 _CAN0IDMR2.Bits.AM7 + +#define CAN0IDMR2_AM0_MASK 1U +#define CAN0IDMR2_AM1_MASK 2U +#define CAN0IDMR2_AM2_MASK 4U +#define CAN0IDMR2_AM3_MASK 8U +#define CAN0IDMR2_AM4_MASK 16U +#define CAN0IDMR2_AM5_MASK 32U +#define CAN0IDMR2_AM6_MASK 64U +#define CAN0IDMR2_AM7_MASK 128U + + +/*** CAN0IDMR3 - MSCAN 0 Identifier Mask Register 3; 0x00000157 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR3STR; +extern volatile CAN0IDMR3STR _CAN0IDMR3 @(REG_BASE + 0x00000157UL); +#define CAN0IDMR3 _CAN0IDMR3.Byte +#define CAN0IDMR3_AM0 _CAN0IDMR3.Bits.AM0 +#define CAN0IDMR3_AM1 _CAN0IDMR3.Bits.AM1 +#define CAN0IDMR3_AM2 _CAN0IDMR3.Bits.AM2 +#define CAN0IDMR3_AM3 _CAN0IDMR3.Bits.AM3 +#define CAN0IDMR3_AM4 _CAN0IDMR3.Bits.AM4 +#define CAN0IDMR3_AM5 _CAN0IDMR3.Bits.AM5 +#define CAN0IDMR3_AM6 _CAN0IDMR3.Bits.AM6 +#define CAN0IDMR3_AM7 _CAN0IDMR3.Bits.AM7 + +#define CAN0IDMR3_AM0_MASK 1U +#define CAN0IDMR3_AM1_MASK 2U +#define CAN0IDMR3_AM2_MASK 4U +#define CAN0IDMR3_AM3_MASK 8U +#define CAN0IDMR3_AM4_MASK 16U +#define CAN0IDMR3_AM5_MASK 32U +#define CAN0IDMR3_AM6_MASK 64U +#define CAN0IDMR3_AM7_MASK 128U + + +/*** CAN0IDAR4 - MSCAN 0 Identifier Acceptance Register 4; 0x00000158 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR4STR; +extern volatile CAN0IDAR4STR _CAN0IDAR4 @(REG_BASE + 0x00000158UL); +#define CAN0IDAR4 _CAN0IDAR4.Byte +#define CAN0IDAR4_AC0 _CAN0IDAR4.Bits.AC0 +#define CAN0IDAR4_AC1 _CAN0IDAR4.Bits.AC1 +#define CAN0IDAR4_AC2 _CAN0IDAR4.Bits.AC2 +#define CAN0IDAR4_AC3 _CAN0IDAR4.Bits.AC3 +#define CAN0IDAR4_AC4 _CAN0IDAR4.Bits.AC4 +#define CAN0IDAR4_AC5 _CAN0IDAR4.Bits.AC5 +#define CAN0IDAR4_AC6 _CAN0IDAR4.Bits.AC6 +#define CAN0IDAR4_AC7 _CAN0IDAR4.Bits.AC7 + +#define CAN0IDAR4_AC0_MASK 1U +#define CAN0IDAR4_AC1_MASK 2U +#define CAN0IDAR4_AC2_MASK 4U +#define CAN0IDAR4_AC3_MASK 8U +#define CAN0IDAR4_AC4_MASK 16U +#define CAN0IDAR4_AC5_MASK 32U +#define CAN0IDAR4_AC6_MASK 64U +#define CAN0IDAR4_AC7_MASK 128U + + +/*** CAN0IDAR5 - MSCAN 0 Identifier Acceptance Register 5; 0x00000159 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR5STR; +extern volatile CAN0IDAR5STR _CAN0IDAR5 @(REG_BASE + 0x00000159UL); +#define CAN0IDAR5 _CAN0IDAR5.Byte +#define CAN0IDAR5_AC0 _CAN0IDAR5.Bits.AC0 +#define CAN0IDAR5_AC1 _CAN0IDAR5.Bits.AC1 +#define CAN0IDAR5_AC2 _CAN0IDAR5.Bits.AC2 +#define CAN0IDAR5_AC3 _CAN0IDAR5.Bits.AC3 +#define CAN0IDAR5_AC4 _CAN0IDAR5.Bits.AC4 +#define CAN0IDAR5_AC5 _CAN0IDAR5.Bits.AC5 +#define CAN0IDAR5_AC6 _CAN0IDAR5.Bits.AC6 +#define CAN0IDAR5_AC7 _CAN0IDAR5.Bits.AC7 + +#define CAN0IDAR5_AC0_MASK 1U +#define CAN0IDAR5_AC1_MASK 2U +#define CAN0IDAR5_AC2_MASK 4U +#define CAN0IDAR5_AC3_MASK 8U +#define CAN0IDAR5_AC4_MASK 16U +#define CAN0IDAR5_AC5_MASK 32U +#define CAN0IDAR5_AC6_MASK 64U +#define CAN0IDAR5_AC7_MASK 128U + + +/*** CAN0IDAR6 - MSCAN 0 Identifier Acceptance Register 6; 0x0000015A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR6STR; +extern volatile CAN0IDAR6STR _CAN0IDAR6 @(REG_BASE + 0x0000015AUL); +#define CAN0IDAR6 _CAN0IDAR6.Byte +#define CAN0IDAR6_AC0 _CAN0IDAR6.Bits.AC0 +#define CAN0IDAR6_AC1 _CAN0IDAR6.Bits.AC1 +#define CAN0IDAR6_AC2 _CAN0IDAR6.Bits.AC2 +#define CAN0IDAR6_AC3 _CAN0IDAR6.Bits.AC3 +#define CAN0IDAR6_AC4 _CAN0IDAR6.Bits.AC4 +#define CAN0IDAR6_AC5 _CAN0IDAR6.Bits.AC5 +#define CAN0IDAR6_AC6 _CAN0IDAR6.Bits.AC6 +#define CAN0IDAR6_AC7 _CAN0IDAR6.Bits.AC7 + +#define CAN0IDAR6_AC0_MASK 1U +#define CAN0IDAR6_AC1_MASK 2U +#define CAN0IDAR6_AC2_MASK 4U +#define CAN0IDAR6_AC3_MASK 8U +#define CAN0IDAR6_AC4_MASK 16U +#define CAN0IDAR6_AC5_MASK 32U +#define CAN0IDAR6_AC6_MASK 64U +#define CAN0IDAR6_AC7_MASK 128U + + +/*** CAN0IDAR7 - MSCAN 0 Identifier Acceptance Register 7; 0x0000015B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN0IDAR7STR; +extern volatile CAN0IDAR7STR _CAN0IDAR7 @(REG_BASE + 0x0000015BUL); +#define CAN0IDAR7 _CAN0IDAR7.Byte +#define CAN0IDAR7_AC0 _CAN0IDAR7.Bits.AC0 +#define CAN0IDAR7_AC1 _CAN0IDAR7.Bits.AC1 +#define CAN0IDAR7_AC2 _CAN0IDAR7.Bits.AC2 +#define CAN0IDAR7_AC3 _CAN0IDAR7.Bits.AC3 +#define CAN0IDAR7_AC4 _CAN0IDAR7.Bits.AC4 +#define CAN0IDAR7_AC5 _CAN0IDAR7.Bits.AC5 +#define CAN0IDAR7_AC6 _CAN0IDAR7.Bits.AC6 +#define CAN0IDAR7_AC7 _CAN0IDAR7.Bits.AC7 + +#define CAN0IDAR7_AC0_MASK 1U +#define CAN0IDAR7_AC1_MASK 2U +#define CAN0IDAR7_AC2_MASK 4U +#define CAN0IDAR7_AC3_MASK 8U +#define CAN0IDAR7_AC4_MASK 16U +#define CAN0IDAR7_AC5_MASK 32U +#define CAN0IDAR7_AC6_MASK 64U +#define CAN0IDAR7_AC7_MASK 128U + + +/*** CAN0IDMR4 - MSCAN 0 Identifier Mask Register 4; 0x0000015C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR4STR; +extern volatile CAN0IDMR4STR _CAN0IDMR4 @(REG_BASE + 0x0000015CUL); +#define CAN0IDMR4 _CAN0IDMR4.Byte +#define CAN0IDMR4_AM0 _CAN0IDMR4.Bits.AM0 +#define CAN0IDMR4_AM1 _CAN0IDMR4.Bits.AM1 +#define CAN0IDMR4_AM2 _CAN0IDMR4.Bits.AM2 +#define CAN0IDMR4_AM3 _CAN0IDMR4.Bits.AM3 +#define CAN0IDMR4_AM4 _CAN0IDMR4.Bits.AM4 +#define CAN0IDMR4_AM5 _CAN0IDMR4.Bits.AM5 +#define CAN0IDMR4_AM6 _CAN0IDMR4.Bits.AM6 +#define CAN0IDMR4_AM7 _CAN0IDMR4.Bits.AM7 + +#define CAN0IDMR4_AM0_MASK 1U +#define CAN0IDMR4_AM1_MASK 2U +#define CAN0IDMR4_AM2_MASK 4U +#define CAN0IDMR4_AM3_MASK 8U +#define CAN0IDMR4_AM4_MASK 16U +#define CAN0IDMR4_AM5_MASK 32U +#define CAN0IDMR4_AM6_MASK 64U +#define CAN0IDMR4_AM7_MASK 128U + + +/*** CAN0IDMR5 - MSCAN 0 Identifier Mask Register 5; 0x0000015D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR5STR; +extern volatile CAN0IDMR5STR _CAN0IDMR5 @(REG_BASE + 0x0000015DUL); +#define CAN0IDMR5 _CAN0IDMR5.Byte +#define CAN0IDMR5_AM0 _CAN0IDMR5.Bits.AM0 +#define CAN0IDMR5_AM1 _CAN0IDMR5.Bits.AM1 +#define CAN0IDMR5_AM2 _CAN0IDMR5.Bits.AM2 +#define CAN0IDMR5_AM3 _CAN0IDMR5.Bits.AM3 +#define CAN0IDMR5_AM4 _CAN0IDMR5.Bits.AM4 +#define CAN0IDMR5_AM5 _CAN0IDMR5.Bits.AM5 +#define CAN0IDMR5_AM6 _CAN0IDMR5.Bits.AM6 +#define CAN0IDMR5_AM7 _CAN0IDMR5.Bits.AM7 + +#define CAN0IDMR5_AM0_MASK 1U +#define CAN0IDMR5_AM1_MASK 2U +#define CAN0IDMR5_AM2_MASK 4U +#define CAN0IDMR5_AM3_MASK 8U +#define CAN0IDMR5_AM4_MASK 16U +#define CAN0IDMR5_AM5_MASK 32U +#define CAN0IDMR5_AM6_MASK 64U +#define CAN0IDMR5_AM7_MASK 128U + + +/*** CAN0IDMR6 - MSCAN 0 Identifier Mask Register 6; 0x0000015E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR6STR; +extern volatile CAN0IDMR6STR _CAN0IDMR6 @(REG_BASE + 0x0000015EUL); +#define CAN0IDMR6 _CAN0IDMR6.Byte +#define CAN0IDMR6_AM0 _CAN0IDMR6.Bits.AM0 +#define CAN0IDMR6_AM1 _CAN0IDMR6.Bits.AM1 +#define CAN0IDMR6_AM2 _CAN0IDMR6.Bits.AM2 +#define CAN0IDMR6_AM3 _CAN0IDMR6.Bits.AM3 +#define CAN0IDMR6_AM4 _CAN0IDMR6.Bits.AM4 +#define CAN0IDMR6_AM5 _CAN0IDMR6.Bits.AM5 +#define CAN0IDMR6_AM6 _CAN0IDMR6.Bits.AM6 +#define CAN0IDMR6_AM7 _CAN0IDMR6.Bits.AM7 + +#define CAN0IDMR6_AM0_MASK 1U +#define CAN0IDMR6_AM1_MASK 2U +#define CAN0IDMR6_AM2_MASK 4U +#define CAN0IDMR6_AM3_MASK 8U +#define CAN0IDMR6_AM4_MASK 16U +#define CAN0IDMR6_AM5_MASK 32U +#define CAN0IDMR6_AM6_MASK 64U +#define CAN0IDMR6_AM7_MASK 128U + + +/*** CAN0IDMR7 - MSCAN 0 Identifier Mask Register 7; 0x0000015F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN0IDMR7STR; +extern volatile CAN0IDMR7STR _CAN0IDMR7 @(REG_BASE + 0x0000015FUL); +#define CAN0IDMR7 _CAN0IDMR7.Byte +#define CAN0IDMR7_AM0 _CAN0IDMR7.Bits.AM0 +#define CAN0IDMR7_AM1 _CAN0IDMR7.Bits.AM1 +#define CAN0IDMR7_AM2 _CAN0IDMR7.Bits.AM2 +#define CAN0IDMR7_AM3 _CAN0IDMR7.Bits.AM3 +#define CAN0IDMR7_AM4 _CAN0IDMR7.Bits.AM4 +#define CAN0IDMR7_AM5 _CAN0IDMR7.Bits.AM5 +#define CAN0IDMR7_AM6 _CAN0IDMR7.Bits.AM6 +#define CAN0IDMR7_AM7 _CAN0IDMR7.Bits.AM7 + +#define CAN0IDMR7_AM0_MASK 1U +#define CAN0IDMR7_AM1_MASK 2U +#define CAN0IDMR7_AM2_MASK 4U +#define CAN0IDMR7_AM3_MASK 8U +#define CAN0IDMR7_AM4_MASK 16U +#define CAN0IDMR7_AM5_MASK 32U +#define CAN0IDMR7_AM6_MASK 64U +#define CAN0IDMR7_AM7_MASK 128U + + +/*** CAN0RXIDR0 - MSCAN 0 Receive Identifier Register 0; 0x00000160 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; +} CAN0RXIDR0STR; +extern volatile CAN0RXIDR0STR _CAN0RXIDR0 @(REG_BASE + 0x00000160UL); +#define CAN0RXIDR0 _CAN0RXIDR0.Byte +#define CAN0RXIDR0_ID21 _CAN0RXIDR0.Bits.ID21 +#define CAN0RXIDR0_ID22 _CAN0RXIDR0.Bits.ID22 +#define CAN0RXIDR0_ID23 _CAN0RXIDR0.Bits.ID23 +#define CAN0RXIDR0_ID24 _CAN0RXIDR0.Bits.ID24 +#define CAN0RXIDR0_ID25 _CAN0RXIDR0.Bits.ID25 +#define CAN0RXIDR0_ID26 _CAN0RXIDR0.Bits.ID26 +#define CAN0RXIDR0_ID27 _CAN0RXIDR0.Bits.ID27 +#define CAN0RXIDR0_ID28 _CAN0RXIDR0.Bits.ID28 +/* CAN0RXIDR_ARR: Access 4 CAN0RXIDRx registers in an array */ +#define CAN0RXIDR_ARR ((volatile byte *) &CAN0RXIDR0) + +#define CAN0RXIDR0_ID21_MASK 1U +#define CAN0RXIDR0_ID22_MASK 2U +#define CAN0RXIDR0_ID23_MASK 4U +#define CAN0RXIDR0_ID24_MASK 8U +#define CAN0RXIDR0_ID25_MASK 16U +#define CAN0RXIDR0_ID26_MASK 32U +#define CAN0RXIDR0_ID27_MASK 64U +#define CAN0RXIDR0_ID28_MASK 128U + + +/*** CAN0RXIDR1 - MSCAN 0 Receive Identifier Register 1; 0x00000161 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN0RXIDR1STR; +extern volatile CAN0RXIDR1STR _CAN0RXIDR1 @(REG_BASE + 0x00000161UL); +#define CAN0RXIDR1 _CAN0RXIDR1.Byte +#define CAN0RXIDR1_ID15 _CAN0RXIDR1.Bits.ID15 +#define CAN0RXIDR1_ID16 _CAN0RXIDR1.Bits.ID16 +#define CAN0RXIDR1_ID17 _CAN0RXIDR1.Bits.ID17 +#define CAN0RXIDR1_IDE _CAN0RXIDR1.Bits.IDE +#define CAN0RXIDR1_SRR _CAN0RXIDR1.Bits.SRR +#define CAN0RXIDR1_ID18 _CAN0RXIDR1.Bits.ID18 +#define CAN0RXIDR1_ID19 _CAN0RXIDR1.Bits.ID19 +#define CAN0RXIDR1_ID20 _CAN0RXIDR1.Bits.ID20 +#define CAN0RXIDR1_ID_15 _CAN0RXIDR1.MergedBits.grpID_15 +#define CAN0RXIDR1_ID_18 _CAN0RXIDR1.MergedBits.grpID_18 +#define CAN0RXIDR1_ID CAN0RXIDR1_ID_15 + +#define CAN0RXIDR1_ID15_MASK 1U +#define CAN0RXIDR1_ID16_MASK 2U +#define CAN0RXIDR1_ID17_MASK 4U +#define CAN0RXIDR1_IDE_MASK 8U +#define CAN0RXIDR1_SRR_MASK 16U +#define CAN0RXIDR1_ID18_MASK 32U +#define CAN0RXIDR1_ID19_MASK 64U +#define CAN0RXIDR1_ID20_MASK 128U +#define CAN0RXIDR1_ID_15_MASK 7U +#define CAN0RXIDR1_ID_15_BITNUM 0U +#define CAN0RXIDR1_ID_18_MASK 224U +#define CAN0RXIDR1_ID_18_BITNUM 5U + + +/*** CAN0RXIDR2 - MSCAN 0 Receive Identifier Register 2; 0x00000162 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; +} CAN0RXIDR2STR; +extern volatile CAN0RXIDR2STR _CAN0RXIDR2 @(REG_BASE + 0x00000162UL); +#define CAN0RXIDR2 _CAN0RXIDR2.Byte +#define CAN0RXIDR2_ID7 _CAN0RXIDR2.Bits.ID7 +#define CAN0RXIDR2_ID8 _CAN0RXIDR2.Bits.ID8 +#define CAN0RXIDR2_ID9 _CAN0RXIDR2.Bits.ID9 +#define CAN0RXIDR2_ID10 _CAN0RXIDR2.Bits.ID10 +#define CAN0RXIDR2_ID11 _CAN0RXIDR2.Bits.ID11 +#define CAN0RXIDR2_ID12 _CAN0RXIDR2.Bits.ID12 +#define CAN0RXIDR2_ID13 _CAN0RXIDR2.Bits.ID13 +#define CAN0RXIDR2_ID14 _CAN0RXIDR2.Bits.ID14 + +#define CAN0RXIDR2_ID7_MASK 1U +#define CAN0RXIDR2_ID8_MASK 2U +#define CAN0RXIDR2_ID9_MASK 4U +#define CAN0RXIDR2_ID10_MASK 8U +#define CAN0RXIDR2_ID11_MASK 16U +#define CAN0RXIDR2_ID12_MASK 32U +#define CAN0RXIDR2_ID13_MASK 64U +#define CAN0RXIDR2_ID14_MASK 128U + + +/*** CAN0RXIDR3 - MSCAN 0 Receive Identifier Register 3; 0x00000163 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN0RXIDR3STR; +extern volatile CAN0RXIDR3STR _CAN0RXIDR3 @(REG_BASE + 0x00000163UL); +#define CAN0RXIDR3 _CAN0RXIDR3.Byte +#define CAN0RXIDR3_RTR _CAN0RXIDR3.Bits.RTR +#define CAN0RXIDR3_ID0 _CAN0RXIDR3.Bits.ID0 +#define CAN0RXIDR3_ID1 _CAN0RXIDR3.Bits.ID1 +#define CAN0RXIDR3_ID2 _CAN0RXIDR3.Bits.ID2 +#define CAN0RXIDR3_ID3 _CAN0RXIDR3.Bits.ID3 +#define CAN0RXIDR3_ID4 _CAN0RXIDR3.Bits.ID4 +#define CAN0RXIDR3_ID5 _CAN0RXIDR3.Bits.ID5 +#define CAN0RXIDR3_ID6 _CAN0RXIDR3.Bits.ID6 +#define CAN0RXIDR3_ID _CAN0RXIDR3.MergedBits.grpID + +#define CAN0RXIDR3_RTR_MASK 1U +#define CAN0RXIDR3_ID0_MASK 2U +#define CAN0RXIDR3_ID1_MASK 4U +#define CAN0RXIDR3_ID2_MASK 8U +#define CAN0RXIDR3_ID3_MASK 16U +#define CAN0RXIDR3_ID4_MASK 32U +#define CAN0RXIDR3_ID5_MASK 64U +#define CAN0RXIDR3_ID6_MASK 128U +#define CAN0RXIDR3_ID_MASK 254U +#define CAN0RXIDR3_ID_BITNUM 1U + + +/*** CAN0RXDSR0 - MSCAN 0 Receive Data Segment Register 0; 0x00000164 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR0STR; +extern volatile CAN0RXDSR0STR _CAN0RXDSR0 @(REG_BASE + 0x00000164UL); +#define CAN0RXDSR0 _CAN0RXDSR0.Byte +#define CAN0RXDSR0_DB0 _CAN0RXDSR0.Bits.DB0 +#define CAN0RXDSR0_DB1 _CAN0RXDSR0.Bits.DB1 +#define CAN0RXDSR0_DB2 _CAN0RXDSR0.Bits.DB2 +#define CAN0RXDSR0_DB3 _CAN0RXDSR0.Bits.DB3 +#define CAN0RXDSR0_DB4 _CAN0RXDSR0.Bits.DB4 +#define CAN0RXDSR0_DB5 _CAN0RXDSR0.Bits.DB5 +#define CAN0RXDSR0_DB6 _CAN0RXDSR0.Bits.DB6 +#define CAN0RXDSR0_DB7 _CAN0RXDSR0.Bits.DB7 +/* CAN0RXDSR_ARR: Access 8 CAN0RXDSRx registers in an array */ +#define CAN0RXDSR_ARR ((volatile byte *) &CAN0RXDSR0) + +#define CAN0RXDSR0_DB0_MASK 1U +#define CAN0RXDSR0_DB1_MASK 2U +#define CAN0RXDSR0_DB2_MASK 4U +#define CAN0RXDSR0_DB3_MASK 8U +#define CAN0RXDSR0_DB4_MASK 16U +#define CAN0RXDSR0_DB5_MASK 32U +#define CAN0RXDSR0_DB6_MASK 64U +#define CAN0RXDSR0_DB7_MASK 128U + + +/*** CAN0RXDSR1 - MSCAN 0 Receive Data Segment Register 1; 0x00000165 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR1STR; +extern volatile CAN0RXDSR1STR _CAN0RXDSR1 @(REG_BASE + 0x00000165UL); +#define CAN0RXDSR1 _CAN0RXDSR1.Byte +#define CAN0RXDSR1_DB0 _CAN0RXDSR1.Bits.DB0 +#define CAN0RXDSR1_DB1 _CAN0RXDSR1.Bits.DB1 +#define CAN0RXDSR1_DB2 _CAN0RXDSR1.Bits.DB2 +#define CAN0RXDSR1_DB3 _CAN0RXDSR1.Bits.DB3 +#define CAN0RXDSR1_DB4 _CAN0RXDSR1.Bits.DB4 +#define CAN0RXDSR1_DB5 _CAN0RXDSR1.Bits.DB5 +#define CAN0RXDSR1_DB6 _CAN0RXDSR1.Bits.DB6 +#define CAN0RXDSR1_DB7 _CAN0RXDSR1.Bits.DB7 + +#define CAN0RXDSR1_DB0_MASK 1U +#define CAN0RXDSR1_DB1_MASK 2U +#define CAN0RXDSR1_DB2_MASK 4U +#define CAN0RXDSR1_DB3_MASK 8U +#define CAN0RXDSR1_DB4_MASK 16U +#define CAN0RXDSR1_DB5_MASK 32U +#define CAN0RXDSR1_DB6_MASK 64U +#define CAN0RXDSR1_DB7_MASK 128U + + +/*** CAN0RXDSR2 - MSCAN 0 Receive Data Segment Register 2; 0x00000166 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR2STR; +extern volatile CAN0RXDSR2STR _CAN0RXDSR2 @(REG_BASE + 0x00000166UL); +#define CAN0RXDSR2 _CAN0RXDSR2.Byte +#define CAN0RXDSR2_DB0 _CAN0RXDSR2.Bits.DB0 +#define CAN0RXDSR2_DB1 _CAN0RXDSR2.Bits.DB1 +#define CAN0RXDSR2_DB2 _CAN0RXDSR2.Bits.DB2 +#define CAN0RXDSR2_DB3 _CAN0RXDSR2.Bits.DB3 +#define CAN0RXDSR2_DB4 _CAN0RXDSR2.Bits.DB4 +#define CAN0RXDSR2_DB5 _CAN0RXDSR2.Bits.DB5 +#define CAN0RXDSR2_DB6 _CAN0RXDSR2.Bits.DB6 +#define CAN0RXDSR2_DB7 _CAN0RXDSR2.Bits.DB7 + +#define CAN0RXDSR2_DB0_MASK 1U +#define CAN0RXDSR2_DB1_MASK 2U +#define CAN0RXDSR2_DB2_MASK 4U +#define CAN0RXDSR2_DB3_MASK 8U +#define CAN0RXDSR2_DB4_MASK 16U +#define CAN0RXDSR2_DB5_MASK 32U +#define CAN0RXDSR2_DB6_MASK 64U +#define CAN0RXDSR2_DB7_MASK 128U + + +/*** CAN0RXDSR3 - MSCAN 0 Receive Data Segment Register 3; 0x00000167 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR3STR; +extern volatile CAN0RXDSR3STR _CAN0RXDSR3 @(REG_BASE + 0x00000167UL); +#define CAN0RXDSR3 _CAN0RXDSR3.Byte +#define CAN0RXDSR3_DB0 _CAN0RXDSR3.Bits.DB0 +#define CAN0RXDSR3_DB1 _CAN0RXDSR3.Bits.DB1 +#define CAN0RXDSR3_DB2 _CAN0RXDSR3.Bits.DB2 +#define CAN0RXDSR3_DB3 _CAN0RXDSR3.Bits.DB3 +#define CAN0RXDSR3_DB4 _CAN0RXDSR3.Bits.DB4 +#define CAN0RXDSR3_DB5 _CAN0RXDSR3.Bits.DB5 +#define CAN0RXDSR3_DB6 _CAN0RXDSR3.Bits.DB6 +#define CAN0RXDSR3_DB7 _CAN0RXDSR3.Bits.DB7 + +#define CAN0RXDSR3_DB0_MASK 1U +#define CAN0RXDSR3_DB1_MASK 2U +#define CAN0RXDSR3_DB2_MASK 4U +#define CAN0RXDSR3_DB3_MASK 8U +#define CAN0RXDSR3_DB4_MASK 16U +#define CAN0RXDSR3_DB5_MASK 32U +#define CAN0RXDSR3_DB6_MASK 64U +#define CAN0RXDSR3_DB7_MASK 128U + + +/*** CAN0RXDSR4 - MSCAN 0 Receive Data Segment Register 4; 0x00000168 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR4STR; +extern volatile CAN0RXDSR4STR _CAN0RXDSR4 @(REG_BASE + 0x00000168UL); +#define CAN0RXDSR4 _CAN0RXDSR4.Byte +#define CAN0RXDSR4_DB0 _CAN0RXDSR4.Bits.DB0 +#define CAN0RXDSR4_DB1 _CAN0RXDSR4.Bits.DB1 +#define CAN0RXDSR4_DB2 _CAN0RXDSR4.Bits.DB2 +#define CAN0RXDSR4_DB3 _CAN0RXDSR4.Bits.DB3 +#define CAN0RXDSR4_DB4 _CAN0RXDSR4.Bits.DB4 +#define CAN0RXDSR4_DB5 _CAN0RXDSR4.Bits.DB5 +#define CAN0RXDSR4_DB6 _CAN0RXDSR4.Bits.DB6 +#define CAN0RXDSR4_DB7 _CAN0RXDSR4.Bits.DB7 + +#define CAN0RXDSR4_DB0_MASK 1U +#define CAN0RXDSR4_DB1_MASK 2U +#define CAN0RXDSR4_DB2_MASK 4U +#define CAN0RXDSR4_DB3_MASK 8U +#define CAN0RXDSR4_DB4_MASK 16U +#define CAN0RXDSR4_DB5_MASK 32U +#define CAN0RXDSR4_DB6_MASK 64U +#define CAN0RXDSR4_DB7_MASK 128U + + +/*** CAN0RXDSR5 - MSCAN 0 Receive Data Segment Register 5; 0x00000169 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR5STR; +extern volatile CAN0RXDSR5STR _CAN0RXDSR5 @(REG_BASE + 0x00000169UL); +#define CAN0RXDSR5 _CAN0RXDSR5.Byte +#define CAN0RXDSR5_DB0 _CAN0RXDSR5.Bits.DB0 +#define CAN0RXDSR5_DB1 _CAN0RXDSR5.Bits.DB1 +#define CAN0RXDSR5_DB2 _CAN0RXDSR5.Bits.DB2 +#define CAN0RXDSR5_DB3 _CAN0RXDSR5.Bits.DB3 +#define CAN0RXDSR5_DB4 _CAN0RXDSR5.Bits.DB4 +#define CAN0RXDSR5_DB5 _CAN0RXDSR5.Bits.DB5 +#define CAN0RXDSR5_DB6 _CAN0RXDSR5.Bits.DB6 +#define CAN0RXDSR5_DB7 _CAN0RXDSR5.Bits.DB7 + +#define CAN0RXDSR5_DB0_MASK 1U +#define CAN0RXDSR5_DB1_MASK 2U +#define CAN0RXDSR5_DB2_MASK 4U +#define CAN0RXDSR5_DB3_MASK 8U +#define CAN0RXDSR5_DB4_MASK 16U +#define CAN0RXDSR5_DB5_MASK 32U +#define CAN0RXDSR5_DB6_MASK 64U +#define CAN0RXDSR5_DB7_MASK 128U + + +/*** CAN0RXDSR6 - MSCAN 0 Receive Data Segment Register 6; 0x0000016A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR6STR; +extern volatile CAN0RXDSR6STR _CAN0RXDSR6 @(REG_BASE + 0x0000016AUL); +#define CAN0RXDSR6 _CAN0RXDSR6.Byte +#define CAN0RXDSR6_DB0 _CAN0RXDSR6.Bits.DB0 +#define CAN0RXDSR6_DB1 _CAN0RXDSR6.Bits.DB1 +#define CAN0RXDSR6_DB2 _CAN0RXDSR6.Bits.DB2 +#define CAN0RXDSR6_DB3 _CAN0RXDSR6.Bits.DB3 +#define CAN0RXDSR6_DB4 _CAN0RXDSR6.Bits.DB4 +#define CAN0RXDSR6_DB5 _CAN0RXDSR6.Bits.DB5 +#define CAN0RXDSR6_DB6 _CAN0RXDSR6.Bits.DB6 +#define CAN0RXDSR6_DB7 _CAN0RXDSR6.Bits.DB7 + +#define CAN0RXDSR6_DB0_MASK 1U +#define CAN0RXDSR6_DB1_MASK 2U +#define CAN0RXDSR6_DB2_MASK 4U +#define CAN0RXDSR6_DB3_MASK 8U +#define CAN0RXDSR6_DB4_MASK 16U +#define CAN0RXDSR6_DB5_MASK 32U +#define CAN0RXDSR6_DB6_MASK 64U +#define CAN0RXDSR6_DB7_MASK 128U + + +/*** CAN0RXDSR7 - MSCAN 0 Receive Data Segment Register 7; 0x0000016B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0RXDSR7STR; +extern volatile CAN0RXDSR7STR _CAN0RXDSR7 @(REG_BASE + 0x0000016BUL); +#define CAN0RXDSR7 _CAN0RXDSR7.Byte +#define CAN0RXDSR7_DB0 _CAN0RXDSR7.Bits.DB0 +#define CAN0RXDSR7_DB1 _CAN0RXDSR7.Bits.DB1 +#define CAN0RXDSR7_DB2 _CAN0RXDSR7.Bits.DB2 +#define CAN0RXDSR7_DB3 _CAN0RXDSR7.Bits.DB3 +#define CAN0RXDSR7_DB4 _CAN0RXDSR7.Bits.DB4 +#define CAN0RXDSR7_DB5 _CAN0RXDSR7.Bits.DB5 +#define CAN0RXDSR7_DB6 _CAN0RXDSR7.Bits.DB6 +#define CAN0RXDSR7_DB7 _CAN0RXDSR7.Bits.DB7 + +#define CAN0RXDSR7_DB0_MASK 1U +#define CAN0RXDSR7_DB1_MASK 2U +#define CAN0RXDSR7_DB2_MASK 4U +#define CAN0RXDSR7_DB3_MASK 8U +#define CAN0RXDSR7_DB4_MASK 16U +#define CAN0RXDSR7_DB5_MASK 32U +#define CAN0RXDSR7_DB6_MASK 64U +#define CAN0RXDSR7_DB7_MASK 128U + + +/*** CAN0RXDLR - MSCAN 0 Receive Data Length Register; 0x0000016C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0RXDLRSTR; +extern volatile CAN0RXDLRSTR _CAN0RXDLR @(REG_BASE + 0x0000016CUL); +#define CAN0RXDLR _CAN0RXDLR.Byte +#define CAN0RXDLR_DLC0 _CAN0RXDLR.Bits.DLC0 +#define CAN0RXDLR_DLC1 _CAN0RXDLR.Bits.DLC1 +#define CAN0RXDLR_DLC2 _CAN0RXDLR.Bits.DLC2 +#define CAN0RXDLR_DLC3 _CAN0RXDLR.Bits.DLC3 +#define CAN0RXDLR_DLC _CAN0RXDLR.MergedBits.grpDLC + +#define CAN0RXDLR_DLC0_MASK 1U +#define CAN0RXDLR_DLC1_MASK 2U +#define CAN0RXDLR_DLC2_MASK 4U +#define CAN0RXDLR_DLC3_MASK 8U +#define CAN0RXDLR_DLC_MASK 15U +#define CAN0RXDLR_DLC_BITNUM 0U + + +/*** CAN0RXTSR - MSCAN 0 Receive Time Stamp Register; 0x0000016E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** CAN0RXTSRH - MSCAN 0 Receive Time Stamp Register High; 0x0000016E ***/ + union { + byte Byte; + struct { + byte TSR8 :1; /* Time Stamp Bit 8 */ + byte TSR9 :1; /* Time Stamp Bit 9 */ + byte TSR10 :1; /* Time Stamp Bit 10 */ + byte TSR11 :1; /* Time Stamp Bit 11 */ + byte TSR12 :1; /* Time Stamp Bit 12 */ + byte TSR13 :1; /* Time Stamp Bit 13 */ + byte TSR14 :1; /* Time Stamp Bit 14 */ + byte TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; + } CAN0RXTSRHSTR; + #define CAN0RXTSRH _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Byte + #define CAN0RXTSRH_TSR8 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR8 + #define CAN0RXTSRH_TSR9 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR9 + #define CAN0RXTSRH_TSR10 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR10 + #define CAN0RXTSRH_TSR11 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR11 + #define CAN0RXTSRH_TSR12 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR12 + #define CAN0RXTSRH_TSR13 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR13 + #define CAN0RXTSRH_TSR14 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR14 + #define CAN0RXTSRH_TSR15 _CAN0RXTSR.Overlap_STR.CAN0RXTSRHSTR.Bits.TSR15 + + #define CAN0RXTSRH_TSR8_MASK 1U + #define CAN0RXTSRH_TSR9_MASK 2U + #define CAN0RXTSRH_TSR10_MASK 4U + #define CAN0RXTSRH_TSR11_MASK 8U + #define CAN0RXTSRH_TSR12_MASK 16U + #define CAN0RXTSRH_TSR13_MASK 32U + #define CAN0RXTSRH_TSR14_MASK 64U + #define CAN0RXTSRH_TSR15_MASK 128U + + + /*** CAN0RXTSRL - MSCAN 0 Receive Time Stamp Register Low; 0x0000016F ***/ + union { + byte Byte; + struct { + byte TSR0 :1; /* Time Stamp Bit 0 */ + byte TSR1 :1; /* Time Stamp Bit 1 */ + byte TSR2 :1; /* Time Stamp Bit 2 */ + byte TSR3 :1; /* Time Stamp Bit 3 */ + byte TSR4 :1; /* Time Stamp Bit 4 */ + byte TSR5 :1; /* Time Stamp Bit 5 */ + byte TSR6 :1; /* Time Stamp Bit 6 */ + byte TSR7 :1; /* Time Stamp Bit 7 */ + } Bits; + } CAN0RXTSRLSTR; + #define CAN0RXTSRL _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Byte + #define CAN0RXTSRL_TSR0 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR0 + #define CAN0RXTSRL_TSR1 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR1 + #define CAN0RXTSRL_TSR2 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR2 + #define CAN0RXTSRL_TSR3 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR3 + #define CAN0RXTSRL_TSR4 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR4 + #define CAN0RXTSRL_TSR5 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR5 + #define CAN0RXTSRL_TSR6 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR6 + #define CAN0RXTSRL_TSR7 _CAN0RXTSR.Overlap_STR.CAN0RXTSRLSTR.Bits.TSR7 + + #define CAN0RXTSRL_TSR0_MASK 1U + #define CAN0RXTSRL_TSR1_MASK 2U + #define CAN0RXTSRL_TSR2_MASK 4U + #define CAN0RXTSRL_TSR3_MASK 8U + #define CAN0RXTSRL_TSR4_MASK 16U + #define CAN0RXTSRL_TSR5_MASK 32U + #define CAN0RXTSRL_TSR6_MASK 64U + #define CAN0RXTSRL_TSR7_MASK 128U + + } Overlap_STR; + + struct { + word TSR0 :1; /* Time Stamp Bit 0 */ + word TSR1 :1; /* Time Stamp Bit 1 */ + word TSR2 :1; /* Time Stamp Bit 2 */ + word TSR3 :1; /* Time Stamp Bit 3 */ + word TSR4 :1; /* Time Stamp Bit 4 */ + word TSR5 :1; /* Time Stamp Bit 5 */ + word TSR6 :1; /* Time Stamp Bit 6 */ + word TSR7 :1; /* Time Stamp Bit 7 */ + word TSR8 :1; /* Time Stamp Bit 8 */ + word TSR9 :1; /* Time Stamp Bit 9 */ + word TSR10 :1; /* Time Stamp Bit 10 */ + word TSR11 :1; /* Time Stamp Bit 11 */ + word TSR12 :1; /* Time Stamp Bit 12 */ + word TSR13 :1; /* Time Stamp Bit 13 */ + word TSR14 :1; /* Time Stamp Bit 14 */ + word TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; +} CAN0RXTSRSTR; +extern volatile CAN0RXTSRSTR _CAN0RXTSR @(REG_BASE + 0x0000016EUL); +#define CAN0RXTSR _CAN0RXTSR.Word +#define CAN0RXTSR_TSR0 _CAN0RXTSR.Bits.TSR0 +#define CAN0RXTSR_TSR1 _CAN0RXTSR.Bits.TSR1 +#define CAN0RXTSR_TSR2 _CAN0RXTSR.Bits.TSR2 +#define CAN0RXTSR_TSR3 _CAN0RXTSR.Bits.TSR3 +#define CAN0RXTSR_TSR4 _CAN0RXTSR.Bits.TSR4 +#define CAN0RXTSR_TSR5 _CAN0RXTSR.Bits.TSR5 +#define CAN0RXTSR_TSR6 _CAN0RXTSR.Bits.TSR6 +#define CAN0RXTSR_TSR7 _CAN0RXTSR.Bits.TSR7 +#define CAN0RXTSR_TSR8 _CAN0RXTSR.Bits.TSR8 +#define CAN0RXTSR_TSR9 _CAN0RXTSR.Bits.TSR9 +#define CAN0RXTSR_TSR10 _CAN0RXTSR.Bits.TSR10 +#define CAN0RXTSR_TSR11 _CAN0RXTSR.Bits.TSR11 +#define CAN0RXTSR_TSR12 _CAN0RXTSR.Bits.TSR12 +#define CAN0RXTSR_TSR13 _CAN0RXTSR.Bits.TSR13 +#define CAN0RXTSR_TSR14 _CAN0RXTSR.Bits.TSR14 +#define CAN0RXTSR_TSR15 _CAN0RXTSR.Bits.TSR15 + +#define CAN0RXTSR_TSR0_MASK 1U +#define CAN0RXTSR_TSR1_MASK 2U +#define CAN0RXTSR_TSR2_MASK 4U +#define CAN0RXTSR_TSR3_MASK 8U +#define CAN0RXTSR_TSR4_MASK 16U +#define CAN0RXTSR_TSR5_MASK 32U +#define CAN0RXTSR_TSR6_MASK 64U +#define CAN0RXTSR_TSR7_MASK 128U +#define CAN0RXTSR_TSR8_MASK 256U +#define CAN0RXTSR_TSR9_MASK 512U +#define CAN0RXTSR_TSR10_MASK 1024U +#define CAN0RXTSR_TSR11_MASK 2048U +#define CAN0RXTSR_TSR12_MASK 4096U +#define CAN0RXTSR_TSR13_MASK 8192U +#define CAN0RXTSR_TSR14_MASK 16384U +#define CAN0RXTSR_TSR15_MASK 32768U + + +/*** CAN0TXIDR0 - MSCAN 0 Transmit Identifier Register 0; 0x00000170 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; +} CAN0TXIDR0STR; +extern volatile CAN0TXIDR0STR _CAN0TXIDR0 @(REG_BASE + 0x00000170UL); +#define CAN0TXIDR0 _CAN0TXIDR0.Byte +#define CAN0TXIDR0_ID21 _CAN0TXIDR0.Bits.ID21 +#define CAN0TXIDR0_ID22 _CAN0TXIDR0.Bits.ID22 +#define CAN0TXIDR0_ID23 _CAN0TXIDR0.Bits.ID23 +#define CAN0TXIDR0_ID24 _CAN0TXIDR0.Bits.ID24 +#define CAN0TXIDR0_ID25 _CAN0TXIDR0.Bits.ID25 +#define CAN0TXIDR0_ID26 _CAN0TXIDR0.Bits.ID26 +#define CAN0TXIDR0_ID27 _CAN0TXIDR0.Bits.ID27 +#define CAN0TXIDR0_ID28 _CAN0TXIDR0.Bits.ID28 +/* CAN0TXIDR_ARR: Access 4 CAN0TXIDRx registers in an array */ +#define CAN0TXIDR_ARR ((volatile byte *) &CAN0TXIDR0) + +#define CAN0TXIDR0_ID21_MASK 1U +#define CAN0TXIDR0_ID22_MASK 2U +#define CAN0TXIDR0_ID23_MASK 4U +#define CAN0TXIDR0_ID24_MASK 8U +#define CAN0TXIDR0_ID25_MASK 16U +#define CAN0TXIDR0_ID26_MASK 32U +#define CAN0TXIDR0_ID27_MASK 64U +#define CAN0TXIDR0_ID28_MASK 128U + + +/*** CAN0TXIDR1 - MSCAN 0 Transmit Identifier Register 1; 0x00000171 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN0TXIDR1STR; +extern volatile CAN0TXIDR1STR _CAN0TXIDR1 @(REG_BASE + 0x00000171UL); +#define CAN0TXIDR1 _CAN0TXIDR1.Byte +#define CAN0TXIDR1_ID15 _CAN0TXIDR1.Bits.ID15 +#define CAN0TXIDR1_ID16 _CAN0TXIDR1.Bits.ID16 +#define CAN0TXIDR1_ID17 _CAN0TXIDR1.Bits.ID17 +#define CAN0TXIDR1_IDE _CAN0TXIDR1.Bits.IDE +#define CAN0TXIDR1_SRR _CAN0TXIDR1.Bits.SRR +#define CAN0TXIDR1_ID18 _CAN0TXIDR1.Bits.ID18 +#define CAN0TXIDR1_ID19 _CAN0TXIDR1.Bits.ID19 +#define CAN0TXIDR1_ID20 _CAN0TXIDR1.Bits.ID20 +#define CAN0TXIDR1_ID_15 _CAN0TXIDR1.MergedBits.grpID_15 +#define CAN0TXIDR1_ID_18 _CAN0TXIDR1.MergedBits.grpID_18 +#define CAN0TXIDR1_ID CAN0TXIDR1_ID_15 + +#define CAN0TXIDR1_ID15_MASK 1U +#define CAN0TXIDR1_ID16_MASK 2U +#define CAN0TXIDR1_ID17_MASK 4U +#define CAN0TXIDR1_IDE_MASK 8U +#define CAN0TXIDR1_SRR_MASK 16U +#define CAN0TXIDR1_ID18_MASK 32U +#define CAN0TXIDR1_ID19_MASK 64U +#define CAN0TXIDR1_ID20_MASK 128U +#define CAN0TXIDR1_ID_15_MASK 7U +#define CAN0TXIDR1_ID_15_BITNUM 0U +#define CAN0TXIDR1_ID_18_MASK 224U +#define CAN0TXIDR1_ID_18_BITNUM 5U + + +/*** CAN0TXIDR2 - MSCAN 0 Transmit Identifier Register 2; 0x00000172 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; +} CAN0TXIDR2STR; +extern volatile CAN0TXIDR2STR _CAN0TXIDR2 @(REG_BASE + 0x00000172UL); +#define CAN0TXIDR2 _CAN0TXIDR2.Byte +#define CAN0TXIDR2_ID7 _CAN0TXIDR2.Bits.ID7 +#define CAN0TXIDR2_ID8 _CAN0TXIDR2.Bits.ID8 +#define CAN0TXIDR2_ID9 _CAN0TXIDR2.Bits.ID9 +#define CAN0TXIDR2_ID10 _CAN0TXIDR2.Bits.ID10 +#define CAN0TXIDR2_ID11 _CAN0TXIDR2.Bits.ID11 +#define CAN0TXIDR2_ID12 _CAN0TXIDR2.Bits.ID12 +#define CAN0TXIDR2_ID13 _CAN0TXIDR2.Bits.ID13 +#define CAN0TXIDR2_ID14 _CAN0TXIDR2.Bits.ID14 + +#define CAN0TXIDR2_ID7_MASK 1U +#define CAN0TXIDR2_ID8_MASK 2U +#define CAN0TXIDR2_ID9_MASK 4U +#define CAN0TXIDR2_ID10_MASK 8U +#define CAN0TXIDR2_ID11_MASK 16U +#define CAN0TXIDR2_ID12_MASK 32U +#define CAN0TXIDR2_ID13_MASK 64U +#define CAN0TXIDR2_ID14_MASK 128U + + +/*** CAN0TXIDR3 - MSCAN 0 Transmit Identifier Register 3; 0x00000173 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN0TXIDR3STR; +extern volatile CAN0TXIDR3STR _CAN0TXIDR3 @(REG_BASE + 0x00000173UL); +#define CAN0TXIDR3 _CAN0TXIDR3.Byte +#define CAN0TXIDR3_RTR _CAN0TXIDR3.Bits.RTR +#define CAN0TXIDR3_ID0 _CAN0TXIDR3.Bits.ID0 +#define CAN0TXIDR3_ID1 _CAN0TXIDR3.Bits.ID1 +#define CAN0TXIDR3_ID2 _CAN0TXIDR3.Bits.ID2 +#define CAN0TXIDR3_ID3 _CAN0TXIDR3.Bits.ID3 +#define CAN0TXIDR3_ID4 _CAN0TXIDR3.Bits.ID4 +#define CAN0TXIDR3_ID5 _CAN0TXIDR3.Bits.ID5 +#define CAN0TXIDR3_ID6 _CAN0TXIDR3.Bits.ID6 +#define CAN0TXIDR3_ID _CAN0TXIDR3.MergedBits.grpID + +#define CAN0TXIDR3_RTR_MASK 1U +#define CAN0TXIDR3_ID0_MASK 2U +#define CAN0TXIDR3_ID1_MASK 4U +#define CAN0TXIDR3_ID2_MASK 8U +#define CAN0TXIDR3_ID3_MASK 16U +#define CAN0TXIDR3_ID4_MASK 32U +#define CAN0TXIDR3_ID5_MASK 64U +#define CAN0TXIDR3_ID6_MASK 128U +#define CAN0TXIDR3_ID_MASK 254U +#define CAN0TXIDR3_ID_BITNUM 1U + + +/*** CAN0TXDSR0 - MSCAN 0 Transmit Data Segment Register 0; 0x00000174 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR0STR; +extern volatile CAN0TXDSR0STR _CAN0TXDSR0 @(REG_BASE + 0x00000174UL); +#define CAN0TXDSR0 _CAN0TXDSR0.Byte +#define CAN0TXDSR0_DB0 _CAN0TXDSR0.Bits.DB0 +#define CAN0TXDSR0_DB1 _CAN0TXDSR0.Bits.DB1 +#define CAN0TXDSR0_DB2 _CAN0TXDSR0.Bits.DB2 +#define CAN0TXDSR0_DB3 _CAN0TXDSR0.Bits.DB3 +#define CAN0TXDSR0_DB4 _CAN0TXDSR0.Bits.DB4 +#define CAN0TXDSR0_DB5 _CAN0TXDSR0.Bits.DB5 +#define CAN0TXDSR0_DB6 _CAN0TXDSR0.Bits.DB6 +#define CAN0TXDSR0_DB7 _CAN0TXDSR0.Bits.DB7 +/* CAN0TXDSR_ARR: Access 8 CAN0TXDSRx registers in an array */ +#define CAN0TXDSR_ARR ((volatile byte *) &CAN0TXDSR0) + +#define CAN0TXDSR0_DB0_MASK 1U +#define CAN0TXDSR0_DB1_MASK 2U +#define CAN0TXDSR0_DB2_MASK 4U +#define CAN0TXDSR0_DB3_MASK 8U +#define CAN0TXDSR0_DB4_MASK 16U +#define CAN0TXDSR0_DB5_MASK 32U +#define CAN0TXDSR0_DB6_MASK 64U +#define CAN0TXDSR0_DB7_MASK 128U + + +/*** CAN0TXDSR1 - MSCAN 0 Transmit Data Segment Register 1; 0x00000175 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR1STR; +extern volatile CAN0TXDSR1STR _CAN0TXDSR1 @(REG_BASE + 0x00000175UL); +#define CAN0TXDSR1 _CAN0TXDSR1.Byte +#define CAN0TXDSR1_DB0 _CAN0TXDSR1.Bits.DB0 +#define CAN0TXDSR1_DB1 _CAN0TXDSR1.Bits.DB1 +#define CAN0TXDSR1_DB2 _CAN0TXDSR1.Bits.DB2 +#define CAN0TXDSR1_DB3 _CAN0TXDSR1.Bits.DB3 +#define CAN0TXDSR1_DB4 _CAN0TXDSR1.Bits.DB4 +#define CAN0TXDSR1_DB5 _CAN0TXDSR1.Bits.DB5 +#define CAN0TXDSR1_DB6 _CAN0TXDSR1.Bits.DB6 +#define CAN0TXDSR1_DB7 _CAN0TXDSR1.Bits.DB7 + +#define CAN0TXDSR1_DB0_MASK 1U +#define CAN0TXDSR1_DB1_MASK 2U +#define CAN0TXDSR1_DB2_MASK 4U +#define CAN0TXDSR1_DB3_MASK 8U +#define CAN0TXDSR1_DB4_MASK 16U +#define CAN0TXDSR1_DB5_MASK 32U +#define CAN0TXDSR1_DB6_MASK 64U +#define CAN0TXDSR1_DB7_MASK 128U + + +/*** CAN0TXDSR2 - MSCAN 0 Transmit Data Segment Register 2; 0x00000176 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR2STR; +extern volatile CAN0TXDSR2STR _CAN0TXDSR2 @(REG_BASE + 0x00000176UL); +#define CAN0TXDSR2 _CAN0TXDSR2.Byte +#define CAN0TXDSR2_DB0 _CAN0TXDSR2.Bits.DB0 +#define CAN0TXDSR2_DB1 _CAN0TXDSR2.Bits.DB1 +#define CAN0TXDSR2_DB2 _CAN0TXDSR2.Bits.DB2 +#define CAN0TXDSR2_DB3 _CAN0TXDSR2.Bits.DB3 +#define CAN0TXDSR2_DB4 _CAN0TXDSR2.Bits.DB4 +#define CAN0TXDSR2_DB5 _CAN0TXDSR2.Bits.DB5 +#define CAN0TXDSR2_DB6 _CAN0TXDSR2.Bits.DB6 +#define CAN0TXDSR2_DB7 _CAN0TXDSR2.Bits.DB7 + +#define CAN0TXDSR2_DB0_MASK 1U +#define CAN0TXDSR2_DB1_MASK 2U +#define CAN0TXDSR2_DB2_MASK 4U +#define CAN0TXDSR2_DB3_MASK 8U +#define CAN0TXDSR2_DB4_MASK 16U +#define CAN0TXDSR2_DB5_MASK 32U +#define CAN0TXDSR2_DB6_MASK 64U +#define CAN0TXDSR2_DB7_MASK 128U + + +/*** CAN0TXDSR3 - MSCAN 0 Transmit Data Segment Register 3; 0x00000177 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR3STR; +extern volatile CAN0TXDSR3STR _CAN0TXDSR3 @(REG_BASE + 0x00000177UL); +#define CAN0TXDSR3 _CAN0TXDSR3.Byte +#define CAN0TXDSR3_DB0 _CAN0TXDSR3.Bits.DB0 +#define CAN0TXDSR3_DB1 _CAN0TXDSR3.Bits.DB1 +#define CAN0TXDSR3_DB2 _CAN0TXDSR3.Bits.DB2 +#define CAN0TXDSR3_DB3 _CAN0TXDSR3.Bits.DB3 +#define CAN0TXDSR3_DB4 _CAN0TXDSR3.Bits.DB4 +#define CAN0TXDSR3_DB5 _CAN0TXDSR3.Bits.DB5 +#define CAN0TXDSR3_DB6 _CAN0TXDSR3.Bits.DB6 +#define CAN0TXDSR3_DB7 _CAN0TXDSR3.Bits.DB7 + +#define CAN0TXDSR3_DB0_MASK 1U +#define CAN0TXDSR3_DB1_MASK 2U +#define CAN0TXDSR3_DB2_MASK 4U +#define CAN0TXDSR3_DB3_MASK 8U +#define CAN0TXDSR3_DB4_MASK 16U +#define CAN0TXDSR3_DB5_MASK 32U +#define CAN0TXDSR3_DB6_MASK 64U +#define CAN0TXDSR3_DB7_MASK 128U + + +/*** CAN0TXDSR4 - MSCAN 0 Transmit Data Segment Register 4; 0x00000178 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR4STR; +extern volatile CAN0TXDSR4STR _CAN0TXDSR4 @(REG_BASE + 0x00000178UL); +#define CAN0TXDSR4 _CAN0TXDSR4.Byte +#define CAN0TXDSR4_DB0 _CAN0TXDSR4.Bits.DB0 +#define CAN0TXDSR4_DB1 _CAN0TXDSR4.Bits.DB1 +#define CAN0TXDSR4_DB2 _CAN0TXDSR4.Bits.DB2 +#define CAN0TXDSR4_DB3 _CAN0TXDSR4.Bits.DB3 +#define CAN0TXDSR4_DB4 _CAN0TXDSR4.Bits.DB4 +#define CAN0TXDSR4_DB5 _CAN0TXDSR4.Bits.DB5 +#define CAN0TXDSR4_DB6 _CAN0TXDSR4.Bits.DB6 +#define CAN0TXDSR4_DB7 _CAN0TXDSR4.Bits.DB7 + +#define CAN0TXDSR4_DB0_MASK 1U +#define CAN0TXDSR4_DB1_MASK 2U +#define CAN0TXDSR4_DB2_MASK 4U +#define CAN0TXDSR4_DB3_MASK 8U +#define CAN0TXDSR4_DB4_MASK 16U +#define CAN0TXDSR4_DB5_MASK 32U +#define CAN0TXDSR4_DB6_MASK 64U +#define CAN0TXDSR4_DB7_MASK 128U + + +/*** CAN0TXDSR5 - MSCAN 0 Transmit Data Segment Register 5; 0x00000179 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR5STR; +extern volatile CAN0TXDSR5STR _CAN0TXDSR5 @(REG_BASE + 0x00000179UL); +#define CAN0TXDSR5 _CAN0TXDSR5.Byte +#define CAN0TXDSR5_DB0 _CAN0TXDSR5.Bits.DB0 +#define CAN0TXDSR5_DB1 _CAN0TXDSR5.Bits.DB1 +#define CAN0TXDSR5_DB2 _CAN0TXDSR5.Bits.DB2 +#define CAN0TXDSR5_DB3 _CAN0TXDSR5.Bits.DB3 +#define CAN0TXDSR5_DB4 _CAN0TXDSR5.Bits.DB4 +#define CAN0TXDSR5_DB5 _CAN0TXDSR5.Bits.DB5 +#define CAN0TXDSR5_DB6 _CAN0TXDSR5.Bits.DB6 +#define CAN0TXDSR5_DB7 _CAN0TXDSR5.Bits.DB7 + +#define CAN0TXDSR5_DB0_MASK 1U +#define CAN0TXDSR5_DB1_MASK 2U +#define CAN0TXDSR5_DB2_MASK 4U +#define CAN0TXDSR5_DB3_MASK 8U +#define CAN0TXDSR5_DB4_MASK 16U +#define CAN0TXDSR5_DB5_MASK 32U +#define CAN0TXDSR5_DB6_MASK 64U +#define CAN0TXDSR5_DB7_MASK 128U + + +/*** CAN0TXDSR6 - MSCAN 0 Transmit Data Segment Register 6; 0x0000017A ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR6STR; +extern volatile CAN0TXDSR6STR _CAN0TXDSR6 @(REG_BASE + 0x0000017AUL); +#define CAN0TXDSR6 _CAN0TXDSR6.Byte +#define CAN0TXDSR6_DB0 _CAN0TXDSR6.Bits.DB0 +#define CAN0TXDSR6_DB1 _CAN0TXDSR6.Bits.DB1 +#define CAN0TXDSR6_DB2 _CAN0TXDSR6.Bits.DB2 +#define CAN0TXDSR6_DB3 _CAN0TXDSR6.Bits.DB3 +#define CAN0TXDSR6_DB4 _CAN0TXDSR6.Bits.DB4 +#define CAN0TXDSR6_DB5 _CAN0TXDSR6.Bits.DB5 +#define CAN0TXDSR6_DB6 _CAN0TXDSR6.Bits.DB6 +#define CAN0TXDSR6_DB7 _CAN0TXDSR6.Bits.DB7 + +#define CAN0TXDSR6_DB0_MASK 1U +#define CAN0TXDSR6_DB1_MASK 2U +#define CAN0TXDSR6_DB2_MASK 4U +#define CAN0TXDSR6_DB3_MASK 8U +#define CAN0TXDSR6_DB4_MASK 16U +#define CAN0TXDSR6_DB5_MASK 32U +#define CAN0TXDSR6_DB6_MASK 64U +#define CAN0TXDSR6_DB7_MASK 128U + + +/*** CAN0TXDSR7 - MSCAN 0 Transmit Data Segment Register 7; 0x0000017B ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN0TXDSR7STR; +extern volatile CAN0TXDSR7STR _CAN0TXDSR7 @(REG_BASE + 0x0000017BUL); +#define CAN0TXDSR7 _CAN0TXDSR7.Byte +#define CAN0TXDSR7_DB0 _CAN0TXDSR7.Bits.DB0 +#define CAN0TXDSR7_DB1 _CAN0TXDSR7.Bits.DB1 +#define CAN0TXDSR7_DB2 _CAN0TXDSR7.Bits.DB2 +#define CAN0TXDSR7_DB3 _CAN0TXDSR7.Bits.DB3 +#define CAN0TXDSR7_DB4 _CAN0TXDSR7.Bits.DB4 +#define CAN0TXDSR7_DB5 _CAN0TXDSR7.Bits.DB5 +#define CAN0TXDSR7_DB6 _CAN0TXDSR7.Bits.DB6 +#define CAN0TXDSR7_DB7 _CAN0TXDSR7.Bits.DB7 + +#define CAN0TXDSR7_DB0_MASK 1U +#define CAN0TXDSR7_DB1_MASK 2U +#define CAN0TXDSR7_DB2_MASK 4U +#define CAN0TXDSR7_DB3_MASK 8U +#define CAN0TXDSR7_DB4_MASK 16U +#define CAN0TXDSR7_DB5_MASK 32U +#define CAN0TXDSR7_DB6_MASK 64U +#define CAN0TXDSR7_DB7_MASK 128U + + +/*** CAN0TXDLR - MSCAN 0 Transmit Data Length Register; 0x0000017C ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN0TXDLRSTR; +extern volatile CAN0TXDLRSTR _CAN0TXDLR @(REG_BASE + 0x0000017CUL); +#define CAN0TXDLR _CAN0TXDLR.Byte +#define CAN0TXDLR_DLC0 _CAN0TXDLR.Bits.DLC0 +#define CAN0TXDLR_DLC1 _CAN0TXDLR.Bits.DLC1 +#define CAN0TXDLR_DLC2 _CAN0TXDLR.Bits.DLC2 +#define CAN0TXDLR_DLC3 _CAN0TXDLR.Bits.DLC3 +#define CAN0TXDLR_DLC _CAN0TXDLR.MergedBits.grpDLC + +#define CAN0TXDLR_DLC0_MASK 1U +#define CAN0TXDLR_DLC1_MASK 2U +#define CAN0TXDLR_DLC2_MASK 4U +#define CAN0TXDLR_DLC3_MASK 8U +#define CAN0TXDLR_DLC_MASK 15U +#define CAN0TXDLR_DLC_BITNUM 0U + + +/*** CAN0TXTBPR - MSCAN 0 Transmit Buffer Priority; 0x0000017D ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; +} CAN0TXTBPRSTR; +extern volatile CAN0TXTBPRSTR _CAN0TXTBPR @(REG_BASE + 0x0000017DUL); +#define CAN0TXTBPR _CAN0TXTBPR.Byte +#define CAN0TXTBPR_PRIO0 _CAN0TXTBPR.Bits.PRIO0 +#define CAN0TXTBPR_PRIO1 _CAN0TXTBPR.Bits.PRIO1 +#define CAN0TXTBPR_PRIO2 _CAN0TXTBPR.Bits.PRIO2 +#define CAN0TXTBPR_PRIO3 _CAN0TXTBPR.Bits.PRIO3 +#define CAN0TXTBPR_PRIO4 _CAN0TXTBPR.Bits.PRIO4 +#define CAN0TXTBPR_PRIO5 _CAN0TXTBPR.Bits.PRIO5 +#define CAN0TXTBPR_PRIO6 _CAN0TXTBPR.Bits.PRIO6 +#define CAN0TXTBPR_PRIO7 _CAN0TXTBPR.Bits.PRIO7 + +#define CAN0TXTBPR_PRIO0_MASK 1U +#define CAN0TXTBPR_PRIO1_MASK 2U +#define CAN0TXTBPR_PRIO2_MASK 4U +#define CAN0TXTBPR_PRIO3_MASK 8U +#define CAN0TXTBPR_PRIO4_MASK 16U +#define CAN0TXTBPR_PRIO5_MASK 32U +#define CAN0TXTBPR_PRIO6_MASK 64U +#define CAN0TXTBPR_PRIO7_MASK 128U + + +/*** CAN0TXTSR - MSCAN 0 Transmit Time Stamp Register; 0x0000017E ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** CAN0TXTSRH - MSCAN 0 Transmit Time Stamp Register High; 0x0000017E ***/ + union { + byte Byte; + struct { + byte TSR8 :1; /* Time Stamp Bit 8 */ + byte TSR9 :1; /* Time Stamp Bit 9 */ + byte TSR10 :1; /* Time Stamp Bit 10 */ + byte TSR11 :1; /* Time Stamp Bit 11 */ + byte TSR12 :1; /* Time Stamp Bit 12 */ + byte TSR13 :1; /* Time Stamp Bit 13 */ + byte TSR14 :1; /* Time Stamp Bit 14 */ + byte TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; + } CAN0TXTSRHSTR; + #define CAN0TXTSRH _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Byte + #define CAN0TXTSRH_TSR8 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR8 + #define CAN0TXTSRH_TSR9 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR9 + #define CAN0TXTSRH_TSR10 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR10 + #define CAN0TXTSRH_TSR11 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR11 + #define CAN0TXTSRH_TSR12 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR12 + #define CAN0TXTSRH_TSR13 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR13 + #define CAN0TXTSRH_TSR14 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR14 + #define CAN0TXTSRH_TSR15 _CAN0TXTSR.Overlap_STR.CAN0TXTSRHSTR.Bits.TSR15 + + #define CAN0TXTSRH_TSR8_MASK 1U + #define CAN0TXTSRH_TSR9_MASK 2U + #define CAN0TXTSRH_TSR10_MASK 4U + #define CAN0TXTSRH_TSR11_MASK 8U + #define CAN0TXTSRH_TSR12_MASK 16U + #define CAN0TXTSRH_TSR13_MASK 32U + #define CAN0TXTSRH_TSR14_MASK 64U + #define CAN0TXTSRH_TSR15_MASK 128U + + + /*** CAN0TXTSRL - MSCAN 0 Transmit Time Stamp Register Low; 0x0000017F ***/ + union { + byte Byte; + struct { + byte TSR0 :1; /* Time Stamp Bit 0 */ + byte TSR1 :1; /* Time Stamp Bit 1 */ + byte TSR2 :1; /* Time Stamp Bit 2 */ + byte TSR3 :1; /* Time Stamp Bit 3 */ + byte TSR4 :1; /* Time Stamp Bit 4 */ + byte TSR5 :1; /* Time Stamp Bit 5 */ + byte TSR6 :1; /* Time Stamp Bit 6 */ + byte TSR7 :1; /* Time Stamp Bit 7 */ + } Bits; + } CAN0TXTSRLSTR; + #define CAN0TXTSRL _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Byte + #define CAN0TXTSRL_TSR0 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR0 + #define CAN0TXTSRL_TSR1 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR1 + #define CAN0TXTSRL_TSR2 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR2 + #define CAN0TXTSRL_TSR3 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR3 + #define CAN0TXTSRL_TSR4 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR4 + #define CAN0TXTSRL_TSR5 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR5 + #define CAN0TXTSRL_TSR6 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR6 + #define CAN0TXTSRL_TSR7 _CAN0TXTSR.Overlap_STR.CAN0TXTSRLSTR.Bits.TSR7 + + #define CAN0TXTSRL_TSR0_MASK 1U + #define CAN0TXTSRL_TSR1_MASK 2U + #define CAN0TXTSRL_TSR2_MASK 4U + #define CAN0TXTSRL_TSR3_MASK 8U + #define CAN0TXTSRL_TSR4_MASK 16U + #define CAN0TXTSRL_TSR5_MASK 32U + #define CAN0TXTSRL_TSR6_MASK 64U + #define CAN0TXTSRL_TSR7_MASK 128U + + } Overlap_STR; + + struct { + word TSR0 :1; /* Time Stamp Bit 0 */ + word TSR1 :1; /* Time Stamp Bit 1 */ + word TSR2 :1; /* Time Stamp Bit 2 */ + word TSR3 :1; /* Time Stamp Bit 3 */ + word TSR4 :1; /* Time Stamp Bit 4 */ + word TSR5 :1; /* Time Stamp Bit 5 */ + word TSR6 :1; /* Time Stamp Bit 6 */ + word TSR7 :1; /* Time Stamp Bit 7 */ + word TSR8 :1; /* Time Stamp Bit 8 */ + word TSR9 :1; /* Time Stamp Bit 9 */ + word TSR10 :1; /* Time Stamp Bit 10 */ + word TSR11 :1; /* Time Stamp Bit 11 */ + word TSR12 :1; /* Time Stamp Bit 12 */ + word TSR13 :1; /* Time Stamp Bit 13 */ + word TSR14 :1; /* Time Stamp Bit 14 */ + word TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; +} CAN0TXTSRSTR; +extern volatile CAN0TXTSRSTR _CAN0TXTSR @(REG_BASE + 0x0000017EUL); +#define CAN0TXTSR _CAN0TXTSR.Word +#define CAN0TXTSR_TSR0 _CAN0TXTSR.Bits.TSR0 +#define CAN0TXTSR_TSR1 _CAN0TXTSR.Bits.TSR1 +#define CAN0TXTSR_TSR2 _CAN0TXTSR.Bits.TSR2 +#define CAN0TXTSR_TSR3 _CAN0TXTSR.Bits.TSR3 +#define CAN0TXTSR_TSR4 _CAN0TXTSR.Bits.TSR4 +#define CAN0TXTSR_TSR5 _CAN0TXTSR.Bits.TSR5 +#define CAN0TXTSR_TSR6 _CAN0TXTSR.Bits.TSR6 +#define CAN0TXTSR_TSR7 _CAN0TXTSR.Bits.TSR7 +#define CAN0TXTSR_TSR8 _CAN0TXTSR.Bits.TSR8 +#define CAN0TXTSR_TSR9 _CAN0TXTSR.Bits.TSR9 +#define CAN0TXTSR_TSR10 _CAN0TXTSR.Bits.TSR10 +#define CAN0TXTSR_TSR11 _CAN0TXTSR.Bits.TSR11 +#define CAN0TXTSR_TSR12 _CAN0TXTSR.Bits.TSR12 +#define CAN0TXTSR_TSR13 _CAN0TXTSR.Bits.TSR13 +#define CAN0TXTSR_TSR14 _CAN0TXTSR.Bits.TSR14 +#define CAN0TXTSR_TSR15 _CAN0TXTSR.Bits.TSR15 + +#define CAN0TXTSR_TSR0_MASK 1U +#define CAN0TXTSR_TSR1_MASK 2U +#define CAN0TXTSR_TSR2_MASK 4U +#define CAN0TXTSR_TSR3_MASK 8U +#define CAN0TXTSR_TSR4_MASK 16U +#define CAN0TXTSR_TSR5_MASK 32U +#define CAN0TXTSR_TSR6_MASK 64U +#define CAN0TXTSR_TSR7_MASK 128U +#define CAN0TXTSR_TSR8_MASK 256U +#define CAN0TXTSR_TSR9_MASK 512U +#define CAN0TXTSR_TSR10_MASK 1024U +#define CAN0TXTSR_TSR11_MASK 2048U +#define CAN0TXTSR_TSR12_MASK 4096U +#define CAN0TXTSR_TSR13_MASK 8192U +#define CAN0TXTSR_TSR14_MASK 16384U +#define CAN0TXTSR_TSR15_MASK 32768U + + +/*** PTT - Port T I/O Register; 0x00000240 ***/ +typedef union { + byte Byte; + struct { + byte PTT0 :1; /* Port T Bit 0 */ + byte PTT1 :1; /* Port T Bit 1 */ + byte PTT2 :1; /* Port T Bit 2 */ + byte PTT3 :1; /* Port T Bit 3 */ + byte PTT4 :1; /* Port T Bit 4 */ + byte PTT5 :1; /* Port T Bit 5 */ + byte PTT6 :1; /* Port T Bit 6 */ + byte PTT7 :1; /* Port T Bit 7 */ + } Bits; +} PTTSTR; +extern volatile PTTSTR _PTT @(REG_BASE + 0x00000240UL); +#define PTT _PTT.Byte +#define PTT_PTT0 _PTT.Bits.PTT0 +#define PTT_PTT1 _PTT.Bits.PTT1 +#define PTT_PTT2 _PTT.Bits.PTT2 +#define PTT_PTT3 _PTT.Bits.PTT3 +#define PTT_PTT4 _PTT.Bits.PTT4 +#define PTT_PTT5 _PTT.Bits.PTT5 +#define PTT_PTT6 _PTT.Bits.PTT6 +#define PTT_PTT7 _PTT.Bits.PTT7 + +#define PTT_PTT0_MASK 1U +#define PTT_PTT1_MASK 2U +#define PTT_PTT2_MASK 4U +#define PTT_PTT3_MASK 8U +#define PTT_PTT4_MASK 16U +#define PTT_PTT5_MASK 32U +#define PTT_PTT6_MASK 64U +#define PTT_PTT7_MASK 128U + + +/*** PTIT - Port T Input Register; 0x00000241 ***/ +typedef union { + byte Byte; + struct { + byte PTIT0 :1; /* Port T Bit 0 */ + byte PTIT1 :1; /* Port T Bit 1 */ + byte PTIT2 :1; /* Port T Bit 2 */ + byte PTIT3 :1; /* Port T Bit 3 */ + byte PTIT4 :1; /* Port T Bit 4 */ + byte PTIT5 :1; /* Port T Bit 5 */ + byte PTIT6 :1; /* Port T Bit 6 */ + byte PTIT7 :1; /* Port T Bit 7 */ + } Bits; +} PTITSTR; +extern volatile PTITSTR _PTIT @(REG_BASE + 0x00000241UL); +#define PTIT _PTIT.Byte +#define PTIT_PTIT0 _PTIT.Bits.PTIT0 +#define PTIT_PTIT1 _PTIT.Bits.PTIT1 +#define PTIT_PTIT2 _PTIT.Bits.PTIT2 +#define PTIT_PTIT3 _PTIT.Bits.PTIT3 +#define PTIT_PTIT4 _PTIT.Bits.PTIT4 +#define PTIT_PTIT5 _PTIT.Bits.PTIT5 +#define PTIT_PTIT6 _PTIT.Bits.PTIT6 +#define PTIT_PTIT7 _PTIT.Bits.PTIT7 + +#define PTIT_PTIT0_MASK 1U +#define PTIT_PTIT1_MASK 2U +#define PTIT_PTIT2_MASK 4U +#define PTIT_PTIT3_MASK 8U +#define PTIT_PTIT4_MASK 16U +#define PTIT_PTIT5_MASK 32U +#define PTIT_PTIT6_MASK 64U +#define PTIT_PTIT7_MASK 128U + + +/*** DDRT - Port T Data Direction Register; 0x00000242 ***/ +typedef union { + byte Byte; + struct { + byte DDRT0 :1; /* Data Direction Port T Bit 0 */ + byte DDRT1 :1; /* Data Direction Port T Bit 1 */ + byte DDRT2 :1; /* Data Direction Port T Bit 2 */ + byte DDRT3 :1; /* Data Direction Port T Bit 3 */ + byte DDRT4 :1; /* Data Direction Port T Bit 4 */ + byte DDRT5 :1; /* Data Direction Port T Bit 5 */ + byte DDRT6 :1; /* Data Direction Port T Bit 6 */ + byte DDRT7 :1; /* Data Direction Port T Bit 7 */ + } Bits; +} DDRTSTR; +extern volatile DDRTSTR _DDRT @(REG_BASE + 0x00000242UL); +#define DDRT _DDRT.Byte +#define DDRT_DDRT0 _DDRT.Bits.DDRT0 +#define DDRT_DDRT1 _DDRT.Bits.DDRT1 +#define DDRT_DDRT2 _DDRT.Bits.DDRT2 +#define DDRT_DDRT3 _DDRT.Bits.DDRT3 +#define DDRT_DDRT4 _DDRT.Bits.DDRT4 +#define DDRT_DDRT5 _DDRT.Bits.DDRT5 +#define DDRT_DDRT6 _DDRT.Bits.DDRT6 +#define DDRT_DDRT7 _DDRT.Bits.DDRT7 + +#define DDRT_DDRT0_MASK 1U +#define DDRT_DDRT1_MASK 2U +#define DDRT_DDRT2_MASK 4U +#define DDRT_DDRT3_MASK 8U +#define DDRT_DDRT4_MASK 16U +#define DDRT_DDRT5_MASK 32U +#define DDRT_DDRT6_MASK 64U +#define DDRT_DDRT7_MASK 128U + + +/*** RDRT - Port T Reduced Drive Register; 0x00000243 ***/ +typedef union { + byte Byte; + struct { + byte RDRT0 :1; /* Reduced Drive Port T Bit 0 */ + byte RDRT1 :1; /* Reduced Drive Port T Bit 1 */ + byte RDRT2 :1; /* Reduced Drive Port T Bit 2 */ + byte RDRT3 :1; /* Reduced Drive Port T Bit 3 */ + byte RDRT4 :1; /* Reduced Drive Port T Bit 4 */ + byte RDRT5 :1; /* Reduced Drive Port T Bit 5 */ + byte RDRT6 :1; /* Reduced Drive Port T Bit 6 */ + byte RDRT7 :1; /* Reduced Drive Port T Bit 7 */ + } Bits; +} RDRTSTR; +extern volatile RDRTSTR _RDRT @(REG_BASE + 0x00000243UL); +#define RDRT _RDRT.Byte +#define RDRT_RDRT0 _RDRT.Bits.RDRT0 +#define RDRT_RDRT1 _RDRT.Bits.RDRT1 +#define RDRT_RDRT2 _RDRT.Bits.RDRT2 +#define RDRT_RDRT3 _RDRT.Bits.RDRT3 +#define RDRT_RDRT4 _RDRT.Bits.RDRT4 +#define RDRT_RDRT5 _RDRT.Bits.RDRT5 +#define RDRT_RDRT6 _RDRT.Bits.RDRT6 +#define RDRT_RDRT7 _RDRT.Bits.RDRT7 + +#define RDRT_RDRT0_MASK 1U +#define RDRT_RDRT1_MASK 2U +#define RDRT_RDRT2_MASK 4U +#define RDRT_RDRT3_MASK 8U +#define RDRT_RDRT4_MASK 16U +#define RDRT_RDRT5_MASK 32U +#define RDRT_RDRT6_MASK 64U +#define RDRT_RDRT7_MASK 128U + + +/*** PERT - Port T Pull Device Enable Register; 0x00000244 ***/ +typedef union { + byte Byte; + struct { + byte PERT0 :1; /* Pull Device Enable Port T Bit 0 */ + byte PERT1 :1; /* Pull Device Enable Port T Bit 1 */ + byte PERT2 :1; /* Pull Device Enable Port T Bit 2 */ + byte PERT3 :1; /* Pull Device Enable Port T Bit 3 */ + byte PERT4 :1; /* Pull Device Enable Port T Bit 4 */ + byte PERT5 :1; /* Pull Device Enable Port T Bit 5 */ + byte PERT6 :1; /* Pull Device Enable Port T Bit 6 */ + byte PERT7 :1; /* Pull Device Enable Port T Bit 7 */ + } Bits; +} PERTSTR; +extern volatile PERTSTR _PERT @(REG_BASE + 0x00000244UL); +#define PERT _PERT.Byte +#define PERT_PERT0 _PERT.Bits.PERT0 +#define PERT_PERT1 _PERT.Bits.PERT1 +#define PERT_PERT2 _PERT.Bits.PERT2 +#define PERT_PERT3 _PERT.Bits.PERT3 +#define PERT_PERT4 _PERT.Bits.PERT4 +#define PERT_PERT5 _PERT.Bits.PERT5 +#define PERT_PERT6 _PERT.Bits.PERT6 +#define PERT_PERT7 _PERT.Bits.PERT7 + +#define PERT_PERT0_MASK 1U +#define PERT_PERT1_MASK 2U +#define PERT_PERT2_MASK 4U +#define PERT_PERT3_MASK 8U +#define PERT_PERT4_MASK 16U +#define PERT_PERT5_MASK 32U +#define PERT_PERT6_MASK 64U +#define PERT_PERT7_MASK 128U + + +/*** PPST - Port T Polarity Select Register; 0x00000245 ***/ +typedef union { + byte Byte; + struct { + byte PPST0 :1; /* Pull Select Port T Bit 0 */ + byte PPST1 :1; /* Pull Select Port T Bit 1 */ + byte PPST2 :1; /* Pull Select Port T Bit 2 */ + byte PPST3 :1; /* Pull Select Port T Bit 3 */ + byte PPST4 :1; /* Pull Select Port T Bit 4 */ + byte PPST5 :1; /* Pull Select Port T Bit 5 */ + byte PPST6 :1; /* Pull Select Port T Bit 6 */ + byte PPST7 :1; /* Pull Select Port T Bit 7 */ + } Bits; +} PPSTSTR; +extern volatile PPSTSTR _PPST @(REG_BASE + 0x00000245UL); +#define PPST _PPST.Byte +#define PPST_PPST0 _PPST.Bits.PPST0 +#define PPST_PPST1 _PPST.Bits.PPST1 +#define PPST_PPST2 _PPST.Bits.PPST2 +#define PPST_PPST3 _PPST.Bits.PPST3 +#define PPST_PPST4 _PPST.Bits.PPST4 +#define PPST_PPST5 _PPST.Bits.PPST5 +#define PPST_PPST6 _PPST.Bits.PPST6 +#define PPST_PPST7 _PPST.Bits.PPST7 + +#define PPST_PPST0_MASK 1U +#define PPST_PPST1_MASK 2U +#define PPST_PPST2_MASK 4U +#define PPST_PPST3_MASK 8U +#define PPST_PPST4_MASK 16U +#define PPST_PPST5_MASK 32U +#define PPST_PPST6_MASK 64U +#define PPST_PPST7_MASK 128U + + +/*** PTS - Port S I/O Register; 0x00000248 ***/ +typedef union { + byte Byte; + struct { + byte PTS0 :1; /* Port S Bit 0 */ + byte PTS1 :1; /* Port S Bit 1 */ + byte PTS2 :1; /* Port S Bit 2 */ + byte PTS3 :1; /* Port S Bit 3 */ + byte PTS4 :1; /* Port S Bit 4 */ + byte PTS5 :1; /* Port S Bit 5 */ + byte PTS6 :1; /* Port S Bit 6 */ + byte PTS7 :1; /* Port S Bit 7 */ + } Bits; +} PTSSTR; +extern volatile PTSSTR _PTS @(REG_BASE + 0x00000248UL); +#define PTS _PTS.Byte +#define PTS_PTS0 _PTS.Bits.PTS0 +#define PTS_PTS1 _PTS.Bits.PTS1 +#define PTS_PTS2 _PTS.Bits.PTS2 +#define PTS_PTS3 _PTS.Bits.PTS3 +#define PTS_PTS4 _PTS.Bits.PTS4 +#define PTS_PTS5 _PTS.Bits.PTS5 +#define PTS_PTS6 _PTS.Bits.PTS6 +#define PTS_PTS7 _PTS.Bits.PTS7 + +#define PTS_PTS0_MASK 1U +#define PTS_PTS1_MASK 2U +#define PTS_PTS2_MASK 4U +#define PTS_PTS3_MASK 8U +#define PTS_PTS4_MASK 16U +#define PTS_PTS5_MASK 32U +#define PTS_PTS6_MASK 64U +#define PTS_PTS7_MASK 128U + + +/*** PTIS - Port S Input Register; 0x00000249 ***/ +typedef union { + byte Byte; + struct { + byte PTIS0 :1; /* Port S Bit 0 */ + byte PTIS1 :1; /* Port S Bit 1 */ + byte PTIS2 :1; /* Port S Bit 2 */ + byte PTIS3 :1; /* Port S Bit 3 */ + byte PTIS4 :1; /* Port S Bit 4 */ + byte PTIS5 :1; /* Port S Bit 5 */ + byte PTIS6 :1; /* Port S Bit 6 */ + byte PTIS7 :1; /* Port S Bit 7 */ + } Bits; +} PTISSTR; +extern volatile PTISSTR _PTIS @(REG_BASE + 0x00000249UL); +#define PTIS _PTIS.Byte +#define PTIS_PTIS0 _PTIS.Bits.PTIS0 +#define PTIS_PTIS1 _PTIS.Bits.PTIS1 +#define PTIS_PTIS2 _PTIS.Bits.PTIS2 +#define PTIS_PTIS3 _PTIS.Bits.PTIS3 +#define PTIS_PTIS4 _PTIS.Bits.PTIS4 +#define PTIS_PTIS5 _PTIS.Bits.PTIS5 +#define PTIS_PTIS6 _PTIS.Bits.PTIS6 +#define PTIS_PTIS7 _PTIS.Bits.PTIS7 + +#define PTIS_PTIS0_MASK 1U +#define PTIS_PTIS1_MASK 2U +#define PTIS_PTIS2_MASK 4U +#define PTIS_PTIS3_MASK 8U +#define PTIS_PTIS4_MASK 16U +#define PTIS_PTIS5_MASK 32U +#define PTIS_PTIS6_MASK 64U +#define PTIS_PTIS7_MASK 128U + + +/*** DDRS - Port S Data Direction Register; 0x0000024A ***/ +typedef union { + byte Byte; + struct { + byte DDRS0 :1; /* Data Direction Port S Bit 0 */ + byte DDRS1 :1; /* Data Direction Port S Bit 1 */ + byte DDRS2 :1; /* Data Direction Port S Bit 2 */ + byte DDRS3 :1; /* Data Direction Port S Bit 3 */ + byte DDRS4 :1; /* Data Direction Port S Bit 4 */ + byte DDRS5 :1; /* Data Direction Port S Bit 5 */ + byte DDRS6 :1; /* Data Direction Port S Bit 6 */ + byte DDRS7 :1; /* Data Direction Port S Bit 7 */ + } Bits; +} DDRSSTR; +extern volatile DDRSSTR _DDRS @(REG_BASE + 0x0000024AUL); +#define DDRS _DDRS.Byte +#define DDRS_DDRS0 _DDRS.Bits.DDRS0 +#define DDRS_DDRS1 _DDRS.Bits.DDRS1 +#define DDRS_DDRS2 _DDRS.Bits.DDRS2 +#define DDRS_DDRS3 _DDRS.Bits.DDRS3 +#define DDRS_DDRS4 _DDRS.Bits.DDRS4 +#define DDRS_DDRS5 _DDRS.Bits.DDRS5 +#define DDRS_DDRS6 _DDRS.Bits.DDRS6 +#define DDRS_DDRS7 _DDRS.Bits.DDRS7 + +#define DDRS_DDRS0_MASK 1U +#define DDRS_DDRS1_MASK 2U +#define DDRS_DDRS2_MASK 4U +#define DDRS_DDRS3_MASK 8U +#define DDRS_DDRS4_MASK 16U +#define DDRS_DDRS5_MASK 32U +#define DDRS_DDRS6_MASK 64U +#define DDRS_DDRS7_MASK 128U + + +/*** RDRS - Port S Reduced Drive Register; 0x0000024B ***/ +typedef union { + byte Byte; + struct { + byte RDRS0 :1; /* Reduced Drive Port S Bit 0 */ + byte RDRS1 :1; /* Reduced Drive Port S Bit 1 */ + byte RDRS2 :1; /* Reduced Drive Port S Bit 2 */ + byte RDRS3 :1; /* Reduced Drive Port S Bit 3 */ + byte RDRS4 :1; /* Reduced Drive Port S Bit 4 */ + byte RDRS5 :1; /* Reduced Drive Port S Bit 5 */ + byte RDRS6 :1; /* Reduced Drive Port S Bit 6 */ + byte RDRS7 :1; /* Reduced Drive Port S Bit 7 */ + } Bits; +} RDRSSTR; +extern volatile RDRSSTR _RDRS @(REG_BASE + 0x0000024BUL); +#define RDRS _RDRS.Byte +#define RDRS_RDRS0 _RDRS.Bits.RDRS0 +#define RDRS_RDRS1 _RDRS.Bits.RDRS1 +#define RDRS_RDRS2 _RDRS.Bits.RDRS2 +#define RDRS_RDRS3 _RDRS.Bits.RDRS3 +#define RDRS_RDRS4 _RDRS.Bits.RDRS4 +#define RDRS_RDRS5 _RDRS.Bits.RDRS5 +#define RDRS_RDRS6 _RDRS.Bits.RDRS6 +#define RDRS_RDRS7 _RDRS.Bits.RDRS7 + +#define RDRS_RDRS0_MASK 1U +#define RDRS_RDRS1_MASK 2U +#define RDRS_RDRS2_MASK 4U +#define RDRS_RDRS3_MASK 8U +#define RDRS_RDRS4_MASK 16U +#define RDRS_RDRS5_MASK 32U +#define RDRS_RDRS6_MASK 64U +#define RDRS_RDRS7_MASK 128U + + +/*** PERS - Port S Pull Device Enable Register; 0x0000024C ***/ +typedef union { + byte Byte; + struct { + byte PERS0 :1; /* Pull Device Enable Port S Bit 0 */ + byte PERS1 :1; /* Pull Device Enable Port S Bit 1 */ + byte PERS2 :1; /* Pull Device Enable Port S Bit 2 */ + byte PERS3 :1; /* Pull Device Enable Port S Bit 3 */ + byte PERS4 :1; /* Pull Device Enable Port S Bit 4 */ + byte PERS5 :1; /* Pull Device Enable Port S Bit 5 */ + byte PERS6 :1; /* Pull Device Enable Port S Bit 6 */ + byte PERS7 :1; /* Pull Device Enable Port S Bit 7 */ + } Bits; +} PERSSTR; +extern volatile PERSSTR _PERS @(REG_BASE + 0x0000024CUL); +#define PERS _PERS.Byte +#define PERS_PERS0 _PERS.Bits.PERS0 +#define PERS_PERS1 _PERS.Bits.PERS1 +#define PERS_PERS2 _PERS.Bits.PERS2 +#define PERS_PERS3 _PERS.Bits.PERS3 +#define PERS_PERS4 _PERS.Bits.PERS4 +#define PERS_PERS5 _PERS.Bits.PERS5 +#define PERS_PERS6 _PERS.Bits.PERS6 +#define PERS_PERS7 _PERS.Bits.PERS7 + +#define PERS_PERS0_MASK 1U +#define PERS_PERS1_MASK 2U +#define PERS_PERS2_MASK 4U +#define PERS_PERS3_MASK 8U +#define PERS_PERS4_MASK 16U +#define PERS_PERS5_MASK 32U +#define PERS_PERS6_MASK 64U +#define PERS_PERS7_MASK 128U + + +/*** PPSS - Port S Polarity Select Register; 0x0000024D ***/ +typedef union { + byte Byte; + struct { + byte PPSS0 :1; /* Pull Select Port S Bit 0 */ + byte PPSS1 :1; /* Pull Select Port S Bit 1 */ + byte PPSS2 :1; /* Pull Select Port S Bit 2 */ + byte PPSS3 :1; /* Pull Select Port S Bit 3 */ + byte PPSS4 :1; /* Pull Select Port S Bit 4 */ + byte PPSS5 :1; /* Pull Select Port S Bit 5 */ + byte PPSS6 :1; /* Pull Select Port S Bit 6 */ + byte PPSS7 :1; /* Pull Select Port S Bit 7 */ + } Bits; +} PPSSSTR; +extern volatile PPSSSTR _PPSS @(REG_BASE + 0x0000024DUL); +#define PPSS _PPSS.Byte +#define PPSS_PPSS0 _PPSS.Bits.PPSS0 +#define PPSS_PPSS1 _PPSS.Bits.PPSS1 +#define PPSS_PPSS2 _PPSS.Bits.PPSS2 +#define PPSS_PPSS3 _PPSS.Bits.PPSS3 +#define PPSS_PPSS4 _PPSS.Bits.PPSS4 +#define PPSS_PPSS5 _PPSS.Bits.PPSS5 +#define PPSS_PPSS6 _PPSS.Bits.PPSS6 +#define PPSS_PPSS7 _PPSS.Bits.PPSS7 + +#define PPSS_PPSS0_MASK 1U +#define PPSS_PPSS1_MASK 2U +#define PPSS_PPSS2_MASK 4U +#define PPSS_PPSS3_MASK 8U +#define PPSS_PPSS4_MASK 16U +#define PPSS_PPSS5_MASK 32U +#define PPSS_PPSS6_MASK 64U +#define PPSS_PPSS7_MASK 128U + + +/*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***/ +typedef union { + byte Byte; + struct { + byte WOMS0 :1; /* Wired-Or Mode Port S Bit 0 */ + byte WOMS1 :1; /* Wired-Or Mode Port S Bit 1 */ + byte WOMS2 :1; /* Wired-Or Mode Port S Bit 2 */ + byte WOMS3 :1; /* Wired-Or Mode Port S Bit 3 */ + byte WOMS4 :1; /* Wired-Or Mode Port S Bit 4 */ + byte WOMS5 :1; /* Wired-Or Mode Port S Bit 5 */ + byte WOMS6 :1; /* Wired-Or Mode Port S Bit 6 */ + byte WOMS7 :1; /* Wired-Or Mode Port S Bit 7 */ + } Bits; +} WOMSSTR; +extern volatile WOMSSTR _WOMS @(REG_BASE + 0x0000024EUL); +#define WOMS _WOMS.Byte +#define WOMS_WOMS0 _WOMS.Bits.WOMS0 +#define WOMS_WOMS1 _WOMS.Bits.WOMS1 +#define WOMS_WOMS2 _WOMS.Bits.WOMS2 +#define WOMS_WOMS3 _WOMS.Bits.WOMS3 +#define WOMS_WOMS4 _WOMS.Bits.WOMS4 +#define WOMS_WOMS5 _WOMS.Bits.WOMS5 +#define WOMS_WOMS6 _WOMS.Bits.WOMS6 +#define WOMS_WOMS7 _WOMS.Bits.WOMS7 + +#define WOMS_WOMS0_MASK 1U +#define WOMS_WOMS1_MASK 2U +#define WOMS_WOMS2_MASK 4U +#define WOMS_WOMS3_MASK 8U +#define WOMS_WOMS4_MASK 16U +#define WOMS_WOMS5_MASK 32U +#define WOMS_WOMS6_MASK 64U +#define WOMS_WOMS7_MASK 128U + + +/*** PTM - Port M I/O Register; 0x00000250 ***/ +typedef union { + byte Byte; + struct { + byte PTM0 :1; /* Port M Bit 0 */ + byte PTM1 :1; /* Port M Bit 1 */ + byte PTM2 :1; /* Port M Bit 2 */ + byte PTM3 :1; /* Port M Bit 3 */ + byte PTM4 :1; /* Port M Bit 4 */ + byte PTM5 :1; /* Port M Bit 5 */ + byte PTM6 :1; /* Port M Bit 6 */ + byte PTM7 :1; /* Port M Bit 7 */ + } Bits; +} PTMSTR; +extern volatile PTMSTR _PTM @(REG_BASE + 0x00000250UL); +#define PTM _PTM.Byte +#define PTM_PTM0 _PTM.Bits.PTM0 +#define PTM_PTM1 _PTM.Bits.PTM1 +#define PTM_PTM2 _PTM.Bits.PTM2 +#define PTM_PTM3 _PTM.Bits.PTM3 +#define PTM_PTM4 _PTM.Bits.PTM4 +#define PTM_PTM5 _PTM.Bits.PTM5 +#define PTM_PTM6 _PTM.Bits.PTM6 +#define PTM_PTM7 _PTM.Bits.PTM7 + +#define PTM_PTM0_MASK 1U +#define PTM_PTM1_MASK 2U +#define PTM_PTM2_MASK 4U +#define PTM_PTM3_MASK 8U +#define PTM_PTM4_MASK 16U +#define PTM_PTM5_MASK 32U +#define PTM_PTM6_MASK 64U +#define PTM_PTM7_MASK 128U + + +/*** PTIM - Port M Input Register; 0x00000251 ***/ +typedef union { + byte Byte; + struct { + byte PTIM0 :1; /* Port M Bit 0 */ + byte PTIM1 :1; /* Port M Bit 1 */ + byte PTIM2 :1; /* Port M Bit 2 */ + byte PTIM3 :1; /* Port M Bit 3 */ + byte PTIM4 :1; /* Port M Bit 4 */ + byte PTIM5 :1; /* Port M Bit 5 */ + byte PTIM6 :1; /* Port M Bit 6 */ + byte PTIM7 :1; /* Port M Bit 7 */ + } Bits; +} PTIMSTR; +extern volatile PTIMSTR _PTIM @(REG_BASE + 0x00000251UL); +#define PTIM _PTIM.Byte +#define PTIM_PTIM0 _PTIM.Bits.PTIM0 +#define PTIM_PTIM1 _PTIM.Bits.PTIM1 +#define PTIM_PTIM2 _PTIM.Bits.PTIM2 +#define PTIM_PTIM3 _PTIM.Bits.PTIM3 +#define PTIM_PTIM4 _PTIM.Bits.PTIM4 +#define PTIM_PTIM5 _PTIM.Bits.PTIM5 +#define PTIM_PTIM6 _PTIM.Bits.PTIM6 +#define PTIM_PTIM7 _PTIM.Bits.PTIM7 + +#define PTIM_PTIM0_MASK 1U +#define PTIM_PTIM1_MASK 2U +#define PTIM_PTIM2_MASK 4U +#define PTIM_PTIM3_MASK 8U +#define PTIM_PTIM4_MASK 16U +#define PTIM_PTIM5_MASK 32U +#define PTIM_PTIM6_MASK 64U +#define PTIM_PTIM7_MASK 128U + + +/*** DDRM - Port M Data Direction Register; 0x00000252 ***/ +typedef union { + byte Byte; + struct { + byte DDRM0 :1; /* Data Direction Port M Bit 0 */ + byte DDRM1 :1; /* Data Direction Port M Bit 1 */ + byte DDRM2 :1; /* Data Direction Port M Bit 2 */ + byte DDRM3 :1; /* Data Direction Port M Bit 3 */ + byte DDRM4 :1; /* Data Direction Port M Bit 4 */ + byte DDRM5 :1; /* Data Direction Port M Bit 5 */ + byte DDRM6 :1; /* Data Direction Port M Bit 6 */ + byte DDRM7 :1; /* Data Direction Port M Bit 7 */ + } Bits; +} DDRMSTR; +extern volatile DDRMSTR _DDRM @(REG_BASE + 0x00000252UL); +#define DDRM _DDRM.Byte +#define DDRM_DDRM0 _DDRM.Bits.DDRM0 +#define DDRM_DDRM1 _DDRM.Bits.DDRM1 +#define DDRM_DDRM2 _DDRM.Bits.DDRM2 +#define DDRM_DDRM3 _DDRM.Bits.DDRM3 +#define DDRM_DDRM4 _DDRM.Bits.DDRM4 +#define DDRM_DDRM5 _DDRM.Bits.DDRM5 +#define DDRM_DDRM6 _DDRM.Bits.DDRM6 +#define DDRM_DDRM7 _DDRM.Bits.DDRM7 + +#define DDRM_DDRM0_MASK 1U +#define DDRM_DDRM1_MASK 2U +#define DDRM_DDRM2_MASK 4U +#define DDRM_DDRM3_MASK 8U +#define DDRM_DDRM4_MASK 16U +#define DDRM_DDRM5_MASK 32U +#define DDRM_DDRM6_MASK 64U +#define DDRM_DDRM7_MASK 128U + + +/*** RDRM - Port M Reduced Drive Register; 0x00000253 ***/ +typedef union { + byte Byte; + struct { + byte RDRM0 :1; /* Reduced Drive Port M Bit 0 */ + byte RDRM1 :1; /* Reduced Drive Port M Bit 1 */ + byte RDRM2 :1; /* Reduced Drive Port M Bit 2 */ + byte RDRM3 :1; /* Reduced Drive Port M Bit 3 */ + byte RDRM4 :1; /* Reduced Drive Port M Bit 4 */ + byte RDRM5 :1; /* Reduced Drive Port M Bit 5 */ + byte RDRM6 :1; /* Reduced Drive Port M Bit 6 */ + byte RDRM7 :1; /* Reduced Drive Port M Bit 7 */ + } Bits; +} RDRMSTR; +extern volatile RDRMSTR _RDRM @(REG_BASE + 0x00000253UL); +#define RDRM _RDRM.Byte +#define RDRM_RDRM0 _RDRM.Bits.RDRM0 +#define RDRM_RDRM1 _RDRM.Bits.RDRM1 +#define RDRM_RDRM2 _RDRM.Bits.RDRM2 +#define RDRM_RDRM3 _RDRM.Bits.RDRM3 +#define RDRM_RDRM4 _RDRM.Bits.RDRM4 +#define RDRM_RDRM5 _RDRM.Bits.RDRM5 +#define RDRM_RDRM6 _RDRM.Bits.RDRM6 +#define RDRM_RDRM7 _RDRM.Bits.RDRM7 + +#define RDRM_RDRM0_MASK 1U +#define RDRM_RDRM1_MASK 2U +#define RDRM_RDRM2_MASK 4U +#define RDRM_RDRM3_MASK 8U +#define RDRM_RDRM4_MASK 16U +#define RDRM_RDRM5_MASK 32U +#define RDRM_RDRM6_MASK 64U +#define RDRM_RDRM7_MASK 128U + + +/*** PERM - Port M Pull Device Enable Register; 0x00000254 ***/ +typedef union { + byte Byte; + struct { + byte PERM0 :1; /* Pull Device Enable Port M Bit 0 */ + byte PERM1 :1; /* Pull Device Enable Port M Bit 1 */ + byte PERM2 :1; /* Pull Device Enable Port M Bit 2 */ + byte PERM3 :1; /* Pull Device Enable Port M Bit 3 */ + byte PERM4 :1; /* Pull Device Enable Port M Bit 4 */ + byte PERM5 :1; /* Pull Device Enable Port M Bit 5 */ + byte PERM6 :1; /* Pull Device Enable Port M Bit 6 */ + byte PERM7 :1; /* Pull Device Enable Port M Bit 7 */ + } Bits; +} PERMSTR; +extern volatile PERMSTR _PERM @(REG_BASE + 0x00000254UL); +#define PERM _PERM.Byte +#define PERM_PERM0 _PERM.Bits.PERM0 +#define PERM_PERM1 _PERM.Bits.PERM1 +#define PERM_PERM2 _PERM.Bits.PERM2 +#define PERM_PERM3 _PERM.Bits.PERM3 +#define PERM_PERM4 _PERM.Bits.PERM4 +#define PERM_PERM5 _PERM.Bits.PERM5 +#define PERM_PERM6 _PERM.Bits.PERM6 +#define PERM_PERM7 _PERM.Bits.PERM7 + +#define PERM_PERM0_MASK 1U +#define PERM_PERM1_MASK 2U +#define PERM_PERM2_MASK 4U +#define PERM_PERM3_MASK 8U +#define PERM_PERM4_MASK 16U +#define PERM_PERM5_MASK 32U +#define PERM_PERM6_MASK 64U +#define PERM_PERM7_MASK 128U + + +/*** PPSM - Port M Polarity Select Register; 0x00000255 ***/ +typedef union { + byte Byte; + struct { + byte PPSM0 :1; /* Pull Select Port M Bit 0 */ + byte PPSM1 :1; /* Pull Select Port M Bit 1 */ + byte PPSM2 :1; /* Pull Select Port M Bit 2 */ + byte PPSM3 :1; /* Pull Select Port M Bit 3 */ + byte PPSM4 :1; /* Pull Select Port M Bit 4 */ + byte PPSM5 :1; /* Pull Select Port M Bit 5 */ + byte PPSM6 :1; /* Pull Select Port M Bit 6 */ + byte PPSM7 :1; /* Pull Select Port M Bit 7 */ + } Bits; +} PPSMSTR; +extern volatile PPSMSTR _PPSM @(REG_BASE + 0x00000255UL); +#define PPSM _PPSM.Byte +#define PPSM_PPSM0 _PPSM.Bits.PPSM0 +#define PPSM_PPSM1 _PPSM.Bits.PPSM1 +#define PPSM_PPSM2 _PPSM.Bits.PPSM2 +#define PPSM_PPSM3 _PPSM.Bits.PPSM3 +#define PPSM_PPSM4 _PPSM.Bits.PPSM4 +#define PPSM_PPSM5 _PPSM.Bits.PPSM5 +#define PPSM_PPSM6 _PPSM.Bits.PPSM6 +#define PPSM_PPSM7 _PPSM.Bits.PPSM7 + +#define PPSM_PPSM0_MASK 1U +#define PPSM_PPSM1_MASK 2U +#define PPSM_PPSM2_MASK 4U +#define PPSM_PPSM3_MASK 8U +#define PPSM_PPSM4_MASK 16U +#define PPSM_PPSM5_MASK 32U +#define PPSM_PPSM6_MASK 64U +#define PPSM_PPSM7_MASK 128U + + +/*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***/ +typedef union { + byte Byte; + struct { + byte WOMM0 :1; /* Wired-Or Mode Port M Bit 0 */ + byte WOMM1 :1; /* Wired-Or Mode Port M Bit 1 */ + byte WOMM2 :1; /* Wired-Or Mode Port M Bit 2 */ + byte WOMM3 :1; /* Wired-Or Mode Port M Bit 3 */ + byte WOMM4 :1; /* Wired-Or Mode Port M Bit 4 */ + byte WOMM5 :1; /* Wired-Or Mode Port M Bit 5 */ + byte WOMM6 :1; /* Wired-Or Mode Port M Bit 6 */ + byte WOMM7 :1; /* Wired-Or Mode Port M Bit 7 */ + } Bits; +} WOMMSTR; +extern volatile WOMMSTR _WOMM @(REG_BASE + 0x00000256UL); +#define WOMM _WOMM.Byte +#define WOMM_WOMM0 _WOMM.Bits.WOMM0 +#define WOMM_WOMM1 _WOMM.Bits.WOMM1 +#define WOMM_WOMM2 _WOMM.Bits.WOMM2 +#define WOMM_WOMM3 _WOMM.Bits.WOMM3 +#define WOMM_WOMM4 _WOMM.Bits.WOMM4 +#define WOMM_WOMM5 _WOMM.Bits.WOMM5 +#define WOMM_WOMM6 _WOMM.Bits.WOMM6 +#define WOMM_WOMM7 _WOMM.Bits.WOMM7 + +#define WOMM_WOMM0_MASK 1U +#define WOMM_WOMM1_MASK 2U +#define WOMM_WOMM2_MASK 4U +#define WOMM_WOMM3_MASK 8U +#define WOMM_WOMM4_MASK 16U +#define WOMM_WOMM5_MASK 32U +#define WOMM_WOMM6_MASK 64U +#define WOMM_WOMM7_MASK 128U + + +/*** MODRR - Module Routing Register; 0x00000257 ***/ +typedef union { + byte Byte; + struct { + byte MODRR0 :1; /* CAN0 Routing Bit 0 */ + byte MODRR1 :1; /* CAN0 Routing Bit 1 */ + byte MODRR2 :1; /* CAN4 Routing Bit 0 */ + byte MODRR3 :1; /* CAN4 Routing Bit 1 */ + byte MODRR4 :1; /* SPI0 Routing */ + byte MODRR5 :1; /* SPI1 Routing */ + byte MODRR6 :1; /* SPI2 Routing */ + byte :1; + } Bits; + struct { + byte grpMODRR :7; + byte :1; + } MergedBits; +} MODRRSTR; +extern volatile MODRRSTR _MODRR @(REG_BASE + 0x00000257UL); +#define MODRR _MODRR.Byte +#define MODRR_MODRR0 _MODRR.Bits.MODRR0 +#define MODRR_MODRR1 _MODRR.Bits.MODRR1 +#define MODRR_MODRR2 _MODRR.Bits.MODRR2 +#define MODRR_MODRR3 _MODRR.Bits.MODRR3 +#define MODRR_MODRR4 _MODRR.Bits.MODRR4 +#define MODRR_MODRR5 _MODRR.Bits.MODRR5 +#define MODRR_MODRR6 _MODRR.Bits.MODRR6 +#define MODRR_MODRR _MODRR.MergedBits.grpMODRR + +#define MODRR_MODRR0_MASK 1U +#define MODRR_MODRR1_MASK 2U +#define MODRR_MODRR2_MASK 4U +#define MODRR_MODRR3_MASK 8U +#define MODRR_MODRR4_MASK 16U +#define MODRR_MODRR5_MASK 32U +#define MODRR_MODRR6_MASK 64U +#define MODRR_MODRR_MASK 127U +#define MODRR_MODRR_BITNUM 0U + + +/*** PTP - Port P I/O Register; 0x00000258 ***/ +typedef union { + byte Byte; + struct { + byte PTP0 :1; /* Port P Bit 0 */ + byte PTP1 :1; /* Port P Bit 1 */ + byte PTP2 :1; /* Port P Bit 2 */ + byte PTP3 :1; /* Port P Bit 3 */ + byte PTP4 :1; /* Port P Bit 4 */ + byte PTP5 :1; /* Port P Bit 5 */ + byte PTP6 :1; /* Port P Bit 6 */ + byte PTP7 :1; /* Port P Bit 7 */ + } Bits; +} PTPSTR; +extern volatile PTPSTR _PTP @(REG_BASE + 0x00000258UL); +#define PTP _PTP.Byte +#define PTP_PTP0 _PTP.Bits.PTP0 +#define PTP_PTP1 _PTP.Bits.PTP1 +#define PTP_PTP2 _PTP.Bits.PTP2 +#define PTP_PTP3 _PTP.Bits.PTP3 +#define PTP_PTP4 _PTP.Bits.PTP4 +#define PTP_PTP5 _PTP.Bits.PTP5 +#define PTP_PTP6 _PTP.Bits.PTP6 +#define PTP_PTP7 _PTP.Bits.PTP7 + +#define PTP_PTP0_MASK 1U +#define PTP_PTP1_MASK 2U +#define PTP_PTP2_MASK 4U +#define PTP_PTP3_MASK 8U +#define PTP_PTP4_MASK 16U +#define PTP_PTP5_MASK 32U +#define PTP_PTP6_MASK 64U +#define PTP_PTP7_MASK 128U + + +/*** PTIP - Port P Input Register; 0x00000259 ***/ +typedef union { + byte Byte; + struct { + byte PTIP0 :1; /* Port P Bit 0 */ + byte PTIP1 :1; /* Port P Bit 1 */ + byte PTIP2 :1; /* Port P Bit 2 */ + byte PTIP3 :1; /* Port P Bit 3 */ + byte PTIP4 :1; /* Port P Bit 4 */ + byte PTIP5 :1; /* Port P Bit 5 */ + byte PTIP6 :1; /* Port P Bit 6 */ + byte PTIP7 :1; /* Port P Bit 7 */ + } Bits; +} PTIPSTR; +extern volatile PTIPSTR _PTIP @(REG_BASE + 0x00000259UL); +#define PTIP _PTIP.Byte +#define PTIP_PTIP0 _PTIP.Bits.PTIP0 +#define PTIP_PTIP1 _PTIP.Bits.PTIP1 +#define PTIP_PTIP2 _PTIP.Bits.PTIP2 +#define PTIP_PTIP3 _PTIP.Bits.PTIP3 +#define PTIP_PTIP4 _PTIP.Bits.PTIP4 +#define PTIP_PTIP5 _PTIP.Bits.PTIP5 +#define PTIP_PTIP6 _PTIP.Bits.PTIP6 +#define PTIP_PTIP7 _PTIP.Bits.PTIP7 + +#define PTIP_PTIP0_MASK 1U +#define PTIP_PTIP1_MASK 2U +#define PTIP_PTIP2_MASK 4U +#define PTIP_PTIP3_MASK 8U +#define PTIP_PTIP4_MASK 16U +#define PTIP_PTIP5_MASK 32U +#define PTIP_PTIP6_MASK 64U +#define PTIP_PTIP7_MASK 128U + + +/*** DDRP - Port P Data Direction Register; 0x0000025A ***/ +typedef union { + byte Byte; + struct { + byte DDRP0 :1; /* Data Direction Port P Bit 0 */ + byte DDRP1 :1; /* Data Direction Port P Bit 1 */ + byte DDRP2 :1; /* Data Direction Port P Bit 2 */ + byte DDRP3 :1; /* Data Direction Port P Bit 3 */ + byte DDRP4 :1; /* Data Direction Port P Bit 4 */ + byte DDRP5 :1; /* Data Direction Port P Bit 5 */ + byte DDRP6 :1; /* Data Direction Port P Bit 6 */ + byte DDRP7 :1; /* Data Direction Port P Bit 7 */ + } Bits; +} DDRPSTR; +extern volatile DDRPSTR _DDRP @(REG_BASE + 0x0000025AUL); +#define DDRP _DDRP.Byte +#define DDRP_DDRP0 _DDRP.Bits.DDRP0 +#define DDRP_DDRP1 _DDRP.Bits.DDRP1 +#define DDRP_DDRP2 _DDRP.Bits.DDRP2 +#define DDRP_DDRP3 _DDRP.Bits.DDRP3 +#define DDRP_DDRP4 _DDRP.Bits.DDRP4 +#define DDRP_DDRP5 _DDRP.Bits.DDRP5 +#define DDRP_DDRP6 _DDRP.Bits.DDRP6 +#define DDRP_DDRP7 _DDRP.Bits.DDRP7 + +#define DDRP_DDRP0_MASK 1U +#define DDRP_DDRP1_MASK 2U +#define DDRP_DDRP2_MASK 4U +#define DDRP_DDRP3_MASK 8U +#define DDRP_DDRP4_MASK 16U +#define DDRP_DDRP5_MASK 32U +#define DDRP_DDRP6_MASK 64U +#define DDRP_DDRP7_MASK 128U + + +/*** RDRP - Port P Reduced Drive Register; 0x0000025B ***/ +typedef union { + byte Byte; + struct { + byte RDRP0 :1; /* Reduced Drive Port P Bit 0 */ + byte RDRP1 :1; /* Reduced Drive Port P Bit 1 */ + byte RDRP2 :1; /* Reduced Drive Port P Bit 2 */ + byte RDRP3 :1; /* Reduced Drive Port P Bit 3 */ + byte RDRP4 :1; /* Reduced Drive Port P Bit 4 */ + byte RDRP5 :1; /* Reduced Drive Port P Bit 5 */ + byte RDRP6 :1; /* Reduced Drive Port P Bit 6 */ + byte RDRP7 :1; /* Reduced Drive Port P Bit 7 */ + } Bits; +} RDRPSTR; +extern volatile RDRPSTR _RDRP @(REG_BASE + 0x0000025BUL); +#define RDRP _RDRP.Byte +#define RDRP_RDRP0 _RDRP.Bits.RDRP0 +#define RDRP_RDRP1 _RDRP.Bits.RDRP1 +#define RDRP_RDRP2 _RDRP.Bits.RDRP2 +#define RDRP_RDRP3 _RDRP.Bits.RDRP3 +#define RDRP_RDRP4 _RDRP.Bits.RDRP4 +#define RDRP_RDRP5 _RDRP.Bits.RDRP5 +#define RDRP_RDRP6 _RDRP.Bits.RDRP6 +#define RDRP_RDRP7 _RDRP.Bits.RDRP7 + +#define RDRP_RDRP0_MASK 1U +#define RDRP_RDRP1_MASK 2U +#define RDRP_RDRP2_MASK 4U +#define RDRP_RDRP3_MASK 8U +#define RDRP_RDRP4_MASK 16U +#define RDRP_RDRP5_MASK 32U +#define RDRP_RDRP6_MASK 64U +#define RDRP_RDRP7_MASK 128U + + +/*** PERP - Port P Pull Device Enable Register; 0x0000025C ***/ +typedef union { + byte Byte; + struct { + byte PERP0 :1; /* Pull Device Enable Port P Bit 0 */ + byte PERP1 :1; /* Pull Device Enable Port P Bit 1 */ + byte PERP2 :1; /* Pull Device Enable Port P Bit 2 */ + byte PERP3 :1; /* Pull Device Enable Port P Bit 3 */ + byte PERP4 :1; /* Pull Device Enable Port P Bit 4 */ + byte PERP5 :1; /* Pull Device Enable Port P Bit 5 */ + byte PERP6 :1; /* Pull Device Enable Port P Bit 6 */ + byte PERP7 :1; /* Pull Device Enable Port P Bit 7 */ + } Bits; +} PERPSTR; +extern volatile PERPSTR _PERP @(REG_BASE + 0x0000025CUL); +#define PERP _PERP.Byte +#define PERP_PERP0 _PERP.Bits.PERP0 +#define PERP_PERP1 _PERP.Bits.PERP1 +#define PERP_PERP2 _PERP.Bits.PERP2 +#define PERP_PERP3 _PERP.Bits.PERP3 +#define PERP_PERP4 _PERP.Bits.PERP4 +#define PERP_PERP5 _PERP.Bits.PERP5 +#define PERP_PERP6 _PERP.Bits.PERP6 +#define PERP_PERP7 _PERP.Bits.PERP7 + +#define PERP_PERP0_MASK 1U +#define PERP_PERP1_MASK 2U +#define PERP_PERP2_MASK 4U +#define PERP_PERP3_MASK 8U +#define PERP_PERP4_MASK 16U +#define PERP_PERP5_MASK 32U +#define PERP_PERP6_MASK 64U +#define PERP_PERP7_MASK 128U + + +/*** PPSP - Port P Polarity Select Register; 0x0000025D ***/ +typedef union { + byte Byte; + struct { + byte PPSP0 :1; /* Pull Select Port P Bit 0 */ + byte PPSP1 :1; /* Pull Select Port P Bit 1 */ + byte PPSP2 :1; /* Pull Select Port P Bit 2 */ + byte PPSP3 :1; /* Pull Select Port P Bit 3 */ + byte PPSP4 :1; /* Pull Select Port P Bit 4 */ + byte PPSP5 :1; /* Pull Select Port P Bit 5 */ + byte PPSP6 :1; /* Pull Select Port P Bit 6 */ + byte PPSP7 :1; /* Pull Select Port P Bit 7 */ + } Bits; +} PPSPSTR; +extern volatile PPSPSTR _PPSP @(REG_BASE + 0x0000025DUL); +#define PPSP _PPSP.Byte +#define PPSP_PPSP0 _PPSP.Bits.PPSP0 +#define PPSP_PPSP1 _PPSP.Bits.PPSP1 +#define PPSP_PPSP2 _PPSP.Bits.PPSP2 +#define PPSP_PPSP3 _PPSP.Bits.PPSP3 +#define PPSP_PPSP4 _PPSP.Bits.PPSP4 +#define PPSP_PPSP5 _PPSP.Bits.PPSP5 +#define PPSP_PPSP6 _PPSP.Bits.PPSP6 +#define PPSP_PPSP7 _PPSP.Bits.PPSP7 + +#define PPSP_PPSP0_MASK 1U +#define PPSP_PPSP1_MASK 2U +#define PPSP_PPSP2_MASK 4U +#define PPSP_PPSP3_MASK 8U +#define PPSP_PPSP4_MASK 16U +#define PPSP_PPSP5_MASK 32U +#define PPSP_PPSP6_MASK 64U +#define PPSP_PPSP7_MASK 128U + + +/*** PIEP - Port P Interrupt Enable Register; 0x0000025E ***/ +typedef union { + byte Byte; + struct { + byte PIEP0 :1; /* Interrupt Enable Port P Bit 0 */ + byte PIEP1 :1; /* Interrupt Enable Port P Bit 1 */ + byte PIEP2 :1; /* Interrupt Enable Port P Bit 2 */ + byte PIEP3 :1; /* Interrupt Enable Port P Bit 3 */ + byte PIEP4 :1; /* Interrupt Enable Port P Bit 4 */ + byte PIEP5 :1; /* Interrupt Enable Port P Bit 5 */ + byte PIEP6 :1; /* Interrupt Enable Port P Bit 6 */ + byte PIEP7 :1; /* Interrupt Enable Port P Bit 7 */ + } Bits; +} PIEPSTR; +extern volatile PIEPSTR _PIEP @(REG_BASE + 0x0000025EUL); +#define PIEP _PIEP.Byte +#define PIEP_PIEP0 _PIEP.Bits.PIEP0 +#define PIEP_PIEP1 _PIEP.Bits.PIEP1 +#define PIEP_PIEP2 _PIEP.Bits.PIEP2 +#define PIEP_PIEP3 _PIEP.Bits.PIEP3 +#define PIEP_PIEP4 _PIEP.Bits.PIEP4 +#define PIEP_PIEP5 _PIEP.Bits.PIEP5 +#define PIEP_PIEP6 _PIEP.Bits.PIEP6 +#define PIEP_PIEP7 _PIEP.Bits.PIEP7 + +#define PIEP_PIEP0_MASK 1U +#define PIEP_PIEP1_MASK 2U +#define PIEP_PIEP2_MASK 4U +#define PIEP_PIEP3_MASK 8U +#define PIEP_PIEP4_MASK 16U +#define PIEP_PIEP5_MASK 32U +#define PIEP_PIEP6_MASK 64U +#define PIEP_PIEP7_MASK 128U + + +/*** PIFP - Port P Interrupt Flag Register; 0x0000025F ***/ +typedef union { + byte Byte; + struct { + byte PIFP0 :1; /* Interrupt Flags Port P Bit 0 */ + byte PIFP1 :1; /* Interrupt Flags Port P Bit 1 */ + byte PIFP2 :1; /* Interrupt Flags Port P Bit 2 */ + byte PIFP3 :1; /* Interrupt Flags Port P Bit 3 */ + byte PIFP4 :1; /* Interrupt Flags Port P Bit 4 */ + byte PIFP5 :1; /* Interrupt Flags Port P Bit 5 */ + byte PIFP6 :1; /* Interrupt Flags Port P Bit 6 */ + byte PIFP7 :1; /* Interrupt Flags Port P Bit 7 */ + } Bits; +} PIFPSTR; +extern volatile PIFPSTR _PIFP @(REG_BASE + 0x0000025FUL); +#define PIFP _PIFP.Byte +#define PIFP_PIFP0 _PIFP.Bits.PIFP0 +#define PIFP_PIFP1 _PIFP.Bits.PIFP1 +#define PIFP_PIFP2 _PIFP.Bits.PIFP2 +#define PIFP_PIFP3 _PIFP.Bits.PIFP3 +#define PIFP_PIFP4 _PIFP.Bits.PIFP4 +#define PIFP_PIFP5 _PIFP.Bits.PIFP5 +#define PIFP_PIFP6 _PIFP.Bits.PIFP6 +#define PIFP_PIFP7 _PIFP.Bits.PIFP7 + +#define PIFP_PIFP0_MASK 1U +#define PIFP_PIFP1_MASK 2U +#define PIFP_PIFP2_MASK 4U +#define PIFP_PIFP3_MASK 8U +#define PIFP_PIFP4_MASK 16U +#define PIFP_PIFP5_MASK 32U +#define PIFP_PIFP6_MASK 64U +#define PIFP_PIFP7_MASK 128U + + +/*** PTH - Port H I/O Register; 0x00000260 ***/ +typedef union { + byte Byte; + struct { + byte PTH0 :1; /* Port H Bit 0 */ + byte PTH1 :1; /* Port H Bit 1 */ + byte PTH2 :1; /* Port H Bit 2 */ + byte PTH3 :1; /* Port H Bit 3 */ + byte PTH4 :1; /* Port H Bit 4 */ + byte PTH5 :1; /* Port H Bit 5 */ + byte PTH6 :1; /* Port H Bit 6 */ + byte PTH7 :1; /* Port H Bit 7 */ + } Bits; +} PTHSTR; +extern volatile PTHSTR _PTH @(REG_BASE + 0x00000260UL); +#define PTH _PTH.Byte +#define PTH_PTH0 _PTH.Bits.PTH0 +#define PTH_PTH1 _PTH.Bits.PTH1 +#define PTH_PTH2 _PTH.Bits.PTH2 +#define PTH_PTH3 _PTH.Bits.PTH3 +#define PTH_PTH4 _PTH.Bits.PTH4 +#define PTH_PTH5 _PTH.Bits.PTH5 +#define PTH_PTH6 _PTH.Bits.PTH6 +#define PTH_PTH7 _PTH.Bits.PTH7 + +#define PTH_PTH0_MASK 1U +#define PTH_PTH1_MASK 2U +#define PTH_PTH2_MASK 4U +#define PTH_PTH3_MASK 8U +#define PTH_PTH4_MASK 16U +#define PTH_PTH5_MASK 32U +#define PTH_PTH6_MASK 64U +#define PTH_PTH7_MASK 128U + + +/*** PTIH - Port H Input Register; 0x00000261 ***/ +typedef union { + byte Byte; + struct { + byte PTIH0 :1; /* Port H Bit 0 */ + byte PTIH1 :1; /* Port H Bit 1 */ + byte PTIH2 :1; /* Port H Bit 2 */ + byte PTIH3 :1; /* Port H Bit 3 */ + byte PTIH4 :1; /* Port H Bit 4 */ + byte PTIH5 :1; /* Port H Bit 5 */ + byte PTIH6 :1; /* Port H Bit 6 */ + byte PTIH7 :1; /* Port H Bit 7 */ + } Bits; +} PTIHSTR; +extern volatile PTIHSTR _PTIH @(REG_BASE + 0x00000261UL); +#define PTIH _PTIH.Byte +#define PTIH_PTIH0 _PTIH.Bits.PTIH0 +#define PTIH_PTIH1 _PTIH.Bits.PTIH1 +#define PTIH_PTIH2 _PTIH.Bits.PTIH2 +#define PTIH_PTIH3 _PTIH.Bits.PTIH3 +#define PTIH_PTIH4 _PTIH.Bits.PTIH4 +#define PTIH_PTIH5 _PTIH.Bits.PTIH5 +#define PTIH_PTIH6 _PTIH.Bits.PTIH6 +#define PTIH_PTIH7 _PTIH.Bits.PTIH7 + +#define PTIH_PTIH0_MASK 1U +#define PTIH_PTIH1_MASK 2U +#define PTIH_PTIH2_MASK 4U +#define PTIH_PTIH3_MASK 8U +#define PTIH_PTIH4_MASK 16U +#define PTIH_PTIH5_MASK 32U +#define PTIH_PTIH6_MASK 64U +#define PTIH_PTIH7_MASK 128U + + +/*** DDRH - Port H Data Direction Register; 0x00000262 ***/ +typedef union { + byte Byte; + struct { + byte DDRH0 :1; /* Data Direction Port H Bit 0 */ + byte DDRH1 :1; /* Data Direction Port H Bit 1 */ + byte DDRH2 :1; /* Data Direction Port H Bit 2 */ + byte DDRH3 :1; /* Data Direction Port H Bit 3 */ + byte DDRH4 :1; /* Data Direction Port H Bit 4 */ + byte DDRH5 :1; /* Data Direction Port H Bit 5 */ + byte DDRH6 :1; /* Data Direction Port H Bit 6 */ + byte DDRH7 :1; /* Data Direction Port H Bit 7 */ + } Bits; +} DDRHSTR; +extern volatile DDRHSTR _DDRH @(REG_BASE + 0x00000262UL); +#define DDRH _DDRH.Byte +#define DDRH_DDRH0 _DDRH.Bits.DDRH0 +#define DDRH_DDRH1 _DDRH.Bits.DDRH1 +#define DDRH_DDRH2 _DDRH.Bits.DDRH2 +#define DDRH_DDRH3 _DDRH.Bits.DDRH3 +#define DDRH_DDRH4 _DDRH.Bits.DDRH4 +#define DDRH_DDRH5 _DDRH.Bits.DDRH5 +#define DDRH_DDRH6 _DDRH.Bits.DDRH6 +#define DDRH_DDRH7 _DDRH.Bits.DDRH7 + +#define DDRH_DDRH0_MASK 1U +#define DDRH_DDRH1_MASK 2U +#define DDRH_DDRH2_MASK 4U +#define DDRH_DDRH3_MASK 8U +#define DDRH_DDRH4_MASK 16U +#define DDRH_DDRH5_MASK 32U +#define DDRH_DDRH6_MASK 64U +#define DDRH_DDRH7_MASK 128U + + +/*** RDRH - Port H Reduced Drive Register; 0x00000263 ***/ +typedef union { + byte Byte; + struct { + byte RDRH0 :1; /* Reduced Drive Port H Bit 0 */ + byte RDRH1 :1; /* Reduced Drive Port H Bit 1 */ + byte RDRH2 :1; /* Reduced Drive Port H Bit 2 */ + byte RDRH3 :1; /* Reduced Drive Port H Bit 3 */ + byte RDRH4 :1; /* Reduced Drive Port H Bit 4 */ + byte RDRH5 :1; /* Reduced Drive Port H Bit 5 */ + byte RDRH6 :1; /* Reduced Drive Port H Bit 6 */ + byte RDRH7 :1; /* Reduced Drive Port H Bit 7 */ + } Bits; +} RDRHSTR; +extern volatile RDRHSTR _RDRH @(REG_BASE + 0x00000263UL); +#define RDRH _RDRH.Byte +#define RDRH_RDRH0 _RDRH.Bits.RDRH0 +#define RDRH_RDRH1 _RDRH.Bits.RDRH1 +#define RDRH_RDRH2 _RDRH.Bits.RDRH2 +#define RDRH_RDRH3 _RDRH.Bits.RDRH3 +#define RDRH_RDRH4 _RDRH.Bits.RDRH4 +#define RDRH_RDRH5 _RDRH.Bits.RDRH5 +#define RDRH_RDRH6 _RDRH.Bits.RDRH6 +#define RDRH_RDRH7 _RDRH.Bits.RDRH7 + +#define RDRH_RDRH0_MASK 1U +#define RDRH_RDRH1_MASK 2U +#define RDRH_RDRH2_MASK 4U +#define RDRH_RDRH3_MASK 8U +#define RDRH_RDRH4_MASK 16U +#define RDRH_RDRH5_MASK 32U +#define RDRH_RDRH6_MASK 64U +#define RDRH_RDRH7_MASK 128U + + +/*** PERH - Port H Pull Device Enable Register; 0x00000264 ***/ +typedef union { + byte Byte; + struct { + byte PERH0 :1; /* Pull Device Enable Port H Bit 0 */ + byte PERH1 :1; /* Pull Device Enable Port H Bit 1 */ + byte PERH2 :1; /* Pull Device Enable Port H Bit 2 */ + byte PERH3 :1; /* Pull Device Enable Port H Bit 3 */ + byte PERH4 :1; /* Pull Device Enable Port H Bit 4 */ + byte PERH5 :1; /* Pull Device Enable Port H Bit 5 */ + byte PERH6 :1; /* Pull Device Enable Port H Bit 6 */ + byte PERH7 :1; /* Pull Device Enable Port H Bit 7 */ + } Bits; +} PERHSTR; +extern volatile PERHSTR _PERH @(REG_BASE + 0x00000264UL); +#define PERH _PERH.Byte +#define PERH_PERH0 _PERH.Bits.PERH0 +#define PERH_PERH1 _PERH.Bits.PERH1 +#define PERH_PERH2 _PERH.Bits.PERH2 +#define PERH_PERH3 _PERH.Bits.PERH3 +#define PERH_PERH4 _PERH.Bits.PERH4 +#define PERH_PERH5 _PERH.Bits.PERH5 +#define PERH_PERH6 _PERH.Bits.PERH6 +#define PERH_PERH7 _PERH.Bits.PERH7 + +#define PERH_PERH0_MASK 1U +#define PERH_PERH1_MASK 2U +#define PERH_PERH2_MASK 4U +#define PERH_PERH3_MASK 8U +#define PERH_PERH4_MASK 16U +#define PERH_PERH5_MASK 32U +#define PERH_PERH6_MASK 64U +#define PERH_PERH7_MASK 128U + + +/*** PPSH - Port H Polarity Select Register; 0x00000265 ***/ +typedef union { + byte Byte; + struct { + byte PPSH0 :1; /* Pull Select Port H Bit 0 */ + byte PPSH1 :1; /* Pull Select Port H Bit 1 */ + byte PPSH2 :1; /* Pull Select Port H Bit 2 */ + byte PPSH3 :1; /* Pull Select Port H Bit 3 */ + byte PPSH4 :1; /* Pull Select Port H Bit 4 */ + byte PPSH5 :1; /* Pull Select Port H Bit 5 */ + byte PPSH6 :1; /* Pull Select Port H Bit 6 */ + byte PPSH7 :1; /* Pull Select Port H Bit 7 */ + } Bits; +} PPSHSTR; +extern volatile PPSHSTR _PPSH @(REG_BASE + 0x00000265UL); +#define PPSH _PPSH.Byte +#define PPSH_PPSH0 _PPSH.Bits.PPSH0 +#define PPSH_PPSH1 _PPSH.Bits.PPSH1 +#define PPSH_PPSH2 _PPSH.Bits.PPSH2 +#define PPSH_PPSH3 _PPSH.Bits.PPSH3 +#define PPSH_PPSH4 _PPSH.Bits.PPSH4 +#define PPSH_PPSH5 _PPSH.Bits.PPSH5 +#define PPSH_PPSH6 _PPSH.Bits.PPSH6 +#define PPSH_PPSH7 _PPSH.Bits.PPSH7 + +#define PPSH_PPSH0_MASK 1U +#define PPSH_PPSH1_MASK 2U +#define PPSH_PPSH2_MASK 4U +#define PPSH_PPSH3_MASK 8U +#define PPSH_PPSH4_MASK 16U +#define PPSH_PPSH5_MASK 32U +#define PPSH_PPSH6_MASK 64U +#define PPSH_PPSH7_MASK 128U + + +/*** PIEH - Port H Interrupt Enable Register; 0x00000266 ***/ +typedef union { + byte Byte; + struct { + byte PIEH0 :1; /* Interrupt Enable Port H Bit 0 */ + byte PIEH1 :1; /* Interrupt Enable Port H Bit 1 */ + byte PIEH2 :1; /* Interrupt Enable Port H Bit 2 */ + byte PIEH3 :1; /* Interrupt Enable Port H Bit 3 */ + byte PIEH4 :1; /* Interrupt Enable Port H Bit 4 */ + byte PIEH5 :1; /* Interrupt Enable Port H Bit 5 */ + byte PIEH6 :1; /* Interrupt Enable Port H Bit 6 */ + byte PIEH7 :1; /* Interrupt Enable Port H Bit 7 */ + } Bits; +} PIEHSTR; +extern volatile PIEHSTR _PIEH @(REG_BASE + 0x00000266UL); +#define PIEH _PIEH.Byte +#define PIEH_PIEH0 _PIEH.Bits.PIEH0 +#define PIEH_PIEH1 _PIEH.Bits.PIEH1 +#define PIEH_PIEH2 _PIEH.Bits.PIEH2 +#define PIEH_PIEH3 _PIEH.Bits.PIEH3 +#define PIEH_PIEH4 _PIEH.Bits.PIEH4 +#define PIEH_PIEH5 _PIEH.Bits.PIEH5 +#define PIEH_PIEH6 _PIEH.Bits.PIEH6 +#define PIEH_PIEH7 _PIEH.Bits.PIEH7 + +#define PIEH_PIEH0_MASK 1U +#define PIEH_PIEH1_MASK 2U +#define PIEH_PIEH2_MASK 4U +#define PIEH_PIEH3_MASK 8U +#define PIEH_PIEH4_MASK 16U +#define PIEH_PIEH5_MASK 32U +#define PIEH_PIEH6_MASK 64U +#define PIEH_PIEH7_MASK 128U + + +/*** PIFH - Port H Interrupt Flag Register; 0x00000267 ***/ +typedef union { + byte Byte; + struct { + byte PIFH0 :1; /* Interrupt Flags Port H Bit 0 */ + byte PIFH1 :1; /* Interrupt Flags Port H Bit 1 */ + byte PIFH2 :1; /* Interrupt Flags Port H Bit 2 */ + byte PIFH3 :1; /* Interrupt Flags Port H Bit 3 */ + byte PIFH4 :1; /* Interrupt Flags Port H Bit 4 */ + byte PIFH5 :1; /* Interrupt Flags Port H Bit 5 */ + byte PIFH6 :1; /* Interrupt Flags Port H Bit 6 */ + byte PIFH7 :1; /* Interrupt Flags Port H Bit 7 */ + } Bits; +} PIFHSTR; +extern volatile PIFHSTR _PIFH @(REG_BASE + 0x00000267UL); +#define PIFH _PIFH.Byte +#define PIFH_PIFH0 _PIFH.Bits.PIFH0 +#define PIFH_PIFH1 _PIFH.Bits.PIFH1 +#define PIFH_PIFH2 _PIFH.Bits.PIFH2 +#define PIFH_PIFH3 _PIFH.Bits.PIFH3 +#define PIFH_PIFH4 _PIFH.Bits.PIFH4 +#define PIFH_PIFH5 _PIFH.Bits.PIFH5 +#define PIFH_PIFH6 _PIFH.Bits.PIFH6 +#define PIFH_PIFH7 _PIFH.Bits.PIFH7 + +#define PIFH_PIFH0_MASK 1U +#define PIFH_PIFH1_MASK 2U +#define PIFH_PIFH2_MASK 4U +#define PIFH_PIFH3_MASK 8U +#define PIFH_PIFH4_MASK 16U +#define PIFH_PIFH5_MASK 32U +#define PIFH_PIFH6_MASK 64U +#define PIFH_PIFH7_MASK 128U + + +/*** PTJ - Port J I/O Register; 0x00000268 ***/ +typedef union { + byte Byte; + struct { + byte PTJ0 :1; /* Port J Bit 0 */ + byte PTJ1 :1; /* Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PTJ6 :1; /* Port J Bit 6 */ + byte PTJ7 :1; /* Port J Bit 7 */ + } Bits; + struct { + byte grpPTJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPTJ_6 :2; + } MergedBits; +} PTJSTR; +extern volatile PTJSTR _PTJ @(REG_BASE + 0x00000268UL); +#define PTJ _PTJ.Byte +#define PTJ_PTJ0 _PTJ.Bits.PTJ0 +#define PTJ_PTJ1 _PTJ.Bits.PTJ1 +#define PTJ_PTJ6 _PTJ.Bits.PTJ6 +#define PTJ_PTJ7 _PTJ.Bits.PTJ7 +#define PTJ_PTJ _PTJ.MergedBits.grpPTJ +#define PTJ_PTJ_6 _PTJ.MergedBits.grpPTJ_6 + +#define PTJ_PTJ0_MASK 1U +#define PTJ_PTJ1_MASK 2U +#define PTJ_PTJ6_MASK 64U +#define PTJ_PTJ7_MASK 128U +#define PTJ_PTJ_MASK 3U +#define PTJ_PTJ_BITNUM 0U +#define PTJ_PTJ_6_MASK 192U +#define PTJ_PTJ_6_BITNUM 6U + + +/*** PTIJ - Port J Input Register; 0x00000269 ***/ +typedef union { + byte Byte; + struct { + byte PTIJ0 :1; /* Port J Bit 0 */ + byte PTIJ1 :1; /* Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PTIJ6 :1; /* Port J Bit 6 */ + byte PTIJ7 :1; /* Port J Bit 7 */ + } Bits; + struct { + byte grpPTIJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPTIJ_6 :2; + } MergedBits; +} PTIJSTR; +extern volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000269UL); +#define PTIJ _PTIJ.Byte +#define PTIJ_PTIJ0 _PTIJ.Bits.PTIJ0 +#define PTIJ_PTIJ1 _PTIJ.Bits.PTIJ1 +#define PTIJ_PTIJ6 _PTIJ.Bits.PTIJ6 +#define PTIJ_PTIJ7 _PTIJ.Bits.PTIJ7 +#define PTIJ_PTIJ _PTIJ.MergedBits.grpPTIJ +#define PTIJ_PTIJ_6 _PTIJ.MergedBits.grpPTIJ_6 + +#define PTIJ_PTIJ0_MASK 1U +#define PTIJ_PTIJ1_MASK 2U +#define PTIJ_PTIJ6_MASK 64U +#define PTIJ_PTIJ7_MASK 128U +#define PTIJ_PTIJ_MASK 3U +#define PTIJ_PTIJ_BITNUM 0U +#define PTIJ_PTIJ_6_MASK 192U +#define PTIJ_PTIJ_6_BITNUM 6U + + +/*** DDRJ - Port J Data Direction Register; 0x0000026A ***/ +typedef union { + byte Byte; + struct { + byte DDRJ0 :1; /* Data Direction Port J Bit 0 */ + byte DDRJ1 :1; /* Data Direction Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte DDRJ6 :1; /* Data Direction Port J Bit 6 */ + byte DDRJ7 :1; /* Data Direction Port J Bit 7 */ + } Bits; + struct { + byte grpDDRJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpDDRJ_6 :2; + } MergedBits; +} DDRJSTR; +extern volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000026AUL); +#define DDRJ _DDRJ.Byte +#define DDRJ_DDRJ0 _DDRJ.Bits.DDRJ0 +#define DDRJ_DDRJ1 _DDRJ.Bits.DDRJ1 +#define DDRJ_DDRJ6 _DDRJ.Bits.DDRJ6 +#define DDRJ_DDRJ7 _DDRJ.Bits.DDRJ7 +#define DDRJ_DDRJ _DDRJ.MergedBits.grpDDRJ +#define DDRJ_DDRJ_6 _DDRJ.MergedBits.grpDDRJ_6 + +#define DDRJ_DDRJ0_MASK 1U +#define DDRJ_DDRJ1_MASK 2U +#define DDRJ_DDRJ6_MASK 64U +#define DDRJ_DDRJ7_MASK 128U +#define DDRJ_DDRJ_MASK 3U +#define DDRJ_DDRJ_BITNUM 0U +#define DDRJ_DDRJ_6_MASK 192U +#define DDRJ_DDRJ_6_BITNUM 6U + + +/*** RDRJ - Port J Reduced Drive Register; 0x0000026B ***/ +typedef union { + byte Byte; + struct { + byte RDRJ0 :1; /* Reduced Drive Port J Bit 0 */ + byte RDRJ1 :1; /* Reduced Drive Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte RDRJ6 :1; /* Reduced Drive Port J Bit 6 */ + byte RDRJ7 :1; /* Reduced Drive Port J Bit 7 */ + } Bits; + struct { + byte grpRDRJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpRDRJ_6 :2; + } MergedBits; +} RDRJSTR; +extern volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000026BUL); +#define RDRJ _RDRJ.Byte +#define RDRJ_RDRJ0 _RDRJ.Bits.RDRJ0 +#define RDRJ_RDRJ1 _RDRJ.Bits.RDRJ1 +#define RDRJ_RDRJ6 _RDRJ.Bits.RDRJ6 +#define RDRJ_RDRJ7 _RDRJ.Bits.RDRJ7 +#define RDRJ_RDRJ _RDRJ.MergedBits.grpRDRJ +#define RDRJ_RDRJ_6 _RDRJ.MergedBits.grpRDRJ_6 + +#define RDRJ_RDRJ0_MASK 1U +#define RDRJ_RDRJ1_MASK 2U +#define RDRJ_RDRJ6_MASK 64U +#define RDRJ_RDRJ7_MASK 128U +#define RDRJ_RDRJ_MASK 3U +#define RDRJ_RDRJ_BITNUM 0U +#define RDRJ_RDRJ_6_MASK 192U +#define RDRJ_RDRJ_6_BITNUM 6U + + +/*** PERJ - Port J Pull Device Enable Register; 0x0000026C ***/ +typedef union { + byte Byte; + struct { + byte PERJ0 :1; /* Pull Device Enable Port J Bit 0 */ + byte PERJ1 :1; /* Pull Device Enable Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PERJ6 :1; /* Pull Device Enable Port J Bit 6 */ + byte PERJ7 :1; /* Pull Device Enable Port J Bit 7 */ + } Bits; + struct { + byte grpPERJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPERJ_6 :2; + } MergedBits; +} PERJSTR; +extern volatile PERJSTR _PERJ @(REG_BASE + 0x0000026CUL); +#define PERJ _PERJ.Byte +#define PERJ_PERJ0 _PERJ.Bits.PERJ0 +#define PERJ_PERJ1 _PERJ.Bits.PERJ1 +#define PERJ_PERJ6 _PERJ.Bits.PERJ6 +#define PERJ_PERJ7 _PERJ.Bits.PERJ7 +#define PERJ_PERJ _PERJ.MergedBits.grpPERJ +#define PERJ_PERJ_6 _PERJ.MergedBits.grpPERJ_6 + +#define PERJ_PERJ0_MASK 1U +#define PERJ_PERJ1_MASK 2U +#define PERJ_PERJ6_MASK 64U +#define PERJ_PERJ7_MASK 128U +#define PERJ_PERJ_MASK 3U +#define PERJ_PERJ_BITNUM 0U +#define PERJ_PERJ_6_MASK 192U +#define PERJ_PERJ_6_BITNUM 6U + + +/*** PPSJ - Port J Polarity Select Register; 0x0000026D ***/ +typedef union { + byte Byte; + struct { + byte PPSJ0 :1; /* Pull Select Port J Bit 0 */ + byte PPSJ1 :1; /* Pull Select Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PPSJ6 :1; /* Pull Select Port J Bit 6 */ + byte PPSJ7 :1; /* Pull Select Port J Bit 7 */ + } Bits; + struct { + byte grpPPSJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPPSJ_6 :2; + } MergedBits; +} PPSJSTR; +extern volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000026DUL); +#define PPSJ _PPSJ.Byte +#define PPSJ_PPSJ0 _PPSJ.Bits.PPSJ0 +#define PPSJ_PPSJ1 _PPSJ.Bits.PPSJ1 +#define PPSJ_PPSJ6 _PPSJ.Bits.PPSJ6 +#define PPSJ_PPSJ7 _PPSJ.Bits.PPSJ7 +#define PPSJ_PPSJ _PPSJ.MergedBits.grpPPSJ +#define PPSJ_PPSJ_6 _PPSJ.MergedBits.grpPPSJ_6 + +#define PPSJ_PPSJ0_MASK 1U +#define PPSJ_PPSJ1_MASK 2U +#define PPSJ_PPSJ6_MASK 64U +#define PPSJ_PPSJ7_MASK 128U +#define PPSJ_PPSJ_MASK 3U +#define PPSJ_PPSJ_BITNUM 0U +#define PPSJ_PPSJ_6_MASK 192U +#define PPSJ_PPSJ_6_BITNUM 6U + + +/*** PIEJ - Port J Interrupt Enable Register; 0x0000026E ***/ +typedef union { + byte Byte; + struct { + byte PIEJ0 :1; /* Interrupt Enable Port J Bit 0 */ + byte PIEJ1 :1; /* Interrupt Enable Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PIEJ6 :1; /* Interrupt Enable Port J Bit 6 */ + byte PIEJ7 :1; /* Interrupt Enable Port J Bit 7 */ + } Bits; + struct { + byte grpPIEJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPIEJ_6 :2; + } MergedBits; +} PIEJSTR; +extern volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000026EUL); +#define PIEJ _PIEJ.Byte +#define PIEJ_PIEJ0 _PIEJ.Bits.PIEJ0 +#define PIEJ_PIEJ1 _PIEJ.Bits.PIEJ1 +#define PIEJ_PIEJ6 _PIEJ.Bits.PIEJ6 +#define PIEJ_PIEJ7 _PIEJ.Bits.PIEJ7 +#define PIEJ_PIEJ _PIEJ.MergedBits.grpPIEJ +#define PIEJ_PIEJ_6 _PIEJ.MergedBits.grpPIEJ_6 + +#define PIEJ_PIEJ0_MASK 1U +#define PIEJ_PIEJ1_MASK 2U +#define PIEJ_PIEJ6_MASK 64U +#define PIEJ_PIEJ7_MASK 128U +#define PIEJ_PIEJ_MASK 3U +#define PIEJ_PIEJ_BITNUM 0U +#define PIEJ_PIEJ_6_MASK 192U +#define PIEJ_PIEJ_6_BITNUM 6U + + +/*** PIFJ - Port J Interrupt Flag Register; 0x0000026F ***/ +typedef union { + byte Byte; + struct { + byte PIFJ0 :1; /* Interrupt Flags Port J Bit 0 */ + byte PIFJ1 :1; /* Interrupt Flags Port J Bit 1 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte PIFJ6 :1; /* Interrupt Flags Port J Bit 6 */ + byte PIFJ7 :1; /* Interrupt Flags Port J Bit 7 */ + } Bits; + struct { + byte grpPIFJ :2; + byte :1; + byte :1; + byte :1; + byte :1; + byte grpPIFJ_6 :2; + } MergedBits; +} PIFJSTR; +extern volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000026FUL); +#define PIFJ _PIFJ.Byte +#define PIFJ_PIFJ0 _PIFJ.Bits.PIFJ0 +#define PIFJ_PIFJ1 _PIFJ.Bits.PIFJ1 +#define PIFJ_PIFJ6 _PIFJ.Bits.PIFJ6 +#define PIFJ_PIFJ7 _PIFJ.Bits.PIFJ7 +#define PIFJ_PIFJ _PIFJ.MergedBits.grpPIFJ +#define PIFJ_PIFJ_6 _PIFJ.MergedBits.grpPIFJ_6 + +#define PIFJ_PIFJ0_MASK 1U +#define PIFJ_PIFJ1_MASK 2U +#define PIFJ_PIFJ6_MASK 64U +#define PIFJ_PIFJ7_MASK 128U +#define PIFJ_PIFJ_MASK 3U +#define PIFJ_PIFJ_BITNUM 0U +#define PIFJ_PIFJ_6_MASK 192U +#define PIFJ_PIFJ_6_BITNUM 6U + + +/*** CAN4CTL0 - MSCAN4 Control 0 Register; 0x00000280 ***/ +typedef union { + byte Byte; + struct { + byte INITRQ :1; /* Initialization Mode Request */ + byte SLPRQ :1; /* Sleep Mode Request */ + byte WUPE :1; /* Wake-Up Enable */ + byte TIME :1; /* Timer Enable */ + byte SYNCH :1; /* Synchronized Status */ + byte CSWAI :1; /* CAN Stops in Wait Mode */ + byte RXACT :1; /* Receiver Active Status */ + byte RXFRM :1; /* Received Frame Flag */ + } Bits; +} CAN4CTL0STR; +extern volatile CAN4CTL0STR _CAN4CTL0 @(REG_BASE + 0x00000280UL); +#define CAN4CTL0 _CAN4CTL0.Byte +#define CAN4CTL0_INITRQ _CAN4CTL0.Bits.INITRQ +#define CAN4CTL0_SLPRQ _CAN4CTL0.Bits.SLPRQ +#define CAN4CTL0_WUPE _CAN4CTL0.Bits.WUPE +#define CAN4CTL0_TIME _CAN4CTL0.Bits.TIME +#define CAN4CTL0_SYNCH _CAN4CTL0.Bits.SYNCH +#define CAN4CTL0_CSWAI _CAN4CTL0.Bits.CSWAI +#define CAN4CTL0_RXACT _CAN4CTL0.Bits.RXACT +#define CAN4CTL0_RXFRM _CAN4CTL0.Bits.RXFRM +/* CAN4CTL_ARR: Access 2 CAN4CTLx registers in an array */ +#define CAN4CTL_ARR ((volatile byte *) &CAN4CTL0) + +#define CAN4CTL0_INITRQ_MASK 1U +#define CAN4CTL0_SLPRQ_MASK 2U +#define CAN4CTL0_WUPE_MASK 4U +#define CAN4CTL0_TIME_MASK 8U +#define CAN4CTL0_SYNCH_MASK 16U +#define CAN4CTL0_CSWAI_MASK 32U +#define CAN4CTL0_RXACT_MASK 64U +#define CAN4CTL0_RXFRM_MASK 128U + + +/*** CAN4CTL1 - MSCAN4 Control 1 Register; 0x00000281 ***/ +typedef union { + byte Byte; + struct { + byte INITAK :1; /* Initialization Mode Acknowledge */ + byte SLPAK :1; /* Sleep Mode Acknowledge */ + byte WUPM :1; /* Wake-Up Mode */ + byte :1; + byte LISTEN :1; /* Listen Only Mode */ + byte LOOPB :1; /* Loop Back Self Test Mode */ + byte CLKSRC :1; /* MSCAN4 Clock Source */ + byte CANE :1; /* MSCAN4 Enable */ + } Bits; +} CAN4CTL1STR; +extern volatile CAN4CTL1STR _CAN4CTL1 @(REG_BASE + 0x00000281UL); +#define CAN4CTL1 _CAN4CTL1.Byte +#define CAN4CTL1_INITAK _CAN4CTL1.Bits.INITAK +#define CAN4CTL1_SLPAK _CAN4CTL1.Bits.SLPAK +#define CAN4CTL1_WUPM _CAN4CTL1.Bits.WUPM +#define CAN4CTL1_LISTEN _CAN4CTL1.Bits.LISTEN +#define CAN4CTL1_LOOPB _CAN4CTL1.Bits.LOOPB +#define CAN4CTL1_CLKSRC _CAN4CTL1.Bits.CLKSRC +#define CAN4CTL1_CANE _CAN4CTL1.Bits.CANE + +#define CAN4CTL1_INITAK_MASK 1U +#define CAN4CTL1_SLPAK_MASK 2U +#define CAN4CTL1_WUPM_MASK 4U +#define CAN4CTL1_LISTEN_MASK 16U +#define CAN4CTL1_LOOPB_MASK 32U +#define CAN4CTL1_CLKSRC_MASK 64U +#define CAN4CTL1_CANE_MASK 128U + + +/*** CAN4BTR0 - MSCAN4 Bus Timing Register 0; 0x00000282 ***/ +typedef union { + byte Byte; + struct { + byte BRP0 :1; /* Baud Rate Prescaler 0 */ + byte BRP1 :1; /* Baud Rate Prescaler 1 */ + byte BRP2 :1; /* Baud Rate Prescaler 2 */ + byte BRP3 :1; /* Baud Rate Prescaler 3 */ + byte BRP4 :1; /* Baud Rate Prescaler 4 */ + byte BRP5 :1; /* Baud Rate Prescaler 5 */ + byte SJW0 :1; /* Synchronization Jump Width 0 */ + byte SJW1 :1; /* Synchronization Jump Width 1 */ + } Bits; + struct { + byte grpBRP :6; + byte grpSJW :2; + } MergedBits; +} CAN4BTR0STR; +extern volatile CAN4BTR0STR _CAN4BTR0 @(REG_BASE + 0x00000282UL); +#define CAN4BTR0 _CAN4BTR0.Byte +#define CAN4BTR0_BRP0 _CAN4BTR0.Bits.BRP0 +#define CAN4BTR0_BRP1 _CAN4BTR0.Bits.BRP1 +#define CAN4BTR0_BRP2 _CAN4BTR0.Bits.BRP2 +#define CAN4BTR0_BRP3 _CAN4BTR0.Bits.BRP3 +#define CAN4BTR0_BRP4 _CAN4BTR0.Bits.BRP4 +#define CAN4BTR0_BRP5 _CAN4BTR0.Bits.BRP5 +#define CAN4BTR0_SJW0 _CAN4BTR0.Bits.SJW0 +#define CAN4BTR0_SJW1 _CAN4BTR0.Bits.SJW1 +/* CAN4BTR_ARR: Access 2 CAN4BTRx registers in an array */ +#define CAN4BTR_ARR ((volatile byte *) &CAN4BTR0) +#define CAN4BTR0_BRP _CAN4BTR0.MergedBits.grpBRP +#define CAN4BTR0_SJW _CAN4BTR0.MergedBits.grpSJW + +#define CAN4BTR0_BRP0_MASK 1U +#define CAN4BTR0_BRP1_MASK 2U +#define CAN4BTR0_BRP2_MASK 4U +#define CAN4BTR0_BRP3_MASK 8U +#define CAN4BTR0_BRP4_MASK 16U +#define CAN4BTR0_BRP5_MASK 32U +#define CAN4BTR0_SJW0_MASK 64U +#define CAN4BTR0_SJW1_MASK 128U +#define CAN4BTR0_BRP_MASK 63U +#define CAN4BTR0_BRP_BITNUM 0U +#define CAN4BTR0_SJW_MASK 192U +#define CAN4BTR0_SJW_BITNUM 6U + + +/*** CAN4BTR1 - MSCAN4 Bus Timing Register 1; 0x00000283 ***/ +typedef union { + byte Byte; + struct { + byte TSEG10 :1; /* Time Segment 10 */ + byte TSEG11 :1; /* Time Segment 11 */ + byte TSEG12 :1; /* Time Segment 12 */ + byte TSEG13 :1; /* Time Segment 13 */ + byte TSEG20 :1; /* Time Segment 20 */ + byte TSEG21 :1; /* Time Segment 21 */ + byte TSEG22 :1; /* Time Segment 22 */ + byte SAMP :1; /* Sampling */ + } Bits; + struct { + byte grpTSEG_10 :4; + byte grpTSEG_20 :3; + byte :1; + } MergedBits; +} CAN4BTR1STR; +extern volatile CAN4BTR1STR _CAN4BTR1 @(REG_BASE + 0x00000283UL); +#define CAN4BTR1 _CAN4BTR1.Byte +#define CAN4BTR1_TSEG10 _CAN4BTR1.Bits.TSEG10 +#define CAN4BTR1_TSEG11 _CAN4BTR1.Bits.TSEG11 +#define CAN4BTR1_TSEG12 _CAN4BTR1.Bits.TSEG12 +#define CAN4BTR1_TSEG13 _CAN4BTR1.Bits.TSEG13 +#define CAN4BTR1_TSEG20 _CAN4BTR1.Bits.TSEG20 +#define CAN4BTR1_TSEG21 _CAN4BTR1.Bits.TSEG21 +#define CAN4BTR1_TSEG22 _CAN4BTR1.Bits.TSEG22 +#define CAN4BTR1_SAMP _CAN4BTR1.Bits.SAMP +#define CAN4BTR1_TSEG_10 _CAN4BTR1.MergedBits.grpTSEG_10 +#define CAN4BTR1_TSEG_20 _CAN4BTR1.MergedBits.grpTSEG_20 +#define CAN4BTR1_TSEG CAN4BTR1_TSEG_10 + +#define CAN4BTR1_TSEG10_MASK 1U +#define CAN4BTR1_TSEG11_MASK 2U +#define CAN4BTR1_TSEG12_MASK 4U +#define CAN4BTR1_TSEG13_MASK 8U +#define CAN4BTR1_TSEG20_MASK 16U +#define CAN4BTR1_TSEG21_MASK 32U +#define CAN4BTR1_TSEG22_MASK 64U +#define CAN4BTR1_SAMP_MASK 128U +#define CAN4BTR1_TSEG_10_MASK 15U +#define CAN4BTR1_TSEG_10_BITNUM 0U +#define CAN4BTR1_TSEG_20_MASK 112U +#define CAN4BTR1_TSEG_20_BITNUM 4U + + +/*** CAN4RFLG - MSCAN4 Receiver Flag Register; 0x00000284 ***/ +typedef union { + byte Byte; + struct { + byte RXF :1; /* Receive Buffer Full */ + byte OVRIF :1; /* Overrun Interrupt Flag */ + byte TSTAT0 :1; /* Transmitter Status Bit 0 */ + byte TSTAT1 :1; /* Transmitter Status Bit 1 */ + byte RSTAT0 :1; /* Receiver Status Bit 0 */ + byte RSTAT1 :1; /* Receiver Status Bit 1 */ + byte CSCIF :1; /* CAN Status Change Interrupt Flag */ + byte WUPIF :1; /* Wake-up Interrupt Flag */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTAT :2; + byte grpRSTAT :2; + byte :1; + byte :1; + } MergedBits; +} CAN4RFLGSTR; +extern volatile CAN4RFLGSTR _CAN4RFLG @(REG_BASE + 0x00000284UL); +#define CAN4RFLG _CAN4RFLG.Byte +#define CAN4RFLG_RXF _CAN4RFLG.Bits.RXF +#define CAN4RFLG_OVRIF _CAN4RFLG.Bits.OVRIF +#define CAN4RFLG_TSTAT0 _CAN4RFLG.Bits.TSTAT0 +#define CAN4RFLG_TSTAT1 _CAN4RFLG.Bits.TSTAT1 +#define CAN4RFLG_RSTAT0 _CAN4RFLG.Bits.RSTAT0 +#define CAN4RFLG_RSTAT1 _CAN4RFLG.Bits.RSTAT1 +#define CAN4RFLG_CSCIF _CAN4RFLG.Bits.CSCIF +#define CAN4RFLG_WUPIF _CAN4RFLG.Bits.WUPIF +#define CAN4RFLG_TSTAT _CAN4RFLG.MergedBits.grpTSTAT +#define CAN4RFLG_RSTAT _CAN4RFLG.MergedBits.grpRSTAT + +#define CAN4RFLG_RXF_MASK 1U +#define CAN4RFLG_OVRIF_MASK 2U +#define CAN4RFLG_TSTAT0_MASK 4U +#define CAN4RFLG_TSTAT1_MASK 8U +#define CAN4RFLG_RSTAT0_MASK 16U +#define CAN4RFLG_RSTAT1_MASK 32U +#define CAN4RFLG_CSCIF_MASK 64U +#define CAN4RFLG_WUPIF_MASK 128U +#define CAN4RFLG_TSTAT_MASK 12U +#define CAN4RFLG_TSTAT_BITNUM 2U +#define CAN4RFLG_RSTAT_MASK 48U +#define CAN4RFLG_RSTAT_BITNUM 4U + + +/*** CAN4RIER - MSCAN4 Receiver Interrupt Enable Register; 0x00000285 ***/ +typedef union { + byte Byte; + struct { + byte RXFIE :1; /* Receiver Full Interrupt Enable */ + byte OVRIE :1; /* Overrun Interrupt Enable */ + byte TSTATE0 :1; /* Transmitter Status Change Enable 0 */ + byte TSTATE1 :1; /* Transmitter Status Change Enable 1 */ + byte RSTATE0 :1; /* Receiver Status Change Enable 0 */ + byte RSTATE1 :1; /* Receiver Status Change Enable 1 */ + byte CSCIE :1; /* CAN Status Change Interrupt Enable */ + byte WUPIE :1; /* Wake-up Interrupt Enable */ + } Bits; + struct { + byte :1; + byte :1; + byte grpTSTATE :2; + byte grpRSTATE :2; + byte :1; + byte :1; + } MergedBits; +} CAN4RIERSTR; +extern volatile CAN4RIERSTR _CAN4RIER @(REG_BASE + 0x00000285UL); +#define CAN4RIER _CAN4RIER.Byte +#define CAN4RIER_RXFIE _CAN4RIER.Bits.RXFIE +#define CAN4RIER_OVRIE _CAN4RIER.Bits.OVRIE +#define CAN4RIER_TSTATE0 _CAN4RIER.Bits.TSTATE0 +#define CAN4RIER_TSTATE1 _CAN4RIER.Bits.TSTATE1 +#define CAN4RIER_RSTATE0 _CAN4RIER.Bits.RSTATE0 +#define CAN4RIER_RSTATE1 _CAN4RIER.Bits.RSTATE1 +#define CAN4RIER_CSCIE _CAN4RIER.Bits.CSCIE +#define CAN4RIER_WUPIE _CAN4RIER.Bits.WUPIE +#define CAN4RIER_TSTATE _CAN4RIER.MergedBits.grpTSTATE +#define CAN4RIER_RSTATE _CAN4RIER.MergedBits.grpRSTATE + +#define CAN4RIER_RXFIE_MASK 1U +#define CAN4RIER_OVRIE_MASK 2U +#define CAN4RIER_TSTATE0_MASK 4U +#define CAN4RIER_TSTATE1_MASK 8U +#define CAN4RIER_RSTATE0_MASK 16U +#define CAN4RIER_RSTATE1_MASK 32U +#define CAN4RIER_CSCIE_MASK 64U +#define CAN4RIER_WUPIE_MASK 128U +#define CAN4RIER_TSTATE_MASK 12U +#define CAN4RIER_TSTATE_BITNUM 2U +#define CAN4RIER_RSTATE_MASK 48U +#define CAN4RIER_RSTATE_BITNUM 4U + + +/*** CAN4TFLG - MSCAN4 Transmitter Flag Register; 0x00000286 ***/ +typedef union { + byte Byte; + struct { + byte TXE0 :1; /* Transmitter Buffer Empty 0 */ + byte TXE1 :1; /* Transmitter Buffer Empty 1 */ + byte TXE2 :1; /* Transmitter Buffer Empty 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TFLGSTR; +extern volatile CAN4TFLGSTR _CAN4TFLG @(REG_BASE + 0x00000286UL); +#define CAN4TFLG _CAN4TFLG.Byte +#define CAN4TFLG_TXE0 _CAN4TFLG.Bits.TXE0 +#define CAN4TFLG_TXE1 _CAN4TFLG.Bits.TXE1 +#define CAN4TFLG_TXE2 _CAN4TFLG.Bits.TXE2 +#define CAN4TFLG_TXE _CAN4TFLG.MergedBits.grpTXE + +#define CAN4TFLG_TXE0_MASK 1U +#define CAN4TFLG_TXE1_MASK 2U +#define CAN4TFLG_TXE2_MASK 4U +#define CAN4TFLG_TXE_MASK 7U +#define CAN4TFLG_TXE_BITNUM 0U + + +/*** CAN4TIER - MSCAN4 Transmitter Interrupt Enable Register; 0x00000287 ***/ +typedef union { + byte Byte; + struct { + byte TXEIE0 :1; /* Transmitter Empty Interrupt Enable 0 */ + byte TXEIE1 :1; /* Transmitter Empty Interrupt Enable 1 */ + byte TXEIE2 :1; /* Transmitter Empty Interrupt Enable 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTXEIE :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TIERSTR; +extern volatile CAN4TIERSTR _CAN4TIER @(REG_BASE + 0x00000287UL); +#define CAN4TIER _CAN4TIER.Byte +#define CAN4TIER_TXEIE0 _CAN4TIER.Bits.TXEIE0 +#define CAN4TIER_TXEIE1 _CAN4TIER.Bits.TXEIE1 +#define CAN4TIER_TXEIE2 _CAN4TIER.Bits.TXEIE2 +#define CAN4TIER_TXEIE _CAN4TIER.MergedBits.grpTXEIE + +#define CAN4TIER_TXEIE0_MASK 1U +#define CAN4TIER_TXEIE1_MASK 2U +#define CAN4TIER_TXEIE2_MASK 4U +#define CAN4TIER_TXEIE_MASK 7U +#define CAN4TIER_TXEIE_BITNUM 0U + + +/*** CAN4TARQ - MSCAN 4 Transmitter Message Abort Request; 0x00000288 ***/ +typedef union { + byte Byte; + struct { + byte ABTRQ0 :1; /* Abort Request 0 */ + byte ABTRQ1 :1; /* Abort Request 1 */ + byte ABTRQ2 :1; /* Abort Request 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTRQ :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TARQSTR; +extern volatile CAN4TARQSTR _CAN4TARQ @(REG_BASE + 0x00000288UL); +#define CAN4TARQ _CAN4TARQ.Byte +#define CAN4TARQ_ABTRQ0 _CAN4TARQ.Bits.ABTRQ0 +#define CAN4TARQ_ABTRQ1 _CAN4TARQ.Bits.ABTRQ1 +#define CAN4TARQ_ABTRQ2 _CAN4TARQ.Bits.ABTRQ2 +#define CAN4TARQ_ABTRQ _CAN4TARQ.MergedBits.grpABTRQ + +#define CAN4TARQ_ABTRQ0_MASK 1U +#define CAN4TARQ_ABTRQ1_MASK 2U +#define CAN4TARQ_ABTRQ2_MASK 4U +#define CAN4TARQ_ABTRQ_MASK 7U +#define CAN4TARQ_ABTRQ_BITNUM 0U + + +/*** CAN4TAAK - MSCAN4 Transmitter Message Abort Control; 0x00000289 ***/ +typedef union { + byte Byte; + struct { + byte ABTAK0 :1; /* Abort Acknowledge 0 */ + byte ABTAK1 :1; /* Abort Acknowledge 1 */ + byte ABTAK2 :1; /* Abort Acknowledge 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpABTAK :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TAAKSTR; +extern volatile CAN4TAAKSTR _CAN4TAAK @(REG_BASE + 0x00000289UL); +#define CAN4TAAK _CAN4TAAK.Byte +#define CAN4TAAK_ABTAK0 _CAN4TAAK.Bits.ABTAK0 +#define CAN4TAAK_ABTAK1 _CAN4TAAK.Bits.ABTAK1 +#define CAN4TAAK_ABTAK2 _CAN4TAAK.Bits.ABTAK2 +#define CAN4TAAK_ABTAK _CAN4TAAK.MergedBits.grpABTAK + +#define CAN4TAAK_ABTAK0_MASK 1U +#define CAN4TAAK_ABTAK1_MASK 2U +#define CAN4TAAK_ABTAK2_MASK 4U +#define CAN4TAAK_ABTAK_MASK 7U +#define CAN4TAAK_ABTAK_BITNUM 0U + + +/*** CAN4TBSEL - MSCAN4 Transmit Buffer Selection; 0x0000028A ***/ +typedef union { + byte Byte; + struct { + byte TX0 :1; /* Transmit Buffer Select 0 */ + byte TX1 :1; /* Transmit Buffer Select 1 */ + byte TX2 :1; /* Transmit Buffer Select 2 */ + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpTX :3; + byte :1; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TBSELSTR; +extern volatile CAN4TBSELSTR _CAN4TBSEL @(REG_BASE + 0x0000028AUL); +#define CAN4TBSEL _CAN4TBSEL.Byte +#define CAN4TBSEL_TX0 _CAN4TBSEL.Bits.TX0 +#define CAN4TBSEL_TX1 _CAN4TBSEL.Bits.TX1 +#define CAN4TBSEL_TX2 _CAN4TBSEL.Bits.TX2 +#define CAN4TBSEL_TX _CAN4TBSEL.MergedBits.grpTX + +#define CAN4TBSEL_TX0_MASK 1U +#define CAN4TBSEL_TX1_MASK 2U +#define CAN4TBSEL_TX2_MASK 4U +#define CAN4TBSEL_TX_MASK 7U +#define CAN4TBSEL_TX_BITNUM 0U + + +/*** CAN4IDAC - MSCAN4 Identifier Acceptance Control Register; 0x0000028B ***/ +typedef union { + byte Byte; + struct { + byte IDHIT0 :1; /* Identifier Acceptance Hit Indicator 0 */ + byte IDHIT1 :1; /* Identifier Acceptance Hit Indicator 1 */ + byte IDHIT2 :1; /* Identifier Acceptance Hit Indicator 2 */ + byte :1; + byte IDAM0 :1; /* Identifier Acceptance Mode 0 */ + byte IDAM1 :1; /* Identifier Acceptance Mode 1 */ + byte :1; + byte :1; + } Bits; + struct { + byte grpIDHIT :3; + byte :1; + byte grpIDAM :2; + byte :1; + byte :1; + } MergedBits; +} CAN4IDACSTR; +extern volatile CAN4IDACSTR _CAN4IDAC @(REG_BASE + 0x0000028BUL); +#define CAN4IDAC _CAN4IDAC.Byte +#define CAN4IDAC_IDHIT0 _CAN4IDAC.Bits.IDHIT0 +#define CAN4IDAC_IDHIT1 _CAN4IDAC.Bits.IDHIT1 +#define CAN4IDAC_IDHIT2 _CAN4IDAC.Bits.IDHIT2 +#define CAN4IDAC_IDAM0 _CAN4IDAC.Bits.IDAM0 +#define CAN4IDAC_IDAM1 _CAN4IDAC.Bits.IDAM1 +#define CAN4IDAC_IDHIT _CAN4IDAC.MergedBits.grpIDHIT +#define CAN4IDAC_IDAM _CAN4IDAC.MergedBits.grpIDAM + +#define CAN4IDAC_IDHIT0_MASK 1U +#define CAN4IDAC_IDHIT1_MASK 2U +#define CAN4IDAC_IDHIT2_MASK 4U +#define CAN4IDAC_IDAM0_MASK 16U +#define CAN4IDAC_IDAM1_MASK 32U +#define CAN4IDAC_IDHIT_MASK 7U +#define CAN4IDAC_IDHIT_BITNUM 0U +#define CAN4IDAC_IDAM_MASK 48U +#define CAN4IDAC_IDAM_BITNUM 4U + + +/*** CAN4RXERR - MSCAN4 Receive Error Counter Register; 0x0000028E ***/ +typedef union { + byte Byte; + struct { + byte RXERR0 :1; /* Bit 0 */ + byte RXERR1 :1; /* Bit 1 */ + byte RXERR2 :1; /* Bit 2 */ + byte RXERR3 :1; /* Bit 3 */ + byte RXERR4 :1; /* Bit 4 */ + byte RXERR5 :1; /* Bit 5 */ + byte RXERR6 :1; /* Bit 6 */ + byte RXERR7 :1; /* Bit 7 */ + } Bits; +} CAN4RXERRSTR; +extern volatile CAN4RXERRSTR _CAN4RXERR @(REG_BASE + 0x0000028EUL); +#define CAN4RXERR _CAN4RXERR.Byte +#define CAN4RXERR_RXERR0 _CAN4RXERR.Bits.RXERR0 +#define CAN4RXERR_RXERR1 _CAN4RXERR.Bits.RXERR1 +#define CAN4RXERR_RXERR2 _CAN4RXERR.Bits.RXERR2 +#define CAN4RXERR_RXERR3 _CAN4RXERR.Bits.RXERR3 +#define CAN4RXERR_RXERR4 _CAN4RXERR.Bits.RXERR4 +#define CAN4RXERR_RXERR5 _CAN4RXERR.Bits.RXERR5 +#define CAN4RXERR_RXERR6 _CAN4RXERR.Bits.RXERR6 +#define CAN4RXERR_RXERR7 _CAN4RXERR.Bits.RXERR7 + +#define CAN4RXERR_RXERR0_MASK 1U +#define CAN4RXERR_RXERR1_MASK 2U +#define CAN4RXERR_RXERR2_MASK 4U +#define CAN4RXERR_RXERR3_MASK 8U +#define CAN4RXERR_RXERR4_MASK 16U +#define CAN4RXERR_RXERR5_MASK 32U +#define CAN4RXERR_RXERR6_MASK 64U +#define CAN4RXERR_RXERR7_MASK 128U + + +/*** CAN4TXERR - MSCAN4 Transmit Error Counter Register; 0x0000028F ***/ +typedef union { + byte Byte; + struct { + byte TXERR0 :1; /* Bit 0 */ + byte TXERR1 :1; /* Bit 1 */ + byte TXERR2 :1; /* Bit 2 */ + byte TXERR3 :1; /* Bit 3 */ + byte TXERR4 :1; /* Bit 4 */ + byte TXERR5 :1; /* Bit 5 */ + byte TXERR6 :1; /* Bit 6 */ + byte TXERR7 :1; /* Bit 7 */ + } Bits; +} CAN4TXERRSTR; +extern volatile CAN4TXERRSTR _CAN4TXERR @(REG_BASE + 0x0000028FUL); +#define CAN4TXERR _CAN4TXERR.Byte +#define CAN4TXERR_TXERR0 _CAN4TXERR.Bits.TXERR0 +#define CAN4TXERR_TXERR1 _CAN4TXERR.Bits.TXERR1 +#define CAN4TXERR_TXERR2 _CAN4TXERR.Bits.TXERR2 +#define CAN4TXERR_TXERR3 _CAN4TXERR.Bits.TXERR3 +#define CAN4TXERR_TXERR4 _CAN4TXERR.Bits.TXERR4 +#define CAN4TXERR_TXERR5 _CAN4TXERR.Bits.TXERR5 +#define CAN4TXERR_TXERR6 _CAN4TXERR.Bits.TXERR6 +#define CAN4TXERR_TXERR7 _CAN4TXERR.Bits.TXERR7 + +#define CAN4TXERR_TXERR0_MASK 1U +#define CAN4TXERR_TXERR1_MASK 2U +#define CAN4TXERR_TXERR2_MASK 4U +#define CAN4TXERR_TXERR3_MASK 8U +#define CAN4TXERR_TXERR4_MASK 16U +#define CAN4TXERR_TXERR5_MASK 32U +#define CAN4TXERR_TXERR6_MASK 64U +#define CAN4TXERR_TXERR7_MASK 128U + + +/*** CAN4IDAR0 - MSCAN4 Identifier Acceptance Register 0; 0x00000290 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR0STR; +extern volatile CAN4IDAR0STR _CAN4IDAR0 @(REG_BASE + 0x00000290UL); +#define CAN4IDAR0 _CAN4IDAR0.Byte +#define CAN4IDAR0_AC0 _CAN4IDAR0.Bits.AC0 +#define CAN4IDAR0_AC1 _CAN4IDAR0.Bits.AC1 +#define CAN4IDAR0_AC2 _CAN4IDAR0.Bits.AC2 +#define CAN4IDAR0_AC3 _CAN4IDAR0.Bits.AC3 +#define CAN4IDAR0_AC4 _CAN4IDAR0.Bits.AC4 +#define CAN4IDAR0_AC5 _CAN4IDAR0.Bits.AC5 +#define CAN4IDAR0_AC6 _CAN4IDAR0.Bits.AC6 +#define CAN4IDAR0_AC7 _CAN4IDAR0.Bits.AC7 +/* CAN4IDAR_ARR: Access 4 CAN4IDARx registers in an array */ +#define CAN4IDAR_ARR ((volatile byte *) &CAN4IDAR0) + +#define CAN4IDAR0_AC0_MASK 1U +#define CAN4IDAR0_AC1_MASK 2U +#define CAN4IDAR0_AC2_MASK 4U +#define CAN4IDAR0_AC3_MASK 8U +#define CAN4IDAR0_AC4_MASK 16U +#define CAN4IDAR0_AC5_MASK 32U +#define CAN4IDAR0_AC6_MASK 64U +#define CAN4IDAR0_AC7_MASK 128U + + +/*** CAN4IDAR1 - MSCAN4 Identifier Acceptance Register 1; 0x00000291 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR1STR; +extern volatile CAN4IDAR1STR _CAN4IDAR1 @(REG_BASE + 0x00000291UL); +#define CAN4IDAR1 _CAN4IDAR1.Byte +#define CAN4IDAR1_AC0 _CAN4IDAR1.Bits.AC0 +#define CAN4IDAR1_AC1 _CAN4IDAR1.Bits.AC1 +#define CAN4IDAR1_AC2 _CAN4IDAR1.Bits.AC2 +#define CAN4IDAR1_AC3 _CAN4IDAR1.Bits.AC3 +#define CAN4IDAR1_AC4 _CAN4IDAR1.Bits.AC4 +#define CAN4IDAR1_AC5 _CAN4IDAR1.Bits.AC5 +#define CAN4IDAR1_AC6 _CAN4IDAR1.Bits.AC6 +#define CAN4IDAR1_AC7 _CAN4IDAR1.Bits.AC7 + +#define CAN4IDAR1_AC0_MASK 1U +#define CAN4IDAR1_AC1_MASK 2U +#define CAN4IDAR1_AC2_MASK 4U +#define CAN4IDAR1_AC3_MASK 8U +#define CAN4IDAR1_AC4_MASK 16U +#define CAN4IDAR1_AC5_MASK 32U +#define CAN4IDAR1_AC6_MASK 64U +#define CAN4IDAR1_AC7_MASK 128U + + +/*** CAN4IDAR2 - MSCAN4 Identifier Acceptance Register 2; 0x00000292 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR2STR; +extern volatile CAN4IDAR2STR _CAN4IDAR2 @(REG_BASE + 0x00000292UL); +#define CAN4IDAR2 _CAN4IDAR2.Byte +#define CAN4IDAR2_AC0 _CAN4IDAR2.Bits.AC0 +#define CAN4IDAR2_AC1 _CAN4IDAR2.Bits.AC1 +#define CAN4IDAR2_AC2 _CAN4IDAR2.Bits.AC2 +#define CAN4IDAR2_AC3 _CAN4IDAR2.Bits.AC3 +#define CAN4IDAR2_AC4 _CAN4IDAR2.Bits.AC4 +#define CAN4IDAR2_AC5 _CAN4IDAR2.Bits.AC5 +#define CAN4IDAR2_AC6 _CAN4IDAR2.Bits.AC6 +#define CAN4IDAR2_AC7 _CAN4IDAR2.Bits.AC7 + +#define CAN4IDAR2_AC0_MASK 1U +#define CAN4IDAR2_AC1_MASK 2U +#define CAN4IDAR2_AC2_MASK 4U +#define CAN4IDAR2_AC3_MASK 8U +#define CAN4IDAR2_AC4_MASK 16U +#define CAN4IDAR2_AC5_MASK 32U +#define CAN4IDAR2_AC6_MASK 64U +#define CAN4IDAR2_AC7_MASK 128U + + +/*** CAN4IDAR3 - MSCAN4 Identifier Acceptance Register 3; 0x00000293 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR3STR; +extern volatile CAN4IDAR3STR _CAN4IDAR3 @(REG_BASE + 0x00000293UL); +#define CAN4IDAR3 _CAN4IDAR3.Byte +#define CAN4IDAR3_AC0 _CAN4IDAR3.Bits.AC0 +#define CAN4IDAR3_AC1 _CAN4IDAR3.Bits.AC1 +#define CAN4IDAR3_AC2 _CAN4IDAR3.Bits.AC2 +#define CAN4IDAR3_AC3 _CAN4IDAR3.Bits.AC3 +#define CAN4IDAR3_AC4 _CAN4IDAR3.Bits.AC4 +#define CAN4IDAR3_AC5 _CAN4IDAR3.Bits.AC5 +#define CAN4IDAR3_AC6 _CAN4IDAR3.Bits.AC6 +#define CAN4IDAR3_AC7 _CAN4IDAR3.Bits.AC7 + +#define CAN4IDAR3_AC0_MASK 1U +#define CAN4IDAR3_AC1_MASK 2U +#define CAN4IDAR3_AC2_MASK 4U +#define CAN4IDAR3_AC3_MASK 8U +#define CAN4IDAR3_AC4_MASK 16U +#define CAN4IDAR3_AC5_MASK 32U +#define CAN4IDAR3_AC6_MASK 64U +#define CAN4IDAR3_AC7_MASK 128U + + +/*** CAN4IDMR0 - MSCAN4 Identifier Mask Register 0; 0x00000294 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR0STR; +extern volatile CAN4IDMR0STR _CAN4IDMR0 @(REG_BASE + 0x00000294UL); +#define CAN4IDMR0 _CAN4IDMR0.Byte +#define CAN4IDMR0_AM0 _CAN4IDMR0.Bits.AM0 +#define CAN4IDMR0_AM1 _CAN4IDMR0.Bits.AM1 +#define CAN4IDMR0_AM2 _CAN4IDMR0.Bits.AM2 +#define CAN4IDMR0_AM3 _CAN4IDMR0.Bits.AM3 +#define CAN4IDMR0_AM4 _CAN4IDMR0.Bits.AM4 +#define CAN4IDMR0_AM5 _CAN4IDMR0.Bits.AM5 +#define CAN4IDMR0_AM6 _CAN4IDMR0.Bits.AM6 +#define CAN4IDMR0_AM7 _CAN4IDMR0.Bits.AM7 +/* CAN4IDMR_ARR: Access 4 CAN4IDMRx registers in an array */ +#define CAN4IDMR_ARR ((volatile byte *) &CAN4IDMR0) + +#define CAN4IDMR0_AM0_MASK 1U +#define CAN4IDMR0_AM1_MASK 2U +#define CAN4IDMR0_AM2_MASK 4U +#define CAN4IDMR0_AM3_MASK 8U +#define CAN4IDMR0_AM4_MASK 16U +#define CAN4IDMR0_AM5_MASK 32U +#define CAN4IDMR0_AM6_MASK 64U +#define CAN4IDMR0_AM7_MASK 128U + + +/*** CAN4IDMR1 - MSCAN4 Identifier Mask Register 1; 0x00000295 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR1STR; +extern volatile CAN4IDMR1STR _CAN4IDMR1 @(REG_BASE + 0x00000295UL); +#define CAN4IDMR1 _CAN4IDMR1.Byte +#define CAN4IDMR1_AM0 _CAN4IDMR1.Bits.AM0 +#define CAN4IDMR1_AM1 _CAN4IDMR1.Bits.AM1 +#define CAN4IDMR1_AM2 _CAN4IDMR1.Bits.AM2 +#define CAN4IDMR1_AM3 _CAN4IDMR1.Bits.AM3 +#define CAN4IDMR1_AM4 _CAN4IDMR1.Bits.AM4 +#define CAN4IDMR1_AM5 _CAN4IDMR1.Bits.AM5 +#define CAN4IDMR1_AM6 _CAN4IDMR1.Bits.AM6 +#define CAN4IDMR1_AM7 _CAN4IDMR1.Bits.AM7 + +#define CAN4IDMR1_AM0_MASK 1U +#define CAN4IDMR1_AM1_MASK 2U +#define CAN4IDMR1_AM2_MASK 4U +#define CAN4IDMR1_AM3_MASK 8U +#define CAN4IDMR1_AM4_MASK 16U +#define CAN4IDMR1_AM5_MASK 32U +#define CAN4IDMR1_AM6_MASK 64U +#define CAN4IDMR1_AM7_MASK 128U + + +/*** CAN4IDMR2 - MSCAN4 Identifier Mask Register 2; 0x00000296 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR2STR; +extern volatile CAN4IDMR2STR _CAN4IDMR2 @(REG_BASE + 0x00000296UL); +#define CAN4IDMR2 _CAN4IDMR2.Byte +#define CAN4IDMR2_AM0 _CAN4IDMR2.Bits.AM0 +#define CAN4IDMR2_AM1 _CAN4IDMR2.Bits.AM1 +#define CAN4IDMR2_AM2 _CAN4IDMR2.Bits.AM2 +#define CAN4IDMR2_AM3 _CAN4IDMR2.Bits.AM3 +#define CAN4IDMR2_AM4 _CAN4IDMR2.Bits.AM4 +#define CAN4IDMR2_AM5 _CAN4IDMR2.Bits.AM5 +#define CAN4IDMR2_AM6 _CAN4IDMR2.Bits.AM6 +#define CAN4IDMR2_AM7 _CAN4IDMR2.Bits.AM7 + +#define CAN4IDMR2_AM0_MASK 1U +#define CAN4IDMR2_AM1_MASK 2U +#define CAN4IDMR2_AM2_MASK 4U +#define CAN4IDMR2_AM3_MASK 8U +#define CAN4IDMR2_AM4_MASK 16U +#define CAN4IDMR2_AM5_MASK 32U +#define CAN4IDMR2_AM6_MASK 64U +#define CAN4IDMR2_AM7_MASK 128U + + +/*** CAN4IDMR3 - MSCAN4 Identifier Mask Register 3; 0x00000297 ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR3STR; +extern volatile CAN4IDMR3STR _CAN4IDMR3 @(REG_BASE + 0x00000297UL); +#define CAN4IDMR3 _CAN4IDMR3.Byte +#define CAN4IDMR3_AM0 _CAN4IDMR3.Bits.AM0 +#define CAN4IDMR3_AM1 _CAN4IDMR3.Bits.AM1 +#define CAN4IDMR3_AM2 _CAN4IDMR3.Bits.AM2 +#define CAN4IDMR3_AM3 _CAN4IDMR3.Bits.AM3 +#define CAN4IDMR3_AM4 _CAN4IDMR3.Bits.AM4 +#define CAN4IDMR3_AM5 _CAN4IDMR3.Bits.AM5 +#define CAN4IDMR3_AM6 _CAN4IDMR3.Bits.AM6 +#define CAN4IDMR3_AM7 _CAN4IDMR3.Bits.AM7 + +#define CAN4IDMR3_AM0_MASK 1U +#define CAN4IDMR3_AM1_MASK 2U +#define CAN4IDMR3_AM2_MASK 4U +#define CAN4IDMR3_AM3_MASK 8U +#define CAN4IDMR3_AM4_MASK 16U +#define CAN4IDMR3_AM5_MASK 32U +#define CAN4IDMR3_AM6_MASK 64U +#define CAN4IDMR3_AM7_MASK 128U + + +/*** CAN4IDAR4 - MSCAN4 Identifier Acceptance Register 4; 0x00000298 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR4STR; +extern volatile CAN4IDAR4STR _CAN4IDAR4 @(REG_BASE + 0x00000298UL); +#define CAN4IDAR4 _CAN4IDAR4.Byte +#define CAN4IDAR4_AC0 _CAN4IDAR4.Bits.AC0 +#define CAN4IDAR4_AC1 _CAN4IDAR4.Bits.AC1 +#define CAN4IDAR4_AC2 _CAN4IDAR4.Bits.AC2 +#define CAN4IDAR4_AC3 _CAN4IDAR4.Bits.AC3 +#define CAN4IDAR4_AC4 _CAN4IDAR4.Bits.AC4 +#define CAN4IDAR4_AC5 _CAN4IDAR4.Bits.AC5 +#define CAN4IDAR4_AC6 _CAN4IDAR4.Bits.AC6 +#define CAN4IDAR4_AC7 _CAN4IDAR4.Bits.AC7 + +#define CAN4IDAR4_AC0_MASK 1U +#define CAN4IDAR4_AC1_MASK 2U +#define CAN4IDAR4_AC2_MASK 4U +#define CAN4IDAR4_AC3_MASK 8U +#define CAN4IDAR4_AC4_MASK 16U +#define CAN4IDAR4_AC5_MASK 32U +#define CAN4IDAR4_AC6_MASK 64U +#define CAN4IDAR4_AC7_MASK 128U + + +/*** CAN4IDAR5 - MSCAN4 Identifier Acceptance Register 5; 0x00000299 ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR5STR; +extern volatile CAN4IDAR5STR _CAN4IDAR5 @(REG_BASE + 0x00000299UL); +#define CAN4IDAR5 _CAN4IDAR5.Byte +#define CAN4IDAR5_AC0 _CAN4IDAR5.Bits.AC0 +#define CAN4IDAR5_AC1 _CAN4IDAR5.Bits.AC1 +#define CAN4IDAR5_AC2 _CAN4IDAR5.Bits.AC2 +#define CAN4IDAR5_AC3 _CAN4IDAR5.Bits.AC3 +#define CAN4IDAR5_AC4 _CAN4IDAR5.Bits.AC4 +#define CAN4IDAR5_AC5 _CAN4IDAR5.Bits.AC5 +#define CAN4IDAR5_AC6 _CAN4IDAR5.Bits.AC6 +#define CAN4IDAR5_AC7 _CAN4IDAR5.Bits.AC7 + +#define CAN4IDAR5_AC0_MASK 1U +#define CAN4IDAR5_AC1_MASK 2U +#define CAN4IDAR5_AC2_MASK 4U +#define CAN4IDAR5_AC3_MASK 8U +#define CAN4IDAR5_AC4_MASK 16U +#define CAN4IDAR5_AC5_MASK 32U +#define CAN4IDAR5_AC6_MASK 64U +#define CAN4IDAR5_AC7_MASK 128U + + +/*** CAN4IDAR6 - MSCAN4 Identifier Acceptance Register 6; 0x0000029A ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR6STR; +extern volatile CAN4IDAR6STR _CAN4IDAR6 @(REG_BASE + 0x0000029AUL); +#define CAN4IDAR6 _CAN4IDAR6.Byte +#define CAN4IDAR6_AC0 _CAN4IDAR6.Bits.AC0 +#define CAN4IDAR6_AC1 _CAN4IDAR6.Bits.AC1 +#define CAN4IDAR6_AC2 _CAN4IDAR6.Bits.AC2 +#define CAN4IDAR6_AC3 _CAN4IDAR6.Bits.AC3 +#define CAN4IDAR6_AC4 _CAN4IDAR6.Bits.AC4 +#define CAN4IDAR6_AC5 _CAN4IDAR6.Bits.AC5 +#define CAN4IDAR6_AC6 _CAN4IDAR6.Bits.AC6 +#define CAN4IDAR6_AC7 _CAN4IDAR6.Bits.AC7 + +#define CAN4IDAR6_AC0_MASK 1U +#define CAN4IDAR6_AC1_MASK 2U +#define CAN4IDAR6_AC2_MASK 4U +#define CAN4IDAR6_AC3_MASK 8U +#define CAN4IDAR6_AC4_MASK 16U +#define CAN4IDAR6_AC5_MASK 32U +#define CAN4IDAR6_AC6_MASK 64U +#define CAN4IDAR6_AC7_MASK 128U + + +/*** CAN4IDAR7 - MSCAN4 Identifier Acceptance Register 7; 0x0000029B ***/ +typedef union { + byte Byte; + struct { + byte AC0 :1; /* Acceptance Code Bit 0 */ + byte AC1 :1; /* Acceptance Code Bit 1 */ + byte AC2 :1; /* Acceptance Code Bit 2 */ + byte AC3 :1; /* Acceptance Code Bit 3 */ + byte AC4 :1; /* Acceptance Code Bit 4 */ + byte AC5 :1; /* Acceptance Code Bit 5 */ + byte AC6 :1; /* Acceptance Code Bit 6 */ + byte AC7 :1; /* Acceptance Code Bit 7 */ + } Bits; +} CAN4IDAR7STR; +extern volatile CAN4IDAR7STR _CAN4IDAR7 @(REG_BASE + 0x0000029BUL); +#define CAN4IDAR7 _CAN4IDAR7.Byte +#define CAN4IDAR7_AC0 _CAN4IDAR7.Bits.AC0 +#define CAN4IDAR7_AC1 _CAN4IDAR7.Bits.AC1 +#define CAN4IDAR7_AC2 _CAN4IDAR7.Bits.AC2 +#define CAN4IDAR7_AC3 _CAN4IDAR7.Bits.AC3 +#define CAN4IDAR7_AC4 _CAN4IDAR7.Bits.AC4 +#define CAN4IDAR7_AC5 _CAN4IDAR7.Bits.AC5 +#define CAN4IDAR7_AC6 _CAN4IDAR7.Bits.AC6 +#define CAN4IDAR7_AC7 _CAN4IDAR7.Bits.AC7 + +#define CAN4IDAR7_AC0_MASK 1U +#define CAN4IDAR7_AC1_MASK 2U +#define CAN4IDAR7_AC2_MASK 4U +#define CAN4IDAR7_AC3_MASK 8U +#define CAN4IDAR7_AC4_MASK 16U +#define CAN4IDAR7_AC5_MASK 32U +#define CAN4IDAR7_AC6_MASK 64U +#define CAN4IDAR7_AC7_MASK 128U + + +/*** CAN4IDMR4 - MSCAN4 Identifier Mask Register 4; 0x0000029C ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR4STR; +extern volatile CAN4IDMR4STR _CAN4IDMR4 @(REG_BASE + 0x0000029CUL); +#define CAN4IDMR4 _CAN4IDMR4.Byte +#define CAN4IDMR4_AM0 _CAN4IDMR4.Bits.AM0 +#define CAN4IDMR4_AM1 _CAN4IDMR4.Bits.AM1 +#define CAN4IDMR4_AM2 _CAN4IDMR4.Bits.AM2 +#define CAN4IDMR4_AM3 _CAN4IDMR4.Bits.AM3 +#define CAN4IDMR4_AM4 _CAN4IDMR4.Bits.AM4 +#define CAN4IDMR4_AM5 _CAN4IDMR4.Bits.AM5 +#define CAN4IDMR4_AM6 _CAN4IDMR4.Bits.AM6 +#define CAN4IDMR4_AM7 _CAN4IDMR4.Bits.AM7 + +#define CAN4IDMR4_AM0_MASK 1U +#define CAN4IDMR4_AM1_MASK 2U +#define CAN4IDMR4_AM2_MASK 4U +#define CAN4IDMR4_AM3_MASK 8U +#define CAN4IDMR4_AM4_MASK 16U +#define CAN4IDMR4_AM5_MASK 32U +#define CAN4IDMR4_AM6_MASK 64U +#define CAN4IDMR4_AM7_MASK 128U + + +/*** CAN4IDMR5 - MSCAN4 Identifier Mask Register 5; 0x0000029D ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR5STR; +extern volatile CAN4IDMR5STR _CAN4IDMR5 @(REG_BASE + 0x0000029DUL); +#define CAN4IDMR5 _CAN4IDMR5.Byte +#define CAN4IDMR5_AM0 _CAN4IDMR5.Bits.AM0 +#define CAN4IDMR5_AM1 _CAN4IDMR5.Bits.AM1 +#define CAN4IDMR5_AM2 _CAN4IDMR5.Bits.AM2 +#define CAN4IDMR5_AM3 _CAN4IDMR5.Bits.AM3 +#define CAN4IDMR5_AM4 _CAN4IDMR5.Bits.AM4 +#define CAN4IDMR5_AM5 _CAN4IDMR5.Bits.AM5 +#define CAN4IDMR5_AM6 _CAN4IDMR5.Bits.AM6 +#define CAN4IDMR5_AM7 _CAN4IDMR5.Bits.AM7 + +#define CAN4IDMR5_AM0_MASK 1U +#define CAN4IDMR5_AM1_MASK 2U +#define CAN4IDMR5_AM2_MASK 4U +#define CAN4IDMR5_AM3_MASK 8U +#define CAN4IDMR5_AM4_MASK 16U +#define CAN4IDMR5_AM5_MASK 32U +#define CAN4IDMR5_AM6_MASK 64U +#define CAN4IDMR5_AM7_MASK 128U + + +/*** CAN4IDMR6 - MSCAN4 Identifier Mask Register 6; 0x0000029E ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR6STR; +extern volatile CAN4IDMR6STR _CAN4IDMR6 @(REG_BASE + 0x0000029EUL); +#define CAN4IDMR6 _CAN4IDMR6.Byte +#define CAN4IDMR6_AM0 _CAN4IDMR6.Bits.AM0 +#define CAN4IDMR6_AM1 _CAN4IDMR6.Bits.AM1 +#define CAN4IDMR6_AM2 _CAN4IDMR6.Bits.AM2 +#define CAN4IDMR6_AM3 _CAN4IDMR6.Bits.AM3 +#define CAN4IDMR6_AM4 _CAN4IDMR6.Bits.AM4 +#define CAN4IDMR6_AM5 _CAN4IDMR6.Bits.AM5 +#define CAN4IDMR6_AM6 _CAN4IDMR6.Bits.AM6 +#define CAN4IDMR6_AM7 _CAN4IDMR6.Bits.AM7 + +#define CAN4IDMR6_AM0_MASK 1U +#define CAN4IDMR6_AM1_MASK 2U +#define CAN4IDMR6_AM2_MASK 4U +#define CAN4IDMR6_AM3_MASK 8U +#define CAN4IDMR6_AM4_MASK 16U +#define CAN4IDMR6_AM5_MASK 32U +#define CAN4IDMR6_AM6_MASK 64U +#define CAN4IDMR6_AM7_MASK 128U + + +/*** CAN4IDMR7 - MSCAN4 Identifier Mask Register 7; 0x0000029F ***/ +typedef union { + byte Byte; + struct { + byte AM0 :1; /* Acceptance Mask Bit 0 */ + byte AM1 :1; /* Acceptance Mask Bit 1 */ + byte AM2 :1; /* Acceptance Mask Bit 2 */ + byte AM3 :1; /* Acceptance Mask Bit 3 */ + byte AM4 :1; /* Acceptance Mask Bit 4 */ + byte AM5 :1; /* Acceptance Mask Bit 5 */ + byte AM6 :1; /* Acceptance Mask Bit 6 */ + byte AM7 :1; /* Acceptance Mask Bit 7 */ + } Bits; +} CAN4IDMR7STR; +extern volatile CAN4IDMR7STR _CAN4IDMR7 @(REG_BASE + 0x0000029FUL); +#define CAN4IDMR7 _CAN4IDMR7.Byte +#define CAN4IDMR7_AM0 _CAN4IDMR7.Bits.AM0 +#define CAN4IDMR7_AM1 _CAN4IDMR7.Bits.AM1 +#define CAN4IDMR7_AM2 _CAN4IDMR7.Bits.AM2 +#define CAN4IDMR7_AM3 _CAN4IDMR7.Bits.AM3 +#define CAN4IDMR7_AM4 _CAN4IDMR7.Bits.AM4 +#define CAN4IDMR7_AM5 _CAN4IDMR7.Bits.AM5 +#define CAN4IDMR7_AM6 _CAN4IDMR7.Bits.AM6 +#define CAN4IDMR7_AM7 _CAN4IDMR7.Bits.AM7 + +#define CAN4IDMR7_AM0_MASK 1U +#define CAN4IDMR7_AM1_MASK 2U +#define CAN4IDMR7_AM2_MASK 4U +#define CAN4IDMR7_AM3_MASK 8U +#define CAN4IDMR7_AM4_MASK 16U +#define CAN4IDMR7_AM5_MASK 32U +#define CAN4IDMR7_AM6_MASK 64U +#define CAN4IDMR7_AM7_MASK 128U + + +/*** CAN4RXIDR0 - MSCAN4 Receive Identifier Register 0; 0x000002A0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; +} CAN4RXIDR0STR; +extern volatile CAN4RXIDR0STR _CAN4RXIDR0 @(REG_BASE + 0x000002A0UL); +#define CAN4RXIDR0 _CAN4RXIDR0.Byte +#define CAN4RXIDR0_ID21 _CAN4RXIDR0.Bits.ID21 +#define CAN4RXIDR0_ID22 _CAN4RXIDR0.Bits.ID22 +#define CAN4RXIDR0_ID23 _CAN4RXIDR0.Bits.ID23 +#define CAN4RXIDR0_ID24 _CAN4RXIDR0.Bits.ID24 +#define CAN4RXIDR0_ID25 _CAN4RXIDR0.Bits.ID25 +#define CAN4RXIDR0_ID26 _CAN4RXIDR0.Bits.ID26 +#define CAN4RXIDR0_ID27 _CAN4RXIDR0.Bits.ID27 +#define CAN4RXIDR0_ID28 _CAN4RXIDR0.Bits.ID28 +/* CAN4RXIDR_ARR: Access 4 CAN4RXIDRx registers in an array */ +#define CAN4RXIDR_ARR ((volatile byte *) &CAN4RXIDR0) + +#define CAN4RXIDR0_ID21_MASK 1U +#define CAN4RXIDR0_ID22_MASK 2U +#define CAN4RXIDR0_ID23_MASK 4U +#define CAN4RXIDR0_ID24_MASK 8U +#define CAN4RXIDR0_ID25_MASK 16U +#define CAN4RXIDR0_ID26_MASK 32U +#define CAN4RXIDR0_ID27_MASK 64U +#define CAN4RXIDR0_ID28_MASK 128U + + +/*** CAN4RXIDR1 - MSCAN4 Receive Identifier Register 1; 0x000002A1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN4RXIDR1STR; +extern volatile CAN4RXIDR1STR _CAN4RXIDR1 @(REG_BASE + 0x000002A1UL); +#define CAN4RXIDR1 _CAN4RXIDR1.Byte +#define CAN4RXIDR1_ID15 _CAN4RXIDR1.Bits.ID15 +#define CAN4RXIDR1_ID16 _CAN4RXIDR1.Bits.ID16 +#define CAN4RXIDR1_ID17 _CAN4RXIDR1.Bits.ID17 +#define CAN4RXIDR1_IDE _CAN4RXIDR1.Bits.IDE +#define CAN4RXIDR1_SRR _CAN4RXIDR1.Bits.SRR +#define CAN4RXIDR1_ID18 _CAN4RXIDR1.Bits.ID18 +#define CAN4RXIDR1_ID19 _CAN4RXIDR1.Bits.ID19 +#define CAN4RXIDR1_ID20 _CAN4RXIDR1.Bits.ID20 +#define CAN4RXIDR1_ID_15 _CAN4RXIDR1.MergedBits.grpID_15 +#define CAN4RXIDR1_ID_18 _CAN4RXIDR1.MergedBits.grpID_18 +#define CAN4RXIDR1_ID CAN4RXIDR1_ID_15 + +#define CAN4RXIDR1_ID15_MASK 1U +#define CAN4RXIDR1_ID16_MASK 2U +#define CAN4RXIDR1_ID17_MASK 4U +#define CAN4RXIDR1_IDE_MASK 8U +#define CAN4RXIDR1_SRR_MASK 16U +#define CAN4RXIDR1_ID18_MASK 32U +#define CAN4RXIDR1_ID19_MASK 64U +#define CAN4RXIDR1_ID20_MASK 128U +#define CAN4RXIDR1_ID_15_MASK 7U +#define CAN4RXIDR1_ID_15_BITNUM 0U +#define CAN4RXIDR1_ID_18_MASK 224U +#define CAN4RXIDR1_ID_18_BITNUM 5U + + +/*** CAN4RXIDR2 - MSCAN4 Receive Identifier Register 2; 0x000002A2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; +} CAN4RXIDR2STR; +extern volatile CAN4RXIDR2STR _CAN4RXIDR2 @(REG_BASE + 0x000002A2UL); +#define CAN4RXIDR2 _CAN4RXIDR2.Byte +#define CAN4RXIDR2_ID7 _CAN4RXIDR2.Bits.ID7 +#define CAN4RXIDR2_ID8 _CAN4RXIDR2.Bits.ID8 +#define CAN4RXIDR2_ID9 _CAN4RXIDR2.Bits.ID9 +#define CAN4RXIDR2_ID10 _CAN4RXIDR2.Bits.ID10 +#define CAN4RXIDR2_ID11 _CAN4RXIDR2.Bits.ID11 +#define CAN4RXIDR2_ID12 _CAN4RXIDR2.Bits.ID12 +#define CAN4RXIDR2_ID13 _CAN4RXIDR2.Bits.ID13 +#define CAN4RXIDR2_ID14 _CAN4RXIDR2.Bits.ID14 + +#define CAN4RXIDR2_ID7_MASK 1U +#define CAN4RXIDR2_ID8_MASK 2U +#define CAN4RXIDR2_ID9_MASK 4U +#define CAN4RXIDR2_ID10_MASK 8U +#define CAN4RXIDR2_ID11_MASK 16U +#define CAN4RXIDR2_ID12_MASK 32U +#define CAN4RXIDR2_ID13_MASK 64U +#define CAN4RXIDR2_ID14_MASK 128U + + +/*** CAN4RXIDR3 - MSCAN4 Receive Identifier Register 3; 0x000002A3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN4RXIDR3STR; +extern volatile CAN4RXIDR3STR _CAN4RXIDR3 @(REG_BASE + 0x000002A3UL); +#define CAN4RXIDR3 _CAN4RXIDR3.Byte +#define CAN4RXIDR3_RTR _CAN4RXIDR3.Bits.RTR +#define CAN4RXIDR3_ID0 _CAN4RXIDR3.Bits.ID0 +#define CAN4RXIDR3_ID1 _CAN4RXIDR3.Bits.ID1 +#define CAN4RXIDR3_ID2 _CAN4RXIDR3.Bits.ID2 +#define CAN4RXIDR3_ID3 _CAN4RXIDR3.Bits.ID3 +#define CAN4RXIDR3_ID4 _CAN4RXIDR3.Bits.ID4 +#define CAN4RXIDR3_ID5 _CAN4RXIDR3.Bits.ID5 +#define CAN4RXIDR3_ID6 _CAN4RXIDR3.Bits.ID6 +#define CAN4RXIDR3_ID _CAN4RXIDR3.MergedBits.grpID + +#define CAN4RXIDR3_RTR_MASK 1U +#define CAN4RXIDR3_ID0_MASK 2U +#define CAN4RXIDR3_ID1_MASK 4U +#define CAN4RXIDR3_ID2_MASK 8U +#define CAN4RXIDR3_ID3_MASK 16U +#define CAN4RXIDR3_ID4_MASK 32U +#define CAN4RXIDR3_ID5_MASK 64U +#define CAN4RXIDR3_ID6_MASK 128U +#define CAN4RXIDR3_ID_MASK 254U +#define CAN4RXIDR3_ID_BITNUM 1U + + +/*** CAN4RXDSR0 - MSCAN4 Receive Data Segment Register 0; 0x000002A4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR0STR; +extern volatile CAN4RXDSR0STR _CAN4RXDSR0 @(REG_BASE + 0x000002A4UL); +#define CAN4RXDSR0 _CAN4RXDSR0.Byte +#define CAN4RXDSR0_DB0 _CAN4RXDSR0.Bits.DB0 +#define CAN4RXDSR0_DB1 _CAN4RXDSR0.Bits.DB1 +#define CAN4RXDSR0_DB2 _CAN4RXDSR0.Bits.DB2 +#define CAN4RXDSR0_DB3 _CAN4RXDSR0.Bits.DB3 +#define CAN4RXDSR0_DB4 _CAN4RXDSR0.Bits.DB4 +#define CAN4RXDSR0_DB5 _CAN4RXDSR0.Bits.DB5 +#define CAN4RXDSR0_DB6 _CAN4RXDSR0.Bits.DB6 +#define CAN4RXDSR0_DB7 _CAN4RXDSR0.Bits.DB7 +/* CAN4RXDSR_ARR: Access 8 CAN4RXDSRx registers in an array */ +#define CAN4RXDSR_ARR ((volatile byte *) &CAN4RXDSR0) + +#define CAN4RXDSR0_DB0_MASK 1U +#define CAN4RXDSR0_DB1_MASK 2U +#define CAN4RXDSR0_DB2_MASK 4U +#define CAN4RXDSR0_DB3_MASK 8U +#define CAN4RXDSR0_DB4_MASK 16U +#define CAN4RXDSR0_DB5_MASK 32U +#define CAN4RXDSR0_DB6_MASK 64U +#define CAN4RXDSR0_DB7_MASK 128U + + +/*** CAN4RXDSR1 - MSCAN4 Receive Data Segment Register 1; 0x000002A5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR1STR; +extern volatile CAN4RXDSR1STR _CAN4RXDSR1 @(REG_BASE + 0x000002A5UL); +#define CAN4RXDSR1 _CAN4RXDSR1.Byte +#define CAN4RXDSR1_DB0 _CAN4RXDSR1.Bits.DB0 +#define CAN4RXDSR1_DB1 _CAN4RXDSR1.Bits.DB1 +#define CAN4RXDSR1_DB2 _CAN4RXDSR1.Bits.DB2 +#define CAN4RXDSR1_DB3 _CAN4RXDSR1.Bits.DB3 +#define CAN4RXDSR1_DB4 _CAN4RXDSR1.Bits.DB4 +#define CAN4RXDSR1_DB5 _CAN4RXDSR1.Bits.DB5 +#define CAN4RXDSR1_DB6 _CAN4RXDSR1.Bits.DB6 +#define CAN4RXDSR1_DB7 _CAN4RXDSR1.Bits.DB7 + +#define CAN4RXDSR1_DB0_MASK 1U +#define CAN4RXDSR1_DB1_MASK 2U +#define CAN4RXDSR1_DB2_MASK 4U +#define CAN4RXDSR1_DB3_MASK 8U +#define CAN4RXDSR1_DB4_MASK 16U +#define CAN4RXDSR1_DB5_MASK 32U +#define CAN4RXDSR1_DB6_MASK 64U +#define CAN4RXDSR1_DB7_MASK 128U + + +/*** CAN4RXDSR2 - MSCAN4 Receive Data Segment Register 2; 0x000002A6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR2STR; +extern volatile CAN4RXDSR2STR _CAN4RXDSR2 @(REG_BASE + 0x000002A6UL); +#define CAN4RXDSR2 _CAN4RXDSR2.Byte +#define CAN4RXDSR2_DB0 _CAN4RXDSR2.Bits.DB0 +#define CAN4RXDSR2_DB1 _CAN4RXDSR2.Bits.DB1 +#define CAN4RXDSR2_DB2 _CAN4RXDSR2.Bits.DB2 +#define CAN4RXDSR2_DB3 _CAN4RXDSR2.Bits.DB3 +#define CAN4RXDSR2_DB4 _CAN4RXDSR2.Bits.DB4 +#define CAN4RXDSR2_DB5 _CAN4RXDSR2.Bits.DB5 +#define CAN4RXDSR2_DB6 _CAN4RXDSR2.Bits.DB6 +#define CAN4RXDSR2_DB7 _CAN4RXDSR2.Bits.DB7 + +#define CAN4RXDSR2_DB0_MASK 1U +#define CAN4RXDSR2_DB1_MASK 2U +#define CAN4RXDSR2_DB2_MASK 4U +#define CAN4RXDSR2_DB3_MASK 8U +#define CAN4RXDSR2_DB4_MASK 16U +#define CAN4RXDSR2_DB5_MASK 32U +#define CAN4RXDSR2_DB6_MASK 64U +#define CAN4RXDSR2_DB7_MASK 128U + + +/*** CAN4RXDSR3 - MSCAN4 Receive Data Segment Register 3; 0x000002A7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR3STR; +extern volatile CAN4RXDSR3STR _CAN4RXDSR3 @(REG_BASE + 0x000002A7UL); +#define CAN4RXDSR3 _CAN4RXDSR3.Byte +#define CAN4RXDSR3_DB0 _CAN4RXDSR3.Bits.DB0 +#define CAN4RXDSR3_DB1 _CAN4RXDSR3.Bits.DB1 +#define CAN4RXDSR3_DB2 _CAN4RXDSR3.Bits.DB2 +#define CAN4RXDSR3_DB3 _CAN4RXDSR3.Bits.DB3 +#define CAN4RXDSR3_DB4 _CAN4RXDSR3.Bits.DB4 +#define CAN4RXDSR3_DB5 _CAN4RXDSR3.Bits.DB5 +#define CAN4RXDSR3_DB6 _CAN4RXDSR3.Bits.DB6 +#define CAN4RXDSR3_DB7 _CAN4RXDSR3.Bits.DB7 + +#define CAN4RXDSR3_DB0_MASK 1U +#define CAN4RXDSR3_DB1_MASK 2U +#define CAN4RXDSR3_DB2_MASK 4U +#define CAN4RXDSR3_DB3_MASK 8U +#define CAN4RXDSR3_DB4_MASK 16U +#define CAN4RXDSR3_DB5_MASK 32U +#define CAN4RXDSR3_DB6_MASK 64U +#define CAN4RXDSR3_DB7_MASK 128U + + +/*** CAN4RXDSR4 - MSCAN4 Receive Data Segment Register 4; 0x000002A8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR4STR; +extern volatile CAN4RXDSR4STR _CAN4RXDSR4 @(REG_BASE + 0x000002A8UL); +#define CAN4RXDSR4 _CAN4RXDSR4.Byte +#define CAN4RXDSR4_DB0 _CAN4RXDSR4.Bits.DB0 +#define CAN4RXDSR4_DB1 _CAN4RXDSR4.Bits.DB1 +#define CAN4RXDSR4_DB2 _CAN4RXDSR4.Bits.DB2 +#define CAN4RXDSR4_DB3 _CAN4RXDSR4.Bits.DB3 +#define CAN4RXDSR4_DB4 _CAN4RXDSR4.Bits.DB4 +#define CAN4RXDSR4_DB5 _CAN4RXDSR4.Bits.DB5 +#define CAN4RXDSR4_DB6 _CAN4RXDSR4.Bits.DB6 +#define CAN4RXDSR4_DB7 _CAN4RXDSR4.Bits.DB7 + +#define CAN4RXDSR4_DB0_MASK 1U +#define CAN4RXDSR4_DB1_MASK 2U +#define CAN4RXDSR4_DB2_MASK 4U +#define CAN4RXDSR4_DB3_MASK 8U +#define CAN4RXDSR4_DB4_MASK 16U +#define CAN4RXDSR4_DB5_MASK 32U +#define CAN4RXDSR4_DB6_MASK 64U +#define CAN4RXDSR4_DB7_MASK 128U + + +/*** CAN4RXDSR5 - MSCAN4 Receive Data Segment Register 5; 0x000002A9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR5STR; +extern volatile CAN4RXDSR5STR _CAN4RXDSR5 @(REG_BASE + 0x000002A9UL); +#define CAN4RXDSR5 _CAN4RXDSR5.Byte +#define CAN4RXDSR5_DB0 _CAN4RXDSR5.Bits.DB0 +#define CAN4RXDSR5_DB1 _CAN4RXDSR5.Bits.DB1 +#define CAN4RXDSR5_DB2 _CAN4RXDSR5.Bits.DB2 +#define CAN4RXDSR5_DB3 _CAN4RXDSR5.Bits.DB3 +#define CAN4RXDSR5_DB4 _CAN4RXDSR5.Bits.DB4 +#define CAN4RXDSR5_DB5 _CAN4RXDSR5.Bits.DB5 +#define CAN4RXDSR5_DB6 _CAN4RXDSR5.Bits.DB6 +#define CAN4RXDSR5_DB7 _CAN4RXDSR5.Bits.DB7 + +#define CAN4RXDSR5_DB0_MASK 1U +#define CAN4RXDSR5_DB1_MASK 2U +#define CAN4RXDSR5_DB2_MASK 4U +#define CAN4RXDSR5_DB3_MASK 8U +#define CAN4RXDSR5_DB4_MASK 16U +#define CAN4RXDSR5_DB5_MASK 32U +#define CAN4RXDSR5_DB6_MASK 64U +#define CAN4RXDSR5_DB7_MASK 128U + + +/*** CAN4RXDSR6 - MSCAN4 Receive Data Segment Register 6; 0x000002AA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR6STR; +extern volatile CAN4RXDSR6STR _CAN4RXDSR6 @(REG_BASE + 0x000002AAUL); +#define CAN4RXDSR6 _CAN4RXDSR6.Byte +#define CAN4RXDSR6_DB0 _CAN4RXDSR6.Bits.DB0 +#define CAN4RXDSR6_DB1 _CAN4RXDSR6.Bits.DB1 +#define CAN4RXDSR6_DB2 _CAN4RXDSR6.Bits.DB2 +#define CAN4RXDSR6_DB3 _CAN4RXDSR6.Bits.DB3 +#define CAN4RXDSR6_DB4 _CAN4RXDSR6.Bits.DB4 +#define CAN4RXDSR6_DB5 _CAN4RXDSR6.Bits.DB5 +#define CAN4RXDSR6_DB6 _CAN4RXDSR6.Bits.DB6 +#define CAN4RXDSR6_DB7 _CAN4RXDSR6.Bits.DB7 + +#define CAN4RXDSR6_DB0_MASK 1U +#define CAN4RXDSR6_DB1_MASK 2U +#define CAN4RXDSR6_DB2_MASK 4U +#define CAN4RXDSR6_DB3_MASK 8U +#define CAN4RXDSR6_DB4_MASK 16U +#define CAN4RXDSR6_DB5_MASK 32U +#define CAN4RXDSR6_DB6_MASK 64U +#define CAN4RXDSR6_DB7_MASK 128U + + +/*** CAN4RXDSR7 - MSCAN4 Receive Data Segment Register 7; 0x000002AB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4RXDSR7STR; +extern volatile CAN4RXDSR7STR _CAN4RXDSR7 @(REG_BASE + 0x000002ABUL); +#define CAN4RXDSR7 _CAN4RXDSR7.Byte +#define CAN4RXDSR7_DB0 _CAN4RXDSR7.Bits.DB0 +#define CAN4RXDSR7_DB1 _CAN4RXDSR7.Bits.DB1 +#define CAN4RXDSR7_DB2 _CAN4RXDSR7.Bits.DB2 +#define CAN4RXDSR7_DB3 _CAN4RXDSR7.Bits.DB3 +#define CAN4RXDSR7_DB4 _CAN4RXDSR7.Bits.DB4 +#define CAN4RXDSR7_DB5 _CAN4RXDSR7.Bits.DB5 +#define CAN4RXDSR7_DB6 _CAN4RXDSR7.Bits.DB6 +#define CAN4RXDSR7_DB7 _CAN4RXDSR7.Bits.DB7 + +#define CAN4RXDSR7_DB0_MASK 1U +#define CAN4RXDSR7_DB1_MASK 2U +#define CAN4RXDSR7_DB2_MASK 4U +#define CAN4RXDSR7_DB3_MASK 8U +#define CAN4RXDSR7_DB4_MASK 16U +#define CAN4RXDSR7_DB5_MASK 32U +#define CAN4RXDSR7_DB6_MASK 64U +#define CAN4RXDSR7_DB7_MASK 128U + + +/*** CAN4RXDLR - MSCAN4 Receive Data Length Register; 0x000002AC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4RXDLRSTR; +extern volatile CAN4RXDLRSTR _CAN4RXDLR @(REG_BASE + 0x000002ACUL); +#define CAN4RXDLR _CAN4RXDLR.Byte +#define CAN4RXDLR_DLC0 _CAN4RXDLR.Bits.DLC0 +#define CAN4RXDLR_DLC1 _CAN4RXDLR.Bits.DLC1 +#define CAN4RXDLR_DLC2 _CAN4RXDLR.Bits.DLC2 +#define CAN4RXDLR_DLC3 _CAN4RXDLR.Bits.DLC3 +#define CAN4RXDLR_DLC _CAN4RXDLR.MergedBits.grpDLC + +#define CAN4RXDLR_DLC0_MASK 1U +#define CAN4RXDLR_DLC1_MASK 2U +#define CAN4RXDLR_DLC2_MASK 4U +#define CAN4RXDLR_DLC3_MASK 8U +#define CAN4RXDLR_DLC_MASK 15U +#define CAN4RXDLR_DLC_BITNUM 0U + + +/*** CAN4RXTSR - MSCAN 4 Receive Time Stamp Register; 0x000002AE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** CAN4RXTSRH - MSCAN 4 Receive Time Stamp Register High; 0x000002AE ***/ + union { + byte Byte; + struct { + byte TSR8 :1; /* Time Stamp Bit 8 */ + byte TSR9 :1; /* Time Stamp Bit 9 */ + byte TSR10 :1; /* Time Stamp Bit 10 */ + byte TSR11 :1; /* Time Stamp Bit 11 */ + byte TSR12 :1; /* Time Stamp Bit 12 */ + byte TSR13 :1; /* Time Stamp Bit 13 */ + byte TSR14 :1; /* Time Stamp Bit 14 */ + byte TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; + } CAN4RXTSRHSTR; + #define CAN4RXTSRH _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Byte + #define CAN4RXTSRH_TSR8 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR8 + #define CAN4RXTSRH_TSR9 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR9 + #define CAN4RXTSRH_TSR10 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR10 + #define CAN4RXTSRH_TSR11 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR11 + #define CAN4RXTSRH_TSR12 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR12 + #define CAN4RXTSRH_TSR13 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR13 + #define CAN4RXTSRH_TSR14 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR14 + #define CAN4RXTSRH_TSR15 _CAN4RXTSR.Overlap_STR.CAN4RXTSRHSTR.Bits.TSR15 + + #define CAN4RXTSRH_TSR8_MASK 1U + #define CAN4RXTSRH_TSR9_MASK 2U + #define CAN4RXTSRH_TSR10_MASK 4U + #define CAN4RXTSRH_TSR11_MASK 8U + #define CAN4RXTSRH_TSR12_MASK 16U + #define CAN4RXTSRH_TSR13_MASK 32U + #define CAN4RXTSRH_TSR14_MASK 64U + #define CAN4RXTSRH_TSR15_MASK 128U + + + /*** CAN4RXTSRL - MSCAN 4 Receive Time Stamp Register Low; 0x000002AF ***/ + union { + byte Byte; + struct { + byte TSR0 :1; /* Time Stamp Bit 0 */ + byte TSR1 :1; /* Time Stamp Bit 1 */ + byte TSR2 :1; /* Time Stamp Bit 2 */ + byte TSR3 :1; /* Time Stamp Bit 3 */ + byte TSR4 :1; /* Time Stamp Bit 4 */ + byte TSR5 :1; /* Time Stamp Bit 5 */ + byte TSR6 :1; /* Time Stamp Bit 6 */ + byte TSR7 :1; /* Time Stamp Bit 7 */ + } Bits; + } CAN4RXTSRLSTR; + #define CAN4RXTSRL _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Byte + #define CAN4RXTSRL_TSR0 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR0 + #define CAN4RXTSRL_TSR1 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR1 + #define CAN4RXTSRL_TSR2 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR2 + #define CAN4RXTSRL_TSR3 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR3 + #define CAN4RXTSRL_TSR4 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR4 + #define CAN4RXTSRL_TSR5 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR5 + #define CAN4RXTSRL_TSR6 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR6 + #define CAN4RXTSRL_TSR7 _CAN4RXTSR.Overlap_STR.CAN4RXTSRLSTR.Bits.TSR7 + + #define CAN4RXTSRL_TSR0_MASK 1U + #define CAN4RXTSRL_TSR1_MASK 2U + #define CAN4RXTSRL_TSR2_MASK 4U + #define CAN4RXTSRL_TSR3_MASK 8U + #define CAN4RXTSRL_TSR4_MASK 16U + #define CAN4RXTSRL_TSR5_MASK 32U + #define CAN4RXTSRL_TSR6_MASK 64U + #define CAN4RXTSRL_TSR7_MASK 128U + + } Overlap_STR; + + struct { + word TSR0 :1; /* Time Stamp Bit 0 */ + word TSR1 :1; /* Time Stamp Bit 1 */ + word TSR2 :1; /* Time Stamp Bit 2 */ + word TSR3 :1; /* Time Stamp Bit 3 */ + word TSR4 :1; /* Time Stamp Bit 4 */ + word TSR5 :1; /* Time Stamp Bit 5 */ + word TSR6 :1; /* Time Stamp Bit 6 */ + word TSR7 :1; /* Time Stamp Bit 7 */ + word TSR8 :1; /* Time Stamp Bit 8 */ + word TSR9 :1; /* Time Stamp Bit 9 */ + word TSR10 :1; /* Time Stamp Bit 10 */ + word TSR11 :1; /* Time Stamp Bit 11 */ + word TSR12 :1; /* Time Stamp Bit 12 */ + word TSR13 :1; /* Time Stamp Bit 13 */ + word TSR14 :1; /* Time Stamp Bit 14 */ + word TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; +} CAN4RXTSRSTR; +extern volatile CAN4RXTSRSTR _CAN4RXTSR @(REG_BASE + 0x000002AEUL); +#define CAN4RXTSR _CAN4RXTSR.Word +#define CAN4RXTSR_TSR0 _CAN4RXTSR.Bits.TSR0 +#define CAN4RXTSR_TSR1 _CAN4RXTSR.Bits.TSR1 +#define CAN4RXTSR_TSR2 _CAN4RXTSR.Bits.TSR2 +#define CAN4RXTSR_TSR3 _CAN4RXTSR.Bits.TSR3 +#define CAN4RXTSR_TSR4 _CAN4RXTSR.Bits.TSR4 +#define CAN4RXTSR_TSR5 _CAN4RXTSR.Bits.TSR5 +#define CAN4RXTSR_TSR6 _CAN4RXTSR.Bits.TSR6 +#define CAN4RXTSR_TSR7 _CAN4RXTSR.Bits.TSR7 +#define CAN4RXTSR_TSR8 _CAN4RXTSR.Bits.TSR8 +#define CAN4RXTSR_TSR9 _CAN4RXTSR.Bits.TSR9 +#define CAN4RXTSR_TSR10 _CAN4RXTSR.Bits.TSR10 +#define CAN4RXTSR_TSR11 _CAN4RXTSR.Bits.TSR11 +#define CAN4RXTSR_TSR12 _CAN4RXTSR.Bits.TSR12 +#define CAN4RXTSR_TSR13 _CAN4RXTSR.Bits.TSR13 +#define CAN4RXTSR_TSR14 _CAN4RXTSR.Bits.TSR14 +#define CAN4RXTSR_TSR15 _CAN4RXTSR.Bits.TSR15 + +#define CAN4RXTSR_TSR0_MASK 1U +#define CAN4RXTSR_TSR1_MASK 2U +#define CAN4RXTSR_TSR2_MASK 4U +#define CAN4RXTSR_TSR3_MASK 8U +#define CAN4RXTSR_TSR4_MASK 16U +#define CAN4RXTSR_TSR5_MASK 32U +#define CAN4RXTSR_TSR6_MASK 64U +#define CAN4RXTSR_TSR7_MASK 128U +#define CAN4RXTSR_TSR8_MASK 256U +#define CAN4RXTSR_TSR9_MASK 512U +#define CAN4RXTSR_TSR10_MASK 1024U +#define CAN4RXTSR_TSR11_MASK 2048U +#define CAN4RXTSR_TSR12_MASK 4096U +#define CAN4RXTSR_TSR13_MASK 8192U +#define CAN4RXTSR_TSR14_MASK 16384U +#define CAN4RXTSR_TSR15_MASK 32768U + + +/*** CAN4TXIDR0 - MSCAN4 Transmit Identifier Register 0; 0x000002B0 ***/ +typedef union { + byte Byte; + struct { + byte ID21 :1; /* Extended format identifier Bit 21 */ + byte ID22 :1; /* Extended format identifier Bit 22 */ + byte ID23 :1; /* Extended format identifier Bit 23 */ + byte ID24 :1; /* Extended format identifier Bit 24 */ + byte ID25 :1; /* Extended format identifier Bit 25 */ + byte ID26 :1; /* Extended format identifier Bit 26 */ + byte ID27 :1; /* Extended format identifier Bit 27 */ + byte ID28 :1; /* Extended format identifier Bit 28 */ + } Bits; +} CAN4TXIDR0STR; +extern volatile CAN4TXIDR0STR _CAN4TXIDR0 @(REG_BASE + 0x000002B0UL); +#define CAN4TXIDR0 _CAN4TXIDR0.Byte +#define CAN4TXIDR0_ID21 _CAN4TXIDR0.Bits.ID21 +#define CAN4TXIDR0_ID22 _CAN4TXIDR0.Bits.ID22 +#define CAN4TXIDR0_ID23 _CAN4TXIDR0.Bits.ID23 +#define CAN4TXIDR0_ID24 _CAN4TXIDR0.Bits.ID24 +#define CAN4TXIDR0_ID25 _CAN4TXIDR0.Bits.ID25 +#define CAN4TXIDR0_ID26 _CAN4TXIDR0.Bits.ID26 +#define CAN4TXIDR0_ID27 _CAN4TXIDR0.Bits.ID27 +#define CAN4TXIDR0_ID28 _CAN4TXIDR0.Bits.ID28 +/* CAN4TXIDR_ARR: Access 4 CAN4TXIDRx registers in an array */ +#define CAN4TXIDR_ARR ((volatile byte *) &CAN4TXIDR0) + +#define CAN4TXIDR0_ID21_MASK 1U +#define CAN4TXIDR0_ID22_MASK 2U +#define CAN4TXIDR0_ID23_MASK 4U +#define CAN4TXIDR0_ID24_MASK 8U +#define CAN4TXIDR0_ID25_MASK 16U +#define CAN4TXIDR0_ID26_MASK 32U +#define CAN4TXIDR0_ID27_MASK 64U +#define CAN4TXIDR0_ID28_MASK 128U + + +/*** CAN4TXIDR1 - MSCAN4 Transmit Identifier Register 1; 0x000002B1 ***/ +typedef union { + byte Byte; + struct { + byte ID15 :1; /* Extended format identifier Bit 15 */ + byte ID16 :1; /* Extended format identifier Bit 16 */ + byte ID17 :1; /* Extended format identifier Bit 17 */ + byte IDE :1; /* ID Extended */ + byte SRR :1; /* Substitute Remote Request */ + byte ID18 :1; /* Extended format identifier Bit 18 */ + byte ID19 :1; /* Extended format identifier Bit 19 */ + byte ID20 :1; /* Extended format identifier Bit 20 */ + } Bits; + struct { + byte grpID_15 :3; + byte :1; + byte :1; + byte grpID_18 :3; + } MergedBits; +} CAN4TXIDR1STR; +extern volatile CAN4TXIDR1STR _CAN4TXIDR1 @(REG_BASE + 0x000002B1UL); +#define CAN4TXIDR1 _CAN4TXIDR1.Byte +#define CAN4TXIDR1_ID15 _CAN4TXIDR1.Bits.ID15 +#define CAN4TXIDR1_ID16 _CAN4TXIDR1.Bits.ID16 +#define CAN4TXIDR1_ID17 _CAN4TXIDR1.Bits.ID17 +#define CAN4TXIDR1_IDE _CAN4TXIDR1.Bits.IDE +#define CAN4TXIDR1_SRR _CAN4TXIDR1.Bits.SRR +#define CAN4TXIDR1_ID18 _CAN4TXIDR1.Bits.ID18 +#define CAN4TXIDR1_ID19 _CAN4TXIDR1.Bits.ID19 +#define CAN4TXIDR1_ID20 _CAN4TXIDR1.Bits.ID20 +#define CAN4TXIDR1_ID_15 _CAN4TXIDR1.MergedBits.grpID_15 +#define CAN4TXIDR1_ID_18 _CAN4TXIDR1.MergedBits.grpID_18 +#define CAN4TXIDR1_ID CAN4TXIDR1_ID_15 + +#define CAN4TXIDR1_ID15_MASK 1U +#define CAN4TXIDR1_ID16_MASK 2U +#define CAN4TXIDR1_ID17_MASK 4U +#define CAN4TXIDR1_IDE_MASK 8U +#define CAN4TXIDR1_SRR_MASK 16U +#define CAN4TXIDR1_ID18_MASK 32U +#define CAN4TXIDR1_ID19_MASK 64U +#define CAN4TXIDR1_ID20_MASK 128U +#define CAN4TXIDR1_ID_15_MASK 7U +#define CAN4TXIDR1_ID_15_BITNUM 0U +#define CAN4TXIDR1_ID_18_MASK 224U +#define CAN4TXIDR1_ID_18_BITNUM 5U + + +/*** CAN4TXIDR2 - MSCAN4 Transmit Identifier Register 2; 0x000002B2 ***/ +typedef union { + byte Byte; + struct { + byte ID7 :1; /* Extended format identifier Bit 7 */ + byte ID8 :1; /* Extended format identifier Bit 8 */ + byte ID9 :1; /* Extended format identifier Bit 9 */ + byte ID10 :1; /* Extended format identifier Bit 10 */ + byte ID11 :1; /* Extended format identifier Bit 11 */ + byte ID12 :1; /* Extended format identifier Bit 12 */ + byte ID13 :1; /* Extended format identifier Bit 13 */ + byte ID14 :1; /* Extended format identifier Bit 14 */ + } Bits; +} CAN4TXIDR2STR; +extern volatile CAN4TXIDR2STR _CAN4TXIDR2 @(REG_BASE + 0x000002B2UL); +#define CAN4TXIDR2 _CAN4TXIDR2.Byte +#define CAN4TXIDR2_ID7 _CAN4TXIDR2.Bits.ID7 +#define CAN4TXIDR2_ID8 _CAN4TXIDR2.Bits.ID8 +#define CAN4TXIDR2_ID9 _CAN4TXIDR2.Bits.ID9 +#define CAN4TXIDR2_ID10 _CAN4TXIDR2.Bits.ID10 +#define CAN4TXIDR2_ID11 _CAN4TXIDR2.Bits.ID11 +#define CAN4TXIDR2_ID12 _CAN4TXIDR2.Bits.ID12 +#define CAN4TXIDR2_ID13 _CAN4TXIDR2.Bits.ID13 +#define CAN4TXIDR2_ID14 _CAN4TXIDR2.Bits.ID14 + +#define CAN4TXIDR2_ID7_MASK 1U +#define CAN4TXIDR2_ID8_MASK 2U +#define CAN4TXIDR2_ID9_MASK 4U +#define CAN4TXIDR2_ID10_MASK 8U +#define CAN4TXIDR2_ID11_MASK 16U +#define CAN4TXIDR2_ID12_MASK 32U +#define CAN4TXIDR2_ID13_MASK 64U +#define CAN4TXIDR2_ID14_MASK 128U + + +/*** CAN4TXIDR3 - MSCAN4 Transmit Identifier Register 3; 0x000002B3 ***/ +typedef union { + byte Byte; + struct { + byte RTR :1; /* Remote Transmission Request */ + byte ID0 :1; /* Extended format identifier Bit 0 */ + byte ID1 :1; /* Extended format identifier Bit 1 */ + byte ID2 :1; /* Extended format identifier Bit 2 */ + byte ID3 :1; /* Extended format identifier Bit 3 */ + byte ID4 :1; /* Extended format identifier Bit 4 */ + byte ID5 :1; /* Extended format identifier Bit 5 */ + byte ID6 :1; /* Extended format identifier Bit 6 */ + } Bits; + struct { + byte :1; + byte grpID :7; + } MergedBits; +} CAN4TXIDR3STR; +extern volatile CAN4TXIDR3STR _CAN4TXIDR3 @(REG_BASE + 0x000002B3UL); +#define CAN4TXIDR3 _CAN4TXIDR3.Byte +#define CAN4TXIDR3_RTR _CAN4TXIDR3.Bits.RTR +#define CAN4TXIDR3_ID0 _CAN4TXIDR3.Bits.ID0 +#define CAN4TXIDR3_ID1 _CAN4TXIDR3.Bits.ID1 +#define CAN4TXIDR3_ID2 _CAN4TXIDR3.Bits.ID2 +#define CAN4TXIDR3_ID3 _CAN4TXIDR3.Bits.ID3 +#define CAN4TXIDR3_ID4 _CAN4TXIDR3.Bits.ID4 +#define CAN4TXIDR3_ID5 _CAN4TXIDR3.Bits.ID5 +#define CAN4TXIDR3_ID6 _CAN4TXIDR3.Bits.ID6 +#define CAN4TXIDR3_ID _CAN4TXIDR3.MergedBits.grpID + +#define CAN4TXIDR3_RTR_MASK 1U +#define CAN4TXIDR3_ID0_MASK 2U +#define CAN4TXIDR3_ID1_MASK 4U +#define CAN4TXIDR3_ID2_MASK 8U +#define CAN4TXIDR3_ID3_MASK 16U +#define CAN4TXIDR3_ID4_MASK 32U +#define CAN4TXIDR3_ID5_MASK 64U +#define CAN4TXIDR3_ID6_MASK 128U +#define CAN4TXIDR3_ID_MASK 254U +#define CAN4TXIDR3_ID_BITNUM 1U + + +/*** CAN4TXDSR0 - MSCAN4 Transmit Data Segment Register 0; 0x000002B4 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR0STR; +extern volatile CAN4TXDSR0STR _CAN4TXDSR0 @(REG_BASE + 0x000002B4UL); +#define CAN4TXDSR0 _CAN4TXDSR0.Byte +#define CAN4TXDSR0_DB0 _CAN4TXDSR0.Bits.DB0 +#define CAN4TXDSR0_DB1 _CAN4TXDSR0.Bits.DB1 +#define CAN4TXDSR0_DB2 _CAN4TXDSR0.Bits.DB2 +#define CAN4TXDSR0_DB3 _CAN4TXDSR0.Bits.DB3 +#define CAN4TXDSR0_DB4 _CAN4TXDSR0.Bits.DB4 +#define CAN4TXDSR0_DB5 _CAN4TXDSR0.Bits.DB5 +#define CAN4TXDSR0_DB6 _CAN4TXDSR0.Bits.DB6 +#define CAN4TXDSR0_DB7 _CAN4TXDSR0.Bits.DB7 +/* CAN4TXDSR_ARR: Access 8 CAN4TXDSRx registers in an array */ +#define CAN4TXDSR_ARR ((volatile byte *) &CAN4TXDSR0) + +#define CAN4TXDSR0_DB0_MASK 1U +#define CAN4TXDSR0_DB1_MASK 2U +#define CAN4TXDSR0_DB2_MASK 4U +#define CAN4TXDSR0_DB3_MASK 8U +#define CAN4TXDSR0_DB4_MASK 16U +#define CAN4TXDSR0_DB5_MASK 32U +#define CAN4TXDSR0_DB6_MASK 64U +#define CAN4TXDSR0_DB7_MASK 128U + + +/*** CAN4TXDSR1 - MSCAN4 Transmit Data Segment Register 1; 0x000002B5 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR1STR; +extern volatile CAN4TXDSR1STR _CAN4TXDSR1 @(REG_BASE + 0x000002B5UL); +#define CAN4TXDSR1 _CAN4TXDSR1.Byte +#define CAN4TXDSR1_DB0 _CAN4TXDSR1.Bits.DB0 +#define CAN4TXDSR1_DB1 _CAN4TXDSR1.Bits.DB1 +#define CAN4TXDSR1_DB2 _CAN4TXDSR1.Bits.DB2 +#define CAN4TXDSR1_DB3 _CAN4TXDSR1.Bits.DB3 +#define CAN4TXDSR1_DB4 _CAN4TXDSR1.Bits.DB4 +#define CAN4TXDSR1_DB5 _CAN4TXDSR1.Bits.DB5 +#define CAN4TXDSR1_DB6 _CAN4TXDSR1.Bits.DB6 +#define CAN4TXDSR1_DB7 _CAN4TXDSR1.Bits.DB7 + +#define CAN4TXDSR1_DB0_MASK 1U +#define CAN4TXDSR1_DB1_MASK 2U +#define CAN4TXDSR1_DB2_MASK 4U +#define CAN4TXDSR1_DB3_MASK 8U +#define CAN4TXDSR1_DB4_MASK 16U +#define CAN4TXDSR1_DB5_MASK 32U +#define CAN4TXDSR1_DB6_MASK 64U +#define CAN4TXDSR1_DB7_MASK 128U + + +/*** CAN4TXDSR2 - MSCAN4 Transmit Data Segment Register 2; 0x000002B6 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR2STR; +extern volatile CAN4TXDSR2STR _CAN4TXDSR2 @(REG_BASE + 0x000002B6UL); +#define CAN4TXDSR2 _CAN4TXDSR2.Byte +#define CAN4TXDSR2_DB0 _CAN4TXDSR2.Bits.DB0 +#define CAN4TXDSR2_DB1 _CAN4TXDSR2.Bits.DB1 +#define CAN4TXDSR2_DB2 _CAN4TXDSR2.Bits.DB2 +#define CAN4TXDSR2_DB3 _CAN4TXDSR2.Bits.DB3 +#define CAN4TXDSR2_DB4 _CAN4TXDSR2.Bits.DB4 +#define CAN4TXDSR2_DB5 _CAN4TXDSR2.Bits.DB5 +#define CAN4TXDSR2_DB6 _CAN4TXDSR2.Bits.DB6 +#define CAN4TXDSR2_DB7 _CAN4TXDSR2.Bits.DB7 + +#define CAN4TXDSR2_DB0_MASK 1U +#define CAN4TXDSR2_DB1_MASK 2U +#define CAN4TXDSR2_DB2_MASK 4U +#define CAN4TXDSR2_DB3_MASK 8U +#define CAN4TXDSR2_DB4_MASK 16U +#define CAN4TXDSR2_DB5_MASK 32U +#define CAN4TXDSR2_DB6_MASK 64U +#define CAN4TXDSR2_DB7_MASK 128U + + +/*** CAN4TXDSR3 - MSCAN4 Transmit Data Segment Register 3; 0x000002B7 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR3STR; +extern volatile CAN4TXDSR3STR _CAN4TXDSR3 @(REG_BASE + 0x000002B7UL); +#define CAN4TXDSR3 _CAN4TXDSR3.Byte +#define CAN4TXDSR3_DB0 _CAN4TXDSR3.Bits.DB0 +#define CAN4TXDSR3_DB1 _CAN4TXDSR3.Bits.DB1 +#define CAN4TXDSR3_DB2 _CAN4TXDSR3.Bits.DB2 +#define CAN4TXDSR3_DB3 _CAN4TXDSR3.Bits.DB3 +#define CAN4TXDSR3_DB4 _CAN4TXDSR3.Bits.DB4 +#define CAN4TXDSR3_DB5 _CAN4TXDSR3.Bits.DB5 +#define CAN4TXDSR3_DB6 _CAN4TXDSR3.Bits.DB6 +#define CAN4TXDSR3_DB7 _CAN4TXDSR3.Bits.DB7 + +#define CAN4TXDSR3_DB0_MASK 1U +#define CAN4TXDSR3_DB1_MASK 2U +#define CAN4TXDSR3_DB2_MASK 4U +#define CAN4TXDSR3_DB3_MASK 8U +#define CAN4TXDSR3_DB4_MASK 16U +#define CAN4TXDSR3_DB5_MASK 32U +#define CAN4TXDSR3_DB6_MASK 64U +#define CAN4TXDSR3_DB7_MASK 128U + + +/*** CAN4TXDSR4 - MSCAN4 Transmit Data Segment Register 4; 0x000002B8 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR4STR; +extern volatile CAN4TXDSR4STR _CAN4TXDSR4 @(REG_BASE + 0x000002B8UL); +#define CAN4TXDSR4 _CAN4TXDSR4.Byte +#define CAN4TXDSR4_DB0 _CAN4TXDSR4.Bits.DB0 +#define CAN4TXDSR4_DB1 _CAN4TXDSR4.Bits.DB1 +#define CAN4TXDSR4_DB2 _CAN4TXDSR4.Bits.DB2 +#define CAN4TXDSR4_DB3 _CAN4TXDSR4.Bits.DB3 +#define CAN4TXDSR4_DB4 _CAN4TXDSR4.Bits.DB4 +#define CAN4TXDSR4_DB5 _CAN4TXDSR4.Bits.DB5 +#define CAN4TXDSR4_DB6 _CAN4TXDSR4.Bits.DB6 +#define CAN4TXDSR4_DB7 _CAN4TXDSR4.Bits.DB7 + +#define CAN4TXDSR4_DB0_MASK 1U +#define CAN4TXDSR4_DB1_MASK 2U +#define CAN4TXDSR4_DB2_MASK 4U +#define CAN4TXDSR4_DB3_MASK 8U +#define CAN4TXDSR4_DB4_MASK 16U +#define CAN4TXDSR4_DB5_MASK 32U +#define CAN4TXDSR4_DB6_MASK 64U +#define CAN4TXDSR4_DB7_MASK 128U + + +/*** CAN4TXDSR5 - MSCAN4 Transmit Data Segment Register 5; 0x000002B9 ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR5STR; +extern volatile CAN4TXDSR5STR _CAN4TXDSR5 @(REG_BASE + 0x000002B9UL); +#define CAN4TXDSR5 _CAN4TXDSR5.Byte +#define CAN4TXDSR5_DB0 _CAN4TXDSR5.Bits.DB0 +#define CAN4TXDSR5_DB1 _CAN4TXDSR5.Bits.DB1 +#define CAN4TXDSR5_DB2 _CAN4TXDSR5.Bits.DB2 +#define CAN4TXDSR5_DB3 _CAN4TXDSR5.Bits.DB3 +#define CAN4TXDSR5_DB4 _CAN4TXDSR5.Bits.DB4 +#define CAN4TXDSR5_DB5 _CAN4TXDSR5.Bits.DB5 +#define CAN4TXDSR5_DB6 _CAN4TXDSR5.Bits.DB6 +#define CAN4TXDSR5_DB7 _CAN4TXDSR5.Bits.DB7 + +#define CAN4TXDSR5_DB0_MASK 1U +#define CAN4TXDSR5_DB1_MASK 2U +#define CAN4TXDSR5_DB2_MASK 4U +#define CAN4TXDSR5_DB3_MASK 8U +#define CAN4TXDSR5_DB4_MASK 16U +#define CAN4TXDSR5_DB5_MASK 32U +#define CAN4TXDSR5_DB6_MASK 64U +#define CAN4TXDSR5_DB7_MASK 128U + + +/*** CAN4TXDSR6 - MSCAN4 Transmit Data Segment Register 6; 0x000002BA ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR6STR; +extern volatile CAN4TXDSR6STR _CAN4TXDSR6 @(REG_BASE + 0x000002BAUL); +#define CAN4TXDSR6 _CAN4TXDSR6.Byte +#define CAN4TXDSR6_DB0 _CAN4TXDSR6.Bits.DB0 +#define CAN4TXDSR6_DB1 _CAN4TXDSR6.Bits.DB1 +#define CAN4TXDSR6_DB2 _CAN4TXDSR6.Bits.DB2 +#define CAN4TXDSR6_DB3 _CAN4TXDSR6.Bits.DB3 +#define CAN4TXDSR6_DB4 _CAN4TXDSR6.Bits.DB4 +#define CAN4TXDSR6_DB5 _CAN4TXDSR6.Bits.DB5 +#define CAN4TXDSR6_DB6 _CAN4TXDSR6.Bits.DB6 +#define CAN4TXDSR6_DB7 _CAN4TXDSR6.Bits.DB7 + +#define CAN4TXDSR6_DB0_MASK 1U +#define CAN4TXDSR6_DB1_MASK 2U +#define CAN4TXDSR6_DB2_MASK 4U +#define CAN4TXDSR6_DB3_MASK 8U +#define CAN4TXDSR6_DB4_MASK 16U +#define CAN4TXDSR6_DB5_MASK 32U +#define CAN4TXDSR6_DB6_MASK 64U +#define CAN4TXDSR6_DB7_MASK 128U + + +/*** CAN4TXDSR7 - MSCAN4 Transmit Data Segment Register 7; 0x000002BB ***/ +typedef union { + byte Byte; + struct { + byte DB0 :1; /* Data Bit 0 */ + byte DB1 :1; /* Data Bit 1 */ + byte DB2 :1; /* Data Bit 2 */ + byte DB3 :1; /* Data Bit 3 */ + byte DB4 :1; /* Data Bit 4 */ + byte DB5 :1; /* Data Bit 5 */ + byte DB6 :1; /* Data Bit 6 */ + byte DB7 :1; /* Data Bit 7 */ + } Bits; +} CAN4TXDSR7STR; +extern volatile CAN4TXDSR7STR _CAN4TXDSR7 @(REG_BASE + 0x000002BBUL); +#define CAN4TXDSR7 _CAN4TXDSR7.Byte +#define CAN4TXDSR7_DB0 _CAN4TXDSR7.Bits.DB0 +#define CAN4TXDSR7_DB1 _CAN4TXDSR7.Bits.DB1 +#define CAN4TXDSR7_DB2 _CAN4TXDSR7.Bits.DB2 +#define CAN4TXDSR7_DB3 _CAN4TXDSR7.Bits.DB3 +#define CAN4TXDSR7_DB4 _CAN4TXDSR7.Bits.DB4 +#define CAN4TXDSR7_DB5 _CAN4TXDSR7.Bits.DB5 +#define CAN4TXDSR7_DB6 _CAN4TXDSR7.Bits.DB6 +#define CAN4TXDSR7_DB7 _CAN4TXDSR7.Bits.DB7 + +#define CAN4TXDSR7_DB0_MASK 1U +#define CAN4TXDSR7_DB1_MASK 2U +#define CAN4TXDSR7_DB2_MASK 4U +#define CAN4TXDSR7_DB3_MASK 8U +#define CAN4TXDSR7_DB4_MASK 16U +#define CAN4TXDSR7_DB5_MASK 32U +#define CAN4TXDSR7_DB6_MASK 64U +#define CAN4TXDSR7_DB7_MASK 128U + + +/*** CAN4TXDLR - MSCAN4 Transmit Data Length Register; 0x000002BC ***/ +typedef union { + byte Byte; + struct { + byte DLC0 :1; /* Data Length Code Bit 0 */ + byte DLC1 :1; /* Data Length Code Bit 1 */ + byte DLC2 :1; /* Data Length Code Bit 2 */ + byte DLC3 :1; /* Data Length Code Bit 3 */ + byte :1; + byte :1; + byte :1; + byte :1; + } Bits; + struct { + byte grpDLC :4; + byte :1; + byte :1; + byte :1; + byte :1; + } MergedBits; +} CAN4TXDLRSTR; +extern volatile CAN4TXDLRSTR _CAN4TXDLR @(REG_BASE + 0x000002BCUL); +#define CAN4TXDLR _CAN4TXDLR.Byte +#define CAN4TXDLR_DLC0 _CAN4TXDLR.Bits.DLC0 +#define CAN4TXDLR_DLC1 _CAN4TXDLR.Bits.DLC1 +#define CAN4TXDLR_DLC2 _CAN4TXDLR.Bits.DLC2 +#define CAN4TXDLR_DLC3 _CAN4TXDLR.Bits.DLC3 +#define CAN4TXDLR_DLC _CAN4TXDLR.MergedBits.grpDLC + +#define CAN4TXDLR_DLC0_MASK 1U +#define CAN4TXDLR_DLC1_MASK 2U +#define CAN4TXDLR_DLC2_MASK 4U +#define CAN4TXDLR_DLC3_MASK 8U +#define CAN4TXDLR_DLC_MASK 15U +#define CAN4TXDLR_DLC_BITNUM 0U + + +/*** CAN4TXTBPR - MSCAN4 Transmit Transmit Buffer Priority; 0x000002BD ***/ +typedef union { + byte Byte; + struct { + byte PRIO0 :1; /* Transmit Buffer Priority Bit 0 */ + byte PRIO1 :1; /* Transmit Buffer Priority Bit 1 */ + byte PRIO2 :1; /* Transmit Buffer Priority Bit 2 */ + byte PRIO3 :1; /* Transmit Buffer Priority Bit 3 */ + byte PRIO4 :1; /* Transmit Buffer Priority Bit 4 */ + byte PRIO5 :1; /* Transmit Buffer Priority Bit 5 */ + byte PRIO6 :1; /* Transmit Buffer Priority Bit 6 */ + byte PRIO7 :1; /* Transmit Buffer Priority Bit 7 */ + } Bits; +} CAN4TXTBPRSTR; +extern volatile CAN4TXTBPRSTR _CAN4TXTBPR @(REG_BASE + 0x000002BDUL); +#define CAN4TXTBPR _CAN4TXTBPR.Byte +#define CAN4TXTBPR_PRIO0 _CAN4TXTBPR.Bits.PRIO0 +#define CAN4TXTBPR_PRIO1 _CAN4TXTBPR.Bits.PRIO1 +#define CAN4TXTBPR_PRIO2 _CAN4TXTBPR.Bits.PRIO2 +#define CAN4TXTBPR_PRIO3 _CAN4TXTBPR.Bits.PRIO3 +#define CAN4TXTBPR_PRIO4 _CAN4TXTBPR.Bits.PRIO4 +#define CAN4TXTBPR_PRIO5 _CAN4TXTBPR.Bits.PRIO5 +#define CAN4TXTBPR_PRIO6 _CAN4TXTBPR.Bits.PRIO6 +#define CAN4TXTBPR_PRIO7 _CAN4TXTBPR.Bits.PRIO7 + +#define CAN4TXTBPR_PRIO0_MASK 1U +#define CAN4TXTBPR_PRIO1_MASK 2U +#define CAN4TXTBPR_PRIO2_MASK 4U +#define CAN4TXTBPR_PRIO3_MASK 8U +#define CAN4TXTBPR_PRIO4_MASK 16U +#define CAN4TXTBPR_PRIO5_MASK 32U +#define CAN4TXTBPR_PRIO6_MASK 64U +#define CAN4TXTBPR_PRIO7_MASK 128U + + +/*** CAN4TXTSR - MSCAN 4 Transmit Time Stamp Register; 0x000002BE ***/ +typedef union { + word Word; + /* Overlapped registers: */ + struct { + /*** CAN4TXTSRH - MSCAN 4 Transmit Time Stamp Register High; 0x000002BE ***/ + union { + byte Byte; + struct { + byte TSR8 :1; /* Time Stamp Bit 8 */ + byte TSR9 :1; /* Time Stamp Bit 9 */ + byte TSR10 :1; /* Time Stamp Bit 10 */ + byte TSR11 :1; /* Time Stamp Bit 11 */ + byte TSR12 :1; /* Time Stamp Bit 12 */ + byte TSR13 :1; /* Time Stamp Bit 13 */ + byte TSR14 :1; /* Time Stamp Bit 14 */ + byte TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; + } CAN4TXTSRHSTR; + #define CAN4TXTSRH _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Byte + #define CAN4TXTSRH_TSR8 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR8 + #define CAN4TXTSRH_TSR9 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR9 + #define CAN4TXTSRH_TSR10 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR10 + #define CAN4TXTSRH_TSR11 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR11 + #define CAN4TXTSRH_TSR12 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR12 + #define CAN4TXTSRH_TSR13 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR13 + #define CAN4TXTSRH_TSR14 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR14 + #define CAN4TXTSRH_TSR15 _CAN4TXTSR.Overlap_STR.CAN4TXTSRHSTR.Bits.TSR15 + + #define CAN4TXTSRH_TSR8_MASK 1U + #define CAN4TXTSRH_TSR9_MASK 2U + #define CAN4TXTSRH_TSR10_MASK 4U + #define CAN4TXTSRH_TSR11_MASK 8U + #define CAN4TXTSRH_TSR12_MASK 16U + #define CAN4TXTSRH_TSR13_MASK 32U + #define CAN4TXTSRH_TSR14_MASK 64U + #define CAN4TXTSRH_TSR15_MASK 128U + + + /*** CAN4TXTSRL - MSCAN 4 Transmit Time Stamp Register Low; 0x000002BF ***/ + union { + byte Byte; + struct { + byte TSR0 :1; /* Time Stamp Bit 0 */ + byte TSR1 :1; /* Time Stamp Bit 1 */ + byte TSR2 :1; /* Time Stamp Bit 2 */ + byte TSR3 :1; /* Time Stamp Bit 3 */ + byte TSR4 :1; /* Time Stamp Bit 4 */ + byte TSR5 :1; /* Time Stamp Bit 5 */ + byte TSR6 :1; /* Time Stamp Bit 6 */ + byte TSR7 :1; /* Time Stamp Bit 7 */ + } Bits; + } CAN4TXTSRLSTR; + #define CAN4TXTSRL _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Byte + #define CAN4TXTSRL_TSR0 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR0 + #define CAN4TXTSRL_TSR1 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR1 + #define CAN4TXTSRL_TSR2 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR2 + #define CAN4TXTSRL_TSR3 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR3 + #define CAN4TXTSRL_TSR4 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR4 + #define CAN4TXTSRL_TSR5 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR5 + #define CAN4TXTSRL_TSR6 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR6 + #define CAN4TXTSRL_TSR7 _CAN4TXTSR.Overlap_STR.CAN4TXTSRLSTR.Bits.TSR7 + + #define CAN4TXTSRL_TSR0_MASK 1U + #define CAN4TXTSRL_TSR1_MASK 2U + #define CAN4TXTSRL_TSR2_MASK 4U + #define CAN4TXTSRL_TSR3_MASK 8U + #define CAN4TXTSRL_TSR4_MASK 16U + #define CAN4TXTSRL_TSR5_MASK 32U + #define CAN4TXTSRL_TSR6_MASK 64U + #define CAN4TXTSRL_TSR7_MASK 128U + + } Overlap_STR; + + struct { + word TSR0 :1; /* Time Stamp Bit 0 */ + word TSR1 :1; /* Time Stamp Bit 1 */ + word TSR2 :1; /* Time Stamp Bit 2 */ + word TSR3 :1; /* Time Stamp Bit 3 */ + word TSR4 :1; /* Time Stamp Bit 4 */ + word TSR5 :1; /* Time Stamp Bit 5 */ + word TSR6 :1; /* Time Stamp Bit 6 */ + word TSR7 :1; /* Time Stamp Bit 7 */ + word TSR8 :1; /* Time Stamp Bit 8 */ + word TSR9 :1; /* Time Stamp Bit 9 */ + word TSR10 :1; /* Time Stamp Bit 10 */ + word TSR11 :1; /* Time Stamp Bit 11 */ + word TSR12 :1; /* Time Stamp Bit 12 */ + word TSR13 :1; /* Time Stamp Bit 13 */ + word TSR14 :1; /* Time Stamp Bit 14 */ + word TSR15 :1; /* Time Stamp Bit 15 */ + } Bits; +} CAN4TXTSRSTR; +extern volatile CAN4TXTSRSTR _CAN4TXTSR @(REG_BASE + 0x000002BEUL); +#define CAN4TXTSR _CAN4TXTSR.Word +#define CAN4TXTSR_TSR0 _CAN4TXTSR.Bits.TSR0 +#define CAN4TXTSR_TSR1 _CAN4TXTSR.Bits.TSR1 +#define CAN4TXTSR_TSR2 _CAN4TXTSR.Bits.TSR2 +#define CAN4TXTSR_TSR3 _CAN4TXTSR.Bits.TSR3 +#define CAN4TXTSR_TSR4 _CAN4TXTSR.Bits.TSR4 +#define CAN4TXTSR_TSR5 _CAN4TXTSR.Bits.TSR5 +#define CAN4TXTSR_TSR6 _CAN4TXTSR.Bits.TSR6 +#define CAN4TXTSR_TSR7 _CAN4TXTSR.Bits.TSR7 +#define CAN4TXTSR_TSR8 _CAN4TXTSR.Bits.TSR8 +#define CAN4TXTSR_TSR9 _CAN4TXTSR.Bits.TSR9 +#define CAN4TXTSR_TSR10 _CAN4TXTSR.Bits.TSR10 +#define CAN4TXTSR_TSR11 _CAN4TXTSR.Bits.TSR11 +#define CAN4TXTSR_TSR12 _CAN4TXTSR.Bits.TSR12 +#define CAN4TXTSR_TSR13 _CAN4TXTSR.Bits.TSR13 +#define CAN4TXTSR_TSR14 _CAN4TXTSR.Bits.TSR14 +#define CAN4TXTSR_TSR15 _CAN4TXTSR.Bits.TSR15 + +#define CAN4TXTSR_TSR0_MASK 1U +#define CAN4TXTSR_TSR1_MASK 2U +#define CAN4TXTSR_TSR2_MASK 4U +#define CAN4TXTSR_TSR3_MASK 8U +#define CAN4TXTSR_TSR4_MASK 16U +#define CAN4TXTSR_TSR5_MASK 32U +#define CAN4TXTSR_TSR6_MASK 64U +#define CAN4TXTSR_TSR7_MASK 128U +#define CAN4TXTSR_TSR8_MASK 256U +#define CAN4TXTSR_TSR9_MASK 512U +#define CAN4TXTSR_TSR10_MASK 1024U +#define CAN4TXTSR_TSR11_MASK 2048U +#define CAN4TXTSR_TSR12_MASK 4096U +#define CAN4TXTSR_TSR13_MASK 8192U +#define CAN4TXTSR_TSR14_MASK 16384U +#define CAN4TXTSR_TSR15_MASK 32768U + + +/*** BAKEY0 - Backdoor Access Key 0; 0x0000FF00 ***/ +typedef union { + word Word; + struct { + word KEY0 :1; /* Backdoor Access Key bits, bit 0 */ + word KEY1 :1; /* Backdoor Access Key bits, bit 1 */ + word KEY2 :1; /* Backdoor Access Key bits, bit 2 */ + word KEY3 :1; /* Backdoor Access Key bits, bit 3 */ + word KEY4 :1; /* Backdoor Access Key bits, bit 4 */ + word KEY5 :1; /* Backdoor Access Key bits, bit 5 */ + word KEY6 :1; /* Backdoor Access Key bits, bit 6 */ + word KEY7 :1; /* Backdoor Access Key bits, bit 7 */ + word KEY8 :1; /* Backdoor Access Key bits, bit 8 */ + word KEY9 :1; /* Backdoor Access Key bits, bit 9 */ + word KEY10 :1; /* Backdoor Access Key bits, bit 10 */ + word KEY11 :1; /* Backdoor Access Key bits, bit 11 */ + word KEY12 :1; /* Backdoor Access Key bits, bit 12 */ + word KEY13 :1; /* Backdoor Access Key bits, bit 13 */ + word KEY14 :1; /* Backdoor Access Key bits, bit 14 */ + word KEY15 :1; /* Backdoor Access Key bits, bit 15 */ + } Bits; +} BAKEY0STR; +/* Tip for register initialization in the user code: const word BAKEY0_INIT @0x0000FF00 = ; */ +#define _BAKEY0 (*(const BAKEY0STR *)0x0000FF00) +#define BAKEY0 _BAKEY0.Word +#define BAKEY0_KEY0 _BAKEY0.Bits.KEY0 +#define BAKEY0_KEY1 _BAKEY0.Bits.KEY1 +#define BAKEY0_KEY2 _BAKEY0.Bits.KEY2 +#define BAKEY0_KEY3 _BAKEY0.Bits.KEY3 +#define BAKEY0_KEY4 _BAKEY0.Bits.KEY4 +#define BAKEY0_KEY5 _BAKEY0.Bits.KEY5 +#define BAKEY0_KEY6 _BAKEY0.Bits.KEY6 +#define BAKEY0_KEY7 _BAKEY0.Bits.KEY7 +#define BAKEY0_KEY8 _BAKEY0.Bits.KEY8 +#define BAKEY0_KEY9 _BAKEY0.Bits.KEY9 +#define BAKEY0_KEY10 _BAKEY0.Bits.KEY10 +#define BAKEY0_KEY11 _BAKEY0.Bits.KEY11 +#define BAKEY0_KEY12 _BAKEY0.Bits.KEY12 +#define BAKEY0_KEY13 _BAKEY0.Bits.KEY13 +#define BAKEY0_KEY14 _BAKEY0.Bits.KEY14 +#define BAKEY0_KEY15 _BAKEY0.Bits.KEY15 +/* BAKEY_ARR: Access 4 BAKEYx registers in an array */ +#define BAKEY_ARR ((volatile word *) &BAKEY0) + +#define BAKEY0_KEY0_MASK 1U +#define BAKEY0_KEY1_MASK 2U +#define BAKEY0_KEY2_MASK 4U +#define BAKEY0_KEY3_MASK 8U +#define BAKEY0_KEY4_MASK 16U +#define BAKEY0_KEY5_MASK 32U +#define BAKEY0_KEY6_MASK 64U +#define BAKEY0_KEY7_MASK 128U +#define BAKEY0_KEY8_MASK 256U +#define BAKEY0_KEY9_MASK 512U +#define BAKEY0_KEY10_MASK 1024U +#define BAKEY0_KEY11_MASK 2048U +#define BAKEY0_KEY12_MASK 4096U +#define BAKEY0_KEY13_MASK 8192U +#define BAKEY0_KEY14_MASK 16384U +#define BAKEY0_KEY15_MASK 32768U + + +/*** BAKEY1 - Backdoor Access Key 1; 0x0000FF02 ***/ +typedef union { + word Word; + struct { + word KEY0 :1; /* Backdoor Access Key bits, bit 0 */ + word KEY1 :1; /* Backdoor Access Key bits, bit 1 */ + word KEY2 :1; /* Backdoor Access Key bits, bit 2 */ + word KEY3 :1; /* Backdoor Access Key bits, bit 3 */ + word KEY4 :1; /* Backdoor Access Key bits, bit 4 */ + word KEY5 :1; /* Backdoor Access Key bits, bit 5 */ + word KEY6 :1; /* Backdoor Access Key bits, bit 6 */ + word KEY7 :1; /* Backdoor Access Key bits, bit 7 */ + word KEY8 :1; /* Backdoor Access Key bits, bit 8 */ + word KEY9 :1; /* Backdoor Access Key bits, bit 9 */ + word KEY10 :1; /* Backdoor Access Key bits, bit 10 */ + word KEY11 :1; /* Backdoor Access Key bits, bit 11 */ + word KEY12 :1; /* Backdoor Access Key bits, bit 12 */ + word KEY13 :1; /* Backdoor Access Key bits, bit 13 */ + word KEY14 :1; /* Backdoor Access Key bits, bit 14 */ + word KEY15 :1; /* Backdoor Access Key bits, bit 15 */ + } Bits; +} BAKEY1STR; +/* Tip for register initialization in the user code: const word BAKEY1_INIT @0x0000FF02 = ; */ +#define _BAKEY1 (*(const BAKEY1STR *)0x0000FF02) +#define BAKEY1 _BAKEY1.Word +#define BAKEY1_KEY0 _BAKEY1.Bits.KEY0 +#define BAKEY1_KEY1 _BAKEY1.Bits.KEY1 +#define BAKEY1_KEY2 _BAKEY1.Bits.KEY2 +#define BAKEY1_KEY3 _BAKEY1.Bits.KEY3 +#define BAKEY1_KEY4 _BAKEY1.Bits.KEY4 +#define BAKEY1_KEY5 _BAKEY1.Bits.KEY5 +#define BAKEY1_KEY6 _BAKEY1.Bits.KEY6 +#define BAKEY1_KEY7 _BAKEY1.Bits.KEY7 +#define BAKEY1_KEY8 _BAKEY1.Bits.KEY8 +#define BAKEY1_KEY9 _BAKEY1.Bits.KEY9 +#define BAKEY1_KEY10 _BAKEY1.Bits.KEY10 +#define BAKEY1_KEY11 _BAKEY1.Bits.KEY11 +#define BAKEY1_KEY12 _BAKEY1.Bits.KEY12 +#define BAKEY1_KEY13 _BAKEY1.Bits.KEY13 +#define BAKEY1_KEY14 _BAKEY1.Bits.KEY14 +#define BAKEY1_KEY15 _BAKEY1.Bits.KEY15 + +#define BAKEY1_KEY0_MASK 1U +#define BAKEY1_KEY1_MASK 2U +#define BAKEY1_KEY2_MASK 4U +#define BAKEY1_KEY3_MASK 8U +#define BAKEY1_KEY4_MASK 16U +#define BAKEY1_KEY5_MASK 32U +#define BAKEY1_KEY6_MASK 64U +#define BAKEY1_KEY7_MASK 128U +#define BAKEY1_KEY8_MASK 256U +#define BAKEY1_KEY9_MASK 512U +#define BAKEY1_KEY10_MASK 1024U +#define BAKEY1_KEY11_MASK 2048U +#define BAKEY1_KEY12_MASK 4096U +#define BAKEY1_KEY13_MASK 8192U +#define BAKEY1_KEY14_MASK 16384U +#define BAKEY1_KEY15_MASK 32768U + + +/*** BAKEY2 - Backdoor Access Key 2; 0x0000FF04 ***/ +typedef union { + word Word; + struct { + word KEY0 :1; /* Backdoor Access Key bits, bit 0 */ + word KEY1 :1; /* Backdoor Access Key bits, bit 1 */ + word KEY2 :1; /* Backdoor Access Key bits, bit 2 */ + word KEY3 :1; /* Backdoor Access Key bits, bit 3 */ + word KEY4 :1; /* Backdoor Access Key bits, bit 4 */ + word KEY5 :1; /* Backdoor Access Key bits, bit 5 */ + word KEY6 :1; /* Backdoor Access Key bits, bit 6 */ + word KEY7 :1; /* Backdoor Access Key bits, bit 7 */ + word KEY8 :1; /* Backdoor Access Key bits, bit 8 */ + word KEY9 :1; /* Backdoor Access Key bits, bit 9 */ + word KEY10 :1; /* Backdoor Access Key bits, bit 10 */ + word KEY11 :1; /* Backdoor Access Key bits, bit 11 */ + word KEY12 :1; /* Backdoor Access Key bits, bit 12 */ + word KEY13 :1; /* Backdoor Access Key bits, bit 13 */ + word KEY14 :1; /* Backdoor Access Key bits, bit 14 */ + word KEY15 :1; /* Backdoor Access Key bits, bit 15 */ + } Bits; +} BAKEY2STR; +/* Tip for register initialization in the user code: const word BAKEY2_INIT @0x0000FF04 = ; */ +#define _BAKEY2 (*(const BAKEY2STR *)0x0000FF04) +#define BAKEY2 _BAKEY2.Word +#define BAKEY2_KEY0 _BAKEY2.Bits.KEY0 +#define BAKEY2_KEY1 _BAKEY2.Bits.KEY1 +#define BAKEY2_KEY2 _BAKEY2.Bits.KEY2 +#define BAKEY2_KEY3 _BAKEY2.Bits.KEY3 +#define BAKEY2_KEY4 _BAKEY2.Bits.KEY4 +#define BAKEY2_KEY5 _BAKEY2.Bits.KEY5 +#define BAKEY2_KEY6 _BAKEY2.Bits.KEY6 +#define BAKEY2_KEY7 _BAKEY2.Bits.KEY7 +#define BAKEY2_KEY8 _BAKEY2.Bits.KEY8 +#define BAKEY2_KEY9 _BAKEY2.Bits.KEY9 +#define BAKEY2_KEY10 _BAKEY2.Bits.KEY10 +#define BAKEY2_KEY11 _BAKEY2.Bits.KEY11 +#define BAKEY2_KEY12 _BAKEY2.Bits.KEY12 +#define BAKEY2_KEY13 _BAKEY2.Bits.KEY13 +#define BAKEY2_KEY14 _BAKEY2.Bits.KEY14 +#define BAKEY2_KEY15 _BAKEY2.Bits.KEY15 + +#define BAKEY2_KEY0_MASK 1U +#define BAKEY2_KEY1_MASK 2U +#define BAKEY2_KEY2_MASK 4U +#define BAKEY2_KEY3_MASK 8U +#define BAKEY2_KEY4_MASK 16U +#define BAKEY2_KEY5_MASK 32U +#define BAKEY2_KEY6_MASK 64U +#define BAKEY2_KEY7_MASK 128U +#define BAKEY2_KEY8_MASK 256U +#define BAKEY2_KEY9_MASK 512U +#define BAKEY2_KEY10_MASK 1024U +#define BAKEY2_KEY11_MASK 2048U +#define BAKEY2_KEY12_MASK 4096U +#define BAKEY2_KEY13_MASK 8192U +#define BAKEY2_KEY14_MASK 16384U +#define BAKEY2_KEY15_MASK 32768U + + +/*** BAKEY3 - Backdoor Access Key 3; 0x0000FF06 ***/ +typedef union { + word Word; + struct { + word KEY0 :1; /* Backdoor Access Key bits, bit 0 */ + word KEY1 :1; /* Backdoor Access Key bits, bit 1 */ + word KEY2 :1; /* Backdoor Access Key bits, bit 2 */ + word KEY3 :1; /* Backdoor Access Key bits, bit 3 */ + word KEY4 :1; /* Backdoor Access Key bits, bit 4 */ + word KEY5 :1; /* Backdoor Access Key bits, bit 5 */ + word KEY6 :1; /* Backdoor Access Key bits, bit 6 */ + word KEY7 :1; /* Backdoor Access Key bits, bit 7 */ + word KEY8 :1; /* Backdoor Access Key bits, bit 8 */ + word KEY9 :1; /* Backdoor Access Key bits, bit 9 */ + word KEY10 :1; /* Backdoor Access Key bits, bit 10 */ + word KEY11 :1; /* Backdoor Access Key bits, bit 11 */ + word KEY12 :1; /* Backdoor Access Key bits, bit 12 */ + word KEY13 :1; /* Backdoor Access Key bits, bit 13 */ + word KEY14 :1; /* Backdoor Access Key bits, bit 14 */ + word KEY15 :1; /* Backdoor Access Key bits, bit 15 */ + } Bits; +} BAKEY3STR; +/* Tip for register initialization in the user code: const word BAKEY3_INIT @0x0000FF06 = ; */ +#define _BAKEY3 (*(const BAKEY3STR *)0x0000FF06) +#define BAKEY3 _BAKEY3.Word +#define BAKEY3_KEY0 _BAKEY3.Bits.KEY0 +#define BAKEY3_KEY1 _BAKEY3.Bits.KEY1 +#define BAKEY3_KEY2 _BAKEY3.Bits.KEY2 +#define BAKEY3_KEY3 _BAKEY3.Bits.KEY3 +#define BAKEY3_KEY4 _BAKEY3.Bits.KEY4 +#define BAKEY3_KEY5 _BAKEY3.Bits.KEY5 +#define BAKEY3_KEY6 _BAKEY3.Bits.KEY6 +#define BAKEY3_KEY7 _BAKEY3.Bits.KEY7 +#define BAKEY3_KEY8 _BAKEY3.Bits.KEY8 +#define BAKEY3_KEY9 _BAKEY3.Bits.KEY9 +#define BAKEY3_KEY10 _BAKEY3.Bits.KEY10 +#define BAKEY3_KEY11 _BAKEY3.Bits.KEY11 +#define BAKEY3_KEY12 _BAKEY3.Bits.KEY12 +#define BAKEY3_KEY13 _BAKEY3.Bits.KEY13 +#define BAKEY3_KEY14 _BAKEY3.Bits.KEY14 +#define BAKEY3_KEY15 _BAKEY3.Bits.KEY15 + +#define BAKEY3_KEY0_MASK 1U +#define BAKEY3_KEY1_MASK 2U +#define BAKEY3_KEY2_MASK 4U +#define BAKEY3_KEY3_MASK 8U +#define BAKEY3_KEY4_MASK 16U +#define BAKEY3_KEY5_MASK 32U +#define BAKEY3_KEY6_MASK 64U +#define BAKEY3_KEY7_MASK 128U +#define BAKEY3_KEY8_MASK 256U +#define BAKEY3_KEY9_MASK 512U +#define BAKEY3_KEY10_MASK 1024U +#define BAKEY3_KEY11_MASK 2048U +#define BAKEY3_KEY12_MASK 4096U +#define BAKEY3_KEY13_MASK 8192U +#define BAKEY3_KEY14_MASK 16384U +#define BAKEY3_KEY15_MASK 32768U + + +/*** NVFPROT3 - Non volatile Block 3 Flash Protection Register; 0x0000FF0A ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} NVFPROT3STR; +/* Tip for register initialization in the user code: const byte NVFPROT3_INIT @0x0000FF0A = ; */ +#define _NVFPROT3 (*(const NVFPROT3STR *)0x0000FF0A) +#define NVFPROT3 _NVFPROT3.Byte +#define NVFPROT3_FPLS0 _NVFPROT3.Bits.FPLS0 +#define NVFPROT3_FPLS1 _NVFPROT3.Bits.FPLS1 +#define NVFPROT3_FPLDIS _NVFPROT3.Bits.FPLDIS +#define NVFPROT3_FPHS0 _NVFPROT3.Bits.FPHS0 +#define NVFPROT3_FPHS1 _NVFPROT3.Bits.FPHS1 +#define NVFPROT3_FPHDIS _NVFPROT3.Bits.FPHDIS +#define NVFPROT3_NV6 _NVFPROT3.Bits.NV6 +#define NVFPROT3_FPOPEN _NVFPROT3.Bits.FPOPEN +#define NVFPROT3_FPLS _NVFPROT3.MergedBits.grpFPLS +#define NVFPROT3_FPHS _NVFPROT3.MergedBits.grpFPHS + +#define NVFPROT3_FPLS0_MASK 1U +#define NVFPROT3_FPLS1_MASK 2U +#define NVFPROT3_FPLDIS_MASK 4U +#define NVFPROT3_FPHS0_MASK 8U +#define NVFPROT3_FPHS1_MASK 16U +#define NVFPROT3_FPHDIS_MASK 32U +#define NVFPROT3_NV6_MASK 64U +#define NVFPROT3_FPOPEN_MASK 128U +#define NVFPROT3_FPLS_MASK 3U +#define NVFPROT3_FPLS_BITNUM 0U +#define NVFPROT3_FPHS_MASK 24U +#define NVFPROT3_FPHS_BITNUM 3U + + +/*** NVFPROT2 - Non volatile Block 2 Flash Protection Register; 0x0000FF0B ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} NVFPROT2STR; +/* Tip for register initialization in the user code: const byte NVFPROT2_INIT @0x0000FF0B = ; */ +#define _NVFPROT2 (*(const NVFPROT2STR *)0x0000FF0B) +#define NVFPROT2 _NVFPROT2.Byte +#define NVFPROT2_FPLS0 _NVFPROT2.Bits.FPLS0 +#define NVFPROT2_FPLS1 _NVFPROT2.Bits.FPLS1 +#define NVFPROT2_FPLDIS _NVFPROT2.Bits.FPLDIS +#define NVFPROT2_FPHS0 _NVFPROT2.Bits.FPHS0 +#define NVFPROT2_FPHS1 _NVFPROT2.Bits.FPHS1 +#define NVFPROT2_FPHDIS _NVFPROT2.Bits.FPHDIS +#define NVFPROT2_NV6 _NVFPROT2.Bits.NV6 +#define NVFPROT2_FPOPEN _NVFPROT2.Bits.FPOPEN +#define NVFPROT2_FPLS _NVFPROT2.MergedBits.grpFPLS +#define NVFPROT2_FPHS _NVFPROT2.MergedBits.grpFPHS + +#define NVFPROT2_FPLS0_MASK 1U +#define NVFPROT2_FPLS1_MASK 2U +#define NVFPROT2_FPLDIS_MASK 4U +#define NVFPROT2_FPHS0_MASK 8U +#define NVFPROT2_FPHS1_MASK 16U +#define NVFPROT2_FPHDIS_MASK 32U +#define NVFPROT2_NV6_MASK 64U +#define NVFPROT2_FPOPEN_MASK 128U +#define NVFPROT2_FPLS_MASK 3U +#define NVFPROT2_FPLS_BITNUM 0U +#define NVFPROT2_FPHS_MASK 24U +#define NVFPROT2_FPHS_BITNUM 3U + + +/*** NVFPROT1 - Non volatile Block 1 Flash Protection Register; 0x0000FF0C ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} NVFPROT1STR; +/* Tip for register initialization in the user code: const byte NVFPROT1_INIT @0x0000FF0C = ; */ +#define _NVFPROT1 (*(const NVFPROT1STR *)0x0000FF0C) +#define NVFPROT1 _NVFPROT1.Byte +#define NVFPROT1_FPLS0 _NVFPROT1.Bits.FPLS0 +#define NVFPROT1_FPLS1 _NVFPROT1.Bits.FPLS1 +#define NVFPROT1_FPLDIS _NVFPROT1.Bits.FPLDIS +#define NVFPROT1_FPHS0 _NVFPROT1.Bits.FPHS0 +#define NVFPROT1_FPHS1 _NVFPROT1.Bits.FPHS1 +#define NVFPROT1_FPHDIS _NVFPROT1.Bits.FPHDIS +#define NVFPROT1_NV6 _NVFPROT1.Bits.NV6 +#define NVFPROT1_FPOPEN _NVFPROT1.Bits.FPOPEN +#define NVFPROT1_FPLS _NVFPROT1.MergedBits.grpFPLS +#define NVFPROT1_FPHS _NVFPROT1.MergedBits.grpFPHS + +#define NVFPROT1_FPLS0_MASK 1U +#define NVFPROT1_FPLS1_MASK 2U +#define NVFPROT1_FPLDIS_MASK 4U +#define NVFPROT1_FPHS0_MASK 8U +#define NVFPROT1_FPHS1_MASK 16U +#define NVFPROT1_FPHDIS_MASK 32U +#define NVFPROT1_NV6_MASK 64U +#define NVFPROT1_FPOPEN_MASK 128U +#define NVFPROT1_FPLS_MASK 3U +#define NVFPROT1_FPLS_BITNUM 0U +#define NVFPROT1_FPHS_MASK 24U +#define NVFPROT1_FPHS_BITNUM 3U + + +/*** NVFPROT0 - Non volatile Block 0 Flash Protection Register; 0x0000FF0D ***/ +typedef union { + byte Byte; + struct { + byte FPLS0 :1; /* Flash Protection Lower Address size 0 */ + byte FPLS1 :1; /* Flash Protection Lower Address size 1 */ + byte FPLDIS :1; /* Flash Protection Lower address range disable */ + byte FPHS0 :1; /* Flash Protection Higher address size 0 */ + byte FPHS1 :1; /* Flash Protection Higher address size 1 */ + byte FPHDIS :1; /* Flash Protection Higher address range disable */ + byte NV6 :1; /* Non Volatile Flag Bit */ + byte FPOPEN :1; /* Opens the flash block or subsections of it for program or erase */ + } Bits; + struct { + byte grpFPLS :2; + byte :1; + byte grpFPHS :2; + byte :1; + byte grpNV_6 :1; + byte :1; + } MergedBits; +} NVFPROT0STR; +/* Tip for register initialization in the user code: const byte NVFPROT0_INIT @0x0000FF0D = ; */ +#define _NVFPROT0 (*(const NVFPROT0STR *)0x0000FF0D) +#define NVFPROT0 _NVFPROT0.Byte +#define NVFPROT0_FPLS0 _NVFPROT0.Bits.FPLS0 +#define NVFPROT0_FPLS1 _NVFPROT0.Bits.FPLS1 +#define NVFPROT0_FPLDIS _NVFPROT0.Bits.FPLDIS +#define NVFPROT0_FPHS0 _NVFPROT0.Bits.FPHS0 +#define NVFPROT0_FPHS1 _NVFPROT0.Bits.FPHS1 +#define NVFPROT0_FPHDIS _NVFPROT0.Bits.FPHDIS +#define NVFPROT0_NV6 _NVFPROT0.Bits.NV6 +#define NVFPROT0_FPOPEN _NVFPROT0.Bits.FPOPEN +#define NVFPROT0_FPLS _NVFPROT0.MergedBits.grpFPLS +#define NVFPROT0_FPHS _NVFPROT0.MergedBits.grpFPHS + +#define NVFPROT0_FPLS0_MASK 1U +#define NVFPROT0_FPLS1_MASK 2U +#define NVFPROT0_FPLDIS_MASK 4U +#define NVFPROT0_FPHS0_MASK 8U +#define NVFPROT0_FPHS1_MASK 16U +#define NVFPROT0_FPHDIS_MASK 32U +#define NVFPROT0_NV6_MASK 64U +#define NVFPROT0_FPOPEN_MASK 128U +#define NVFPROT0_FPLS_MASK 3U +#define NVFPROT0_FPLS_BITNUM 0U +#define NVFPROT0_FPHS_MASK 24U +#define NVFPROT0_FPHS_BITNUM 3U + + +/*** NVFSEC - Non volatile Flash Security Register; 0x0000FF0F ***/ +typedef union { + byte Byte; + struct { + byte SEC0 :1; /* Memory security bit 0 */ + byte SEC1 :1; /* Memory security bit 1 */ + byte NV2 :1; /* Non Volatile flag bit 2 */ + byte NV3 :1; /* Non Volatile flag bit 3 */ + byte NV4 :1; /* Non Volatile flag bit 4 */ + byte NV5 :1; /* Non Volatile flag bit 5 */ + byte KEYEN0 :1; /* Backdoor Key Security Enable Bit 0 */ + byte KEYEN1 :1; /* Backdoor Key Security Enable Bit 1 */ + } Bits; + struct { + byte grpSEC :2; + byte grpNV_2 :4; + byte grpKEYEN :2; + } MergedBits; +} NVFSECSTR; +/* Tip for register initialization in the user code: const byte NVFSEC_INIT @0x0000FF0F = ; */ +#define _NVFSEC (*(const NVFSECSTR *)0x0000FF0F) +#define NVFSEC _NVFSEC.Byte +#define NVFSEC_SEC0 _NVFSEC.Bits.SEC0 +#define NVFSEC_SEC1 _NVFSEC.Bits.SEC1 +#define NVFSEC_NV2 _NVFSEC.Bits.NV2 +#define NVFSEC_NV3 _NVFSEC.Bits.NV3 +#define NVFSEC_NV4 _NVFSEC.Bits.NV4 +#define NVFSEC_NV5 _NVFSEC.Bits.NV5 +#define NVFSEC_KEYEN0 _NVFSEC.Bits.KEYEN0 +#define NVFSEC_KEYEN1 _NVFSEC.Bits.KEYEN1 +#define NVFSEC_SEC _NVFSEC.MergedBits.grpSEC +#define NVFSEC_NV_2 _NVFSEC.MergedBits.grpNV_2 +#define NVFSEC_KEYEN _NVFSEC.MergedBits.grpKEYEN +#define NVFSEC_NV NVFSEC_NV_2 + +#define NVFSEC_SEC0_MASK 1U +#define NVFSEC_SEC1_MASK 2U +#define NVFSEC_NV2_MASK 4U +#define NVFSEC_NV3_MASK 8U +#define NVFSEC_NV4_MASK 16U +#define NVFSEC_NV5_MASK 32U +#define NVFSEC_KEYEN0_MASK 64U +#define NVFSEC_KEYEN1_MASK 128U +#define NVFSEC_SEC_MASK 3U +#define NVFSEC_SEC_BITNUM 0U +#define NVFSEC_NV_2_MASK 60U +#define NVFSEC_NV_2_BITNUM 2U +#define NVFSEC_KEYEN_MASK 192U +#define NVFSEC_KEYEN_BITNUM 6U + + + /* Watchdog reset macro */ +#ifndef __RESET_WATCHDOG +#ifdef _lint + #define __RESET_WATCHDOG() /* empty */ +#else + #define __RESET_WATCHDOG() (void)(ARMCOP = 0x55U, ARMCOP = 0xAAU) +#endif +#endif /* __RESET_WATCHDOG */ + + +/***********************************************/ +/** D E P R E C I A T E D S Y M B O L S **/ +/***********************************************/ +/* --------------------------------------------------------------------------- */ +/* The following symbols were removed, because they were invalid or irrelevant */ +/* --------------------------------------------------------------------------- */ +#define MCCNTlo_BIT0 This_symb_has_been_depreciated +#define MCCNTlo_BIT1 This_symb_has_been_depreciated +#define MCCNTlo_BIT2 This_symb_has_been_depreciated +#define MCCNTlo_BIT3 This_symb_has_been_depreciated +#define MCCNTlo_BIT4 This_symb_has_been_depreciated +#define MCCNTlo_BIT5 This_symb_has_been_depreciated +#define MCCNTlo_BIT6 This_symb_has_been_depreciated +#define MCCNTlo_BIT7 This_symb_has_been_depreciated +#define MCCNThi_BIT8 This_symb_has_been_depreciated +#define MCCNThi_BIT9 This_symb_has_been_depreciated +#define MCCNThi_BIT10 This_symb_has_been_depreciated +#define MCCNThi_BIT11 This_symb_has_been_depreciated +#define MCCNThi_BIT12 This_symb_has_been_depreciated +#define MCCNThi_BIT13 This_symb_has_been_depreciated +#define MCCNThi_BIT14 This_symb_has_been_depreciated +#define MCCNThi_BIT15 This_symb_has_been_depreciated +#define MCCNTlo_BIT0_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT1_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT2_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT3_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT4_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT5_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT6_MASK This_symb_has_been_depreciated +#define MCCNTlo_BIT7_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT8_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT9_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT10_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT11_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT12_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT13_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT14_MASK This_symb_has_been_depreciated +#define MCCNThi_BIT15_MASK This_symb_has_been_depreciated + + +#ifndef __V30COMPATIBLE__ +#pragma OPTION DEL V30toV31Compatible +#endif +/*lint -restore +esym(961,18.4) +esym(961,19.7) Enable MISRA rule (1.1,18.4,6.4,19.7) checking. */ + +#endif diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/main.c b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/main.c new file mode 100644 index 00000000..1735d6c7 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/main.c @@ -0,0 +1,86 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\main.c +* \brief Demo program application source file. +* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static void Init(void); + + +/************************************************************************************//** +** \brief This is the entry point for the bootloader application and is called +** by the reset interrupt vector after the C-startup routines executed. +** \return none. +** +****************************************************************************************/ +void main(void) +{ + /* initialize the microcontroller */ + Init(); + /* initialize the bootloader interface */ + BootComInit(); + + /* start the infinite program loop */ + while (1) + { + /* toggle LED with a fixed frequency */ + LedToggle(); + /* check for bootloader activation request */ + BootComCheckActivationRequest(); + } +} /*** end of main ***/ + + +/************************************************************************************//** +** \brief Initializes the microcontroller. +** \return none. +** +****************************************************************************************/ +static void Init(void) +{ + /* init the led driver */ + LedInit(); + /* init the timer driver */ + TimeInit(); + /* enable IRQ's, because they were initially disabled by the bootloader */ + IrqInterruptEnable(); +} /*** end of Init ***/ + + +/*********************************** end of main.c *************************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/memory.x b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/memory.x new file mode 100644 index 00000000..c9bb2e58 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/memory.x @@ -0,0 +1,65 @@ +/* This is a linker parameter file for the MC9S12DG256B */ +NAMES END /* CodeWarrior will pass all the needed files to the linker by command line. But here you may add your own files too. */ + +SEGMENTS /* Here all RAM/ROM areas of the device are listed. Used in PLACEMENT below. */ + +/* Register space */ +/* IO_SEG = PAGED 0x0000 TO 0x03FF; intentionally not defined */ + +/* EPROM */ + EEPROM = READ_ONLY 0x0400 TO 0x0FEF; + +/* RAM */ + RAM = READ_WRITE 0x1000 TO 0x3FFF; + +/* non-paged FLASHs */ + ROM_4000 = READ_ONLY 0x4000 TO 0x7FFF; + ROM_C000 = READ_ONLY 0xC000 TO 0xE7FF; /* last part reserved for OpenBLT */ + +/* paged FLASH: 0x8000 TO 0xBFFF; addressed through PPAGE */ + PAGE_30 = READ_ONLY 0x308000 TO 0x30BFFF; + PAGE_31 = READ_ONLY 0x318000 TO 0x31BFFF; + PAGE_32 = READ_ONLY 0x328000 TO 0x32BFFF; + PAGE_33 = READ_ONLY 0x338000 TO 0x33BFFF; + PAGE_34 = READ_ONLY 0x348000 TO 0x34BFFF; + PAGE_35 = READ_ONLY 0x358000 TO 0x35BFFF; + PAGE_36 = READ_ONLY 0x368000 TO 0x36BFFF; + PAGE_37 = READ_ONLY 0x378000 TO 0x37BFFF; + PAGE_38 = READ_ONLY 0x388000 TO 0x38BFFF; + PAGE_39 = READ_ONLY 0x398000 TO 0x39BFFF; + PAGE_3A = READ_ONLY 0x3A8000 TO 0x3ABFFF; + PAGE_3B = READ_ONLY 0x3B8000 TO 0x3BBFFF; + PAGE_3C = READ_ONLY 0x3C8000 TO 0x3CBFFF; + PAGE_3D = READ_ONLY 0x3D8000 TO 0x3DBFFF; +/* PAGE_3E = READ_ONLY 0x3E8000 TO 0x3EBFFF; not used: equivalent to ROM_4000 */ +/* PAGE_3F = READ_ONLY 0x3F8000 TO 0x3FBEFF; not used: equivalent to ROM_C000 */ +END + +PLACEMENT /* here all predefined and user segments are placed into the SEGMENTS defined above. */ + _PRESTART, /* Used in HIWARE format: jump to _Startup at the code start */ + STARTUP, /* startup data structures */ + ROM_VAR, /* constant variables */ + STRINGS, /* string literals */ + VIRTUAL_TABLE_SEGMENT, /* C++ virtual table segment */ + DEFAULT_ROM, NON_BANKED, /* runtime routines which must not be banked */ + COPY /* copy down information: how to initialize variables */ + /* in case you want to use ROM_4000 here as well, make sure + that all files (incl. library files) are compiled with the + option: -OnB=b */ + INTO ROM_C000/*, ROM_4000*/; + + OTHER_ROM INTO PAGE_30, PAGE_31, PAGE_32, PAGE_33, PAGE_34, PAGE_35, PAGE_36, PAGE_37, + PAGE_38, PAGE_39, PAGE_3A, PAGE_3B, PAGE_3C, PAGE_3D ; + + SSTACK, /* allocate stack first to avoid overwriting variables on overflow */ + DEFAULT_RAM INTO RAM; + +END + +ENTRIES /* keep the following unreferenced variables */ + _vectab +END + +STACKSIZE 0x100 + + diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/prog.dox b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/prog.dox new file mode 100644 index 00000000..5927ee7b --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/prog.dox @@ -0,0 +1,7 @@ +/** +\defgroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior User Program +\brief User Program. +\ingroup HCS12_Evbplus_Dragon12p_CodeWarrior +*/ + + diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/start12.c b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/start12.c new file mode 100644 index 00000000..85c5a9d8 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/start12.c @@ -0,0 +1,475 @@ +/***************************************************** + start12.c - standard startup code + The startup code may be optimized to special user requests + ---------------------------------------------------- + Copyright (c) Metrowerks, Basel, Switzerland + All rights reserved + +Note: ROM libraries are not implemented in this startup code +Note: C++ destructors of global objects are NOT yet supported in the HIWARE Object File Format. + To use this feature, please build your application with the ELF object file format. + *****************************************************/ +/* these macros remove some unused fields in the startup descriptor */ +#define __NO_FLAGS_OFFSET /* we do not need the flags field in the startup data descriptor */ +#define __NO_MAIN_OFFSET /* we do not need the main field in the startup data descriptor */ +#define __NO_STACKOFFSET_OFFSET /* we do not need the stackOffset field in the startup data descriptor */ + +/*#define __BANKED_COPY_DOWN : allow to allocate .copy in flash area */ +#if defined(__BANKED_COPY_DOWN) && (!defined(__HCS12X__) || !defined(__ELF_OBJECT_FILE_FORMAT__)) +#error /* the __BANKED_COPY_DOWN switch is only supported for the HCS12X with ELF */ + /* (and not for the HC12, HCS12 or for the HIWARE object file format) */ +#endif + +#include "hidef.h" +#include "start12.h" + +/***************************************************************************/ +/* Macros to control how the startup code handles the COP: */ +/* #define _DO_FEED_COP_ : do feed the COP */ +/* #define _DO_ENABLE_COP_: do enable the COP */ +/* #define _DO_DISABLE_COP_: disable the COP */ +/* Without defining any of these, the startup code does NOT handle the COP */ +/***************************************************************************/ +/* __ONLY_INIT_SP define: */ +/* This define selects an shorter version of the startup code */ +/* which only loads the stack pointer and directly afterwards calls */ +/* main. This version does however NOT initialized global variables */ +/* (So this version is not ANSI compliant!) */ +/***************************************************************************/ +/* __FAR_DATA define: */ +/* By default, the startup code only supports to initialize the default */ +/* kind of memory. If some memory is allocated far in the small or banked */ +/* memory model, then the startup code only supports to initialize this */ +/* memory blocks if __FAR_DATA is defined. If __FAR_DATA is not defined, */ +/* then the linker will issue a message like */ +/* "L1128: Cutting value _Range beg data member from 0xF01000 to 0x1000" */ +/* and this startup code writes to the cutted address */ +/***************************************************************************/ +/* __BANKED_COPY_DOWN define: */ +/* by default, the startup code assumes that the startup data structure */ +/* _startupData, the zero out areas and the .copy section are all */ +/* allocated in NON_BANKED memory. Especially the .copy section can be */ +/* huge if there are many or huge RAM areas to initialize. */ +/* For the HCS12X, which also copies the XGATE RAM located code via .copy */ +/* section, the startup code supports to allocate .copy in a banked flash */ +/* The placement of .copy in the prm file has to be adapted when adding or */ +/* removing the this macro. */ +/* Note: This macro is only supported for the HCS12X and when using ELF */ +/***************************************************************************/ + +#ifdef __cplusplus +#define __EXTERN_C extern "C" +#else +#define __EXTERN_C +#endif + +/*lint -estring(961,"only preprocessor statements and comments before '#include'") , MISRA 19.1 ADV, non_bank.sgm and default.sgm each contain a conditionally compiled CODE_SEG pragma */ + +__EXTERN_C void main(void); /* prototype of main function */ + +#ifndef __ONLY_INIT_SP +#pragma DATA_SEG __NEAR_SEG STARTUP_DATA /* _startupData can be accessed using 16 bit accesses. */ +/* This is needed because it contains the stack top, and without stack, far data cannot be accessed */ +struct _tagStartup _startupData; /* read-only: */ + /* _startupData is allocated in ROM and */ + /* initialized by the linker */ +#pragma DATA_SEG DEFAULT +#endif /* __ONLY_INIT_SP */ + +#if defined(FAR_DATA) && (!defined(__HCS12X__) || defined(__BANKED_COPY_DOWN)) +/*lint -e451 non_bank.sgm contains a conditionally compiled CODE_SEG pragma */ +#include "non_bank.sgm" +/*lint +e451 */ + +/* the init function must be in non banked memory if banked variables are used */ +/* because _SET_PAGE is called, which may change any page register. */ + +/*lint -esym(752,_SET_PAGE) , symbol '_SET_PAGE' is referenced in HLI */ +__EXTERN_C void _SET_PAGE(void); /* the inline assembler needs a prototype */ + /* this is a runtime routine with a special */ + /* calling convention, do not use it in c code! */ +#else +/*lint -e451 default.sgm contains a conditionally compiled CODE_SEG pragma */ +#include "default.sgm" +/*lint +e451 */ +#endif /* defined(FAR_DATA) && (!defined(__HCS12X__) || defined(__BANKED_COPY_DOWN)) */ + + +/* define value and bits for Windef Register */ +#ifdef HC812A4 +#define WINDEF (*(volatile unsigned char*) 0x37) +#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__) +#define __ENABLE_PPAGE__ 0x40 +#else +#define __ENABLE_PPAGE__ 0x0 +#endif +#if defined(__DPAGE__) +#define __ENABLE_DPAGE__ 0x80 +#else +#define __ENABLE_DPAGE__ 0x0 +#endif +#if defined(__EPAGE__) +#define __ENABLE_EPAGE__ 0x20 +#else +#define __ENABLE_EPAGE__ 0x0 +#endif +#endif /* HC812A4 */ + +#define ___INITRM (*(volatile unsigned char *) 0x0010) +#define ___INITRG (*(volatile unsigned char *) 0x0011) +#define ___INITEE (*(volatile unsigned char *) 0x0012) + +#if defined(_DO_FEED_COP_) +#define __FEED_COP_IN_HLI() } asm movb #0x55, _COP_RST_ADR; asm movb #0xAA, _COP_RST_ADR; asm { +#else +#define __FEED_COP_IN_HLI() /* do nothing */ +#endif + +#ifndef __ONLY_INIT_SP +#if (!defined(FAR_DATA) || defined(__HCS12X__)) && (defined( __BANKED__) || defined(__LARGE__) || defined(__BANKED_COPY_DOWN)) +static void __far Init(void) +#else +static void Init(void) +#endif + { +/* purpose: 1) zero out RAM-areas where data is allocated */ +/* 2) copy initialization data from ROM to RAM */ +/* 3) call global constructors in C++ */ +/* called from: _Startup, LibInits */ + asm { +ZeroOut: +#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__) + LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer +#else + LDX _startupData.pZeroOut ; *pZeroOut +#endif + LDY _startupData.nofZeroOuts ; nofZeroOuts + BEQ CopyDown ; if nothing to zero out + +NextZeroOut: PSHY ; save nofZeroOuts +#if defined(FAR_DATA) + LDAB 1,X+ ; load page of destination address + LDY 2,X+ ; load offset of destination address +#if defined(__HCS12X__) + STAB __GPAGE_ADR__ +#else /* defined(__HCS12X__) */ + __PIC_JSR(_SET_PAGE) ; sets the page in the correct page register +#endif /* defined(__HCS12X__) */ +#else /* FAR_DATA */ + LDY 2,X+ ; start address and advance *pZeroOut (X = X+4) +#endif /* FAR_DATA */ + +#if defined(__HCS12X__) && defined(FAR_DATA) + PSHX + LDX 0,X ; byte count +#if defined(__OPTIMIZE_FOR_SIZE__) + CLRA +NextWord: GSTAA 1,Y+ ; clear memory byte + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE X, NextWord ; dec byte count +#else + LDD #0 + LSRX + BEQ LoopClrW1 ; do we copy more than 1 byte? +NextWord: GSTD 2,Y+ ; clear memory word + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE X, NextWord ; dec word count +LoopClrW1: + BCC LastClr ; handle last byte + GSTAA 1,Y+ ; handle last byte +LastClr: +#endif + PULX + LEAX 2,X +#elif defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */ + LDD 2,X+ ; byte count +NextWord: CLR 1,Y+ ; clear memory byte + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D, NextWord ; dec byte count +#else /* __OPTIMIZE_FOR_TIME__ */ + LDD 2,X+ ; byte count + LSRD ; /2 and save bit 0 in the carry + BEQ LoopClrW1 ; do we copy more than 1 byte? + PSHX + LDX #0 +LoopClrW: STX 2,Y+ ; Word-Clear + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D, LoopClrW + PULX +LoopClrW1: + BCC LastClr ; handle last byte + CLR 1,Y+ +LastClr: +#endif /* __OPTIMIZE_FOR_SIZE__/__OPTIMIZE_FOR_TIME__ */ + PULY ; restore nofZeroOuts + DEY ; dec nofZeroOuts + BNE NextZeroOut +CopyDown: +#if defined(__BANKED_COPY_DOWN) + LDAA _startupData.toCopyDownBeg:0 ; get PAGE address of .copy section + STAA __PPAGE_ADR__ ; set PPAGE address + LDX _startupData.toCopyDownBeg:1 ; load address of copy down desc. +#elif defined(__ELF_OBJECT_FILE_FORMAT__) + LDX _startupData.toCopyDownBeg ; load address of copy down desc. +#else + LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc. +#endif +NextBlock: + LDD 2,X+ ; size of init-data -> D + BEQ funcInits ; end of copy down desc. +#ifdef FAR_DATA + PSHD ; save counter + LDAB 1,X+ ; load destination page + LDY 2,X+ ; destination address +#if defined(__HCS12X__) + STAB __GPAGE_ADR__ +#else /* __HCS12X__ */ + __PIC_JSR(_SET_PAGE) ; sets the destinations page register +#endif /* __HCS12X__ */ + PULD ; restore counter +#else /* FAR_DATA */ + LDY 2,X+ ; load destination address +#endif /* FAR_DATA */ + +#if defined(__HCS12X__) && defined(FAR_DATA) +#if defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */ +Copy: PSHA + LDAA 1,X+ + GSTAA 1,Y+ ; move a byte from ROM to the data area + PULA + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-byte loop +#else + LSRD ; /2 and save bit 0 in the carry + BEQ Copy1 ; do we copy more than 1 byte? + +Copy: PSHD + LDD 2,X+ + GSTD 2,Y+ ; move a word from ROM to the data area + PULD + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-word loop +Copy1: + BCC NextBlock ; handle last byte? + LDAA 1,X+ + GSTAA 1,Y+ ; move a byte from ROM to the data area +#endif +#elif defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */ +Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-byte loop +#else /* __OPTIMIZE_FOR_TIME__ */ + LSRD ; /2 and save bit 0 in the carry + BEQ Copy1 ; do we copy more than 1 byte? +Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-word loop +Copy1: + BCC NextBlock ; handle last byte? + MOVB 1,X+,1,Y+ ; copy the last byte +#endif /* __OPTIMIZE_FOR_SIZE__/__OPTIMIZE_FOR_TIME__ */ + BRA NextBlock +funcInits: ; call of global construtors is only in c++ necessary +#if defined(__cplusplus) +#if defined(__ELF_OBJECT_FILE_FORMAT__) +#if defined( __BANKED__) || defined(__LARGE__) + LDY _startupData.nofInitBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.initBodies ; load address of first module to initialize +nextInit: + LEAX 3,X ; increment to next init + PSHX ; save address of next function to initialize + PSHY ; save cpp counter + CALL [-3,X] ; use double indirect call to load the page register also + PULY ; restore cpp counter + PULX ; restore actual address + DEY ; decrement cpp counter + BNE nextInit +#else /* defined( __BANKED__) || defined(__LARGE__) */ + + LDD _startupData.nofInitBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.initBodies ; load address of first module to initialize +nextInit: + LDY 2,X+ ; load address of first module to initialize + PSHD + PSHX ; save actual address + JSR 0,Y ; call initialization function + PULX ; restore actual address + PULD ; restore cpp counter + DBNE D, nextInit +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +#else /* __ELF_OBJECT_FILE_FORMAT__ */ + LDX _startupData.mInits ; load address of first module to initialize +#if defined( __BANKED__) || defined(__LARGE__) +nextInit: LDY 3,X+ ; load address of initialization function + BEQ done ; stop when address == 0 + ; in common environments the offset of a function is never 0, so this test could be avoided +#ifdef __InitFunctionsMayHaveOffset0__ + BRCLR -1,X, done, 0xff ; stop when address == 0 +#endif /* __InitFunctionsMayHaveOffset0__ */ + PSHX ; save address of next function to initialize + CALL [-3,X] ; use double indirect call to load the page register also +#else /* defined( __BANKED__) || defined(__LARGE__) */ +nextInit: + LDY 2,X+ ; load address of first module to initialize + BEQ done ; stop when address of function == 0 + PSHX ; save actual address + JSR 0,Y ; call initialization function +#endif /* defined( __BANKED__) || defined(__LARGE__) */ + PULX ; restore actual address + BRA nextInit +#endif /* __ELF_OBJECT_FILE_FORMAT__ */ +done: +#endif /* __cplusplus */ + } +} +#endif /* __ONLY_INIT_SP */ + +#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) && 0 /* the call to main does not support to return anymore */ + +#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) +static void __far Fini(void) +#else +static void Fini(void) +#endif +{ +/* purpose: 1) call global destructors in C++ */ + asm { +#if defined( __BANKED__) || defined(__LARGE__) + + LDY _startupData.nofFiniBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.finiBodies ; load address of first module to finalize +nextInit2: + LEAX 3,X ; increment to next init + PSHX ; save address of next function to finalize + PSHY ; save cpp counter + CALL [-3,X] ; use double indirect call to load the page register also + PULY ; restore cpp counter + PULX ; restore actual address + DEY ; decrement cpp counter + BNE nextInit2 +#else /* defined( __BANKED__) || defined(__LARGE__) */ + + LDD _startupData.nofFiniBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.finiBodies ; load address of first module to finalize +nextInit2: + LDY 2,X+ ; load address of first module to finalize + PSHD + PSHX ; save actual address + JSR 0,Y ; call finalize function + PULX ; restore actual address + PULD ; restore cpp counter + DBNE D, nextInit2 +#endif /* defined(__BANKED__) || defined(__LARGE__) */ +done:; + } +} +#endif + +/*lint -e451 non_bank.sgm contains a conditionally compiled CODE_SEG pragma */ +#include "non_bank.sgm" +/*lint +e451 */ + +#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */ +#pragma NO_FRAME +#pragma NO_ENTRY +#if !defined(__SMALL__) +#pragma NO_EXIT +#endif + +/* The function _Startup must be called in order to initialize global variables and to call main */ +/* You can adapt this function or call it from your startup code to implement a different startup */ +/* functionality. */ + +/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */ +/* on hardware */ + +/* to set the reset vector several ways are possible : */ +/* 1. define the function with "interrupt 0" as done below in the first case */ +/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */ +/* of course, even more posibilities exists */ +/* the reset vector must be set so that the application has a defined entry point */ + +#if defined(__SET_RESET_VECTOR__) +__EXTERN_C void __interrupt 0 _Startup(void) { +#else +__EXTERN_C void _Startup(void) { +#endif +/* purpose: 1) initialize the stack + 2) initialize the RAM, copy down init data etc (Init) + 3) call main; + parameters: NONE + called from: _PRESTART-code generated by the Linker + or directly referenced by the reset vector */ + + /* initialize the stack pointer */ + /*lint -e{960} , MISRA 14.3 REQ, macro INIT_SP_FROM_STARTUP_DESC() expands to HLI code */ + /*lint -e{522} , MISRA 14.2 REQ, macro INIT_SP_FROM_STARTUP_DESC() expands to HLI code */ + INIT_SP_FROM_STARTUP_DESC(); /* HLI macro definition in hidef.h */ + + ___INITRG = 0x00; /* lock registers block to 0x0000 */ + ___INITRM = 0x39; /* lock Ram to end at 0x3FFF */ + ___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */ + + /* Here user defined code could be inserted, the stack could be used */ +#if defined(_DO_DISABLE_COP_) + _DISABLE_COP(); +#endif + + /* Example : Set up WinDef Register to allow Paging */ +#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */ +#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0) + WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__; +#endif +#endif + +#if (defined(__MAP_RAM__) || defined(__MAP_FLASH__) || defined(__MAP_EXTERNAL__)) && !defined(__DO_SET_MMCTL1__) +#define __DO_SET_MMCTL1__ +#endif + + +#if defined(__DO_SET_MMCTL1__) + /* Set the MMCTL1 byte. Please use for HCS12XE and change the bits according */ + /* to your configuration. */ + /* Note: MMCTL1 is write once therefore please adapt this initialization here. */ + /* This has to be done prior to the call to Init. */ +#define _MMCTL1_ADR (0x00000013) +#define _MMCTL1_BIT_TGMRAMON (1<<7) /* EEE Tag RAM and FTM SCRATCH RAM visible in the memory map */ +#define _MMCTL1_BIT_EEEIFRON (1<<5) /* EEE IFR visible in the memory map */ +#define _MMCTL1_BIT_PGMIFRON (1<<4) /* Program IFR visible in the memory map */ +#define _MMCTL1_BIT_RAMHM (1<<3) /* RAM only in the higher half of the memory map */ +#define _MMCTL1_BIT_EROMON (1<<2) /* Enables emulated Flash or ROM memory in the memory map */ +#define _MMCTL1_BIT_ROMHM (1<<1) /* FLASH or ROM only in higher Half of Memory Map */ +#define _MMCTL1_BIT_ROMON (1<<0) /* Enable FLASH or ROM in the memory map */ + +#define _MMCTL1_SET(value) ((*(volatile unsigned char*)_MMCTL1_ADR)= (value)) + +#if defined(__MAP_FLASH__) + _MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON); +#elif defined(__MAP_EXTERNAL__) + _MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON | _MMCTL1_BIT_ROMHM); +#else /* RAM */ + _MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON | _MMCTL1_BIT_RAMHM | _MMCTL1_BIT_ROMHM); +#endif +#endif + +#ifndef __ONLY_INIT_SP + /*lint -e{522} , MISRA 14.2 REQ, function Init() contains HLI only */ + Init(); /* zero out, copy down, call constructors */ +#endif + + /* Here user defined code could be inserted, all global variables are initilized */ +#if defined(_DO_ENABLE_COP_) + _ENABLE_COP(1); +#endif + + /* call main() */ + main(); +} + +/*lint --e{766} , non_bank.sgm is not a regular header file, it contains a conditionally compiled CODE_SEG pragma */ +/*lint +estring(961,"only preprocessor statements and comments before '#include'") */ +/*lint +e451 */ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/time.c b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/time.c new file mode 100644 index 00000000..addcdcee --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/time.c @@ -0,0 +1,144 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\timer.c +* \brief Timer driver source file. +* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Number of free running timer counts in 1 millisecond. */ +#define TIMER_COUNTS_PER_MS (BOOT_CPU_SYSTEM_SPEED_KHZ) + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Local variable for storing the number of milliseconds that have elapsed since + * startup. + */ +static unsigned long millisecond_counter; + + +/************************************************************************************//** +** \brief Initializes the timer. +** \return none. +** +****************************************************************************************/ +void TimeInit(void) +{ + /* reset the timer configuration. note that this also sets the default prescaler + * to 1, so the free running counter runs at the same speed as the system clock. + */ + TimeDeinit(); + + /* configure timer channel 0 as a 1 millisecond software timer */ + TIOS_IOS0 = 1; + /* make sure timer 0 interrupt flag is cleared */ + TFLG1 = TFLG1_C0F_MASK; + /* generate output compare event in 1 milliseconds from now */ + TC0 = TCNT + TIMER_COUNTS_PER_MS; + /* enable the interrupt for timer channel 0 */ + TIE_C0I = 1; + /* enable the timer subsystem */ + TSCR1_TEN = 1; + /* reset the millisecond counter */ + TimeSet(0); +} /*** end of TimeInit ***/ + + +/************************************************************************************//** +** \brief Stops and disables the timer. +** \return none. +** +****************************************************************************************/ +void TimeDeinit(void) +{ + /* bring the timer subsystem back into its reset state */ + TIE = 0; + TSCR1 = 0; + TSCR2 = 0; + TIOS = 0; + TTOV = 0; + TCTL1 = 0; + TCTL2 = 0; + TCTL3 = 0; + TCTL4 = 0; +} /*** end of TimeDeinit ***/ + + +/************************************************************************************//** +** \brief Sets the initial counter value of the millisecond timer. +** \param timer_value initialize value of the millisecond timer. +** \return none. +** +****************************************************************************************/ +void TimeSet(unsigned long timer_value) +{ + /* set the millisecond counter */ + millisecond_counter = timer_value; +} /*** end of TimeSet ***/ + + +/************************************************************************************//** +** \brief Obtains the counter value of the millisecond timer. +** \return Current value of the millisecond timer. +** +****************************************************************************************/ +unsigned long TimeGet(void) +{ + /* read and return the millisecond counter value */ + return millisecond_counter; +} /*** end of TimeGet ***/ + + +/************************************************************************************//** +** \brief Interrupt service routine of the timer. +** \return none. +** +****************************************************************************************/ +__interrupt void TimeISRHandler(void) +{ + /* make sure timer 0 interrupt flag is cleared */ + TFLG1 = TFLG1_C0F_MASK; + /* generate output compare event in 1 milliseconds from now */ + TC0 += TIMER_COUNTS_PER_MS; + /* increment the millisecond counter */ + millisecond_counter++; +} /*** end of TimeISRHandler ***/ + + +/*********************************** end of time.c *************************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/time.h b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/time.h new file mode 100644 index 00000000..27f848a9 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/time.h @@ -0,0 +1,46 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\timer.h +* \brief Timer driver header file. +* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef TIME_H +#define TIME_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void TimeInit(void); +void TimeDeinit(void); +void TimeSet(unsigned long timer_value); +unsigned long TimeGet(void); +void TimeISRHandler(void); + +#endif /* TIME_H */ +/*********************************** end of time.h *************************************/ diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/vectors.c b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/vectors.c new file mode 100644 index 00000000..9f0e0a94 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/Prog/vectors.c @@ -0,0 +1,150 @@ +/************************************************************************************//** +* \file Demo\HCS12_Evbplus_Dragon12p_CodeWarrior\Prog\vectors.c +* \brief Demo program interrupt vectors source file. +* \ingroup Prog_HCS12_Evbplus_Dragon12p_CodeWarrior +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* External functions +****************************************************************************************/ +extern void near _Startup(void); + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Type for vector table entries. */ +typedef void (*near tIsrFunc)(void); + + +/**************************************************************************************** +** NAME: UnusedISR +** PARAMETER: none +** RETURN VALUE: none +** DESCRIPTION: Catch-all for unused interrrupt service routines. +** +****************************************************************************************/ +__interrupt void UnusedISR(void) +{ + /* unexpected interrupt occured, so halt the system */ + while (1) { ; } +} /*** end of UnusedISR ***/ + + +/**************************************************************************************** +* I N T E R R U P T V E C T O R T A B L E +****************************************************************************************/ +/** \brief Interrupt vector table. + * \details Normally, these are at 0xff80-0xffff, but the bootloader occupies 0xe800 - + * 0xffff. The bootloader expects the vector table to be at the end of user + * program flash, which is 0xe780 - 0xe7ff. 2 more bytes are reserved for the + * checksum that is programmed and verified by the bootloader, so the start + * address ends up being 0xe77e. Note that this needs to be updated when the + * size of the bootloader changes, as defined in the flashLayout[] table in + * flash.c of the bootloader. + */ +const tIsrFunc _vectab[] @0xe77e = +{ + (tIsrFunc)0xaa55, /* Reserved for OpenBLT checksum */ + (tIsrFunc)UnusedISR, /* Reserved 0xFF80 */ + (tIsrFunc)UnusedISR, /* Reserved 0xFF82 */ + (tIsrFunc)UnusedISR, /* Reserved 0xFF84 */ + (tIsrFunc)UnusedISR, /* Reserved 0xFF86 */ + (tIsrFunc)UnusedISR, /* Reserved 0xFF88 */ + (tIsrFunc)UnusedISR, /* Reserved 0xFF8A */ + (tIsrFunc)UnusedISR, /* PWM Emergency Shutdown 0xFF8C */ + (tIsrFunc)UnusedISR, /* PortP Interrupt 0xFF8E */ + (tIsrFunc)UnusedISR, /* MSCAN4 Transmit 0xFF90 */ + (tIsrFunc)UnusedISR, /* MSCAN4 Receive 0xFF92 */ + (tIsrFunc)UnusedISR, /* MSCAN4 Errors 0xFF94 */ + (tIsrFunc)UnusedISR, /* MSCAN4 WakeUp 0xFF96 */ + (tIsrFunc)UnusedISR, /* MSCAN3 Transmit 0xFF98 */ + (tIsrFunc)UnusedISR, /* MSCAN3 Receive 0xFF9A */ + (tIsrFunc)UnusedISR, /* MSCAN3 Errors 0xFF9C */ + (tIsrFunc)UnusedISR, /* MSCAN3 WakeUp 0xFF9E */ + (tIsrFunc)UnusedISR, /* MSCAN2 Transmit 0xFFA0 */ + (tIsrFunc)UnusedISR, /* MSCAN2 Receive 0xFFA2 */ + (tIsrFunc)UnusedISR, /* MSCAN2 Errors 0xFFA4 */ + (tIsrFunc)UnusedISR, /* MSCAN2 WakeUp 0xFFA6 */ + (tIsrFunc)UnusedISR, /* MSCAN1 Transmit 0xFFA8 */ + (tIsrFunc)UnusedISR, /* MSCAN1 Receive 0xFFAA */ + (tIsrFunc)UnusedISR, /* MSCAN1 Errors 0xFFAC */ + (tIsrFunc)UnusedISR, /* MSCAN1 WakeUp 0xFFAE */ + (tIsrFunc)UnusedISR, /* MSCAN0 Transmit 0xFFB0 */ + (tIsrFunc)UnusedISR, /* MSCAN0 Receive 0xFFB2 */ + (tIsrFunc)UnusedISR, /* MSCAN0 Errors 0xFFB4 */ + (tIsrFunc)UnusedISR, /* MSCAN0 WakeUp 0xFFB6 */ + (tIsrFunc)UnusedISR, /* Flash 0xFFB8 */ + (tIsrFunc)UnusedISR, /* Eeprom WakeUp 0xFFBA */ + (tIsrFunc)UnusedISR, /* SPI2 0xFFBC */ + (tIsrFunc)UnusedISR, /* SPI1 0xFFBE */ + (tIsrFunc)UnusedISR, /* IIC Bus 0xFFC0 */ + (tIsrFunc)UnusedISR, /* DLC 0xFFC2 */ + (tIsrFunc)UnusedISR, /* SCME 0xFFC4 */ + (tIsrFunc)UnusedISR, /* CRG Lock 0xFFC6 */ + (tIsrFunc)UnusedISR, /* Pulse AccB Overflow 0xFFC8 */ + (tIsrFunc)UnusedISR, /* Mod Down Cnt Underflow 0xFFCA */ + (tIsrFunc)UnusedISR, /* PortH Interrupt 0xFFCC */ + (tIsrFunc)UnusedISR, /* PortJ Interrupt 0xFFCE */ + (tIsrFunc)UnusedISR, /* ATD1 0xFFD0 */ + (tIsrFunc)UnusedISR, /* ATD0 0xFFD2 */ + (tIsrFunc)UnusedISR, /* SCI1 0xFFD4 */ + (tIsrFunc)UnusedISR, /* SCI0 0xFFD6 */ + (tIsrFunc)UnusedISR, /* SPI0 0xFFD8 */ + (tIsrFunc)UnusedISR, /* Pulse AccA Input Edge 0xFFDA */ + (tIsrFunc)UnusedISR, /* Pulse AccA Overflow 0xFFDC */ + (tIsrFunc)UnusedISR, /* Timer Overflow 0xFFDE */ + (tIsrFunc)UnusedISR, /* Timer 7 0xFFE0 */ + (tIsrFunc)UnusedISR, /* Timer 6 0xFFE2 */ + (tIsrFunc)UnusedISR, /* Timer 5 0xFFE4 */ + (tIsrFunc)UnusedISR, /* Timer 4 0xFFE6 */ + (tIsrFunc)UnusedISR, /* Timer 3 0xFFE8 */ + (tIsrFunc)UnusedISR, /* Timer 2 0xFFEA */ + (tIsrFunc)UnusedISR, /* Timer 1 0xFFEC */ + (tIsrFunc)TimeISRHandler, /* Timer 0 0xFFEE */ + (tIsrFunc)UnusedISR, /* RTI 0xFFF0 */ + (tIsrFunc)UnusedISR, /* IRQ 0xFFF2 */ + (tIsrFunc)UnusedISR, /* XIRQ 0xFFF4 */ + (tIsrFunc)UnusedISR, /* SWI 0xFFF6 */ + (tIsrFunc)UnusedISR, /* Unimpl Instr Trap 0xFFF8 */ + (tIsrFunc)UnusedISR, /* COP Failure Reset 0xFFFA */ + (tIsrFunc)UnusedISR, /* COP Clk Mon Fail 0xFFFC */ + (tIsrFunc)_Startup /* Reset(N/A) 0xFFFE */ +}; +#pragma CODE_SEG DEFAULT +/************************************ end of vectors.c *********************************/ + + diff --git a/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/demo.dox b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/demo.dox new file mode 100644 index 00000000..4422ef96 --- /dev/null +++ b/Target/Demo/HCS12_Evbplus_Dragon12p_CodeWarrior/demo.dox @@ -0,0 +1,8 @@ +/** +\defgroup HCS12_Evbplus_Dragon12p_CodeWarrior Demo for Dragon12-plus/CodeWarrior +\brief Preconfigured programs for the EVBplus Dragon12-plus and the CodeWarrior IDE. +\details Refer to http://feaser.com/openblt/doku.php?id=manual:demos + for detailed getting started instructions. +*/ + + diff --git a/Target/Source/HCS12/CodeWarrior/memory.x b/Target/Source/HCS12/CodeWarrior/memory.x new file mode 100644 index 00000000..9666fc7a --- /dev/null +++ b/Target/Source/HCS12/CodeWarrior/memory.x @@ -0,0 +1,37 @@ +NAMES END /* CodeWarrior will pass all the needed files to the linker by command line. But here you may add your own files too. */ + +SEGMENTS /* Here all RAM/ROM areas of the device are listed. Used in PLACEMENT below. */ + /* RAM */ + RAM = READ_WRITE 0x3800 TO 0x3FFF; + /* non-paged FLASHs */ + ROM_C000 = READ_ONLY 0xe800 TO 0xFEEF; + /* for fixed address reset_connected_handler OpenBLT function */ + ENTRY_SEG = READ_ONLY 0xFEF0 TO 0xFEFF; +END + +PLACEMENT /* here all predefined and user segments are placed into the SEGMENTS defined above. */ + _PRESTART, /* Used in HIWARE format: jump to _Startup at the code start */ + STARTUP, /* startup data structures */ + ROM_VAR, /* constant variables */ + STRINGS, /* string literals */ + VIRTUAL_TABLE_SEGMENT, /* C++ virtual table segment */ + DEFAULT_ROM, NON_BANKED, /* runtime routines which must not be banked */ + COPY /* copy down information: how to initialize variables */ + /* in case you want to use ROM_4000 here as well, make sure + that all files (incl. library files) are compiled with the + option: -OnB=b */ + INTO ROM_C000; + ENTRY INTO ENTRY_SEG; + + SSTACK, /* allocate stack first to avoid overwriting variables on overflow */ + DEFAULT_RAM INTO RAM; +END + +ENTRIES /* keep the following unreferenced variables/functios */ + _vectab + reset_connected_handler +END + +STACKSIZE 0x100 + + diff --git a/Target/Source/HCS12/CodeWarrior/start12.c b/Target/Source/HCS12/CodeWarrior/start12.c new file mode 100644 index 00000000..011badee --- /dev/null +++ b/Target/Source/HCS12/CodeWarrior/start12.c @@ -0,0 +1,485 @@ +/***************************************************** + start12.c - standard startup code + The startup code may be optimized to special user requests + ---------------------------------------------------- + Copyright (c) Metrowerks, Basel, Switzerland + All rights reserved + +Note: ROM libraries are not implemented in this startup code +Note: C++ destructors of global objects are NOT yet supported in the HIWARE Object File Format. + To use this feature, please build your application with the ELF object file format. + *****************************************************/ +/* these macros remove some unused fields in the startup descriptor */ +#define __NO_FLAGS_OFFSET /* we do not need the flags field in the startup data descriptor */ +#define __NO_MAIN_OFFSET /* we do not need the main field in the startup data descriptor */ +#define __NO_STACKOFFSET_OFFSET /* we do not need the stackOffset field in the startup data descriptor */ + +/*#define __BANKED_COPY_DOWN : allow to allocate .copy in flash area */ +#if defined(__BANKED_COPY_DOWN) && (!defined(__HCS12X__) || !defined(__ELF_OBJECT_FILE_FORMAT__)) +#error /* the __BANKED_COPY_DOWN switch is only supported for the HCS12X with ELF */ + /* (and not for the HC12, HCS12 or for the HIWARE object file format) */ +#endif + +#include "hidef.h" +#include "start12.h" + +/***************************************************************************/ +/* Macros to control how the startup code handles the COP: */ +/* #define _DO_FEED_COP_ : do feed the COP */ +/* #define _DO_ENABLE_COP_: do enable the COP */ +/* #define _DO_DISABLE_COP_: disable the COP */ +/* Without defining any of these, the startup code does NOT handle the COP */ +/***************************************************************************/ +/* __ONLY_INIT_SP define: */ +/* This define selects an shorter version of the startup code */ +/* which only loads the stack pointer and directly afterwards calls */ +/* main. This version does however NOT initialized global variables */ +/* (So this version is not ANSI compliant!) */ +/***************************************************************************/ +/* __FAR_DATA define: */ +/* By default, the startup code only supports to initialize the default */ +/* kind of memory. If some memory is allocated far in the small or banked */ +/* memory model, then the startup code only supports to initialize this */ +/* memory blocks if __FAR_DATA is defined. If __FAR_DATA is not defined, */ +/* then the linker will issue a message like */ +/* "L1128: Cutting value _Range beg data member from 0xF01000 to 0x1000" */ +/* and this startup code writes to the cutted address */ +/***************************************************************************/ +/* __BANKED_COPY_DOWN define: */ +/* by default, the startup code assumes that the startup data structure */ +/* _startupData, the zero out areas and the .copy section are all */ +/* allocated in NON_BANKED memory. Especially the .copy section can be */ +/* huge if there are many or huge RAM areas to initialize. */ +/* For the HCS12X, which also copies the XGATE RAM located code via .copy */ +/* section, the startup code supports to allocate .copy in a banked flash */ +/* The placement of .copy in the prm file has to be adapted when adding or */ +/* removing the this macro. */ +/* Note: This macro is only supported for the HCS12X and when using ELF */ +/***************************************************************************/ + +#ifdef __cplusplus +#define __EXTERN_C extern "C" +#else +#define __EXTERN_C +#endif + +/*lint -estring(961,"only preprocessor statements and comments before '#include'") , MISRA 19.1 ADV, non_bank.sgm and default.sgm each contain a conditionally compiled CODE_SEG pragma */ + +__EXTERN_C void main(void); /* prototype of main function */ + +#ifndef __ONLY_INIT_SP +#pragma DATA_SEG __NEAR_SEG STARTUP_DATA /* _startupData can be accessed using 16 bit accesses. */ +/* This is needed because it contains the stack top, and without stack, far data cannot be accessed */ +struct _tagStartup _startupData; /* read-only: */ + /* _startupData is allocated in ROM and */ + /* initialized by the linker */ +#pragma DATA_SEG DEFAULT +#endif /* __ONLY_INIT_SP */ + +#if defined(FAR_DATA) && (!defined(__HCS12X__) || defined(__BANKED_COPY_DOWN)) +/*lint -e451 non_bank.sgm contains a conditionally compiled CODE_SEG pragma */ +#include "non_bank.sgm" +/*lint +e451 */ + +/* the init function must be in non banked memory if banked variables are used */ +/* because _SET_PAGE is called, which may change any page register. */ + +/*lint -esym(752,_SET_PAGE) , symbol '_SET_PAGE' is referenced in HLI */ +__EXTERN_C void _SET_PAGE(void); /* the inline assembler needs a prototype */ + /* this is a runtime routine with a special */ + /* calling convention, do not use it in c code! */ +#else +/*lint -e451 default.sgm contains a conditionally compiled CODE_SEG pragma */ +#include "default.sgm" +/*lint +e451 */ +#endif /* defined(FAR_DATA) && (!defined(__HCS12X__) || defined(__BANKED_COPY_DOWN)) */ + + +/* define value and bits for Windef Register */ +#ifdef HC812A4 +#define WINDEF (*(volatile unsigned char*) 0x37) +#if defined( __BANKED__) || defined(__LARGE__) || defined(__PPAGE__) +#define __ENABLE_PPAGE__ 0x40 +#else +#define __ENABLE_PPAGE__ 0x0 +#endif +#if defined(__DPAGE__) +#define __ENABLE_DPAGE__ 0x80 +#else +#define __ENABLE_DPAGE__ 0x0 +#endif +#if defined(__EPAGE__) +#define __ENABLE_EPAGE__ 0x20 +#else +#define __ENABLE_EPAGE__ 0x0 +#endif +#endif /* HC812A4 */ + +#define ___INITRM (*(volatile unsigned char *) 0x0010) +#define ___INITRG (*(volatile unsigned char *) 0x0011) +#define ___INITEE (*(volatile unsigned char *) 0x0012) + +#if defined(_DO_FEED_COP_) +#define __FEED_COP_IN_HLI() } asm movb #0x55, _COP_RST_ADR; asm movb #0xAA, _COP_RST_ADR; asm { +#else +#define __FEED_COP_IN_HLI() /* do nothing */ +#endif + +#ifndef __ONLY_INIT_SP +#if (!defined(FAR_DATA) || defined(__HCS12X__)) && (defined( __BANKED__) || defined(__LARGE__) || defined(__BANKED_COPY_DOWN)) +static void __far Init(void) +#else +static void Init(void) +#endif + { +/* purpose: 1) zero out RAM-areas where data is allocated */ +/* 2) copy initialization data from ROM to RAM */ +/* 3) call global constructors in C++ */ +/* called from: _Startup, LibInits */ + asm { +ZeroOut: +#if defined(__HIWARE_OBJECT_FILE_FORMAT__) && defined(__LARGE__) + LDX _startupData.pZeroOut:1 ; in the large memory model in the HIWARE format, pZeroOut is a 24 bit pointer +#else + LDX _startupData.pZeroOut ; *pZeroOut +#endif + LDY _startupData.nofZeroOuts ; nofZeroOuts + BEQ CopyDown ; if nothing to zero out + +NextZeroOut: PSHY ; save nofZeroOuts +#if defined(FAR_DATA) + LDAB 1,X+ ; load page of destination address + LDY 2,X+ ; load offset of destination address +#if defined(__HCS12X__) + STAB __GPAGE_ADR__ +#else /* defined(__HCS12X__) */ + __PIC_JSR(_SET_PAGE) ; sets the page in the correct page register +#endif /* defined(__HCS12X__) */ +#else /* FAR_DATA */ + LDY 2,X+ ; start address and advance *pZeroOut (X = X+4) +#endif /* FAR_DATA */ + +#if defined(__HCS12X__) && defined(FAR_DATA) + PSHX + LDX 0,X ; byte count +#if defined(__OPTIMIZE_FOR_SIZE__) + CLRA +NextWord: GSTAA 1,Y+ ; clear memory byte + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE X, NextWord ; dec byte count +#else + LDD #0 + LSRX + BEQ LoopClrW1 ; do we copy more than 1 byte? +NextWord: GSTD 2,Y+ ; clear memory word + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE X, NextWord ; dec word count +LoopClrW1: + BCC LastClr ; handle last byte + GSTAA 1,Y+ ; handle last byte +LastClr: +#endif + PULX + LEAX 2,X +#elif defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */ + LDD 2,X+ ; byte count +NextWord: CLR 1,Y+ ; clear memory byte + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D, NextWord ; dec byte count +#else /* __OPTIMIZE_FOR_TIME__ */ + LDD 2,X+ ; byte count + LSRD ; /2 and save bit 0 in the carry + BEQ LoopClrW1 ; do we copy more than 1 byte? + PSHX + LDX #0 +LoopClrW: STX 2,Y+ ; Word-Clear + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D, LoopClrW + PULX +LoopClrW1: + BCC LastClr ; handle last byte + CLR 1,Y+ +LastClr: +#endif /* __OPTIMIZE_FOR_SIZE__/__OPTIMIZE_FOR_TIME__ */ + PULY ; restore nofZeroOuts + DEY ; dec nofZeroOuts + BNE NextZeroOut +CopyDown: +#if defined(__BANKED_COPY_DOWN) + LDAA _startupData.toCopyDownBeg:0 ; get PAGE address of .copy section + STAA __PPAGE_ADR__ ; set PPAGE address + LDX _startupData.toCopyDownBeg:1 ; load address of copy down desc. +#elif defined(__ELF_OBJECT_FILE_FORMAT__) + LDX _startupData.toCopyDownBeg ; load address of copy down desc. +#else + LDX _startupData.toCopyDownBeg:2 ; load address of copy down desc. +#endif +NextBlock: + LDD 2,X+ ; size of init-data -> D + BEQ funcInits ; end of copy down desc. +#ifdef FAR_DATA + PSHD ; save counter + LDAB 1,X+ ; load destination page + LDY 2,X+ ; destination address +#if defined(__HCS12X__) + STAB __GPAGE_ADR__ +#else /* __HCS12X__ */ + __PIC_JSR(_SET_PAGE) ; sets the destinations page register +#endif /* __HCS12X__ */ + PULD ; restore counter +#else /* FAR_DATA */ + LDY 2,X+ ; load destination address +#endif /* FAR_DATA */ + +#if defined(__HCS12X__) && defined(FAR_DATA) +#if defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */ +Copy: PSHA + LDAA 1,X+ + GSTAA 1,Y+ ; move a byte from ROM to the data area + PULA + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-byte loop +#else + LSRD ; /2 and save bit 0 in the carry + BEQ Copy1 ; do we copy more than 1 byte? + +Copy: PSHD + LDD 2,X+ + GSTD 2,Y+ ; move a word from ROM to the data area + PULD + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-word loop +Copy1: + BCC NextBlock ; handle last byte? + LDAA 1,X+ + GSTAA 1,Y+ ; move a byte from ROM to the data area +#endif +#elif defined(__OPTIMIZE_FOR_SIZE__) /* -os, default */ +Copy: MOVB 1,X+,1,Y+ ; move a byte from ROM to the data area + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-byte loop +#else /* __OPTIMIZE_FOR_TIME__ */ + LSRD ; /2 and save bit 0 in the carry + BEQ Copy1 ; do we copy more than 1 byte? +Copy: MOVW 2,X+,2,Y+ ; move a word from ROM to the data area + __FEED_COP_IN_HLI() ; feed the COP if necessary /*lint !e505 !e522 asm code */ + DBNE D,Copy ; copy-word loop +Copy1: + BCC NextBlock ; handle last byte? + MOVB 1,X+,1,Y+ ; copy the last byte +#endif /* __OPTIMIZE_FOR_SIZE__/__OPTIMIZE_FOR_TIME__ */ + BRA NextBlock +funcInits: ; call of global construtors is only in c++ necessary +#if defined(__cplusplus) +#if defined(__ELF_OBJECT_FILE_FORMAT__) +#if defined( __BANKED__) || defined(__LARGE__) + LDY _startupData.nofInitBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.initBodies ; load address of first module to initialize +nextInit: + LEAX 3,X ; increment to next init + PSHX ; save address of next function to initialize + PSHY ; save cpp counter + CALL [-3,X] ; use double indirect call to load the page register also + PULY ; restore cpp counter + PULX ; restore actual address + DEY ; decrement cpp counter + BNE nextInit +#else /* defined( __BANKED__) || defined(__LARGE__) */ + + LDD _startupData.nofInitBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.initBodies ; load address of first module to initialize +nextInit: + LDY 2,X+ ; load address of first module to initialize + PSHD + PSHX ; save actual address + JSR 0,Y ; call initialization function + PULX ; restore actual address + PULD ; restore cpp counter + DBNE D, nextInit +#endif /* defined( __BANKED__) || defined(__LARGE__) */ +#else /* __ELF_OBJECT_FILE_FORMAT__ */ + LDX _startupData.mInits ; load address of first module to initialize +#if defined( __BANKED__) || defined(__LARGE__) +nextInit: LDY 3,X+ ; load address of initialization function + BEQ done ; stop when address == 0 + ; in common environments the offset of a function is never 0, so this test could be avoided +#ifdef __InitFunctionsMayHaveOffset0__ + BRCLR -1,X, done, 0xff ; stop when address == 0 +#endif /* __InitFunctionsMayHaveOffset0__ */ + PSHX ; save address of next function to initialize + CALL [-3,X] ; use double indirect call to load the page register also +#else /* defined( __BANKED__) || defined(__LARGE__) */ +nextInit: + LDY 2,X+ ; load address of first module to initialize + BEQ done ; stop when address of function == 0 + PSHX ; save actual address + JSR 0,Y ; call initialization function +#endif /* defined( __BANKED__) || defined(__LARGE__) */ + PULX ; restore actual address + BRA nextInit +#endif /* __ELF_OBJECT_FILE_FORMAT__ */ +done: +#endif /* __cplusplus */ + } +} +#endif /* __ONLY_INIT_SP */ + +#if defined( __ELF_OBJECT_FILE_FORMAT__) && defined(__cplusplus ) && 0 /* the call to main does not support to return anymore */ + +#if !defined(FAR_DATA) && (defined( __BANKED__) || defined(__LARGE__)) +static void __far Fini(void) +#else +static void Fini(void) +#endif +{ +/* purpose: 1) call global destructors in C++ */ + asm { +#if defined( __BANKED__) || defined(__LARGE__) + + LDY _startupData.nofFiniBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.finiBodies ; load address of first module to finalize +nextInit2: + LEAX 3,X ; increment to next init + PSHX ; save address of next function to finalize + PSHY ; save cpp counter + CALL [-3,X] ; use double indirect call to load the page register also + PULY ; restore cpp counter + PULX ; restore actual address + DEY ; decrement cpp counter + BNE nextInit2 +#else /* defined( __BANKED__) || defined(__LARGE__) */ + + LDD _startupData.nofFiniBodies; load number of cpp. + BEQ done ; if cppcount == 0, goto done + LDX _startupData.finiBodies ; load address of first module to finalize +nextInit2: + LDY 2,X+ ; load address of first module to finalize + PSHD + PSHX ; save actual address + JSR 0,Y ; call finalize function + PULX ; restore actual address + PULD ; restore cpp counter + DBNE D, nextInit2 +#endif /* defined(__BANKED__) || defined(__LARGE__) */ +done:; + } +} +#endif + +/*lint -e451 non_bank.sgm contains a conditionally compiled CODE_SEG pragma */ +#include "non_bank.sgm" +/*lint +e451 */ + +#pragma MESSAGE DISABLE C12053 /* Stack-pointer change not in debugging-information */ +#pragma NO_FRAME +#pragma NO_ENTRY +#if !defined(__SMALL__) +#pragma NO_EXIT +#endif + +/* The function _Startup must be called in order to initialize global variables and to call main */ +/* You can adapt this function or call it from your startup code to implement a different startup */ +/* functionality. */ + +/* You should also setup the needed IO registers as WINDEF (HC12A4 only) or the COP registers to run */ +/* on hardware */ + +/* to set the reset vector several ways are possible : */ +/* 1. define the function with "interrupt 0" as done below in the first case */ +/* 2. add the following line to your prm file : VECTOR ADDRESS 0xfffe _Startup */ +/* of course, even more posibilities exists */ +/* the reset vector must be set so that the application has a defined entry point */ + +#if defined(__SET_RESET_VECTOR__) +__EXTERN_C void __interrupt 0 _Startup(void) { +#else +__EXTERN_C void _Startup(void) { +#endif +/* purpose: 1) initialize the stack + 2) initialize the RAM, copy down init data etc (Init) + 3) call main; + parameters: NONE + called from: _PRESTART-code generated by the Linker + or directly referenced by the reset vector */ + + /* initialize the stack pointer */ + /*lint -e{960} , MISRA 14.3 REQ, macro INIT_SP_FROM_STARTUP_DESC() expands to HLI code */ + /*lint -e{522} , MISRA 14.2 REQ, macro INIT_SP_FROM_STARTUP_DESC() expands to HLI code */ + /* With OpenBLT this function is not directly called at reset, but called by a custom + * reset handler. For this to work, the stackpointer must be initialized before this + * function is called, otherwise the RTS instruction won't know where to go. + */ + /*INIT_SP_FROM_STARTUP_DESC();*/ /* HLI macro definition in hidef.h */ + + ___INITRG = 0x00; /* lock registers block to 0x0000 */ + ___INITRM = 0x39; /* lock Ram to end at 0x3FFF */ + ___INITEE = 0x09; /* lock EEPROM block to end at 0x0fff */ + + /* Here user defined code could be inserted, the stack could be used */ +#if defined(_DO_DISABLE_COP_) + _DISABLE_COP(); +#endif + + /* Example : Set up WinDef Register to allow Paging */ +#ifdef HC812A4 /* HC12 A4 derivative needs WINDEF to configure which pages are available */ +#if (__ENABLE_EPAGE__ != 0 || __ENABLE_DPAGE__ != 0 || __ENABLE_PPAGE__ != 0) + WINDEF= __ENABLE_EPAGE__ | __ENABLE_DPAGE__ | __ENABLE_PPAGE__; +#endif +#endif + +#if (defined(__MAP_RAM__) || defined(__MAP_FLASH__) || defined(__MAP_EXTERNAL__)) && !defined(__DO_SET_MMCTL1__) +#define __DO_SET_MMCTL1__ +#endif + + +#if defined(__DO_SET_MMCTL1__) + /* Set the MMCTL1 byte. Please use for HCS12XE and change the bits according */ + /* to your configuration. */ + /* Note: MMCTL1 is write once therefore please adapt this initialization here. */ + /* This has to be done prior to the call to Init. */ +#define _MMCTL1_ADR (0x00000013) +#define _MMCTL1_BIT_TGMRAMON (1<<7) /* EEE Tag RAM and FTM SCRATCH RAM visible in the memory map */ +#define _MMCTL1_BIT_EEEIFRON (1<<5) /* EEE IFR visible in the memory map */ +#define _MMCTL1_BIT_PGMIFRON (1<<4) /* Program IFR visible in the memory map */ +#define _MMCTL1_BIT_RAMHM (1<<3) /* RAM only in the higher half of the memory map */ +#define _MMCTL1_BIT_EROMON (1<<2) /* Enables emulated Flash or ROM memory in the memory map */ +#define _MMCTL1_BIT_ROMHM (1<<1) /* FLASH or ROM only in higher Half of Memory Map */ +#define _MMCTL1_BIT_ROMON (1<<0) /* Enable FLASH or ROM in the memory map */ + +#define _MMCTL1_SET(value) ((*(volatile unsigned char*)_MMCTL1_ADR)= (value)) + +#if defined(__MAP_FLASH__) + _MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON); +#elif defined(__MAP_EXTERNAL__) + _MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON | _MMCTL1_BIT_ROMHM); +#else /* RAM */ + _MMCTL1_SET(_MMCTL1_BIT_ROMON | _MMCTL1_BIT_EROMON | _MMCTL1_BIT_RAMHM | _MMCTL1_BIT_ROMHM); +#endif +#endif + +#ifndef __ONLY_INIT_SP + /*lint -e{522} , MISRA 14.2 REQ, function Init() contains HLI only */ + Init(); /* zero out, copy down, call constructors */ +#endif + + /* Here user defined code could be inserted, all global variables are initilized */ +#if defined(_DO_ENABLE_COP_) + _ENABLE_COP(1); +#endif + + /* OpenBLT modifcation: do not call main. instead do this in the reset handler found in + * vectors.c + */ + main(); + /* main(); */ +} + + + + +/*lint --e{766} , non_bank.sgm is not a regular header file, it contains a conditionally compiled CODE_SEG pragma */ +/*lint +estring(961,"only preprocessor statements and comments before '#include'") */ +/*lint +e451 */ diff --git a/Target/Source/HCS12/CodeWarrior/vectors.c b/Target/Source/HCS12/CodeWarrior/vectors.c new file mode 100644 index 00000000..4b0f667d --- /dev/null +++ b/Target/Source/HCS12/CodeWarrior/vectors.c @@ -0,0 +1,1770 @@ +/************************************************************************************//** +* \file Source\HCS12\CodeWarrior\vectors.c +* \brief Bootloader interrupt vector table source file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "hidef.h" +#include "start12.h" + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Start address of the user program's vector table. + * \attention This value must be updated if the memory reserved for the bootloader + * changes. + */ +#define VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR (0xE780) + + +/**************************************************************************************** +* External functions +****************************************************************************************/ +extern void near main(void); + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Type for vector table entries. */ +typedef void (*near tIsrFunc)(void); + + +/************************************************************************************//** +** \brief Wrapper for calling the default reset handler which puts the communication +** module in a disconnected state. +** \return none. +** +****************************************************************************************/ +void reset_handler(void) +{ + /* initialize the stack pointer */ + INIT_SP_FROM_STARTUP_DESC(); + /* perform standard C startup initialiation */ + _Startup(); + /* start the program */ + main(); +} /*** end of reset_handler ***/ + + +/************************************************************************************//** +** \brief Wrapper for calling the reset handler which puts the communication +** module in a connected state. Typically only called from a running user +** program to reactivate the bootloader to perform a remote firmware update. +** \attention This section must be added to the linker command file to force this +** function to always be at the same fixed address. +** SECTIONS +** ENTRY_SEG = READ_ONLY 0xFEF0 TO 0xFEFF; +** END +** PLACEMENT +** ENTRY INTO ENTRY_SEG; +** END +** +** Make sure that the linker does not remove this function because it believes +** it is unused. This can be done in the linker command file: +** ENTRIES +** reset_connected_handler +** END +** \return none. +** +****************************************************************************************/ +#pragma CODE_SEG ENTRY +void reset_connected_handler(void) +{ + /* initialize the stack pointer */ + INIT_SP_FROM_STARTUP_DESC(); + /* perform standard C startup initialiation */ + _Startup(); + /* this part makes the difference with the normal reset_handler */ + ComSetConnectEntryState(); + /* start the program */ + main(); +} /*** end of reset_connected_handler ***/ +#pragma CODE_SEG DEFAULT + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector0_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (0 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector0_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector1_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (1 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector1_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector2_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (2 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector2_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector3_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (3 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector3_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector4_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (4 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector4_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector5_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (5 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector5_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector6_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (6 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector6_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector7_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (7 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector7_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector8_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (8 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector8_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector9_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (9 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector9_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector10_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (10 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector10_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector11_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (11 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector11_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector12_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (12 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector12_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector13_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (13 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector13_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector14_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (14 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector14_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector15_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (15 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector15_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector16_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (16 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector16_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector17_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (17 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector17_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector18_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (18 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector18_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector19_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (19 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector19_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector20_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (20 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector20_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector21_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (21 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector21_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector22_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (22 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector22_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector23_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (23 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector23_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector24_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (24 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector24_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector25_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (25 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector25_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector26_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (26 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector26_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector27_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (27 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector27_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector28_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (28 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector28_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector29_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (29 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector29_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector30_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (30 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector30_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector31_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (31 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector31_handler ***/ + + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector32_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (32 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector32_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector33_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (33 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector33_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector34_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (34 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector34_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector35_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (35 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector35_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector36_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (36 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector36_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector37_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (37 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector37_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector38_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (38 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector38_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector39_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (39 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector39_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector40_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (40 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector40_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector41_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (41 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector41_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector42_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (42 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector42_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector43_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (43 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector43_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector44_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (44 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector44_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector45_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (45 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector45_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector46_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (46 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector46_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector47_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (47 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector47_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector48_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (48 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector48_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector49_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (49 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector49_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector50_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (50 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector50_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector51_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (51 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector51_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector52_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (52 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector52_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector53_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (53 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector53_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector54_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (54 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector54_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector55_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (55 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector55_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector56_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (56 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector56_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector57_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (57 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector57_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector58_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (58 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector58_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector59_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (59 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector59_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector60_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (60 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector60_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector61_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (61 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector61_handler ***/ + + +/************************************************************************************//** +** \brief ISR handler for a specific vector index in the interrupt vector table for +** linking the actual interrupts vectors to the one in the user program's +** vector table. +** \return none. +** +****************************************************************************************/ +void Vector62_handler(void) +{ + /* Note that this function is called upon interrupt and therefore all CPU registers + * (excluding the SP) are already backed up on the stack, so we are free to use them. + */ + asm + { + /* Load the address of the user program's ISR into X. */ + LDX (VCT_USER_PROGRAM_VECTOR_TABLE_STARTADDR + (62 * 2)) + /* Jump there. It is important to use the JMP instruction here as opposed to other + * branch instruction, because the JMP instruction does not modify the stack by + * saving a return address for example. + */ + JMP 0,X + } +} /*** end of Vector62_handler ***/ + + +/**************************************************************************************** +* I N T E R R U P T V E C T O R T A B L E +****************************************************************************************/ +/** \brief The interrupt vector table. It contains the reset vector and all other + * interrupts vectors are remapped to the user program vector table. + */ +const tIsrFunc _vectab[] @0xff80 = +{ + (tIsrFunc)Vector0_handler, /* Reserved 0xFF80 */ + (tIsrFunc)Vector1_handler, /* Reserved 0xFF82 */ + (tIsrFunc)Vector2_handler, /* Reserved 0xFF84 */ + (tIsrFunc)Vector3_handler, /* Reserved 0xFF86 */ + (tIsrFunc)Vector4_handler, /* Reserved 0xFF88 */ + (tIsrFunc)Vector5_handler, /* Reserved 0xFF8A */ + (tIsrFunc)Vector6_handler, /* PWM Emergency Shutdown 0xFF8C */ + (tIsrFunc)Vector7_handler, /* PortP Interrupt 0xFF8E */ + (tIsrFunc)Vector8_handler, /* MSCAN4 Transmit 0xFF90 */ + (tIsrFunc)Vector9_handler, /* MSCAN4 Receive 0xFF92 */ + (tIsrFunc)Vector10_handler, /* MSCAN4 Errors 0xFF94 */ + (tIsrFunc)Vector11_handler, /* MSCAN4 WakeUp 0xFF96 */ + (tIsrFunc)Vector12_handler, /* MSCAN3 Transmit 0xFF98 */ + (tIsrFunc)Vector13_handler, /* MSCAN3 Receive 0xFF9A */ + (tIsrFunc)Vector14_handler, /* MSCAN3 Errors 0xFF9C */ + (tIsrFunc)Vector15_handler, /* MSCAN3 WakeUp 0xFF9E */ + (tIsrFunc)Vector16_handler, /* MSCAN2 Transmit 0xFFA0 */ + (tIsrFunc)Vector17_handler, /* MSCAN2 Receive 0xFFA2 */ + (tIsrFunc)Vector18_handler, /* MSCAN2 Errors 0xFFA4 */ + (tIsrFunc)Vector19_handler, /* MSCAN2 WakeUp 0xFFA6 */ + (tIsrFunc)Vector20_handler, /* MSCAN1 Transmit 0xFFA8 */ + (tIsrFunc)Vector21_handler, /* MSCAN1 Receive 0xFFAA */ + (tIsrFunc)Vector22_handler, /* MSCAN1 Errors 0xFFAC */ + (tIsrFunc)Vector23_handler, /* MSCAN1 WakeUp 0xFFAE */ + (tIsrFunc)Vector24_handler, /* MSCAN0 Transmit 0xFFB0 */ + (tIsrFunc)Vector25_handler, /* MSCAN0 Receive 0xFFB2 */ + (tIsrFunc)Vector26_handler, /* MSCAN0 Errors 0xFFB4 */ + (tIsrFunc)Vector27_handler, /* MSCAN0 WakeUp 0xFFB6 */ + (tIsrFunc)Vector28_handler, /* Flash 0xFFB8 */ + (tIsrFunc)Vector29_handler, /* Eeprom WakeUp 0xFFBA */ + (tIsrFunc)Vector30_handler, /* SPI2 0xFFBC */ + (tIsrFunc)Vector31_handler, /* SPI1 0xFFBE */ + (tIsrFunc)Vector32_handler, /* IIC Bus 0xFFC0 */ + (tIsrFunc)Vector33_handler, /* DLC 0xFFC2 */ + (tIsrFunc)Vector34_handler, /* SCME 0xFFC4 */ + (tIsrFunc)Vector35_handler, /* CRG Lock 0xFFC6 */ + (tIsrFunc)Vector36_handler, /* Pulse AccB Overflow 0xFFC8 */ + (tIsrFunc)Vector37_handler, /* Mod Down Cnt Underflow 0xFFCA */ + (tIsrFunc)Vector38_handler, /* PortH Interrupt 0xFFCC */ + (tIsrFunc)Vector39_handler, /* PortJ Interrupt 0xFFCE */ + (tIsrFunc)Vector40_handler, /* ATD1 0xFFD0 */ + (tIsrFunc)Vector41_handler, /* ATD0 0xFFD2 */ + (tIsrFunc)Vector42_handler, /* SCI1 0xFFD4 */ + (tIsrFunc)Vector43_handler, /* SCI0 0xFFD6 */ + (tIsrFunc)Vector44_handler, /* SPI0 0xFFD8 */ + (tIsrFunc)Vector45_handler, /* Pulse AccA Input Edge 0xFFDA */ + (tIsrFunc)Vector46_handler, /* Pulse AccA Overflow 0xFFDC */ + (tIsrFunc)Vector47_handler, /* Timer Overflow 0xFFDE */ + (tIsrFunc)Vector48_handler, /* Timer 7 0xFFE0 */ + (tIsrFunc)Vector49_handler, /* Timer 6 0xFFE2 */ + (tIsrFunc)Vector50_handler, /* Timer 5 0xFFE4 */ + (tIsrFunc)Vector51_handler, /* Timer 4 0xFFE6 */ + (tIsrFunc)Vector52_handler, /* Timer 3 0xFFE8 */ + (tIsrFunc)Vector53_handler, /* Timer 2 0xFFEA */ + (tIsrFunc)Vector54_handler, /* Timer 1 0xFFEC */ + (tIsrFunc)Vector55_handler, /* Timer 0 0xFFEE */ + (tIsrFunc)Vector56_handler, /* RTI 0xFFF0 */ + (tIsrFunc)Vector57_handler, /* IRQ 0xFFF2 */ + (tIsrFunc)Vector58_handler, /* XIRQ 0xFFF4 */ + (tIsrFunc)Vector59_handler, /* SWI 0xFFF6 */ + (tIsrFunc)Vector60_handler, /* Unimpl Instr Trap 0xFFF8 */ + (tIsrFunc)Vector61_handler, /* COP Failure Reset 0xFFFA */ + (tIsrFunc)Vector62_handler, /* COP Clk Mon Fail 0xFFFC */ + (tIsrFunc)reset_handler /* Reset(N/A) 0xFFFE */ +}; +#pragma CODE_SEG DEFAULT +/************************************ end of vectors.c *********************************/ + + diff --git a/Target/Source/HCS12/cpu.c b/Target/Source/HCS12/cpu.c new file mode 100644 index 00000000..5d092a5f --- /dev/null +++ b/Target/Source/HCS12/cpu.c @@ -0,0 +1,144 @@ +/************************************************************************************//** +* \file Source\HCS12\cpu.c +* \brief Bootloader cpu module source file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Start address of the user program. This is the address of the reset vector + * in the user program's vector table. + * \attention This value must be updated if the memory reserved for the bootloader + * changes. + */ +#define CPU_USER_PROGRAM_STARTADDR_PTR (0xE7FE) + + +/**************************************************************************************** +* Hook functions +****************************************************************************************/ +#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0) +extern blt_bool CpuUserProgramStartHook(void); +#endif + + +/**************************************************************************************** +* External functions +****************************************************************************************/ +extern void reset_handler(void); /* implemented in C startup */ + + +/************************************************************************************//** +** \brief Starts the user program, if one is present. In this case this function +** does not return. +** \return none. +** +****************************************************************************************/ +void CpuStartUserProgram(void) +{ + void (*pProgResetHandler)(void); + + /* check if a user program is present by verifying the checksum */ + if (NvmVerifyChecksum() == BLT_FALSE) + { + /* not a valid user program so it cannot be started */ + return; + } + #if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0) + /* invoke callback */ + if (CpuUserProgramStartHook() == BLT_FALSE) + { + /* callback requests the user program to not be started */ + return; + } + #endif + #if (BOOT_COM_ENABLE > 0) + /* release the communication interface */ + ComFree(); + #endif + /* reset the timer */ + TimerReset(); + /* set the address where the bootloader needs to jump to. this is the address of + * the last entry in the user program's vector table. this address points to the + * user program's reset handler. + */ + pProgResetHandler = (void(*)(void))(*((blt_int16u*)CPU_USER_PROGRAM_STARTADDR_PTR)); + /* start the user program by activating its reset interrupt service routine */ + pProgResetHandler(); +} /*** end of CpuStartUserProgram ***/ + + +/************************************************************************************//** +** \brief Copies data from the source to the destination address. +** \param dest Destination address for the data. +** \param src Source address of the data. +** \param len length of the data in bytes. +** \return none. +** +****************************************************************************************/ +void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len) +{ + blt_int8u *from, *to; + + /* set casted pointers */ + from = (blt_int8u *)src; + to = (blt_int8u *)dest; + + /* copy all bytes from source address to destination address */ + while(len-- > 0) + { + /* store byte value from source to destination */ + *to++ = *from++; + /* keep the watchdog happy */ + CopService(); + } +} /*** end of CpuMemCopy ***/ + + +/************************************************************************************//** +** \brief Perform a soft reset of the microcontroller by starting from the reset ISR. +** \return none. +** +****************************************************************************************/ +void CpuReset(void) +{ + /* perform a software reset by calling the reset ISR routine */ + reset_handler(); +} /*** end of CpuReset ***/ + + +/*********************************** end of cpu.c **************************************/ diff --git a/Target/Source/HCS12/cpu.h b/Target/Source/HCS12/cpu.h new file mode 100644 index 00000000..169d9280 --- /dev/null +++ b/Target/Source/HCS12/cpu.h @@ -0,0 +1,46 @@ +/************************************************************************************//** +* \file Source\HCS12\cpu.h +* \brief Bootloader cpu module header file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef CPU_H +#define CPU_H + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void CpuStartUserProgram(void); +void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len); +void CpuReset(void); + + +#endif /* CPU_H */ +/*********************************** end of cpu.h **************************************/ diff --git a/Target/Source/HCS12/flash.c b/Target/Source/HCS12/flash.c new file mode 100644 index 00000000..e5e0dc47 --- /dev/null +++ b/Target/Source/HCS12/flash.c @@ -0,0 +1,975 @@ +/************************************************************************************//** +* \file Source\HCS12\flash.c +* \brief Bootloader flash driver source file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Value for an invalid flash sector. */ +#define FLASH_INVALID_SECTOR_IDX (0xff) +/** \brief Value for an invalid flash address. */ +#define FLASH_INVALID_ADDRESS (0xffffffff) +/** \brief Standard size of a flash block for writing. */ +#define FLASH_WRITE_BLOCK_SIZE (512) +/** \brief Total numbers of sectors in array flashLayout[]. */ +#define FLASH_TOTAL_SECTORS (sizeof(flashLayout)/sizeof(flashLayout[0])) +#define FLASH_LAST_SECTOR_IDX (FLASH_TOTAL_SECTORS-1) +#define FLASH_ERASE_BLOCK_SIZE (512) +/** \brief Offset into the user program's vector table where the checksum is located. */ +#define FLASH_VECTOR_TABLE_CS_OFFSET (0x82) +/** \brief Total size of the vector table, excluding the bootloader specific checksum. */ +#define FLASH_VECTOR_TABLE_SIZE (0x80) +/** \brief Start address of the bootloader programmable flash. */ +#define FLASH_START_ADDRESS (flashLayout[0].sector_start) +/** \brief End address of the bootloader programmable flash. */ +#define FLASH_END_ADDRESS (flashLayout[FLASH_LAST_SECTOR_IDX].sector_start + \ + flashLayout[FLASH_LAST_SECTOR_IDX].sector_size - 1) +/** \brief Size of a flash page on the HCS12. */ +#define FLASH_PAGE_SIZE (0x4000) /* flash page size in bytes */ +/** \brief Physical start address of the HCS12 page window. */ +#define FLASH_PAGE_OFFSET (0x8000) /* physical start addr. of pages */ +/** \brief PPAGE register to select a specific flash page. */ +#define FLASH_PPAGE_REG (*(volatile blt_int8u *)(0x0030)) +/** \brief Base address of the flash related control registers. */ +#define FLASH_REGS_BASE_ADDRESS (0x0100) +/** \brief Macro for accessing the flash related control registers. */ +#define FLASH ((volatile tFlashRegs *)FLASH_REGS_BASE_ADDRESS) +/** \brief Program word flash command. */ +#define FLASH_PROGRAM_WORD_CMD (0x20) +/** \brief Erase sector flash command. */ +#define FLASH_ERASE_SECTOR_CMD (0x40) +#if (BOOT_NVM_SIZE_KB > 256) +/** \brief Number of flash pages in a block. */ +#define FLASH_PAGES_PER_BLOCK (8) +#else +/** \brief Number of flash pages in a block. */ +#define FLASH_PAGES_PER_BLOCK (4) +#endif +/** \brief Bitmask for selecting a block with flash pages. */ +#define FLASH_BLOCK_SEL_MASK (0x03) + + +/**************************************************************************************** +* Register definitions +****************************************************************************************/ +/** \brief FCLKDIV - enable prescaler by 8 bit. */ +#define PRDIV8_BIT (0x40) +/** \brief FSTAT - flash access error bit. */ +#define ACCERR_BIT (0x10) +/** \brief FSTAT - protection violation bit. */ +#define PVIOL_BIT (0x20) +/** \brief FSTAT - command buffer empty flag bit. */ +#define CBEIF_BIT (0x80) +/** \brief FCNFG - command buf. empty irq enable bit. */ +#define CBEIE_BIT (0x80) +/** \brief FCNFG - command complete irg enable bit. */ +#define CCIE_BIT (0x40) +/** \brief FCNFG - enable security key writing bit. */ +#define KEYACC_BIT (0x20) + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Structure type for the flash sectors in the flash layout table. */ +typedef struct +{ + blt_addr sector_start; /**< sector start address */ + blt_int32u sector_size; /**< sector size in bytes */ +} tFlashSector; + +/** \brief Structure type for grouping flash block information. + * \details Programming is done per block of max FLASH_WRITE_BLOCK_SIZE. for this a + * flash block manager is implemented in this driver. this flash block manager + * depends on this flash block info structure. It holds the base address of + * the flash block and the data that should be programmed into the flash + * block. The .base_addr must be a multiple of FLASH_WRITE_BLOCK_SIZE. + */ +typedef struct +{ + blt_addr base_addr; + blt_int8u data[FLASH_WRITE_BLOCK_SIZE]; +} tFlashBlockInfo; + +/** \brief Structure type for the flash control registers. */ +typedef volatile struct +{ + volatile blt_int8u fclkdiv; /**< flash clock devider register */ + volatile blt_int8u fsec; /**< flash security register */ + volatile blt_int8u ftstmod; /**< flash test mode register */ + volatile blt_int8u fcnfg; /**< flash configuration register */ + volatile blt_int8u fprot; /**< flash protection register */ + volatile blt_int8u fstat; /**< flash status register */ + volatile blt_int8u fcmd; /**< flash command register */ +} tFlashRegs; + +/** \brief Pointer type to flash command execution function. */ +typedef void (*pFlashExeCmdFct) (void); + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address); +static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr); +static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address, + blt_int8u *data, blt_int32u len); +static blt_bool FlashWriteBlock(tFlashBlockInfo *block); +static blt_int8u FlashGetLinearAddrByte(blt_addr addr); +static blt_int8u FlashGetPhysPage(blt_addr addr); +static blt_int16u FlashGetPhysAddr(blt_addr addr); +static void FlashExecuteCommand(void); +static blt_bool FlashOperate(blt_int8u cmd, blt_addr addr, blt_int16u data); + + +/**************************************************************************************** +* Local constant declarations +****************************************************************************************/ +/** \brief Array wit the layout of the flash memory. + * \details Also controls what part of the flash memory is reserved for the bootloader. + * If the bootloader size changes, the reserved sectors for the bootloader + * might need adjustment to make sure the bootloader doesn't get overwritten. + * This layout uses linear addresses only. For example, the first address on + * page 0x3F is: 0x3F * 0x4000 (page size) = 0xFC000. Note that page 0x3F is + * where the bootloader also resides and it has been entered as 8 chunks of 2kb. + * This allows flexibility for reserving more/less space for the bootloader in + * case its size changes in the future. + */ +static const tFlashSector flashLayout[] = +{ +#if (BOOT_NVM_SIZE_KB > 512) +#error "BOOT_NVM_SIZE_KB > 512 is currently not supported." +#endif +#if (BOOT_NVM_SIZE_KB >= 512) + { 0x80000, 0x4000 }, /* flash page 0x20 - 16kb */ + { 0x84000, 0x4000 }, /* flash page 0x21 - 16kb */ + { 0x88000, 0x4000 }, /* flash page 0x22 - 16kb */ + { 0x8C000, 0x4000 }, /* flash page 0x23 - 16kb */ + { 0x90000, 0x4000 }, /* flash page 0x24 - 16kb */ + { 0x94000, 0x4000 }, /* flash page 0x25 - 16kb */ + { 0x98000, 0x4000 }, /* flash page 0x26 - 16kb */ + { 0x9C000, 0x4000 }, /* flash page 0x27 - 16kb */ + { 0xA0000, 0x4000 }, /* flash page 0x28 - 16kb */ + { 0xA4000, 0x4000 }, /* flash page 0x29 - 16kb */ + { 0xA8000, 0x4000 }, /* flash page 0x2A - 16kb */ + { 0xAC000, 0x4000 }, /* flash page 0x2B - 16kb */ + { 0xB0000, 0x4000 }, /* flash page 0x2C - 16kb */ + { 0xB4000, 0x4000 }, /* flash page 0x2D - 16kb */ + { 0xB8000, 0x4000 }, /* flash page 0x2E - 16kb */ + { 0xBC000, 0x4000 }, /* flash page 0x2F - 16kb */ +#endif +#if (BOOT_NVM_SIZE_KB >= 256) + { 0xC0000, 0x4000 }, /* flash page 0x30 - 16kb */ + { 0xC4000, 0x4000 }, /* flash page 0x31 - 16kb */ + { 0xC8000, 0x4000 }, /* flash page 0x32 - 16kb */ + { 0xCC000, 0x4000 }, /* flash page 0x33 - 16kb */ + { 0xD0000, 0x4000 }, /* flash page 0x34 - 16kb */ + { 0xD4000, 0x4000 }, /* flash page 0x35 - 16kb */ + { 0xD8000, 0x4000 }, /* flash page 0x36 - 16kb */ + { 0xDC000, 0x4000 }, /* flash page 0x37 - 16kb */ +#endif +#if (BOOT_NVM_SIZE_KB >= 128) + { 0xE0000, 0x4000 }, /* flash page 0x38 - 16kb */ + { 0xE4000, 0x4000 }, /* flash page 0x39 - 16kb */ +#endif +#if (BOOT_NVM_SIZE_KB >= 96) + { 0xE8000, 0x4000 }, /* flash page 0x3A - 16kb */ + { 0xEC000, 0x4000 }, /* flash page 0x3B - 16kb */ +#endif +#if (BOOT_NVM_SIZE_KB >= 64) + { 0xF0000, 0x4000 }, /* flash page 0x3C - 16kb */ + { 0xF4000, 0x4000 }, /* flash page 0x3D - 16kb */ +#endif + { 0xF8000, 0x4000 }, /* flash page 0x3E - 16kb */ + { 0xFC000, 0x0800 }, /* flash page 0x3F - 2kb */ + { 0xFC800, 0x0800 }, /* flash page 0x3F - 2kb */ + { 0xFD000, 0x0800 }, /* flash page 0x3F - 2kb */ + { 0xFD800, 0x0800 }, /* flash page 0x3F - 2kb */ + { 0xFE000, 0x0800 }, /* flash page 0x3F - 2kb */ + /* { 0xFE800, 0x0800 }, flash page 0x3F - reserved for bootloader */ + /* { 0xFF000, 0x0800 }, flash page 0x3F - reserved for bootloader */ + /* { 0xFF800, 0x0800 }, flash page 0x3F - reserved for bootloader */ +}; + +/** \brief Array with executable code for performing flash operations. + * \details This array contains the machine code to perform the actual command on the + * flash device, such as program or erase. the code is compiler and location + * independent. This allows us to copy it to a ram buffer and execute the code + * from ram. This way the flash driver can be located in flash memory without + * running into problems when erasing/programming the same flash block that + * contains the flash driver. the source code for the machine code is as + * follows: + * // launch the command + * FLASH->fstat = CBEIF_BIT; + * // wait at least 4 cycles (per AN2720) + * asm("nop"); + * asm("nop"); + * asm("nop"); + * asm("nop"); + * // wait for command to complete + * while ((FLASH->fstat & CCIF_BIT) != CCIF_BIT); + */ +static const blt_int8u flashExecCmd[] = +{ + /* asm("psha"); backup A */ + 0x36, + /* asm("pshx"); backup X */ + 0x34, + /* asm("ldx #0x100"); load flash register base in X */ + 0xce, 0x01, 0x00, + /* asm("leax 5,x"); point X to FSTAT register */ + 0x1a, 0x05, + /* asm("ldaa #0x80"); load CBEIF mask in A */ + 0x86, 0x80, + /* asm("staa 0,x"); set CBEIF bit in FSTAT to launch the command */ + 0x6a, 0x00, + /* asm("nop"); [4 times] wait at least 4 cycles */ + 0xa7,0xa7, 0xa7, 0xa7, + /* asm("brclr 0,x,#0x40,*"); wait for command completion: CCIF in FSTAT equals 1 */ + 0x0f, 0x00, 0x40, 0xfc, + /* asm("pulx"); restore X */ + 0x30, + /* asm("pula"); restore A */ + 0x32, + /* asm("rts"); return */ + 0x3d +}; + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Local variable with information about the flash block that is currently + * being operated on. + * \details The smallest amount of flash that can be programmed is + * FLASH_WRITE_BLOCK_SIZE. A flash block manager is implemented in this driver + * and stores info in this variable. Whenever new data should be flashed, it + * is first added to a RAM buffer, which is part of this variable. Whenever + * the RAM buffer, which has the size of a flash block, is full or data needs + * to be written to a different block, the contents of the RAM buffer are + * programmed to flash. The flash block manager requires some software + * overhead, yet results is faster flash programming because data is first + * harvested, ideally until there is enough to program an entire flash block, + * before the flash device is actually operated on. + */ +static tFlashBlockInfo blockInfo; + +/** \brief Local variable with information about the flash boot block. + * \details The first block of the user program holds the vector table, which on the + * STM32 is also the where the checksum is written to. Is it likely that + * the vector table is first flashed and then, at the end of the programming + * sequence, the checksum. This means that this flash block need to be written + * to twice. Normally this is not a problem with flash memory, as long as you + * write the same values to those bytes that are not supposed to be changed + * and the locations where you do write to are still in the erased 0xFF state. + * Unfortunately, writing twice to flash this way, does not work reliably on + * all micros. This is why we need to have an extra block, the bootblock, + * placed under the management of the block manager. This way is it possible + * to implement functionality so that the bootblock is only written to once + * at the end of the programming sequence. + */ +static tFlashBlockInfo bootBlockInfo; + +/** \brief RAM buffer where the executable flash operation code is copied to. */ +static blt_int8u flashExecCmdRam[(sizeof(flashExecCmd)/sizeof(flashExecCmd[0]))]; + +/** \brief Maximum number of supported blocks, which is determined dynamically to have + * code that is independent of the used HCS12 derivative. + */ +static blt_int8u flashMaxNrBlocks; + + +/************************************************************************************//** +** \brief Initializes the flash driver. +** \return none. +** +****************************************************************************************/ +void FlashInit(void) +{ + blt_bool result = BLT_FALSE; + blt_int8u cnt; + blt_int8u prescaler = 1; + blt_int16u clockFreq; + + /* flash EEPROM programming requires a minimal system speed of 1 MHz */ + ASSERT_CT(BOOT_CPU_SYSTEM_SPEED_KHZ >= 1000); + + /* init the flash block info structs by setting the address to an invalid address */ + blockInfo.base_addr = FLASH_INVALID_ADDRESS; + bootBlockInfo.base_addr = FLASH_INVALID_ADDRESS; + + /* determine how many flash blocks this device supports by first trying to set all + * all block selection bits. on devices where a specific block is not supported, + * the bit is reserved and will read back 0 afterwards + */ + FLASH->fcnfg |= FLASH_BLOCK_SEL_MASK; + /* read back which ones got set */ + flashMaxNrBlocks = (FLASH->fcnfg & FLASH_BLOCK_SEL_MASK) + 1; + /* set back to default reset value */ + FLASH->fcnfg &= ~(CBEIE_BIT | CCIE_BIT | KEYACC_BIT | FLASH_BLOCK_SEL_MASK); + + /* enable extra prescale factor of 8 when the external crystal is > 12.8 MHz */ + if (BOOT_CPU_XTAL_SPEED_KHZ > 12800) + { + prescaler = 8; + } + + /* FDIV[5..0] can only be between 0 and 63 so do a linear search to find the correct + * setting. + */ + for (cnt = 0; cnt <= 63; cnt++) + { + /* calculate current clock: FCLK = Fexternal_clock / (1 + FDIV[5..0]) */ + clockFreq = BOOT_CPU_XTAL_SPEED_KHZ / (prescaler * (1 + cnt)); + + /* is this a valid setting? */ + if ( (clockFreq > 150) && (clockFreq < 200) ) + { + /* configure the setting while taking into account the prescaler */ + if (prescaler == 8) + { + FLASH->fclkdiv = (PRDIV8_BIT | cnt); + } + else + { + FLASH->fclkdiv = cnt; + } + + /* all done */ + result = BLT_TRUE; + break; + } + } + + /* make sure that a valid clock divider was found */ + ASSERT_RT(result == BLT_TRUE); +} /*** end of FlashInit ***/ + + +/************************************************************************************//** +** \brief Writes the data to flash through a flash block manager. Note that this +** function also checks that no data is programmed outside the flash +** memory region, so the bootloader can never be overwritten. +** \param addr Start address. +** \param len Length in bytes. +** \param data Pointer to the data buffer. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data) +{ + blt_addr base_addr; + blt_addr last_block_base_addr; + + /* make sure the addresses are within the flash device */ + if ( (addr < FLASH_START_ADDRESS) || ((addr+len-1) > FLASH_END_ADDRESS) ) + { + return BLT_FALSE; + } + + /* determine the start address of the last block in flash */ + last_block_base_addr = flashLayout[FLASH_LAST_SECTOR_IDX].sector_start + \ + flashLayout[FLASH_LAST_SECTOR_IDX].sector_size - \ + FLASH_ERASE_BLOCK_SIZE; + + /* if this is the bootblock, then let the boot block manager handle it */ + base_addr = (addr/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE; + if (base_addr == last_block_base_addr) + { + /* let the boot block manager handle it */ + return FlashAddToBlock(&bootBlockInfo, addr, data, len); + } + /* let the block manager handle it */ + return FlashAddToBlock(&blockInfo, addr, data, len); +} /*** end of FlashWrite ***/ + + +/************************************************************************************//** +** \brief Erases the flash memory. Note that this function also checks that no +** data is erased outside the flash memory region, so the bootloader can +** never be erased. +** \param addr Start address. +** \param len Length in bytes. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool FlashErase(blt_addr addr, blt_int32u len) +{ + blt_addr erase_base_addr; + blt_int16u nr_of_erase_blocks; + blt_int32u total_erase_len; + blt_int16u block_cnt; + + /* determine the base address for the erase operation, by aligning to + * FLASH_ERASE_BLOCK_SIZE. + */ + erase_base_addr = (addr/FLASH_ERASE_BLOCK_SIZE)*FLASH_ERASE_BLOCK_SIZE; + + /* make sure the addresses are within the flash device */ + if ( (erase_base_addr < FLASH_START_ADDRESS) || ((addr+len-1) > FLASH_END_ADDRESS) ) + { + return BLT_FALSE; + } + + /* determine number of bytes to erase from base address */ + total_erase_len = len + (addr - erase_base_addr); + + /* determine the number of blocks to erase */ + nr_of_erase_blocks = (blt_int16u) (total_erase_len / FLASH_ERASE_BLOCK_SIZE); + if ((total_erase_len % FLASH_ERASE_BLOCK_SIZE) > 0) + { + nr_of_erase_blocks++; + } + + /* erase all blocks one by one */ + for (block_cnt=0; block_cntdata and sets the +** base address. +** \param block Pointer to flash block info structure to operate on. +** \param address Base address of the block data. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address) +{ + blt_int8u oldPage; + + /* check address alignment */ + if ((address % FLASH_WRITE_BLOCK_SIZE) != 0) + { + return BLT_FALSE; + } + /* make sure that we are initializing a new block and not the same one */ + if (block->base_addr == address) + { + /* block already initialized, so nothing to do */ + return BLT_TRUE; + } + /* set the base address */ + block->base_addr = address; + /* backup originally selected page */ + oldPage = FLASH_PPAGE_REG; + /* select correct page */ + FLASH_PPAGE_REG = FlashGetPhysPage(address); + /* copy the current data from flash */ + CpuMemCopy((blt_addr)block->data, (blt_addr)FlashGetPhysAddr(address), FLASH_WRITE_BLOCK_SIZE); + /* restore originally selected page */ + FLASH_PPAGE_REG = oldPage; + + return BLT_TRUE; +} /*** end of FlashInitBlock ***/ + + +/************************************************************************************//** +** \brief Switches blocks by programming the current one and initializing the +** next. +** \param block Pointer to flash block info structure to operate on. +** \param base_addr Base address of the next block. +** \return The pointer of the block info struct that is no being used, or a NULL +** pointer in case of error. +** +****************************************************************************************/ +static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr) +{ + /* check if a switch needs to be made away from the boot block. in this case the boot + * block shouldn't be written yet, because this is done at the end of the programming + * session by FlashDone(), this is right after the checksum was written. + */ + if (block == &bootBlockInfo) + { + /* switch from the boot block to the generic block info structure */ + block = &blockInfo; + } + /* check if a switch back into the bootblock is needed. in this case the generic block + * doesn't need to be written here yet. + */ + else if (base_addr == flashLayout[FLASH_LAST_SECTOR_IDX].sector_start) + { + /* switch from the generic block to the boot block info structure */ + block = &bootBlockInfo; + base_addr = flashLayout[FLASH_LAST_SECTOR_IDX].sector_start; + } + else + { + /* need to switch to a new block, so program the current one and init the next */ + if (FlashWriteBlock(block) == BLT_FALSE) + { + return BLT_NULL; + } + } + + /* initialize tne new block when necessary */ + if (FlashInitBlock(block, base_addr) == BLT_FALSE) + { + return BLT_NULL; + } + + /* still here to all is okay */ + return block; +} /*** end of FlashSwitchBlock ***/ + + +/************************************************************************************//** +** \brief Programming is done per block. This function adds data to the block +** that is currently collecting data to be written to flash. If the +** address is outside of the current block, the current block is written +** to flash an a new block is initialized. +** \param block Pointer to flash block info structure to operate on. +** \param address Flash destination address. +** \param data Pointer to the byte array with data. +** \param len Number of bytes to add to the block. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address, + blt_int8u *data, blt_int32u len) +{ + blt_addr current_base_addr; + blt_int8u *dst; + blt_int8u *src; + + /* determine the current base address */ + current_base_addr = (address/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE; + + /* make sure the blockInfo is not uninitialized */ + if (block->base_addr == FLASH_INVALID_ADDRESS) + { + /* initialize the blockInfo struct for the current block */ + if (FlashInitBlock(block, current_base_addr) == BLT_FALSE) + { + return BLT_FALSE; + } + } + + /* check if the new data fits in the current block */ + if (block->base_addr != current_base_addr) + { + /* need to switch to a new block, so program the current one and init the next */ + block = FlashSwitchBlock(block, current_base_addr); + if (block == BLT_NULL) + { + return BLT_FALSE; + } + } + + /* add the data to the current block, but check for block overflow */ + dst = &(block->data[address - block->base_addr]); + src = data; + do + { + /* keep the watchdog happy */ + CopService(); + /* buffer overflow? */ + if ((blt_addr)(dst-&(block->data[0])) >= FLASH_WRITE_BLOCK_SIZE) + { + /* need to switch to a new block, so program the current one and init the next */ + block = FlashSwitchBlock(block, current_base_addr+FLASH_WRITE_BLOCK_SIZE); + if (block == BLT_NULL) + { + return BLT_FALSE; + } + /* reset destination pointer */ + dst = &(block->data[0]); + } + /* write the data to the buffer */ + *dst = *src; + /* update pointers */ + dst++; + src++; + /* decrement byte counter */ + len--; + } + while (len > 0); + /* still here so all is good */ + return BLT_TRUE; +} /*** end of FlashAddToBlock ***/ + + +/************************************************************************************//** +** \brief Programs FLASH_WRITE_BLOCK_SIZE bytes to flash from the block->data +** array. +** \param block Pointer to flash block info structure to operate on. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +static blt_bool FlashWriteBlock(tFlashBlockInfo *block) +{ + blt_bool result = BLT_TRUE; + blt_addr prog_addr; + blt_int16u prog_data; + blt_int16u word_cnt; + + + /* make sure the blockInfo is not uninitialized */ + if (block->base_addr == FLASH_INVALID_ADDRESS) + { + return BLT_FALSE; + } + /* program all words in the block one by one */ + for (word_cnt=0; word_cnt<(FLASH_WRITE_BLOCK_SIZE/sizeof(blt_int16u)); word_cnt++) + { + prog_addr = block->base_addr + (word_cnt * sizeof(blt_int16u)); + prog_data = *(volatile blt_int16u*)(&block->data[word_cnt * sizeof(blt_int16u)]); + /* keep the watchdog happy */ + CopService(); + /* program the word to flash */ + if (FlashOperate(FLASH_PROGRAM_WORD_CMD, prog_addr, prog_data) == BLT_FALSE) + { + /* error occurred */ + result = BLT_FALSE; + break; + } + /* verify that the written data is actually there */ + if (FlashGetLinearAddrByte(prog_addr) != (blt_int8u)(prog_data >> 8)) + { + /* msb not correctly written */ + result = BLT_FALSE; + break; + } + if (FlashGetLinearAddrByte(prog_addr+1) != (blt_int8u)(prog_data)) + { + /* lsb not correctly written */ + result = BLT_FALSE; + break; + } + } + /* still here so all is okay */ + return result; +} /*** end of FlashWriteBlock ***/ + + +/************************************************************************************//** +** \brief Reads the byte value from the linear address. +** \param addr Linear address. +** \return The byte value located at the linear address. +** +****************************************************************************************/ +static blt_int8u FlashGetLinearAddrByte(blt_addr addr) +{ + blt_int8u oldPage; + blt_int8u result; + + /* backup originally selected page */ + oldPage = FLASH_PPAGE_REG; + + /* select correct page */ + FLASH_PPAGE_REG = FlashGetPhysPage(addr); + + /* read the byte value from the page address */ + result = *((blt_int8u*)FlashGetPhysAddr(addr)); + + /* restore originally selected page */ + FLASH_PPAGE_REG = oldPage; + + /* return the read byte value */ + return result; +} /*** end of FlashGetLinearAddrByte ***/ + + +/************************************************************************************//** +** \brief Extracts the physical flash page number from a linear address. +** \param addr Linear address. +** \return The page number. +** +****************************************************************************************/ +static blt_int8u FlashGetPhysPage(blt_addr addr) +{ + return (blt_int8u)(addr / FLASH_PAGE_SIZE); +} /*** end of FlashGetPhysPage ***/ + + +/************************************************************************************//** +** \brief Extracts the physical address on the flash page number from a +** linear address. +** \param addr Linear address. +** \return The physical address. +** +****************************************************************************************/ +static blt_int16u FlashGetPhysAddr(blt_addr addr) +{ + return (blt_int16u)(((blt_int16u)addr % FLASH_PAGE_SIZE) + FLASH_PAGE_OFFSET); +} /*** end of FlashGetPhysAddr ***/ + + +/************************************************************************************//** +** \brief Executes the command. The actual code for the command execution is +** stored as location independant machine code in array flashExecCmd[]. +** The contents of this array are temporarily copied to RAM. This way the +** function can be executed from RAM avoiding problem when try to perform +** a flash operation on the same flash block that this driver is located. +** \return none. +** +****************************************************************************************/ +static void FlashExecuteCommand(void) +{ + /* pointer to command execution function */ + pFlashExeCmdFct pExecCommandFct; + blt_int8u cnt; + + /* copy code for command execution to ram buffer */ + for (cnt=0; cnt<(sizeof(flashExecCmd)/sizeof(flashExecCmd[0])); cnt++) + { + flashExecCmdRam[cnt] = flashExecCmd[cnt]; + } + + /* init the function pointer */ + pExecCommandFct = (pFlashExeCmdFct) ((void *)flashExecCmdRam); + /* call the command execution function */ + pExecCommandFct(); +} /*** end of FlashExecuteCommand ***/ + + +/************************************************************************************//** +** \brief Prepares the flash command and executes it. +** \param cmd Command to be launched. +** \param addr Physical address for operation. +** \param data Data to write to addr for operation. +** \return BLT_TRUE if operation was successful, otherwise BLT_FALSE. +** +****************************************************************************************/ +static blt_bool FlashOperate(blt_int8u cmd, blt_addr addr, blt_int16u data) +{ + blt_bool result; + blt_int8u oldPage; + blt_int8u selPage; + + /* set default result to error */ + result = BLT_FALSE; + /* backup originally selected page */ + oldPage = FLASH_PPAGE_REG; + /* calculate page number */ + selPage = FlashGetPhysPage(addr); + /* select correct page */ + FLASH_PPAGE_REG = selPage; + + /* there are always a fixed number of pages per block. to get the block index number + * we simply divide by this number of pages per block. to one tricky thing is that + * the block number goes from high to low with increasing page numbers so we need to + * invert it. After the inversion we apply a bitmask to obtain the block selection bits + */ + FLASH->fcnfg &= ~FLASH_BLOCK_SEL_MASK; + FLASH->fcnfg |= (~(selPage / FLASH_PAGES_PER_BLOCK)) & FLASH_BLOCK_SEL_MASK; + + /* clear error flags */ + FLASH->fstat = (ACCERR_BIT | PVIOL_BIT); + /* command buffer empty? */ + if ((FLASH->fstat & CBEIF_BIT) == CBEIF_BIT) + { + /* write data value to the physical address to operate on */ + *((blt_int16u*)FlashGetPhysAddr(addr)) = data; + /* write the command */ + FLASH->fcmd = cmd; + /* launch the actual command */ + FlashExecuteCommand(); + /* check error flags */ + if ((FLASH->fstat & (ACCERR_BIT | PVIOL_BIT)) == 0) + { + /* operation was successful */ + result = BLT_TRUE; + } + } + + /* restore originally selected page */ + FLASH_PPAGE_REG = oldPage; + + return result; +} /*** end of FlashOperate ***/ + + +/*********************************** end of flash.c ************************************/ diff --git a/Target/Source/HCS12/flash.h b/Target/Source/HCS12/flash.h new file mode 100644 index 00000000..f14107f5 --- /dev/null +++ b/Target/Source/HCS12/flash.h @@ -0,0 +1,48 @@ +/************************************************************************************//** +* \file Source\HCS12\flash.c +* \brief Bootloader flash driver source file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef FLASH_H +#define FLASH_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void FlashInit(void); +blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data); +blt_bool FlashErase(blt_addr addr, blt_int32u len); +blt_bool FlashWriteChecksum(void); +blt_bool FlashVerifyChecksum(void); +blt_bool FlashDone(void); + + +#endif /* FLASH_H */ +/*********************************** end of flash.h ************************************/ diff --git a/Target/Source/HCS12/nvm.c b/Target/Source/HCS12/nvm.c new file mode 100644 index 00000000..5827fcc7 --- /dev/null +++ b/Target/Source/HCS12/nvm.c @@ -0,0 +1,216 @@ +/************************************************************************************//** +* \file Source\HCS12\nvm.c +* \brief Bootloader non-volatile memory driver source file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ + + +/**************************************************************************************** +* Hook functions +****************************************************************************************/ +#if (BOOT_NVM_HOOKS_ENABLE > 0) +extern void NvmInitHook(void); +extern blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data); +extern blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len); +extern blt_bool NvmDoneHook(void); +#endif + +#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) +extern blt_bool NvmWriteChecksumHook(void); +extern blt_bool NvmVerifyChecksumHook(void); +#endif + + + +/************************************************************************************//** +** \brief Initializes the NVM driver. +** \return none. +** +****************************************************************************************/ +void NvmInit(void) +{ +#if (BOOT_NVM_HOOKS_ENABLE > 0) + /* give the application a chance to initialize a driver for operating on NVM + * that is not by default supported by this driver. + */ + NvmInitHook(); +#endif + + /* init the internal driver */ + FlashInit(); +} /*** end of NvmInit ***/ + + +/************************************************************************************//** +** \brief Programs the non-volatile memory. +** \param addr Start address. +** \param len Length in bytes. +** \param data Pointer to the data buffer. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data) +{ +#if (BOOT_NVM_HOOKS_ENABLE > 0) + blt_int8u result = BLT_NVM_NOT_IN_RANGE; +#endif + +#if (BOOT_NVM_HOOKS_ENABLE > 0) + /* give the application a chance to operate on memory that is not by default supported + * by this driver. + */ + result = NvmWriteHook(addr, len, data); + + /* process the return code */ + if (result == BLT_NVM_OKAY) + { + /* data was within range of the additionally supported memory and succesfully + * programmed, so we are all done. + */ + return BLT_TRUE; + } + else if (result == BLT_NVM_ERROR) + { + /* data was within range of the additionally supported memory and attempted to be + * programmed, but an error occurred, so we can't continue. + */ + return BLT_FALSE; + } +#endif + + /* still here so the internal driver should try and perform the program operation */ + return FlashWrite(addr, len, data); +} /*** end of NvmWrite ***/ + + +/************************************************************************************//** +** \brief Erases the non-volatile memory. +** \param addr Start address. +** \param len Length in bytes. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmErase(blt_addr addr, blt_int32u len) +{ +#if (BOOT_NVM_HOOKS_ENABLE > 0) + blt_int8u result = BLT_NVM_NOT_IN_RANGE; +#endif + +#if (BOOT_NVM_HOOKS_ENABLE > 0) + /* give the application a chance to operate on memory that is not by default supported + * by this driver. + */ + result = NvmEraseHook(addr, len); + + /* process the return code */ + if (result == BLT_NVM_OKAY) + { + /* address was within range of the additionally supported memory and succesfully + * erased, so we are all done. + */ + return BLT_TRUE; + } + else if (result == BLT_NVM_ERROR) + { + /* address was within range of the additionally supported memory and attempted to be + * erased, but an error occurred, so we can't continue. + */ + return BLT_FALSE; + } +#endif + + /* still here so the internal driver should try and perform the erase operation */ + return FlashErase(addr, len); +} /*** end of NvmErase ***/ + + +/************************************************************************************//** +** \brief Verifies the checksum, which indicates that a valid user program is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmVerifyChecksum(void) +{ +#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) + /* check checksum using the application specific method. */ + return NvmVerifyChecksumHook(); +#else + /* check checksum using the interally supported method. */ + return FlashVerifyChecksum(); +#endif +} /*** end of NvmVerifyChecksum ***/ + + +/************************************************************************************//** +** \brief Once all erase and programming operations are completed, this +** function is called, so at the end of the programming session and +** right before a software reset is performed. It is used to calculate +** a checksum and program this into flash. This checksum is later used +** to determine if a valid user program is present in flash. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmDone(void) +{ +#if (BOOT_NVM_HOOKS_ENABLE > 0) + /* give the application's NVM driver a chance to finish up */ + if (NvmDoneHook() == BLT_FALSE) + { + /* error so no need to continue */ + return BLT_FALSE; + } +#endif + +#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) + /* compute and write checksum, using the application specific method. */ + if (NvmWriteChecksumHook() == BLT_FALSE) + { + return BLT_FALSE; + } +#else + /* compute and write checksum, which is programmed by the internal driver. */ + if (FlashWriteChecksum() == BLT_FALSE) + { + return BLT_FALSE; + } +#endif + + /* finish up internal driver operations */ + return FlashDone(); +} /*** end of NvmDone ***/ + + +/*********************************** end of nvm.c **************************************/ diff --git a/Target/Source/HCS12/nvm.h b/Target/Source/HCS12/nvm.h new file mode 100644 index 00000000..09a19be6 --- /dev/null +++ b/Target/Source/HCS12/nvm.h @@ -0,0 +1,65 @@ +/************************************************************************************//** +* \file Source\HCS12\nvm.h +* \brief Bootloader non-volatile memory driver header file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef NVM_H +#define NVM_H + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "flash.h" /* LPC2xxx flash driver */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void NvmInit(void); +blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data); +blt_bool NvmErase(blt_addr addr, blt_int32u len); +blt_bool NvmVerifyChecksum(void); +blt_bool NvmDone(void); + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/* return codes for hook function NvmWrite/Erase */ +/** \brief Return code for success. */ +#define BLT_NVM_ERROR (0x00) +/** \brief Return code for error. */ +#define BLT_NVM_OKAY (0x01) +/** \brief Return code for not in range. */ +#define BLT_NVM_NOT_IN_RANGE (0x02) + + +#endif /* NVM_H */ +/*********************************** end of nvm.h **************************************/ diff --git a/Target/Source/HCS12/target.dox b/Target/Source/HCS12/target.dox new file mode 100644 index 00000000..b7ce6178 --- /dev/null +++ b/Target/Source/HCS12/target.dox @@ -0,0 +1,8 @@ +/** +\defgroup Target_HCS12 Target HCS12 +\brief Target dependent code for the Freescale HCS12 microcontroller family. +\details This module implements the bootloader's target dependent part for the + Freescale HCS12 microcontroller family. +*/ + + diff --git a/Target/Source/HCS12/timer.c b/Target/Source/HCS12/timer.c new file mode 100644 index 00000000..8857bb09 --- /dev/null +++ b/Target/Source/HCS12/timer.c @@ -0,0 +1,178 @@ +/************************************************************************************//** +* \file Source\HCS12\timer.c +* \brief Bootloader timer driver source file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Structure type with the layout of the timer related control registers. */ +typedef struct +{ + volatile blt_int8u tios; /**< input capture/output compare select */ + volatile blt_int8u cforc; /**< compare force register */ + volatile blt_int8u oc7m; /**< output compare 7 mask register */ + volatile blt_int8u oc7d; /**< output compare 7 data register */ + volatile blt_int16u tcnt; /**< timer counter register */ + volatile blt_int8u tscr1; /**< system control register 1 */ + volatile blt_int8u ttov; /**< toggle overflow register */ + volatile blt_int8u tctl1; /**< timer control register 1 */ + volatile blt_int8u tctl2; /**< timer control register 2 */ + volatile blt_int8u tctl3; /**< timer control register 3 */ + volatile blt_int8u tctl4; /**< timer control register 4 */ + volatile blt_int8u tie; /**< interrupt enable register */ + volatile blt_int8u tscr2; /**< system control register 2 */ + volatile blt_int8u tflg1; /**< timer interrupt flag 1 */ + volatile blt_int8u tflg2; /**< timer interrupt flag 2 */ + volatile blt_int16u tc[8]; /**< input capture/output compare register n */ +} tTimerRegs; /**< timer related registers */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Base address for the timer related control registers. */ +#define TIMER_REGS_BASE_ADDRESS (0x0040) +/** \brief Macro for accessing the flash related control registers. */ +#define TIMER ((volatile tTimerRegs *)TIMER_REGS_BASE_ADDRESS) +/** \brief Number of free running counter ticks in one millisecond. */ +#define TIMER_COUNTS_PER_MS (BOOT_CPU_SYSTEM_SPEED_KHZ) + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Local variable for storing the number of milliseconds that have elapsed since + * startup. + */ +static blt_int32u millisecond_counter; + + +/**************************************************************************************** +* Register definitions +****************************************************************************************/ +/** \brief TSCR1 - timer enable bit. */ +#define TEN_BIT (0x80) +/** \brief TIOS - channel 0 ic/oc configuration bit. */ +#define IOS0_BIT (0x01) +/** \brief TFLG1 - channel 0 ic/oc event flag bit. */ +#define C0F_BIT (0x01) + + +/************************************************************************************//** +** \brief Initializes the polling based millisecond timer driver. +** \return none. +** +****************************************************************************************/ +void TimerInit(void) +{ + /* reset the timer configuration. note that this also sets the default prescaler + * to 1, so the free running counter runs at the same speed as the system + * (BOOT_CPU_SYSTEM_SPEED_KHZ). + */ + TimerReset(); + /* configure timer channel 0 as a 1 millisecond software timer */ + TIMER->tios |= IOS0_BIT; + /* make sure timer 0 interrupt flag is cleared */ + TIMER->tflg1 = C0F_BIT; + /* generate output compare event in 1 milliseconds from now */ + TIMER->tc[0] = TIMER->tcnt + TIMER_COUNTS_PER_MS; + /* enable the timer subsystem */ + TIMER->tscr1 |= TEN_BIT; + /* reset the millisecond counter value */ + millisecond_counter = 0; +} /*** end of TimerInit ***/ + + +/************************************************************************************//** +** \brief Reset the timer by placing the timer back into it's default reset +** configuration. +** \return none. +** +****************************************************************************************/ +void TimerReset(void) +{ + /* bring the timer subsystem back into its reset state */ + TIMER->tie = 0; + TIMER->tscr1 = 0; + TIMER->tscr2 = 0; + TIMER->tios = 0; + TIMER->ttov = 0; + TIMER->tctl1 = 0; + TIMER->tctl2 = 0; + TIMER->tctl3 = 0; + TIMER->tctl4 = 0; +} /* end of TimerReset */ + + +/************************************************************************************//** +** \brief Updates the millisecond timer. +** \return none. +** +****************************************************************************************/ +void TimerUpdate(void) +{ + /* check if the millisecond event occurred */ + if ((TIMER->tflg1 & C0F_BIT) == C0F_BIT) + { + /* make sure timer 0 interrupt flag is cleared */ + TIMER->tflg1 = C0F_BIT; + /* generate output compare event in 1 milliseconds from now */ + TIMER->tc[0] += TIMER_COUNTS_PER_MS; + /* increment the millisecond counter */ + millisecond_counter++; + } +} /*** end of TimerUpdate ***/ + + +/************************************************************************************//** +** \brief Obtains the counter value of the millisecond timer. +** \return Current value of the millisecond timer. +** +****************************************************************************************/ +blt_int32u TimerGet(void) +{ + /* updating timer here allows this function to be called in a loop with timeout + * detection. + */ + TimerUpdate(); + /* read and return the amount of milliseconds that passed since initialization */ + return millisecond_counter; +} /*** end of TimerGet ***/ + + +/*********************************** end of timer.c ************************************/ diff --git a/Target/Source/HCS12/timer.h b/Target/Source/HCS12/timer.h new file mode 100644 index 00000000..70a08b8a --- /dev/null +++ b/Target/Source/HCS12/timer.h @@ -0,0 +1,46 @@ +/************************************************************************************//** +* \file Source\HCS12\timer.h +* \brief Bootloader timer driver header file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef TIMER_H +#define TIMER_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void TimerInit(void); +void TimerUpdate(void); +blt_int32u TimerGet(void); +void TimerReset(void); + + +#endif /* TIMER_H */ +/*********************************** end of timer.h ************************************/ diff --git a/Target/Source/HCS12/types.h b/Target/Source/HCS12/types.h new file mode 100644 index 00000000..688abbfe --- /dev/null +++ b/Target/Source/HCS12/types.h @@ -0,0 +1,63 @@ +/************************************************************************************//** +* \file Source\HCS12\types.h +* \brief Bootloader types header file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef TYPES_H +#define TYPES_H + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Boolean true value. */ +#define BLT_TRUE (1) +/** \brief Boolean false value. */ +#define BLT_FALSE (0) +/** \brief NULL pointer value. */ +#define BLT_NULL ((void *)0) + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +typedef unsigned char blt_bool; /**< boolean type */ +typedef char blt_char; /**< character type */ +typedef unsigned long blt_addr; /**< memory address type */ +typedef unsigned char blt_int8u; /**< 8-bit unsigned integer */ +typedef signed char blt_int8s; /**< 8-bit signed integer */ +typedef unsigned short blt_int16u; /**< 16-bit unsigned integer */ +typedef signed short blt_int16s; /**< 16-bit signed integer */ +typedef unsigned long blt_int32u; /**< 32-bit unsigned integer */ +typedef signed long blt_int32s; /**< 32-bit signed integer */ + + +#endif /* TYPES_H */ +/*********************************** end of types.h ************************************/ diff --git a/Target/Source/HCS12/uart.c b/Target/Source/HCS12/uart.c new file mode 100644 index 00000000..4f91e6c9 --- /dev/null +++ b/Target/Source/HCS12/uart.c @@ -0,0 +1,252 @@ +/************************************************************************************//** +* \file Source\HCS12\uart.c +* \brief Bootloader UART communication interface source file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ + + +#if (BOOT_COM_UART_ENABLE > 0) +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Structure type with the layout of the UART related controler registers. */ +typedef volatile struct +{ + volatile blt_int8u scibdh; /**< baudrate control register [SBR 12..8] */ + volatile blt_int8u scibdl; /**< baudrate control register [SBR 8..0] */ + volatile blt_int8u scicr1; /**< control register 1 */ + volatile blt_int8u scicr2; /**< control register 2 */ + volatile blt_int8u scisr1; /**< status regsiter 1 */ + volatile blt_int8u scisr2; /**< status register 2 */ + volatile blt_int8u scidrh; /**< data register high (for ninth bit) */ + volatile blt_int8u scidrl; /**< data regsiter low */ +} tUartRegs; /**< sci related registers */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +#if (BOOT_COM_UART_CHANNEL_INDEX == 0) +/** \brief Set UART base address to SCI0. */ +#define UART_REGS_BASE_ADDRESS (0x00c8) +#elif (BOOT_COM_UART_CHANNEL_INDEX == 1) +/** \brief Set UART base address to SCI1. */ +#define UART_REGS_BASE_ADDRESS (0x00d0) +#endif +/** \brief Macro for accessing the UART related control registers. */ +#define UART ((volatile tUartRegs *)UART_REGS_BASE_ADDRESS) + + +/**************************************************************************************** +* Register definitions +****************************************************************************************/ +/** \brief SCICR2 - transmitter enable bit. */ +#define TE_BIT (0x08) +/** \brief SCICR2 - receiver enable bit. */ +#define RE_BIT (0x04) +/** \brief SCISR1 - receiver data register full bit. */ +#define RDRF_BIT (0x20) +/** \brief SCISR1 - transmit data register empty bit. */ +#define TDRE_BIT (0x80) + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static blt_bool UartReceiveByte(blt_int8u *data); +static blt_bool UartTransmitByte(blt_int8u data); + + +/************************************************************************************//** +** \brief Initializes the UART communication interface. +** \return none. +** +****************************************************************************************/ +void UartInit(void) +{ + blt_int16u baudrate_sbr0_12; + + /* the current implementation supports SCI0 and SCI1. throw an assertion error in + * case a different UART channel is configured. + */ + ASSERT_CT((BOOT_COM_UART_CHANNEL_INDEX == 0) || (BOOT_COM_UART_CHANNEL_INDEX == 1)); + /* reset the SCI subsystem's configuration, which automatically configures it for + * 8,n,1 communication mode. + */ + UART->scicr2 = 0; + UART->scicr1 = 0; + UART->scibdh = 0; + UART->scibdl = 0; + /* configure the baudrate from BOOT_COM_UART_BAUDRATE */ + baudrate_sbr0_12 = (BOOT_CPU_SYSTEM_SPEED_KHZ * 1000ul) / 16 / BOOT_COM_UART_BAUDRATE; + /* baudrate register value cannot be more than 13 bits */ + ASSERT_RT((baudrate_sbr0_12 & 0xe000) == 0); + /* write first MSB then LSB for the baudrate to latch */ + UART->scibdh = (blt_int8u)(baudrate_sbr0_12 >> 8); + UART->scibdl = (blt_int8u)baudrate_sbr0_12; + /* enable the transmitted and receiver */ + UART->scicr2 |= (TE_BIT | RE_BIT); +} /*** end of UartInit ***/ + + +/************************************************************************************//** +** \brief Transmits a packet formatted for the communication interface. +** \param data Pointer to byte array with data that it to be transmitted. +** \param len Number of bytes that are to be transmitted. +** \return none. +** +****************************************************************************************/ +void UartTransmitPacket(blt_int8u *data, blt_int8u len) +{ + blt_int16u data_index; + + /* verify validity of the len-paramenter */ + ASSERT_RT(len <= BOOT_COM_TX_MAX_DATA); + + /* first transmit the length of the packet */ + ASSERT_RT(UartTransmitByte(len) == BLT_TRUE); + + /* transmit all the packet bytes one-by-one */ + for (data_index = 0; data_index < len; data_index++) + { + /* keep the watchdog happy */ + CopService(); + /* write byte */ + ASSERT_RT(UartTransmitByte(data[data_index]) == BLT_TRUE); + } +} /*** end of UartTransmitPacket ***/ + + +/************************************************************************************//** +** \brief Receives a communication interface packet if one is present. +** \param data Pointer to byte array where the data is to be stored. +** \return BLT_TRUE if a packet was received, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool UartReceivePacket(blt_int8u *data) +{ + static blt_int8u xcpCtoReqPacket[XCP_CTO_PACKET_LEN+1]; /* one extra for length */ + static blt_int8u xcpCtoRxLength; + static blt_bool xcpCtoRxInProgress = BLT_FALSE; + + /* start of cto packet received? */ + if (xcpCtoRxInProgress == BLT_FALSE) + { + /* store the message length when received */ + if (UartReceiveByte(&xcpCtoReqPacket[0]) == BLT_TRUE) + { + /* indicate that a cto packet is being received */ + xcpCtoRxInProgress = BLT_TRUE; + + /* reset packet data count */ + xcpCtoRxLength = 0; + } + } + else + { + /* store the next packet byte */ + if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == BLT_TRUE) + { + /* increment the packet data count */ + xcpCtoRxLength++; + + /* check to see if the entire packet was received */ + if (xcpCtoRxLength == xcpCtoReqPacket[0]) + { + /* copy the packet data */ + CpuMemCopy((blt_int32u)data, (blt_int32u)&xcpCtoReqPacket[1], xcpCtoRxLength); + /* done with cto packet reception */ + xcpCtoRxInProgress = BLT_FALSE; + + /* packet reception complete */ + return BLT_TRUE; + } + } + } + /* packet reception not yet complete */ + return BLT_FALSE; +} /*** end of UartReceivePacket ***/ + + +/************************************************************************************//** +** \brief Receives a communication interface byte if one is present. +** \param data Pointer to byte where the data is to be stored. +** \return BLT_TRUE if a byte was received, BLT_FALSE otherwise. +** +****************************************************************************************/ +static blt_bool UartReceiveByte(blt_int8u *data) +{ + /* check if a new byte was received by means of the RDRF-bit */ + if((UART->scisr1 & RDRF_BIT) != 0) + { + /* store the received byte */ + data[0] = UART->scidrl; + /* inform caller of the newly received byte */ + return BLT_TRUE; + } + /* inform caller that no new data was received */ + return BLT_FALSE; +} /*** end of UartReceiveByte ***/ + + +/************************************************************************************//** +** \brief Transmits a communication interface byte. +** \param data Value of byte that is to be transmitted. +** \return BLT_TRUE if the byte was transmitted, BLT_FALSE otherwise. +** +****************************************************************************************/ +static blt_bool UartTransmitByte(blt_int8u data) +{ + /* check if tx holding register can accept new data */ + if ((UART->scisr1 & TDRE_BIT) == 0) + { + /* UART not ready. should not happen */ + return BLT_FALSE; + } + /* write byte to transmit holding register */ + UART->scidrl = data; + /* wait for tx holding register to be empty */ + while((UART->scisr1 & TDRE_BIT) == 0) + { + /* keep the watchdog happy */ + CopService(); + } + /* byte transmitted */ + return BLT_TRUE; +} /*** end of UartTransmitByte ***/ +#endif /* BOOT_COM_UART_ENABLE > 0 */ + + +/*********************************** end of uart.c *************************************/ diff --git a/Target/Source/HCS12/uart.h b/Target/Source/HCS12/uart.h new file mode 100644 index 00000000..9b7bd3d3 --- /dev/null +++ b/Target/Source/HCS12/uart.h @@ -0,0 +1,47 @@ +/************************************************************************************//** +* \file Source\HCS12\uart.h +* \brief Bootloader UART communication interface header file. +* \ingroup Target_HCS12 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along with OpenBLT. +* If not, see . +* +* A special exception to the GPL is included to allow you to distribute a combined work +* that includes OpenBLT without being obliged to provide the source code for any +* proprietary components. The exception text is included at the bottom of the license +* file . +* +* \endinternal +****************************************************************************************/ +#ifndef UART_H +#define UART_H + +#if (BOOT_COM_UART_ENABLE > 0) +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void UartInit(void); +void UartTransmitPacket(blt_int8u *data, blt_int8u len); +blt_bool UartReceivePacket(blt_int8u *data); +#endif /* BOOT_COM_UART_ENABLE > 0 */ + + +#endif /* UART_H */ +/*********************************** end of uart.h *************************************/