\a Register | \a Bit fields |
SCU_CLKCR | FDIV, IDIV, PCLKSEL, RTCLKSEL |
SCU_CGATSET0 | All bits |
SCU_CGATCLR0 | All bits |
SCU_ANAOFFSET | ADJL_OFFSET |
VADC0_ACCPROT0 | All bits |
VADC0_ACCPROT1 | All bits |
\a Register | \a Bit fields |
SCU_CLKCR | FDIV, IDIV, PCLKSEL, RTCLKSEL |
SCU_CGATSET0 | All bits |
SCU_CGATCLR0 | All bits |
SCU_ANAOFFSET | ADJL_OFFSET |
VADC0_ACCPROT0 | All bits |
VADC0_ACCPROT1 | All bits |
0 | DXnA |
1 | DXnB |
2 | DXnC |
3 | DXnD |
4 | DXnE |
5 | DXnF |
6 | DXnG |
7 | Always 1 | + *
0 | DXnA |
1 | DXnB |
2 | DXnC |
3 | DXnD |
4 | DXnE |
5 | DXnF |
6 | DXnG |
7 | Always 1 | + *
\a Register | \a Bit fields |
SCU_CLKCR | FDIV, IDIV, PCLKSEL, RTCLKSEL |
SCU_CGATSET0 | All bits |
SCU_CGATCLR0 | All bits |
SCU_ANAOFFSET | ADJL_OFFSET |
VADC0_ACCPROT0 | All bits |
VADC0_ACCPROT1 | All bits |
\a Register | \a Bit fields |
SCU_CLKCR | FDIV, IDIV, PCLKSEL, RTCLKSEL |
SCU_CGATSET0 | All bits |
SCU_CGATCLR0 | All bits |
SCU_ANAOFFSET | ADJL_OFFSET |
VADC0_ACCPROT0 | All bits |
VADC0_ACCPROT1 | All bits |
0 | DXnA |
1 | DXnB |
2 | DXnC |
3 | DXnD |
4 | DXnE |
5 | DXnF |
6 | DXnG |
7 | Always 1 | + *
0 | DXnA |
1 | DXnB |
2 | DXnC |
3 | DXnD |
4 | DXnE |
5 | DXnF |
6 | DXnG |
7 | Always 1 | + *