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Refs #963. Updated CAN driver in the STM32F3 port and the HAL drivers in all STM32F3 demo programs for compatibility with the latest ST HAL. 

git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@751 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg 2020-02-27 10:03:06 +00:00
parent fda6c55db5
commit c251cf3a6b
1029 changed files with 440007 additions and 297606 deletions
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Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/bin/openblt_stm32f303.elf
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Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h
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@ -16,29 +16,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -119,11 +103,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V2.3.2 * @brief CMSIS Device version number V2.3.4
*/ */
#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F3_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32F3_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\ #define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
|(__STM32F3_CMSIS_VERSION_SUB1 << 16)\ |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
@ -179,21 +163,21 @@
*/ */
typedef enum typedef enum
{ {
RESET = 0, RESET = 0U,
SET = !RESET SET = !RESET
} FlagStatus, ITStatus; } FlagStatus, ITStatus;
typedef enum typedef enum
{ {
DISABLE = 0, DISABLE = 0U,
ENABLE = !DISABLE ENABLE = !DISABLE
} FunctionalState; } FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum typedef enum
{ {
ERROR = 0, SUCCESS = 0U,
SUCCESS = !ERROR ERROR = !SUCCESS
} ErrorStatus; } ErrorStatus;
/** /**
@ -221,15 +205,13 @@ typedef enum
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
#if defined (USE_HAL_DRIVER)
#include "stm32f3xx_hal.h"
#endif /* USE_HAL_DRIVER */
/** /**
* @} * @}
*/ */
#if defined (USE_HAL_DRIVER)
#include "stm32f3xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus #ifdef __cplusplus
} }

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Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h
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@ -6,32 +6,16 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{

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@ -1,136 +0,0 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. October 2015
* $Revision: V.1.4.5 a
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
/* extern const q31_t realCoefAQ31[1024]; */
/* extern const q31_t realCoefBQ31[1024]; */
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

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@ -1,79 +0,0 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

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@ -1,43 +1,104 @@
/**************************************************************************//** /**************************************************************************//**
* @file cmsis_armcc.h * @file cmsis_armcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V4.30 * @version V5.0.4
* @date 20. October 2015 * @date 10. January 2018
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED /*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
All rights reserved. *
Redistribution and use in source and binary forms, with or without * SPDX-License-Identifier: Apache-2.0
modification, are permitted provided that the following conditions are met: *
- Redistributions of source code must retain the above copyright * Licensed under the Apache License, Version 2.0 (the License); you may
notice, this list of conditions and the following disclaimer. * not use this file except in compliance with the License.
- Redistributions in binary form must reproduce the above copyright * You may obtain a copy of the License at
notice, this list of conditions and the following disclaimer in the *
documentation and/or other materials provided with the distribution. * www.apache.org/licenses/LICENSE-2.0
- Neither the name of ARM nor the names of its contributors may be used *
to endorse or promote products derived from this software without * Unless required by applicable law or agreed to in writing, software
specific prior written permission. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * See the License for the specific language governing permissions and
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * limitations under the License.
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H #ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H #define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!" #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif #endif
/* ########################### Core Function Access ########################### */ /* ########################### Core Function Access ########################### */
@ -46,7 +107,19 @@
@{ @{
*/ */
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */ /* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */ /* intrinsic void __disable_irq(); */
/** /**
@ -181,7 +254,8 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
} }
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/** /**
\brief Enable FIQ \brief Enable FIQ
@ -256,14 +330,13 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{ {
register uint32_t __regFaultMask __ASM("faultmask"); register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1); __regFaultMask = (faultMask & (uint32_t)1U);
} }
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/** /**
\brief Get FPSCR \brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register. \details Returns the current value of the Floating Point Status/Control register.
@ -271,7 +344,8 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
*/ */
__STATIC_INLINE uint32_t __get_FPSCR(void) __STATIC_INLINE uint32_t __get_FPSCR(void)
{ {
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr"); register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr); return(__regfpscr);
#else #else
@ -287,15 +361,15 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
*/ */
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{ {
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr"); register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr); __regfpscr = (fpscr);
#else
(void)fpscr;
#endif #endif
} }
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */ /*@} end of CMSIS_Core_RegAccFunctions */
@ -369,9 +443,10 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
__schedule_barrier();\ __schedule_barrier();\
} while (0U) } while (0U)
/** /**
\brief Reverse byte order (32 bit) \brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value. \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse \param [in] value Value to reverse
\return Reversed value \return Reversed value
*/ */
@ -380,7 +455,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
/** /**
\brief Reverse byte order (16 bit) \brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values. \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse \param [in] value Value to reverse
\return Reversed value \return Reversed value
*/ */
@ -392,14 +467,15 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
} }
#endif #endif
/** /**
\brief Reverse byte order in signed short value \brief Reverse byte order (16 bit)
\details Reverses the byte order in a signed short value with sign extension to integer. \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse \param [in] value Value to reverse
\return Reversed value \return Reversed value
*/ */
#ifndef __NO_EMBEDDED_ASM #ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{ {
revsh r0, r0 revsh r0, r0
bx lr bx lr
@ -410,8 +486,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
/** /**
\brief Rotate Right in unsigned value (32 bit) \brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate \param [in] op1 Value to rotate
\param [in] value Number of Bits to rotate \param [in] op2 Number of Bits to rotate
\return Rotated value \return Rotated value
*/ */
#define __ROR __ror #define __ROR __ror
@ -433,23 +509,24 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] value Value to reverse \param [in] value Value to reverse
\return Reversed value \return Reversed value
*/ */
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit #define __RBIT __rbit
#else #else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{ {
uint32_t result; uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */ result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U) for (value >>= 1U; value != 0U; value >>= 1U)
{ {
result <<= 1U; result <<= 1U;
result |= value & 1U; result |= value & 1U;
s--; s--;
} }
result <<= s; /* shift when v's highest bits are zero */ result <<= s; /* shift when v's highest bits are zero */
return(result); return result;
} }
#endif #endif
@ -463,7 +540,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __CLZ __clz #define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/** /**
\brief LDR Exclusive (8 bit) \brief LDR Exclusive (8 bit)
@ -645,7 +723,60 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/ */
#define __STRT(value, ptr) __strt(value, ptr) #define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
@ -656,7 +787,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
@{ @{
*/ */
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8 #define __SADD8 __sadd8
#define __QADD8 __qadd8 #define __QADD8 __qadd8
@ -727,7 +858,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U)) ((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */ #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */ /*@} end of group CMSIS_SIMD_intrinsics */

937
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Prog/lib/CMSIS/Include/cmsis_armcc_V6.h → Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Include/cmsis_armclang.h
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Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Include/cmsis_compiler.h Normal file
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@ -0,0 +1,266 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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@ -0,0 +1,935 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

39
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Include/cmsis_version.h Normal file
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@ -0,0 +1,39 @@
/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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399
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Include/core_cm0.h
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@ -1,40 +1,30 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_cm0.h * @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V4.30 * @version V5.0.5
* @date 20. October 2015 * @date 28. May 2018
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED /*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
All rights reserved. *
Redistribution and use in source and binary forms, with or without * SPDX-License-Identifier: Apache-2.0
modification, are permitted provided that the following conditions are met: *
- Redistributions of source code must retain the above copyright * Licensed under the Apache License, Version 2.0 (the License); you may
notice, this list of conditions and the following disclaimer. * not use this file except in compliance with the License.
- Redistributions in binary form must reproduce the above copyright * You may obtain a copy of the License at
notice, this list of conditions and the following disclaimer in the *
documentation and/or other materials provided with the distribution. * www.apache.org/licenses/LICENSE-2.0
- Neither the name of ARM nor the names of its contributors may be used *
to endorse or promote products derived from this software without * Unless required by applicable law or agreed to in writing, software
specific prior written permission. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * See the License for the specific language governing permissions and
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * limitations under the License.
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
@ -70,53 +60,15 @@
@{ @{
*/ */
#include "cmsis_version.h"
/* CMSIS CM0 definitions */ /* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ #define __CORTEX_M (0U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not. /** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all This core does not support an FPU at all
@ -128,7 +80,7 @@
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP #if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
@ -143,7 +95,7 @@
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TMS470__ ) #elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__ #if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
@ -160,8 +112,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */ #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@ -555,18 +507,18 @@ typedef struct
/** /**
\brief Mask and shift a bit field value for use in a register bit range. \brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field. \param[in] field Name of the register bit field.
\param[in] value Value of the bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value. \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/** /**
\brief Mask and shift a register value to extract a bit filed value. \brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field. \param[in] field Name of the register bit field.
\param[in] value Value of register. \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value. \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
@ -578,7 +530,7 @@ typedef struct
@{ @{
*/ */
/* Memory mapping of Cortex-M0 Hardware */ /* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
@ -614,87 +566,177 @@ typedef struct
@{ @{
*/ */
/* Interrupt Priorities are WORD accessible only under ARMv6M */ #ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */ /* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/** /**
\brief Enable External Interrupt \brief Enable Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Disable External Interrupt \brief Get Interrupt Enable status
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
} }
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Interrupt number. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{ {
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
} }
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
\details Sets the priority of an interrupt. \details Sets the priority of a device specific interrupt or a processor exception.
\note The priority cannot be set for every core interrupt. The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{ {
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) >= 0)
{ {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
else else
{ {
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
} }
@ -702,24 +744,108 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify an external (device specific) interrupt, The interrupt number can be positive to specify a device specific interrupt,
or negative to specify an internal (core) interrupt. or negative to specify a processor exception.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{ {
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{ {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} }
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
} }
@ -727,7 +853,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{ {
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
@ -744,6 +870,31 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
@ -753,7 +904,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
@{ @{
*/ */
#if (__Vendor_SysTickConfig == 0U) #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/** /**
\brief System Tick Configuration \brief System Tick Configuration

425
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Include/core_cm0plus.h
View File

@ -1,40 +1,30 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_cm0plus.h * @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V4.30 * @version V5.0.6
* @date 20. October 2015 * @date 28. May 2018
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED /*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
All rights reserved. *
Redistribution and use in source and binary forms, with or without * SPDX-License-Identifier: Apache-2.0
modification, are permitted provided that the following conditions are met: *
- Redistributions of source code must retain the above copyright * Licensed under the Apache License, Version 2.0 (the License); you may
notice, this list of conditions and the following disclaimer. * not use this file except in compliance with the License.
- Redistributions in binary form must reproduce the above copyright * You may obtain a copy of the License at
notice, this list of conditions and the following disclaimer in the *
documentation and/or other materials provided with the distribution. * www.apache.org/licenses/LICENSE-2.0
- Neither the name of ARM nor the names of its contributors may be used *
to endorse or promote products derived from this software without * Unless required by applicable law or agreed to in writing, software
specific prior written permission. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * See the License for the specific language governing permissions and
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * limitations under the License.
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
@ -70,53 +60,15 @@
@{ @{
*/ */
#include "cmsis_version.h"
/* CMSIS CM0+ definitions */ /* CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ #define __CORTEX_M (0U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not. /** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all This core does not support an FPU at all
@ -128,7 +80,7 @@
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP #if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
@ -143,7 +95,7 @@
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TMS470__ ) #elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__ #if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
@ -160,8 +112,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */ #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@ -404,7 +356,7 @@ typedef struct
{ {
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1U) #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else #else
uint32_t RESERVED0; uint32_t RESERVED0;
@ -461,7 +413,7 @@ typedef struct
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1U) #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
/* SCB Interrupt Control State Register Definitions */ /* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
@ -558,7 +510,7 @@ typedef struct
/*@} end of group CMSIS_SysTick */ /*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1U) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU) \defgroup CMSIS_MPU Memory Protection Unit (MPU)
@ -578,6 +530,8 @@ typedef struct
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type; } MPU_Type;
#define MPU_TYPE_RALIASES 1U
/* MPU Type Register Definitions */ /* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
@ -667,18 +621,18 @@ typedef struct
/** /**
\brief Mask and shift a bit field value for use in a register bit range. \brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field. \param[in] field Name of the register bit field.
\param[in] value Value of the bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value. \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/** /**
\brief Mask and shift a register value to extract a bit filed value. \brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field. \param[in] field Name of the register bit field.
\param[in] value Value of register. \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value. \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
@ -690,7 +644,7 @@ typedef struct
@{ @{
*/ */
/* Memory mapping of Cortex-M0+ Hardware */ /* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
@ -700,7 +654,7 @@ typedef struct
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif #endif
@ -730,87 +684,177 @@ typedef struct
@{ @{
*/ */
/* Interrupt Priorities are WORD accessible only under ARMv6M */ #ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */ /* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/** /**
\brief Enable External Interrupt \brief Enable Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Disable External Interrupt \brief Get Interrupt Enable status
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
} }
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Interrupt number. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{ {
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
} }
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
\details Sets the priority of an interrupt. \details Sets the priority of a device specific interrupt or a processor exception.
\note The priority cannot be set for every core interrupt. The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{ {
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) >= 0)
{ {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
else else
{ {
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
} }
@ -818,24 +862,117 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify an external (device specific) interrupt, The interrupt number can be positive to specify a device specific interrupt,
or negative to specify an internal (core) interrupt. or negative to specify a processor exception.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{ {
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{ {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} }
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
If VTOR is not present address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
#else
uint32_t *vectors = (uint32_t *)0x0U;
#endif
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
uint32_t *vectors = (uint32_t *)SCB->VTOR;
#else
uint32_t *vectors = (uint32_t *)0x0U;
#endif
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
} }
@ -843,7 +980,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{ {
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
@ -859,6 +996,38 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv7.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
@ -869,7 +1038,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
@{ @{
*/ */
#if (__Vendor_SysTickConfig == 0U) #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/** /**
\brief System Tick Configuration \brief System Tick Configuration

976
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Include/core_cm1.h Normal file
View File

@ -0,0 +1,976 @@
/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.0
* @date 23. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

1993
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482
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Include/core_cm3.h
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@ -1,40 +1,30 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_cm3.h * @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V4.30 * @version V5.0.8
* @date 20. October 2015 * @date 04. June 2018
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED /*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
All rights reserved. *
Redistribution and use in source and binary forms, with or without * SPDX-License-Identifier: Apache-2.0
modification, are permitted provided that the following conditions are met: *
- Redistributions of source code must retain the above copyright * Licensed under the Apache License, Version 2.0 (the License); you may
notice, this list of conditions and the following disclaimer. * not use this file except in compliance with the License.
- Redistributions in binary form must reproduce the above copyright * You may obtain a copy of the License at
notice, this list of conditions and the following disclaimer in the *
documentation and/or other materials provided with the distribution. * www.apache.org/licenses/LICENSE-2.0
- Neither the name of ARM nor the names of its contributors may be used *
to endorse or promote products derived from this software without * Unless required by applicable law or agreed to in writing, software
specific prior written permission. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * See the License for the specific language governing permissions and
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * limitations under the License.
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
@ -70,53 +60,15 @@
@{ @{
*/ */
#include "cmsis_version.h"
/* CMSIS CM3 definitions */ /* CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
__CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ #define __CORTEX_M (3U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not. /** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all This core does not support an FPU at all
@ -128,7 +80,7 @@
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP #if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
@ -143,7 +95,7 @@
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TMS470__ ) #elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__ #if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
@ -160,8 +112,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */ #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@ -191,7 +143,7 @@
#endif #endif
#ifndef __NVIC_PRIO_BITS #ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 4U #define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif #endif
@ -308,9 +260,11 @@ typedef union
struct struct
{ {
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit */
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
@ -336,12 +290,15 @@ typedef union
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
@ -487,7 +444,7 @@ typedef struct
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */ /* SCB Vector Table Offset Register Definitions */
#if (__CM3_REV < 0x0201U) /* core r2p1 */ #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
@ -602,6 +559,60 @@ typedef struct
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */ /* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
@ -645,7 +656,7 @@ typedef struct
{ {
uint32_t RESERVED0[1U]; uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) #if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
#else #else
uint32_t RESERVED1[1U]; uint32_t RESERVED1[1U];
@ -770,7 +781,7 @@ typedef struct
/* ITM Trace Privilege Register Definitions */ /* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */ /* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
@ -984,7 +995,7 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U]; uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
@ -995,7 +1006,7 @@ typedef struct
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U]; uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U]; uint32_t RESERVED4[1U];
@ -1065,8 +1076,11 @@ typedef struct
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */ /* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */ /* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
@ -1091,12 +1105,15 @@ typedef struct
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */ /* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */ /* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */ /* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
@ -1118,16 +1135,16 @@ typedef struct
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */ /* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */ /*@}*/ /* end of group CMSIS_TPI */
#if (__MPU_PRESENT == 1U) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU) \defgroup CMSIS_MPU Memory Protection Unit (MPU)
@ -1153,6 +1170,8 @@ typedef struct
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
} MPU_Type; } MPU_Type;
#define MPU_TYPE_RALIASES 4U
/* MPU Type Register Definitions */ /* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
@ -1337,18 +1356,18 @@ typedef struct
/** /**
\brief Mask and shift a bit field value for use in a register bit range. \brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field. \param[in] field Name of the register bit field.
\param[in] value Value of the bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value. \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/** /**
\brief Mask and shift a register value to extract a bit filed value. \brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field. \param[in] field Name of the register bit field.
\param[in] value Value of register. \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value. \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
@ -1360,7 +1379,7 @@ typedef struct
@{ @{
*/ */
/* Memory mapping of Cortex-M3 Hardware */ /* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
@ -1379,7 +1398,7 @@ typedef struct
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#if (__MPU_PRESENT == 1U) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif #endif
@ -1410,6 +1429,45 @@ typedef struct
@{ @{
*/ */
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/** /**
\brief Set Priority Grouping \brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence. \details Sets the priority grouping field using the required unlock sequence.
@ -1419,7 +1477,7 @@ typedef struct
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field. \param [in] PriorityGroup Priority grouping field.
*/ */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{ {
uint32_t reg_value; uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
@ -1428,7 +1486,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value | reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value; SCB->AIRCR = reg_value;
} }
@ -1438,121 +1496,178 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
\details Reads the priority grouping field from the NVIC Interrupt Controller. \details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{ {
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
} }
/** /**
\brief Enable External Interrupt \brief Enable Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Disable External Interrupt \brief Get Interrupt Enable status
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
} }
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Interrupt number. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{ {
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
} }
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Get Active Interrupt \brief Get Active Interrupt
\details Reads the active register in NVIC and returns the active bit. \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Interrupt number. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active. \return 0 Interrupt status is not active.
\return 1 Interrupt status is active. \return 1 Interrupt status is active.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{ {
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
} }
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
\details Sets the priority of an interrupt. \details Sets the priority of a device specific interrupt or a processor exception.
\note The priority cannot be set for every core interrupt. The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{ {
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) >= 0)
{ {
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} }
else else
{ {
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify an external (device specific) interrupt, The interrupt number can be positive to specify a device specific interrupt,
or negative to specify an internal (core) interrupt. or negative to specify a processor exception.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{ {
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) >= 0)
{ {
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
} }
else else
{ {
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
} }
} }
@ -1609,11 +1724,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
} }
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{ {
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
@ -1630,6 +1776,38 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv7.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
@ -1640,7 +1818,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
@{ @{
*/ */
#if (__Vendor_SysTickConfig == 0U) #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/** /**
\brief System Tick Configuration \brief System Tick Configuration
@ -1683,8 +1861,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
@{ @{
*/ */
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/** /**

3002
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Include/core_cm33.h Normal file
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524
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Include/core_cm4.h
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@ -1,40 +1,30 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_cm4.h * @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
* @version V4.30 * @version V5.0.8
* @date 20. October 2015 * @date 04. June 2018
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED /*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
All rights reserved. *
Redistribution and use in source and binary forms, with or without * SPDX-License-Identifier: Apache-2.0
modification, are permitted provided that the following conditions are met: *
- Redistributions of source code must retain the above copyright * Licensed under the Apache License, Version 2.0 (the License); you may
notice, this list of conditions and the following disclaimer. * not use this file except in compliance with the License.
- Redistributions in binary form must reproduce the above copyright * You may obtain a copy of the License at
notice, this list of conditions and the following disclaimer in the *
documentation and/or other materials provided with the distribution. * www.apache.org/licenses/LICENSE-2.0
- Neither the name of ARM nor the names of its contributors may be used *
to endorse or promote products derived from this software without * Unless required by applicable law or agreed to in writing, software
specific prior written permission. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * See the License for the specific language governing permissions and
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * limitations under the License.
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
@ -70,60 +60,22 @@
@{ @{
*/ */
/* CMSIS CM4 definitions */ #include "cmsis_version.h"
#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ /* CMSIS CM4 definitions */
#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
__CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ #define __CORTEX_M (4U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not. /** __FPU_USED indicates whether an FPU is used or not.
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/ */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP #if defined __TARGET_FPU_VFP
#if (__FPU_PRESENT == 1U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U #define __FPU_USED 1U
#else #else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@ -133,9 +85,9 @@
#define __FPU_USED 0U #define __FPU_USED 0U
#endif #endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP #if defined __ARM_PCS_VFP
#if (__FPU_PRESENT == 1) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U #define __FPU_USED 1U
#else #else
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@ -147,7 +99,7 @@
#elif defined ( __GNUC__ ) #elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if (__FPU_PRESENT == 1U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U #define __FPU_USED 1U
#else #else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@ -159,7 +111,7 @@
#elif defined ( __ICCARM__ ) #elif defined ( __ICCARM__ )
#if defined __ARMVFP__ #if defined __ARMVFP__
#if (__FPU_PRESENT == 1U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U #define __FPU_USED 1U
#else #else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@ -169,9 +121,9 @@
#define __FPU_USED 0U #define __FPU_USED 0U
#endif #endif
#elif defined ( __TMS470__ ) #elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__ #if defined __TI_VFP_SUPPORT__
#if (__FPU_PRESENT == 1U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U #define __FPU_USED 1U
#else #else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@ -183,7 +135,7 @@
#elif defined ( __TASKING__ ) #elif defined ( __TASKING__ )
#if defined __FPU_VFP__ #if defined __FPU_VFP__
#if (__FPU_PRESENT == 1U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U #define __FPU_USED 1U
#else #else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@ -195,7 +147,7 @@
#elif defined ( __CSMC__ ) #elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U) #if ( __CSMC__ & 0x400U)
#if (__FPU_PRESENT == 1U) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U #define __FPU_USED 1U
#else #else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@ -207,9 +159,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */ #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#include "core_cmFunc.h" /* Core Function Access */
#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
#ifdef __cplusplus #ifdef __cplusplus
} }
@ -244,7 +195,7 @@
#endif #endif
#ifndef __NVIC_PRIO_BITS #ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 4U #define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif #endif
@ -367,11 +318,12 @@ typedef union
struct struct
{ {
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t T:1; /*!< bit: 24 Thumb bit */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
@ -397,8 +349,8 @@ typedef union
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
@ -406,6 +358,9 @@ typedef union
#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
@ -662,6 +617,66 @@ typedef struct
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */ /* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
@ -831,7 +846,7 @@ typedef struct
/* ITM Trace Privilege Register Definitions */ /* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */ /* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
@ -1045,7 +1060,7 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U]; uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
@ -1056,7 +1071,7 @@ typedef struct
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U]; uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U]; uint32_t RESERVED4[1U];
@ -1126,8 +1141,11 @@ typedef struct
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */ /* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */ /* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
@ -1152,12 +1170,15 @@ typedef struct
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */ /* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */ /* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */ /* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
@ -1179,16 +1200,16 @@ typedef struct
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */ /* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */ /*@}*/ /* end of group CMSIS_TPI */
#if (__MPU_PRESENT == 1U) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU) \defgroup CMSIS_MPU Memory Protection Unit (MPU)
@ -1214,6 +1235,8 @@ typedef struct
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
} MPU_Type; } MPU_Type;
#define MPU_TYPE_RALIASES 4U
/* MPU Type Register Definitions */ /* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
@ -1280,10 +1303,9 @@ typedef struct
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */ /*@} end of group CMSIS_MPU */
#endif #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
#if (__FPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_FPU Floating Point Unit (FPU) \defgroup CMSIS_FPU Floating Point Unit (FPU)
@ -1388,7 +1410,6 @@ typedef struct
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
/*@} end of group CMSIS_FPU */ /*@} end of group CMSIS_FPU */
#endif
/** /**
@ -1506,18 +1527,18 @@ typedef struct
/** /**
\brief Mask and shift a bit field value for use in a register bit range. \brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field. \param[in] field Name of the register bit field.
\param[in] value Value of the bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value. \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/** /**
\brief Mask and shift a register value to extract a bit filed value. \brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field. \param[in] field Name of the register bit field.
\param[in] value Value of register. \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value. \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
@ -1529,7 +1550,7 @@ typedef struct
@{ @{
*/ */
/* Memory mapping of Cortex-M4 Hardware */ /* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
@ -1548,15 +1569,13 @@ typedef struct
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#if (__MPU_PRESENT == 1U) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif #endif
#if (__FPU_PRESENT == 1U) #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
#endif
/*@} */ /*@} */
@ -1584,6 +1603,48 @@ typedef struct
@{ @{
*/ */
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
/** /**
\brief Set Priority Grouping \brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence. \details Sets the priority grouping field using the required unlock sequence.
@ -1593,7 +1654,7 @@ typedef struct
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field. \param [in] PriorityGroup Priority grouping field.
*/ */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{ {
uint32_t reg_value; uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
@ -1602,7 +1663,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value | reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
SCB->AIRCR = reg_value; SCB->AIRCR = reg_value;
} }
@ -1612,121 +1673,178 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
\details Reads the priority grouping field from the NVIC Interrupt Controller. \details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{ {
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
} }
/** /**
\brief Enable External Interrupt \brief Enable Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Disable External Interrupt \brief Get Interrupt Enable status
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
} }
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Interrupt number. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{ {
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
} }
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Get Active Interrupt \brief Get Active Interrupt
\details Reads the active register in NVIC and returns the active bit. \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Interrupt number. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active. \return 0 Interrupt status is not active.
\return 1 Interrupt status is active. \return 1 Interrupt status is active.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{ {
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
} }
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
\details Sets the priority of an interrupt. \details Sets the priority of a device specific interrupt or a processor exception.
\note The priority cannot be set for every core interrupt. The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{ {
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) >= 0)
{ {
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} }
else else
{ {
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify an external (device specific) interrupt, The interrupt number can be positive to specify a device specific interrupt,
or negative to specify an internal (core) interrupt. or negative to specify a processor exception.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{ {
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) >= 0)
{ {
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
} }
else else
{ {
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
} }
} }
@ -1783,11 +1901,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
} }
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{ {
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
@ -1804,6 +1953,49 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ########################## MPU functions #################################### */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#include "mpu_armv7.h"
#endif
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
uint32_t mvfr0;
mvfr0 = FPU->MVFR0;
if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
{
return 1U; /* Single precision FPU */
}
else
{
return 0U; /* No FPU */
}
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
@ -1814,7 +2006,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
@{ @{
*/ */
#if (__Vendor_SysTickConfig == 0U) #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/** /**
\brief System Tick Configuration \brief System Tick Configuration
@ -1857,8 +2049,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
@{ @{
*/ */
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/** /**

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@ -1,87 +0,0 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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@ -1,87 +0,0 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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@ -1,96 +0,0 @@
/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

348
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Include/core_sc000.h
View File

@ -1,40 +1,30 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_sc000.h * @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File * @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V4.30 * @version V5.0.5
* @date 20. October 2015 * @date 28. May 2018
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED /*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
All rights reserved. *
Redistribution and use in source and binary forms, with or without * SPDX-License-Identifier: Apache-2.0
modification, are permitted provided that the following conditions are met: *
- Redistributions of source code must retain the above copyright * Licensed under the Apache License, Version 2.0 (the License); you may
notice, this list of conditions and the following disclaimer. * not use this file except in compliance with the License.
- Redistributions in binary form must reproduce the above copyright * You may obtain a copy of the License at
notice, this list of conditions and the following disclaimer in the *
documentation and/or other materials provided with the distribution. * www.apache.org/licenses/LICENSE-2.0
- Neither the name of ARM nor the names of its contributors may be used *
to endorse or promote products derived from this software without * Unless required by applicable law or agreed to in writing, software
specific prior written permission. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * See the License for the specific language governing permissions and
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * limitations under the License.
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
@ -70,53 +60,15 @@
@{ @{
*/ */
#include "cmsis_version.h"
/* CMSIS SC000 definitions */ /* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_SC (000U) /*!< Cortex secure core */ #define __CORTEX_SC (000U) /*!< Cortex secure core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not. /** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all This core does not support an FPU at all
@ -128,7 +80,7 @@
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP #if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
@ -143,7 +95,7 @@
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TMS470__ ) #elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__ #if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
@ -160,8 +112,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */ #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@ -569,7 +521,7 @@ typedef struct
/*@} end of group CMSIS_SysTick */ /*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1U) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU) \defgroup CMSIS_MPU Memory Protection Unit (MPU)
@ -678,18 +630,18 @@ typedef struct
/** /**
\brief Mask and shift a bit field value for use in a register bit range. \brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field. \param[in] field Name of the register bit field.
\param[in] value Value of the bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value. \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/** /**
\brief Mask and shift a register value to extract a bit filed value. \brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field. \param[in] field Name of the register bit field.
\param[in] value Value of register. \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value. \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
@ -701,7 +653,7 @@ typedef struct
@{ @{
*/ */
/* Memory mapping of SC000 Hardware */ /* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
@ -712,7 +664,7 @@ typedef struct
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif #endif
@ -742,7 +694,46 @@ typedef struct
@{ @{
*/ */
/* Interrupt Priorities are WORD accessible only under ARMv6M */ #ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */ /* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
@ -750,79 +741,128 @@ typedef struct
/** /**
\brief Enable External Interrupt \brief Enable Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Disable External Interrupt \brief Get Interrupt Enable status
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
} }
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Interrupt number. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{ {
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
} }
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
\details Sets the priority of an interrupt. \details Sets the priority of a device specific interrupt or a processor exception.
\note The priority cannot be set for every core interrupt. The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{ {
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) >= 0)
{ {
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
else else
{ {
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
} }
} }
@ -830,24 +870,55 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify an external (device specific) interrupt, The interrupt number can be positive to specify a device specific interrupt,
or negative to specify an internal (core) interrupt. or negative to specify a processor exception.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{ {
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{ {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
} }
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
} }
@ -855,7 +926,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{ {
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
@ -872,6 +943,31 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
@ -881,7 +977,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
@{ @{
*/ */
#if (__Vendor_SysTickConfig == 0U) #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/** /**
\brief System Tick Configuration \brief System Tick Configuration

466
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Include/core_sc300.h
View File

@ -1,40 +1,30 @@
/**************************************************************************//** /**************************************************************************//**
* @file core_sc300.h * @file core_sc300.h
* @brief CMSIS SC300 Core Peripheral Access Layer Header File * @brief CMSIS SC300 Core Peripheral Access Layer Header File
* @version V4.30 * @version V5.0.6
* @date 20. October 2015 * @date 04. June 2018
******************************************************************************/ ******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED /*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
All rights reserved. *
Redistribution and use in source and binary forms, with or without * SPDX-License-Identifier: Apache-2.0
modification, are permitted provided that the following conditions are met: *
- Redistributions of source code must retain the above copyright * Licensed under the Apache License, Version 2.0 (the License); you may
notice, this list of conditions and the following disclaimer. * not use this file except in compliance with the License.
- Redistributions in binary form must reproduce the above copyright * You may obtain a copy of the License at
notice, this list of conditions and the following disclaimer in the *
documentation and/or other materials provided with the distribution. * www.apache.org/licenses/LICENSE-2.0
- Neither the name of ARM nor the names of its contributors may be used *
to endorse or promote products derived from this software without * Unless required by applicable law or agreed to in writing, software
specific prior written permission. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * See the License for the specific language governing permissions and
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * limitations under the License.
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
@ -70,53 +60,15 @@
@{ @{
*/ */
#include "cmsis_version.h"
/* CMSIS SC300 definitions */ /* CMSIS SC300 definitions */
#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ #define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
__SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_SC (300U) /*!< Cortex secure core */ #define __CORTEX_SC (300U) /*!< Cortex secure core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not. /** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all This core does not support an FPU at all
@ -128,7 +80,7 @@
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP #if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
@ -143,7 +95,7 @@
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
#elif defined ( __TMS470__ ) #elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__ #if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif #endif
@ -160,8 +112,8 @@
#endif #endif
#include "core_cmInstr.h" /* Core Instruction Access */ #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus #ifdef __cplusplus
} }
@ -191,7 +143,7 @@
#endif #endif
#ifndef __NVIC_PRIO_BITS #ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 4U #define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif #endif
@ -308,9 +260,11 @@ typedef union
struct struct
{ {
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit */
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
@ -336,12 +290,15 @@ typedef union
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */ #define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
@ -599,6 +556,60 @@ typedef struct
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
/* SCB Hard Fault Status Register Definitions */ /* SCB Hard Fault Status Register Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
@ -966,7 +977,7 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U]; uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
@ -977,7 +988,7 @@ typedef struct
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U]; uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
uint32_t RESERVED4[1U]; uint32_t RESERVED4[1U];
@ -1047,8 +1058,11 @@ typedef struct
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */ /* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */ /* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
@ -1073,12 +1087,15 @@ typedef struct
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */ /* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
/* TPI Integration Mode Control Register Definitions */ /* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */ /* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
@ -1100,16 +1117,16 @@ typedef struct
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */ /* TPI DEVTYPE Register Definitions */
#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
/*@}*/ /* end of group CMSIS_TPI */ /*@}*/ /* end of group CMSIS_TPI */
#if (__MPU_PRESENT == 1U) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
/** /**
\ingroup CMSIS_core_register \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU) \defgroup CMSIS_MPU Memory Protection Unit (MPU)
@ -1319,18 +1336,18 @@ typedef struct
/** /**
\brief Mask and shift a bit field value for use in a register bit range. \brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field. \param[in] field Name of the register bit field.
\param[in] value Value of the bit field. \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value. \return Masked and shifted value.
*/ */
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/** /**
\brief Mask and shift a register value to extract a bit filed value. \brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field. \param[in] field Name of the register bit field.
\param[in] value Value of register. \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value. \return Masked and shifted bit field value.
*/ */
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */ /*@} end of group CMSIS_core_bitfield */
@ -1342,7 +1359,7 @@ typedef struct
@{ @{
*/ */
/* Memory mapping of Cortex-M3 Hardware */ /* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
@ -1361,7 +1378,7 @@ typedef struct
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#if (__MPU_PRESENT == 1U) #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif #endif
@ -1392,6 +1409,46 @@ typedef struct
@{ @{
*/ */
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/** /**
\brief Set Priority Grouping \brief Set Priority Grouping
\details Sets the priority grouping field using the required unlock sequence. \details Sets the priority grouping field using the required unlock sequence.
@ -1401,7 +1458,7 @@ typedef struct
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field. \param [in] PriorityGroup Priority grouping field.
*/ */
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{ {
uint32_t reg_value; uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
@ -1420,121 +1477,178 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
\details Reads the priority grouping field from the NVIC Interrupt Controller. \details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{ {
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
} }
/** /**
\brief Enable External Interrupt \brief Enable Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller. \details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Disable External Interrupt \brief Get Interrupt Enable status
\details Disables a device-specific interrupt in the NVIC interrupt controller. \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{ {
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
} }
/** /**
\brief Get Pending Interrupt \brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Interrupt number. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending. \return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending. \return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{ {
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
} }
/** /**
\brief Set Pending Interrupt \brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt. \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Clear Pending Interrupt \brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt. \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn External interrupt number. Value cannot be negative. \param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{ {
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
} }
/** /**
\brief Get Active Interrupt \brief Get Active Interrupt
\details Reads the active register in NVIC and returns the active bit. \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
\param [in] IRQn Interrupt number. \param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not active. \return 0 Interrupt status is not active.
\return 1 Interrupt status is active. \return 1 Interrupt status is active.
\note IRQn must not be negative.
*/ */
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{ {
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
} }
/** /**
\brief Set Interrupt Priority \brief Set Interrupt Priority
\details Sets the priority of an interrupt. \details Sets the priority of a device specific interrupt or a processor exception.
\note The priority cannot be set for every core interrupt. The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\param [in] priority Priority to set. \param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/ */
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{ {
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) >= 0)
{ {
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} }
else else
{ {
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
} }
} }
/** /**
\brief Get Interrupt Priority \brief Get Interrupt Priority
\details Reads the priority of an interrupt. \details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify an external (device specific) interrupt, The interrupt number can be positive to specify a device specific interrupt,
or negative to specify an internal (core) interrupt. or negative to specify a processor exception.
\param [in] IRQn Interrupt number. \param [in] IRQn Interrupt number.
\return Interrupt Priority. \return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller. Value is aligned automatically to the implemented priority bits of the microcontroller.
*/ */
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{ {
if ((int32_t)(IRQn) < 0) if ((int32_t)(IRQn) >= 0)
{ {
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
} }
else else
{ {
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
} }
} }
@ -1591,11 +1705,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
} }
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
VTOR must been relocated to SRAM before.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/** /**
\brief System Reset \brief System Reset
\details Initiates a system reset request to reset the MCU. \details Initiates a system reset request to reset the MCU.
*/ */
__STATIC_INLINE void NVIC_SystemReset(void) __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{ {
__DSB(); /* Ensure all outstanding memory accesses included __DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */ buffered write are completed before reset */
@ -1613,6 +1758,31 @@ __STATIC_INLINE void NVIC_SystemReset(void)
/*@} end of CMSIS_Core_NVICFunctions */ /*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */ /* ################################## SysTick function ############################################ */
/** /**
@ -1622,7 +1792,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
@{ @{
*/ */
#if (__Vendor_SysTickConfig == 0U) #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/** /**
\brief System Tick Configuration \brief System Tick Configuration
@ -1665,8 +1835,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
@{ @{
*/ */
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
/** /**

270
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/CMSIS/Include/mpu_armv7.h Normal file
View File

@ -0,0 +1,270 @@
/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if non-shareable) or 010b (if shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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@ -0,0 +1,333 @@
/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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@ -0,0 +1,70 @@
/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

1029
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75
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@ -7,29 +7,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -70,6 +54,27 @@
/** @defgroup HAL_Exported_Constants HAL Exported Constants /** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{ * @{
*/ */
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
typedef enum
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/**
* @}
*/
/**
* @}
*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region /** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region
* @brief SYSCFG registers bit address in the alias region * @brief SYSCFG registers bit address in the alias region
* @{ * @{
@ -847,6 +852,16 @@
*/ */
#endif /* SYSCFG_RCR_PAGE0 */ #endif /* SYSCFG_RCR_PAGE0 */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/** /**
* @} * @}
*/ */
@ -869,16 +884,30 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
* @} * @}
*/ */
/* Exported variables ---------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions * @brief HAL Control functions
* @{ * @{
*/ */
/* Peripheral Control functions ************************************************/ /* Peripheral Control functions ************************************************/
void HAL_IncTick(void); void HAL_IncTick(void);
void HAL_Delay(__IO uint32_t Delay); void HAL_Delay(uint32_t Delay);
void HAL_SuspendTick(void); void HAL_SuspendTick(void);
void HAL_ResumeTick(void); void HAL_ResumeTick(void);
uint32_t HAL_GetTick(void); uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void); uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void); uint32_t HAL_GetDEVID(void);

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

43
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@ -7,29 +7,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -47,7 +31,7 @@
#if defined USE_LEGACY #if defined USE_LEGACY
#include "Legacy/stm32_hal_legacy.h" #include "Legacy/stm32_hal_legacy.h"
#endif #endif
#include <stdio.h> #include <stddef.h>
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
@ -72,10 +56,13 @@ typedef enum
} HAL_LockTypeDef; } HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == BIT)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
do{ \ do{ \
@ -83,8 +70,6 @@ typedef enum
(__DMA_HANDLE_).Parent = (__HANDLE__); \ (__DMA_HANDLE_).Parent = (__HANDLE__); \
} while(0U) } while(0U)
#define UNUSED(x) ((void)(x))
/** @brief Reset the Handle's State field. /** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle. * @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose: * @note This macro can be used for the following purpose:
@ -123,7 +108,7 @@ typedef enum
}while (0U) }while (0U)
#endif /* USE_RTOS */ #endif /* USE_RTOS */
#if defined ( __GNUC__ ) #if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak #ifndef __weak
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#endif /* __weak */ #endif /* __weak */
@ -134,7 +119,7 @@ typedef enum
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__GNUC__) /* GNU Compiler */ #if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END #ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4))) #define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */ #endif /* __ALIGN_END */

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

404
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h Normal file
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@ -0,0 +1,404 @@
/**
******************************************************************************
* @file stm32f3xx_hal_exti.h
* @author MCD Application Team
* @brief Header file of EXTI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_EXTI_H
#define STM32F3xx_HAL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @defgroup EXTI EXTI
* @brief EXTI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
/**
* @brief HAL EXTI common Callback ID enumeration definition
*/
typedef enum
{
HAL_EXTI_COMMON_CB_ID = 0x00U
} EXTI_CallbackIDTypeDef;
/**
* @brief EXTI Handle structure definition
*/
typedef struct
{
uint32_t Line; /*!< Exti line number */
void (* PendingCallback)(void); /*!< Exti pending callback */
} EXTI_HandleTypeDef;
/**
* @brief EXTI Configuration structure definition
*/
typedef struct
{
uint32_t Line; /*!< The Exti line to be configured. This parameter
can be a value of @ref EXTI_Line */
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_Line EXTI Line
* @{
*/
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u) /*!< External interrupt line 0 */
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u) /*!< External interrupt line 1 */
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u) /*!< External interrupt line 2 */
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u) /*!< External interrupt line 3 */
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u) /*!< External interrupt line 4 */
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u) /*!< External interrupt line 5 */
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u) /*!< External interrupt line 6 */
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u) /*!< External interrupt line 7 */
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u) /*!< External interrupt line 8 */
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u) /*!< External interrupt line 9 */
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au) /*!< External interrupt line 10 */
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu) /*!< External interrupt line 11 */
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu) /*!< External interrupt line 12 */
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du) /*!< External interrupt line 13 */
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu) /*!< External interrupt line 14 */
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu) /*!< External interrupt line 15 */
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#if defined(EXTI_IMR_MR18)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
#else
#define EXTI_LINE_18 (EXTI_RESERVED | EXTI_REG1 | 0x12u)
#endif /* EXTI_IMR_MR18 */
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u) /*!< External interrupt line 19 Connected to the RTC tamper and Timestamps */
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u) /*!< External interrupt line 20 Connected to the RTC wakeup timer */
#if defined(EXTI_IMR_MR21)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u) /*!< External interrupt line 21 Connected to the Comparator 1 output */
#else
#define EXTI_LINE_21 (EXTI_RESERVED | EXTI_REG1 | 0x15u)
#endif /* EXTI_IMR_MR21 */
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u) /*!< External interrupt line 22 Connected to the Comparator 2 output */
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) /*!< External interrupt line 23 Connected to the internal I2C1 wakeup event */
#if defined(EXTI_IMR_MR24)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) /*!< External interrupt line 24 Connected to the internal I2C2 wakeup event */
#else
#define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u)
#endif /* EXTI_IMR_MR24 */
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) /*!< External interrupt line 25 Connected to the internal USART1 wakeup event */
#if defined(EXTI_IMR_MR26)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au) /*!< External interrupt line 26 Connected to the internal USART2 wakeup event */
#else
#define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au)
#endif /* EXTI_IMR_MR26 */
#if defined(EXTI_IMR_MR27)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu) /*!< External interrupt line 27 Connected to the internal I2C3 wakeup event */
#else
#define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)
#endif /* EXTI_IMR_MR27 */
#if defined(EXTI_IMR_MR28)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) /*!< External interrupt line 28 Connected to the internal USART3 wakeup event */
#else
#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
#endif /* EXTI_IMR_MR28 */
#if defined(EXTI_32_63_SUPPORT)
#if defined(EXTI_IMR_MR29)
#define EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du) /*!< External interrupt line 29 Connected to the Comparator 3 output */
#else
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
#endif /* EXTI_IMR_MR29 */
#if defined(EXTI_IMR_MR30)
#define EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu) /*!< External interrupt line 30 Connected to the Comparator 4 output */
#else
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#endif /* EXTI_IMR_MR30 */
#if defined(EXTI_IMR_MR31)
#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu) /*!< External interrupt line 31 Connected to the Comparator 5 output */
#else
#define EXTI_LINE_31 (EXTI_RESERVED | EXTI_REG1 | 0x1Fu)
#endif /* EXTI_IMR_MR31 */
#define EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u) /*!< External interrupt line 32 Connected to the Comparator 6 output */
#if defined(EXTI_IMR2_MR33)
#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u) /*!< External interrupt line 33 Connected to the Comparator 7 output */
#else
#define EXTI_LINE_33 (EXTI_RESERVED | EXTI_REG2 | 0x01u)
#endif /* EXTI_IMR2_MR33 */
#if defined(EXTI_IMR2_MR34)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u) /*!< External interrupt line 34 Connected to the USART4 output */
#else
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
#endif /* EXTI_IMR2_MR34 */
#if defined(EXTI_IMR2_MR35)
#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u) /*!< External interrupt line 35 Connected to the USART5 output */
#else
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
#endif /* EXTI_IMR2_MR35 */
#endif /* EXTI_32_63_SUPPORT */
/**
* @}
*/
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
#define EXTI_MODE_NONE 0x00000000u
#define EXTI_MODE_INTERRUPT 0x00000001u
#define EXTI_MODE_EVENT 0x00000002u
/**
* @}
*/
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
#define EXTI_TRIGGER_NONE 0x00000000u
#define EXTI_TRIGGER_RISING 0x00000001u
#define EXTI_TRIGGER_FALLING 0x00000002u
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000u
#define EXTI_GPIOB 0x00000001u
#define EXTI_GPIOC 0x00000002u
#define EXTI_GPIOD 0x00000003u
#if defined(GPIOE)
#define EXTI_GPIOE 0x00000004u
#endif /* GPIOE */
#define EXTI_GPIOF 0x00000005u
#if defined(GPIOG)
#define EXTI_GPIOG 0x00000006u
#endif /* GPIOG */
#if defined(GPIOH)
#define EXTI_GPIOH 0x00000007u
#endif /* GPIOH */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
* @{
*/
/**
* @}
*/
/* Private constants --------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24u
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI Register and bit usage
*/
#define EXTI_REG_SHIFT 16u
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define EXTI_PIN_MASK 0x0000001Fu
/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
/**
* @brief EXTI Mask for trigger possibilities
*/
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
#if defined(EXTI_32_63_SUPPORT)
#define EXTI_LINE_NB 36uL
#else
#define EXTI_LINE_NB 29uL
#endif /* EXTI_32_63_SUPPORT */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#if defined(GPIOH)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH))
#elif defined(GPIOE)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF))
#else
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOF))
#endif /* GPIOE */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
* @brief EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_EXTI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

30
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@ -6,31 +6,15 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ******************************************************************************
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/

39
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -322,17 +306,10 @@ typedef struct
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */ /* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) #if defined(STM32F302xE) || defined(STM32F303xE)
#define OB_WRP_PAGES32TO47MASK (0x00FF0000U) #define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
#define OB_WRP_PAGES48TO255MASK (0xFF000000U) #define OB_WRP_PAGES48TO255MASK (0xFF000000U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ #endif /* STM32F302xE || STM32F303xE */
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
#define OB_WRP_PAGES48TO127MASK (0xFF000000U)
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) \ #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) \
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \ || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \

32
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h
View File

@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -227,8 +211,8 @@ typedef enum
*/ */
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ #define IS_GPIO_PIN(__PIN__) (((((uint32_t)__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) ((((uint32_t)__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h
View File

@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

158
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h
View File

@ -6,36 +6,20 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_I2C_H #ifndef STM32F3xx_HAL_I2C_H
#define __STM32F3xx_HAL_I2C_H #define STM32F3xx_HAL_I2C_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -102,17 +86,17 @@ typedef struct
* 01 : Abort (Abort user request on going)\n * 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n * 10 : Timeout\n
* 11 : Error\n * 11 : Error\n
* b5 IP initilisation status\n * b5 Peripheral initialization status\n
* 0 : Reset (IP not initialized)\n * 0 : Reset (peripheral not initialized)\n
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n * b4 (not used)\n
* x : Should be set to 0\n * x : Should be set to 0\n
* b3\n * b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n * 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (IP in Address Listen Mode)\n * 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n * b2 Intrinsic process state\n
* 0 : Ready\n * 0 : Ready\n
* 1 : Busy (IP busy with some configuration or internal operations)\n * 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n * b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n * 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n * 1 : Busy (Rx operation ongoing)\n
@ -186,6 +170,11 @@ typedef enum
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ #define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ #define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ #define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/** /**
* @} * @}
*/ */
@ -226,7 +215,54 @@ typedef struct __I2C_HandleTypeDef
__IO uint32_t ErrorCode; /*!< I2C Error code */ __IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef; } I2C_HandleTypeDef;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief HAL I2C Callback ID enumeration definition
*/
typedef enum
{
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
} HAL_I2C_CallbackIDTypeDef;
/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -248,6 +284,13 @@ typedef struct __I2C_HandleTypeDef
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) #define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) #define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define I2C_OTHER_FRAME (0x000000AAU)
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/** /**
* @} * @}
*/ */
@ -335,9 +378,9 @@ typedef struct __I2C_HandleTypeDef
* @{ * @{
*/ */
#define I2C_NO_STARTSTOP (0x00000000U) #define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP I2C_CR2_STOP #define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) #define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE I2C_CR2_START #define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/** /**
* @} * @}
*/ */
@ -396,7 +439,15 @@ typedef struct __I2C_HandleTypeDef
* @param __HANDLE__ specifies the I2C Handle. * @param __HANDLE__ specifies the I2C Handle.
* @retval None * @retval None
*/ */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#endif
/** @brief Enable the specified I2C interrupt. /** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle. * @param __HANDLE__ specifies the I2C Handle.
@ -469,6 +520,7 @@ typedef struct __I2C_HandleTypeDef
* *
* @retval The new state of __FLAG__ (SET or RESET). * @retval The new state of __FLAG__ (SET or RESET).
*/ */
#define I2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. /** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
@ -528,6 +580,15 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
@ -553,10 +614,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
@ -568,6 +629,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
/** /**
* @} * @}
*/ */
@ -659,15 +725,20 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \ ((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME)) ((REQUEST) == I2C_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) #define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) #define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) #define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) #define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
@ -677,6 +748,9 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/** /**
* @} * @}
*/ */
@ -703,6 +777,6 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#endif #endif
#endif /* __STM32F3xx_HAL_I2C_H */ #endif /* STM32F3xx_HAL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

37
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@ -6,36 +6,20 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_I2C_EX_H #ifndef STM32F3xx_HAL_I2C_EX_H
#define __STM32F3xx_HAL_I2C_EX_H #define STM32F3xx_HAL_I2C_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -141,6 +125,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))) (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))
/** /**
* @} * @}
*/ */
@ -174,6 +161,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
} }
#endif #endif
#endif /* __STM32F3xx_HAL_I2C_EX_H */ #endif /* STM32F3xx_HAL_I2C_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

998
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@ -6,107 +6,39 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_PCD_EX_H #ifndef STM32F3xx_HAL_PCD_EX_H
#define __STM32F3xx_HAL_PCD_EX_H #define STM32F3xx_HAL_PCD_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if defined(STM32F302xE) || defined(STM32F303xE) || \
defined(STM32F302xC) || defined(STM32F303xC) || \
defined(STM32F302x8) || \
defined(STM32F373xC)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h" #include "stm32f3xx_hal_def.h"
#if defined (USB)
/** @addtogroup STM32F3xx_HAL_Driver /** @addtogroup STM32F3xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup PCDEx /** @addtogroup PCDEx
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/** @defgroup PCDEx_Exported_Macros PCD Extended Exported Macros
* @{
*/
/**
* @brief Gets address in an endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#if defined(STM32F302xC) || defined(STM32F303xC) || \
defined(STM32F373xC)
#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400U)))))
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400U)))))
#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400U)))))
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400U)))))
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \
PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
}
#endif /* STM32F302xC || STM32F303xC || */
/* STM32F373xC */
#if defined(STM32F302xE) || defined(STM32F303xE) || \
defined(STM32F302x8)
#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400U)))))
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400U)))))
#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400U)))))
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400U)))))
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum));\
PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
}
#endif /* STM32F302xE || STM32F303xE || */
/* STM32F302x8 */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{ * @{
@ -114,20 +46,18 @@
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @{ * @{
*/ */
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
uint32_t pmaadress); HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
uint32_t pmaadress);
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state); void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
/** void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
* @} void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
*/
/**
* @}
*/
/** /**
* @} * @}
@ -137,16 +67,20 @@ void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
* @} * @}
*/ */
#endif /* STM32F302xE || STM32F303xE || */ /**
/* STM32F302xC || STM32F303xC || */ * @}
/* STM32F302x8 || */ */
/* STM32F373xC */
/**
* @}
*/
#endif /* defined (USB) */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32F3xx_HAL_PCD_EX_H */ #endif /* STM32F3xx_HAL_PCD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

28
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

28
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

30
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -1703,7 +1687,7 @@ typedef struct
*/ */
/* Initialization and de-initialization functions ******************************/ /* Initialization and de-initialization functions ******************************/
void HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);

28
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

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@ -23,29 +23,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

28
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@ -22,29 +22,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

50
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -146,7 +130,7 @@ typedef struct
#endif /* LSE_VALUE */ #endif /* LSE_VALUE */
#if !defined (LSI_VALUE) #if !defined (LSI_VALUE)
#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ #define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */
#endif /* LSI_VALUE */ #endif /* LSI_VALUE */
/** /**
* @} * @}
@ -790,6 +774,7 @@ typedef struct
/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
* @{ * @{
*/ */
#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as main PLL entry clock source */
#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */
@ -2308,10 +2293,29 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMu
} }
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */ #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
/**
* @brief Configure PLL clock source
* @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource
* @param PLLSource This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_NONE
* @arg @ref LL_RCC_PLLSOURCE_HSI (*)
* @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
* @arg @ref LL_RCC_PLLSOURCE_HSE
* @arg @ref LL_RCC_PLLSOURCE_HSI48 (*)
*
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
}
/** /**
* @brief Get the oscillator used as PLL clock source. * @brief Get the oscillator used as PLL clock source.
* @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
* @retval Returned value can be one of the following values: * @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_NONE
* @arg @ref LL_RCC_PLLSOURCE_HSI (*) * @arg @ref LL_RCC_PLLSOURCE_HSI (*)
* @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*) * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
* @arg @ref LL_RCC_PLLSOURCE_HSE * @arg @ref LL_RCC_PLLSOURCE_HSE

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h
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@ -18,29 +18,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

221
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_usart.h
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@ -6,36 +6,20 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_LL_USART_H #ifndef STM32F3xx_LL_USART_H
#define __STM32F3xx_LL_USART_H #define STM32F3xx_LL_USART_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -58,13 +42,6 @@ extern "C" {
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/** @defgroup USART_LL_Private_Constants USART Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER) #if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros /** @defgroup USART_LL_Private_Macros USART Private Macros
@ -86,6 +63,7 @@ extern "C" {
*/ */
typedef struct typedef struct
{ {
uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
@ -171,7 +149,7 @@ typedef struct
*/ */
#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */ #define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected flag */
#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
@ -275,7 +253,7 @@ typedef struct
#else #else
#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ #define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ #define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
#endif #endif/* USART_7BITS_SUPPORT */
/** /**
* @} * @}
*/ */
@ -505,7 +483,8 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve * @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/ */
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\
+ ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/** /**
* @brief Compute USARTDIV value according to Peripheral Clock and * @brief Compute USARTDIV value according to Peripheral Clock and
@ -514,7 +493,7 @@ typedef struct
* @param __BAUDRATE__ Baud rate value to achieve * @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/ */
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/** /**
* @} * @}
@ -567,7 +546,7 @@ __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
} }
/** /**
@ -609,7 +588,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)); return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
} }
/** /**
@ -816,7 +795,7 @@ __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)); return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
} }
/** /**
@ -1004,7 +983,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
} }
/** /**
@ -1251,7 +1230,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)); return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
} }
/** /**
@ -1319,7 +1298,7 @@ __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)); return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
} }
/** /**
@ -1498,7 +1477,7 @@ __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
} }
/** /**
@ -1531,7 +1510,7 @@ __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS); return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
} }
/** /**
@ -1586,8 +1565,8 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
uint32_t BaudRate) uint32_t BaudRate)
{ {
register uint32_t usartdiv = 0x0U; uint32_t usartdiv;
register uint32_t brrtemp = 0x0U; register uint32_t brrtemp;
if (OverSampling == LL_USART_OVERSAMPLING_8) if (OverSampling == LL_USART_OVERSAMPLING_8)
{ {
@ -1617,16 +1596,20 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
*/ */
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
{ {
register uint32_t usartdiv = 0x0U; register uint32_t usartdiv;
register uint32_t brrresult = 0x0U; register uint32_t brrresult = 0x0U;
usartdiv = USARTx->BRR; usartdiv = USARTx->BRR;
if (OverSampling == LL_USART_OVERSAMPLING_8) if (usartdiv == 0U)
{ {
if ((usartdiv & 0xFFF7U) != 0U) /* Do not perform a division by 0 */
}
else if (OverSampling == LL_USART_OVERSAMPLING_8)
{
usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
if (usartdiv != 0U)
{ {
usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
brrresult = (PeriphClk * 2U) / usartdiv; brrresult = (PeriphClk * 2U) / usartdiv;
} }
} }
@ -1730,7 +1713,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
} }
/** /**
@ -1776,7 +1759,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{ {
MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
} }
/** /**
@ -1837,7 +1820,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
} }
/** /**
@ -1876,7 +1859,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
} }
/** /**
@ -1923,7 +1906,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR
*/ */
__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{ {
MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
} }
/** /**
@ -1952,7 +1935,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
{ {
MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos); MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
} }
/** /**
@ -2013,7 +1996,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
} }
/** /**
@ -2091,7 +2074,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
} }
/** /**
@ -2192,7 +2175,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)); return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
} }
/** /**
@ -2263,7 +2246,8 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
{ {
/* In Asynchronous mode, the following bits must be kept cleared: /* In Asynchronous mode, the following bits must be kept cleared:
- LINEN, CLKEN bits in the USART_CR2 register, - LINEN, CLKEN bits in the USART_CR2 register,
- SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
} }
@ -2299,7 +2283,8 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
{ {
/* In Synchronous mode, the following bits must be kept cleared: /* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register, - LINEN bit in the USART_CR2 register,
- SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ - SCEN, IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
/* set the UART/USART in Synchronous mode */ /* set the UART/USART in Synchronous mode */
@ -2339,7 +2324,8 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
{ {
/* In LIN mode, the following bits must be kept cleared: /* In LIN mode, the following bits must be kept cleared:
- STOP and CLKEN bits in the USART_CR2 register, - STOP and CLKEN bits in the USART_CR2 register,
- IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
/* Set the UART/USART in LIN mode */ /* Set the UART/USART in LIN mode */
@ -2377,7 +2363,8 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
{ {
/* In Half Duplex mode, the following bits must be kept cleared: /* In Half Duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register, - LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/ - SCEN and IREN bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
/* set the UART/USART in Half Duplex mode */ /* set the UART/USART in Half Duplex mode */
@ -2417,7 +2404,8 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
{ {
/* In Smartcard mode, the following bits must be kept cleared: /* In Smartcard mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register, - LINEN bit in the USART_CR2 register,
- IREN and HDSEL bits in the USART_CR3 register.*/ - IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
/* Configure Stop bits to 1.5 bits */ /* Configure Stop bits to 1.5 bits */
@ -2460,7 +2448,8 @@ __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
{ {
/* In IRDA mode, the following bits must be kept cleared: /* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register, - LINEN, STOP and CLKEN bits in the USART_CR2 register,
- SCEN and HDSEL bits in the USART_CR3 register.*/ - SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* set the UART/USART in IRDA mode */ /* set the UART/USART in IRDA mode */
@ -2498,7 +2487,8 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
{ {
/* In Multi Processor mode, the following bits must be kept cleared: /* In Multi Processor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register, - LINEN and CLKEN bits in the USART_CR2 register,
- IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ - IREN, SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
} }
@ -2519,7 +2509,7 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)); return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
} }
/** /**
@ -2530,18 +2520,18 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)); return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
} }
/** /**
* @brief Check if the USART Noise error detected Flag is set or not * @brief Check if the USART Noise error detected Flag is set or not
* @rmtoll ISR NF LL_USART_IsActiveFlag_NE * @rmtoll ISR NE LL_USART_IsActiveFlag_NE
* @param USARTx USART Instance * @param USARTx USART Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)); return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
} }
/** /**
@ -2552,7 +2542,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)); return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
} }
/** /**
@ -2563,7 +2553,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)); return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
} }
/** /**
@ -2574,7 +2564,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)); return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
} }
/** /**
@ -2585,7 +2575,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)); return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
} }
/** /**
@ -2596,7 +2586,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)); return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
} }
/** /**
@ -2609,7 +2599,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)); return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
} }
/** /**
@ -2622,7 +2612,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)); return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
} }
/** /**
@ -2635,7 +2625,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)); return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
} }
/** /**
@ -2646,7 +2636,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)); return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
} }
/** /**
@ -2659,7 +2649,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)); return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
} }
/** /**
@ -2672,7 +2662,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)); return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
} }
/** /**
@ -2685,7 +2675,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)); return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
} }
/** /**
@ -2696,7 +2686,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)); return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
} }
/** /**
@ -2707,7 +2697,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)); return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
} }
/** /**
@ -2718,7 +2708,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)); return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
} }
/** /**
@ -2729,7 +2719,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)); return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
} }
/** /**
@ -2742,7 +2732,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)); return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
} }
/** /**
@ -2753,7 +2743,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)); return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
} }
/** /**
@ -2764,10 +2754,9 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)); return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
} }
/** /**
* @brief Clear Parity Error Flag * @brief Clear Parity Error Flag
* @rmtoll ICR PECF LL_USART_ClearFlag_PE * @rmtoll ICR PECF LL_USART_ClearFlag_PE
@ -2791,7 +2780,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
} }
/** /**
* @brief Clear Noise detected Flag * @brief Clear Noise Error detected Flag
* @rmtoll ICR NCF LL_USART_ClearFlag_NE * @rmtoll ICR NCF LL_USART_ClearFlag_NE
* @param USARTx USART Instance * @param USARTx USART Instance
* @retval None * @retval None
@ -3215,7 +3204,7 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
} }
/** /**
@ -3226,7 +3215,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U);
} }
/** /**
@ -3237,7 +3226,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
} }
/** /**
@ -3248,7 +3237,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U);
} }
/** /**
@ -3259,7 +3248,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
} }
/** /**
@ -3270,7 +3259,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)); return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
} }
/** /**
@ -3281,7 +3270,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)); return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
} }
/** /**
@ -3294,7 +3283,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)); return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
} }
/** /**
@ -3307,7 +3296,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
} }
/** /**
@ -3318,7 +3307,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
} }
/** /**
@ -3331,7 +3320,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
} }
/** /**
@ -3344,7 +3333,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)); return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
} }
@ -3386,7 +3375,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
} }
/** /**
@ -3419,7 +3408,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
} }
/** /**
@ -3452,7 +3441,7 @@ __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx) __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
{ {
return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)); return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
} }
/** /**
@ -3467,7 +3456,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx
*/ */
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
{ {
register uint32_t data_reg_addr = 0U; register uint32_t data_reg_addr;
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
{ {
@ -3499,7 +3488,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t
*/ */
__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
{ {
return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
} }
/** /**
@ -3534,7 +3523,7 @@ __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value
*/ */
__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
{ {
USARTx->TDR = Value & 0x1FFU; USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
} }
/** /**
@ -3555,7 +3544,7 @@ __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Valu
*/ */
__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) __STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
{ {
SET_BIT(USARTx->RQR, USART_RQR_ABRRQ); SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
} }
/** /**
@ -3566,7 +3555,7 @@ __STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
{ {
SET_BIT(USARTx->RQR, USART_RQR_SBKRQ); SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
} }
/** /**
@ -3577,18 +3566,20 @@ __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
{ {
SET_BIT(USARTx->RQR, USART_RQR_MMRQ); SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
} }
/** /**
* @brief Request a Receive Data flush * @brief Request a Receive Data flush
* @note Allows to discard the received data without reading them, and avoid an overrun
* condition.
* @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush
* @param USARTx USART Instance * @param USARTx USART Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
{ {
SET_BIT(USARTx->RQR, USART_RQR_RXFRQ); SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
} }
/** /**
@ -3601,7 +3592,7 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
*/ */
__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
{ {
SET_BIT(USARTx->RQR, USART_RQR_TXFRQ); SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
} }
/** /**
@ -3630,7 +3621,7 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS
* @} * @}
*/ */
#endif /* USART1 || USART2|| USART3 || UART4 || UART5 */ #endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
/** /**
* @} * @}
@ -3640,6 +3631,6 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS
} }
#endif #endif
#endif /* __STM32F3xx_LL_USART_H */ #endif /* STM32F3xx_LL_USART_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

248
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_usb.h Normal file
View File

@ -0,0 +1,248 @@
/**
******************************************************************************
* @file stm32f3xx_ll_usb.h
* @author MCD Application Team
* @brief Header file of USB Low Layer HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_LL_USB_H
#define STM32F3xx_LL_USB_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
#if defined (USB)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup USB_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief USB Mode definition
*/
typedef enum
{
USB_DEVICE_MODE = 0
} USB_ModeTypeDef;
/**
* @brief USB Initialization Structure definition
*/
typedef struct
{
uint32_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref USB_Core_Speed */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref USB_Core_PHY */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
} USB_CfgTypeDef;
typedef struct
{
uint8_t num; /*!< Endpoint number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t pmaadress; /*!< PMA Address
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr0; /*!< PMA Address0
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr1; /*!< PMA Address1
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint8_t doublebuffer; /*!< Double buffer enable
This parameter can be 0 or 1 */
uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral
This parameter is added to ensure compatibility across USB peripherals */
uint32_t maxpacket; /*!< Endpoint Max packet size
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
} USB_EPTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0U
#define DEP0CTL_MPS_32 1U
#define DEP0CTL_MPS_16 2U
#define DEP0CTL_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3U
/**
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_FS_SPEED 2U
/**
* @}
*/
#define BTABLE_ADDRESS 0x000U
#if defined(STM32F303xC) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F301x8) || defined(STM32F373xC) || defined(STM32F378xx) || defined(STM32F302xC)
#define PMA_ACCESS 2U
#endif /* STM32F303xC || */
/* STM32F303x8 || STM32F334x8 || */
/* STM32F301x8 || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F302x8)
#define PMA_ACCESS 1U
#endif /* STM32F302xE || STM32F303xE || */
/* STM32F302xC || */
/* STM32F302x8 */
#define EP_ADDR_MSK 0x7U
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
* @{
*/
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) */
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_LL_USB_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h
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@ -18,29 +18,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

141
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@ -21,31 +21,15 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ******************************************************************************
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@ -68,11 +52,11 @@
* @{ * @{
*/ */
/** /**
* @brief STM32F3xx HAL Driver version number V1.5.0 * @brief STM32F3xx HAL Driver version number V1.5.3
*/ */
#define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ #define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F3xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32F3xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\ #define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\ |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\
@ -85,11 +69,13 @@
*/ */
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Exported variables --------------------------------------------------------*/
/** @defgroup HAL_Private_Variables HAL Private Variables /** @defgroup HAL_Exported_Variables HAL Exported Variables
* @{ * @{
*/ */
__IO uint32_t uwTick; __IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/** /**
* @} * @}
*/ */
@ -109,12 +95,12 @@ __IO uint32_t uwTick;
=============================================================================== ===============================================================================
[..] This section provides functions allowing to: [..] This section provides functions allowing to:
(+) Initializes the Flash interface, the NVIC allocation and initial clock (+) Initializes the Flash interface, the NVIC allocation and initial clock
configuration. It initializes the source of time base also when timeout configuration. It initializes the systick also when timeout is needed
is needed and the backup domain when enabled. and the backup domain when enabled.
(+) de-Initializes common part of the HAL. (+) de-Initializes common part of the HAL.
(+) Configure The time base source to have 1ms time base with a dedicated (+) Configure The time base source to have 1ms time base with a dedicated
Tick interrupt priority. Tick interrupt priority.
(++) Systick timer is used by default as source of time base, but user (++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
@ -170,8 +156,7 @@ HAL_StatusTypeDef HAL_Init(void)
} }
/** /**
* @brief This function de-Initializes common part of the HAL and stops the source * @brief This function de-Initializes common part of the HAL and stops the systick.
* of time base.
* @note This function is optional. * @note This function is optional.
* @retval HAL status * @retval HAL status
*/ */
@ -195,23 +180,23 @@ HAL_StatusTypeDef HAL_DeInit(void)
} }
/** /**
* @brief Initializes the MSP. * @brief Initialize the MSP.
* @retval None * @retval None
*/ */
__weak void HAL_MspInit(void) __weak void HAL_MspInit(void)
{ {
/* NOTE : This function Should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file the HAL_MspInit could be implemented in the user file
*/ */
} }
/** /**
* @brief DeInitializes the MSP. * @brief DeInitialize the MSP.
* @retval None * @retval None
*/ */
__weak void HAL_MspDeInit(void) __weak void HAL_MspDeInit(void)
{ {
/* NOTE : This function Should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file the HAL_MspDeInit could be implemented in the user file
*/ */
} }
@ -225,7 +210,7 @@ __weak void HAL_MspDeInit(void)
* @note In the default implementation , SysTick timer is the source of time base. * @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals. * It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process, * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The the SysTick interrupt must have higher priority (numerically lower) * The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __Weak to be overwritten in case of other * The function is declared as __Weak to be overwritten in case of other
* implementation in user file. * implementation in user file.
@ -234,12 +219,22 @@ __weak void HAL_MspDeInit(void)
*/ */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{ {
/*Configure the SysTick to have interrupt in 1ms time basis*/ /* Configure the SysTick to have interrupt in 1ms time basis*/
HAL_SYSTICK_Config(SystemCoreClock / 1000U); if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
{
/*Configure the SysTick IRQ priority */ return HAL_ERROR;
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U); }
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority;
}
else
{
return HAL_ERROR;
}
/* Return function status */ /* Return function status */
return HAL_OK; return HAL_OK;
} }
@ -275,14 +270,14 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
* @brief This function is called to increment a global variable "uwTick" * @brief This function is called to increment a global variable "uwTick"
* used as application time base. * used as application time base.
* @note In the default implementation, this variable is incremented each 1ms * @note In the default implementation, this variable is incremented each 1ms
* in Systick ISR. * in SysTick ISR.
* @note This function is declared as __weak to be overwritten in case of other * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file. * implementations in user file.
* @retval None * @retval None
*/ */
__weak void HAL_IncTick(void) __weak void HAL_IncTick(void)
{ {
uwTick++; uwTick += uwTickFreq;
} }
/** /**
@ -296,6 +291,56 @@ __weak uint32_t HAL_GetTick(void)
return uwTick; return uwTick;
} }
/**
* @brief This function returns a tick priority.
* @retval tick priority
*/
uint32_t HAL_GetTickPrio(void)
{
return uwTickPrio;
}
/**
* @brief Set new tick Freq.
* @retval status
*/
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_TickFreqTypeDef prevTickFreq;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
/* Back up uwTickFreq frequency */
prevTickFreq = uwTickFreq;
/* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status != HAL_OK)
{
/* Restore previous tick frequency */
uwTickFreq = prevTickFreq;
}
}
return status;
}
/**
* @brief Return tick frequency.
* @retval tick period in Hz
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
return uwTickFreq;
}
/** /**
* @brief This function provides accurate delay (in milliseconds) based * @brief This function provides accurate delay (in milliseconds) based
* on variable incremented. * on variable incremented.
@ -307,15 +352,15 @@ __weak uint32_t HAL_GetTick(void)
* @param Delay specifies the delay time length, in milliseconds. * @param Delay specifies the delay time length, in milliseconds.
* @retval None * @retval None
*/ */
__weak void HAL_Delay(__IO uint32_t Delay) __weak void HAL_Delay(uint32_t Delay)
{ {
uint32_t tickstart = HAL_GetTick(); uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay; uint32_t wait = Delay;
/* Add a period to guarantee minimum wait */ /* Add freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY) if (wait < HAL_MAX_DELAY)
{ {
wait++; wait += (uint32_t)(uwTickFreq);
} }
while((HAL_GetTick() - tickstart) < wait) while((HAL_GetTick() - tickstart) < wait)
@ -360,7 +405,7 @@ __weak void HAL_ResumeTick(void)
/** /**
* @brief This function returns the HAL revision * @brief This function returns the HAL revision
* @retval version : 0xXYZR (8bits for each decimal, R for RC) * @retval version 0xXYZR (8bits for each decimal, R for RC)
*/ */
uint32_t HAL_GetHalVersion(void) uint32_t HAL_GetHalVersion(void)
{ {

30
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c
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@ -69,31 +69,15 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ******************************************************************************
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/ */
/* /*

90
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@ -63,29 +63,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -194,12 +178,6 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
DMA_CalcBaseAndBitshift(hdma); DMA_CalcBaseAndBitshift(hdma);
/* Clean callbacks */
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
/* Initialise the error code */ /* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE; hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@ -250,10 +228,16 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/* Clear all flags */ /* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
/* Initialize the error code */ /* Clean callbacks */
hdma->XferCpltCallback = NULL;
hdma->XferHalfCpltCallback = NULL;
hdma->XferErrorCallback = NULL;
hdma->XferAbortCallback = NULL;
/* Reset the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE; hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state */ /* Reset the DMA state */
hdma->State = HAL_DMA_STATE_RESET; hdma->State = HAL_DMA_STATE_RESET;
/* Release Lock */ /* Release Lock */
@ -394,27 +378,39 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
/** /**
* @brief Abort the DMA Transfer. * @brief Abort the DMA Transfer.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{ {
/* Disable DMA IT */ if(hdma->State != HAL_DMA_STATE_BUSY)
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); {
/* no transfer ongoing */
/* Disable the channel */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
hdma->Instance->CCR &= ~DMA_CCR_EN;
/* Process Unlocked */
/* Clear all flags */ __HAL_UNLOCK(hdma);
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
return HAL_ERROR;
/* Change the DMA state*/ }
hdma->State = HAL_DMA_STATE_READY; else
{
/* Process Unlocked */ /* Disable DMA IT */
__HAL_UNLOCK(hdma); hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
return HAL_OK; /* Disable the channel */
hdma->Instance->CCR &= ~DMA_CCR_EN;
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
}
/* Change the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_OK;
} }
/** /**

631
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c Normal file
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@ -0,0 +1,631 @@
/**
******************************************************************************
* @file stm32f3xx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt
(++) Event
(++) Both of them
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two different
interrupts pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected through multiplexer.
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rule:
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
* of bounds [0,3] in following API :
* HAL_EXTI_SetConfigLine
* HAL_EXTI_GetConfigLine
* HAL_EXTI_ClearConfigLine
*/
#ifdef HAL_EXTI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
#define EXTI_MODE_OFFSET 0x08u /* 0x20: offset between CPU IMR/EMR registers */
#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check parameters */
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* Compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
/* Configure rising trigger */
regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store rising trigger mode */
*regaddr = regval;
/* Configure falling trigger */
regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store falling trigger mode */
*regaddr = regval;
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
/* Configure interrupt mode : read current mode */
regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* Configure event mode : read current mode */
regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == NULL) || (pExtiConfig == NULL))
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Get core mode : interrupt */
regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
}
else
{
pExtiConfig->Mode = EXTI_MODE_NONE;
}
/* Get event mode */
regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
}
/* Get falling configuration */
regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
}
else
{
pExtiConfig->GPIOSel = 0x00u;
}
}
else
{
/* No Trigger selected */
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Clear interrupt mode */
regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 2] Clear event mode */
regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
{
regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* Get Gpio port selection for gpio lines */
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
{
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
SYSCFG->EXTICR[linepos >> 2u] = regval;
}
}
return HAL_OK;
}
/**
* @brief Register callback for a dedicated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
hexti->PendingCallback = pPendingCbfn;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(ExtiLine));
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t maskline;
uint32_t offset;
/* Compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending bit */
regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & maskline);
if (regval != 0x00u)
{
/* Clear pending bit */
EXTI->PR = maskline;
/* Call callback */
if (hexti->PendingCallback != NULL)
{
hexti->PendingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be checked.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* Get pending bit */
regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset));
/* return 1 if bit is set else 0 */
regval = ((*regaddr & maskline) >> linepos);
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be clear.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING_FALLING
* This parameter is kept for compatibility with other series.
* @retval None.
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
assert_param(IS_EXTI_PENDING_EDGE(Edge));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get pending bit */
regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset));
/* Clear Pending bit */
*regaddr = maskline;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
regaddr = (&EXTI->SWIER + (EXTI_CONFIG_OFFSET * offset));
*regaddr = maskline;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_EXTI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

50
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c
View File

@ -70,31 +70,15 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ******************************************************************************
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@ -171,7 +155,7 @@ extern void FLASH_PageErase(uint32_t PageAddress);
* @note If an erase and a program operations are requested simultaneously, * @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one. * the erase operation is performed before the program one.
* *
* @note FLASH should be previously erased before new programmation (only exception to this * @note FLASH should be previously erased before new programming (only exception to this
* is when 0x0000 is programmed) * is when 0x0000 is programmed)
* *
* @param TypeProgram Indicate the way to program at a specified address. * @param TypeProgram Indicate the way to program at a specified address.
@ -224,7 +208,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
/* If the program operation is completed, disable the PG Bit */ /* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG); CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
/* In case of error, stop programation procedure */ /* In case of error, stop programming procedure */
if (status != HAL_OK) if (status != HAL_OK)
{ {
break; break;
@ -495,18 +479,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
*/ */
HAL_StatusTypeDef HAL_FLASH_Unlock(void) HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{ {
if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK)) HAL_StatusTypeDef status = HAL_OK;
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
{ {
/* Authorize the FLASH Registers access */ /* Authorize the FLASH Registers access */
WRITE_REG(FLASH->KEYR, FLASH_KEY1); WRITE_REG(FLASH->KEYR, FLASH_KEY1);
WRITE_REG(FLASH->KEYR, FLASH_KEY2); WRITE_REG(FLASH->KEYR, FLASH_KEY2);
}
else /* Verify Flash is unlocked */
{ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
return HAL_ERROR; {
status = HAL_ERROR;
}
} }
return HAL_OK; return status;
} }
/** /**

58
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c
View File

@ -28,31 +28,15 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ******************************************************************************
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@ -915,32 +899,26 @@ static uint32_t FLASH_OB_GetRDP(void)
/* Read RDP level bits */ /* Read RDP level bits */
#if defined(FLASH_OBR_RDPRT) #if defined(FLASH_OBR_RDPRT)
tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
#endif #elif defined(FLASH_OBR_LEVEL1_PROT)
#if defined(FLASH_OBR_LEVEL1_PROT)
tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_LEVEL1_PROT | FLASH_OBR_LEVEL2_PROT)); tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_LEVEL1_PROT | FLASH_OBR_LEVEL2_PROT));
#endif /* FLASH_OBR_LEVEL1_PROT */ #endif /* FLASH_OBR_RDPRT */
#if defined(FLASH_OBR_RDPRT) #if defined(FLASH_OBR_RDPRT)
if (tmp_reg == FLASH_OBR_RDPRT_1) if (tmp_reg == FLASH_OBR_RDPRT_2)
#endif #elif defined(FLASH_OBR_LEVEL1_PROT)
#if defined(FLASH_OBR_LEVEL1_PROT) if (tmp_reg == FLASH_OBR_LEVEL2_PROT)
if (tmp_reg == FLASH_OBR_LEVEL1_PROT) #endif /* FLASH_OBR_RDPRT */
#endif /* FLASH_OBR_LEVEL1_PROT */
{
return OB_RDP_LEVEL_1;
}
#if defined(FLASH_OBR_RDPRT)
else if (tmp_reg == FLASH_OBR_RDPRT_2)
#elif defined(FLASH_OBR_LEVEL2_PROT)
else if (tmp_reg == FLASH_OBR_LEVEL2_PROT)
#endif
{ {
return OB_RDP_LEVEL_2; return OB_RDP_LEVEL_2;
} }
else else if (tmp_reg == 0U)
{ {
return OB_RDP_LEVEL_0; return OB_RDP_LEVEL_0;
} }
else
{
return OB_RDP_LEVEL_1;
}
} }
/** /**

167
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c
View File

@ -91,29 +91,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -130,6 +114,13 @@
* @{ * @{
*/ */
/** MISRA C:2012 deviation rule has been granted for following rules:
* Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
* which may be out of array bounds [..,UNKNOWN] in following APIs:
* HAL_GPIO_Init
* HAL_GPIO_DeInit
*/
#ifdef HAL_GPIO_MODULE_ENABLED #ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
@ -187,9 +178,9 @@
*/ */
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{ {
uint32_t position = 0x00U; uint32_t position = 0x00u;
uint32_t iocurrent = 0x00U; uint32_t iocurrent;
uint32_t temp = 0x00U; uint32_t temp;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
@ -198,12 +189,12 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */ /* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != RESET) while (((GPIO_Init->Pin) >> position) != 0x00u)
{ {
/* Get current io position */ /* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1U << position); iocurrent = (GPIO_Init->Pin) & (1uL << position);
if(iocurrent) if (iocurrent != 0x00u)
{ {
/*--------------------- GPIO Mode Configuration ------------------------*/ /*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */ /* In case of Alternate function mode selection */
@ -212,18 +203,18 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Check the Alternate function parameters */ /* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */ /* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3]; temp = GPIOx->AFR[position >> 3u];
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; temp &= ~(0xFu << ((position & 0x07u) * 4u));
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
GPIOx->AFR[position >> 3] = temp; GPIOx->AFR[position >> 3u] = temp;
} }
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER; temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
GPIOx->MODER = temp; GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */ /* In case of Output or Alternate function mode selection */
@ -234,21 +225,21 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */ /* Configure the IO Speed */
temp = GPIOx->OSPEEDR; temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
temp |= (GPIO_Init->Speed << (position * 2U)); temp |= (GPIO_Init->Speed << (position * 2u));
GPIOx->OSPEEDR = temp; GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */ /* Configure the IO Output Type */
temp = GPIOx->OTYPER; temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT_0 << position) ; temp &= ~(GPIO_OTYPER_OT_0 << position) ;
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
GPIOx->OTYPER = temp; GPIOx->OTYPER = temp;
} }
/* Activate the Pull-up or Pull down resistor for the current IO */ /* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR; temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
temp |= ((GPIO_Init->Pull) << (position * 2U)); temp |= ((GPIO_Init->Pull) << (position * 2u));
GPIOx->PUPDR = temp; GPIOx->PUPDR = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/ /*--------------------- EXTI Mode Configuration ------------------------*/
@ -258,14 +249,14 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Enable SYSCFG Clock */ /* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2]; temp = SYSCFG->EXTICR[position >> 2u];
temp &= ~((0x0FU) << (4U * (position & 0x03U))); temp &= ~(0x0FuL << (4u * (position & 0x03u)));
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
SYSCFG->EXTICR[position >> 2] = temp; SYSCFG->EXTICR[position >> 2u] = temp;
/* Clear EXTI line configuration */ /* Clear EXTI line configuration */
temp = EXTI->IMR; temp = EXTI->IMR;
temp &= ~((uint32_t)iocurrent); temp &= ~(iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{ {
temp |= iocurrent; temp |= iocurrent;
@ -273,7 +264,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
EXTI->IMR = temp; EXTI->IMR = temp;
temp = EXTI->EMR; temp = EXTI->EMR;
temp &= ~((uint32_t)iocurrent); temp &= ~(iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{ {
temp |= iocurrent; temp |= iocurrent;
@ -282,7 +273,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Clear Rising Falling edge configuration */ /* Clear Rising Falling edge configuration */
temp = EXTI->RTSR; temp = EXTI->RTSR;
temp &= ~((uint32_t)iocurrent); temp &= ~(iocurrent);
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
{ {
temp |= iocurrent; temp |= iocurrent;
@ -290,7 +281,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
EXTI->RTSR = temp; EXTI->RTSR = temp;
temp = EXTI->FTSR; temp = EXTI->FTSR;
temp &= ~((uint32_t)iocurrent); temp &= ~(iocurrent);
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
{ {
temp |= iocurrent; temp |= iocurrent;
@ -298,7 +289,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
EXTI->FTSR = temp; EXTI->FTSR = temp;
} }
} }
position++; position++;
} }
} }
@ -312,59 +303,59 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
*/ */
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{ {
uint32_t position = 0x00U; uint32_t position = 0x00u;
uint32_t iocurrent = 0x00U; uint32_t iocurrent;
uint32_t tmp = 0x00U; uint32_t tmp;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */ /* Configure the port pins */
while ((GPIO_Pin >> position) != RESET) while ((GPIO_Pin >> position) != 0x00u)
{ {
/* Get current io position */ /* Get current io position */
iocurrent = GPIO_Pin & (1U << position); iocurrent = (GPIO_Pin) & (1uL << position);
if (iocurrent) if (iocurrent != 0x00u)
{ {
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = SYSCFG->EXTICR[position >> 2u];
tmp &= (0x0FuL << (4u * (position & 0x03u)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
{
/* Clear EXTI line configuration */
EXTI->IMR &= ~((uint32_t)iocurrent);
EXTI->EMR &= ~((uint32_t)iocurrent);
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~((uint32_t)iocurrent);
EXTI->FTSR &= ~((uint32_t)iocurrent);
/* Configure the External Interrupt or event for the current IO */
tmp = 0x0FuL << (4u * (position & 0x03u));
SYSCFG->EXTICR[position >> 2u] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/ /*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO Direction in Input Floting Mode */ /* Configure IO Direction in Input Floating Mode */
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U)); GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u));
/* Configure the default Alternate Function in current IO */ /* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ;
/* Configure the default value for IO Speed */ /* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
/* Configure the default value IO Output Type */ /* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
tmp = SYSCFG->EXTICR[position >> 2];
tmp &= ((0x0FU) << (4U * (position & 0x03U)));
if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
tmp = (0x0FU) << (4U * (position & 0x03U));
SYSCFG->EXTICR[position >> 2] &= ~tmp;
/* Clear EXTI line configuration */
EXTI->IMR &= ~((uint32_t)iocurrent);
EXTI->EMR &= ~((uint32_t)iocurrent);
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~((uint32_t)iocurrent);
EXTI->FTSR &= ~((uint32_t)iocurrent);
}
} }
position++; position++;
} }
} }
@ -453,7 +444,14 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->ODR ^= GPIO_Pin; if ((GPIOx->ODR & GPIO_Pin) != 0X00u)
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
} }
/** /**
@ -483,10 +481,11 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
GPIOx->LCKR = GPIO_Pin; GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */ /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */
GPIOx->LCKR = tmp; GPIOx->LCKR = tmp;
/* Read LCKK bit*/ /* Read LCKK register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR; tmp = GPIOx->LCKR;
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) /* read again in order to confirm lock is active */
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
{ {
return HAL_OK; return HAL_OK;
} }
@ -504,7 +503,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{ {
/* EXTI line interrupt detected */ /* EXTI line interrupt detected */
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
{ {
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin);

3177
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c
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@ -17,7 +17,8 @@
(+) Possibility to disable or enable Analog Noise Filter (+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter (+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode (+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
##### How to use this driver ##### ##### How to use this driver #####
============================================================================== ==============================================================================
@ -34,29 +35,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -96,6 +81,7 @@
[..] This section provides functions allowing to: [..] This section provides functions allowing to:
(+) Configure Noise Filters (+) Configure Noise Filters
(+) Configure Wake Up Feature (+) Configure Wake Up Feature
(+) Configure Fast Mode Plus
@endverbatim @endverbatim
* @{ * @{
@ -154,7 +140,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t
*/ */
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{ {
uint32_t tmpreg = 0U; uint32_t tmpreg;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
@ -198,7 +184,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
} }
/** /**
* @brief Enable I2C wakeup from stop mode. * @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral. * the configuration information for the specified I2Cx peripheral.
* @retval HAL status * @retval HAL status
@ -237,7 +223,7 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
} }
/** /**
* @brief Disable I2C wakeup from stop mode. * @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral. * the configuration information for the specified I2Cx peripheral.
* @retval HAL status * @retval HAL status

1804
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd.c
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@ -2,37 +2,21 @@
****************************************************************************** ******************************************************************************
* @file stm32f3xx_hal_pcd_ex.c * @file stm32f3xx_hal_pcd_ex.c
* @author MCD Application Team * @author MCD Application Team
* @brief Extended PCD HAL module driver. * @brief PCD Extended HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller: * functionalities of the USB Peripheral Controller:
* + Configuration of the PMA for EP * + Extended features functions
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -40,13 +24,6 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h" #include "stm32f3xx_hal.h"
#ifdef HAL_PCD_MODULE_ENABLED
#if defined(STM32F302xE) || defined(STM32F303xE) || \
defined(STM32F302xC) || defined(STM32F303xC) || \
defined(STM32F302x8) || \
defined(STM32F373xC)
/** @addtogroup STM32F3xx_HAL_Driver /** @addtogroup STM32F3xx_HAL_Driver
* @{ * @{
*/ */
@ -56,254 +33,140 @@
* @{ * @{
*/ */
/* Private typedef -----------------------------------------------------------*/ #ifdef HAL_PCD_MODULE_ENABLED
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/ #if defined (USB)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{ * @{
*/ */
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions * @brief PCDEx control functions
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
##### Extended Peripheral Control functions ##### ##### Extended features functions #####
=============================================================================== ===============================================================================
[..] This section provides functions allowing to: [..] This section provides functions allowing to:
(+) Update PMA configuration (+) Update FIFO configuration
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Configure PMA for EP * @brief Configure PMA for EP
* @param hpcd PCD handle * @param hpcd Device instance
* @param ep_addr endpoint address * @param ep_addr endpoint address
* @param ep_kind endpoint Kind * @param ep_kind endpoint Kind
* @arg USB_SNG_BUF: Single Buffer used * USB_SNG_BUF: Single Buffer used
* @arg USB_DBL_BUF: Double Buffer used * USB_DBL_BUF: Double Buffer used
* @param pmaadress EP address in The PMA: In case of single buffer endpoint * @param pmaadress: EP address in The PMA: In case of single buffer endpoint
* this parameter is 16-bit value providing the address * this parameter is 16-bit value providing the address
* in PMA allocated to endpoint. * in PMA allocated to endpoint.
* In case of double buffer endpoint this parameter * In case of double buffer endpoint this parameter
* is a 32-bit value providing the endpoint buffer 0 address * is a 32-bit value providing the endpoint buffer 0 address
* in the LSB part of 32-bit value and endpoint buffer 1 address * in the LSB part of 32-bit value and endpoint buffer 1 address
* in the MSB part of 32-bit value. * in the MSB part of 32-bit value.
* @retval : status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr, uint16_t ep_addr,
uint16_t ep_kind, uint16_t ep_kind,
uint32_t pmaadress) uint32_t pmaadress)
{ {
PCD_EPTypeDef *ep; PCD_EPTypeDef *ep;
/* initialize ep structure*/ /* initialize ep structure*/
if ((0x80U & ep_addr) == 0x80U) if ((0x80U & ep_addr) == 0x80U)
{ {
ep = &hpcd->IN_ep[ep_addr & 0x7FU]; ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
} }
else else
{ {
ep = &hpcd->OUT_ep[ep_addr]; ep = &hpcd->OUT_ep[ep_addr];
} }
/* Here we check if the endpoint is single or double Buffer*/ /* Here we check if the endpoint is single or double Buffer*/
if (ep_kind == PCD_SNG_BUF) if (ep_kind == PCD_SNG_BUF)
{ {
/*Single Buffer*/ /* Single Buffer */
ep->doublebuffer = 0U; ep->doublebuffer = 0U;
/*Configure the PMA*/ /* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress; ep->pmaadress = (uint16_t)pmaadress;
} }
else /*USB_DBL_BUF*/ else /* USB_DBL_BUF */
{ {
/*Double Buffer Endpoint*/ /* Double Buffer Endpoint */
ep->doublebuffer = 1; ep->doublebuffer = 1U;
/*Configure the PMA*/ /* Configure the PMA */
ep->pmaaddr0 = pmaadress & 0xFFFFU; ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U; ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
} }
return HAL_OK;
}
/**
* @}
*/
/** return HAL_OK;
* @}
*/
/** @defgroup PCDEx_Private_Functions PCD Extended Private Functions
* @{
*/
#if defined(STM32F303xC) || \
defined(STM32F303x8) || defined(STM32F334x8) || \
defined(STM32F301x8) || \
defined(STM32F373xC) || defined(STM32F378xx) || \
defined(STM32F302xC)
/**
* @brief Copy a buffer from user memory area to packet memory area (PMA)
* @param USBx: USB peripheral instance register address.
* @param pbUsrBuf: pointer to user memory area.
* @param wPMABufAddr: address into PMA.
* @param wNBytes: no. of bytes to be copied.
* @retval None
*/
void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
uint32_t i, temp1, temp2;
uint16_t *pdwVal;
pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
for (i = n; i != 0; i--)
{
temp1 = (uint16_t) * pbUsrBuf;
pbUsrBuf++;
temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ;
*pdwVal++ = temp2;
pdwVal++;
pbUsrBuf++;
}
} }
/** /**
* @brief Copy a buffer from user memory area to packet memory area (PMA) * @brief Software Device Connection,
* @param USBx: USB peripheral instance register address. * this function is not required by USB OTG FS peripheral, it is used
* @param pbUsrBuf: pointer to user memory area. * only by USB Device FS peripheral.
* @param wPMABufAddr: address into PMA. * @param hpcd: PCD handle
* @param wNBytes: no. of bytes to be copied. * @param state: connection state (0 : disconnected / 1: connected)
* @retval None * @retval None
*/ */
void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
{
uint32_t n = (uint32_t)wNBytes >> 1U;
uint32_t i;
uint16_t *pdwVal;
uint32_t temp;
pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
for (i = n; i != 0U; i--)
{
temp = *pdwVal++;
*pbUsrBuf++ = ((temp >> 0) & 0xFF);
*pbUsrBuf++ = ((temp >> 8) & 0xFF);
pdwVal++;
}
if (wNBytes % 2)
{
temp = *pdwVal++;
*pbUsrBuf++ = ((temp >> 0) & 0xFF);
}
}
#endif /* STM32F303xC || */
/* STM32F303x8 || STM32F334x8 || */
/* STM32F301x8 || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || \
defined(STM32F302x8)
/**
* @brief Copy a buffer from user memory area to packet memory area (PMA)
* @param USBx: USB peripheral instance register address.
* @param pbUsrBuf: pointer to user memory area.
* @param wPMABufAddr: address into PMA.
* @param wNBytes: no. of bytes to be copied.
* @retval None
*/
void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
uint32_t i;
uint16_t temp1, temp2;
uint16_t *pdwVal;
pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
for (i = n; i != 0U; i--)
{
temp1 = (uint16_t) * pbUsrBuf;
pbUsrBuf++;
temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ;
*pdwVal++ = temp2;
pbUsrBuf++;
}
}
/**
* @brief Copy a buffer from user memory area to packet memory area (PMA)
* @param USBx: USB peripheral instance register address.
* @param pbUsrBuf: pointer to user memory area.
* @param wPMABufAddr: address into PMA.
* @param wNBytes: no. of bytes to be copied.
* @retval None
*/
void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = (uint32_t)wNBytes >> 1U;
uint32_t i;
uint16_t *pdwVal;
uint32_t temp;
pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
for (i = n; i != 0U; i--)
{
temp = *pdwVal++;
*pbUsrBuf++ = ((temp >> 0) & 0xFF);
*pbUsrBuf++ = ((temp >> 8) & 0xFF);
}
if (wNBytes % 2)
{
temp = *pdwVal++;
*pbUsrBuf++ = ((temp >> 0) & 0xFF);
}
}
#endif /* STM32F302xE || STM32F303xE || */
/* STM32F302xC || */
/* STM32F302x8 */
/**
* @}
*/
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @addtogroup PCDEx_Exported_Functions_Group2 Extended Initialization and de-initialization functions
* @{
*/
/**
* @brief Software Device Connection
* @param hpcd PCD handle
* @param state Device state
* @retval None
*/
__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
{ {
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(hpcd); UNUSED(hpcd);
UNUSED(state); UNUSED(state);
/* NOTE : This function Should not be modified, when the callback is needed, /* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCDEx_SetConnectionState could be implenetd in the user file the HAL_PCDEx_SetConnectionState could be implemented in the user file
*/ */
} }
/** /**
* @} * @brief Send LPM message to user layer callback.
*/ * @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_LPM_Callback could be implemented in the user file
*/
}
/**
* @brief Send BatteryCharging message to user layer callback.
* @param hpcd PCD handle
* @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_BCD_Callback could be implemented in the user file
*/
}
/** /**
* @} * @}
@ -312,16 +175,15 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui
/** /**
* @} * @}
*/ */
#endif /* defined (USB) */
/**
* @}
*/
#endif /* STM32F302xE || STM32F303xE || */
/* STM32F302xC || STM32F303xC || */
/* STM32F302x8 || */
/* STM32F373xC */
#endif /* HAL_PCD_MODULE_ENABLED */ #endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c
View File

@ -12,29 +12,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c
View File

@ -11,29 +11,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

207
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c
View File

@ -48,32 +48,16 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ******************************************************************************
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h" #include "stm32f3xx_hal.h"
@ -227,36 +211,92 @@ const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
* @note This function does not modify the configuration of the * @note This function does not modify the configuration of the
* - Peripheral clocks * - Peripheral clocks
* - LSI, LSE and RTC clocks * - LSI, LSE and RTC clocks
* @retval None * @retval HAL status
*/ */
void HAL_RCC_DeInit(void) HAL_StatusTypeDef HAL_RCC_DeInit(void)
{ {
/* Set HSION bit, HSITRIM[4:0] bits to the reset value*/ uint32_t tickstart = 0;
SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
/* Set HSION bit */
SET_BIT(RCC->CR, RCC_CR_HSION);
/* Insure HSIRDY bit is set before writing default HSITRIM value */
/* Get start tick */
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Set HSITRIM default value */
MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, RCC_CR_HSITRIM_4);
/* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */ /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */
CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO); CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO);
/* Insure HSI selected as system clock source */
/* Get start tick */
tickstart = HAL_GetTick();
/* Wait till system clock source is ready */
while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
{
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Update the SystemCoreClock global variable for HSI as system clock source */
SystemCoreClock = HSI_VALUE;
/* Configure the source of time base considering new system clock settings */
if(HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
}
/* Reset HSEON, CSSON, PLLON bits */ /* Reset HSEON, CSSON, PLLON bits */
CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
/* Reset HSEBYP bit */ /* Reset HSEBYP bit */
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
/* Insure PLLRDY is reset */
/* Get start tick */
tickstart = HAL_GetTick();
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
{
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Reset CFGR register */ /* Reset CFGR register */
CLEAR_REG(RCC->CFGR); CLEAR_REG(RCC->CFGR);
/* Reset CFGR2 register */ /* Reset CFGR2 register */
CLEAR_REG(RCC->CFGR2); CLEAR_REG(RCC->CFGR2);
/* Reset CFGR3 register */ /* Reset CFGR3 register */
CLEAR_REG(RCC->CFGR3); CLEAR_REG(RCC->CFGR3);
/* Clear all interrupt flags */
SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
/* Disable all interrupts */ /* Disable all interrupts */
CLEAR_REG(RCC->CIR); CLEAR_REG(RCC->CIR);
/* Update the SystemCoreClock global variable */ /* Reset all CSR flags */
SystemCoreClock = HSI_VALUE; __HAL_RCC_CLEAR_RESET_FLAGS();
return HAL_OK;
} }
/** /**
@ -275,10 +315,19 @@ void HAL_RCC_DeInit(void)
*/ */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{ {
uint32_t tickstart = 0U; uint32_t tickstart;
uint32_t pll_config;
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
uint32_t pll_config2;
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */ /* Check the parameters */
assert_param(RCC_OscInitStruct != NULL);
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/ /*------------------------------- HSE Configuration ------------------------*/
@ -593,10 +642,31 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
} }
else else
{ {
return HAL_ERROR; /* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
{
return HAL_ERROR;
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
pll_config2 = RCC->CFGR2;
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV))
#else
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
#endif
{
return HAL_ERROR;
}
}
} }
} }
return HAL_OK; return HAL_OK;
} }
@ -626,9 +696,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{ {
uint32_t tickstart = 0U; uint32_t tickstart = 0U;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */ /* Check the parameters */
assert_param(RCC_ClkInitStruct != NULL);
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
assert_param(IS_FLASH_LATENCY(FLatency)); assert_param(IS_FLASH_LATENCY(FLatency));
@ -637,14 +712,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
(HCLK) of the device. */ (HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */ /* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) if(FLatency > __HAL_FLASH_GET_LATENCY())
{ {
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency); __HAL_FLASH_SET_LATENCY(FLatency);
/* Check that the new number of wait states is taken into account to access the Flash /* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */ memory by reading the FLASH_ACR register */
if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) if(__HAL_FLASH_GET_LATENCY() != FLatency)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -689,51 +764,29 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
return HAL_ERROR; return HAL_ERROR;
} }
} }
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick */ /* Get Start Tick */
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
{ {
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
{ {
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) return HAL_TIMEOUT;
{
return HAL_TIMEOUT;
}
} }
} }
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) }
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */ /* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) if(FLatency < __HAL_FLASH_GET_LATENCY())
{ {
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency); __HAL_FLASH_SET_LATENCY(FLatency);
/* Check that the new number of wait states is taken into account to access the Flash /* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */ memory by reading the FLASH_ACR register */
if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) if(__HAL_FLASH_GET_LATENCY() != FLatency)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -757,7 +810,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
/* Configure the source of time base considering new system clocks settings*/ /* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY); HAL_InitTick (uwTickPrio);
return HAL_OK; return HAL_OK;
} }
@ -932,23 +985,23 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI) if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
{ {
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (HSE_VALUE / prediv) * pllmul; pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
} }
else else
{ {
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (HSI_VALUE >> 1U) * pllmul; pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
} }
#else #else
if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV) if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV)
{ {
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (HSE_VALUE / prediv) * pllmul; pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
} }
else else
{ {
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (HSI_VALUE / prediv) * pllmul; pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
} }
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
sysclockfreq = pllclk; sysclockfreq = pllclk;

32
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c
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@ -10,29 +10,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -114,6 +98,10 @@ static uint32_t RCC_GetPLLCLKFreq(void);
* order to modify the RTC Clock source, as consequence RTC registers (including * order to modify the RTC Clock source, as consequence RTC registers (including
* the backup registers) and RCC_BDCR register are set to their reset values. * the backup registers) and RCC_BDCR register are set to their reset values.
* *
* @note When the TIMx clock source is APB clock, so the TIMx clock is APB clock or
* APB clock x 2 depending on the APB prescaler.
* When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2.
*
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)

5433
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c
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28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

56
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -52,6 +36,22 @@
/** @addtogroup GPIO_LL /** @addtogroup GPIO_LL
* @{ * @{
*/ */
/** MISRA C:2012 deviation rule has been granted for following rules:
* Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
* range of the shift operator in following API :
* LL_GPIO_Init
* LL_GPIO_DeInit
* LL_GPIO_SetPinMode
* LL_GPIO_GetPinMode
* LL_GPIO_SetPinSpeed
* LL_GPIO_GetPinSpeed
* LL_GPIO_SetPinPull
* LL_GPIO_GetPinPull
* LL_GPIO_GetAFPin_0_7
* LL_GPIO_SetAFPin_0_7
* LL_GPIO_SetAFPin_8_15
* LL_GPIO_GetAFPin_8_15
*/
/* Private types -------------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
@ -60,7 +60,7 @@
/** @addtogroup GPIO_LL_Private_Macros /** @addtogroup GPIO_LL_Private_Macros
* @{ * @{
*/ */
#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) #define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ #define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
@ -193,8 +193,8 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
*/ */
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
{ {
uint32_t pinpos = 0x00000000U; uint32_t pinpos;
uint32_t currentpin = 0x00000000U; uint32_t currentpin;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
@ -207,12 +207,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
pinpos = POSITION_VAL(GPIO_InitStruct->Pin); pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
/* Configure the port pins */ /* Configure the port pins */
while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u)
{ {
/* Get current io position */ /* Get current io position */
currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos);
if (currentpin) if (currentpin != 0x00u)
{ {
/* Pin Mode configuration */ /* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);

63
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -239,24 +223,43 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void);
*/ */
ErrorStatus LL_RCC_DeInit(void) ErrorStatus LL_RCC_DeInit(void)
{ {
uint32_t vl_mask = 0U; __IO uint32_t vl_mask;
/* Set HSION bit */ /* Set HSION bit */
LL_RCC_HSI_Enable(); LL_RCC_HSI_Enable();
/* Wait for HSI READY bit */
while(LL_RCC_HSI_IsReady() != 1U)
{}
/* Set HSITRIM bits to the reset value*/ /* Set HSITRIM bits to the reset value*/
LL_RCC_HSI_SetCalibTrimming(0x10U); LL_RCC_HSI_SetCalibTrimming(0x10U);
/* Reset SW, HPRE, PPRE and MCOSEL bits */ /* Reset SW, HPRE, PPRE and MCOSEL bits */
vl_mask = 0xFFFFFFFFU; vl_mask = 0xFFFFFFFFU;
CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL)); CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 |\
RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL));
/* Write new value in CFGR register */
LL_RCC_WriteReg(CFGR, vl_mask); LL_RCC_WriteReg(CFGR, vl_mask);
/* Wait till system clock source is ready */
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
{}
/* Read CR register */
vl_mask = LL_RCC_ReadReg(CR);
/* Reset HSEON, CSSON, PLLON bits */ /* Reset HSEON, CSSON, PLLON bits */
vl_mask = 0xFFFFFFFFU;
CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON)); CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
/* Write new value in CR register */
LL_RCC_WriteReg(CR, vl_mask); LL_RCC_WriteReg(CR, vl_mask);
/* Wait for PLL READY bit to be reset */
while(LL_RCC_PLL_IsReady() != 0U)
{}
/* Reset HSEBYP bit */ /* Reset HSEBYP bit */
LL_RCC_HSE_DisableBypass(); LL_RCC_HSE_DisableBypass();
@ -270,12 +273,18 @@ ErrorStatus LL_RCC_DeInit(void)
LL_RCC_WriteReg(CFGR3, 0x00000000U); LL_RCC_WriteReg(CFGR3, 0x00000000U);
/* Clear pending flags */ /* Clear pending flags */
vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_CSSC); vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC |\
SET_BIT(RCC->CIR, vl_mask); LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_CSSC);
/* Write new value in CIR register */
LL_RCC_WriteReg(CIR, vl_mask);
/* Disable all interrupts */ /* Disable all interrupts */
LL_RCC_WriteReg(CIR, 0x00000000U); LL_RCC_WriteReg(CIR, 0x00000000U);
/* Clear reset flags */
LL_RCC_ClearResetFlags();
return SUCCESS; return SUCCESS;
} }

97
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usart.c
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@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -38,11 +22,11 @@
#include "stm32f3xx_ll_usart.h" #include "stm32f3xx_ll_usart.h"
#include "stm32f3xx_ll_rcc.h" #include "stm32f3xx_ll_rcc.h"
#include "stm32f3xx_ll_bus.h" #include "stm32f3xx_ll_bus.h"
#ifdef USE_FULL_ASSERT #ifdef USE_FULL_ASSERT
#include "stm32_assert.h" #include "stm32_assert.h"
#else #else
#define assert_param(expr) ((void)0U) #define assert_param(expr) ((void)0U)
#endif #endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F3xx_LL_Driver /** @addtogroup STM32F3xx_LL_Driver
* @{ * @{
@ -57,15 +41,6 @@
/* Private types -------------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros /** @addtogroup USART_LL_Private_Macros
* @{ * @{
@ -82,47 +57,47 @@
#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) #define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \ || ((__VALUE__) == LL_USART_DIRECTION_TX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
|| ((__VALUE__) == LL_USART_PARITY_EVEN) \ || ((__VALUE__) == LL_USART_PARITY_EVEN) \
|| ((__VALUE__) == LL_USART_PARITY_ODD)) || ((__VALUE__) == LL_USART_PARITY_ODD))
#if defined(USART_7BITS_SUPPORT) #if defined(USART_7BITS_SUPPORT)
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
|| ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B)) || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
#else #else
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \ #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B)) || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
#endif #endif /* USART_7BITS_SUPPORT */
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
|| ((__VALUE__) == LL_USART_OVERSAMPLING_8)) || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
|| ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
|| ((__VALUE__) == LL_USART_PHASE_2EDGE)) || ((__VALUE__) == LL_USART_PHASE_2EDGE))
#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
|| ((__VALUE__) == LL_USART_POLARITY_HIGH)) || ((__VALUE__) == LL_USART_POLARITY_HIGH))
#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
|| ((__VALUE__) == LL_USART_CLOCK_ENABLE)) || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
|| ((__VALUE__) == LL_USART_STOPBITS_1) \ || ((__VALUE__) == LL_USART_STOPBITS_1) \
|| ((__VALUE__) == LL_USART_STOPBITS_1_5) \ || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
|| ((__VALUE__) == LL_USART_STOPBITS_2)) || ((__VALUE__) == LL_USART_STOPBITS_2))
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
|| ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
/** /**
* @} * @}
@ -209,7 +184,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
* @brief Initialize USART registers according to the specified * @brief Initialize USART registers according to the specified
* parameters in USART_InitStruct. * parameters in USART_InitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance * @param USARTx USART Instance
* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
@ -222,7 +197,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
{ {
ErrorStatus status = ERROR; ErrorStatus status = ERROR;
uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
#if defined(STM32F303x8)||defined(STM32F334x8)||defined(STM32F328xx)||defined(STM32F301x8)||defined(STM32F302x8)||defined(STM32F318xx) #if (!defined(RCC_CFGR3_USART2SW)||!defined (RCC_CFGR3_USART3SW))
LL_RCC_ClocksTypeDef RCC_Clocks; LL_RCC_ClocksTypeDef RCC_Clocks;
#endif #endif
@ -275,7 +250,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
} }
else if (USARTx == USART2) else if (USARTx == USART2)
{ {
#if defined (RCC_CFGR3_USART2SW) #if defined(RCC_CFGR3_USART2SW)
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE); periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
#else #else
/* USART2 clock is PCLK */ /* USART2 clock is PCLK */
@ -285,7 +260,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
} }
else if (USARTx == USART3) else if (USARTx == USART3)
{ {
#if defined (RCC_CFGR3_USART3SW) #if defined(RCC_CFGR3_USART3SW)
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE); periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
#else #else
/* USART3 clock is PCLK */ /* USART3 clock is PCLK */
@ -326,7 +301,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
/* Check BRR is greater than or equal to 16d */ /* Check BRR is greater than or equal to 16d */
assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
/* Check BRR is greater than or equal to 16d */ /* Check BRR is lower than or equal to 0xFFFF */
assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
} }
} }
@ -338,7 +313,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
/** /**
* @brief Set each @ref LL_USART_InitTypeDef field to default value. * @brief Set each @ref LL_USART_InitTypeDef field to default value.
* @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
* whose fields will be set to default values. * whose fields will be set to default values.
* @retval None * @retval None
*/ */
@ -358,7 +333,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
* @brief Initialize USART Clock related settings according to the * @brief Initialize USART Clock related settings according to the
* specified parameters in the USART_ClockInitStruct. * specified parameters in the USART_ClockInitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance * @param USARTx USART Instance
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral. * that contains the Clock configuration information for the specified USART peripheral.
@ -422,7 +397,7 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef
/** /**
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* whose fields will be set to default values. * whose fields will be set to default values.
* @retval None * @retval None
*/ */
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
@ -446,7 +421,7 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
* @} * @}
*/ */
#endif /* USART1 || USART2|| USART3 || UART4 || UART5 */ #endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
/** /**
* @} * @}

886
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usb.c Normal file
View File

@ -0,0 +1,886 @@
/**
******************************************************************************
* @file stm32f3xx_ll_usb.c
* @author MCD Application Team
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Initialization/de-initialization functions
* + I/O operation functions
* + Peripheral Control functions
* + Peripheral State functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
(#) Call USB_CoreInit() API to initialize the USB Core peripheral.
(#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
/** @addtogroup STM32F3xx_LL_USB_DRIVER
* @{
*/
#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
#if defined (USB)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @brief Initializes the USB Core
* @param USBx: USB Instance
* @param cfg : pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(cfg);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_EnableGlobalInt
* Enables the controller's Global Int in the AHB Config reg
* @param USBx : Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
{
uint16_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Set interrupt mask */
USBx->CNTR |= winterruptmask;
return HAL_OK;
}
/**
* @brief USB_DisableGlobalInt
* Disable the controller's Global Int in the AHB Config reg
* @param USBx : Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
{
uint16_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Clear interrupt mask */
USBx->CNTR &= ~winterruptmask;
return HAL_OK;
}
/**
* @brief USB_SetCurrentMode : Set functional mode
* @param USBx : Selected device
* @param mode : current core mode
* This parameter can be one of the these values:
* @arg USB_DEVICE_MODE: Peripheral mode mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(mode);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_DevInit : Initializes the USB controller registers
* for device mode
* @param USBx : Selected device
* @param cfg : pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(cfg);
/* Init Device */
/*CNTR_FRES = 1*/
USBx->CNTR = USB_CNTR_FRES;
/*CNTR_FRES = 0*/
USBx->CNTR = 0;
/*Clear pending interrupts*/
USBx->ISTR = 0;
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
/* Enable USB Device Interrupt mask */
(void)USB_EnableGlobalInt(USBx);
return HAL_OK;
}
/**
* @brief USB_SetDevSpeed :Initializes the device speed
* depending on the PHY type and the enumeration speed of the device.
* @param USBx Selected device
* @param speed device speed
* @retval Hal status
*/
HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(speed);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_FlushTxFifo : Flush a Tx FIFO
* @param USBx : Selected device
* @param num : FIFO number
* This parameter can be a value from 1 to 15
15 means Flush all Tx FIFOs
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(num);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_FlushRxFifo : Flush Rx FIFO
* @param USBx : Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief Activate and configure an endpoint
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
HAL_StatusTypeDef ret = HAL_OK;
uint16_t wEpRegVal;
wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
/* initialize Endpoint */
switch (ep->type)
{
case EP_TYPE_CTRL:
wEpRegVal |= USB_EP_CONTROL;
break;
case EP_TYPE_BULK:
wEpRegVal |= USB_EP_BULK;
break;
case EP_TYPE_INTR:
wEpRegVal |= USB_EP_INTERRUPT;
break;
case EP_TYPE_ISOC:
wEpRegVal |= USB_EP_ISOCHRONOUS;
break;
default:
ret = HAL_ERROR;
break;
}
PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX);
PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
if (ep->doublebuffer == 0U)
{
if (ep->is_in != 0U)
{
/*Set the endpoint Transmit buffer address */
PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
if (ep->type != EP_TYPE_ISOC)
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
}
else
{
/*Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
/*Set the endpoint Receive buffer counter*/
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
PCD_CLEAR_RX_DTOG(USBx, ep->num);
/* Configure VALID status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
}
/*Double Buffer*/
else
{
/* Set the endpoint as double buffered */
PCD_SET_EP_DBUF(USBx, ep->num);
/* Set buffer address for double buffered mode */
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
if (ep->is_in == 0U)
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
/* Reset value of the data toggle bits for the endpoint out */
PCD_TX_DTOG(USBx, ep->num);
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
PCD_RX_DTOG(USBx, ep->num);
if (ep->type != EP_TYPE_ISOC)
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
}
else
{
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
}
return ret;
}
/**
* @brief De-activate and de-initialize an endpoint
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
if (ep->doublebuffer == 0U)
{
if (ep->is_in != 0U)
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
}
/*Double Buffer*/
else
{
if (ep->is_in == 0U)
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(USBx, ep->num);
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
PCD_RX_DTOG(USBx, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
}
return HAL_OK;
}
/**
* @brief USB_EPStartXfer : setup and starts a transfer over an EP
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
uint16_t pmabuffer;
uint32_t len;
/* IN endpoint */
if (ep->is_in == 1U)
{
/*Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
ep->xfer_len -= len;
}
else
{
len = ep->xfer_len;
ep->xfer_len = 0U;
}
/* configure and validate Tx endpoint */
if (ep->doublebuffer == 0U)
{
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
}
else
{
/* Write the data to the USB endpoint */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
}
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
}
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
}
else /* OUT endpoint */
{
/* Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
ep->xfer_len -= len;
}
else
{
len = ep->xfer_len;
ep->xfer_len = 0U;
}
/* configure and validate Rx endpoint */
if (ep->doublebuffer == 0U)
{
/*Set RX buffer count*/
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
}
else
{
/*Set the Double buffer counter*/
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
}
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
return HAL_OK;
}
/**
* @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
* with the EP/channel
* @param USBx : Selected device
* @param src : pointer to source buffer
* @param ch_ep_num : endpoint or host channel number
* @param len : Number of bytes to write
* @retval HAL status
*/
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(src);
UNUSED(ch_ep_num);
UNUSED(len);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_ReadPacket : read a packet from the Tx FIFO associated
* with the EP/channel
* @param USBx : Selected device
* @param dest : destination pointer
* @param len : Number of bytes to read
* @retval pointer to destination buffer
*/
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(dest);
UNUSED(len);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return ((void *)NULL);
}
/**
* @brief USB_EPSetStall : set a stall condition over an EP
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
if (ep->is_in != 0U)
{
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
}
else
{
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
}
return HAL_OK;
}
/**
* @brief USB_EPClearStall : Clear a stall condition over an EP
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
if (ep->doublebuffer == 0U)
{
if (ep->is_in != 0U)
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
if (ep->type != EP_TYPE_ISOC)
{
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
}
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
/* Configure VALID status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
}
return HAL_OK;
}
/**
* @brief USB_StopDevice : Stop the usb device mode
* @param USBx : Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
{
/* disable all interrupts and force USB reset */
USBx->CNTR = USB_CNTR_FRES;
/* clear interrupt status register */
USBx->ISTR = 0;
/* switch-off device */
USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
return HAL_OK;
}
/**
* @brief USB_SetDevAddress : Stop the usb device mode
* @param USBx : Selected device
* @param address : new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
{
if (address == 0U)
{
/* set device address and enable function */
USBx->DADDR = USB_DADDR_EF;
}
return HAL_OK;
}
/**
* @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
* @param USBx : Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
* @param USBx : Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_ReadInterrupts: return the global USB interrupt status
* @param USBx : Selected device
* @retval HAL status
*/
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
{
uint32_t tmpreg;
tmpreg = USBx->ISTR;
return tmpreg;
}
/**
* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
* @param USBx : Selected device
* @retval HAL status
*/
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return (0);
}
/**
* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
* @param USBx : Selected device
* @retval HAL status
*/
uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return (0);
}
/**
* @brief Returns Device OUT EP Interrupt register
* @param USBx : Selected device
* @param epnum : endpoint number
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(epnum);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return (0);
}
/**
* @brief Returns Device IN EP Interrupt register
* @param USBx : Selected device
* @param epnum : endpoint number
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(epnum);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return (0);
}
/**
* @brief USB_ClearInterrupts: clear a USB interrupt
* @param USBx Selected device
* @param interrupt interrupt flag
* @retval None
*/
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(interrupt);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
}
/**
* @brief Prepare the EP0 to start the first control setup
* @param USBx Selected device
* @param psetup pointer to setup packet
* @retval HAL status
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(psetup);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
{
USBx->CNTR |= USB_CNTR_RESUME;
return HAL_OK;
}
/**
* @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
{
USBx->CNTR &= ~(USB_CNTR_RESUME);
return HAL_OK;
}
/**
* @brief Copy a buffer from user memory area to packet memory area (PMA)
* @param USBx USB peripheral instance register address.
* @param pbUsrBuf pointer to user memory area.
* @param wPMABufAddr address into PMA.
* @param wNBytes: no. of bytes to be copied.
* @retval None
*/
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
uint32_t i, temp1, temp2;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
for (i = n; i != 0U; i--)
{
temp1 = *pBuf;
pBuf++;
temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8));
*pdwVal = (uint16_t)temp2;
pdwVal++;
#if PMA_ACCESS > 1U
pdwVal++;
#endif
pBuf++;
}
}
/**
* @brief Copy a buffer from user memory area to packet memory area (PMA)
* @param USBx: USB peripheral instance register address.
* @param pbUsrBuf pointer to user memory area.
* @param wPMABufAddr address into PMA.
* @param wNBytes: no. of bytes to be copied.
* @retval None
*/
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
uint32_t n = (uint32_t)wNBytes >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
uint32_t i, temp;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
for (i = n; i != 0U; i--)
{
temp = *(__IO uint16_t *)pdwVal;
pdwVal++;
*pBuf = (uint8_t)((temp >> 0) & 0xFFU);
pBuf++;
*pBuf = (uint8_t)((temp >> 8) & 0xFFU);
pBuf++;
#if PMA_ACCESS > 1U
pdwVal++;
#endif
}
if ((wNBytes % 2U) != 0U)
{
temp = *pdwVal;
*pBuf = (uint8_t)((temp >> 0) & 0xFFU);
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) */
#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

28
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c
View File

@ -6,29 +6,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */

108
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_core.h
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@ -2,35 +2,27 @@
****************************************************************************** ******************************************************************************
* @file usbd_core.h * @file usbd_core.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.4.2
* @date 11-December-2015
* @brief Header file for usbd_core.c file * @brief Header file for usbd_core.c file
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * This software component is licensed by ST under Ultimate Liberty license
* You may not use this file except in compliance with the License. * SLA0044, the "License"; You may not use this file except in compliance with
* You may obtain a copy of the License at: * the License. You may obtain a copy of the License at:
* * www.st.com/SLA0044
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_CORE_H #ifndef __USBD_CORE_H
#define __USBD_CORE_H #define __USBD_CORE_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@ -42,65 +34,67 @@
/** @addtogroup STM32_USB_DEVICE_LIBRARY /** @addtogroup STM32_USB_DEVICE_LIBRARY
* @{ * @{
*/ */
/** @defgroup USBD_CORE /** @defgroup USBD_CORE
* @brief This file is the Header file for usbd_core.c file * @brief This file is the Header file for usbd_core.c file
* @{ * @{
*/ */
/** @defgroup USBD_CORE_Exported_Defines /** @defgroup USBD_CORE_Exported_Defines
* @{ * @{
*/ */
#ifndef USBD_DEBUG_LEVEL
#define USBD_DEBUG_LEVEL 0U
#endif /* USBD_DEBUG_LEVEL */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_CORE_Exported_TypesDefinitions /** @defgroup USBD_CORE_Exported_TypesDefinitions
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_CORE_Exported_Macros /** @defgroup USBD_CORE_Exported_Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_CORE_Exported_Variables /** @defgroup USBD_CORE_Exported_Variables
* @{ * @{
*/ */
#define USBD_SOF USBD_LL_SOF #define USBD_SOF USBD_LL_SOF
/** /**
* @} * @}
*/ */
/** @defgroup USBD_CORE_Exported_FunctionsPrototype /** @defgroup USBD_CORE_Exported_FunctionsPrototype
* @{ * @{
*/ */
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id); USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id);
USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass); USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass);
USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx);
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup); USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup);
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata);
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed);
@ -115,37 +109,37 @@ USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev);
/* USBD Low Level Driver */ /* USBD Low Level Driver */
USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_DeInit (USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev,
uint8_t ep_addr, uint8_t ep_addr,
uint8_t ep_type, uint8_t ep_type,
uint16_t ep_mps); uint16_t ep_mps);
USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr); USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr);
USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev,
uint8_t ep_addr, uint8_t ep_addr,
uint8_t *pbuf, uint8_t *pbuf,
uint16_t size); uint16_t size);
USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev,
uint8_t ep_addr, uint8_t ep_addr,
uint8_t *pbuf, uint8_t *pbuf,
uint16_t size); uint16_t size);
uint32_t USBD_LL_GetRxDataSize (USBD_HandleTypeDef *pdev, uint8_t ep_addr); uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
void USBD_LL_Delay (uint32_t Delay); void USBD_LL_Delay(uint32_t Delay);
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
@ -155,11 +149,11 @@ void USBD_LL_Delay (uint32_t Delay);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

62
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h
View File

@ -2,35 +2,27 @@
****************************************************************************** ******************************************************************************
* @file usbd_req.h * @file usbd_req.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.4.2
* @date 11-December-2015
* @brief Header file for the usbd_req.c file * @brief Header file for the usbd_req.c file
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * This software component is licensed by ST under Ultimate Liberty license
* You may not use this file except in compliance with the License. * SLA0044, the "License"; You may not use this file except in compliance with
* You may obtain a copy of the License at: * the License. You may obtain a copy of the License at:
* * www.st.com/SLA0044
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USB_REQUEST_H #ifndef __USB_REQUEST_H
#define __USB_REQUEST_H #define __USB_REQUEST_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@ -40,18 +32,18 @@
/** @addtogroup STM32_USB_DEVICE_LIBRARY /** @addtogroup STM32_USB_DEVICE_LIBRARY
* @{ * @{
*/ */
/** @defgroup USBD_REQ /** @defgroup USBD_REQ
* @brief header file for the usbd_req.c file * @brief header file for the usbd_req.c file
* @{ * @{
*/ */
/** @defgroup USBD_REQ_Exported_Defines /** @defgroup USBD_REQ_Exported_Defines
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_REQ_Exported_Types /** @defgroup USBD_REQ_Exported_Types
@ -59,41 +51,41 @@
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_REQ_Exported_Macros /** @defgroup USBD_REQ_Exported_Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_REQ_Exported_Variables /** @defgroup USBD_REQ_Exported_Variables
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_REQ_Exported_FunctionsPrototype /** @defgroup USBD_REQ_Exported_FunctionsPrototype
* @{ * @{
*/ */
USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
void USBD_CtlError (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
void USBD_ParseSetupRequest (USBD_SetupReqTypedef *req, uint8_t *pdata); void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata);
void USBD_GetString (uint8_t *desc, uint8_t *unicode, uint16_t *len); void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len);
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
@ -103,11 +95,11 @@ void USBD_GetString (uint8_t *desc, uint8_t *unicode, uint16_t *len);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

378
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_def.h
View File

@ -2,35 +2,27 @@
****************************************************************************** ******************************************************************************
* @file usbd_def.h * @file usbd_def.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.4.2 * @brief General defines for the usb device library
* @date 11-December-2015
* @brief General defines for the usb device library
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * This software component is licensed by ST under Ultimate Liberty license
* You may not use this file except in compliance with the License. * SLA0044, the "License"; You may not use this file except in compliance with
* You may obtain a copy of the License at: * the License. You may obtain a copy of the License at:
* * www.st.com/SLA0044
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_DEF_H #ifndef __USBD_DEF_H
#define __USBD_DEF_H #define __USBD_DEF_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@ -39,186 +31,206 @@
/** @addtogroup STM32_USBD_DEVICE_LIBRARY /** @addtogroup STM32_USBD_DEVICE_LIBRARY
* @{ * @{
*/ */
/** @defgroup USB_DEF /** @defgroup USB_DEF
* @brief general defines for the usb device library file * @brief general defines for the usb device library file
* @{ * @{
*/ */
/** @defgroup USB_DEF_Exported_Defines /** @defgroup USB_DEF_Exported_Defines
* @{ * @{
*/ */
#ifndef NULL #ifndef NULL
#define NULL 0 #define NULL 0U
#endif #endif /* NULL */
#ifndef USBD_MAX_NUM_INTERFACES
#define USBD_MAX_NUM_INTERFACES 1U
#endif /* USBD_MAX_NUM_CONFIGURATION */
#define USB_LEN_DEV_QUALIFIER_DESC 0x0A #ifndef USBD_MAX_NUM_CONFIGURATION
#define USB_LEN_DEV_DESC 0x12 #define USBD_MAX_NUM_CONFIGURATION 1U
#define USB_LEN_CFG_DESC 0x09 #endif /* USBD_MAX_NUM_CONFIGURATION */
#define USB_LEN_IF_DESC 0x09
#define USB_LEN_EP_DESC 0x07
#define USB_LEN_OTG_DESC 0x03
#define USB_LEN_LANGID_STR_DESC 0x04
#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09
#define USBD_IDX_LANGID_STR 0x00 #ifndef USBD_LPM_ENABLED
#define USBD_IDX_MFC_STR 0x01 #define USBD_LPM_ENABLED 0U
#define USBD_IDX_PRODUCT_STR 0x02 #endif /* USBD_LPM_ENABLED */
#define USBD_IDX_SERIAL_STR 0x03
#define USBD_IDX_CONFIG_STR 0x04
#define USBD_IDX_INTERFACE_STR 0x05
#define USB_REQ_TYPE_STANDARD 0x00 #ifndef USBD_SELF_POWERED
#define USB_REQ_TYPE_CLASS 0x20 #define USBD_SELF_POWERED 1U
#define USB_REQ_TYPE_VENDOR 0x40 #endif /*USBD_SELF_POWERED */
#define USB_REQ_TYPE_MASK 0x60
#define USB_REQ_RECIPIENT_DEVICE 0x00 #ifndef USBD_SUPPORT_USER_STRING_DESC
#define USB_REQ_RECIPIENT_INTERFACE 0x01 #define USBD_SUPPORT_USER_STRING_DESC 0U
#define USB_REQ_RECIPIENT_ENDPOINT 0x02 #endif /* USBD_SUPPORT_USER_STRING_DESC */
#define USB_REQ_RECIPIENT_MASK 0x03
#define USB_REQ_GET_STATUS 0x00 #define USB_LEN_DEV_QUALIFIER_DESC 0x0AU
#define USB_REQ_CLEAR_FEATURE 0x01 #define USB_LEN_DEV_DESC 0x12U
#define USB_REQ_SET_FEATURE 0x03 #define USB_LEN_CFG_DESC 0x09U
#define USB_REQ_SET_ADDRESS 0x05 #define USB_LEN_IF_DESC 0x09U
#define USB_REQ_GET_DESCRIPTOR 0x06 #define USB_LEN_EP_DESC 0x07U
#define USB_REQ_SET_DESCRIPTOR 0x07 #define USB_LEN_OTG_DESC 0x03U
#define USB_REQ_GET_CONFIGURATION 0x08 #define USB_LEN_LANGID_STR_DESC 0x04U
#define USB_REQ_SET_CONFIGURATION 0x09 #define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09U
#define USB_REQ_GET_INTERFACE 0x0A
#define USB_REQ_SET_INTERFACE 0x0B
#define USB_REQ_SYNCH_FRAME 0x0C
#define USB_DESC_TYPE_DEVICE 1 #define USBD_IDX_LANGID_STR 0x00U
#define USB_DESC_TYPE_CONFIGURATION 2 #define USBD_IDX_MFC_STR 0x01U
#define USB_DESC_TYPE_STRING 3 #define USBD_IDX_PRODUCT_STR 0x02U
#define USB_DESC_TYPE_INTERFACE 4 #define USBD_IDX_SERIAL_STR 0x03U
#define USB_DESC_TYPE_ENDPOINT 5 #define USBD_IDX_CONFIG_STR 0x04U
#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 #define USBD_IDX_INTERFACE_STR 0x05U
#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7
#define USB_DESC_TYPE_BOS 0x0F
#define USB_CONFIG_REMOTE_WAKEUP 2 #define USB_REQ_TYPE_STANDARD 0x00U
#define USB_CONFIG_SELF_POWERED 1 #define USB_REQ_TYPE_CLASS 0x20U
#define USB_REQ_TYPE_VENDOR 0x40U
#define USB_REQ_TYPE_MASK 0x60U
#define USB_FEATURE_EP_HALT 0 #define USB_REQ_RECIPIENT_DEVICE 0x00U
#define USB_FEATURE_REMOTE_WAKEUP 1 #define USB_REQ_RECIPIENT_INTERFACE 0x01U
#define USB_FEATURE_TEST_MODE 2 #define USB_REQ_RECIPIENT_ENDPOINT 0x02U
#define USB_REQ_RECIPIENT_MASK 0x03U
#define USB_DEVICE_CAPABITY_TYPE 0x10 #define USB_REQ_GET_STATUS 0x00U
#define USB_REQ_CLEAR_FEATURE 0x01U
#define USB_REQ_SET_FEATURE 0x03U
#define USB_REQ_SET_ADDRESS 0x05U
#define USB_REQ_GET_DESCRIPTOR 0x06U
#define USB_REQ_SET_DESCRIPTOR 0x07U
#define USB_REQ_GET_CONFIGURATION 0x08U
#define USB_REQ_SET_CONFIGURATION 0x09U
#define USB_REQ_GET_INTERFACE 0x0AU
#define USB_REQ_SET_INTERFACE 0x0BU
#define USB_REQ_SYNCH_FRAME 0x0CU
#define USB_HS_MAX_PACKET_SIZE 512 #define USB_DESC_TYPE_DEVICE 0x01U
#define USB_FS_MAX_PACKET_SIZE 64 #define USB_DESC_TYPE_CONFIGURATION 0x02U
#define USB_MAX_EP0_SIZE 64 #define USB_DESC_TYPE_STRING 0x03U
#define USB_DESC_TYPE_INTERFACE 0x04U
#define USB_DESC_TYPE_ENDPOINT 0x05U
#define USB_DESC_TYPE_DEVICE_QUALIFIER 0x06U
#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 0x07U
#define USB_DESC_TYPE_BOS 0x0FU
#define USB_CONFIG_REMOTE_WAKEUP 0x02U
#define USB_CONFIG_SELF_POWERED 0x01U
#define USB_FEATURE_EP_HALT 0x00U
#define USB_FEATURE_REMOTE_WAKEUP 0x01U
#define USB_FEATURE_TEST_MODE 0x02U
#define USB_DEVICE_CAPABITY_TYPE 0x10U
#define USB_HS_MAX_PACKET_SIZE 512U
#define USB_FS_MAX_PACKET_SIZE 64U
#define USB_MAX_EP0_SIZE 64U
/* Device Status */ /* Device Status */
#define USBD_STATE_DEFAULT 1 #define USBD_STATE_DEFAULT 0x01U
#define USBD_STATE_ADDRESSED 2 #define USBD_STATE_ADDRESSED 0x02U
#define USBD_STATE_CONFIGURED 3 #define USBD_STATE_CONFIGURED 0x03U
#define USBD_STATE_SUSPENDED 4 #define USBD_STATE_SUSPENDED 0x04U
/* EP0 State */ /* EP0 State */
#define USBD_EP0_IDLE 0 #define USBD_EP0_IDLE 0x00U
#define USBD_EP0_SETUP 1 #define USBD_EP0_SETUP 0x01U
#define USBD_EP0_DATA_IN 2 #define USBD_EP0_DATA_IN 0x02U
#define USBD_EP0_DATA_OUT 3 #define USBD_EP0_DATA_OUT 0x03U
#define USBD_EP0_STATUS_IN 4 #define USBD_EP0_STATUS_IN 0x04U
#define USBD_EP0_STATUS_OUT 5 #define USBD_EP0_STATUS_OUT 0x05U
#define USBD_EP0_STALL 6 #define USBD_EP0_STALL 0x06U
#define USBD_EP_TYPE_CTRL 0 #define USBD_EP_TYPE_CTRL 0x00U
#define USBD_EP_TYPE_ISOC 1 #define USBD_EP_TYPE_ISOC 0x01U
#define USBD_EP_TYPE_BULK 2 #define USBD_EP_TYPE_BULK 0x02U
#define USBD_EP_TYPE_INTR 3 #define USBD_EP_TYPE_INTR 0x03U
/** /**
* @} * @}
*/ */
/** @defgroup USBD_DEF_Exported_TypesDefinitions /** @defgroup USBD_DEF_Exported_TypesDefinitions
* @{ * @{
*/ */
typedef struct usb_setup_req typedef struct usb_setup_req
{ {
uint8_t bmRequest;
uint8_t bmRequest; uint8_t bRequest;
uint8_t bRequest; uint16_t wValue;
uint16_t wValue; uint16_t wIndex;
uint16_t wIndex; uint16_t wLength;
uint16_t wLength; } USBD_SetupReqTypedef;
}USBD_SetupReqTypedef;
struct _USBD_HandleTypeDef; struct _USBD_HandleTypeDef;
typedef struct _Device_cb typedef struct _Device_cb
{ {
uint8_t (*Init) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); uint8_t (*Init)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
uint8_t (*DeInit) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); uint8_t (*DeInit)(struct _USBD_HandleTypeDef *pdev, uint8_t cfgidx);
/* Control Endpoints*/ /* Control Endpoints*/
uint8_t (*Setup) (struct _USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req); uint8_t (*Setup)(struct _USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);
uint8_t (*EP0_TxSent) (struct _USBD_HandleTypeDef *pdev ); uint8_t (*EP0_TxSent)(struct _USBD_HandleTypeDef *pdev);
uint8_t (*EP0_RxReady) (struct _USBD_HandleTypeDef *pdev ); uint8_t (*EP0_RxReady)(struct _USBD_HandleTypeDef *pdev);
/* Class Specific Endpoints*/ /* Class Specific Endpoints*/
uint8_t (*DataIn) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); uint8_t (*DataIn)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
uint8_t (*DataOut) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); uint8_t (*DataOut)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
uint8_t (*SOF) (struct _USBD_HandleTypeDef *pdev); uint8_t (*SOF)(struct _USBD_HandleTypeDef *pdev);
uint8_t (*IsoINIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); uint8_t (*IsoINIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
uint8_t (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); uint8_t (*IsoOUTIncomplete)(struct _USBD_HandleTypeDef *pdev, uint8_t epnum);
uint8_t *(*GetHSConfigDescriptor)(uint16_t *length); uint8_t *(*GetHSConfigDescriptor)(uint16_t *length);
uint8_t *(*GetFSConfigDescriptor)(uint16_t *length); uint8_t *(*GetFSConfigDescriptor)(uint16_t *length);
uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length); uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length);
uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length); uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length);
#if (USBD_SUPPORT_USER_STRING == 1) #if (USBD_SUPPORT_USER_STRING_DESC == 1U)
uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index, uint16_t *length); uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length);
#endif #endif
} USBD_ClassTypeDef; } USBD_ClassTypeDef;
/* Following USB Device Speed */ /* Following USB Device Speed */
typedef enum typedef enum
{ {
USBD_SPEED_HIGH = 0, USBD_SPEED_HIGH = 0U,
USBD_SPEED_FULL = 1, USBD_SPEED_FULL = 1U,
USBD_SPEED_LOW = 2, USBD_SPEED_LOW = 2U,
}USBD_SpeedTypeDef; } USBD_SpeedTypeDef;
/* Following USB Device status */ /* Following USB Device status */
typedef enum { typedef enum
USBD_OK = 0, {
USBD_OK = 0U,
USBD_BUSY, USBD_BUSY,
USBD_FAIL, USBD_FAIL,
}USBD_StatusTypeDef; } USBD_StatusTypeDef;
/* USB Device descriptors structure */ /* USB Device descriptors structure */
typedef struct typedef struct
{ {
uint8_t *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
#if (USBD_LPM_ENABLED == 1) #if (USBD_LPM_ENABLED == 1U)
uint8_t *(*GetBOSDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length);
#endif #endif
} USBD_DescriptorsTypeDef; } USBD_DescriptorsTypeDef;
/* USB Device handle structure */ /* USB Device handle structure */
typedef struct typedef struct
{ {
uint32_t status; uint32_t status;
uint32_t total_length; uint32_t is_used;
uint32_t rem_length; uint32_t total_length;
uint32_t maxpacket; uint32_t rem_length;
uint32_t maxpacket;
} USBD_EndpointTypeDef; } USBD_EndpointTypeDef;
/* USB Device handle structure */ /* USB Device handle structure */
@ -227,92 +239,98 @@ typedef struct _USBD_HandleTypeDef
uint8_t id; uint8_t id;
uint32_t dev_config; uint32_t dev_config;
uint32_t dev_default_config; uint32_t dev_default_config;
uint32_t dev_config_status; uint32_t dev_config_status;
USBD_SpeedTypeDef dev_speed; USBD_SpeedTypeDef dev_speed;
USBD_EndpointTypeDef ep_in[15]; USBD_EndpointTypeDef ep_in[16];
USBD_EndpointTypeDef ep_out[15]; USBD_EndpointTypeDef ep_out[16];
uint32_t ep0_state; uint32_t ep0_state;
uint32_t ep0_data_len; uint32_t ep0_data_len;
uint8_t dev_state; uint8_t dev_state;
uint8_t dev_old_state; uint8_t dev_old_state;
uint8_t dev_address; uint8_t dev_address;
uint8_t dev_connection_status; uint8_t dev_connection_status;
uint8_t dev_test_mode; uint8_t dev_test_mode;
uint32_t dev_remote_wakeup; uint32_t dev_remote_wakeup;
USBD_SetupReqTypedef request; USBD_SetupReqTypedef request;
USBD_DescriptorsTypeDef *pDesc; USBD_DescriptorsTypeDef *pDesc;
USBD_ClassTypeDef *pClass; USBD_ClassTypeDef *pClass;
void *pClassData; void *pClassData;
void *pUserData; void *pUserData;
void *pData; void *pData;
} USBD_HandleTypeDef; } USBD_HandleTypeDef;
/** /**
* @} * @}
*/ */
/** @defgroup USBD_DEF_Exported_Macros /** @defgroup USBD_DEF_Exported_Macros
* @{ * @{
*/ */
#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ #define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
(((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) (((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
#define LOBYTE(x) ((uint8_t)(x & 0x00FF)) #define LOBYTE(x) ((uint8_t)((x) & 0x00FFU))
#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) #define HIBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U))
#define MIN(a, b) (((a) < (b)) ? (a) : (b)) #define MIN(a, b) (((a) < (b)) ? (a) : (b))
#define MAX(a, b) (((a) > (b)) ? (a) : (b)) #define MAX(a, b) (((a) > (b)) ? (a) : (b))
#if defined ( __GNUC__ ) #if defined ( __GNUC__ )
#ifndef __weak #ifndef __weak
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#endif /* __weak */ #endif /* __weak */
#ifndef __packed #ifndef __packed
#define __packed __attribute__((__packed__)) #define __packed __attribute__((__packed__))
#endif /* __packed */ #endif /* __packed */
#endif /* __GNUC__ */ #endif /* __GNUC__ */
/* In HS mode and when the DMA is used, all variables and data structures dealing /* In HS mode and when the DMA is used, all variables and data structures dealing
with the DMA during the transaction process should be 4-bytes aligned */ with the DMA during the transaction process should be 4-bytes aligned */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4U)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4U)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
#if defined (__GNUC__) /* GNU Compiler */
#define __ALIGN_END __attribute__ ((aligned (4)))
#define __ALIGN_BEGIN
#else
#define __ALIGN_END
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#elif defined (__TASKING__) /* TASKING Compiler */
#define __ALIGN_BEGIN __align(4)
#endif /* __CC_ARM */
#endif /* __GNUC__ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_DEF_Exported_Variables /** @defgroup USBD_DEF_Exported_Variables
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_DEF_Exported_FunctionsPrototype /** @defgroup USBD_DEF_Exported_FunctionsPrototype
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
@ -322,9 +340,9 @@ typedef struct _USBD_HandleTypeDef
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

81
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h
View File

@ -2,35 +2,27 @@
****************************************************************************** ******************************************************************************
* @file usbd_ioreq.h * @file usbd_ioreq.h
* @author MCD Application Team * @author MCD Application Team
* @version V2.4.2
* @date 11-December-2015
* @brief Header file for the usbd_ioreq.c file * @brief Header file for the usbd_ioreq.c file
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * This software component is licensed by ST under Ultimate Liberty license
* You may not use this file except in compliance with the License. * SLA0044, the "License"; You may not use this file except in compliance with
* You may obtain a copy of the License at: * the License. You may obtain a copy of the License at:
* * www.st.com/SLA0044
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __USBD_IOREQ_H #ifndef __USBD_IOREQ_H
#define __USBD_IOREQ_H #define __USBD_IOREQ_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@ -40,18 +32,18 @@
/** @addtogroup STM32_USB_DEVICE_LIBRARY /** @addtogroup STM32_USB_DEVICE_LIBRARY
* @{ * @{
*/ */
/** @defgroup USBD_IOREQ /** @defgroup USBD_IOREQ
* @brief header file for the usbd_ioreq.c file * @brief header file for the usbd_ioreq.c file
* @{ * @{
*/ */
/** @defgroup USBD_IOREQ_Exported_Defines /** @defgroup USBD_IOREQ_Exported_Defines
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_IOREQ_Exported_Types /** @defgroup USBD_IOREQ_Exported_Types
@ -61,56 +53,55 @@
/** /**
* @} * @}
*/ */
/** @defgroup USBD_IOREQ_Exported_Macros /** @defgroup USBD_IOREQ_Exported_Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_IOREQ_Exported_Variables /** @defgroup USBD_IOREQ_Exported_Variables
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype /** @defgroup USBD_IOREQ_Exported_FunctionsPrototype
* @{ * @{
*/ */
USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *buf, uint8_t *pbuf,
uint16_t len); uint16_t len);
USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint8_t *pbuf,
uint16_t len); uint16_t len);
USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint8_t *pbuf,
uint16_t len); uint16_t len);
USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint8_t *pbuf,
uint16_t len); uint16_t len);
USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev);
USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev);
uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr);
uint8_t epnum);
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
@ -120,9 +111,9 @@ uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev ,
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

464
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_core.c
View File

@ -2,28 +2,20 @@
****************************************************************************** ******************************************************************************
* @file usbd_core.c * @file usbd_core.c
* @author MCD Application Team * @author MCD Application Team
* @version V2.4.2
* @date 11-December-2015
* @brief This file provides all the USBD core functions. * @brief This file provides all the USBD core functions.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * This software component is licensed by ST under Ultimate Liberty license
* You may not use this file except in compliance with the License. * SLA0044, the "License"; You may not use this file except in compliance with
* You may obtain a copy of the License at: * the License. You may obtain a copy of the License at:
* * www.st.com/SLA0044
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "usbd_core.h" #include "usbd_core.h"
@ -33,57 +25,58 @@
*/ */
/** @defgroup USBD_CORE /** @defgroup USBD_CORE
* @brief usbd core module * @brief usbd core module
* @{ * @{
*/ */
/** @defgroup USBD_CORE_Private_TypesDefinitions /** @defgroup USBD_CORE_Private_TypesDefinitions
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_CORE_Private_Defines /** @defgroup USBD_CORE_Private_Defines
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_CORE_Private_Macros /** @defgroup USBD_CORE_Private_Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_CORE_Private_FunctionPrototypes /** @defgroup USBD_CORE_Private_FunctionPrototypes
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_CORE_Private_Variables /** @defgroup USBD_CORE_Private_Variables
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_CORE_Private_Functions /** @defgroup USBD_CORE_Private_Functions
* @{ * @{
*/ */
/** /**
* @brief USBD_Init * @brief USBD_Init
@ -93,38 +86,41 @@
* @param id: Low level core index * @param id: Low level core index
* @retval None * @retval None
*/ */
USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev,
USBD_DescriptorsTypeDef *pdesc, uint8_t id)
{ {
/* Check whether the USB Host handle is valid */ /* Check whether the USB Host handle is valid */
if(pdev == NULL) if (pdev == NULL)
{ {
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Device handle"); USBD_ErrLog("Invalid Device handle");
return USBD_FAIL; #endif
return USBD_FAIL;
} }
/* Unlink previous class*/ /* Unlink previous class*/
if(pdev->pClass != NULL) if (pdev->pClass != NULL)
{ {
pdev->pClass = NULL; pdev->pClass = NULL;
} }
/* Assign USBD Descriptors */ /* Assign USBD Descriptors */
if(pdesc != NULL) if (pdesc != NULL)
{ {
pdev->pDesc = pdesc; pdev->pDesc = pdesc;
} }
/* Set Device initial State */ /* Set Device initial State */
pdev->dev_state = USBD_STATE_DEFAULT; pdev->dev_state = USBD_STATE_DEFAULT;
pdev->id = id; pdev->id = id;
/* Initialize low level driver */ /* Initialize low level driver */
USBD_LL_Init(pdev); USBD_LL_Init(pdev);
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_DeInit * @brief USBD_DeInit
* Re-Initialize th device library * Re-Initialize th device library
* @param pdev: device instance * @param pdev: device instance
* @retval status: status * @retval status: status
@ -132,23 +128,22 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *
USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
{ {
/* Set Default State */ /* Set Default State */
pdev->dev_state = USBD_STATE_DEFAULT; pdev->dev_state = USBD_STATE_DEFAULT;
/* Free Class Resources */ /* Free Class Resources */
pdev->pClass->DeInit(pdev, pdev->dev_config); pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
/* Stop the low level driver */ /* Stop the low level driver */
USBD_LL_Stop(pdev); USBD_LL_Stop(pdev);
/* Initialize low level driver */ /* Initialize low level driver */
USBD_LL_DeInit(pdev); USBD_LL_DeInit(pdev);
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_RegisterClass * @brief USBD_RegisterClass
* Link class driver to Device Core. * Link class driver to Device Core.
* @param pDevice : Device Handle * @param pDevice : Device Handle
* @param pclass: Class handle * @param pclass: Class handle
@ -156,8 +151,8 @@ USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)
*/ */
USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)
{ {
USBD_StatusTypeDef status = USBD_OK; USBD_StatusTypeDef status = USBD_OK;
if(pclass != 0) if (pclass != NULL)
{ {
/* link the class to the USB Device handle */ /* link the class to the USB Device handle */
pdev->pClass = pclass; pdev->pClass = pclass;
@ -165,59 +160,62 @@ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeD
} }
else else
{ {
#if (USBD_DEBUG_LEVEL > 1U)
USBD_ErrLog("Invalid Class handle"); USBD_ErrLog("Invalid Class handle");
status = USBD_FAIL; #endif
status = USBD_FAIL;
} }
return status; return status;
} }
/** /**
* @brief USBD_Start * @brief USBD_Start
* Start the USB Device Core. * Start the USB Device Core.
* @param pdev: Device Handle * @param pdev: Device Handle
* @retval USBD Status * @retval USBD Status
*/ */
USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev)
{ {
/* Start the low level driver */ /* Start the low level driver */
USBD_LL_Start(pdev); USBD_LL_Start(pdev);
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_Stop * @brief USBD_Stop
* Stop the USB Device Core. * Stop the USB Device Core.
* @param pdev: Device Handle * @param pdev: Device Handle
* @retval USBD Status * @retval USBD Status
*/ */
USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev)
{ {
/* Free Class Resources */ /* Free Class Resources */
pdev->pClass->DeInit(pdev, pdev->dev_config); pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
/* Stop the low level driver */ /* Stop the low level driver */
USBD_LL_Stop(pdev); USBD_LL_Stop(pdev);
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_RunTestMode * @brief USBD_RunTestMode
* Launch test mode process * Launch test mode process
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev)
{ {
/* Prevent unused argument compilation warning */
UNUSED(pdev);
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_SetClassConfig * @brief USBD_SetClassConfig
* Configure device and start the interface * Configure device and start the interface
* @param pdev: device instance * @param pdev: device instance
* @param cfgidx: configuration index * @param cfgidx: configuration index
@ -226,21 +224,22 @@ USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev)
USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{ {
USBD_StatusTypeDef ret = USBD_FAIL; USBD_StatusTypeDef ret = USBD_FAIL;
if(pdev->pClass != NULL) if (pdev->pClass != NULL)
{ {
/* Set configuration and Start the Class*/ /* Set configuration and Start the Class*/
if(pdev->pClass->Init(pdev, cfgidx) == 0) if (pdev->pClass->Init(pdev, cfgidx) == 0U)
{ {
ret = USBD_OK; ret = USBD_OK;
} }
} }
return ret;
return ret;
} }
/** /**
* @brief USBD_ClrClassConfig * @brief USBD_ClrClassConfig
* Clear current configuration * Clear current configuration
* @param pdev: device instance * @param pdev: device instance
* @param cfgidx: configuration index * @param cfgidx: configuration index
@ -249,317 +248,364 @@ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx
USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx)
{ {
/* Clear configuration and De-initialize the Class process*/ /* Clear configuration and De-initialize the Class process*/
pdev->pClass->DeInit(pdev, cfgidx); pdev->pClass->DeInit(pdev, cfgidx);
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_SetupStage * @brief USBD_SetupStage
* Handle the setup stage * Handle the setup stage
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)
{ {
USBD_ParseSetupRequest(&pdev->request, psetup); USBD_ParseSetupRequest(&pdev->request, psetup);
pdev->ep0_state = USBD_EP0_SETUP; pdev->ep0_state = USBD_EP0_SETUP;
pdev->ep0_data_len = pdev->request.wLength; pdev->ep0_data_len = pdev->request.wLength;
switch (pdev->request.bmRequest & 0x1F) switch (pdev->request.bmRequest & 0x1FU)
{ {
case USB_REQ_RECIPIENT_DEVICE: case USB_REQ_RECIPIENT_DEVICE:
USBD_StdDevReq (pdev, &pdev->request); USBD_StdDevReq(pdev, &pdev->request);
break; break;
case USB_REQ_RECIPIENT_INTERFACE: case USB_REQ_RECIPIENT_INTERFACE:
USBD_StdItfReq(pdev, &pdev->request); USBD_StdItfReq(pdev, &pdev->request);
break; break;
case USB_REQ_RECIPIENT_ENDPOINT: case USB_REQ_RECIPIENT_ENDPOINT:
USBD_StdEPReq(pdev, &pdev->request); USBD_StdEPReq(pdev, &pdev->request);
break; break;
default: default:
USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80); USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U));
break; break;
} }
return USBD_OK;
return USBD_OK;
} }
/** /**
* @brief USBD_DataOutStage * @brief USBD_DataOutStage
* Handle data OUT stage * Handle data OUT stage
* @param pdev: device instance * @param pdev: device instance
* @param epnum: endpoint index * @param epnum: endpoint index
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata) USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{ {
USBD_EndpointTypeDef *pep; USBD_EndpointTypeDef *pep;
if(epnum == 0) if (epnum == 0U)
{ {
pep = &pdev->ep_out[0]; pep = &pdev->ep_out[0];
if ( pdev->ep0_state == USBD_EP0_DATA_OUT) if (pdev->ep0_state == USBD_EP0_DATA_OUT)
{ {
if(pep->rem_length > pep->maxpacket) if (pep->rem_length > pep->maxpacket)
{ {
pep->rem_length -= pep->maxpacket; pep->rem_length -= pep->maxpacket;
USBD_CtlContinueRx (pdev, USBD_CtlContinueRx(pdev, pdata,
pdata, (uint16_t)MIN(pep->rem_length, pep->maxpacket));
MIN(pep->rem_length ,pep->maxpacket));
} }
else else
{ {
if((pdev->pClass->EP0_RxReady != NULL)&& if ((pdev->pClass->EP0_RxReady != NULL) &&
(pdev->dev_state == USBD_STATE_CONFIGURED)) (pdev->dev_state == USBD_STATE_CONFIGURED))
{ {
pdev->pClass->EP0_RxReady(pdev); pdev->pClass->EP0_RxReady(pdev);
} }
USBD_CtlSendStatus(pdev); USBD_CtlSendStatus(pdev);
} }
} }
else
{
if (pdev->ep0_state == USBD_EP0_STATUS_OUT)
{
/*
* STATUS PHASE completed, update ep0_state to idle
*/
pdev->ep0_state = USBD_EP0_IDLE;
USBD_LL_StallEP(pdev, 0U);
}
}
} }
else if((pdev->pClass->DataOut != NULL)&& else if ((pdev->pClass->DataOut != NULL) &&
(pdev->dev_state == USBD_STATE_CONFIGURED)) (pdev->dev_state == USBD_STATE_CONFIGURED))
{ {
pdev->pClass->DataOut(pdev, epnum); pdev->pClass->DataOut(pdev, epnum);
} }
else
{
/* should never be in this condition */
return USBD_FAIL;
}
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_DataInStage * @brief USBD_DataInStage
* Handle data in stage * Handle data in stage
* @param pdev: device instance * @param pdev: device instance
* @param epnum: endpoint index * @param epnum: endpoint index
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata) USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev,
uint8_t epnum, uint8_t *pdata)
{ {
USBD_EndpointTypeDef *pep; USBD_EndpointTypeDef *pep;
if(epnum == 0) if (epnum == 0U)
{ {
pep = &pdev->ep_in[0]; pep = &pdev->ep_in[0];
if ( pdev->ep0_state == USBD_EP0_DATA_IN) if (pdev->ep0_state == USBD_EP0_DATA_IN)
{ {
if(pep->rem_length > pep->maxpacket) if (pep->rem_length > pep->maxpacket)
{ {
pep->rem_length -= pep->maxpacket; pep->rem_length -= pep->maxpacket;
USBD_CtlContinueSendData (pdev, USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length);
pdata,
pep->rem_length);
/* Prepare endpoint for premature end of transfer */ /* Prepare endpoint for premature end of transfer */
USBD_LL_PrepareReceive (pdev, USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
0,
NULL,
0);
} }
else else
{ /* last packet is MPS multiple, so send ZLP packet */ {
if((pep->total_length % pep->maxpacket == 0) && /* last packet is MPS multiple, so send ZLP packet */
(pep->total_length >= pep->maxpacket) && if ((pep->total_length % pep->maxpacket == 0U) &&
(pep->total_length < pdev->ep0_data_len )) (pep->total_length >= pep->maxpacket) &&
(pep->total_length < pdev->ep0_data_len))
{ {
USBD_CtlContinueSendData(pdev, NULL, 0U);
USBD_CtlContinueSendData(pdev , NULL, 0); pdev->ep0_data_len = 0U;
pdev->ep0_data_len = 0;
/* Prepare endpoint for premature end of transfer */
/* Prepare endpoint for premature end of transfer */ USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
USBD_LL_PrepareReceive (pdev,
0,
NULL,
0);
} }
else else
{ {
if((pdev->pClass->EP0_TxSent != NULL)&& if ((pdev->pClass->EP0_TxSent != NULL) &&
(pdev->dev_state == USBD_STATE_CONFIGURED)) (pdev->dev_state == USBD_STATE_CONFIGURED))
{ {
pdev->pClass->EP0_TxSent(pdev); pdev->pClass->EP0_TxSent(pdev);
} }
USBD_LL_StallEP(pdev, 0x80U);
USBD_CtlReceiveStatus(pdev); USBD_CtlReceiveStatus(pdev);
} }
} }
} }
if (pdev->dev_test_mode == 1) else
{ {
USBD_RunTestMode(pdev); if ((pdev->ep0_state == USBD_EP0_STATUS_IN) ||
pdev->dev_test_mode = 0; (pdev->ep0_state == USBD_EP0_IDLE))
{
USBD_LL_StallEP(pdev, 0x80U);
}
}
if (pdev->dev_test_mode == 1U)
{
USBD_RunTestMode(pdev);
pdev->dev_test_mode = 0U;
} }
} }
else if((pdev->pClass->DataIn != NULL)&& else if ((pdev->pClass->DataIn != NULL) &&
(pdev->dev_state == USBD_STATE_CONFIGURED)) (pdev->dev_state == USBD_STATE_CONFIGURED))
{ {
pdev->pClass->DataIn(pdev, epnum); pdev->pClass->DataIn(pdev, epnum);
} }
else
{
/* should never be in this condition */
return USBD_FAIL;
}
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_LL_Reset * @brief USBD_LL_Reset
* Handle Reset event * Handle Reset event
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev)
{ {
/* Open EP0 OUT */ /* Open EP0 OUT */
USBD_LL_OpenEP(pdev, USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
0x00, pdev->ep_out[0x00U & 0xFU].is_used = 1U;
USBD_EP_TYPE_CTRL,
USB_MAX_EP0_SIZE);
pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;
/* Open EP0 IN */ /* Open EP0 IN */
USBD_LL_OpenEP(pdev, USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE);
0x80, pdev->ep_in[0x80U & 0xFU].is_used = 1U;
USBD_EP_TYPE_CTRL,
USB_MAX_EP0_SIZE);
pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;
/* Upon Reset call user call back */ /* Upon Reset call user call back */
pdev->dev_state = USBD_STATE_DEFAULT; pdev->dev_state = USBD_STATE_DEFAULT;
pdev->ep0_state = USBD_EP0_IDLE;
if (pdev->pClassData) pdev->dev_config = 0U;
pdev->pClass->DeInit(pdev, pdev->dev_config); pdev->dev_remote_wakeup = 0U;
if (pdev->pClassData)
{
pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
}
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_LL_Reset * @brief USBD_LL_Reset
* Handle Reset event * Handle Reset event
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev,
USBD_SpeedTypeDef speed)
{ {
pdev->dev_speed = speed; pdev->dev_speed = speed;
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_Suspend * @brief USBD_Suspend
* Handle Suspend event * Handle Suspend event
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev)
{ {
pdev->dev_old_state = pdev->dev_state; pdev->dev_old_state = pdev->dev_state;
pdev->dev_state = USBD_STATE_SUSPENDED; pdev->dev_state = USBD_STATE_SUSPENDED;
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_Resume * @brief USBD_Resume
* Handle Resume event * Handle Resume event
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev)
{ {
pdev->dev_state = pdev->dev_old_state; if (pdev->dev_state == USBD_STATE_SUSPENDED)
{
pdev->dev_state = pdev->dev_old_state;
}
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_SOF * @brief USBD_SOF
* Handle SOF event * Handle SOF event
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev)
{ {
if(pdev->dev_state == USBD_STATE_CONFIGURED) if (pdev->dev_state == USBD_STATE_CONFIGURED)
{ {
if(pdev->pClass->SOF != NULL) if (pdev->pClass->SOF != NULL)
{ {
pdev->pClass->SOF(pdev); pdev->pClass->SOF(pdev);
} }
} }
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_IsoINIncomplete * @brief USBD_IsoINIncomplete
* Handle iso in incomplete event * Handle iso in incomplete event
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev,
uint8_t epnum)
{ {
/* Prevent unused arguments compilation warning */
UNUSED(pdev);
UNUSED(epnum);
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_IsoOUTIncomplete * @brief USBD_IsoOUTIncomplete
* Handle iso out incomplete event * Handle iso out incomplete event
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev,
uint8_t epnum)
{ {
/* Prevent unused arguments compilation warning */
UNUSED(pdev);
UNUSED(epnum);
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_DevConnected * @brief USBD_DevConnected
* Handle device connection event * Handle device connection event
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev)
{ {
/* Prevent unused argument compilation warning */
UNUSED(pdev);
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_DevDisconnected * @brief USBD_DevDisconnected
* Handle device disconnection event * Handle device disconnection event
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev)
{ {
/* Free Class Resources */ /* Free Class Resources */
pdev->dev_state = USBD_STATE_DEFAULT; pdev->dev_state = USBD_STATE_DEFAULT;
pdev->pClass->DeInit(pdev, pdev->dev_config); pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config);
return USBD_OK; return USBD_OK;
} }
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1098
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c
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File diff suppressed because it is too large Load Diff

132
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c
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@ -2,28 +2,20 @@
****************************************************************************** ******************************************************************************
* @file usbd_ioreq.c * @file usbd_ioreq.c
* @author MCD Application Team * @author MCD Application Team
* @version V2.4.2
* @date 11-December-2015
* @brief This file provides the IO requests APIs for control endpoints. * @brief This file provides the IO requests APIs for control endpoints.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2015 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * This software component is licensed by ST under Ultimate Liberty license
* You may not use this file except in compliance with the License. * SLA0044, the "License"; You may not use this file except in compliance with
* You may obtain a copy of the License at: * the License. You may obtain a copy of the License at:
* * www.st.com/SLA0044
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "usbd_ioreq.h" #include "usbd_ioreq.h"
@ -33,56 +25,56 @@
*/ */
/** @defgroup USBD_IOREQ /** @defgroup USBD_IOREQ
* @brief control I/O requests module * @brief control I/O requests module
* @{ * @{
*/ */
/** @defgroup USBD_IOREQ_Private_TypesDefinitions /** @defgroup USBD_IOREQ_Private_TypesDefinitions
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_IOREQ_Private_Defines /** @defgroup USBD_IOREQ_Private_Defines
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_IOREQ_Private_Macros /** @defgroup USBD_IOREQ_Private_Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_IOREQ_Private_Variables /** @defgroup USBD_IOREQ_Private_Variables
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_IOREQ_Private_FunctionPrototypes /** @defgroup USBD_IOREQ_Private_FunctionPrototypes
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @defgroup USBD_IOREQ_Private_Functions /** @defgroup USBD_IOREQ_Private_Functions
* @{ * @{
*/ */
/** /**
* @brief USBD_CtlSendData * @brief USBD_CtlSendData
@ -92,17 +84,17 @@
* @param len: length of data to be sent * @param len: length of data to be sent
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint8_t *pbuf, uint16_t len)
uint16_t len)
{ {
/* Set EP0 State */ /* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_IN; pdev->ep0_state = USBD_EP0_DATA_IN;
pdev->ep_in[0].total_length = len; pdev->ep_in[0].total_length = len;
pdev->ep_in[0].rem_length = len; pdev->ep_in[0].rem_length = len;
/* Start the transfer */
USBD_LL_Transmit (pdev, 0x00, pbuf, len); /* Start the transfer */
USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
return USBD_OK; return USBD_OK;
} }
@ -114,13 +106,12 @@ USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev,
* @param len: length of data to be sent * @param len: length of data to be sent
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint8_t *pbuf, uint16_t len)
uint16_t len)
{ {
/* Start the next transfer */ /* Start the next transfer */
USBD_LL_Transmit (pdev, 0x00, pbuf, len); USBD_LL_Transmit(pdev, 0x00U, pbuf, len);
return USBD_OK; return USBD_OK;
} }
@ -132,20 +123,17 @@ USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev,
* @param len: length of data to be received * @param len: length of data to be received
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint8_t *pbuf, uint16_t len)
uint16_t len)
{ {
/* Set EP0 State */ /* Set EP0 State */
pdev->ep0_state = USBD_EP0_DATA_OUT; pdev->ep0_state = USBD_EP0_DATA_OUT;
pdev->ep_out[0].total_length = len; pdev->ep_out[0].total_length = len;
pdev->ep_out[0].rem_length = len; pdev->ep_out[0].rem_length = len;
/* Start the transfer */ /* Start the transfer */
USBD_LL_PrepareReceive (pdev, USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
0,
pbuf,
len);
return USBD_OK; return USBD_OK;
} }
@ -157,32 +145,28 @@ USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev,
* @param len: length of data to be received * @param len: length of data to be received
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev,
uint8_t *pbuf, uint8_t *pbuf, uint16_t len)
uint16_t len)
{ {
USBD_LL_PrepareReceive(pdev, 0U, pbuf, len);
USBD_LL_PrepareReceive (pdev,
0,
pbuf,
len);
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_CtlSendStatus * @brief USBD_CtlSendStatus
* send zero lzngth packet on the ctl pipe * send zero lzngth packet on the ctl pipe
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev)
{ {
/* Set EP0 State */ /* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_IN; pdev->ep0_state = USBD_EP0_STATUS_IN;
/* Start the transfer */ /* Start the transfer */
USBD_LL_Transmit (pdev, 0x00, NULL, 0); USBD_LL_Transmit(pdev, 0x00U, NULL, 0U);
return USBD_OK; return USBD_OK;
} }
@ -192,21 +176,17 @@ USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev)
* @param pdev: device instance * @param pdev: device instance
* @retval status * @retval status
*/ */
USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev)
{ {
/* Set EP0 State */ /* Set EP0 State */
pdev->ep0_state = USBD_EP0_STATUS_OUT; pdev->ep0_state = USBD_EP0_STATUS_OUT;
/* Start the transfer */ /* Start the transfer */
USBD_LL_PrepareReceive ( pdev, USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U);
0,
NULL,
0);
return USBD_OK; return USBD_OK;
} }
/** /**
* @brief USBD_GetRxCount * @brief USBD_GetRxCount
* returns the received data length * returns the received data length
@ -214,23 +194,23 @@ USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev)
* @param ep_addr: endpoint address * @param ep_addr: endpoint address
* @retval Rx Data blength * @retval Rx Data blength
*/ */
uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , uint8_t ep_addr) uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
{ {
return USBD_LL_GetRxDataSize(pdev, ep_addr); return USBD_LL_GetRxDataSize(pdev, ep_addr);
} }
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

79
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/stm32f3xx_hal_conf.h
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@ -5,29 +5,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2018 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -49,7 +33,7 @@
*/ */
#define HAL_MODULE_ENABLED #define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_ADC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */ /*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */ /*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_CEC_MODULE_ENABLED */ /*#define HAL_CEC_MODULE_ENABLED */
@ -81,6 +65,8 @@
/*#define HAL_WWDG_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */
#define HAL_PCD_MODULE_ENABLED #define HAL_PCD_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
#define HAL_DMA_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED
@ -169,6 +155,32 @@
#define PREFETCH_ENABLE 1 #define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 0 #define INSTRUCTION_CACHE_ENABLE 0
#define DATA_CACHE_ENABLE 0 #define DATA_CACHE_ENABLE 0
#define USE_SPI_CRC 0U
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* OPAMP register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
/* ########################## Assert Selection ############################## */ /* ########################## Assert Selection ############################## */
/** /**
@ -177,15 +189,6 @@
*/ */
/* #define USE_FULL_ASSERT 1U */ /* #define USE_FULL_ASSERT 1U */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
/** /**
* @brief Include module's header file * @brief Include module's header file
@ -199,6 +202,10 @@
#include "stm32f3xx_hal_gpio.h" #include "stm32f3xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */ #endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32f3xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED #ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f3xx_hal_dma.h" #include "stm32f3xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */ #endif /* HAL_DMA_MODULE_ENABLED */
@ -215,6 +222,10 @@
#include "stm32f3xx_hal_can.h" #include "stm32f3xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */ #endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
#include "stm32f3xx_hal_can_legacy.h"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED #ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f3xx_hal_cec.h" #include "stm32f3xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */ #endif /* HAL_CEC_MODULE_ENABLED */
@ -250,7 +261,7 @@
#ifdef HAL_PCCARD_MODULE_ENABLED #ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f3xx_hal_pccard.h" #include "stm32f3xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */ #endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_HRTIM_MODULE_ENABLED #ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32f3xx_hal_hrtim.h" #include "stm32f3xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */ #endif /* HAL_HRTIM_MODULE_ENABLED */
@ -327,7 +338,7 @@
#ifdef USE_FULL_ASSERT #ifdef USE_FULL_ASSERT
/** /**
* @brief The assert_param macro is used for function's parameters check. * @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function * @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source * which reports the name of the source file and the source
* line number of the call that failed. * line number of the call that failed.
* If expr is true, it returns no value. * If expr is true, it returns no value.

62
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/lib/system_stm32f3xx.c
View File

@ -44,29 +44,13 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2> * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without modification, * This software component is licensed by ST under BSD 3-Clause license,
* are permitted provided that the following conditions are met: * the "License"; You may not use this file except in compliance with the
* 1. Redistributions of source code must retain the above copyright notice, * License. You may obtain a copy of the License at:
* this list of conditions and the following disclaimer. * opensource.org/licenses/BSD-3-Clause
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
@ -161,41 +145,15 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/** /**
* @brief Setup the microcontroller system * @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and the PLL configuration is reset.
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemInit(void) void SystemInit(void)
{ {
/* FPU settings ------------------------------------------------------------*/ /* FPU settings --------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif #endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= 0x00000001U;
/* Reset CFGR register */
RCC->CFGR &= 0xF87FC00CU;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= 0xFEF6FFFFU;
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
RCC->CFGR &= 0xFF80FFFFU;
/* Reset PREDIV1[3:0] bits */
RCC->CFGR2 &= 0xFFFFFFF0U;
/* Reset USARTSW[1:0], I2CSW and TIMs bits */
RCC->CFGR3 &= 0xFF00FCCCU;
/* Disable all interrupts */
RCC->CIR = 0x00000000U;
#ifdef VECT_TAB_SRAM #ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */

362
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/usbd_conf.c
View File

@ -1,51 +1,23 @@
/* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* @file : usbd_conf.c * @file : usbd_conf.c
* @version : v2.0_Cube * @version : v2.0_Cube
* @brief : This file implements the board support package for the USB device library * @brief : This file implements the board support package for the USB device library
****************************************************************************** ******************************************************************************
* This notice applies to any and all portions of this file * @attention
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
* *
* Copyright (c) 2018 STMicroelectronics International N.V. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved. * All rights reserved.</center></h2>
* *
* Redistribution and use in source and binary forms, with or without * This software component is licensed by ST under Ultimate Liberty license
* modification, are permitted, provided that the following conditions are met: * SLA0044, the "License"; You may not use this file except in compliance with
* * the License. You may obtain a copy of the License at:
* 1. Redistribution of source code must retain the above copyright notice, * www.st.com/SLA0044
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of other
* contributors to this software may be used to endorse or promote products
* derived from this software without specific written permission.
* 4. This software, including modifications and/or derivative works of this
* software, must execute solely and exclusively on microcontroller or
* microprocessor devices manufactured by or for STMicroelectronics.
* 5. Redistribution and use of this software other than as permitted under
* this license is void and will automatically terminate your rights under
* this license.
*
* THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
* PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
* RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
* SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h" #include "stm32f3xx.h"
@ -81,11 +53,15 @@ PCD_HandleTypeDef hpcd_USB_FS;
/* USER CODE END PFP */ /* USER CODE END PFP */
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
static USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status);
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
/* USER CODE END 1 */ /* USER CODE END 1 */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
else
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state); void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/******************************************************************************* /*******************************************************************************
LL Driver Callbacks (PCD -> USB Device Library) LL Driver Callbacks (PCD -> USB Device Library)
@ -94,7 +70,7 @@ void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
{ {
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct = {0};
if(pcdHandle->Instance==USB) if(pcdHandle->Instance==USB)
{ {
/* USER CODE BEGIN USB_MspInit 0 */ /* USER CODE BEGIN USB_MspInit 0 */
@ -148,7 +124,11 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)
* @param hpcd: PCD handle * @param hpcd: PCD handle
* @retval None * @retval None
*/ */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{ {
USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);
} }
@ -159,7 +139,11 @@ void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
* @param epnum: Endpoint number * @param epnum: Endpoint number
* @retval None * @retval None
*/ */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{ {
USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);
} }
@ -170,7 +154,11 @@ void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
* @param epnum: Endpoint number * @param epnum: Endpoint number
* @retval None * @retval None
*/ */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{ {
USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);
} }
@ -180,7 +168,11 @@ void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
* @param hpcd: PCD handle * @param hpcd: PCD handle
* @retval None * @retval None
*/ */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{ {
USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);
} }
@ -190,7 +182,11 @@ void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
* @param hpcd: PCD handle * @param hpcd: PCD handle
* @retval None * @retval None
*/ */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{ {
USBD_SpeedTypeDef speed = USBD_SPEED_FULL; USBD_SpeedTypeDef speed = USBD_SPEED_FULL;
@ -217,7 +213,11 @@ void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
* @param hpcd: PCD handle * @param hpcd: PCD handle
* @retval None * @retval None
*/ */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{ {
/* Invoke hook function to allow the application to prepare entry into low power /* Invoke hook function to allow the application to prepare entry into low power
* mode. * mode.
@ -241,7 +241,11 @@ void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
* @param hpcd: PCD handle * @param hpcd: PCD handle
* @retval None * @retval None
*/ */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{ {
/* USER CODE BEGIN 3 */ /* USER CODE BEGIN 3 */
@ -259,7 +263,11 @@ void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
* @param epnum: Endpoint number * @param epnum: Endpoint number
* @retval None * @retval None
*/ */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{ {
USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
} }
@ -270,7 +278,11 @@ void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
* @param epnum: Endpoint number * @param epnum: Endpoint number
* @retval None * @retval None
*/ */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#else
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{ {
USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);
} }
@ -280,7 +292,11 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
* @param hpcd: PCD handle * @param hpcd: PCD handle
* @retval None * @retval None
*/ */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{ {
USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);
} }
@ -290,7 +306,11 @@ void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
* @param hpcd: PCD handle * @param hpcd: PCD handle
* @retval None * @retval None
*/ */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
static void PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
#else
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{ {
USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);
} }
@ -323,11 +343,30 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
ASSERT_RT(BLT_FALSE); ASSERT_RT(BLT_FALSE);
} }
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
/* Register USB PCD CallBacks */
HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SOF_CB_ID, PCD_SOFCallback);
HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SETUPSTAGE_CB_ID, PCD_SetupStageCallback);
HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESET_CB_ID, PCD_ResetCallback);
HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_SUSPEND_CB_ID, PCD_SuspendCallback);
HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_RESUME_CB_ID, PCD_ResumeCallback);
HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_CONNECT_CB_ID, PCD_ConnectCallback);
HAL_PCD_RegisterCallback(&hpcd_USB_FS, HAL_PCD_DISCONNECT_CB_ID, PCD_DisconnectCallback);
HAL_PCD_RegisterDataOutStageCallback(&hpcd_USB_FS, PCD_DataOutStageCallback);
HAL_PCD_RegisterDataInStageCallback(&hpcd_USB_FS, PCD_DataInStageCallback);
HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_FS, PCD_ISOOUTIncompleteCallback);
HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_FS, PCD_ISOINIncompleteCallback);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* USER CODE BEGIN EndPoint_Configuration */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18); HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18);
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58); HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x80 , PCD_SNG_BUF, 0x58);
/* USER CODE END EndPoint_Configuration */
/* USER CODE BEGIN EndPoint_Configuration_CDC */
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0); HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x81 , PCD_SNG_BUF, 0xC0);
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110); HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x01 , PCD_SNG_BUF, 0x110);
HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100); HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x82 , PCD_SNG_BUF, 0x100);
/* USER CODE END EndPoint_Configuration_CDC */
return USBD_OK; return USBD_OK;
} }
@ -343,23 +382,8 @@ USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)
hal_status = HAL_PCD_DeInit(pdev->pData); hal_status = HAL_PCD_DeInit(pdev->pData);
switch (hal_status) { usb_status = USBD_Get_USB_Status(hal_status);
case HAL_OK :
usb_status = USBD_OK;
break;
case HAL_ERROR :
usb_status = USBD_FAIL;
break;
case HAL_BUSY :
usb_status = USBD_BUSY;
break;
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
break;
default :
usb_status = USBD_FAIL;
break;
}
return usb_status; return usb_status;
} }
@ -374,24 +398,9 @@ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)
USBD_StatusTypeDef usb_status = USBD_OK; USBD_StatusTypeDef usb_status = USBD_OK;
hal_status = HAL_PCD_Start(pdev->pData); hal_status = HAL_PCD_Start(pdev->pData);
switch (hal_status) { usb_status = USBD_Get_USB_Status(hal_status);
case HAL_OK :
usb_status = USBD_OK;
break;
case HAL_ERROR :
usb_status = USBD_FAIL;
break;
case HAL_BUSY :
usb_status = USBD_BUSY;
break;
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
break;
default :
usb_status = USBD_FAIL;
break;
}
return usb_status; return usb_status;
} }
@ -407,23 +416,8 @@ USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)
hal_status = HAL_PCD_Stop(pdev->pData); hal_status = HAL_PCD_Stop(pdev->pData);
switch (hal_status) { usb_status = USBD_Get_USB_Status(hal_status);
case HAL_OK :
usb_status = USBD_OK;
break;
case HAL_ERROR :
usb_status = USBD_FAIL;
break;
case HAL_BUSY :
usb_status = USBD_BUSY;
break;
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
break;
default :
usb_status = USBD_FAIL;
break;
}
return usb_status; return usb_status;
} }
@ -442,23 +436,8 @@ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uin
hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);
switch (hal_status) { usb_status = USBD_Get_USB_Status(hal_status);
case HAL_OK :
usb_status = USBD_OK;
break;
case HAL_ERROR :
usb_status = USBD_FAIL;
break;
case HAL_BUSY :
usb_status = USBD_BUSY;
break;
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
break;
default :
usb_status = USBD_FAIL;
break;
}
return usb_status; return usb_status;
} }
@ -475,23 +454,8 @@ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);
switch (hal_status) { usb_status = USBD_Get_USB_Status(hal_status);
case HAL_OK :
usb_status = USBD_OK;
break;
case HAL_ERROR :
usb_status = USBD_FAIL;
break;
case HAL_BUSY :
usb_status = USBD_BUSY;
break;
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
break;
default :
usb_status = USBD_FAIL;
break;
}
return usb_status; return usb_status;
} }
@ -508,23 +472,8 @@ USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr); hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr);
switch (hal_status) { usb_status = USBD_Get_USB_Status(hal_status);
case HAL_OK :
usb_status = USBD_OK;
break;
case HAL_ERROR :
usb_status = USBD_FAIL;
break;
case HAL_BUSY :
usb_status = USBD_BUSY;
break;
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
break;
default :
usb_status = USBD_FAIL;
break;
}
return usb_status; return usb_status;
} }
@ -541,23 +490,8 @@ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)
hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);
switch (hal_status) { usb_status = USBD_Get_USB_Status(hal_status);
case HAL_OK :
usb_status = USBD_OK;
break;
case HAL_ERROR :
usb_status = USBD_FAIL;
break;
case HAL_BUSY :
usb_status = USBD_BUSY;
break;
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
break;
default :
usb_status = USBD_FAIL;
break;
}
return usb_status; return usb_status;
} }
@ -574,23 +508,8 @@ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_add
hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);
switch (hal_status) { usb_status = USBD_Get_USB_Status(hal_status);
case HAL_OK :
usb_status = USBD_OK;
break;
case HAL_ERROR :
usb_status = USBD_FAIL;
break;
case HAL_BUSY :
usb_status = USBD_BUSY;
break;
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
break;
default :
usb_status = USBD_FAIL;
break;
}
return usb_status; return usb_status;
} }
@ -627,23 +546,8 @@ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_a
hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);
switch (hal_status) { usb_status = USBD_Get_USB_Status(hal_status);
case HAL_OK :
usb_status = USBD_OK;
break;
case HAL_ERROR :
usb_status = USBD_FAIL;
break;
case HAL_BUSY :
usb_status = USBD_BUSY;
break;
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
break;
default :
usb_status = USBD_FAIL;
break;
}
return usb_status; return usb_status;
} }
@ -662,23 +566,8 @@ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, u
hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);
switch (hal_status) { usb_status = USBD_Get_USB_Status(hal_status);
case HAL_OK :
usb_status = USBD_OK;
break;
case HAL_ERROR :
usb_status = USBD_FAIL;
break;
case HAL_BUSY :
usb_status = USBD_BUSY;
break;
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
break;
default :
usb_status = USBD_FAIL;
break;
}
return usb_status; return usb_status;
} }
@ -697,23 +586,8 @@ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_a
hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);
switch (hal_status) { usb_status = USBD_Get_USB_Status(hal_status);
case HAL_OK :
usb_status = USBD_OK;
break;
case HAL_ERROR :
usb_status = USBD_FAIL;
break;
case HAL_BUSY :
usb_status = USBD_BUSY;
break;
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
break;
default :
usb_status = USBD_FAIL;
break;
}
return usb_status; return usb_status;
} }
@ -744,7 +618,11 @@ void USBD_LL_Delay(uint32_t Delay)
* @param state: Connection state (0: disconnected / 1: connected) * @param state: Connection state (0: disconnected / 1: connected)
* @retval None * @retval None
*/ */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
void PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
#else
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{ {
/* USER CODE BEGIN 6 */ /* USER CODE BEGIN 6 */
if (state == 1) if (state == 1)
@ -760,4 +638,34 @@ void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
/* USER CODE END 6 */ /* USER CODE END 6 */
} }
/**
* @brief Retuns the USB status depending on the HAL status:
* @param hal_status: HAL status
* @retval USB status
*/
USBD_StatusTypeDef USBD_Get_USB_Status(HAL_StatusTypeDef hal_status)
{
USBD_StatusTypeDef usb_status = USBD_OK;
switch (hal_status)
{
case HAL_OK :
usb_status = USBD_OK;
break;
case HAL_ERROR :
usb_status = USBD_FAIL;
break;
case HAL_BUSY :
usb_status = USBD_BUSY;
break;
case HAL_TIMEOUT :
usb_status = USBD_FAIL;
break;
default :
usb_status = USBD_FAIL;
break;
}
return usb_status;
}
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

33
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/usbd_conf.h
View File

@ -91,17 +91,15 @@
*/ */
/*---------- -----------*/ /*---------- -----------*/
#define USBD_MAX_NUM_INTERFACES 1 #define USBD_MAX_NUM_INTERFACES 1U
/*---------- -----------*/ /*---------- -----------*/
#define USBD_MAX_NUM_CONFIGURATION 1 #define USBD_MAX_NUM_CONFIGURATION 1U
/*---------- -----------*/ /*---------- -----------*/
#define USBD_MAX_STR_DESC_SIZ 512 #define USBD_MAX_STR_DESC_SIZ 512U
/*---------- -----------*/ /*---------- -----------*/
#define USBD_SUPPORT_USER_STRING 0 #define USBD_DEBUG_LEVEL 0U
/*---------- -----------*/ /*---------- -----------*/
#define USBD_DEBUG_LEVEL 0 #define USBD_SELF_POWERED 1U
/*---------- -----------*/
#define USBD_SELF_POWERED 1
/****************************************/ /****************************************/
/* #define for FS and HS identification */ /* #define for FS and HS identification */
@ -116,6 +114,27 @@
* @{ * @{
*/ */
/* Memory management macros */
/** Alias for memory allocation. */
#define USBD_malloc (uint32_t *)USBD_static_malloc
/** Alias for memory release. */
#define USBD_free USBD_static_free
/** Alias for memory set. */
#define USBD_memset /* Not used */
/** Alias for memory copy. */
#define USBD_memcpy /* Not used */
/** Alias for delay. */
#define USBD_Delay HAL_Delay
/* For footprint reasons and since only one allocation is handled in the HID class
driver, the malloc/free is changed into a static allocation method */
void *USBD_static_malloc(uint32_t size);
void USBD_static_free(void *p);
/* DEBUG macros */ /* DEBUG macros */

96
Target/Demo/ARMCM4_STM32F3_Discovery_F303VC_GCC/Boot/usbd_desc.c
View File

@ -129,6 +129,19 @@
* @brief Private functions declaration. * @brief Private functions declaration.
* @{ * @{
*/ */
static void Get_SerialNum(void);
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len);
/**
* @}
*/
/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
* @brief Private functions declaration for FS.
* @{
*/
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
@ -138,10 +151,6 @@ uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);
#ifdef USB_SUPPORT_USER_STRING_DESC
uint8_t * USBD_FS_USRStringDesc(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length);
#endif /* USB_SUPPORT_USER_STRING_DESC */
/** /**
* @} * @}
*/ */
@ -218,6 +227,14 @@ __ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =
/* Internal string descriptor. */ /* Internal string descriptor. */
__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; __ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
#pragma data_alignment=4
#endif
__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] __ALIGN_END = {
USB_SIZ_STRING_SERIAL,
USB_DESC_TYPE_STRING,
};
/** /**
* @} * @}
*/ */
@ -235,6 +252,7 @@ __ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;
*/ */
uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{ {
UNUSED(speed);
*length = sizeof(USBD_FS_DeviceDesc); *length = sizeof(USBD_FS_DeviceDesc);
return USBD_FS_DeviceDesc; return USBD_FS_DeviceDesc;
} }
@ -247,6 +265,7 @@ uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
*/ */
uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{ {
UNUSED(speed);
*length = sizeof(USBD_LangIDDesc); *length = sizeof(USBD_LangIDDesc);
return USBD_LangIDDesc; return USBD_LangIDDesc;
} }
@ -278,6 +297,7 @@ uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length
*/ */
uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{ {
UNUSED(speed);
USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
return USBD_StrDesc; return USBD_StrDesc;
} }
@ -290,15 +310,16 @@ uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *l
*/ */
uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)
{ {
if(speed == USBD_SPEED_HIGH) UNUSED(speed);
{ *length = USB_SIZ_STRING_SERIAL;
USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length);
} /* Update the serial number string descriptor with the data from the unique
else * ID */
{ Get_SerialNum();
USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); /* USER CODE BEGIN USBD_FS_SerialStrDescriptor */
}
return USBD_StrDesc; /* USER CODE END USBD_FS_SerialStrDescriptor */
return (uint8_t *) USBD_StringSerial;
} }
/** /**
@ -339,6 +360,55 @@ uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *leng
return USBD_StrDesc; return USBD_StrDesc;
} }
/**
* @brief Create the serial number string descriptor
* @param None
* @retval None
*/
static void Get_SerialNum(void)
{
uint32_t deviceserial0, deviceserial1, deviceserial2;
deviceserial0 = *(uint32_t *) DEVICE_ID1;
deviceserial1 = *(uint32_t *) DEVICE_ID2;
deviceserial2 = *(uint32_t *) DEVICE_ID3;
deviceserial0 += deviceserial2;
if (deviceserial0 != 0)
{
IntToUnicode(deviceserial0, &USBD_StringSerial[2], 8);
IntToUnicode(deviceserial1, &USBD_StringSerial[18], 4);
}
}
/**
* @brief Convert Hex 32Bits value into char
* @param value: value to convert
* @param pbuf: pointer to the buffer
* @param len: buffer length
* @retval None
*/
static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len)
{
uint8_t idx = 0;
for (idx = 0; idx < len; idx++)
{
if (((value >> 28)) < 0xA)
{
pbuf[2 * idx] = (value >> 28) + '0';
}
else
{
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
}
value = value << 4;
pbuf[2 * idx + 1] = 0;
}
}
/** /**
* @} * @}
*/ */

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