From d78ae71cdb5c4b1be66a0c1bd632d3a2c9769bbd Mon Sep 17 00:00:00 2001 From: Frank Voorburg Date: Fri, 20 Mar 2020 16:51:43 +0000 Subject: [PATCH] Refs #816. Added S32K144 EVB demo programs for the IAR Embedded Workbench. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@764 5dc33758-31d5-4daf-9ae8-b24bf3d40d73 --- .../Boot/S32K144_64_flash.icf | 121 + .../Boot/bin/openblt_s32k144.out | Bin 0 -> 152164 bytes .../Boot/bin/openblt_s32k144.srec | 486 + .../Boot/blt_conf.h | 176 + .../Boot/boot.dox | 7 + .../ARMCM4_S32K14_S32K144EVB_IAR/Boot/hooks.c | 307 + .../Boot/ide/s32k144.dep | 695 + .../Boot/ide/s32k144.ewd | 2966 ++++ .../Boot/ide/s32k144.ewp | 2266 +++ .../Boot/ide/s32k144.ewt | 2528 ++++ .../Boot/ide/s32k144.eww | 7 + .../ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.c | 108 + .../ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.h | 40 + .../Boot/lib/S32K144.h | 11937 ++++++++++++++++ .../Boot/lib/S32K144_features.h | 1507 ++ .../Boot/lib/devassert.h | 84 + .../Boot/lib/device_registers.h | 70 + .../Boot/lib/s32_core_cm4.h | 209 + .../Boot/lib/startup.c | 248 + .../Boot/lib/startup.h | 133 + .../Boot/lib/system_S32K144.c | 197 + .../Boot/lib/system_S32K144.h | 111 + .../ARMCM4_S32K14_S32K144EVB_IAR/Boot/main.c | 208 + .../Boot/startup_S32K144.s | 693 + .../Prog/S32K144_64_flash.icf | 121 + .../Prog/bin/demoprog_s32k144.out | Bin 0 -> 60328 bytes .../Prog/bin/demoprog_s32k144.srec | 240 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.c | 772 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.h | 40 + .../Prog/header.h | 42 + .../Prog/ide/s32k144.dep | 264 + .../Prog/ide/s32k144.ewd | 2966 ++++ .../Prog/ide/s32k144.ewp | 2167 +++ .../Prog/ide/s32k144.ewt | 2432 ++++ .../Prog/ide/s32k144.eww | 7 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.c | 96 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.h | 39 + .../Prog/lib/S32K144.h | 11937 ++++++++++++++++ .../Prog/lib/S32K144_features.h | 1507 ++ .../Prog/lib/devassert.h | 84 + .../Prog/lib/device_registers.h | 70 + .../Prog/lib/s32_core_cm4.h | 209 + .../Prog/lib/startup.c | 248 + .../Prog/lib/startup.h | 133 + .../Prog/lib/system_S32K144.c | 197 + .../Prog/lib/system_S32K144.h | 111 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/main.c | 204 + .../Prog/prog.dox | 13 + .../Prog/startup_S32K144.s | 693 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.c | 88 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.h | 38 + .../ARMCM4_S32K14_S32K144EVB_IAR/demo.dox | 8 + Target/Source/ARMCM4_S32K14/IAR/cpu_comp.c | 59 + Target/Source/ARMCM4_S32K14/rs232.c | 2 +- 54 files changed, 49890 insertions(+), 1 deletion(-) create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/S32K144_64_flash.icf create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/bin/openblt_s32k144.out create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/bin/openblt_s32k144.srec create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/blt_conf.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/boot.dox create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/hooks.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.dep create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.ewd create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.ewp create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.ewt create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.eww create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/S32K144.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/S32K144_features.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/devassert.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/device_registers.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/s32_core_cm4.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/startup.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/startup.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/system_S32K144.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/system_S32K144.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/main.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/startup_S32K144.s create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/S32K144_64_flash.icf create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/bin/demoprog_s32k144.out create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/bin/demoprog_s32k144.srec create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/header.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.dep create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.ewd create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.ewp create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.ewt create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.eww create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/S32K144.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/S32K144_features.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/devassert.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/device_registers.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/s32_core_cm4.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/startup.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/startup.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/system_S32K144.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/system_S32K144.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/main.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/prog.dox create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/startup_S32K144.s create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/demo.dox create mode 100644 Target/Source/ARMCM4_S32K14/IAR/cpu_comp.c diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/S32K144_64_flash.icf b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/S32K144_64_flash.icf new file mode 100644 index 00000000..295c8d15 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/S32K144_64_flash.icf @@ -0,0 +1,121 @@ +/* +** ################################################################### +** Processor: S32K144 with 64 KB SRAM +** Compiler: IAR ANSI C/C++ Compiler for ARM +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright (c) 2015-2016 Freescale Semiconductor, Inc. +** Copyright 2017 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* If symbol __flash_vector_table__=1 is defined at link time + * the interrupt vector will not be copied to RAM. + * Warning: Using the interrupt vector from FLASH will not allow + * INT_SYS_InstallHandler because the section is Read Only. + */ +define symbol __ram_vector_table_size__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x00000400; +define symbol __ram_vector_table_offset__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x000003FF; + +/* Flash */ +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_flash_config_start = 0x00000400; +define symbol m_flash_config_end = 0x0000040F; + +define symbol m_text_start = 0x00000410; +define symbol m_text_end = 0x00001FFF; + +/* SRAM_L */ +define symbol m_interrupts_ram_start = 0x1FFF8000; +define symbol m_interrupts_ram_end = 0x1FFF8000 + __ram_vector_table_offset__; + +define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; +define symbol m_data_end = 0x1FFFFFFF; + +/* SRAM_U */ +define symbol m_data_2_start = 0x20000000; +define symbol m_data_2_end = 0x20006FFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x00000400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x00000400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = isdefinedsymbol(__flash_vector_table__) ? m_interrupts_start : m_interrupts_ram_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; + +define exported symbol __RAM_START = m_interrupts_ram_start; +define exported symbol __RAM_END = m_data_2_end; + +define memory mem with size = 4G; +define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end]; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA_region_2 = mem:[from m_data_2_start to m_data_2_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end]; +define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; + + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* Custom Section Block that can be used to place data at absolute address. */ +/* Use __attribute__((section (".customSection"))) to place data here. */ +define block customSectionBlock { section .customSection }; + +define block __CODE_ROM { section .textrw_init }; +define block __CODE_RAM { section .textrw }; + +initialize manually { section .textrw }; +initialize manually { section .bss }; +initialize manually { section .customSection }; +initialize manually { section .data }; +initialize manually { section __DLIB_PERTHREAD }; +do not initialize { section .noinit, section .bss, section .data, section __DLIB_PERTHREAD, section .customSection }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in m_flash_config_region { section FlashConfig }; +place in TEXT_region { readonly }; +place in TEXT_region { block __CODE_ROM }; +place in DATA_region { block RW }; +place in DATA_region { block __CODE_RAM }; +place in DATA_region_2 { first block customSectionBlock }; +place in DATA_region_2 { block ZI }; +place in DATA_region_2 { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in m_interrupts_ram_region { section m_interrupts_ram }; + + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/bin/openblt_s32k144.out b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/bin/openblt_s32k144.out new file mode 100644 index 0000000000000000000000000000000000000000..842d7c8e4d6ac348eef0b60373e87ba7e9ba285a GIT binary patch literal 152164 zcmeEv31C#k{r|jccXMyZ2?W@LD*@yd@gyV=2m&Gjk4l?_WHC`lLJo}9BU%r%R;@>C zJ*u_VYPGGRSZk&7YpvB*ZG!r%wFmL2+FIKcP!>?~|9ocN+antgV>Z~|-;#P#|ef=74f3V$)MhbB>?jygrzmUNfI`Chq13kU2{TKE0Y!8Znc4^P3%0SQ5 z?ZNgePnG&@T5!Za0&`7~0;^FO&^+6NwQYY42E2a^?h*uN!%BiMFjWAUwro zTQ_Ni$z47n06$2}i+r&? zXj&rR+S5_y?si-PrU-l->?mX0Tiyv=9NbJ=v~k;mf643$27Fz?UEZs5myaAWynf_W zC1RTxH%&adNh?a1R7~6J7L$h7jwD4B_Z|&MPm$57$*1UY{JOg6GFxojBm%eZafzvT z+p(o%v*rU)-`pN-%1o>q^1hZfxl0syZ0gy4V$ar1`WE0UKw8WkT9;6FRW5!< zsHbO|dM4XXul>xlpSkuk{euhF)2EmqI)!iRrltkn&Dxml!3PYjE*(6Wog#2w5QRXO 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+S9031DFDE2 diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/blt_conf.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/blt_conf.h new file mode 100644 index 00000000..966813dd --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/blt_conf.h @@ -0,0 +1,176 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/blt_conf.h +* \brief Bootloader configuration header file. +* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef BLT_CONF_H +#define BLT_CONF_H + +/**************************************************************************************** +* C P U D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* To properly initialize the baudrate clocks of the communication interface, typically + * the speed of the crystal oscillator and/or the speed at which the system runs is + * needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and + * BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is + * not dependent on the targets architecture, the byte ordering needs to be known. + * Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects + * little endian mode. + * + * Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be + * called the moment the user program is about to be started. This could be used to + * de-initialize application specific parts, for example to stop blinking an LED, etc. + */ +/** \brief Frequency of the external crystal oscillator. */ +#define BOOT_CPU_XTAL_SPEED_KHZ (8000) +/** \brief Desired system speed. */ +#define BOOT_CPU_SYSTEM_SPEED_KHZ (80000) +/** \brief Motorola or Intel style byte ordering. */ +#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0) +/** \brief Enable/disable hook function call right before user program start. */ +#define BOOT_CPU_USER_PROGRAM_START_HOOK (1) + + +/**************************************************************************************** +* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N +****************************************************************************************/ +/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE + * configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed + * in bits/second. The maximum amount of data bytes in a message for data transmission + * and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA, + * respectively. It is common for a microcontroller to have more than 1 UART interface + * on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface. + * + */ +/** \brief Enable/disable UART transport layer. */ +#define BOOT_COM_RS232_ENABLE (1) +/** \brief Configure the desired communication speed. */ +#define BOOT_COM_RS232_BAUDRATE (57600) +/** \brief Configure number of bytes in the target->host data packet. */ +#define BOOT_COM_RS232_TX_MAX_DATA (64) +/** \brief Configure number of bytes in the host->target data packet. */ +#define BOOT_COM_RS232_RX_MAX_DATA (64) +/** \brief Select the desired UART peripheral as a zero based index. */ +#define BOOT_COM_RS232_CHANNEL_INDEX (1) + +/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE + * configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed + * in bits/second. Two CAN messages are reserved for communication with the host. The + * message identifier for sending data from the target to the host is configured with + * BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with + * BOOT_COM_CAN_RXMSG_ID. Note that an extended 29-bit CAN identifier is configured by + * OR-ing with mask 0x80000000. The maximum amount of data bytes in a message for data + * transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and + * BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more + * than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the + * CAN controller channel. + * + */ +/** \brief Enable/disable CAN transport layer. */ +#define BOOT_COM_CAN_ENABLE (1) +/** \brief Configure the desired CAN baudrate. */ +#define BOOT_COM_CAN_BAUDRATE (500000) +/** \brief Configure CAN message ID target->host. */ +#define BOOT_COM_CAN_TX_MSG_ID (0x7E1 /*| 0x80000000*/) +/** \brief Configure number of bytes in the target->host CAN message. */ +#define BOOT_COM_CAN_TX_MAX_DATA (8) +/** \brief Configure CAN message ID host->target. */ +#define BOOT_COM_CAN_RX_MSG_ID (0x667 /*| 0x80000000*/) +/** \brief Configure number of bytes in the host->target CAN message. */ +#define BOOT_COM_CAN_RX_MAX_DATA (8) +/** \brief Select the desired CAN peripheral as a zero based index. */ +#define BOOT_COM_CAN_CHANNEL_INDEX (0) + + +/**************************************************************************************** +* B A C K D O O R E N T R Y C O N F I G U R A T I O N +****************************************************************************************/ +/* It is possible to implement an application specific method to force the bootloader to + * stay active after a reset. Such a backdoor entry into the bootloader is desired in + * situations where the user program does not run properly and therefore cannot + * reactivate the bootloader. By enabling these hook functions, the application can + * implement the backdoor, which overrides the default backdoor entry that is programmed + * into the bootloader. When desired for security purposes, these hook functions can + * also be implemented in a way that disables the backdoor entry altogether. + */ +/** \brief Enable/disable the backdoor override hook functions. */ +#define BOOT_BACKDOOR_HOOKS_ENABLE (0) + + +/**************************************************************************************** +* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* The NVM driver typically supports erase and program operations of the internal memory + * present on the microcontroller. Through these hook functions the NVM driver can be + * extended to support additional memory types such as external flash memory and serial + * eeproms. The size of the internal memory in kilobytes is specified with configurable + * BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can + * be overridden with a application specific method by enabling configuration switch + * BOOT_NVM_CHECKSUM_HOOKS_ENABLE. + */ +/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */ +#define BOOT_NVM_HOOKS_ENABLE (0) +/** \brief Configure the size of the default memory device (typically flash EEPROM). */ +#define BOOT_NVM_SIZE_KB (512) +/** \brief Enable/disable hooks functions to override the user program checksum handling. */ +#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0) + + +/**************************************************************************************** +* W A T C H D O G D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* The COP driver cannot be configured internally in the bootloader, because its use + * and configuration is application specific. The bootloader does need to service the + * watchdog in case it is used. When the application requires the use of a watchdog, + * set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through + * hook functions. + */ +/** \brief Enable/disable the hook functions for controlling the watchdog. */ +#define BOOT_COP_HOOKS_ENABLE (1) + + +/**************************************************************************************** +* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N +****************************************************************************************/ +/* A security mechanism can be enabled in the bootloader's XCP module by setting configu- + * rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming + * operations can be performed, access to this resource need to be unlocked. + * In the Microboot settings on tab "XCP Protection" you need to specify a DLL that + * implements the unlocking algorithm. The demo programs are configured for the (simple) + * algorithm in "libseednkey.dll". The source code for this DLL is available so it can be + * customized to your needs. + * During the unlock sequence, Microboot requests a seed from the bootloader, which is in + * the format of a byte array. Using this seed the unlock algorithm in the DLL computes + * a key, which is also a byte array, and sends this back to the bootloader. The + * bootloader then verifies this key to determine if programming and erase operations are + * permitted. + * After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook() + * are called by the bootloader to obtain the seed and to verify the key, respectively. + */ +#define BOOT_XCP_SEED_KEY_ENABLE (0) + + +#endif /* BLT_CONF_H */ +/*********************************** end of blt_conf.h *********************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/boot.dox b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/boot.dox new file mode 100644 index 00000000..e9e14acb --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/boot.dox @@ -0,0 +1,7 @@ +/** +\defgroup Boot_ARMCM4_S32K14_S32K144EVB_IAR Bootloader +\brief Bootloader. +\ingroup ARMCM4_S32K14_S32K144EVB_IAR +*/ + + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/hooks.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/hooks.c new file mode 100644 index 00000000..bed8d469 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/hooks.c @@ -0,0 +1,307 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/hooks.c +* \brief Bootloader callback source file. +* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "led.h" /* LED driver header */ +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* B A C K D O O R E N T R Y H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Initializes the backdoor entry option. +** \return none. +** +****************************************************************************************/ +void BackDoorInitHook(void) +{ +} /*** end of BackDoorInitHook ***/ + + +/************************************************************************************//** +** \brief Checks if a backdoor entry is requested. +** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool BackDoorEntryHook(void) +{ + /* default implementation always activates the bootloader after a reset */ + return BLT_TRUE; +} /*** end of BackDoorEntryHook ***/ +#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* C P U D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0) +/************************************************************************************//** +** \brief Callback that gets called when the bootloader is about to exit and +** hand over control to the user program. This is the last moment that +** some final checking can be performed and if necessary prevent the +** bootloader from activiting the user program. +** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep +** keep the bootloader active. +** +****************************************************************************************/ +blt_bool CpuUserProgramStartHook(void) +{ + /* additional and optional backdoor entry through the pushbutton (SW2) on the board. to + * force the bootloader to stay active after reset, keep it pressed during reset. + */ + if ((PTC->PDIR & GPIO_PDIR_PDI(1 << 12U)) != 0U) + { + /* pushbutton pressed, so do not start the user program and keep the + * bootloader active instead. + */ + return BLT_FALSE; + } + + /* clean up the LED driver */ + LedBlinkExit(); + + /* okay to start the user program */ + return BLT_TRUE; +} /*** end of CpuUserProgramStartHook ***/ +#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */ + + +/**************************************************************************************** +* W A T C H D O G D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_COP_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Callback that gets called at the end of the internal COP driver +** initialization routine. It can be used to configure and enable the +** watchdog. +** \return none. +** +****************************************************************************************/ +void CopInitHook(void) +{ + /* this function is called upon initialization. might as well use it to initialize + * the LED driver. It is kind of a visual watchdog anyways. + */ + LedBlinkInit(100); +} /*** end of CopInitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the end of the internal COP driver +** service routine. This gets called upon initialization and during +** potential long lasting loops and routine. It can be used to service +** the watchdog to prevent a watchdog reset. +** \return none. +** +****************************************************************************************/ +void CopServiceHook(void) +{ + /* run the LED blink task. this is a better place to do it than in the main() program + * loop. certain operations such as flash erase can take a long time, which would cause + * a blink interval to be skipped. this function is also called during such operations, + * so no blink intervals will be skipped when calling the LED blink task here. + */ + LedBlinkTask(); +} /*** end of CopServiceHook ***/ +#endif /* BOOT_COP_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_NVM_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Callback that gets called at the start of the internal NVM driver +** initialization routine. +** \return none. +** +****************************************************************************************/ +void NvmInitHook(void) +{ +} /*** end of NvmInitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of a firmware update to reinitialize +** the NVM driver. +** \return none. +** +****************************************************************************************/ +void NvmReinitHook(void) +{ +} /*** end of NvmReinitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of the NVM driver write +** routine. It allows additional memory to be operated on. If the address +** is not within the range of the additional memory, then +** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't +** been written yet. +** \param addr Start address. +** \param len Length in bytes. +** \param data Pointer to the data buffer. +** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is +** not within the supported memory range, or BLT_NVM_ERROR is the write +** operation failed. +** +****************************************************************************************/ +blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data) +{ + return BLT_NVM_NOT_IN_RANGE; +} /*** end of NvmWriteHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of the NVM driver erase +** routine. It allows additional memory to be operated on. If the address +** is not within the range of the additional memory, then +** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory +** hasn't been erased yet. +** \param addr Start address. +** \param len Length in bytes. +** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is +** not within the supported memory range, or BLT_NVM_ERROR is the erase +** operation failed. +** +****************************************************************************************/ +blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len) +{ + return BLT_NVM_NOT_IN_RANGE; +} /*** end of NvmEraseHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the end of the NVM programming session. +** \return BLT_TRUE is successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmDoneHook(void) +{ + return BLT_TRUE; +} /*** end of NvmDoneHook ***/ +#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */ + + +#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Verifies the checksum, which indicates that a valid user program is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmVerifyChecksumHook(void) +{ + return BLT_TRUE; +} /*** end of NvmVerifyChecksum ***/ + + +/************************************************************************************//** +** \brief Writes a checksum of the user program to non-volatile memory. This is +** performed once the entire user program has been programmed. Through +** the checksum, the bootloader can check if a valid user programming is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmWriteChecksumHook(void) +{ + return BLT_TRUE; +} +#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_XCP_SEED_KEY_ENABLE > 0) +/************************************************************************************//** +** \brief Provides a seed to the XCP master that will be used for the key +** generation when the master attempts to unlock the specified resource. +** Called by the GET_SEED command. +** \param resource Resource that the seed if requested for (XCP_RES_XXX). +** \param seed Pointer to byte buffer wher the seed will be stored. +** \return Length of the seed in bytes. +** +****************************************************************************************/ +blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed) +{ + /* request seed for unlocking ProGraMming resource */ + if ((resource & XCP_RES_PGM) != 0) + { + seed[0] = 0x55; + } + + /* return seed length */ + return 1; +} /*** end of XcpGetSeedHook ***/ + + +/************************************************************************************//** +** \brief Called by the UNLOCK command and checks if the key to unlock the +** specified resource was correct. If so, then the resource protection +** will be removed. +** \param resource resource to unlock (XCP_RES_XXX). +** \param key pointer to the byte buffer holding the key. +** \param len length of the key in bytes. +** \return 1 if the key was correct, 0 otherwise. +** +****************************************************************************************/ +blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len) +{ + /* suppress compiler warning for unused parameter */ + len = len; + + /* the example key algorithm in "libseednkey.dll" works as follows: + * - PGM will be unlocked if key = seed - 1 + */ + + /* check key for unlocking ProGraMming resource */ + if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1))) + { + /* correct key received for unlocking PGM resource */ + return 1; + } + + /* still here so key incorrect */ + return 0; +} /*** end of XcpVerifyKeyHook ***/ +#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */ + + +/*********************************** end of hooks.c ************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.dep b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.dep new file mode 100644 index 00000000..3ceeceb4 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.dep @@ -0,0 +1,695 @@ + + + 4 + 684628677 + + Debug + + $PROJ_DIR$\..\main.c + $PROJ_DIR$\..\..\..\..\Source\assert.c + $PROJ_DIR$\..\blt_conf.h + $PROJ_DIR$\..\hooks.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\IAR\cpu_comp.c + $PROJ_DIR$\..\lib\device_registers.h + $PROJ_DIR$\..\startup_S32K144.s + $PROJ_DIR$\..\led.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\can.c + $PROJ_DIR$\..\lib\system_S32K144.c + $PROJ_DIR$\..\lib\S32K144_features.h + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\cpu.c + $PROJ_DIR$\..\lib\startup.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\flash.c + $PROJ_DIR$\..\led.h + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\flash.h + $PROJ_DIR$\..\lib\startup.h + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\rs232.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\timer.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\types.h + $PROJ_DIR$\..\lib\S32K144.h + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\nvm.c + $PROJ_DIR$\..\lib\devassert.h + $PROJ_DIR$\..\lib\s32_core_cm4.h + $PROJ_DIR$\..\lib\system_S32K144.h + $PROJ_DIR$\..\obj\hooks.__cstat.et + $PROJ_DIR$\..\obj\rs232.__cstat.et + $PROJ_DIR$\..\obj\com.xcl + $PROJ_DIR$\..\obj\nvm.__cstat.et + $PROJ_DIR$\..\obj\cop.__cstat.et + $TOOLKIT_DIR$\inc\c\string.h + $TOOLKIT_DIR$\inc\c\ysizet.h + $PROJ_DIR$\..\obj\cpu.xcl + $PROJ_DIR$\..\obj\assert.__cstat.et + $PROJ_DIR$\..\obj\can.__cstat.et + $PROJ_DIR$\..\obj\can.xcl + $PROJ_DIR$\..\obj\nvm.xcl + $PROJ_DIR$\..\obj\cop.xcl + $PROJ_DIR$\..\obj\file.xcl + $PROJ_DIR$\..\obj\cpu_comp.__cstat.et + $TOOLKIT_DIR$\inc\c\DLib_Product_string.h + $PROJ_DIR$\..\obj\backdoor.__cstat.et + $PROJ_DIR$\..\obj\file.__cstat.et + $PROJ_DIR$\..\obj\xcp.__cstat.et + $TOOLKIT_DIR$\inc\c\ctype.h + $PROJ_DIR$\..\obj\can.o + $PROJ_DIR$\..\obj\assert.xcl + $PROJ_DIR$\..\obj\cpu_comp.xcl + $PROJ_DIR$\..\obj\backdoor.xcl + $PROJ_DIR$\..\obj\flash.__cstat.et + $PROJ_DIR$\..\obj\net.__cstat.et + $PROJ_DIR$\..\obj\cpu.__cstat.et + $PROJ_DIR$\..\obj\hooks.xcl + $PROJ_DIR$\..\obj\com.__cstat.et + $PROJ_DIR$\..\obj\hooks.o + $PROJ_DIR$\..\obj\rs232.xcl + $PROJ_DIR$\..\obj\net.xcl + $PROJ_DIR$\..\obj\net.o + $PROJ_DIR$\..\obj\file.o + $PROJ_DIR$\..\obj\cpu_comp.o + $PROJ_DIR$\..\obj\cop.o + $PROJ_DIR$\..\obj\xcp.o + $PROJ_DIR$\..\obj\flash.xcl + $PROJ_DIR$\..\obj\flash.o + $PROJ_DIR$\..\obj\cpu.o + $PROJ_DIR$\..\obj\backdoor.o + $PROJ_DIR$\..\obj\rs232.o + $PROJ_DIR$\..\obj\assert.o + $PROJ_DIR$\..\obj\nvm.o + $PROJ_DIR$\..\obj\com.o + $PROJ_DIR$\..\obj\startup_S32K144.o + $PROJ_DIR$\..\obj\s32k144.pbd + $PROJ_DIR$\..\obj\boot.__cstat.et + $PROJ_DIR$\..\obj\timer.xcl + $PROJ_DIR$\..\obj\boot.xcl + $PROJ_DIR$\..\obj\led.o + $PROJ_DIR$\..\obj\startup.__cstat.et + $PROJ_DIR$\..\bin\openblt_s32k144.out + $PROJ_DIR$\..\obj\xcp.xcl + $PROJ_DIR$\..\obj\timer.o + $TOOLKIT_DIR$\inc\c\yvals.h + $PROJ_DIR$\..\timer.c + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $PROJ_DIR$\..\obj\led.xcl + $PROJ_DIR$\..\bin\demoprog_s32k144.srec + $PROJ_DIR$\..\obj\main.xcl + $PROJ_DIR$\..\header.h + $PROJ_DIR$\..\obj\openblt_s32k144.map + $PROJ_DIR$\..\obj\main.o + $PROJ_DIR$\..\S32K144_64_flash.icf + $TOOLKIT_DIR$\inc\c\stdbool.h + $PROJ_DIR$\..\obj\system_S32K144.o + $PROJ_DIR$\..\obj\startup.xcl + $PROJ_DIR$\..\obj\boot.o + $PROJ_DIR$\..\obj\system_S32K144.__cstat.et + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $PROJ_DIR$\..\obj\timer.__cstat.et + $TOOLKIT_DIR$\lib\shb_l.a + $PROJ_DIR$\..\obj\main.__cstat.et + $TOOLKIT_DIR$\inc\c\ycheck.h + $PROJ_DIR$\..\boot.c + $PROJ_DIR$\..\..\..\..\Source\com.h + $PROJ_DIR$\..\..\..\..\Source\xcp.c + $PROJ_DIR$\..\..\..\..\Source\cop.c + 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$PROJ_DIR$\..\..\..\..\Source\plausibility.h + + + $PROJ_DIR$\..\..\..\..\Source\rs232.h + + + $PROJ_DIR$\..\..\..\..\Source\timer.h + + + $PROJ_DIR$\..\..\..\..\Source\usb.h + + + $PROJ_DIR$\..\..\..\..\Source\xcp.c + + + $PROJ_DIR$\..\..\..\..\Source\xcp.h + + + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.eww b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.eww new file mode 100644 index 00000000..fcec0790 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\s32k144.ewp + + + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.c new file mode 100644 index 00000000..df4ca52b --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.c @@ -0,0 +1,108 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.c +* \brief LED driver source file. +* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "led.h" /* module header */ +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Holds the desired LED blink interval time. */ +static blt_int16u ledBlinkIntervalMs; + + +/************************************************************************************//** +** \brief Initializes the LED blink driver. +** \param interval_ms Specifies the desired LED blink interval time in milliseconds. +** \return none. +** +****************************************************************************************/ +void LedBlinkInit(blt_int16u interval_ms) +{ + /* LED GPIO pin configuration. PD0 = GPIO, MUX = ALT1. */ + PORTD->PCR[0] |= PORT_PCR_MUX(1); + /* configure Port D pin 0 GPIO as digital output */ + PTD->PDDR |= GPIO_PDDR_PDD(0x00000001); + /* turn the LED off on Port D pin 0 */ + PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001); + /* store the interval time between LED toggles */ + ledBlinkIntervalMs = interval_ms; +} /*** end of LedBlinkInit ***/ + + +/************************************************************************************//** +** \brief Task function for blinking the LED as a fixed timer interval. +** \return none. +** +****************************************************************************************/ +void LedBlinkTask(void) +{ + static blt_bool ledOn = BLT_FALSE; + static blt_int32u nextBlinkEvent = 0; + + /* check for blink event */ + if (TimerGet() >= nextBlinkEvent) + { + /* toggle the LED state */ + if (ledOn == BLT_FALSE) + { + ledOn = BLT_TRUE; + /* Turn the LED on. */ + PTD->PCOR |= GPIO_PCOR_PTCO(0x00000001); + } + else + { + ledOn = BLT_FALSE; + /* Turn the LED off. */ + PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001); + } + /* schedule the next blink event */ + nextBlinkEvent = TimerGet() + ledBlinkIntervalMs; + } +} /*** end of LedBlinkTask ***/ + + +/************************************************************************************//** +** \brief Cleans up the LED blink driver. This is intended to be used upon program +** exit. +** \return none. +** +****************************************************************************************/ +void LedBlinkExit(void) +{ + /* Turn the LED off. */ + PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001); +} /*** end of LedBlinkExit ***/ + + +/*********************************** end of led.c **************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.h new file mode 100644 index 00000000..6889ee12 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.h @@ -0,0 +1,40 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.h +* \brief LED driver header file. +* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef LED_H +#define LED_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void LedBlinkInit(blt_int16u interval_ms); +void LedBlinkTask(void); +void LedBlinkExit(void); + + +#endif /* LED_H */ +/*********************************** end of led.h **************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/S32K144.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/S32K144.h new file mode 100644 index 00000000..ae04b8bb --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/S32K144.h @@ -0,0 +1,11937 @@ +/* +** ################################################################### +** Processor: S32K144 +** Reference manual: S32K1XXRM Rev. 9, 09/2018 +** Version: rev. 4.2, 2019-02-19 +** Build: b190219 +** +** Abstract: +** Peripheral Access Layer for S32K144 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-04-09) - Iulian Talpiga +** Initial version. +** - rev. 1.1 (2015-05-19) - Bogdan Nitu +** Updated interrupts table +** Removed SIM_CHIPCTL_DAC2CMP +** Compacted PORT_PCR registers +** Compacted PCC registers +** - rev. 1.2 (2015-06-02) - Bogdan Nitu +** Added 'U' suffix to all integer constants +** Use "" instead of <> for Platform type inclusion +** CNT register from WDOG module is RW +** - rev. 1.3 (2015-08-05) - Iulian Talpiga +** Synchronized with latest RDP +** Removed OSC32 module +** Removed reserved registers +** Incorporated bit band acces macros +** Switched to standard C99 data types +** Added 'u' to constants +** Added size defines for register arrays +** Define peripheral instance count +** - rev. 1.4 (2015-08-10) - Iulian Talpiga +** Compacted TRGMUX registers +** Defined array index offsets for PCC and TRGMUX +** Added FPU registers +** Group FTM channel registers +** Added interrupt information to peripherals +** Renamed CAN interrupts according to the reference manual +** Added author information to revisions +** - rev. 1.5 (2015-09-16) - Iulian Talpiga +** Renamed NVIC and SCB to avoid conflict +** Compacted CAN Wake-up Message buffers +** Added CAN embedded RAM +** Updated interrupts: LPIT, FTFE, LPUART,ACMP +** Corrected ADC_SC1_ADCH_WIDTH +** Compacted PDB registers +** Corrected CAN, FTM, and PDB count defines +** Guarding register acces macro against redefintion +** - rev. 1.6 (2015-09-29) - Iulian Talpiga +** Added WATER and FIFO registers to LPUART. +** - rev. 1.7 (2015-10-21) - Iulian Talpiga +** Updated ADC, AIPS, CMP, LMEM, LPTMR, PMC, PORT, RCM, RTC, SCG, SIM +** Compacted MPU and LPIT +** Added FSL_SysTick +** Updated doxygen documentation grouping +** Updated interrupts: RCM +** - rev. 1.8 (2016-01-06) - Iulian Talpiga +** Updated DMA, compacted TCD registers +** Updated SCG, removed SC2P - SC16P +** Added 8 and 16 bit access to DATA register, CRC module +** - rev. 1.9 (2016-02-15) - Iulian Talpiga +** Updated CRC, renamed DATA union +** Updated PMC, added CLKBIASDIS bitfield +** Added FSL_NVIC registers to SVD +** - rev. 2.0 (2016-04-07) - Iulian Talpiga +** Updated support for Rev2.0 silicon (0N47T) +** Updated ADC, AIPS, DMA, FlexIO, FTM, GPIO, LPI2C, LPIT, LPSPI, MCM, MPU, MSCM, PMC, RTC, RCM, PCC, RTC, SCG, SIM, TRGMUX and WDOG module +** Updated interrupts +** Added EIM and ERM modules +** Added EIM and ERM modules +** - rev. 2.1 (2016-06-10) - Iulian Talpiga +** Updated to latest RM +** Minor changes to: CAN, EIM, LPI2C, MPU, PCC, PMC, RTC, SIM and TRGMUX +** - rev. 2.2 (2016-08-02) - Iulian Talpiga +** Updated to latest RM +** Minor changes to: ADC, CAN, CRC, FTFC, LMEM, LPI2C, MCM, MSCM, PCC, RTC, SIM +** Added CSE_PRAM +** - rev. 2.3 (2016-09-09) - Iulian Talpiga +** Updated to latest RM +** Minor changes to: PCC, FSL_NVIC and FTM +** - rev. 2.4 (2016-09-28) - Iulian Talpiga +** Fix RAMn array size in FlexCAN +** Fix FCSESTAT bit order +** Added CP0CFG0, CP0CFG1,CP0CFG2 and CP0CFG3 in MSCM +** Fixed STIR register in FSL_NVIC +** Fixed SHPR3 and ACTLR registers in FSL_SCB +** - rev. 2.5 (2016-11-25) - Iulian Talpiga +** Fix FRAC bit-field in PCC module +** Removed BITBAND_ACCESS macros +** Added MISRA declarations +** Updated copyright +** Changed prefix of NVIC, SCB and SysTick to S32_ +** - rev. 2.6 (2017-01-09) - Iulian Talpiga +** Fix interrupts for CAN, LPUART, FTFC +** - rev. 2.7 (2017-02-22) - Iulian Talpiga +** Update header as per rev S32K14XRM Rev. 2, 02/2017 +** Updated modules AIPS, CAN, LPI2C, LPSPI, MCM, MPU, SCG and SIM +** - rev. 2.8 (2017-03-27) - Iulian Talpiga +** Synchronized PCC_FlexIO on S32K Family +** - rev. 3.0 (2017-08-04) - Mihai Volmer +** Update header as per rev S32K1XXRM Rev. 4, 06/2017 +** Updated modules CAN, MCM and PORTn +** - rev. 3.1 (2017-09-25) - Andrei Bolojan +** Update NVIC Size of Registers Arrays +** - rev. 4.0 (2018-02-28) - Mihai Volmer +** Updated header as per rev S32K1XXRM Rev. 6, 12/2017 +** Updated modules ERM, I2C, MSCM and SIM +** - rev. 4.1 (2018-07-19) - Dan Nastasa +** Updated the header based on S32K1XXRM Rev. 8, 06/2018. +** - rev. 4.2 (2019-02-19) - Ionut Pavel +** Updated the header based on S32K1XXRM Rev. 9, 09/2018. +** +** ################################################################### +*/ + +/*! + * @file S32K144.h + * @version 4.2 + * @date 2019-02-19 + * @brief Peripheral Access Layer for S32K144 + * + * This file contains register definitions and macros for easy access to their + * bit fields. + * + * This file assumes LITTLE endian system. + */ + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced +* The SoC header defines typedef for all modules. +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced +* The SoC header defines macros for all modules and registers. +* +* @section [global] +* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro +* These are generated macros used for accessing the bit-fields from registers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.1, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.2, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.4, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.5, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler +* This type qualifier is needed to ensure correct I/O access and addressing. +*/ + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(S32K144_H_) /* Check if memory map has not been already included */ +#define S32K144_H_ +#define MCU_S32K144 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error S32K144 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0400u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0002u + +/* ---------------------------------------------------------------------------- + -- Generic macros + ---------------------------------------------------------------------------- */ + +/* IO definitions (access restrictions to peripheral registers) */ +/** +* IO Type Qualifiers are used +* \li to specify the access to peripheral variables. +* \li for automatic generation of peripheral register debug information. +*/ +#ifndef __IO +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + + +/** +* @brief 32 bits memory read macro. +*/ +#if !defined(REG_READ32) + #define REG_READ32(address) (*(volatile uint32_t*)(address)) +#endif + +/** +* @brief 32 bits memory write macro. +*/ +#if !defined(REG_WRITE32) + #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value)) +#endif + +/** +* @brief 32 bits bits setting macro. +*/ +#if !defined(REG_BIT_SET32) + #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask)) +#endif + +/** +* @brief 32 bits bits clearing macro. +*/ +#if !defined(REG_BIT_CLEAR32) + #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask)))) +#endif + +/** +* @brief 32 bit clear bits and set with new value +* @note It is user's responsability to make sure that value has only "mask" bits set - (value&~mask)==0 +*/ +#if !defined(REG_RMW32) + #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value))))) +#endif + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers for S32K144 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers_S32K144 Interrupt vector numbers for S32K144 + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 139u /**< Number of interrupts in the Vector table */ + +/** + * @brief Defines the Interrupt Numbers definitions + * + * This enumeration is used to configure the interrupts. + * + * Implements : IRQn_Type_Class + */ +typedef enum +{ + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0u, /**< DMA channel 0 transfer complete */ + DMA1_IRQn = 1u, /**< DMA channel 1 transfer complete */ + DMA2_IRQn = 2u, /**< DMA channel 2 transfer complete */ + DMA3_IRQn = 3u, /**< DMA channel 3 transfer complete */ + DMA4_IRQn = 4u, /**< DMA channel 4 transfer complete */ + DMA5_IRQn = 5u, /**< DMA channel 5 transfer complete */ + DMA6_IRQn = 6u, /**< DMA channel 6 transfer complete */ + DMA7_IRQn = 7u, /**< DMA channel 7 transfer complete */ + DMA8_IRQn = 8u, /**< DMA channel 8 transfer complete */ + DMA9_IRQn = 9u, /**< DMA channel 9 transfer complete */ + DMA10_IRQn = 10u, /**< DMA channel 10 transfer complete */ + DMA11_IRQn = 11u, /**< DMA channel 11 transfer complete */ + DMA12_IRQn = 12u, /**< DMA channel 12 transfer complete */ + DMA13_IRQn = 13u, /**< DMA channel 13 transfer complete */ + DMA14_IRQn = 14u, /**< DMA channel 14 transfer complete */ + DMA15_IRQn = 15u, /**< DMA channel 15 transfer complete */ + DMA_Error_IRQn = 16u, /**< DMA error interrupt channels 0-15 */ + MCM_IRQn = 17u, /**< FPU sources */ + FTFC_IRQn = 18u, /**< FTFC Command complete */ + Read_Collision_IRQn = 19u, /**< FTFC Read collision */ + LVD_LVW_IRQn = 20u, /**< PMC Low voltage detect interrupt */ + FTFC_Fault_IRQn = 21u, /**< FTFC Double bit fault detect */ + WDOG_EWM_IRQn = 22u, /**< Single interrupt vector for WDOG and EWM */ + RCM_IRQn = 23u, /**< RCM Asynchronous Interrupt */ + LPI2C0_Master_IRQn = 24u, /**< LPI2C0 Master Interrupt */ + LPI2C0_Slave_IRQn = 25u, /**< LPI2C0 Slave Interrupt */ + LPSPI0_IRQn = 26u, /**< LPSPI0 Interrupt */ + LPSPI1_IRQn = 27u, /**< LPSPI1 Interrupt */ + LPSPI2_IRQn = 28u, /**< LPSPI2 Interrupt */ + LPUART0_RxTx_IRQn = 31u, /**< LPUART0 Transmit / Receive Interrupt */ + LPUART1_RxTx_IRQn = 33u, /**< LPUART1 Transmit / Receive Interrupt */ + LPUART2_RxTx_IRQn = 35u, /**< LPUART2 Transmit / Receive Interrupt */ + ADC0_IRQn = 39u, /**< ADC0 interrupt request. */ + ADC1_IRQn = 40u, /**< ADC1 interrupt request. */ + CMP0_IRQn = 41u, /**< CMP0 interrupt request */ + ERM_single_fault_IRQn = 44u, /**< ERM single bit error correction */ + ERM_double_fault_IRQn = 45u, /**< ERM double bit error non-correctable */ + RTC_IRQn = 46u, /**< RTC alarm interrupt */ + RTC_Seconds_IRQn = 47u, /**< RTC seconds interrupt */ + LPIT0_Ch0_IRQn = 48u, /**< LPIT0 channel 0 overflow interrupt */ + LPIT0_Ch1_IRQn = 49u, /**< LPIT0 channel 1 overflow interrupt */ + LPIT0_Ch2_IRQn = 50u, /**< LPIT0 channel 2 overflow interrupt */ + LPIT0_Ch3_IRQn = 51u, /**< LPIT0 channel 3 overflow interrupt */ + PDB0_IRQn = 52u, /**< PDB0 interrupt */ + SCG_IRQn = 57u, /**< SCG bus interrupt request */ + LPTMR0_IRQn = 58u, /**< LPTIMER interrupt request */ + PORTA_IRQn = 59u, /**< Port A pin detect interrupt */ + PORTB_IRQn = 60u, /**< Port B pin detect interrupt */ + PORTC_IRQn = 61u, /**< Port C pin detect interrupt */ + PORTD_IRQn = 62u, /**< Port D pin detect interrupt */ + PORTE_IRQn = 63u, /**< Port E pin detect interrupt */ + SWI_IRQn = 64u, /**< Software interrupt */ + PDB1_IRQn = 68u, /**< PDB1 interrupt */ + FLEXIO_IRQn = 69u, /**< FlexIO Interrupt */ + CAN0_ORed_IRQn = 78u, /**< CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */ + CAN0_Error_IRQn = 79u, /**< CAN0 Interrupt indicating that errors were detected on the CAN bus */ + CAN0_Wake_Up_IRQn = 80u, /**< CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */ + CAN0_ORed_0_15_MB_IRQn = 81u, /**< CAN0 OR'ed Message buffer (0-15) */ + CAN0_ORed_16_31_MB_IRQn = 82u, /**< CAN0 OR'ed Message buffer (16-31) */ + CAN1_ORed_IRQn = 85u, /**< CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */ + CAN1_Error_IRQn = 86u, /**< CAN1 Interrupt indicating that errors were detected on the CAN bus */ + CAN1_ORed_0_15_MB_IRQn = 88u, /**< CAN1 OR'ed Interrupt for Message buffer (0-15) */ + CAN2_ORed_IRQn = 92u, /**< CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */ + CAN2_Error_IRQn = 93u, /**< CAN2 Interrupt indicating that errors were detected on the CAN bus */ + CAN2_ORed_0_15_MB_IRQn = 95u, /**< CAN2 OR'ed Message buffer (0-15) */ + FTM0_Ch0_Ch1_IRQn = 99u, /**< FTM0 Channel 0 and 1 interrupt */ + FTM0_Ch2_Ch3_IRQn = 100u, /**< FTM0 Channel 2 and 3 interrupt */ + FTM0_Ch4_Ch5_IRQn = 101u, /**< FTM0 Channel 4 and 5 interrupt */ + FTM0_Ch6_Ch7_IRQn = 102u, /**< FTM0 Channel 6 and 7 interrupt */ + FTM0_Fault_IRQn = 103u, /**< FTM0 Fault interrupt */ + FTM0_Ovf_Reload_IRQn = 104u, /**< FTM0 Counter overflow and Reload interrupt */ + FTM1_Ch0_Ch1_IRQn = 105u, /**< FTM1 Channel 0 and 1 interrupt */ + FTM1_Ch2_Ch3_IRQn = 106u, /**< FTM1 Channel 2 and 3 interrupt */ + FTM1_Ch4_Ch5_IRQn = 107u, /**< FTM1 Channel 4 and 5 interrupt */ + FTM1_Ch6_Ch7_IRQn = 108u, /**< FTM1 Channel 6 and 7 interrupt */ + FTM1_Fault_IRQn = 109u, /**< FTM1 Fault interrupt */ + FTM1_Ovf_Reload_IRQn = 110u, /**< FTM1 Counter overflow and Reload interrupt */ + FTM2_Ch0_Ch1_IRQn = 111u, /**< FTM2 Channel 0 and 1 interrupt */ + FTM2_Ch2_Ch3_IRQn = 112u, /**< FTM2 Channel 2 and 3 interrupt */ + FTM2_Ch4_Ch5_IRQn = 113u, /**< FTM2 Channel 4 and 5 interrupt */ + FTM2_Ch6_Ch7_IRQn = 114u, /**< FTM2 Channel 6 and 7 interrupt */ + FTM2_Fault_IRQn = 115u, /**< FTM2 Fault interrupt */ + FTM2_Ovf_Reload_IRQn = 116u, /**< FTM2 Counter overflow and Reload interrupt */ + FTM3_Ch0_Ch1_IRQn = 117u, /**< FTM3 Channel 0 and 1 interrupt */ + FTM3_Ch2_Ch3_IRQn = 118u, /**< FTM3 Channel 2 and 3 interrupt */ + FTM3_Ch4_Ch5_IRQn = 119u, /**< FTM3 Channel 4 and 5 interrupt */ + FTM3_Ch6_Ch7_IRQn = 120u, /**< FTM3 Channel 6 and 7 interrupt */ + FTM3_Fault_IRQn = 121u, /**< FTM3 Fault interrupt */ + FTM3_Ovf_Reload_IRQn = 122u /**< FTM3 Counter overflow and Reload interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers_S32K144 */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer for S32K144 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer_S32K144 Device Peripheral Access Layer for S32K144 + * @{ + */ + +/* @brief This module covers memory mapped registers available on SoC */ + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + + +/** ADC - Size of Registers Arrays */ +#define ADC_SC1_COUNT 16u +#define ADC_R_COUNT 16u +#define ADC_CV_COUNT 2u + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ + __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ + __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ + __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ + __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ + __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ + __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ + __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ + __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ + __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ + __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ + __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ + __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ + __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ + __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ + __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ + __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ + __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ + __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ +} ADC_Type, *ADC_MemMapPtr; + + /** Number of instances of the ADC module. */ +#define ADC_INSTANCE_COUNT (2u) + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x40027000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } + /** Number of interrupt vector arrays for the ADC module. */ +#define ADC_IRQS_ARR_COUNT (1u) + /** Number of interrupt channels for the ADC module. */ +#define ADC_IRQS_CH_COUNT (1u) +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0u +#define ADC_SC1_ADCH_WIDTH 5u +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<