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Refs #287. Added the Dave4/GCC demo programs for the XMC4700 Relax Kit. 

git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@226 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg 2017-05-03 13:25:42 +00:00
parent 3281f3c13f
commit e3192b1421
217 changed files with 224011 additions and 0 deletions
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210
Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.cproject Normal file
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61
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14
Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/.settings/com.dave.mbs.xc800.prefs Normal file
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DEVICE_DESC=Package\= LQFP144 \nROM\= 2 MB Flash \nRAM\= 352 KB RAM \nInOut\= 91 digital I/O \nADC\= 32 ADC Channels, 12-bit, Delta Sigma Demodulator \nDAC\= 2 DAC Channels, 12 bit \nTimed_InOut\= 26 Timer, 48 CAPCOM channels, 2 POSIF \nSerial\= 6 USIC channels, ETH, USB, CAN \nDMA\= 12 DMA channels, ETH DMA, USB DMA \nTouch\= Touch and LED matrix control \nEBU\= MUX, DEMUX, Burst, SDRAM \n
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9
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.1
* @date 30. January 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* ARM Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* ARM Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#include <cmsis_iar.h>
#ifndef __NO_RETURN
#define __NO_RETURN __noreturn
#endif
#ifndef __USED
#define __USED __root
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
__packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
/*
* TI ARM Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/*********************************************************************************************************************
* @file system_XMC4700.h
* @brief Device specific initialization for the XMC4700-Series according to CMSIS
* @version V1.0
* @date 22 May 2015
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2015-2016, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
**************************** Change history *********************************
* V1.0, 22 May 2015, JFT, Initial version
*****************************************************************************
* @endcond
*/
#ifndef SYSTEM_XMC4700_H
#define SYSTEM_XMC4700_H
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include <stdint.h>
/*******************************************************************************
* MACROS
*******************************************************************************/
#define OFI_FREQUENCY (24000000UL) /**< 24MHz Backup Clock (fOFI) frequency. */
#define OSI_FREQUENCY (32768UL) /**< 32KHz Internal Slow Clock source (fOSI) frequency. */
/*******************************************************************************
* GLOBAL VARIABLES
*******************************************************************************/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint8_t g_chipid[16];
/*******************************************************************************
* API PROTOTYPES
*******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Initialize the system
*
*/
void SystemInit(void);
/**
* @brief Initialize CPU settings
*
*/
void SystemCoreSetup(void);
/**
* @brief Initialize clock
*
*/
void SystemCoreClockSetup(void);
/**
* @brief Update SystemCoreClock variable
*
*/
void SystemCoreClockUpdate(void);
/**
* @brief Returns frequency of the high performace oscillator
* User needs to overload this function to return the correct oscillator frequency
*/
uint32_t OSCHP_GetFrequency(void);
#ifdef __cplusplus
}
#endif
#endif

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/*********************************************************************************************************************
* @file syscalls.c
* @brief Newlib stubs
* @version V1.6
* @date 20 Apr 2017
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* *************************** Change history ********************************
* V0.1 : Initial version
* V0.2 : Label updates
* V1.0 : Made _sbrk device agnostic
* V1.1 : C++ support
* V1.2 : Restored compatibility with old project files
* V1.3 Jan 2014, PKB : Encapsulating everything in this file for use only with GCC
* V1.4 11 Dec 2015, JFT : Fix heap overflow
* V1.5 09 Mar 2016, JFT : Add dso_handle to support destructors call at exit
* V1.6 20 Apr 2017, JFT : Foward declaration of __sbrk to fix link time optimization (-flto) compilation errors
* @endcond
*/
/*
* This file contains stubs for standard C library functionality that must
* typically be provided for the underlying platform.
*
*/
#if defined ( __GNUC__ )
#include <stdint.h>
#include <errno.h>
#include <sys/types.h>
/* Forward prototypes. */
caddr_t _sbrk(int nbytes) __attribute__((externally_visible));
void _init(void) __attribute__((externally_visible));
/* c++ destructor dynamic shared object needed if -fuse-cxa-atexit is used*/
void *__dso_handle __attribute__ ((weak));
// defined in linker script
extern caddr_t Heap_Bank1_Start;
extern caddr_t Heap_Bank1_End;
caddr_t _sbrk(int nbytes)
{
static caddr_t heap_ptr = NULL;
caddr_t base;
if (heap_ptr == NULL) {
heap_ptr = (caddr_t)&Heap_Bank1_Start;
}
base = heap_ptr;
/* heap word alignment */
nbytes = (nbytes + 3) & ~0x3U;
if ((caddr_t)&Heap_Bank1_End > (heap_ptr + nbytes))
{
heap_ptr += nbytes;
return (base);
}
else
{
/* Heap overflow */
errno = ENOMEM;
return ((caddr_t)-1);
}
}
/* Init */
void _init(void)
{}
#endif /* __GNUC__ */

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/**
* @file xmc4_flash.h
* @date 2016-03-22
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2014-12-10:
* - Initial <br>
* 2015-02-20:
* - Updated for Documentation related changes<br>
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
* 2015-08-17:
* - Added the below API's to the public interface.
* 1. XMC_FLASH_Reset
* 2. XMC_FLASH_ErasePhysicalSector
* 3. XMC_FLASH_EraseUCB
* 4. XMC_FLASH_ResumeProtection
* 5. XMC_FLASH_RepairPhysicalSector
* - Added support for XMC4800/4700 devices
* 2015-12-07:
* - Fix XMC_FLASH_READ_ACCESS_TIME for XMC43, 47 and 48 devices
* 2016-03-18:
* - Fix implementation of XMC_PREFETCH_EnableInstructionBuffer and XMC_PREFETCH_DisableInstructionBuffer
* 2016-03-22:
* - Fix implementation of XMC_PREFETCH_InvalidateInstructionBuffer
* @endcond
*
*/
#ifndef XMC4_FLASH_H
#define XMC4_FLASH_H
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_common.h"
#if UC_FAMILY == XMC4
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup FLASH
* @{
*/
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_FLASH_UNCACHED_BASE (0x0C000000U) /**< Non cached flash starting address of for
XMC4 family of microcontrollers */
#define XMC_FLASH_WORDS_PER_PAGE (64UL) /**< Number of words in a page (256 bytes / 4 bytes = 64 words)*/
#define XMC_FLASH_BYTES_PER_PAGE (256UL) /**< Number of bytes in a page*/
#define XMC_FLASH_UCB0 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0000UL) /**< Starting address of User
Configurable Block 0*/
#define XMC_FLASH_UCB1 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0400UL) /**< Starting address of User
Configurable Block 1*/
#define XMC_FLASH_UCB2 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0800UL) /**< Starting address of User
Configurable Block 2*/
#define XMC_FLASH_BYTES_PER_UCB (1024UL) /**< Number of bytes in a user configurable block*/
/**< Note : Total number of Sectors depends on the flash size of the controller. So while using these macros for flash
* operations ensure that sector is available, other may lead to flash error.
*/
#define XMC_FLASH_SECTOR_0 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x00000UL) /**<Starting address of sector0 */
#define XMC_FLASH_SECTOR_1 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x04000UL) /**<Starting address of sector1 */
#define XMC_FLASH_SECTOR_2 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x08000UL) /**<Starting address of sector2 */
#define XMC_FLASH_SECTOR_3 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x0C000UL) /**<Starting address of sector3 */
#define XMC_FLASH_SECTOR_4 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x10000UL) /**<Starting address of sector4 */
#define XMC_FLASH_SECTOR_5 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x14000UL) /**<Starting address of sector5 */
#define XMC_FLASH_SECTOR_6 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x18000UL) /**<Starting address of sector6 */
#define XMC_FLASH_SECTOR_7 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x1C000UL) /**<Starting address of sector7 */
#define XMC_FLASH_SECTOR_8 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x20000UL) /**<Starting address of sector8 */
#define XMC_FLASH_SECTOR_9 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x40000UL) /**<Starting address of sector9 */
#define XMC_FLASH_SECTOR_10 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x80000UL) /**<Starting address of sector10*/
#define XMC_FLASH_SECTOR_11 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xC0000UL) /**<Starting address of sector11*/
#define XMC_FLASH_SECTOR_12 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x100000UL) /**<Starting address of sector12*/
#define XMC_FLASH_SECTOR_13 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x140000UL) /**<Starting address of sector13*/
#define XMC_FLASH_SECTOR_14 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x180000UL) /**<Starting address of sector14*/
#define XMC_FLASH_SECTOR_15 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x1C0000UL) /**<Starting address of sector15*/
#define XMC_FLASH_PHY_SECTOR_0 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x00000UL) /**<Starting address of non cached
physical sector0 */
#define XMC_FLASH_PHY_SECTOR_4 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x10000UL) /**<Starting address of non cached
physical sector4 */
#define XMC_FLASH_PHY_SECTOR_8 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x20000UL) /**<Starting address of non cached
physical sector8 */
#define XMC_FLASH_PHY_SECTOR_9 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x40000UL) /**<Starting address of non cached
physical sector9 */
#define XMC_FLASH_PHY_SECTOR_10 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x80000UL) /**<Starting address of non cached
physical sector10 */
#define XMC_FLASH_PHY_SECTOR_11 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xC0000UL) /**<Starting address of non cached
physical sector11 */
#define XMC_FLASH_PHY_SECTOR_12 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x100000UL) /**<Starting address of non cached
physical sector12 */
#define XMC_FLASH_PHY_SECTOR_13 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x140000UL) /**<Starting address of non cached
physical sector13 */
#define XMC_FLASH_PHY_SECTOR_14 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x180000UL) /**<Starting address of non cached
physical sector14 */
#define XMC_FLASH_PHY_SECTOR_15 (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x1C0000UL) /**<Starting address of non cached
physical sector15 */
#if UC_SERIES == XMC45 || UC_SERIES == XMC43 || UC_SERIES == XMC47 || UC_SERIES == XMC48
#define XMC_FLASH_READ_ACCESS_TIME (22E-9F) /* Flash read access time */
#else
#define XMC_FLASH_READ_ACCESS_TIME (20E-9F)
#endif
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/**
* Defines the return status of the API.
*/
typedef enum XMC_FLASH_STATUS
{
XMC_FLASH_STATUS_OK = 0U, /**< Operation completed successfully*/
XMC_FLASH_STATUS_BUSY = FLASH_FSR_PBUSY_Msk, /**< API cannot proceed since FLASH is busy*/
XMC_FLASH_STATUS_PROGRAMMING_STATE = FLASH_FSR_PROG_Msk, /**< Write page is in progress or finished */
XMC_FLASH_STATUS_ERASE_STATE = FLASH_FSR_ERASE_Msk, /**< Erase page is in progress or finished */
XMC_FLASH_STATUS_PAGE_MODE = FLASH_FSR_PFPAGE_Msk, /**< Flash is in page mode. Assembly buffer
of PFLASH is in use */
XMC_FLASH_STATUS_OPERATION_ERROR = FLASH_FSR_PFOPER_Msk, /**< Flash Operation aborted */
XMC_FLASH_STATUS_COMMAND_SEQUENCE_ERROR = FLASH_FSR_SQER_Msk, /**< Improper address or Invalid state machine
operation */
XMC_FLASH_STATUS_PROTECTION_ERROR = FLASH_FSR_PROER_Msk, /**< Flash operation addressing the locked
sector */
XMC_FLASH_STATUS_SINGLE_BIT_ERROR_AND_CORRECTION = FLASH_FSR_PFSBER_Msk, /**< Single bit error detected and
corrected */
XMC_FLASH_STATUS_DOUBLE_BIT_ERROR = FLASH_FSR_PFDBER_Msk, /**< Multiple bit error occurred */
XMC_FLASH_STATUS_PROTECTION_INSTALLED = FLASH_FSR_PROIN_Msk, /**< Confirmation of the read or/and write
protection is successful */
XMC_FLASH_STATUS_READ_PROTECTION_INSTALLED = FLASH_FSR_RPROIN_Msk, /**< Confirmation of read and global write
protection is successful for user-0 */
XMC_FLASH_STATUS_READ_PROTECTION_DISABLED_STATE = FLASH_FSR_RPRODIS_Msk, /**< Read or/and write protection is
temporarily disabled */
XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB0 = FLASH_FSR_WPROIN0_Msk, /**< Sector write protection is installed
for user-0 */
XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB1 = FLASH_FSR_WPROIN1_Msk, /**< Sector write protection is installed
for user-1 */
XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB2 = FLASH_FSR_WPROIN2_Msk, /**< Sector OTP protection is installed
for user-2 */
XMC_FLASH_STATUS_WRITE_PROTECTION_DISABLED_UCB0 = FLASH_FSR_WPRODIS0_Msk, /**< Sector write protection is disabled
for user-0 */
XMC_FLASH_STATUS_WRITE_PROTECTION_DISABLED_UCB1 = FLASH_FSR_WPRODIS1_Msk, /**< Sector write protection is disabled
for user-1 */
XMC_FLASH_STATUS_SLEEP_MODE = FLASH_FSR_SLM_Msk, /**< Indicates flash in sleep mode or not */
XMC_FLASH_STATUS_VERIFY_ERROR = (int32_t)FLASH_FSR_VER_Msk, /**< Write verification and Erase
verification error occurred */
} XMC_FLASH_STATUS_t;
/**
* Provides the options to select flash margin read settings of the for quality assurance.
*/
typedef enum XMC_FLASH_MARGIN
{
XMC_FLASH_MARGIN_DEFAULT = 0x0U << FLASH_MARP_MARGIN_Pos, /**< Default margin */
XMC_FLASH_MARGIN_TIGHT0 = 0x1U << FLASH_MARP_MARGIN_Pos, /**< Sub-optimal 0-bits are read as 1s */
XMC_FLASH_MARGIN_TIGHT1 = 0x4U << FLASH_MARP_MARGIN_Pos /**< Sub-optimal 1-bits are read as 0s */
} XMC_FLASH_MARGIN_t;
/**
* Provides the options to select flash operational events
*/
typedef enum XMC_FLASH_EVENT
{
XMC_FLASH_EVENT_VERIFY_AND_OPERATION_ERROR = 0x01U << FLASH_FCON_VOPERM_Pos, /**< Flash verify and operation error
event */
XMC_FLASH_EVENT_COMMAND_SEQUENCE_ERROR = 0x02U << FLASH_FCON_VOPERM_Pos, /**< Flash command sequence error event*/
XMC_FLASH_EVENT_PROTECTION_ERROR = 0x04U << FLASH_FCON_VOPERM_Pos, /**< Flash protection error event */
XMC_FLASH_EVENT_SINGLE_BIT_ERROR = 0x08U << FLASH_FCON_VOPERM_Pos, /**< Flash single bit error event */
XMC_FLASH_EVENT_DOUBLE_BIT_ERROR = 0x20U << FLASH_FCON_VOPERM_Pos, /**< Flash double bit error event*/
XMC_FLASH_EVENT_END_OF_BUSY = (int32_t)(0x80U << FLASH_FCON_VOPERM_Pos) /**< Flash end of busy event*/
} XMC_FLASH_EVENT_t;
/**
* Provides the options to select sectors for write protection and select global read protection.
* The members can be combined using 'OR' operator for multiple selection.<br>
*
*/
typedef enum XMC_FLASH_PROTECTION
{
XMC_FLASH_PROTECTION_WRITE_SECTOR_0 = 0x0001UL, /**< Sector 0 write protection */
XMC_FLASH_PROTECTION_WRITE_SECTOR_1 = 0x0002UL, /**< Sector 1 write protection */
XMC_FLASH_PROTECTION_WRITE_SECTOR_2 = 0x0004UL, /**< Sector 3 write protection */
XMC_FLASH_PROTECTION_WRITE_SECTOR_3 = 0x0008UL, /**< Sector 3 write protection */
XMC_FLASH_PROTECTION_WRITE_SECTOR_4 = 0x0010UL, /**< Sector 4 write protection */
XMC_FLASH_PROTECTION_WRITE_SECTOR_5 = 0x0020UL, /**< Sector 5 write protection */
XMC_FLASH_PROTECTION_WRITE_SECTOR_6 = 0x0040UL, /**< Sector 6 write protection */
XMC_FLASH_PROTECTION_WRITE_SECTOR_7 = 0x0080UL, /**< Sector 7 write protection */
XMC_FLASH_PROTECTION_WRITE_SECTOR_8 = 0x0100UL, /**< Sector 8 write protection */
XMC_FLASH_PROTECTION_WRITE_SECTOR_9 = 0x0200UL, /**< Sector 9 write protection */
XMC_FLASH_PROTECTION_WRITE_SECTORS_10_11 = 0x0400UL, /**< Sector 10 and 11 write protection */
XMC_FLASH_PROTECTION_WRITE_SECTORS_12_13 = 0x0800UL, /**< Sector 12 and 13 write protection */
XMC_FLASH_PROTECTION_WRITE_SECTORS_14_15 = 0x1000UL, /**< Sector 14 and 15 write protection */
XMC_FLASH_PROTECTION_READ_GLOBAL = 0x8000UL /**< Global read protection (Applicable for UserLevel0 alone)*/
} XMC_FLASH_PROTECTION_t;
/*********************************************************************************************************************
* API PROTOTYPES
********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Enables the wait state for error correction.process, It enables one additional wait state for ECC by setting WSECPF
* bit of FCON register.\n
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_DisableWaitStateForECC()\n\n\n
*
*/
__STATIC_INLINE void XMC_FLASH_EnableWaitStateForECC(void)
{
FLASH0->FCON |= FLASH_FCON_WSECPF_Msk;
}
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Disables the wait state for error correction.\n\n Removes additional wait state for ECC by resetting WSECPF bit of
* FCON register.\n
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_EnableWaitStateForECC()\n\n\n
*
*/
__STATIC_INLINE void XMC_FLASH_DisableWaitStateForECC(void)
{
FLASH0->FCON &= (uint32_t)~FLASH_FCON_WSECPF_Msk;
}
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Enables dynamic idle mode feature to save power.\n\n It switches off the PFLASH read path when no read access is
* pending. Hence power is saved marginally. This slightly reduces the flash read performance because static
* pre-fetching is disabled.It sets the FCON register IDLE bit to enable this feature.
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_DisableDynamicIdle()\n\n\n
*
*/
__STATIC_INLINE void XMC_FLASH_EnableDynamicIdle(void)
{
FLASH0->FCON |= FLASH_FCON_IDLE_Msk;
}
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Disables dynamic idle mode feature.\n\n It resets the FCON register IDLE bit to disable this feature. Hence normal
* flash read operation is selected.
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_EnableDynamicIdle()\n\n\n
*
*/
__STATIC_INLINE void XMC_FLASH_DisableDynamicIdle(void)
{
FLASH0->FCON &= (uint32_t)~FLASH_FCON_IDLE_Msk;
}
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Enables sleep mode of the PFLASH.\n\n Sleep mode is enabled by setting the bit FCON.SLEEP.
*
* \par<b>Note:</b><br>
* fCPU must be equal or above 1 MHz when wake-up request is triggered.
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_DisableSleepRequest()\n\n\n
*
*/
__STATIC_INLINE void XMC_FLASH_EnableSleepRequest(void)
{
FLASH0->FCON |= (uint32_t)FLASH_FCON_SLEEP_Msk;
}
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Wake-up the PFLASH from sleep.\n\n Wakes-up from sleep is done by clearing the bit FCON.SLEEP, if selected via this
* bit, or wake-up is initiated by releasing the external sleep signal from SCU.
*
* \par<b>Note:</b><br>
* fCPU must be equal or above 1 MHz when wake-up request is triggered.
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_EnableSleepRequest()\n\n\n
*
*/
__STATIC_INLINE void XMC_FLASH_DisableSleepRequest(void)
{
FLASH0->FCON &= (uint32_t)~FLASH_FCON_SLEEP_Msk;
}
/**
*
* @param margin PFLASH margin selection. Use type @ref XMC_FLASH_MARGIN_t.
*
* @return None
*
* \par<b>Description:</b><br>
* Sets the read margin levels for checking the healthiness of flash data.\n\n Configures the margin field of MARP
* MARP register with the specified \a margin level. It changes the margin levels for read operations to find
* problematic array bits.
*
* \par<b>Related APIs:</b><BR>
* None
*/
__STATIC_INLINE void XMC_FLASH_SetMargin(const XMC_FLASH_MARGIN_t margin)
{
FLASH0->MARP = (FLASH0->MARP & (uint32_t)~FLASH_MARP_MARGIN_Msk) | margin;
}
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Enables double bit error trap.\n\n. It enables by setting MARP register bit TRAPDIS.
*
* \par<b>Related APIs:</b><BR>
* None
*/
__STATIC_INLINE void XMC_FLASH_EnableDoubleBitErrorTrap(void)
{
FLASH0->MARP &= (uint32_t)~FLASH_MARP_TRAPDIS_Msk;
}
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Disables the trap generation for double bit error by clearing MARP register bit TRAPDIS.\n\n The double-bit error
* trap can be disabled for margin checks and also redirected to an error interrupt. Any time during the execution the
* double bit error trap can be enabled back by calling XMC_FLASH_EnableDoubleBitErrorTrap() API.
*
* \par<b>Related APIs:</b><BR>
* None
*/
__STATIC_INLINE void XMC_FLASH_DisableDoubleBitErrorTrap(void)
{
FLASH0->MARP |= FLASH_MARP_TRAPDIS_Msk;
}
/**
*
* @param num_wait_states number of wait states for initial read access<BR> Range: [0 to 15]
*
* @return None
*
* \par<b>Description:</b><br>
* Configures the number of wait states for initial flash read access.\n\n Depending on the configured \a
* num_wait_states value into FCON resister \a WSPFLASH field, the read performance gets optimized . The wait cycles
* for the flash read access must be configured based on the CPU frequency (fCPU), in relation to the flash access
* time (\a ta) defined. The access time formula (\a WSPFLASH x (\a \a \a 1 / fCPU) \a >= \a ta) applies only for
* the values \a \a \a num_wait_states >0.
*
* \par<b>Related APIs:</b><BR>
* None
*/
__STATIC_INLINE void XMC_FLASH_SetWaitStates(uint32_t num_wait_states)
{
FLASH0->FCON = (FLASH0->FCON & (uint32_t)~FLASH_FCON_WSPFLASH_Msk) |
(num_wait_states << FLASH_FCON_WSPFLASH_Pos);
}
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Configures the cacheable accesses to use the instruction buffer by resetting the register bit PREF_PCON.IBYP.
*
* \par<b>Related APIs:</b><BR>
* None
*/
__STATIC_INLINE void XMC_PREFETCH_EnableInstructionBuffer(void)
{
PREF->PCON &= (uint32_t)~PREF_PCON_IBYP_Msk;
}
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Bypasses the instruction buffer for cacheable accesses, by setting the register bit PREF_PCON.IBYP.
*
* \par<b>Related APIs:</b><BR>
* None
*/
__STATIC_INLINE void XMC_PREFETCH_DisableInstructionBuffer(void)
{
PREF->PCON |= PREF_PCON_IBYP_Msk;
}
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Invalidates the instruction buffer by setting PREF_PCON register bit IINV.\n\n After system reset, the instruction
* buffer is automatically invalidated.
*
* \par<b>Note:</b><br>
* The complete invalidation operation is performed in a single cycle.
*
* \par<b>Related APIs:</b><BR>
* None
*/
__STATIC_INLINE void XMC_PREFETCH_InvalidateInstructionBuffer(void)
{
PREF->PCON |= PREF_PCON_IINV_Msk;
__DSB();
__ISB();
PREF->PCON &= ~PREF_PCON_IINV_Msk;
__DSB();
__ISB();
}
/**
*
* @param user ID number of the user configuration block (UCB).<BR> Range: [0 to 2]
*
* @param protection_mask ORed values of @ref XMC_FLASH_PROTECTION_t enum type, for which sectors the protection
* has to be enabled.
* @param password_0 First password for protection.<BR> Range: [0 to 4294967295]
* @param password_1 Second password for protection.<BR> Range: [0 to 4294967295]
*
* @return None
*
* \par<b>Description:</b><br>
* Installs the global read and sector write protection.\n\n The installation starts by issuing the page mode entry
* command followed by the load page command. The load page command mode loads the required sectors intended for
* protection specified in \a protection_mask. It also loads the specified passwords \a password0 and \a password1
* respectively. Finally, it issues the write page command for the specified \a user configuration block. Calling
* XMC_FLASH_ConfirmProtection() after this API completes the protection process by freezing the sectors forever.
*
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_ConfirmProtection()<BR>
* XMC_FLASH_VerifyReadProtection()<BR>
*/
void XMC_FLASH_InstallProtection(uint8_t user,
uint32_t protection_mask,
uint32_t password_0,
uint32_t password_1);
/**
*
* @param user ID number of the user configuration block (UCB).<BR> Range: [0 to 2]
*
* @return None
*
* \par<b>Description:</b><br>
* Confirms the protection, so that sectors specified under \a user configurable block are locked forever.\n\n The
* protection shall be installed by calling XMC_FLASH_InstallProtection() before calling this API.
* The confirmation starts by issuing the page mode entry command followed by the load page command. The load page
* command issues the confirmation protection command for the sectors on which the protection installation was done.
* It also loads the specified passwords \a password0 and \a password1 respectively. Finally, it issues the confirm
* protection command for the specified \a user configuration block so that the sectors will be protected forever.
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_InstallProtection()<BR>
*
*/
void XMC_FLASH_ConfirmProtection(uint8_t user);
/**
*
* @param password_0 First password used for protection.<BR> Range: [0 to 4294967295]
* @param password_1 Second password used for protection.<BR> Range: [0 to 4294967295]
*
* @return true if read protection installed properly else returns \a false.
*
* \par<b>Description:</b><br>
* Verifies sector read protection is properly installed or not.\n\n Before entering into verify read protection
* process, it clears the error status bits inside status register. It temporarily disables the protection with
* passwords \a password0 and \a password1 respectively. It reads the FSR register and verifies the protection state.
* Resumption of read protection after disablement is achieved by XMC_FLASH_ResumeProtection or until next reset.
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_InstallProtection()<BR>
* XMC_FLASH_VerifyWriteProtection()<BR>
* XMC_FLASH_ResumeProtection()<BR>
*/
bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1);
/**
*
* @param user ID number of the user configuration block (UCB).<BR> Range: [0 to 2]
*
* @param protection_mask ORed values of @ref XMC_FLASH_PROTECTION_t enum type, for which sectors the protection
* has to be verified.
* @param password_0 First password used for protection.<BR> Range: [0 to 4294967295]
* @param password_1 Second password used for protection.<BR> Range: [0 to 4294967295]
*
* @return true if write protection installed properly else returns \a false.
*
* \par<b>Description:</b><br>
* Verifies sector read protection is properly installed or not.\n\n Before entering into verify read protection
* process, it clears the error status bits inside status register. It temporarily disables the protection with
* passwords \a password0 and \a password1 respectively for the intended sectors specified in \a protection_mask.
* It reads the FSR register and verifies the write protection state.
* Resumption of write protection after disablement is achieved by XMC_FLASH_ResumeProtection or until next reset.
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_InstallProtection()<BR>
* XMC_FLASH_VerifyReadProtection()<BR>
* XMC_FLASH_ResumeProtection()<BR>
*/
bool XMC_FLASH_VerifyWriteProtection(uint32_t user,
uint32_t protection_mask,
uint32_t password_0,
uint32_t password_1);
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Resumes flash protection as it was configured before.\n\n
* It clears all the disable proection status flags FSR.WPRODISx and FSR.RPRODIS. But FSR.WPRODISx is not
* cleared when corresponding UCBx is not in the “confirmed” state.
*
* \par<b>Related APIs:</b><BR>
* None
*/
void XMC_FLASH_ResumeProtection(void);
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Repairs the physical sector "PS4".\n\n
* For selected devices, Erase Physical Sector can also be used for Sector Soft Repair, depending on the configuration
* of PROCON1.PSR. This command sequence is required to run an EEPROM emulation algorithm that cycles the logical
* sectors S4..S7 of PS4. This command sequence repairs the corrupted logical sectors inside the physical sector due to
* interrupted erase operation.
*
* \par<b>Related APIs:</b><BR>
* None
*/
void XMC_FLASH_RepairPhysicalSector(void);
/**
*
* @param sector_start_address Pointer to the starting address of physical sector. Use XMC_FLASH_SECTOR_x MACRO defined
* in xmc4_flash.h file.
*
* @return None
*
* \par<b>Description:</b><br>
* Erases the physical sector "PSA".\n\n If "PSA" does not point to base address of a correct sector or an unavailable
* sector, it returns SQER.
*
*
* \par<b>Related APIs:</b><BR>
* None
*/
void XMC_FLASH_ErasePhysicalSector(uint32_t *sector_start_address);
/**
*
* @param ucb_sector_start_address Pointer to the starting address of physical sector. Use XMC_FLASH_UCBx MACRO
* defined in xmc4_flash.h file.
*
* @return None
*
* \par<b>Description:</b><br>
* The addressed user configuration block “UCB” is erased.\n\n
* Erases UCB whose startting address specified in the input parameter \a ucb_sector_start_address. When the UCB has
* an active write protection or the Flash module has an active global read protection the execution fails and
* PROER is set. The command fails with SQER when \a ucb_sector_start_address is not the start address of a valid UCB.
* Call \ref XMC_FLASH_GetStatus API after this API to verify the erase was proper ot not.
*
* \par<b>Related APIs:</b><BR>
* None
*/
void XMC_FLASH_EraseUCB(uint32_t *ucb_sector_start_address);
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Resets the command interpreter to its initial state.\n\n
* Reset to Read can cancel every command sequence before its last command cycle has been received. All error flags
* gets cleared by calling this API.
* \par<b>Note:</b><br>
* todo
*
* \par<b>Related APIs:</b><BR>
* None
*/
void XMC_FLASH_Reset(void);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif
#endif

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/**
* @file xmc4_gpio.h
* @date 2015-10-09
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft<br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* 2015-10-09:
* - Added PORT MACRO checks and definitions for XMC4800/4700 devices
* @endcond
*
*/
#ifndef XMC4_GPIO_H
#define XMC4_GPIO_H
/**********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_common.h"
#if UC_FAMILY == XMC4
#include "xmc4_gpio_map.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup GPIO
* @{
*/
/**********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#if defined(PORT0)
#define XMC_GPIO_PORT0 ((XMC_GPIO_PORT_t *) PORT0_BASE)
#define XMC_GPIO_CHECK_PORT0(port) (port == XMC_GPIO_PORT0)
#else
#define XMC_GPIO_CHECK_PORT0(port) 0
#endif
#if defined(PORT1)
#define XMC_GPIO_PORT1 ((XMC_GPIO_PORT_t *) PORT1_BASE)
#define XMC_GPIO_CHECK_PORT1(port) (port == XMC_GPIO_PORT1)
#else
#define XMC_GPIO_CHECK_PORT1(port) 0
#endif
#if defined(PORT2)
#define XMC_GPIO_PORT2 ((XMC_GPIO_PORT_t *) PORT2_BASE)
#define XMC_GPIO_CHECK_PORT2(port) (port == XMC_GPIO_PORT2)
#else
#define XMC_GPIO_CHECK_PORT2(port) 0
#endif
#if defined(PORT3)
#define XMC_GPIO_PORT3 ((XMC_GPIO_PORT_t *) PORT3_BASE)
#define XMC_GPIO_CHECK_PORT3(port) (port == XMC_GPIO_PORT3)
#else
#define XMC_GPIO_CHECK_PORT3(port) 0
#endif
#if defined(PORT4)
#define XMC_GPIO_PORT4 ((XMC_GPIO_PORT_t *) PORT4_BASE)
#define XMC_GPIO_CHECK_PORT4(port) (port == XMC_GPIO_PORT4)
#else
#define XMC_GPIO_CHECK_PORT4(port) 0
#endif
#if defined(PORT5)
#define XMC_GPIO_PORT5 ((XMC_GPIO_PORT_t *) PORT5_BASE)
#define XMC_GPIO_CHECK_PORT5(port) (port == XMC_GPIO_PORT5)
#else
#define XMC_GPIO_CHECK_PORT5(port) 0
#endif
#if defined(PORT6)
#define XMC_GPIO_PORT6 ((XMC_GPIO_PORT_t *) PORT6_BASE)
#define XMC_GPIO_CHECK_PORT6(port) (port == XMC_GPIO_PORT6)
#else
#define XMC_GPIO_CHECK_PORT6(port) 0
#endif
#if defined(PORT7)
#define XMC_GPIO_PORT7 ((XMC_GPIO_PORT_t *) PORT7_BASE)
#define XMC_GPIO_CHECK_PORT7(port) (port == XMC_GPIO_PORT7)
#else
#define XMC_GPIO_CHECK_PORT7(port) 0
#endif
#if defined(PORT8)
#define XMC_GPIO_PORT8 ((XMC_GPIO_PORT_t *) PORT8_BASE)
#define XMC_GPIO_CHECK_PORT8(port) (port == XMC_GPIO_PORT8)
#else
#define XMC_GPIO_CHECK_PORT8(port) 0
#endif
#if defined(PORT9)
#define XMC_GPIO_PORT9 ((XMC_GPIO_PORT_t *) PORT9_BASE)
#define XMC_GPIO_CHECK_PORT9(port) (port == XMC_GPIO_PORT9)
#else
#define XMC_GPIO_CHECK_PORT9(port) 0
#endif
#if defined(PORT14)
#define XMC_GPIO_PORT14 ((XMC_GPIO_PORT_t *) PORT14_BASE)
#define XMC_GPIO_CHECK_PORT14(port) (port == XMC_GPIO_PORT14)
#else
#define XMC_GPIO_CHECK_PORT14(port) 0
#endif
#if defined(PORT15)
#define XMC_GPIO_PORT15 ((XMC_GPIO_PORT_t *) PORT15_BASE)
#define XMC_GPIO_CHECK_PORT15(port) (port == XMC_GPIO_PORT15)
#else
#define XMC_GPIO_CHECK_PORT15(port) 0
#endif
#define XMC_GPIO_CHECK_PORT(port) (XMC_GPIO_CHECK_PORT0(port) || \
XMC_GPIO_CHECK_PORT1(port) || \
XMC_GPIO_CHECK_PORT2(port) || \
XMC_GPIO_CHECK_PORT3(port) || \
XMC_GPIO_CHECK_PORT4(port) || \
XMC_GPIO_CHECK_PORT5(port) || \
XMC_GPIO_CHECK_PORT6(port) || \
XMC_GPIO_CHECK_PORT7(port) || \
XMC_GPIO_CHECK_PORT8(port) || \
XMC_GPIO_CHECK_PORT9(port) || \
XMC_GPIO_CHECK_PORT14(port) || \
XMC_GPIO_CHECK_PORT15(port))
#define XMC_GPIO_CHECK_OUTPUT_PORT(port) (XMC_GPIO_CHECK_PORT0(port) || \
XMC_GPIO_CHECK_PORT1(port) || \
XMC_GPIO_CHECK_PORT2(port) || \
XMC_GPIO_CHECK_PORT3(port) || \
XMC_GPIO_CHECK_PORT4(port) || \
XMC_GPIO_CHECK_PORT5(port) || \
XMC_GPIO_CHECK_PORT6(port) || \
XMC_GPIO_CHECK_PORT7(port) || \
XMC_GPIO_CHECK_PORT8(port) || \
XMC_GPIO_CHECK_PORT9(port))
#define XMC_GPIO_CHECK_ANALOG_PORT(port) (XMC_GPIO_CHECK_PORT14(port) || \
XMC_GPIO_CHECK_PORT15(port))
#define XMC_GPIO_CHECK_OUTPUT_STRENGTH(strength) ((strength == XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE) ||\
(strength == XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE) ||\
(strength == XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE) ||\
(strength == XMC_GPIO_OUTPUT_STRENGTH_STRONG_SLOW_EDGE) ||\
(strength == XMC_GPIO_OUTPUT_STRENGTH_MEDIUM) ||\
(strength == XMC_GPIO_OUTPUT_STRENGTH_WEAK))
/**********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* Defines the direction and characteristics of a pin. Use type \a XMC_GPIO_MODE_t for this enum. For the operation
* with alternate functions, the port pins are directly connected to input or output functions of the on-chip periphery.
*/
typedef enum XMC_GPIO_MODE
{
XMC_GPIO_MODE_INPUT_TRISTATE = 0x0UL << PORT0_IOCR0_PC0_Pos, /**< No internal pull device active */
XMC_GPIO_MODE_INPUT_PULL_DOWN = 0x1UL << PORT0_IOCR0_PC0_Pos, /**< Internal pull-down device active */
XMC_GPIO_MODE_INPUT_PULL_UP = 0x2UL << PORT0_IOCR0_PC0_Pos, /**< Internal pull-up device active */
XMC_GPIO_MODE_INPUT_SAMPLING = 0x3UL << PORT0_IOCR0_PC0_Pos, /**< No internal pull device active;Pn_OUTx continuously samples the input value */
XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE = 0x4UL << PORT0_IOCR0_PC0_Pos, /**< Inverted no internal pull device active */
XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN = 0x5UL << PORT0_IOCR0_PC0_Pos, /**< Inverted internal pull-down device active */
XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP = 0x6UL << PORT0_IOCR0_PC0_Pos, /**< Inverted internal pull-up device active */
XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING = 0x7UL << PORT0_IOCR0_PC0_Pos, /**< Inverted no internal pull device active; Pn_OUTx continuously samples the input value */
XMC_GPIO_MODE_OUTPUT_PUSH_PULL = 0x80UL, /**< Push-pull general-purpose output */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN = 0xc0UL, /**< Open-drain general-purpose output */
XMC_GPIO_MODE_OUTPUT_ALT1 = 0x1UL << PORT0_IOCR0_PC0_Pos,
XMC_GPIO_MODE_OUTPUT_ALT2 = 0x2UL << PORT0_IOCR0_PC0_Pos,
XMC_GPIO_MODE_OUTPUT_ALT3 = 0x3UL << PORT0_IOCR0_PC0_Pos,
XMC_GPIO_MODE_OUTPUT_ALT4 = 0x4UL << PORT0_IOCR0_PC0_Pos,
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT1, /**< Push-pull alternate output function 1 */
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT2, /**< Push-pull alternate output function 2 */
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT3, /**< Push-pull alternate output function 3 */
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4 = XMC_GPIO_MODE_OUTPUT_PUSH_PULL | XMC_GPIO_MODE_OUTPUT_ALT4, /**< Push-pull alternate output function 4 */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT1, /**< Open drain alternate output function 1 */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT2, /**< Open drain alternate output function 2 */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT3, /**< Open drain alternate output function 3 */
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4 = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN | XMC_GPIO_MODE_OUTPUT_ALT4, /**< Open drain alternate output function 4 */
} XMC_GPIO_MODE_t;
/**
* Defines output strength and slew rate of a pin. Use type \a XMC_GPIO_OUTPUT_STRENGTH_t for this enum.
*
*/
typedef enum XMC_GPIO_OUTPUT_STRENGTH
{
XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE = 0x0U, /**< Defines pad driver mode, for high speed 3.3V LVTTL outputs */
XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE = 0x1U, /**< Defines pad driver mode, for high speed 3.3V LVTTL outputs */
XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE = 0x2U, /**< Defines pad driver mode, medium speed 3.3V LVTTL outputs */
XMC_GPIO_OUTPUT_STRENGTH_STRONG_SLOW_EDGE = 0x3U, /**< Defines pad driver mode, medium speed 3.3V LVTTL outputs */
XMC_GPIO_OUTPUT_STRENGTH_MEDIUM = 0x4U, /**< Defines pad driver mode, for low speed 3.3V LVTTL outputs */
XMC_GPIO_OUTPUT_STRENGTH_WEAK = 0x7U /**< Defines pad driver mode, low speed 3.3V LVTTL outputs */
} XMC_GPIO_OUTPUT_STRENGTH_t;
/**********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/**
* Structure points port hardware registers. Use type XMC_GPIO_PORT_t for this structure.
*/
typedef struct XMC_GPIO_PORT {
__IO uint32_t OUT; /**< The port output register determines the value of a GPIO pin when it is selected by
Pn_IOCRx as output */
__O uint32_t OMR; /**< The port output modification register contains control bits that make it possible
to individually set, reset, or toggle the logic state of a single port line*/
__I uint32_t RESERVED0[2];
__IO uint32_t IOCR[4]; /**< The port input/output control registers select the digital output and input driver
functionality and characteristics of a GPIO port pin */
__I uint32_t RESERVED1;
__I uint32_t IN; /**< The logic level of a GPIO pin can be read via the read-only port input register
Pn_IN */
__I uint32_t RESERVED2[6];
__IO uint32_t PDR[2]; /**< Pad Driver Mode Registers */
__I uint32_t RESERVED3[6];
__IO uint32_t PDISC; /**< Pin Function Decision Control Register is to disable/enable the digital pad
structure in shared analog and digital ports*/
__I uint32_t RESERVED4[3];
__IO uint32_t PPS; /**< Pin Power Save Register */
__IO uint32_t HWSEL; /**< Pin Hardware Select Register */
} XMC_GPIO_PORT_t;
/**
* Structure initializes port pin. Use type XMC_GPIO_CONFIG_t for this structure.
*/
typedef struct XMC_GPIO_CONFIG
{
XMC_GPIO_MODE_t mode; /**< Defines the direction and characteristics of a pin */
XMC_GPIO_OUTPUT_LEVEL_t output_level; /**< Defines output level of a pin */
XMC_GPIO_OUTPUT_STRENGTH_t output_strength; /**< Defines pad driver mode of a pin */
} XMC_GPIO_CONFIG_t;
/**********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
__STATIC_INLINE bool XMC_GPIO_IsModeValid(XMC_GPIO_MODE_t mode)
{
return ((mode == XMC_GPIO_MODE_INPUT_TRISTATE) ||
(mode == XMC_GPIO_MODE_INPUT_PULL_DOWN) ||
(mode == XMC_GPIO_MODE_INPUT_PULL_UP) ||
(mode == XMC_GPIO_MODE_INPUT_SAMPLING) ||
(mode == XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE) ||
(mode == XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN) ||
(mode == XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP) ||
(mode == XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3) ||
(mode == XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3) ||
(mode == XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4));
}
/**
*
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDR.
* @param pin Port pin number.
* @param strength Output driver mode selection. Refer data structure @ref XMC_GPIO_OUTPUT_STRENGTH_t for details.
*
* @return None
*
* \par<b>Description:</b><br>
* Sets port pin output strength and slew rate. It configures hardware registers Pn_PDR. \a strength is initially
* configured during initialization in XMC_GPIO_Init(). Call this API to alter output driver mode as needed later in
* the program.
*
* \par<b>Related APIs:</b><BR>
* None
*
* \par<b>Note:</b><br>
* Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().
*
*/
void XMC_GPIO_SetOutputStrength(XMC_GPIO_PORT_t *const port, const uint8_t pin, XMC_GPIO_OUTPUT_STRENGTH_t strength);
/**
* @} (end addtogroup GPIO)
*/
/**
* @} (end addtogroup XMClib)
*/
#endif /* UC_FAMILY == XMC4 */
#endif /* XMC4_GPIO_H */

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/**
* @file xmc4_rtc.h
* @date 2015-05-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial
*
* 2015-05-20:
* - Documentation updates <br>
*
* @endcond
*
*/
#ifndef XMC4_RTC_H
#define XMC4_RTC_H
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup RTC
* @{
*/
/*********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* Wakeup events for RTC from hibernate domain
*/
typedef enum XMC_RTC_WAKEUP_EVENT
{
XMC_RTC_WAKEUP_EVENT_ON_ALARM = RTC_CTR_TAE_Msk, /**< Wakeup from alarm event */
XMC_RTC_WAKEUP_EVENT_ON_SECONDS = RTC_CTR_ESEC_Msk, /**< Wakeup from seconds event */
XMC_RTC_WAKEUP_EVENT_ON_MINUTES = RTC_CTR_EMIC_Msk, /**< Wakeup from minutes event */
XMC_RTC_WAKEUP_EVENT_ON_HOURS = RTC_CTR_EHOC_Msk, /**< Wakeup from hours event */
XMC_RTC_WAKEUP_EVENT_ON_DAYS = RTC_CTR_EDAC_Msk, /**< Wakeup from days event */
XMC_RTC_WAKEUP_EVENT_ON_MONTHS = RTC_CTR_EMOC_Msk, /**< Wakeup from months event */
XMC_RTC_WAKEUP_EVENT_ON_YEARS = RTC_CTR_EYEC_Msk /**< Wakeup from years event */
} XMC_RTC_WAKEUP_EVENT_t;
/*********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param event A valid RTC Wakeup event (::XMC_RTC_WAKEUP_EVENT_t) or a valid combination of
* logically OR'd events
* @return None
*
* \par<b>Description: </b><br>
* Enable Wakeup from hibernate mode <br>
*
* \par
* The function sets the bitfields of CTR register to enable wakeup from hibernate mode.
* Setting the masking value for the RTC wakeup events containing in the ::XMC_RTC_WAKEUP_EVENT_t
* leads to a wakeup from hibernate mode.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_DisableHibernationWakeUp()
*/
__STATIC_INLINE void XMC_RTC_EnableHibernationWakeUp(const uint32_t event)
{
RTC->CTR |= event;
}
/**
* @param event A valid RTC Wakeup event (::XMC_RTC_WAKEUP_EVENT_t) or a valid combination of
* logically OR'd events
* @return None
*
* \par<b>Description: </b><br>
* Disable Wakeup from hibernate mode <br>
*
* \par
* The function resets the bitfields of CTR register to disable wakeup from hibernate mode.
* Resetting the masking value for the RTC wakeup events containing in the ::XMC_RTC_WAKEUP_EVENT_t
* disables wakeup from hibernate mode.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_EnableHibernationWakeUp()
*/
__STATIC_INLINE void XMC_RTC_DisableHibernationWakeUp(const uint32_t event)
{
RTC->CTR &= ~event;
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* XMC4_RTC_H */

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/**
* @file xmc_can_map.h
* @date 2015-10-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-10-20:
* - Removed "const" in the MOs for avoiding compiler warnings
*
* 2015-09-15:
* - Initial version
*
* @endcond
*
*/
#ifndef XMC_CAN_MAP_H
#define XMC_CAN_MAP_H
/*******************************************************************************
* MACROS
*******************************************************************************/
#if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN48)
#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#endif
#if (UC_DEVICE == XMC1403) && (UC_PACKAGE == VQFN64)
#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P4_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P4_9 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#endif
#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN48)
#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#endif
#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == VQFN64)
#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P4_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P4_9 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#endif
#if (UC_DEVICE == XMC1404) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P0_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P0_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P0_14 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE0_RXD_P0_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE0_RXD_P2_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE0_RXD_P2_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE0_RXD_P1_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE0_RXD_P1_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#define CAN_NODE1_RXD_P0_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P0_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P4_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P4_9 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_P2_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
#define CAN_NODE1_RXD_P2_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE1_RXD_P1_2 XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
#define CAN_NODE1_RXD_P1_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
#endif
#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4100) && (UC_PACKAGE == VQFN48)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#endif
#if (UC_DEVICE == XMC4108) && (UC_PACKAGE == VQFN48)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#endif
#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4200) && (UC_PACKAGE == VQFN48)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP100)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4400) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP100)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4402) && (UC_PACKAGE == LQFP64)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == BGA144)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP100)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4500) && (UC_PACKAGE == LQFP144)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4502) && (UC_PACKAGE == LQFP100)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP144)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE3_RXD_P0_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE3_RXD_P6_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE4_RXD_P2_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE4_RXD_P14_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE5_RXD_P5_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#endif
#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LQFP100)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE3_RXD_P0_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE3_RXD_P6_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE4_RXD_P2_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE4_RXD_P14_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#endif
#if (UC_DEVICE == XMC4800) && (UC_PACKAGE == LFBGA196)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P3_11 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE2_RXD_P1_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE2_RXD_P3_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE2_RXD_P4_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE2_RXD_CAN1INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#define CAN_NODE3_RXD_P0_8 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE3_RXD_P6_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE3_RXD_P7_1 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE4_RXD_P2_15 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE4_RXD_P14_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE4_RXD_P7_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE5_RXD_P5_10 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE5_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE5_RXD_P8_0 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#endif
#if (UC_DEVICE == XMC4300) && (UC_PACKAGE == LQFP100)
#define CAN_NODE0_RXD_P1_5 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE0_RXD_P14_3 XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
#define CAN_NODE0_RXD_P3_12 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P2_6 XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
#define CAN_NODE1_RXD_P1_13 XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
#define CAN_NODE1_RXD_P1_4 XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
#define CAN_NODE1_RXD_CAN0INS XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
#endif
#if (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || (UC_SERIES == XMC43)|| (UC_SERIES == XMC14)
#define CAN_MO0 ((CAN_MO_TypeDef *)&(CAN_MO->MO[0]))
#define CAN_MO1 ((CAN_MO_TypeDef *)&(CAN_MO->MO[1]))
#define CAN_MO2 ((CAN_MO_TypeDef *)&(CAN_MO->MO[2]))
#define CAN_MO3 ((CAN_MO_TypeDef *)&(CAN_MO->MO[3]))
#define CAN_MO4 ((CAN_MO_TypeDef *)&(CAN_MO->MO[4]))
#define CAN_MO5 ((CAN_MO_TypeDef *)&(CAN_MO->MO[5]))
#define CAN_MO6 ((CAN_MO_TypeDef *)&(CAN_MO->MO[6]))
#define CAN_MO7 ((CAN_MO_TypeDef *)&(CAN_MO->MO[7]))
#define CAN_MO8 ((CAN_MO_TypeDef *)&(CAN_MO->MO[8]))
#define CAN_MO9 ((CAN_MO_TypeDef *)&(CAN_MO->MO[9]))
#define CAN_MO10 ((CAN_MO_TypeDef *)&(CAN_MO->MO[10]))
#define CAN_MO11 ((CAN_MO_TypeDef *)&(CAN_MO->MO[11]))
#define CAN_MO12 ((CAN_MO_TypeDef *)&(CAN_MO->MO[12]))
#define CAN_MO13 ((CAN_MO_TypeDef *)&(CAN_MO->MO[13]))
#define CAN_MO14 ((CAN_MO_TypeDef *)&(CAN_MO->MO[14]))
#define CAN_MO15 ((CAN_MO_TypeDef *)&(CAN_MO->MO[15]))
#define CAN_MO16 ((CAN_MO_TypeDef *)&(CAN_MO->MO[16]))
#define CAN_MO17 ((CAN_MO_TypeDef *)&(CAN_MO->MO[17]))
#define CAN_MO18 ((CAN_MO_TypeDef *)&(CAN_MO->MO[18]))
#define CAN_MO19 ((CAN_MO_TypeDef *)&(CAN_MO->MO[19]))
#define CAN_MO20 ((CAN_MO_TypeDef *)&(CAN_MO->MO[20]))
#define CAN_MO21 ((CAN_MO_TypeDef *)&(CAN_MO->MO[21]))
#define CAN_MO22 ((CAN_MO_TypeDef *)&(CAN_MO->MO[22]))
#define CAN_MO23 ((CAN_MO_TypeDef *)&(CAN_MO->MO[23]))
#define CAN_MO24 ((CAN_MO_TypeDef *)&(CAN_MO->MO[24]))
#define CAN_MO25 ((CAN_MO_TypeDef *)&(CAN_MO->MO[25]))
#define CAN_MO26 ((CAN_MO_TypeDef *)&(CAN_MO->MO[26]))
#define CAN_MO27 ((CAN_MO_TypeDef *)&(CAN_MO->MO[27]))
#define CAN_MO28 ((CAN_MO_TypeDef *)&(CAN_MO->MO[28]))
#define CAN_MO29 ((CAN_MO_TypeDef *)&(CAN_MO->MO[29]))
#define CAN_MO30 ((CAN_MO_TypeDef *)&(CAN_MO->MO[30]))
#define CAN_MO31 ((CAN_MO_TypeDef *)&(CAN_MO->MO[31]))
#endif
#if (UC_SERIES == XMC47) || (UC_SERIES == XMC48)|| (UC_SERIES == XMC43)
#define CAN_MO32 ((CAN_MO_TypeDef *)&(CAN_MO->MO[32]))
#define CAN_MO33 ((CAN_MO_TypeDef *)&(CAN_MO->MO[33]))
#define CAN_MO34 ((CAN_MO_TypeDef *)&(CAN_MO->MO[34]))
#define CAN_MO35 ((CAN_MO_TypeDef *)&(CAN_MO->MO[35]))
#define CAN_MO36 ((CAN_MO_TypeDef *)&(CAN_MO->MO[36]))
#define CAN_MO37 ((CAN_MO_TypeDef *)&(CAN_MO->MO[37]))
#define CAN_MO38 ((CAN_MO_TypeDef *)&(CAN_MO->MO[38]))
#define CAN_MO39 ((CAN_MO_TypeDef *)&(CAN_MO->MO[39]))
#define CAN_MO40 ((CAN_MO_TypeDef *)&(CAN_MO->MO[40]))
#define CAN_MO41 ((CAN_MO_TypeDef *)&(CAN_MO->MO[41]))
#define CAN_MO42 ((CAN_MO_TypeDef *)&(CAN_MO->MO[42]))
#define CAN_MO43 ((CAN_MO_TypeDef *)&(CAN_MO->MO[43]))
#define CAN_MO44 ((CAN_MO_TypeDef *)&(CAN_MO->MO[44]))
#define CAN_MO45 ((CAN_MO_TypeDef *)&(CAN_MO->MO[45]))
#define CAN_MO46 ((CAN_MO_TypeDef *)&(CAN_MO->MO[46]))
#define CAN_MO47 ((CAN_MO_TypeDef *)&(CAN_MO->MO[47]))
#define CAN_MO48 ((CAN_MO_TypeDef *)&(CAN_MO->MO[48]))
#define CAN_MO49 ((CAN_MO_TypeDef *)&(CAN_MO->MO[49]))
#define CAN_MO50 ((CAN_MO_TypeDef *)&(CAN_MO->MO[50]))
#define CAN_MO51 ((CAN_MO_TypeDef *)&(CAN_MO->MO[51]))
#define CAN_MO52 ((CAN_MO_TypeDef *)&(CAN_MO->MO[52]))
#define CAN_MO53 ((CAN_MO_TypeDef *)&(CAN_MO->MO[53]))
#define CAN_MO54 ((CAN_MO_TypeDef *)&(CAN_MO->MO[54]))
#define CAN_MO55 ((CAN_MO_TypeDef *)&(CAN_MO->MO[55]))
#define CAN_MO56 ((CAN_MO_TypeDef *)&(CAN_MO->MO[56]))
#define CAN_MO57 ((CAN_MO_TypeDef *)&(CAN_MO->MO[57]))
#define CAN_MO58 ((CAN_MO_TypeDef *)&(CAN_MO->MO[58]))
#define CAN_MO59 ((CAN_MO_TypeDef *)&(CAN_MO->MO[59]))
#define CAN_MO60 ((CAN_MO_TypeDef *)&(CAN_MO->MO[60]))
#define CAN_MO61 ((CAN_MO_TypeDef *)&(CAN_MO->MO[61]))
#define CAN_MO62 ((CAN_MO_TypeDef *)&(CAN_MO->MO[62]))
#define CAN_MO63 ((CAN_MO_TypeDef *)&(CAN_MO->MO[63]))
#if (UC_SERIES != XMC43)
#define CAN_MO64 ((CAN_MO_TypeDef *)&(CAN_MO->MO[64]))
#define CAN_MO65 ((CAN_MO_TypeDef *)&(CAN_MO->MO[65]))
#define CAN_MO66 ((CAN_MO_TypeDef *)&(CAN_MO->MO[66]))
#define CAN_MO67 ((CAN_MO_TypeDef *)&(CAN_MO->MO[67]))
#define CAN_MO68 ((CAN_MO_TypeDef *)&(CAN_MO->MO[68]))
#define CAN_MO69 ((CAN_MO_TypeDef *)&(CAN_MO->MO[69]))
#define CAN_MO70 ((CAN_MO_TypeDef *)&(CAN_MO->MO[70]))
#define CAN_MO71 ((CAN_MO_TypeDef *)&(CAN_MO->MO[71]))
#define CAN_MO72 ((CAN_MO_TypeDef *)&(CAN_MO->MO[72]))
#define CAN_MO73 ((CAN_MO_TypeDef *)&(CAN_MO->MO[73]))
#define CAN_MO74 ((CAN_MO_TypeDef *)&(CAN_MO->MO[74]))
#define CAN_MO75 ((CAN_MO_TypeDef *)&(CAN_MO->MO[75]))
#define CAN_MO76 ((CAN_MO_TypeDef *)&(CAN_MO->MO[76]))
#define CAN_MO77 ((CAN_MO_TypeDef *)&(CAN_MO->MO[77]))
#define CAN_MO78 ((CAN_MO_TypeDef *)&(CAN_MO->MO[78]))
#define CAN_MO79 ((CAN_MO_TypeDef *)&(CAN_MO->MO[79]))
#define CAN_MO80 ((CAN_MO_TypeDef *)&(CAN_MO->MO[80]))
#define CAN_MO81 ((CAN_MO_TypeDef *)&(CAN_MO->MO[81]))
#define CAN_MO82 ((CAN_MO_TypeDef *)&(CAN_MO->MO[82]))
#define CAN_MO83 ((CAN_MO_TypeDef *)&(CAN_MO->MO[83]))
#define CAN_MO84 ((CAN_MO_TypeDef *)&(CAN_MO->MO[84]))
#define CAN_MO85 ((CAN_MO_TypeDef *)&(CAN_MO->MO[85]))
#define CAN_MO86 ((CAN_MO_TypeDef *)&(CAN_MO->MO[86]))
#define CAN_MO87 ((CAN_MO_TypeDef *)&(CAN_MO->MO[87]))
#define CAN_MO88 ((CAN_MO_TypeDef *)&(CAN_MO->MO[88]))
#define CAN_MO89 ((CAN_MO_TypeDef *)&(CAN_MO->MO[89]))
#define CAN_MO90 ((CAN_MO_TypeDef *)&(CAN_MO->MO[90]))
#define CAN_MO91 ((CAN_MO_TypeDef *)&(CAN_MO->MO[91]))
#define CAN_MO92 ((CAN_MO_TypeDef *)&(CAN_MO->MO[92]))
#define CAN_MO93 ((CAN_MO_TypeDef *)&(CAN_MO->MO[93]))
#define CAN_MO94 ((CAN_MO_TypeDef *)&(CAN_MO->MO[94]))
#define CAN_MO95 ((CAN_MO_TypeDef *)&(CAN_MO->MO[95]))
#define CAN_MO96 ((CAN_MO_TypeDef *)&(CAN_MO->MO[96]))
#define CAN_MO97 ((CAN_MO_TypeDef *)&(CAN_MO->MO[97]))
#define CAN_MO98 ((CAN_MO_TypeDef *)&(CAN_MO->MO[98]))
#define CAN_MO99 ((CAN_MO_TypeDef *)&(CAN_MO->MO[99]))
#define CAN_MO100 ((CAN_MO_TypeDef *)&(CAN_MO->MO[100]))
#define CAN_MO101 ((CAN_MO_TypeDef *)&(CAN_MO->MO[101]))
#define CAN_MO102 ((CAN_MO_TypeDef *)&(CAN_MO->MO[102]))
#define CAN_MO103 ((CAN_MO_TypeDef *)&(CAN_MO->MO[103]))
#define CAN_MO104 ((CAN_MO_TypeDef *)&(CAN_MO->MO[104]))
#define CAN_MO105 ((CAN_MO_TypeDef *)&(CAN_MO->MO[105]))
#define CAN_MO106 ((CAN_MO_TypeDef *)&(CAN_MO->MO[106]))
#define CAN_MO107 ((CAN_MO_TypeDef *)&(CAN_MO->MO[107]))
#define CAN_MO108 ((CAN_MO_TypeDef *)&(CAN_MO->MO[108]))
#define CAN_MO109 ((CAN_MO_TypeDef *)&(CAN_MO->MO[109]))
#define CAN_MO110 ((CAN_MO_TypeDef *)&(CAN_MO->MO[110]))
#define CAN_MO111 ((CAN_MO_TypeDef *)&(CAN_MO->MO[111]))
#define CAN_MO112 ((CAN_MO_TypeDef *)&(CAN_MO->MO[112]))
#define CAN_MO113 ((CAN_MO_TypeDef *)&(CAN_MO->MO[113]))
#define CAN_MO114 ((CAN_MO_TypeDef *)&(CAN_MO->MO[114]))
#define CAN_MO115 ((CAN_MO_TypeDef *)&(CAN_MO->MO[115]))
#define CAN_MO116 ((CAN_MO_TypeDef *)&(CAN_MO->MO[116]))
#define CAN_MO117 ((CAN_MO_TypeDef *)&(CAN_MO->MO[117]))
#define CAN_MO118 ((CAN_MO_TypeDef *)&(CAN_MO->MO[118]))
#define CAN_MO119 ((CAN_MO_TypeDef *)&(CAN_MO->MO[119]))
#define CAN_MO120 ((CAN_MO_TypeDef *)&(CAN_MO->MO[120]))
#define CAN_MO121 ((CAN_MO_TypeDef *)&(CAN_MO->MO[121]))
#define CAN_MO122 ((CAN_MO_TypeDef *)&(CAN_MO->MO[122]))
#define CAN_MO123 ((CAN_MO_TypeDef *)&(CAN_MO->MO[123]))
#define CAN_MO124 ((CAN_MO_TypeDef *)&(CAN_MO->MO[124]))
#define CAN_MO125 ((CAN_MO_TypeDef *)&(CAN_MO->MO[125]))
#define CAN_MO126 ((CAN_MO_TypeDef *)&(CAN_MO->MO[126]))
#define CAN_MO127 ((CAN_MO_TypeDef *)&(CAN_MO->MO[127]))
#define CAN_MO128 ((CAN_MO_TypeDef *)&(CAN_MO->MO[128]))
#define CAN_MO129 ((CAN_MO_TypeDef *)&(CAN_MO->MO[129]))
#define CAN_MO130 ((CAN_MO_TypeDef *)&(CAN_MO->MO[130]))
#define CAN_MO131 ((CAN_MO_TypeDef *)&(CAN_MO->MO[131]))
#define CAN_MO132 ((CAN_MO_TypeDef *)&(CAN_MO->MO[132]))
#define CAN_MO133 ((CAN_MO_TypeDef *)&(CAN_MO->MO[133]))
#define CAN_MO134 ((CAN_MO_TypeDef *)&(CAN_MO->MO[134]))
#define CAN_MO135 ((CAN_MO_TypeDef *)&(CAN_MO->MO[135]))
#define CAN_MO136 ((CAN_MO_TypeDef *)&(CAN_MO->MO[136]))
#define CAN_MO137 ((CAN_MO_TypeDef *)&(CAN_MO->MO[137]))
#define CAN_MO138 ((CAN_MO_TypeDef *)&(CAN_MO->MO[138]))
#define CAN_MO139 ((CAN_MO_TypeDef *)&(CAN_MO->MO[139]))
#define CAN_MO140 ((CAN_MO_TypeDef *)&(CAN_MO->MO[140]))
#define CAN_MO141 ((CAN_MO_TypeDef *)&(CAN_MO->MO[141]))
#define CAN_MO142 ((CAN_MO_TypeDef *)&(CAN_MO->MO[142]))
#define CAN_MO143 ((CAN_MO_TypeDef *)&(CAN_MO->MO[143]))
#define CAN_MO144 ((CAN_MO_TypeDef *)&(CAN_MO->MO[144]))
#define CAN_MO145 ((CAN_MO_TypeDef *)&(CAN_MO->MO[145]))
#define CAN_MO146 ((CAN_MO_TypeDef *)&(CAN_MO->MO[146]))
#define CAN_MO147 ((CAN_MO_TypeDef *)&(CAN_MO->MO[147]))
#define CAN_MO148 ((CAN_MO_TypeDef *)&(CAN_MO->MO[148]))
#define CAN_MO149 ((CAN_MO_TypeDef *)&(CAN_MO->MO[149]))
#define CAN_MO150 ((CAN_MO_TypeDef *)&(CAN_MO->MO[150]))
#define CAN_MO151 ((CAN_MO_TypeDef *)&(CAN_MO->MO[151]))
#define CAN_MO152 ((CAN_MO_TypeDef *)&(CAN_MO->MO[152]))
#define CAN_MO153 ((CAN_MO_TypeDef *)&(CAN_MO->MO[153]))
#define CAN_MO154 ((CAN_MO_TypeDef *)&(CAN_MO->MO[154]))
#define CAN_MO155 ((CAN_MO_TypeDef *)&(CAN_MO->MO[155]))
#define CAN_MO156 ((CAN_MO_TypeDef *)&(CAN_MO->MO[156]))
#define CAN_MO157 ((CAN_MO_TypeDef *)&(CAN_MO->MO[157]))
#define CAN_MO158 ((CAN_MO_TypeDef *)&(CAN_MO->MO[158]))
#define CAN_MO159 ((CAN_MO_TypeDef *)&(CAN_MO->MO[159]))
#define CAN_MO160 ((CAN_MO_TypeDef *)&(CAN_MO->MO[160]))
#define CAN_MO161 ((CAN_MO_TypeDef *)&(CAN_MO->MO[161]))
#define CAN_MO162 ((CAN_MO_TypeDef *)&(CAN_MO->MO[162]))
#define CAN_MO163 ((CAN_MO_TypeDef *)&(CAN_MO->MO[163]))
#define CAN_MO164 ((CAN_MO_TypeDef *)&(CAN_MO->MO[164]))
#define CAN_MO165 ((CAN_MO_TypeDef *)&(CAN_MO->MO[165]))
#define CAN_MO166 ((CAN_MO_TypeDef *)&(CAN_MO->MO[166]))
#define CAN_MO167 ((CAN_MO_TypeDef *)&(CAN_MO->MO[167]))
#define CAN_MO168 ((CAN_MO_TypeDef *)&(CAN_MO->MO[168]))
#define CAN_MO169 ((CAN_MO_TypeDef *)&(CAN_MO->MO[169]))
#define CAN_MO170 ((CAN_MO_TypeDef *)&(CAN_MO->MO[170]))
#define CAN_MO171 ((CAN_MO_TypeDef *)&(CAN_MO->MO[171]))
#define CAN_MO172 ((CAN_MO_TypeDef *)&(CAN_MO->MO[172]))
#define CAN_MO173 ((CAN_MO_TypeDef *)&(CAN_MO->MO[173]))
#define CAN_MO174 ((CAN_MO_TypeDef *)&(CAN_MO->MO[174]))
#define CAN_MO175 ((CAN_MO_TypeDef *)&(CAN_MO->MO[175]))
#define CAN_MO176 ((CAN_MO_TypeDef *)&(CAN_MO->MO[176]))
#define CAN_MO177 ((CAN_MO_TypeDef *)&(CAN_MO->MO[177]))
#define CAN_MO178 ((CAN_MO_TypeDef *)&(CAN_MO->MO[178]))
#define CAN_MO179 ((CAN_MO_TypeDef *)&(CAN_MO->MO[179]))
#define CAN_MO180 ((CAN_MO_TypeDef *)&(CAN_MO->MO[180]))
#define CAN_MO181 ((CAN_MO_TypeDef *)&(CAN_MO->MO[181]))
#define CAN_MO182 ((CAN_MO_TypeDef *)&(CAN_MO->MO[182]))
#define CAN_MO183 ((CAN_MO_TypeDef *)&(CAN_MO->MO[183]))
#define CAN_MO184 ((CAN_MO_TypeDef *)&(CAN_MO->MO[184]))
#define CAN_MO185 ((CAN_MO_TypeDef *)&(CAN_MO->MO[185]))
#define CAN_MO186 ((CAN_MO_TypeDef *)&(CAN_MO->MO[186]))
#define CAN_MO187 ((CAN_MO_TypeDef *)&(CAN_MO->MO[187]))
#define CAN_MO188 ((CAN_MO_TypeDef *)&(CAN_MO->MO[188]))
#define CAN_MO189 ((CAN_MO_TypeDef *)&(CAN_MO->MO[189]))
#define CAN_MO190 ((CAN_MO_TypeDef *)&(CAN_MO->MO[190]))
#define CAN_MO191 ((CAN_MO_TypeDef *)&(CAN_MO->MO[191]))
#define CAN_MO192 ((CAN_MO_TypeDef *)&(CAN_MO->MO[192]))
#define CAN_MO193 ((CAN_MO_TypeDef *)&(CAN_MO->MO[193]))
#define CAN_MO194 ((CAN_MO_TypeDef *)&(CAN_MO->MO[194]))
#define CAN_MO195 ((CAN_MO_TypeDef *)&(CAN_MO->MO[195]))
#define CAN_MO196 ((CAN_MO_TypeDef *)&(CAN_MO->MO[196]))
#define CAN_MO197 ((CAN_MO_TypeDef *)&(CAN_MO->MO[197]))
#define CAN_MO198 ((CAN_MO_TypeDef *)&(CAN_MO->MO[198]))
#define CAN_MO199 ((CAN_MO_TypeDef *)&(CAN_MO->MO[199]))
#define CAN_MO200 ((CAN_MO_TypeDef *)&(CAN_MO->MO[200]))
#define CAN_MO201 ((CAN_MO_TypeDef *)&(CAN_MO->MO[201]))
#define CAN_MO202 ((CAN_MO_TypeDef *)&(CAN_MO->MO[202]))
#define CAN_MO203 ((CAN_MO_TypeDef *)&(CAN_MO->MO[203]))
#define CAN_MO204 ((CAN_MO_TypeDef *)&(CAN_MO->MO[204]))
#define CAN_MO205 ((CAN_MO_TypeDef *)&(CAN_MO->MO[205]))
#define CAN_MO206 ((CAN_MO_TypeDef *)&(CAN_MO->MO[206]))
#define CAN_MO207 ((CAN_MO_TypeDef *)&(CAN_MO->MO[207]))
#define CAN_MO208 ((CAN_MO_TypeDef *)&(CAN_MO->MO[208]))
#define CAN_MO209 ((CAN_MO_TypeDef *)&(CAN_MO->MO[209]))
#define CAN_MO210 ((CAN_MO_TypeDef *)&(CAN_MO->MO[210]))
#define CAN_MO211 ((CAN_MO_TypeDef *)&(CAN_MO->MO[211]))
#define CAN_MO212 ((CAN_MO_TypeDef *)&(CAN_MO->MO[212]))
#define CAN_MO213 ((CAN_MO_TypeDef *)&(CAN_MO->MO[213]))
#define CAN_MO214 ((CAN_MO_TypeDef *)&(CAN_MO->MO[214]))
#define CAN_MO215 ((CAN_MO_TypeDef *)&(CAN_MO->MO[215]))
#define CAN_MO216 ((CAN_MO_TypeDef *)&(CAN_MO->MO[216]))
#define CAN_MO217 ((CAN_MO_TypeDef *)&(CAN_MO->MO[217]))
#define CAN_MO218 ((CAN_MO_TypeDef *)&(CAN_MO->MO[218]))
#define CAN_MO219 ((CAN_MO_TypeDef *)&(CAN_MO->MO[219]))
#define CAN_MO220 ((CAN_MO_TypeDef *)&(CAN_MO->MO[220]))
#define CAN_MO221 ((CAN_MO_TypeDef *)&(CAN_MO->MO[221]))
#define CAN_MO222 ((CAN_MO_TypeDef *)&(CAN_MO->MO[222]))
#define CAN_MO223 ((CAN_MO_TypeDef *)&(CAN_MO->MO[223]))
#define CAN_MO224 ((CAN_MO_TypeDef *)&(CAN_MO->MO[224]))
#define CAN_MO225 ((CAN_MO_TypeDef *)&(CAN_MO->MO[225]))
#define CAN_MO226 ((CAN_MO_TypeDef *)&(CAN_MO->MO[226]))
#define CAN_MO227 ((CAN_MO_TypeDef *)&(CAN_MO->MO[227]))
#define CAN_MO228 ((CAN_MO_TypeDef *)&(CAN_MO->MO[228]))
#define CAN_MO229 ((CAN_MO_TypeDef *)&(CAN_MO->MO[229]))
#define CAN_MO230 ((CAN_MO_TypeDef *)&(CAN_MO->MO[230]))
#define CAN_MO231 ((CAN_MO_TypeDef *)&(CAN_MO->MO[231]))
#define CAN_MO232 ((CAN_MO_TypeDef *)&(CAN_MO->MO[232]))
#define CAN_MO233 ((CAN_MO_TypeDef *)&(CAN_MO->MO[233]))
#define CAN_MO234 ((CAN_MO_TypeDef *)&(CAN_MO->MO[234]))
#define CAN_MO235 ((CAN_MO_TypeDef *)&(CAN_MO->MO[235]))
#define CAN_MO236 ((CAN_MO_TypeDef *)&(CAN_MO->MO[236]))
#define CAN_MO237 ((CAN_MO_TypeDef *)&(CAN_MO->MO[237]))
#define CAN_MO238 ((CAN_MO_TypeDef *)&(CAN_MO->MO[238]))
#define CAN_MO239 ((CAN_MO_TypeDef *)&(CAN_MO->MO[239]))
#define CAN_MO240 ((CAN_MO_TypeDef *)&(CAN_MO->MO[240]))
#define CAN_MO241 ((CAN_MO_TypeDef *)&(CAN_MO->MO[241]))
#define CAN_MO242 ((CAN_MO_TypeDef *)&(CAN_MO->MO[242]))
#define CAN_MO243 ((CAN_MO_TypeDef *)&(CAN_MO->MO[243]))
#define CAN_MO244 ((CAN_MO_TypeDef *)&(CAN_MO->MO[244]))
#define CAN_MO245 ((CAN_MO_TypeDef *)&(CAN_MO->MO[245]))
#define CAN_MO246 ((CAN_MO_TypeDef *)&(CAN_MO->MO[246]))
#define CAN_MO247 ((CAN_MO_TypeDef *)&(CAN_MO->MO[247]))
#define CAN_MO248 ((CAN_MO_TypeDef *)&(CAN_MO->MO[248]))
#define CAN_MO249 ((CAN_MO_TypeDef *)&(CAN_MO->MO[249]))
#define CAN_MO250 ((CAN_MO_TypeDef *)&(CAN_MO->MO[250]))
#define CAN_MO251 ((CAN_MO_TypeDef *)&(CAN_MO->MO[251]))
#define CAN_MO252 ((CAN_MO_TypeDef *)&(CAN_MO->MO[252]))
#define CAN_MO253 ((CAN_MO_TypeDef *)&(CAN_MO->MO[253]))
#define CAN_MO254 ((CAN_MO_TypeDef *)&(CAN_MO->MO[254]))
#define CAN_MO255 ((CAN_MO_TypeDef *)&(CAN_MO->MO[255]))
#endif
#endif
#endif /* XMC_CAN_MAP_H*/

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/**
* @file xmc_common.h
* @date 2017-04-04
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-06-20:
* - Initial
* - Brief section updated
* - Added XMC_LIB_VERSION macro
*
* 2016-02-26:
* - Updated XMC_LIB_VERSION macro to v2.1.6
*
* 2016-05-30:
* - Updated XMC_LIB_VERSION macro to v2.1.8
*
* 2016-11-18:
* - Updated XMC_LIB_VERSION macro to v2.1.10
* - Changed type of size in XMC_PRIOARRAY_t to fix compilation warnings
*
* 2017-04-04:
* - Updated XMC_LIB_VERSION macro to v2.1.12
*
* @endcond
*
*/
#ifndef XMC_COMMON_H
#define XMC_COMMON_H
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "xmc_device.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup COMMON
* @brief Common APIs to all peripherals for XMC microcontroller family
* @{
*/
/**********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#define XMC_LIB_MAJOR_VERSION (2U)
#define XMC_LIB_MINOR_VERSION (1U)
#define XMC_LIB_PATCH_VERSION (12U)
#define XMC_LIB_VERSION ((XMC_LIB_MAJOR_VERSION << 16U) + (XMC_LIB_MINOR_VERSION << 8U) + XMC_LIB_PATCH_VERSION)
/* Define WEAK attribute */
#if !defined(__WEAK)
#if defined ( __CC_ARM )
#define __WEAK __attribute__ ((weak))
#elif defined ( __ICCARM__ )
#define __WEAK __weak
#elif defined ( __GNUC__ )
#define __WEAK __attribute__ ((weak))
#elif defined ( __TASKING__ )
#define __WEAK __attribute__ ((weak))
#endif
#endif
#ifdef XMC_ASSERT_ENABLE
#define XMC_ASSERT(msg, exp) { if(!(exp)) {XMC_AssertHandler(msg, __FILE__, __LINE__);} }
#else
#define XMC_ASSERT(msg, exp) { ; }
#endif
#ifdef XMC_DEBUG_ENABLE
#include <stdio.h>
#define XMC_DEBUG(...) { printf(__VA_ARGS__); }
#else
#define XMC_DEBUG(...) { ; }
#endif
#define XMC_UNUSED_ARG(x) (void)x
#define XMC_STRUCT_INIT(m) memset(&m, 0, sizeof(m))
#define XMC_PRIOARRAY_DEF(name, size) \
XMC_PRIOARRAY_ITEM_t prioarray_m_##name[size + 2]; \
XMC_PRIOARRAY_t prioarray_def_##name = {(size), (prioarray_m_##name)};
#define XMC_PRIOARRAY(name) \
&prioarray_def_##name
/**********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/*
*
*/
typedef struct XMC_DRIVER_VERSION
{
uint8_t major;
uint8_t minor;
uint8_t patch;
} XMC_DRIVER_VERSION_t;
/*
*
*/
typedef void *XMC_LIST_t;
/*
*
*/
typedef struct XMC_PRIOARRAY_ITEM
{
int32_t priority;
int32_t previous;
int32_t next;
} XMC_PRIOARRAY_ITEM_t;
/*
*
*/
typedef struct XMC_PRIOARRAY
{
int32_t size;
XMC_PRIOARRAY_ITEM_t *items;
} XMC_PRIOARRAY_t;
/**********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/*
*
*/
void XMC_AssertHandler(const char *const msg, const char *const file, uint32_t line);
/*
*
*/
void XMC_LIST_Init(XMC_LIST_t *list);
/*
*
*/
void XMC_LIST_Add(XMC_LIST_t *list, void *const item);
/*
*
*/
void XMC_LIST_Remove(XMC_LIST_t *list, void *const item);
/*
*
*/
uint32_t XMC_LIST_GetLength(XMC_LIST_t *list);
/*
*
*/
void *XMC_LIST_GetHead(XMC_LIST_t *list);
/*
*
*/
void *XMC_LIST_GetTail(XMC_LIST_t *list);
/*
*
*/
void XMC_LIST_Insert(XMC_LIST_t *list, void *prev_item, void *new_item);
/*
*
*/
void XMC_PRIOARRAY_Init(XMC_PRIOARRAY_t *prioarray);
/*
*
*/
void XMC_PRIOARRAY_Add(XMC_PRIOARRAY_t *prioarray, int32_t item, int32_t priority);
/*
*
*/
void XMC_PRIOARRAY_Remove(XMC_PRIOARRAY_t *prioarray, int32_t item);
/*
*
*/
__STATIC_INLINE int32_t XMC_PRIOARRAY_GetHead(XMC_PRIOARRAY_t *prioarray)
{
XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL);
return prioarray->items[prioarray->size].next;
}
/*
*
*/
__STATIC_INLINE int32_t XMC_PRIOARRAY_GetTail(XMC_PRIOARRAY_t *prioarray)
{
XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL);
return prioarray->items[prioarray->size + 1].previous;
}
/*
*
*/
__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemPriority(XMC_PRIOARRAY_t *prioarray, int32_t item)
{
XMC_ASSERT("XMC_PRIOARRAY_GetItemPriority: item out of range", (item >= 0) && (item < prioarray->size));
return prioarray->items[item].priority;
}
/*
*
*/
__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemNext(XMC_PRIOARRAY_t *prioarray, int32_t item)
{
XMC_ASSERT("XMC_PRIOARRAY_GetItemNext: item out of range", (item >= 0) && (item < prioarray->size));
return prioarray->items[item].next;
}
/*
*
*/
__STATIC_INLINE int32_t XMC_PRIOARRAY_GetItemPrevious(XMC_PRIOARRAY_t *prioarray, int32_t item)
{
XMC_ASSERT("XMC_PRIOARRAY_GetItemPrevious: item out of range", (item >= 0) && (item < prioarray->size));
return prioarray->items[item].previous;
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* XMC_COMMON_H */

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/**
* @file xmc_dma_map.h
* @date 2015-05-07
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial version
*
* 2015-05-07:
* - Change line numbering for DMA1 <br>
*
* @endcond
*/
#ifndef XMC_DMA_MAP_H
#define XMC_DMA_MAP_H
#define DMA_PERIPHERAL_REQUEST(line, sel) (uint8_t)(line | (sel << 4U))
/*
* DMA LINE 0 of DMA0
*/
#define DMA0_PERIPHERAL_REQUEST_ERU0_SR0_0 DMA_PERIPHERAL_REQUEST(0, 0)
#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR0_0 DMA_PERIPHERAL_REQUEST(0, 1)
#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR3_0 DMA_PERIPHERAL_REQUEST(0, 2)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR0_0 DMA_PERIPHERAL_REQUEST(0, 3)
#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR3_0 DMA_PERIPHERAL_REQUEST(0, 4)
#define DMA0_PERIPHERAL_REQUEST_DSD_SRM0_0 DMA_PERIPHERAL_REQUEST(0, 5)
#endif
#define DMA0_PERIPHERAL_REQUEST_CCU40_SR0_0 DMA_PERIPHERAL_REQUEST(0, 6)
#define DMA0_PERIPHERAL_REQUEST_CCU80_SR0_0 DMA_PERIPHERAL_REQUEST(0, 7)
#define DMA0_PERIPHERAL_REQUEST_CAN_SR0_0 DMA_PERIPHERAL_REQUEST(0, 9)
#define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_0 DMA_PERIPHERAL_REQUEST(0, 10)
#define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_0 DMA_PERIPHERAL_REQUEST(0, 11)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR3_0 DMA_PERIPHERAL_REQUEST(0, 13)
#define DMA0_PERIPHERAL_REQUEST_CCU42_SR0_0 DMA_PERIPHERAL_REQUEST(0, 14)
#endif
#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41))
#define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR0_0 DMA_PERIPHERAL_REQUEST(0, 15)
#endif
/*
* DMA LINE 1 of DMA0
*/
#define DMA0_PERIPHERAL_REQUEST_ERU0_SR3_1 DMA_PERIPHERAL_REQUEST(1, 0)
#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR1_1 DMA_PERIPHERAL_REQUEST(1, 1)
#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR2_1 DMA_PERIPHERAL_REQUEST(1, 2)
#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR0_1 DMA_PERIPHERAL_REQUEST(1, 3)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR2_1 DMA_PERIPHERAL_REQUEST(1, 4)
#endif
#define DMA0_PERIPHERAL_REQUEST_DAC_SR0_1 DMA_PERIPHERAL_REQUEST(1, 5)
#define DMA0_PERIPHERAL_REQUEST_CCU40_SR0_1 DMA_PERIPHERAL_REQUEST(1, 6)
#define DMA0_PERIPHERAL_REQUEST_CCU80_SR0_1 DMA_PERIPHERAL_REQUEST(1, 7)
#define DMA0_PERIPHERAL_REQUEST_CAN_SR0_1 DMA_PERIPHERAL_REQUEST(1, 9)
#define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_1 DMA_PERIPHERAL_REQUEST(1, 10)
#define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_1 DMA_PERIPHERAL_REQUEST(1, 11)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR0_1 DMA_PERIPHERAL_REQUEST(1, 13)
#define DMA0_PERIPHERAL_REQUEST_CCU42_SR0_1 DMA_PERIPHERAL_REQUEST(1, 14)
#endif
#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41))
#define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR1_1 DMA_PERIPHERAL_REQUEST(1, 15)
#endif
/*
* DMA LINE 2 of DMA0
*/
#define DMA0_PERIPHERAL_REQUEST_ERU0_SR1_2 DMA_PERIPHERAL_REQUEST(2, 0)
#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR2_2 DMA_PERIPHERAL_REQUEST(2, 1)
#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR3_2 DMA_PERIPHERAL_REQUEST(2, 2)
#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR3_2 DMA_PERIPHERAL_REQUEST(2, 3)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR1_2 DMA_PERIPHERAL_REQUEST(2, 4)
#define DMA0_PERIPHERAL_REQUEST_DSD_SRM1_2 DMA_PERIPHERAL_REQUEST(2, 5)
#define DMA0_PERIPHERAL_REQUEST_DSD_SRM3_2 DMA_PERIPHERAL_REQUEST(2, 6)
#endif
#define DMA0_PERIPHERAL_REQUEST_CCU40_SR1_2 DMA_PERIPHERAL_REQUEST(2, 7)
#define DMA0_PERIPHERAL_REQUEST_CCU80_SR1_2 DMA_PERIPHERAL_REQUEST(2, 8)
#define DMA0_PERIPHERAL_REQUEST_CAN_SR1_2 DMA_PERIPHERAL_REQUEST(2, 10)
#define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_2 DMA_PERIPHERAL_REQUEST(2, 11)
#define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_2 DMA_PERIPHERAL_REQUEST(2, 12)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR2_2 DMA_PERIPHERAL_REQUEST(2, 13)
#define DMA0_PERIPHERAL_REQUEST_CCU42_SR1_2 DMA_PERIPHERAL_REQUEST(2, 14)
#endif
/*
* DMA LINE 3 of DMA0
*/
#define DMA0_PERIPHERAL_REQUEST_ERU0_SR2_3 DMA_PERIPHERAL_REQUEST(3, 0)
#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR2_3 DMA_PERIPHERAL_REQUEST(3, 1)
#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR3_3 DMA_PERIPHERAL_REQUEST(3, 2)
#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR1_3 DMA_PERIPHERAL_REQUEST(3, 3)
#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR2_3 DMA_PERIPHERAL_REQUEST(3, 4)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_DSD_SRM2_3 DMA_PERIPHERAL_REQUEST(3, 5)
#endif
#define DMA0_PERIPHERAL_REQUEST_DAC_SR1_3 DMA_PERIPHERAL_REQUEST(3, 6)
#define DMA0_PERIPHERAL_REQUEST_CCU40_SR1_3 DMA_PERIPHERAL_REQUEST(3, 7)
#define DMA0_PERIPHERAL_REQUEST_CCU80_SR1_3 DMA_PERIPHERAL_REQUEST(3, 8)
#define DMA0_PERIPHERAL_REQUEST_CAN_SR1_3 DMA_PERIPHERAL_REQUEST(3, 10)
#define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_3 DMA_PERIPHERAL_REQUEST(3, 11)
#define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_3 DMA_PERIPHERAL_REQUEST(3, 12)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR1_3 DMA_PERIPHERAL_REQUEST(3, 13)
#define DMA0_PERIPHERAL_REQUEST_CCU42_SR1_3 DMA_PERIPHERAL_REQUEST(3, 14)
#endif
/*
* DMA LINE 4 of DMA0
*/
#define DMA0_PERIPHERAL_REQUEST_ERU0_SR2_4 DMA_PERIPHERAL_REQUEST(4, 0)
#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR0_4 DMA_PERIPHERAL_REQUEST(4, 1)
#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR1_4 DMA_PERIPHERAL_REQUEST(4, 2)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR1_4 DMA_PERIPHERAL_REQUEST(4, 3)
#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR2_4 DMA_PERIPHERAL_REQUEST(4, 4)
#define DMA0_PERIPHERAL_REQUEST_DSD_SRM2_4 DMA_PERIPHERAL_REQUEST(4, 5)
#endif
#define DMA0_PERIPHERAL_REQUEST_DAC_SR1_4 DMA_PERIPHERAL_REQUEST(4, 6)
#define DMA0_PERIPHERAL_REQUEST_CCU41_SR0_4 DMA_PERIPHERAL_REQUEST(4, 7)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_CCU81_SR0_4 DMA_PERIPHERAL_REQUEST(4, 8)
#endif
#define DMA0_PERIPHERAL_REQUEST_CAN_SR2_4 DMA_PERIPHERAL_REQUEST(4, 10)
#define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_4 DMA_PERIPHERAL_REQUEST(4, 11)
#define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_4 DMA_PERIPHERAL_REQUEST(4, 12)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR1_4 DMA_PERIPHERAL_REQUEST(4, 13)
#define DMA0_PERIPHERAL_REQUEST_CCU43_SR0_4 DMA_PERIPHERAL_REQUEST(4, 14)
#endif
/*
* DMA LINE 5 of DMA0
*/
#define DMA0_PERIPHERAL_REQUEST_ERU0_SR1_5 DMA_PERIPHERAL_REQUEST(5, 0)
#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR0_5 DMA_PERIPHERAL_REQUEST(5, 1)
#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR1_5 DMA_PERIPHERAL_REQUEST(5, 2)
#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR2_5 DMA_PERIPHERAL_REQUEST(5, 3)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR0_5 DMA_PERIPHERAL_REQUEST(5, 4)
#endif
#define DMA0_PERIPHERAL_REQUEST_DAC_SR0_5 DMA_PERIPHERAL_REQUEST(5, 5)
#define DMA0_PERIPHERAL_REQUEST_CCU41_SR0_5 DMA_PERIPHERAL_REQUEST(5, 6)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_CCU81_SR0_5 DMA_PERIPHERAL_REQUEST(5, 7)
#endif
#define DMA0_PERIPHERAL_REQUEST_CAN_SR2_5 DMA_PERIPHERAL_REQUEST(5, 9)
#define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_5 DMA_PERIPHERAL_REQUEST(5, 10)
#define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_5 DMA_PERIPHERAL_REQUEST(5, 11)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR2_5 DMA_PERIPHERAL_REQUEST(5, 13)
#define DMA0_PERIPHERAL_REQUEST_CCU43_SR0_5 DMA_PERIPHERAL_REQUEST(5, 14)
#endif
#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41))
#define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR0_5 DMA_PERIPHERAL_REQUEST(5, 15)
#endif
/*
* DMA LINE 6 of DMA0
*/
#define DMA0_PERIPHERAL_REQUEST_ERU0_SR3_6 DMA_PERIPHERAL_REQUEST(6, 0)
#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR1_6 DMA_PERIPHERAL_REQUEST(6, 1)
#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR2_6 DMA_PERIPHERAL_REQUEST(6, 2)
#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR1_6 DMA_PERIPHERAL_REQUEST(6, 3)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G2SR3_6 DMA_PERIPHERAL_REQUEST(6, 4)
#define DMA0_PERIPHERAL_REQUEST_DSD_SRM1_6 DMA_PERIPHERAL_REQUEST(6, 5)
#define DMA0_PERIPHERAL_REQUEST_DSD_SRM3_6 DMA_PERIPHERAL_REQUEST(6, 6)
#endif
#define DMA0_PERIPHERAL_REQUEST_CCU41_SR1_6 DMA_PERIPHERAL_REQUEST(6, 7)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_CCU81_SR1_6 DMA_PERIPHERAL_REQUEST(6, 8)
#endif
#define DMA0_PERIPHERAL_REQUEST_CAN_SR3_6 DMA_PERIPHERAL_REQUEST(6, 10)
#define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_6 DMA_PERIPHERAL_REQUEST(6, 11)
#define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_6 DMA_PERIPHERAL_REQUEST(6, 12)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR0_6 DMA_PERIPHERAL_REQUEST(6, 13)
#define DMA0_PERIPHERAL_REQUEST_CCU43_SR1_6 DMA_PERIPHERAL_REQUEST(6, 14)
#endif
/*
* DMA LINE 7 of DMA0
*/
#define DMA0_PERIPHERAL_REQUEST_ERU0_SR0_7 DMA_PERIPHERAL_REQUEST(7, 0)
#define DMA0_PERIPHERAL_REQUEST_VADC_C0SR0_7 DMA_PERIPHERAL_REQUEST(7, 1)
#define DMA0_PERIPHERAL_REQUEST_VADC_G0SR3_7 DMA_PERIPHERAL_REQUEST(7, 2)
#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR0_7 DMA_PERIPHERAL_REQUEST(7, 3)
#define DMA0_PERIPHERAL_REQUEST_VADC_G1SR3_7 DMA_PERIPHERAL_REQUEST(7, 4)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_DSD_SRM0_7 DMA_PERIPHERAL_REQUEST(7, 5)
#endif
#define DMA0_PERIPHERAL_REQUEST_CCU41_SR1_7 DMA_PERIPHERAL_REQUEST(7, 6)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_CCU81_SR1_7 DMA_PERIPHERAL_REQUEST(7, 7)
#endif
#define DMA0_PERIPHERAL_REQUEST_CAN_SR3_7 DMA_PERIPHERAL_REQUEST(7, 9)
#define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_7 DMA_PERIPHERAL_REQUEST(7, 10)
#define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_7 DMA_PERIPHERAL_REQUEST(7, 11)
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44))
#define DMA0_PERIPHERAL_REQUEST_VADC_G3SR3_7 DMA_PERIPHERAL_REQUEST(7, 13)
#define DMA0_PERIPHERAL_REQUEST_CCU43_SR1_7 DMA_PERIPHERAL_REQUEST(7, 14)
#endif
#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41))
#define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR1_7 DMA_PERIPHERAL_REQUEST(7, 15)
#endif
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || UC_SERIES == XMC45)
/*
* DMA LINE 0 of DMA1
*/
#define DMA1_PERIPHERAL_REQUEST_ERU0_SR0_8 DMA_PERIPHERAL_REQUEST(0, 0)
#define DMA1_PERIPHERAL_REQUEST_VADC_C0SR0_8 DMA_PERIPHERAL_REQUEST(0, 1)
#define DMA1_PERIPHERAL_REQUEST_VADC_G3SR0_8 DMA_PERIPHERAL_REQUEST(0, 2)
#define DMA1_PERIPHERAL_REQUEST_DSD_SRM0_8 DMA_PERIPHERAL_REQUEST(0, 3)
#define DMA1_PERIPHERAL_REQUEST_DAC_SR0_8 DMA_PERIPHERAL_REQUEST(0, 4)
#define DMA1_PERIPHERAL_REQUEST_CCU42_SR0_8 DMA_PERIPHERAL_REQUEST(0, 5)
#define DMA1_PERIPHERAL_REQUEST_USIC2_SR0_8 DMA_PERIPHERAL_REQUEST(0, 6)
#define DMA1_PERIPHERAL_REQUEST_USIC2_SR2_8 DMA_PERIPHERAL_REQUEST(0, 7)
/*
* DMA LINE 1 of DMA1
*/
#define DMA1_PERIPHERAL_REQUEST_ERU0_SR1_9 DMA_PERIPHERAL_REQUEST(1, 0)
#define DMA1_PERIPHERAL_REQUEST_VADC_C0SR1_9 DMA_PERIPHERAL_REQUEST(1, 1)
#define DMA1_PERIPHERAL_REQUEST_VADC_G3SR1_9 DMA_PERIPHERAL_REQUEST(1, 2)
#define DMA1_PERIPHERAL_REQUEST_DSD_SRM1_9 DMA_PERIPHERAL_REQUEST(1, 3)
#define DMA1_PERIPHERAL_REQUEST_DAC_SR1_9 DMA_PERIPHERAL_REQUEST(1, 4)
#define DMA1_PERIPHERAL_REQUEST_CCU42_SR1_9 DMA_PERIPHERAL_REQUEST(1, 5)
#define DMA1_PERIPHERAL_REQUEST_USIC2_SR1_9 DMA_PERIPHERAL_REQUEST(1, 6)
#define DMA1_PERIPHERAL_REQUEST_USIC2_SR3_9 DMA_PERIPHERAL_REQUEST(1, 7)
/*
* DMA LINE 2 of DMA1
*/
#define DMA1_PERIPHERAL_REQUEST_ERU0_SR2_10 DMA_PERIPHERAL_REQUEST(2, 0)
#define DMA1_PERIPHERAL_REQUEST_VADC_C0SR2_10 DMA_PERIPHERAL_REQUEST(2, 1)
#define DMA1_PERIPHERAL_REQUEST_VADC_G3SR2_10 DMA_PERIPHERAL_REQUEST(2, 2)
#define DMA1_PERIPHERAL_REQUEST_DSD_SRM2_10 DMA_PERIPHERAL_REQUEST(2, 3)
#define DMA1_PERIPHERAL_REQUEST_DAC_SR0_10 DMA_PERIPHERAL_REQUEST(2, 4)
#define DMA1_PERIPHERAL_REQUEST_CCU43_SR0_10 DMA_PERIPHERAL_REQUEST(2, 5)
#define DMA1_PERIPHERAL_REQUEST_USIC2_SR0_10 DMA_PERIPHERAL_REQUEST(2, 6)
#define DMA1_PERIPHERAL_REQUEST_USIC2_SR2_10 DMA_PERIPHERAL_REQUEST(2, 7)
/*
* DMA LINE 3 of DMA1
*/
#define DMA1_PERIPHERAL_REQUEST_ERU0_SR3_11 DMA_PERIPHERAL_REQUEST(3, 0)
#define DMA1_PERIPHERAL_REQUEST_VADC_C0SR3_11 DMA_PERIPHERAL_REQUEST(3, 1)
#define DMA1_PERIPHERAL_REQUEST_VADC_G3SR3_11 DMA_PERIPHERAL_REQUEST(3, 2)
#define DMA1_PERIPHERAL_REQUEST_DSD_SRM3_11 DMA_PERIPHERAL_REQUEST(3, 3)
#define DMA1_PERIPHERAL_REQUEST_DAC_SR1_11 DMA_PERIPHERAL_REQUEST(3, 4)
#define DMA1_PERIPHERAL_REQUEST_CCU43_SR1_11 DMA_PERIPHERAL_REQUEST(3, 5)
#define DMA1_PERIPHERAL_REQUEST_USIC2_SR1_11 DMA_PERIPHERAL_REQUEST(3, 6)
#define DMA1_PERIPHERAL_REQUEST_USIC2_SR3_11 DMA_PERIPHERAL_REQUEST(3, 7)
#endif /* (UC_SERIES == XMC45) */
#endif /* XMC_DMA_MAP_H */

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/**
* @file xmc_ecat.h
* @date 2015-12-27
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-12-27:
* - Initial Version<br>
*
* @endcond
*/
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup ECAT
* @brief EtherCAT Low level driver for XMC4800/XMC4300 series.
*
* EtherCAT is an Ethernet-based fieldbus system.
* The EtherCAT Slave Controller (ECAT) read the data addressed to them while the telegram passes through the device.
* An EtherCAT Slave Controller (ESC) takes care of the EtherCAT communication as an interface between the EtherCAT
* fieldbus and the slave application. EtherCAT uses standard IEEE 802.3 Ethernet frames, thus a standard network
* controller can be used and no special hardware is required on master side. EtherCAT has a reserved EtherType of
* 0x88A4 that distinguishes it from other Ethernet frames. Thus, EtherCAT can run in parallel to other Ethernet
* protocols. EtherCAT does not require the IP protocol, however it can be encapsulated in IP/UDP. The EtherCAT
* Slave Controller processes the frame in hardware. Thus, communication performance is independent from processor
* power.
*
* The XMC_ECAT low level driver provides functions to configure and initialize the ECAT hardware peripheral.
* For EHTERCAT stack integration, the necessary hardware accees layer APIs shall be explicitly implemented depending
* upon the stack provider. The XMC_ECAT lld layer provides only the hardware initialization functions for start up and
* basic functionalities.
* @{
*/
#ifndef XMC_ECAT_H
#define XMC_ECAT_H
/**********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_common.h"
#if defined (ECAT0)
#include "xmc_ecat_map.h"
/**********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
/**********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* ECAT status return values
*/
typedef enum XMC_ECAT_STATUS
{
XMC_ECAT_STATUS_OK = 0U, /**< Driver accepted application request */
XMC_ECAT_STATUS_BUSY = 1U, /**< Driver is busy and cannot handle request */
XMC_ECAT_STATUS_ERROR = 2U /**< Driver could not fulfil application request */
} XMC_ECAT_STATUS_t;
/**
* EtherCAT event enumeration types
*/
typedef enum XMC_ECAT_EVENT
{
XMC_ECAT_EVENT_AL_CONTROL = ECAT_AL_EVENT_MASK_AL_CE_MASK_Msk, /**< Application control event mask */
XMC_ECAT_EVENT_DC_LATCH = ECAT_AL_EVENT_MASK_DC_LE_MASK_Msk, /**< Distributed Clock latch event mask */
XMC_ECAT_EVENT_DC_SYNC0 = ECAT_AL_EVENT_MASK_ST_S0_MASK_Msk, /**< State of distributed clock sync-0 event mask */
XMC_ECAT_EVENT_DC_SYNC1 = ECAT_AL_EVENT_MASK_ST_S1_MASK_Msk, /**< State of distributed clock sync-1 event mask */
XMC_ECAT_EVENT_SM_ACTIVATION_REGISTER = ECAT_AL_EVENT_MASK_SM_A_MASK_Msk, /**< SyncManager activation register mask*/
XMC_ECAT_EVENT_EEPROM = ECAT_AL_EVENT_MASK_EEP_E_MASK_Msk, /**< EEPROM Emulation event mask*/
XMC_ECAT_EVENT_WATCHDOG = ECAT_AL_EVENT_MASK_WP_D_MASK_Msk, /**< WATCHDOG process data event mask*/
XMC_ECAT_EVENT_SM0 = ECAT_AL_EVENT_MASK_SMI_0_MASK_Msk, /**< Sync Manager 0 event mask*/
XMC_ECAT_EVENT_SM1 = ECAT_AL_EVENT_MASK_SMI_1_MASK_Msk, /**< Sync Manager 1 event mask*/
XMC_ECAT_EVENT_SM2 = ECAT_AL_EVENT_MASK_SMI_2_MASK_Msk, /**< Sync Manager 2 event mask*/
XMC_ECAT_EVENT_SM3 = ECAT_AL_EVENT_MASK_SMI_3_MASK_Msk, /**< Sync Manager 3 event mask*/
XMC_ECAT_EVENT_SM4 = ECAT_AL_EVENT_MASK_SMI_4_MASK_Msk, /**< Sync Manager 4 event mask*/
XMC_ECAT_EVENT_SM5 = ECAT_AL_EVENT_MASK_SMI_5_MASK_Msk, /**< Sync Manager 5 event mask*/
XMC_ECAT_EVENT_SM6 = ECAT_AL_EVENT_MASK_SMI_6_MASK_Msk, /**< Sync Manager 6 event mask*/
XMC_ECAT_EVENT_SM7 = ECAT_AL_EVENT_MASK_SMI_7_MASK_Msk /**< Sync Manager 7 event mask*/
} XMC_ECAT_EVENT_t;
/**********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/* Anonymous structure/union guard start */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__TASKING__)
#pragma warning 586
#endif
/**
* ECAT port control data structure
*/
typedef struct XMC_ECAT_PORT_CTRL
{
union
{
struct
{
uint32_t enable_rstreq: 1; /**< Master can trigger a reset of the XMC4700 / XMC4800 (::bool) */
uint32_t: 7; /**< Reserved bits */
uint32_t latch_input0: 2; /**< Latch input 0 selection (::XMC_ECAT_PORT_LATCHIN0_t) */
uint32_t: 2; /**< Reserved bits */
uint32_t latch_input1: 2; /**< Latch input 1 selection (::XMC_ECAT_PORT_LATCHIN1_t) */
uint32_t: 2; /**< Reserved bits */
uint32_t phyaddr_offset: 5; /**< Ethernet PHY address offset, address of port 0 */
uint32_t: 1; /**< Reserved bits */
uint32_t mdio: 2; /**< Bidirectional, push-pull management data I/O line (::XMC_ETH_MAC_PORT_CTRL_MDIO_t) */
uint32_t: 8; /**< Reserved bits */
};
uint32_t raw;
} common;
union
{
struct
{
uint32_t rxd0: 2; /**< Receive data bit 0 (::XMC_ECAT_PORT0_CTRL_RXD0_t) */
uint32_t rxd1: 2; /**< Receive data bit 1 (::XMC_ECAT_PORT0_CTRL_RXD1_t) */
uint32_t rxd2: 2; /**< Receive data bit 2 (::XMC_ECAT_PORT0_CTRL_RXD2_t) */
uint32_t rxd3: 2; /**< Receive data bit 3 (::XMC_ECAT_PORT0_CTRL_RXD3_t) */
uint32_t rx_err: 2; /**< RX Error (::XMC_ECAT_PORT0_CTRL_RX_ERR_t) */
uint32_t rx_dv: 2; /**< RX Data valid (::XMC_ECAT_PORT0_CTRL_RX_DV_t) */
uint32_t rx_clk: 2; /**< RX Clock (::XMC_ECAT_PORT0_CTRL_RX_CLK_t) */
uint32_t: 2; /**< Reserved bits */
uint32_t link: 2; /**< Link status (::XMC_ECAT_PORT0_CTRL_LINK_t) */
uint32_t: 10; /**< Reserved bits */
uint32_t tx_clk: 2; /**< TX Clock (::XMC_ECAT_PORT0_CTRL_TX_CLK_t) */
uint32_t tx_shift: 2; /**< TX signal delay (::XMC_ECAT_PORT0_CTRL_TX_SHIFT_t) */
};
uint32_t raw;
} port0;
union
{
struct
{
uint32_t rxd0: 2; /**< Receive data bit 0 (::XMC_ECAT_PORT_CTRL_RXD0_t) */
uint32_t rxd1: 2; /**< Receive data bit 1 (::XMC_ECAT_PORT_CTRL_RXD1_t) */
uint32_t rxd2: 2; /**< Receive data bit 2 (::XMC_ECAT_PORT_CTRL_RXD2_t) */
uint32_t rxd3: 2; /**< Receive data bit 3 (::XMC_ECAT_PORT_CTRL_RXD3_t) */
uint32_t rx_err: 2; /**< RX Error (::XMC_ECAT_PORT_CTRL_RX_ERR_t) */
uint32_t rx_dv: 2; /**< RX Data valid (::XMC_ECAT_PORT_CTRL_RX_DV_t) */
uint32_t rx_clk: 2; /**< RX Clock (::XMC_ECAT_PORT_CTRL_RX_CLK_t) */
uint32_t: 2; /**< Reserved bits */
uint32_t link: 2; /**< Link status (::XMC_ECAT_PORT_CTRL_LINK_t) */
uint32_t: 10; /**< Reserved bits */
uint32_t tx_clk: 2; /**< TX Clock (::XMC_ECAT_PORT_CTRL_TX_CLK_t) */
uint32_t tx_shift: 2; /**< TX signal delay (::XMC_ECAT_PORT1_CTRL_TX_SHIFT_t) */
};
uint32_t raw;
} port1;
} XMC_ECAT_PORT_CTRL_t;
/**
* ECAT EEPROM configuration area data structure
*/
typedef union XMC_ECAT_CONFIG
{
struct
{
uint32_t : 8;
uint32_t : 2;
uint32_t enable_dc_sync_out : 1;
uint32_t enable_dc_latch_in : 1;
uint32_t enable_enhanced_link_p0 : 1;
uint32_t enable_enhanced_link_p1 : 1;
uint32_t : 2;
uint32_t : 16;
uint16_t sync_pulse_length; /**< Initialization value for Pulse Length of SYNC Signals register*/
uint32_t : 16;
uint16_t station_alias; /**< Initialization value for Configured Station Alias Address register */
uint16_t : 16;
uint16_t : 16;
uint16_t checksum;
};
uint32_t dword[4]; /**< Four 32 bit double word equivalent to 8 16 bit configuration area word. */
} XMC_ECAT_CONFIG_t;
/* Anonymous structure/union guard end */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__TASKING__)
#pragma warning restore
#endif
/**********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param config XMC_ECAT_CONFIG_t
* @return XMC_ECAT_STATUS_t ECAT Initialization status
*
* \par<b>Description: </b><br>
* Initialize the Ethernet MAC peripheral <br>
*
* \par
* The function sets the link speed, applies the duplex mode, sets auto-negotiation
* and loop-back settings.
*/
void XMC_ECAT_Init(XMC_ECAT_CONFIG_t *const config);
/**
* @param None
* @return None
*
* \par<b>Description: </b><br>
* Enable the EtherCAT peripheral <br>
*
* \par
* The function de-asserts the peripheral reset.
*/
void XMC_ECAT_Enable(void);
/**
* @param None
* @return None
*
* \par<b>Description: </b><br>
* Disable the EtherCAT peripheral <br>
*
* \par
* The function asserts the peripheral reset.
*/
void XMC_ECAT_Disable(void);
/**
* @param phy_addr PHY address
* @param reg_addr Register address
* @param data The destination to which the read data needs to be copied to.
*
* @return XMC_ECAT_STATUS_t EtherCAT Read PHY API return status
*
* \par<b>Description: </b><br>
* Read a PHY register <br>
*
* \par
* The function reads a PHY register. It essentially polls busy bit during max
* PHY_TIMEOUT time and reads the information into 'data' when not busy.
*/
XMC_ECAT_STATUS_t XMC_ECAT_ReadPhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);
/**
* @param phy_addr PHY address
* @param reg_addr Register address
* @param data The data to write
* @return XMC_ECAT_STATUS_t EtherCAT Write PHY API return status
*
* \par<b>Description: </b><br>
* Write a PHY register <br>
*
* \par
* The function reads a PHY register. It essentially writes the data and polls
* the busy bit until it is no longer busy.
*/
XMC_ECAT_STATUS_t XMC_ECAT_WritePhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t data);
/**
* @param port_ctrl Port control configuration
* @return None
*
* \par<b>Description: </b><br>
* Set port control configuration <br>
*
* \par
* The function sets the port control by writing the configuration into the ECAT CON register.
*
*/
__STATIC_INLINE void XMC_ECAT_SetPortControl(const XMC_ECAT_PORT_CTRL_t port_ctrl)
{
ECAT0_CON->CON = (uint32_t)port_ctrl.common.raw;
ECAT0_CON->CONP0 = (uint32_t)port_ctrl.port0.raw;
ECAT0_CON->CONP1 = (uint32_t)port_ctrl.port1.raw;
}
/**
* @param event Single or logically OR'd events specified in the enum type @refXMC_ECAT_EVENT_t
* @return None
*
* \par<b>Description: </b><br>
* Enable ECAT event(s) <br>
*
* \par
* The function can be used to enable ECAT event(s).
*/
void XMC_ECAT_EnableEvent(uint32_t event);
/**
* @param event Single or logically OR'd events specified in the enum type @refXMC_ECAT_EVENT_t
* @return None
*
* \par<b>Description: </b><br>
* Disable an ECAT event(s) <br>
*
* \par
* The function can be used to disable ECAT event(s).
*/
void XMC_ECAT_DisableEvent(uint32_t event);
/**
* @param None
* @return uint32_t Event status
*
* \par<b>Description: </b><br>
* Get event status <br>
*
* \par
* The function returns the ECAT status and interrupt status as a single word. The user
* can then check the status of the events by using an appropriate mask.
*/
uint32_t XMC_ECAT_GetEventStatus(void);
/**
* @param channel SyncManager channel number.
* @return None
*
* \par<b>Description: </b><br>
* Disables selected SyncManager channel <br>
*
* \par
* Sets bit 0 of the corresponding 0x807 register.
*/
void XMC_ECAT_DisableSyncManChannel(const uint8_t channel);
/**
* @param channel SyncManager channel number.
* @return None
*
* \par<b>Description: </b><br>
* Enables selected SyncManager channel <br>
*
* \par
* Resets bit 0 of the corresponding 0x807 register.
*/
void XMC_ECAT_EnableSyncManChannel(const uint8_t channel);
/**
* @param None
* @return uint16_t Content of register 0x220-0x221
*
* \par<b>Description: </b><br>
* Get content of AL event register <br>
*
* \par
* Get the first two bytes of the AL Event register (0x220-0x221).
*/
__STATIC_INLINE uint16_t XMC_ECAT_GetALEventRegister(void)
{
return ((uint16_t)ECAT0->AL_EVENT_REQ);
}
/**
* @param None
* @return uint16_t Content of register 0x220-0x221
*
* \par<b>Description: </b><br>
* Get content of AL event register <br>
*
* \par
* Get the first two bytes of the AL Event register (0x220-0x221).
*/
__STATIC_INLINE uint16_t XMC_ECAT_GetALEventMask(void)
{
return ((uint16_t)ECAT0->AL_EVENT_MASK);
}
/**
* @param intMask Interrupt mask (disabled interrupt shall be zero)
* @return None
*
* \par<b>Description: </b><br>
* Sets application event mask register <br>
*
* \par
* Performs a logical OR with the AL Event Mask register (0x0204 : 0x0205).
*/
__STATIC_INLINE void XMC_ECAT_SetALEventMask(uint16_t intMask)
{
ECAT0->AL_EVENT_MASK |= (uint32_t)(intMask);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* defined (ECAT) */
#endif /* XMC_ECAT_H */

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/**
* @file xmc_ecat_map.h
* @date 2016-07-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-09-09:
* - Initial
*
* 2015-07-20:
* - Added XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 and XMC_ECAT_PORT_CTRL_LATCHIN0_P9_1
*
* @endcond
*/
#ifndef XMC_ECAT_MAP_H
#define XMC_ECAT_MAP_H
/**
* ECAT PORT 0 receive data 0 line
*/
typedef enum XMC_ECAT_PORT0_CTRL_RXD0
{
XMC_ECAT_PORT0_CTRL_RXD0_P1_4 = 0U, /**< RXD0A receive data line */
XMC_ECAT_PORT0_CTRL_RXD0_P5_0 = 1U, /**< RXD0B receive data line */
XMC_ECAT_PORT0_CTRL_RXD0_P7_4 = 2U, /**< RXD0C receive data line */
} XMC_ECAT_PORT0_CTRL_RXD0_t;
/**
* ECAT PORT 0 receive data 1 line
*/
typedef enum XMC_ECAT_PORT0_CTRL_RXD1
{
XMC_ECAT_PORT0_CTRL_RXD1_P1_5 = 0U, /**< RXD1A receive data line */
XMC_ECAT_PORT0_CTRL_RXD1_P5_1 = 1U, /**< RXD1B receive data line */
XMC_ECAT_PORT0_CTRL_RXD1_P7_5 = 2U, /**< RXD1C receive data line */
} XMC_ECAT_PORT0_CTRL_RXD1_t;
/**
* ECAT PORT 0 receive data 2 line
*/
typedef enum XMC_ECAT_PORT0_CTRL_RXD2
{
XMC_ECAT_PORT0_CTRL_RXD2_P1_10 = 0U, /**< RXD2A receive data line */
XMC_ECAT_PORT0_CTRL_RXD2_P5_2 = 1U, /**< RXD2B receive data line */
XMC_ECAT_PORT0_CTRL_RXD2_P7_6 = 2U /**< RXD2C receive data line */
} XMC_ECAT_PORT0_CTRL_RXD2_t;
/**
* ECAT PORT 0 receive data 3 line
*/
typedef enum XMC_ECAT_PORT0_CTRL_RXD3
{
XMC_ECAT_PORT0_CTRL_RXD3_P1_11 = 0U, /**< RXD3A Receive data line */
XMC_ECAT_PORT0_CTRL_RXD3_P5_7 = 1U, /**< RXD3B Receive data line */
XMC_ECAT_PORT0_CTRL_RXD3_P7_7 = 2U /**< RXD3C Receive data line */
} XMC_ECAT_PORT0_CTRL_RXD3_t;
/**
* ECAT PORT 0 receive error line
*/
typedef enum XMC_ECAT_PORT0_CTRL_RX_ERR
{
XMC_ECAT_PORT0_CTRL_RX_ERR_P4_0 = 0U, /**< RX_ERRA Receive error line */
XMC_ECAT_PORT0_CTRL_RX_ERR_P2_6 = 1U, /**< RX_ERRB Receive error line */
XMC_ECAT_PORT0_CTRL_RX_ERR_P7_9 = 2U /**< RX_ERRC Receive error line */
} XMC_ECAT_PORT0_CTRL_RX_ERR_t;
/**
* ECAT PORT 0 receive clock line
*/
typedef enum XMC_ECAT_PORT0_CTRL_RX_CLK
{
XMC_ECAT_PORT0_CTRL_RX_CLK_P1_1 = 0U, /**< RX_CLKA Recevive clock */
XMC_ECAT_PORT0_CTRL_RX_CLK_P5_4 = 1U, /**< RX_CLKB Recevive clock */
XMC_ECAT_PORT0_CTRL_RX_CLK_P7_10 = 2U, /**< RX_CLKC Recevive clock */
} XMC_ECAT_PORT0_CTRL_RX_CLK_t;
/**
* ECAT PORT 0 data valid
*/
typedef enum XMC_ECAT_PORT0_CTRL_RX_DV
{
XMC_ECAT_PORT0_CTRL_RX_DV_P1_9 = 0U, /**< RX_DVA Receive data valid */
XMC_ECAT_PORT0_CTRL_RX_DV_P5_6 = 1U, /**< RX_DVB Receive data valid */
XMC_ECAT_PORT0_CTRL_RX_DV_P7_11 = 2U, /**< RX_DVC Receive data valid */
} XMC_ECAT_PORT0_CTRL_RX_DV_t;
/**
* ECAT PORT 0 link status
*/
typedef enum XMC_ECAT_PORT0_CTRL_LINK
{
XMC_ECAT_PORT0_CTRL_LINK_P4_1 = 0U, /**< LINKA Link status */
XMC_ECAT_PORT0_CTRL_LINK_P1_15 = 1U, /**< LINKB Link status */
XMC_ECAT_PORT0_CTRL_LINK_P9_10 = 2U, /**< LINKC Link status */
} XMC_ECAT_PORT0_CTRL_LINK_t;
/**
* ECAT PORT 0 transmit clock
*/
typedef enum XMC_ECAT_PORT0_CTRL_TX_CLK
{
XMC_ECAT_PORT0_CTRL_TX_CLK_P1_0 = 0U, /**< TX_CLKA transmit clock */
XMC_ECAT_PORT0_CTRL_TX_CLK_P5_5 = 1U, /**< TX_CLKB transmit clock */
XMC_ECAT_PORT0_CTRL_TX_CLK_P9_1 = 2U, /**< TX_CLKC transmit clock */
} XMC_ECAT_PORT0_CTRL_TX_CLK_t;
/**
* ECAT PORT 1 receive data 0 line
*/
typedef enum XMC_ECAT_PORT1_CTRL_RXD0
{
XMC_ECAT_PORT1_CTRL_RXD0_P0_11 = 0U, /**< RXD0A receive data line */
XMC_ECAT_PORT1_CTRL_RXD0_P14_7 = 1U, /**< RXD0B receive data line */
XMC_ECAT_PORT1_CTRL_RXD0_P8_4 = 2U, /**< RXD0C receive data line */
} XMC_ECAT_PORT1_CTRL_RXD0_t;
/**
* ECAT PORT 1 receive data 1 line
*/
typedef enum XMC_ECAT_PORT1_CTRL_RXD1
{
XMC_ECAT_PORT1_CTRL_RXD1_P0_6 = 0U, /**< RXD1A receive data line */
XMC_ECAT_PORT1_CTRL_RXD1_P14_12 = 1U, /**< RXD1B receive data line */
XMC_ECAT_PORT1_CTRL_RXD1_P8_5 = 2U, /**< RXD1C receive data line */
} XMC_ECAT_PORT1_CTRL_RXD1_t;
/**
* ECAT PORT 1 receive data 2 line
*/
typedef enum XMC_ECAT_PORT1_CTRL_RXD2
{
XMC_ECAT_PORT1_CTRL_RXD2_P0_5 = 0U, /**< RXD2A receive data line */
XMC_ECAT_PORT1_CTRL_RXD2_P14_13 = 1U, /**< RXD2B receive data line */
XMC_ECAT_PORT1_CTRL_RXD2_P8_6 = 2U /**< RXD2C receive data line */
} XMC_ECAT_PORT1_CTRL_RXD2_t;
/**
* ECAT PORT 1 receive data 3 line
*/
typedef enum XMC_ECAT_PORT1_CTRL_RXD3
{
XMC_ECAT_PORT1_CTRL_RXD3_P0_4 = 0U, /**< RXD3A Receive data line */
XMC_ECAT_PORT1_CTRL_RXD3_P14_14 = 1U, /**< RXD3B Receive data line */
XMC_ECAT_PORT1_CTRL_RXD3_P8_7 = 2U /**< RXD3C Receive data line */
} XMC_ECAT_PORT1_CTRL_RXD3_t;
/**
* ECAT PORT 1 receive error line
*/
typedef enum XMC_ECAT_PORT1_CTRL_RX_ERR
{
XMC_ECAT_PORT1_CTRL_RX_ERR_P3_5 = 0U, /**< RX_ERRA Receive error line */
XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2 = 1U, /**< RX_ERRB Receive error line */
XMC_ECAT_PORT1_CTRL_RX_ERR_P8_9 = 2U /**< RX_ERRC Receive error line */
} XMC_ECAT_PORT1_CTRL_RX_ERR_t;
/**
* ECAT PORT 1 receive clock line
*/
typedef enum XMC_ECAT_PORT1_CTRL_RX_CLK
{
XMC_ECAT_PORT1_CTRL_RX_CLK_P0_1 = 0U, /**< RX_CLKA Recevive clock */
XMC_ECAT_PORT1_CTRL_RX_CLK_P14_6 = 1U, /**< RX_CLKB Recevive clock */
XMC_ECAT_PORT1_CTRL_RX_CLK_P8_10 = 2U, /**< RX_CLKC Recevive clock */
} XMC_ECAT_PORT1_CTRL_RX_CLK_t;
/**
* ECAT PORT 1 data valid
*/
typedef enum XMC_ECAT_PORT1_CTRL_RX_DV
{
XMC_ECAT_PORT1_CTRL_RX_DV_P0_9 = 0U, /**< RX_DVA Receive data valid */
XMC_ECAT_PORT1_CTRL_RX_DV_P14_15 = 1U, /**< RX_DVB Receive data valid */
XMC_ECAT_PORT1_CTRL_RX_DV_P8_11 = 2U, /**< RX_DVC Receive data valid */
} XMC_ECAT_PORT1_CTRL_RX_DV_t;
/**
* ECAT PORT 0 link status
*/
typedef enum XMC_ECAT_PORT1_CTRL_LINK
{
XMC_ECAT_PORT1_CTRL_LINK_P3_4 = 0U, /**< LINKA Link status */
XMC_ECAT_PORT1_CTRL_LINK_P15_3 = 1U, /**< LINKB Link status */
XMC_ECAT_PORT1_CTRL_LINK_P9_11 = 2U, /**< LINKC Link status */
} XMC_ECAT_PORT1_CTRL_LINK_t;
/**
* ECAT PORT 1 transmit clock
*/
typedef enum XMC_ECAT_PORT1_CTRL_TX_CLK
{
XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10 = 0U, /**< TX_CLKA transmit clock */
XMC_ECAT_PORT1_CTRL_TX_CLK_P5_9 = 1U, /**< TX_CLKB transmit clock */
XMC_ECAT_PORT1_CTRL_TX_CLK_P9_0 = 2U, /**< TX_CLKC transmit clock */
} XMC_ECAT_PORT1_CTRL_TX_CLK_t;
/**
* ECAT management data I/O
*/
typedef enum XMC_ECAT_PORT_CTRL_MDIO
{
XMC_ECAT_PORT_CTRL_MDIO_P0_12 = 0U, /**< MDIOA management data I/O */
XMC_ECAT_PORT_CTRL_MDIO_P4_2 = 1U, /**< MDIOB management data I/O */
XMC_ECAT_PORT_CTRL_MDIO_P9_7 = 2U /**< MDIOC management data I/O */
} XMC_ECAT_PORT_CTRL_MDIO_t;
/**
* ECAT latch 0
*/
typedef enum XMC_ECAT_PORT_CTRL_LATCHIN0
{
XMC_ECAT_PORT_CTRL_LATCHIN0_P14_5 = 0U, /**< LATCH0A line */
XMC_ECAT_PORT_CTRL_LATCHIN0_9_0 = 1U, /**< LATCH0B line @deprecated Please use instead XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 */
XMC_ECAT_PORT_CTRL_LATCHIN0_P9_0 = 1U, /**< LATCH0B line */
XMC_ECAT_PORT_CTRL_LATCHIN0_ERU0_PDOUT0 = 2U, /**< LATCH0C line */
XMC_ECAT_PORT_CTRL_LATCHIN0_ERU1_PDOUT0 = 3U, /**< LATCH0D line */
} XMC_ECAT_PORT_CTRL_LATCHIN0_t;
/**
* ECAT latch 1
*/
typedef enum XMC_ECAT_PORT_CTRL_LATCHIN1
{
XMC_ECAT_PORT_CTRL_LATCHIN1_P14_4 = 0U, /**< LATCH1 A line */
XMC_ECAT_PORT_CTRL_LATCHIN1_9_1 = 1U, /**< LATCH1 B line @deprecated Please use instead XMC_ECAT_PORT_CTRL_LATCHIN1_P9_1 */
XMC_ECAT_PORT_CTRL_LATCHIN1_P9_1 = 1U, /**< LATCH1 B line */
XMC_ECAT_PORT_CTRL_LATCHIN1_ERU0_PDOUT1 = 2U, /**< LATCH1C line */
XMC_ECAT_PORT_CTRL_LATCHIN1_ERU1_PDOUT1 = 3U, /**< LATCH1D line */
} XMC_ECAT_PORT_CTRL_LATCHIN1_t;
/**
* ECAT Port 0 Manual TX Shift configuration
*/
typedef enum XMC_ECAT_PORT0_CTRL_TX_SHIFT
{
XMC_ECAT_PORT0_CTRL_TX_SHIFT_0NS = 0U, /**< ECAT Port 0 Manual TX Shift compensation 0 nanoseconds */
XMC_ECAT_PORT0_CTRL_TX_SHIFT_10NS = 1U, /**< ECAT Port 0 Manual TX Shift compensation 10 nanoseconds */
XMC_ECAT_PORT0_CTRL_TX_SHIFT_20NS = 2U, /**< ECAT Port 0 Manual TX Shift compensation 20 nanoseconds */
XMC_ECAT_PORT0_CTRL_TX_SHIFT_30NS = 3U /**< ECAT Port 0 Manual TX Shift compensation 30 nanoseconds */
} XMC_ECAT_PORT0_CTRL_TX_SHIFT_t;
/**
* ECAT Port 1 Manual TX Shift configuration
*/
typedef enum XMC_ECAT_PORT1_CTRL_TX_SHIFT
{
XMC_ECAT_PORT1_CTRL_TX_SHIFT_0NS = 0U, /**< ECAT Port 0 Manual TX Shift compensation 0 nanoseconds */
XMC_ECAT_PORT1_CTRL_TX_SHIFT_10NS = 1U, /**< ECAT Port 0 Manual TX Shift compensation 10 nanoseconds */
XMC_ECAT_PORT1_CTRL_TX_SHIFT_20NS = 2U, /**< ECAT Port 0 Manual TX Shift compensation 20 nanoseconds */
XMC_ECAT_PORT1_CTRL_TX_SHIFT_30NS = 3U /**< ECAT Port 0 Manual TX Shift compensation 30 nanoseconds */
} XMC_ECAT_PORT1_CTRL_TX_SHIFT_t;
#endif

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/**
* @file xmc_eru.h
* @date 2016-03-10
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
* - Documentation updates <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
*
* 2015-10-07:
* - Doc update for XMC_ERU_ETL_CONFIG_t field <br>
*
* 2016-03-10:
* - XMC_ERU_ETL_GetEdgeDetection() API is added to get the configured edge for event generation. <br>
*
* @endcond
*/
#ifndef XMC_ERU_H
#define XMC_ERU_H
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_common.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup ERU
* @brief Event Request Unit (ERU) driver for the XMC microcontroller family.
*
* The Event Request Unit (ERU) is a versatile multiple input event detection and processing unit.
* The ERU module can be used to expand the P-to-P connections of the device: ports-to-peripherals,
* peripherals-to-peripherals and ports-to-ports. It also offers configurable logic, that allows the generation of
* triggers, pattern detection and real-time signal monitoring.
*
* @image html "eru_overview.png"
*
* The driver is divided into two sections:
* \par Event trigger logic (ERU_ETL):
* This section of the LLD provides the configuration structure XMC_ERU_ETL_CONFIG_t and the initialization function
* XMC_ERU_ETL_Init().\n
* It can be used to:
* -# Select one out of two inputs (A and B). For each of these two inputs, a vector of 4 possible signals is available.
* (XMC_ERU_ETL_SetSource())
* -# Logically combine the two input signals to a common trigger. (XMC_ERU_ETL_SetSource())
* -# Define the transition (edge selection, or by software) that leads to a trigger event and can also store this status.
* (XMC_ERU_ETL_SetEdgeDetection() and XMC_ERU_ETL_SetStatusFlag())
* -# Distribute the events and status flags to the output channels. (XMC_ERU_ETL_EnableOutputTrigger())
*
* \par Output gating unit (ERU_OGU):
* This section of the LLD provides the provides the configuration structure XMC_ERU_OGU_CONFIG_t and the initialization
* function XMC_ERU_ETL_OGU_Init().
* It can be used to:
* -# Combine the trigger events and status information and gates the output depending on a gating signal.
* (XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_DisablePeripheralTrigger(), XMC_ERU_OGU_SetServiceRequestMode())
* @{
*/
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#if defined(ERU0)
#define XMC_ERU0 ((XMC_ERU_t *) ERU0_BASE) /**< ERU module 0 */
#endif
#if defined(ERU1)
#define XMC_ERU1 ((XMC_ERU_t *) ERU1_BASE) /**< ERU module 1, only available in XMC4 family */
#endif
#if UC_FAMILY == XMC1
#include "xmc1_eru_map.h"
#endif
#if UC_FAMILY == XMC4
#include "xmc4_eru_map.h"
#endif
#if defined(XMC_ERU0) && defined(XMC_ERU1)
#define XMC_ERU_CHECK_MODULE_PTR(PTR) (((PTR)== XMC_ERU0) | ((PTR)== XMC_ERU1))
#elif defined(XMC_ERU0)
#define XMC_ERU_CHECK_MODULE_PTR(PTR) (((PTR)== XMC_ERU0))
#elif defined(XMC_ERU1)
#define XMC_ERU_CHECK_MODULE_PTR(PTR) (((PTR)== XMC_ERU0))
#endif
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/**
* Defines input signal for path A of ERSx(Event request source, x = [0 to 3]) unit.
* @image html "eru_input_a.png" "ETLx Input A selection"
*/
typedef enum XMC_ERU_ETL_INPUT_A
{
XMC_ERU_ETL_INPUT_A0 = 0x0U, /**< input A0 is selected */
XMC_ERU_ETL_INPUT_A1 = 0x1U, /**< input A1 is selected */
XMC_ERU_ETL_INPUT_A2 = 0x2U, /**< input A2 is selected */
XMC_ERU_ETL_INPUT_A3 = 0x3U /**< input A3 is selected */
} XMC_ERU_ETL_INPUT_A_t;
/**
* Defines input signal for path B of ERSx(Event request source, x = [0 to 3]) unit.
* @image html "eru_input_b.png" "ETLx Input B selection"
*/
typedef enum XMC_ERU_ETL_INPUT_B
{
XMC_ERU_ETL_INPUT_B0 = 0x0U, /**< input B0 is selected */
XMC_ERU_ETL_INPUT_B1 = 0x1U, /**< input B1 is selected */
XMC_ERU_ETL_INPUT_B2 = 0x2U, /**< input B2 is selected */
XMC_ERU_ETL_INPUT_B3 = 0x3U /**< input B3 is selected */
} XMC_ERU_ETL_INPUT_B_t;
/**
* Defines input path combination along with polarity for event generation by ERSx(Event request source) unit to
* ETLx(Event trigger logic),x = [0 to 3] unit.
* @image html "eru_input_trigger.png" "ETLx input trigger signal generation"
*/
typedef enum XMC_ERU_ETL_SOURCE
{
XMC_ERU_ETL_SOURCE_A = 0x0U, /**< select (A) path as a event source */
XMC_ERU_ETL_SOURCE_B = 0x1U, /**< select (B) path as a event source */
XMC_ERU_ETL_SOURCE_A_OR_B = 0x2U, /**< select (A <b>OR</b> B) path as a event source */
XMC_ERU_ETL_SOURCE_A_AND_B = 0x3U, /**< select (A <b>AND</b> B) path as a event source */
XMC_ERU_ETL_SOURCE_NOT_A = 0x4U, /**< select (inverted A) path as a event source */
XMC_ERU_ETL_SOURCE_NOT_A_OR_B = 0x6U, /**< select (inverted A <b>OR</b> B) path as a event source */
XMC_ERU_ETL_SOURCE_NOT_A_AND_B = 0x7U, /**< select (inverted A <b>AND</b> B) path as a event source */
XMC_ERU_ETL_SOURCE_NOT_B = 0x9U, /**< select (inverted B) path as a event source */
XMC_ERU_ETL_SOURCE_A_OR_NOT_B = 0xaU, /**< select (A <b>OR</b> inverted B) path as a event source */
XMC_ERU_ETL_SOURCE_A_AND_NOT_B = 0xbU, /**< select (A <b>AND</b> inverted B) path as a event source */
XMC_ERU_ETL_SOURCE_NOT_A_OR_NOT_B = 0xeU, /**< select (inverted A <b>OR</b> inverted B) path as a event
source */
XMC_ERU_ETL_SOURCE_NOT_A_AND_NOT_B = 0xfU /**< select (inverted A <b>AND</b> inverted B) path as a event
source */
} XMC_ERU_ETL_SOURCE_t;
/**
* Defines trigger edge for the event generation by ETLx (Event Trigger Logic, x = [0 to 3]) unit, by getting the signal
* from ERSx(Event request source, x = [0 to 3]) unit.
*/
typedef enum XMC_ERU_ETL_EDGE_DETECTION
{
XMC_ERU_ETL_EDGE_DETECTION_DISABLED = 0U, /**< no event enabled */
XMC_ERU_ETL_EDGE_DETECTION_RISING = 1U, /**< detection of rising edge generates the event */
XMC_ERU_ETL_EDGE_DETECTION_FALLING = 2U, /**< detection of falling edge generates the event */
XMC_ERU_ETL_EDGE_DETECTION_BOTH = 3U /**< detection of either edges generates the event */
} XMC_ERU_ETL_EDGE_DETECTION_t;
/**
* Defines Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by
* ETLx(Event Trigger Logic, x = [0 to 3]) unit.
* @note Generation of output trigger pulse need to be enabled @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t
* @image html "eru_connection_matrix.png" "ERU_ETL ERU_OGU Connection matrix"
*/
typedef enum XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL
{
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL0 = 0U, /**< Event from input ETLx triggers output OGU0 */
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL1 = 1U, /**< Event from input ETLx triggers output OGU1 */
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL2 = 2U, /**< Event from input ETLx triggers output OGU2 */
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL3 = 3U, /**< Event from input ETLx triggers output OGU3 */
} XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t;
/**
* Defines generation of the trigger pulse by ETLx(Event Trigger Logic, x = [0 to 3]) unit.
* Use type XMC_ERU_ETL_OUTPUT_TRIGGER_t for this enum.
*/
typedef enum XMC_ERU_ETL_OUTPUT_TRIGGER
{
XMC_ERU_ETL_OUTPUT_TRIGGER_DISABLED = 0U, /**< trigger pulse generation disabled */
XMC_ERU_ETL_OUTPUT_TRIGGER_ENABLED = 1U /**< trigger pulse generation enabled */
} XMC_ERU_ETL_OUTPUT_TRIGGER_t;
/**
* Defines status flag reset mode generated by ETLx(Event Trigger Logic, x = [0 to 3]) unit.
* Use type XMC_ERU_ETL_STATUS_FLAG_MODE_t for this enum.
*/
typedef enum XMC_ERU_ETL_STATUS_FLAG_MODE
{
XMC_ERU_ETL_STATUS_FLAG_MODE_SWCTRL = 0U, /**< Status flag is in sticky mode. Retain the same state until
cleared by software. In case of pattern match this mode
is used. */
XMC_ERU_ETL_STATUS_FLAG_MODE_HWCTRL = 1U /**< Status flag is in non-sticky mode. Automatically cleared by
the opposite edge detection.\n
eg. if positive edge is selected as trigger event, for the
negative edge event the status flag is cleared. */
} XMC_ERU_ETL_STATUS_FLAG_MODE_t;
/**
* Defines pattern detection feature to be enabled or not in OGUy(Output gating unit, y = [0 to 3]).
*
*/
typedef enum XMC_ERU_OGU_PATTERN_DETECTION
{
XMC_ERU_OGU_PATTERN_DETECTION_DISABLED = 0U, /**< Pattern match is disabled */
XMC_ERU_OGU_PATTERN_DETECTION_ENABLED = 1U /**< Pattern match is enabled, the selected status flags of
ETLx(Event Trigger Logic, x = [0 to 3]) unit, are
used in pattern detection. */
} XMC_ERU_OGU_PATTERN_DETECTION_t;
/**
* Defines the inputs for Pattern detection. The configured status flag signal from the ETLx(Event Trigger Logic,
* x = [0 to 3]) unit indicates the pattern to be detected.
*/
typedef enum XMC_ERU_OGU_PATTERN_DETECTION_INPUT
{
XMC_ERU_OGU_PATTERN_DETECTION_INPUT0 = 1U, /**< Status flag ETL0, participating in pattern match */
XMC_ERU_OGU_PATTERN_DETECTION_INPUT1 = 2U, /**< Status flag ETL1, participating in pattern match */
XMC_ERU_OGU_PATTERN_DETECTION_INPUT2 = 4U, /**< Status flag ETL0, participating in pattern match */
XMC_ERU_OGU_PATTERN_DETECTION_INPUT3 = 8U /**< Status flag ETL0, participating in pattern match */
} XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t;
/**
* Defines peripheral trigger signal for event generation. Based on the selected peripheral for event generation,
* the trigger signal is mapped.
*/
typedef enum XMC_ERU_OGU_PERIPHERAL_TRIGGER
{
XMC_ERU_OGU_PERIPHERAL_TRIGGER1 = 1U, /**< OGUy1 signal is mapped for event generation */
XMC_ERU_OGU_PERIPHERAL_TRIGGER2 = 2U, /**< OGUy2 signal is mapped for event generation */
XMC_ERU_OGU_PERIPHERAL_TRIGGER3 = 3U /**< OGUy3 signal is mapped for event generation */
} XMC_ERU_OGU_PERIPHERAL_TRIGGER_t;
/**
* Defines the gating scheme for service request generation. In later stage of the OGUy(Output gating unit,
* y = [0 to 3]) based on the gating scheme selected ERU_GOUTy(gated output signal) output is defined.
* @image html "interrupt_gating_signal.png" "Interrupt gating signal"
*/
typedef enum XMC_ERU_OGU_SERVICE_REQUEST
{
XMC_ERU_OGU_SERVICE_REQUEST_DISABLED = 0U, /**< Service request blocked, ERUx_GOUTy = 0 */
XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER = 1U, /**< Service request generated enabled, ERUx_GOUTy = 1 */
XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MATCH = 2U, /**< Service request generated on trigger
event and input pattern match,
ERUx_GOUTy = ~pattern matching result*/
XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MISMATCH = 3U/**< Service request generated on trigger
event and input pattern mismatch,
ERUx_GOUTy = pattern matching result*/
} XMC_ERU_OGU_SERVICE_REQUEST_t;
/*********************************************************************************************************************
* DATA STRUCTURES
********************************************************************************************************************/
/*Anonymous structure/union guard start*/
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined(__TASKING__)
#pragma warning 586
#endif
/**
* ERU module
*/
typedef struct {
union {
__IO uint32_t EXISEL;
struct {
__IO uint32_t EXS0A : 2;
__IO uint32_t EXS0B : 2;
__IO uint32_t EXS1A : 2;
__IO uint32_t EXS1B : 2;
__IO uint32_t EXS2A : 2;
__IO uint32_t EXS2B : 2;
__IO uint32_t EXS3A : 2;
__IO uint32_t EXS3B : 2;
} EXISEL_b;
};
__I uint32_t RESERVED0[3];
union {
__IO uint32_t EXICON[4];
struct {
__IO uint32_t PE : 1;
__IO uint32_t LD : 1;
__IO uint32_t ED : 2;
__IO uint32_t OCS : 3;
__IO uint32_t FL : 1;
__IO uint32_t SS : 4;
__I uint32_t RESERVED1 : 20;
} EXICON_b[4];
};
union {
__IO uint32_t EXOCON[4];
struct {
__IO uint32_t ISS : 2;
__IO uint32_t GEEN : 1;
__I uint32_t PDR : 1;
__IO uint32_t GP : 2;
uint32_t : 6;
__IO uint32_t IPEN : 4;
__I uint32_t RESERVED2 : 16;
} EXOCON_b[4];
};
} XMC_ERU_t;
/**
* \if XMC4
* Structure for initializing ERUx_ETLy (x = [0..1], y = [0..4]) module.
* \endif
* \if XMC1
* Structure for initializing ERUx_ETLy (x = [0], y = [0..4]) module.
* \endif
*/
typedef struct XMC_ERU_ETL_CONFIG
{
union
{
uint32_t input; /**< While configuring the bit fields, the values have to be shifted according to the position */
struct
{
uint32_t input_a: 2; /**< Configures input A. Refer @ref XMC_ERU_ETL_INPUT_A_t for valid values */
uint32_t input_b: 2; /**< Configures input B. Refer @ref XMC_ERU_ETL_INPUT_B_t for valid values */
uint32_t : 28;
};
};
union
{
uint32_t raw;
struct
{
uint32_t enable_output_trigger: 1; /**< Enables the generation of trigger pulse(PE), for the configured edge
detection. This accepts boolean values as input. */
uint32_t status_flag_mode: 1; /**< Enables the status flag auto clear(LD), for the opposite edge of the
configured event edge. This accepts boolean values as input. */
uint32_t edge_detection: 2; /**< Configure the event trigger edge(FE, RE).
Refer @ref XMC_ERU_ETL_EDGE_DETECTION_t for valid values. */
uint32_t output_trigger_channel: 3; /**< Output channel select(OCS) for ETLx output trigger pulse.
Refer @ref XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t for valid values. */
uint32_t : 1;
uint32_t source: 4; /**< Input path combination along with polarity for event generation.
Refer @ref XMC_ERU_ETL_SOURCE_t for valid values. */
uint32_t : 20;
};
};
} XMC_ERU_ETL_CONFIG_t;
/**
* \if XMC4
* Structure for initializing ERUx_OGUy (x = [0..1], y = [0..4]) module.
* \endif
* \if XMC1
* Structure for initializing ERUx_OGUy (x = [0], y = [0..4]) module.
* \endif
*/
typedef union XMC_ERU_OGU_CONFIG
{
uint32_t raw;
struct
{
uint32_t peripheral_trigger: 2; /**< peripheral trigger(ISS) input selection.
Refer @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t for valid values. */
uint32_t enable_pattern_detection: 1; /**< Enable generation of(GEEN) event for pattern detection result change.
This accepts boolean values as input. */
uint32_t : 1;
uint32_t service_request: 2; /**< Gating(GP) on service request generation for pattern detection result.
Refer @ref XMC_ERU_OGU_SERVICE_REQUEST_t for valid values. */
uint32_t : 6;
uint32_t pattern_detection_input: 4; /**< Enable input for the pattern detection(IPENx, x = [0 to 3]).
Refer @ref XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t for valid values.
<b>OR</b> combination of the enum items given as input */
uint32_t : 16;
};
} XMC_ERU_OGU_CONFIG_t;
/*Anonymous structure/union guard end */
#if defined(__CC_ARM)
#pragma pop
#elif defined(__TASKING__)
#pragma warning restore
#endif
/*********************************************************************************************************************
* API PROTOTYPES
********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC4
* If ERU1 module is selected, it enables clock and releases reset.<br>
* \endif
* \if XMC1
* Abstract API, not mandatory to call. <br>
* \endif
* \par
* This API is called by XMC_ERU_ETL_Init() or XMC_ERU_OGU_Init() and therefore no need to call it explicitly during
* initialization sequence. Call this API to enable ERU1 module once again if the module is disabled by calling
* XMC_ERU_Disable(). For ERU0 module clock gating and reset features are not available.
*
* \par<b>Note:</b><br>
* \if XMC4
* 1. Required to configure ERU1 module again after calling XMC_ERU_Disable(). Since the all the registers are
* reset with default values.
* \endif
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_Init(), XMC_ERU_OGU_Init(), XMC_ERU_Disable().
*/
void XMC_ERU_Enable(XMC_ERU_t *const eru);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC4
* Disables clock and releases reset for ERU1 module.<br>
* \endif
* \if XMC1
* Abstract API, not mandatory to call. <br>
* \endif
*
* \par<b>Note:</b><br>
* \if XMC4
* 1. Required to configure ERU1 module again after calling XMC_ERU_ETL_Init() or XMC_ERU_OGU_Init(). Since the all the
* registers are reset with default values.
* \endif
* \par<b>Related APIs:</b><BR>
* XMC_ERU_Enable()
*/
void XMC_ERU_Disable(XMC_ERU_t *const eru);
/* ERU_ETL APIs */
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_ETLx(Event trigger logic unit) channel
* Range : [0 to 3]
* @param config pointer to a constant ERU_ETLx configuration data structure.
* Refer data structure XMC_ERU_ETL_CONFIG_t for detail.
*
* @return None
*
* <b>Description:</b><br>
* Initializes the selected ERU_ETLx \a channel with the \a config structure.<br>
*
* Invokes XMC_ERU_Enable() to enable \a eru module clock. Then configures
* <ul>
* <li>Input signal for path A and Path B,</li>
* <li>Trigger pulse generation,</li>
* <li>status flag clear mode,</li>
* <li>Event Trigger edge,</li>
* <li>Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse,</li>
* <li>input path combination along with polarity for event generation</li>
* </ul>.
*/
void XMC_ERU_ETL_Init(XMC_ERU_t *const eru, const uint8_t channel, const XMC_ERU_ETL_CONFIG_t *const config);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3]
* @param input_a input signal for path A of ERSx(Event request source, x = [0 to 3]) unit.\n
* Refer XMC_ERU_ETL_INPUT_A_t for valid value or xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of
* the input is done based on selected signal.\n
* e.g: ERU0_ETL3_INPUTA_P2_7.
* @param input_b input signal for path B of ERSx(Event request source, x = [0 to 3]) unit.\n
* Refer XMC_ERU_ETL_INPUT_B_t for valid value or xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of
* the input is done based on selected signal.\n
* e.g: ERU0_ETL0_INPUTB_P2_0.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures the event source for path A and path B in with selected \a input_a and \a input_b respectively.<br>
* \par
* These values are set during initialization in XMC_ERU_ETL_Init(). Call this to change the input, as needed later in
* the program. According to the ports/peripheral selected, the event source has to be changed.
*/
void XMC_ERU_ETL_SetInput(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_INPUT_A_t input_a,
const XMC_ERU_ETL_INPUT_B_t input_b);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3]
* @param source input path combination along with polarity for event generation by ERSx(Event request source) unit.
* Refer @ref XMC_ERU_ETL_SOURCE_t enum for valid input values.
*
* @return None
*
* \par<b>Description:</b><br>
* Select input path combination along with polarity for event generation by setting (SS, NA, NB) bits in
* ERSx(Event request source) unit <br>
* \par
* The signal ERSxO is generated from the selection and this is connected to ETLx(Event trigger logic,
* x = [0 to 3]) for further action. These values are set during initialization in XMC_ERU_ETL_Init(). Call this to
* change the source, as needed later in the program.
*/
void XMC_ERU_ETL_SetSource(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_SOURCE_t source);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3]
* @param edge_detection event trigger edge.
* Refer @ref XMC_ERU_ETL_EDGE_DETECTION_t enum for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Configure event trigger edge/s by setting (RE, FE) bits of EXICONx(x = [0 to 3]) register.<br>
* \par
* Rising edge, falling edge or either edges can be selected to generate the event.These values are set during
* initialization in XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program.
*/
void XMC_ERU_ETL_SetEdgeDetection(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_EDGE_DETECTION_t edge_detection);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3]
*
* @return XMC_ERU_ETL_EDGE_DETECTION_t indicate which egde/s is configured for event generation
*
* \par<b>Description:</b><br>
* Return event trigger edge/s by reading (RE, FE) bits of EXICONx(x = [0 to 3]) register.<br>
* \par
* Rising edge, falling edge or either edges can be selected to generate the event.
* Call this to get the configured trigger edge. */
XMC_ERU_ETL_EDGE_DETECTION_t XMC_ERU_ETL_GetEdgeDetection(XMC_ERU_t *const eru,
const uint8_t channel);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3]
*
* @return None
*
* \par<b>Description:</b><br>
* Set the status flag bit(FL) in EXICONx(x = [0 to 3]).<br>
* \par
* The status flag indicates that the configured event has occurred. This status flag is used in Pattern match detection
* by OGUy(Output gating unit, y = [0 to 3]).
* \par
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_ClearStatusFlag(), XMC_ERU_ETL_GetStatusFlag()
*/
__STATIC_INLINE void XMC_ERU_ETL_SetStatusFlag(XMC_ERU_t *const eru, const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_ETL_SetStatusFlag:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_SetStatusFlag:Invalid Channel Number", (channel < 4U));
eru->EXICON_b[channel].FL = true;
}
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3]
*
* @return None
*
* \par<b>Description:</b><br>
* Set the status flag bit(FL) in EXICONx(x = [0 to 3]).<br>
* \par
* If auto clear of the status flag is not enabled by detection of the opposite edge of the event edge, this API clears
* the Flag. SO that next event is considered as new event.
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_SetStatusFlag(), XMC_ERU_ETL_GetStatusFlag()
*/
__STATIC_INLINE void XMC_ERU_ETL_ClearStatusFlag(XMC_ERU_t *const eru, const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_ETL_ClearStatusFlag:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_ClearStatusFlag:Invalid Channel Number", (channel < 4U));
eru->EXICON_b[channel].FL = false;
}
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3].
*
* @return uint32_t Current state of the status flag bit(FL). Result is in 32-bit format.
*
* \par<b>Description:</b><br>
* Returns status flag state of \a channel.
* \par
* The function can typically be used to clear the status flag using software, when auto clear is not enabled.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_SetStatusFlag(), XMC_ERU_ETL_ClearStatusFlag()
*/
__STATIC_INLINE uint32_t XMC_ERU_ETL_GetStatusFlag(XMC_ERU_t *const eru, const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_ETL_GetStatusFlag:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_GetStatusFlag:Invalid Channel Number", (channel < 4U));
return (uint32_t)eru->EXICON_b[channel].FL;
}
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3].
* @param mode Set whether status flag has to be cleared by software or hardware.
* Refer @ref XMC_ERU_ETL_STATUS_FLAG_MODE_t for valid value.
*
* @return None
*
* \par<b>Description:</b><br>
* Set the mode for status flag mode by setting (LD) bit in EXICONx(x = \a channel) register.<br>
* \par
* If SWCTRL is selected, status flag has to be cleared by software. This is typically used for pattern match detection.
* If HWCTRL is selected, status flag is cleared by hardware. If Positive edge is selected as event edge, for negative
* edge status flag is cleared and vice versa.This is typically used for continuous event detection.These values are set
* during initialization in XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_ClearStatusFlag(), XMC_ERU_ETL_GetStatusFlag()
*/
void XMC_ERU_ETL_SetStatusFlagMode(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_STATUS_FLAG_MODE_t mode);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3].
* @param trigger Output Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse
* Refer @ref XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t for valid value.
*
* @return None
*
* \par<b>Description:</b><br>
* Configure which Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by
* ETLx(Event Trigger Logic, x = \a channel) by setting (OCS and PE) bit fields.
* \par
* The trigger pulse is generated for one clock pulse along with the flag status update. This is typically used to
* trigger the ISR for the external events. The configured OGUy(Output gating unit y = [0 to 3]), generates the event
* based on the trigger pulse.If output trigger pulse generation is disabled by XMC_ERU_ETL_DisableOutputTrigger(),
* XMC_ERU_ETL_EnableOutputTrigger() can called to reconfigure. These values are set during initialization in
* XMC_ERU_ETL_Init(). Call this to change the trigger edge, as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_DisableOutputTrigger()
*/
void XMC_ERU_ETL_EnableOutputTrigger(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t trigger);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address.
* @param channel ERU_ETLx(Event trigger logic unit) channel.
* Range : [0 to 3].
*
* @return None
*
* \par<b>Description:</b><br>
* Disables the trigger pulse generation by clearing the (PE) of the EXICONx(x = \a channel).
* \par
* Typically this can used when only pattern match is being used for event generation.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_ETL_EnableOutputTrigger()
*/
void XMC_ERU_ETL_DisableOutputTrigger(XMC_ERU_t *const eru, const uint8_t channel);
/* ERU_OGU APIs */
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
* @param config pointer to constant ERU_OGUy configuration data structure.
* Refer data structure XMC_ERU_OGU_CONFIG_t for detail.
*
* @return None
*
* <b>Description:</b><br>
* Initializes the selected ERU_OGUy \a channel with the \a config structure.<br>
*
* Invokes XMC_ERU_Enable() to enable \a eru module clock. Then configures
* <ul>
* <li>Pattern detection,</li>
* <li>Peripheral trigger input,</li>
* <li>Gating for service request generation</li>
* </ul>.
*/
void XMC_ERU_OGU_Init(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_CONFIG_t *const config);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
* @param input ERU_ETLx(x = [0 to 3]), for pattern match detection.
* Refer @ref XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t for valid values. Logical <b>OR</b> combination of the
* enum items can be passed as the input.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures ERU_ETLx(x = [0 to 3]) for pattern match detection by setting IPENx(x = [0 to 3]) and GEEN bits.
* \par
* These bits are dedicated to each channel of the ERU_ETLx(x = [0 to 3]). These values are set during initialization in
* XMC_ERU_OGU_Init(). Call this to change the pattern, as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_OGU_DisablePatternDetection(), XMC_ERU_OGU_GetPatternDetectionStatus()
*/
void XMC_ERU_OGU_EnablePatternDetection(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t input);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
*
* @return None
*
* \par<b>Description:</b><br>
* Disable the pattern detection by clearing (GEEN) bit.
* \par
* Typically XMC_ERU_OGU_DisablePatternDetection is used when events has to be generated peripheral triggers.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_GetPatternDetectionStatus()
*/
void XMC_ERU_OGU_DisablePatternDetection(XMC_ERU_t *const eru, const uint8_t channel);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
*
* @return uint32_t returns the pattern match result. Result is in 32-bit format.
*
* \par<b>Description:</b><br>
* This API returns the pattern match result by reading (PDR) bit.
* \par
* \par<b>Related APIs:</b><BR>
* XMC_ERU_OGU_EnablePatternDetection(), XMC_ERU_OGU_DisablePatternDetection()
*/
__STATIC_INLINE uint32_t XMC_ERU_OGU_GetPatternDetectionStatus(XMC_ERU_t *const eru,
const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_OGU_GetPatternDetectionStatus:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_GetPatternDetectionStatus:Invalid Channel Number", (channel < 4U));
return (uint32_t)eru->EXOCON_b[channel].PDR;
}
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
* @param peripheral_trigger which peripheral trigger signal is used for event generation.
* Refer @ref XMC_ERU_OGU_PERIPHERAL_TRIGGER_t for the valid values, or
xmc1_eru_map.h/xmc4_eru_map.h file where the mapping of the peripheral input is done based
on input. e.g: ERU0_OGU0_PERIPHERAL_TRIGGER_CCU40_SR0.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures peripheral trigger input, by setting (ISS) bit.
* \par
* Based on the peripheral the input signal has to be selected. These values are set during initialization in
* XMC_ERU_OGU_Init(). Call this to change the input, as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_OGU_DisablePeripheralTrigger()
*/
void XMC_ERU_OGU_EnablePeripheralTrigger(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_PERIPHERAL_TRIGGER_t peripheral_trigger);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
*
* @return None
*
* \par<b>Description:</b><br>
* Disables event generation based on peripheral trigger by clearing (ISS) bit.
* \par
* This is typically used when peripheral trigger is no longer need. After calling
* XMC_ERU_OGU_DisablePeripheralTrigger(), XMC_ERU_OGU_EnablePeripheralTrigger() has to be called to reconfigure the
* signals again.
*
* \par<b>Related APIs:</b><BR>
* XMC_ERU_OGU_EnablePeripheralTrigger()
*/
void XMC_ERU_OGU_DisablePeripheralTrigger(XMC_ERU_t *const eru,
const uint8_t channel);
/**
* @param eru A constant pointer to XMC_ERU_t, pointing to the ERU base address
* @param channel ERU_OGUy(Output gating unit) channel
* Range : [0 to 3]
* @param mode gating scheme for service request generation.
* Refer @ref XMC_ERU_OGU_SERVICE_REQUEST_t for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures the gating scheme for service request generation by setting (GP) bit.<br>
* \par
* Typically this function is used to change the service request generation scheme. These values are set during
* initialization in XMC_ERU_OGU_Init(). Call this to change the gating mode, as needed later in the program.
*
*/
void XMC_ERU_OGU_SetServiceRequestMode(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_SERVICE_REQUEST_t mode);
#ifdef __cplusplus
}
#endif
/**
* @} (end addtogroup ERU)
*/
/**
* @} (end addtogroup XMClib)
*/
#endif /* XMC_ERU_H */

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/**
* @file xmc_eth_mac_map.h
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-06-20:
* - Initial <br>
*
* @endcond
*/
#ifndef XMC_ETH_MAC_MAP_H
#define XMC_ETH_MAC_MAP_H
/**
* ETH MAC interface mode
*/
typedef enum XMC_ETH_MAC_PORT_CTRL_MODE
{
XMC_ETH_MAC_PORT_CTRL_MODE_MII = 0x0U, /**< MII mode */
XMC_ETH_MAC_PORT_CTRL_MODE_RMII = 0x1U /**< RMII mode */
} XMC_ETH_MAC_PORT_CTRL_MODE_t;
/**
* ETH MAC receive data 0 line
*/
typedef enum XMC_ETH_MAC_PORT_CTRL_RXD0
{
XMC_ETH_MAC_PORT_CTRL_RXD0_P2_2 = 0U, /**< RXD0A receive data line */
XMC_ETH_MAC_PORT_CTRL_RXD0_P0_2 = 1U, /**< RXD0B receive data line */
XMC_ETH_MAC_PORT_CTRL_RXD0_P14_8 = 2U, /**< RXD0C receive data line */
XMC_ETH_MAC_PORT_CTRL_RXD0_P5_0 = 3U /**< RXD0D receive data line */
} XMC_ETH_MAC_PORT_CTRL_RXD0_t;
/**
* ETH MAC receive data 1 line
*/
typedef enum XMC_ETH_MAC_PORT_CTRL_RXD1
{
XMC_ETH_MAC_PORT_CTRL_RXD1_P2_3 = 0U, /**< RXD1A receive data line */
XMC_ETH_MAC_PORT_CTRL_RXD1_P0_3 = 1U, /**< RXD1B receive data line */
XMC_ETH_MAC_PORT_CTRL_RXD1_P14_9 = 2U, /**< RXD1C receive data line */
XMC_ETH_MAC_PORT_CTRL_RXD1_P5_1 = 3U /**< RXD1D receive data line */
} XMC_ETH_MAC_PORT_CTRL_RXD1_t;
/**
* ETH MAC receive data 2 line
*/
typedef enum XMC_ETH_MAC_PORT_CTRL_RXD2
{
XMC_ETH_MAC_PORT_CTRL_RXD2_P5_8 = 0U, /**< RXD2A receive data line */
XMC_ETH_MAC_PORT_CTRL_RXD2_P6_4 = 1U /**< RXD2B receive data line */
} XMC_ETH_MAC_PORT_CTRL_RXD2_t;
/**
* ETH MAC receive data 3 line
*/
typedef enum XMC_ETH_MAC_PORT_CTRL_RXD3
{
XMC_ETH_MAC_PORT_CTRL_RXD3_P5_9 = 0U, /**< RXD3A Receive data line */
XMC_ETH_MAC_PORT_CTRL_RXD3_P6_3 = 1U /**< RXD3B Receive data line */
} XMC_ETH_MAC_PORT_CTRL_RXD3_t;
/**
* ETH MAC PHY clock
*/
typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_RMII
{
XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P2_1 = 0U, /**< XMC_ETH_RMIIA PHY clock */
XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P0_0 = 1U, /**< XMC_ETH_RMIIB PHY clock */
XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P15_8 = 2U, /**< XMC_ETH_RMIIC PHY clock */
XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P6_5 = 3U /**< XMC_ETH_RMIID PHY clock */
} XMC_ETH_MAC_PORT_CTRL_CLK_RMII_t;
/**
* ETH MAC carrier sense data valid
*/
typedef enum XMC_ETH_MAC_PORT_CTRL_CRS_DV
{
XMC_ETH_MAC_PORT_CTRL_CRS_DV_P2_5 = 0U, /**< XMC_ETH_CRS_DVA carrier sense data valid */
XMC_ETH_MAC_PORT_CTRL_CRS_DV_P0_1 = 1U, /**< XMC_ETH_CRS_DVB carrier sense data valid */
XMC_ETH_MAC_PORT_CTRL_CRS_DV_P15_9 = 2U, /**< XMC_ETH_CRS_DVC carrier sense data valid */
XMC_ETH_MAC_PORT_CTRL_CRS_DV_P5_2 = 3U /**< XMC_ETH_CRS_DVD carrier sense data valid */
} XMC_ETH_MAC_PORT_CTRL_CRS_DV_t;
/**
* ETH MAC carrier sense
*/
typedef enum XMC_ETH_MAC_PORT_CTRL_CRS
{
XMC_ETH_MAC_PORT_CTRL_CRS_P5_11 = 0U, /**< XMC_ETH_CRSA carrier sense */
XMC_ETH_MAC_PORT_CTRL_CRS_P5_4 = 3U /**< XMC_ETH_CRSD carrier sense */
} XMC_ETH_MAC_PORT_CTRL_CRS_t;
/**
* ETH MAC receive error
*/
typedef enum XMC_ETH_MAC_PORT_CTRL_RXER
{
XMC_ETH_MAC_PORT_CTRL_RXER_P2_4 = 0U, /**< XMC_ETH_RXERA carrier sense */
XMC_ETH_MAC_PORT_CTRL_RXER_P0_11 = 1U, /**< XMC_ETH_RXERB carrier sense */
XMC_ETH_MAC_PORT_CTRL_RXER_P5_3 = 3U /**< XMC_ETH_RXERD carrier sense */
} XMC_ETH_MAC_PORT_CTRL_RXER_t;
/**
* ETH MAC collision detection
*/
typedef enum XMC_ETH_MAC_PORT_CTRL_COL
{
XMC_ETH_MAC_PORT_CTRL_COL_P2_15 = 0U, /**< XMC_ETH_COLA collision detection */
XMC_ETH_MAC_PORT_CTRL_COL_P5_5 = 3U /**< XMC_ETH_COLD collision detection */
} XMC_ETH_MAC_PORT_CTRL_COL_t;
/**
* ETH PHY transmit clock
*/
typedef enum XMC_ETH_MAC_PORT_CTRL_CLK_TX
{
XMC_ETH_MAC_PORT_CTRL_CLK_TX_P5_10 = 0U, /**< XMC_ETH_CLK_TXA PHY transmit clock */
XMC_ETH_MAC_PORT_CTRL_CLK_TX_P6_6 = 1U /**< XMC_ETH_CLK_TXB PHY transmit clock */
} XMC_ETH_MAC_PORT_CTRL_CLK_TX_t;
/**
* ETH management data I/O
*/
typedef enum XMC_ETH_MAC_PORT_CTRL_MDIO
{
XMC_ETH_MAC_PORT_CTRL_MDIO_P0_9 = 0U, /**< XMC_ETH_MDIOA management data I/O */
XMC_ETH_MAC_PORT_CTRL_MDIO_P2_0 = 1U, /**< XMC_ETH_MDIOB management data I/O */
XMC_ETH_MAC_PORT_CTRL_MDIO_P1_11 = 2U /**< XMC_ETH_MDIOC management data I/O */
} XMC_ETH_MAC_PORT_CTRL_MDIO_t;
#endif

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/**
* @file xmc_eth_phy.h
* @date 2015-12-15
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-06-20:
* - Initial
*
* 2015-12-15:
* - Added XMC_ETH_PHY_ExitPowerDown and XMC_ETH_PHY_Reset
*
* @endcond
*/
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup ETH_PHY
* @brief Ethernet PHY driver for XMC4000 microcontroller family.
*
* The XMC_ETH_PHY low level driver provides functions used by XMC_ETH_MAC.
* @{
*/
#ifndef XMC_ETH_PHY_H
#define XMC_ETH_PHY_H
/*******************************************************************************
* INCLUDES
*******************************************************************************/
#include <xmc_eth_mac.h>
/*******************************************************************************
* ENUMS
*******************************************************************************/
/**
* ETH PHY status returns
*/
typedef enum XMC_ETH_PHY_STATUS
{
XMC_ETH_PHY_STATUS_OK = 0U, /**< OK. All is well! */
XMC_ETH_PHY_STATUS_BUSY = 1U, /**< Busy */
XMC_ETH_PHY_STATUS_ERROR = 2U, /**< Error */
XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID = 3U, /**< Error in device identifier */
XMC_ETH_PHY_STATUS_ERROR_TIMEOUT = 4U /**< Time-out error */
} XMC_ETH_PHY_STATUS_t;
/*******************************************************************************
* DATA STRUCTURES
*******************************************************************************/
/**
* ETH PHY configuration
*/
typedef struct XMC_ETH_PHY_CONFIG
{
XMC_ETH_LINK_INTERFACE_t interface; /**< Link interface */
XMC_ETH_LINK_SPEED_t speed; /**< ETH speed: 100M or 10M? */
XMC_ETH_LINK_DUPLEX_t duplex; /**< Half or full duplex? */
bool enable_auto_negotiate; /**< Enable auto-negotiate? */
bool enable_loop_back; /**< Enable loop-back? */
} XMC_ETH_PHY_CONFIG_t;
/*******************************************************************************
* API PROTOTYPES
*******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
* @param phy_addr Physical address
* @param config A constant pointer to XMC_ETH_PHY_CONFIG_t, pointing to a physical layer config
* @return int32_t return status XMC_ETH_PHY_STATUS_t
*
* \par<b>Description: </b><br>
* Initialize the ETH physical layer interface <br>
*
* \par
* The function sets the link speed, applies the duplex mode, sets auto-negotiation
* and loop-back settings.
*/
int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config);
/**
* @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
* @param phy_addr Physical address
* @return int32_t return status XMC_ETH_PHY_STATUS_t
*
* \par<b>Description: </b><br>
* Enter power down mode <br>
*
*/
int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr);
/**
* @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
* @param phy_addr Physical address
* @return int32_t return status XMC_ETH_PHY_STATUS_t
*
* \par<b>Description: </b><br>
* Exit power down mode <br>
*
*/
int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr);
/**
* @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
* @param phy_addr Physical address
* @return int32_t return status XMC_ETH_PHY_STATUS_t
*
* \par<b>Description: </b><br>
* Reset transciver <br>
*
*/
int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr);
/**
* @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
* @param phy_addr Physical address
* @return XMC_ETH_LINK_STATUS_t ETH link status
*
* \par<b>Description: </b><br>
* Get link status <br>
*
* \par
* The function reads the physical layer interface and returns the link status.
* It returns either ::XMC_ETH_LINK_STATUS_UP or ::XMC_ETH_LINK_STATUS_DOWN.
*/
XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr);
/**
* @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
* @param phy_addr Physical address
* @return XMC_ETH_LINK_SPEED_t ETH link speed
*
* \par<b>Description: </b><br>
* Get link speed <br>
*
* \par
* The function reads the physical layer interface and returns the link speed.
* It returns either ::XMC_ETH_LINK_SPEED_100M or ::XMC_ETH_LINK_SPEED_10M.
*/
XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr);
/**
* @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
* @param phy_addr Physical address
* @return XMC_ETH_LINK_DUPLEX_t ETH link duplex settings
*
* \par<b>Description: </b><br>
* Get link duplex settings <br>
*
* \par
* The function reads the physical layer interface and returns the link duplex settings.
* It returns either ::XMC_ETH_LINK_DUPLEX_FULL or ::XMC_ETH_LINK_DUPLEX_HALF.
*/
XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr);
/**
* @param eth_mac A constant pointer to XMC_ETH_MAC_t, pointing to the ETH MAC base address
* @param phy_addr Physical address
* @return bool True if autonegotiation process is finished otherwise false
*
* \par<b>Description: </b><br>
* Get status of autonegotiation <br>
*/
bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* XMC_ETH_PHY_H */

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/**
* @file xmc_fce.h
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial
*
* 2015-05-20:
* - Description updated <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
* @endcond
*
*/
#ifndef XMC_FCE_H
#define XMC_FCE_H
/**********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include <xmc_common.h>
#if defined (FCE)
/**
* @addtogroup XMClib
* @{
*/
/**
* @addtogroup FCE
* @brief Flexible CRC Engine(FCE) driver for the XMC microcontroller family.
*
* The FCE provides a parallel implementation of Cyclic Redundancy Code (CRC)
* algorithms. The current FCE version for the XMC4000 microcontroller family implements the
* IEEE 802.3 ethernet CRC32, the CCITT CRC16 and the SAE J1850 CRC8 polynomials.
* The primary target of FCE is to be used as an hardware acceleration engine for software
* applications or operating systems services using CRC signatures.
*
* @image html fce_overview.png
* @image latex ../images/fce_overview.png
* FCE Features: <br>
* @image html fce_polynomials.png
* @image latex ../images/fce_polynomials.png
* * CRC kernel 0 and 1: IEEE 802.3 CRC32 ethernet polynomial: 0x04C11DB71 <br>
* * CRC kernel 2: CCITT CRC16 polynomial: 0x1021 <br>
* * CRC kernel 3: SAE J1850 CRC8 polynomial: 0x1D <br>
* * Configuration Registers enable to control the CRC operation and perform automatic checksum checks at
* the end of a message. <br>
* * Extended register interface to control reliability of FCE execution in safety applications. <br>
* * Error notification scheme via dedicated interrupt node for: <br>
a)Transient error detection: Error interrupt generation (maskable) with local status register
(cleared by software) <br>
b)Checksum failure: Error interrupt generation (maskable) with local status register (cleared by software) <br>
FCE provides one interrupt line to the interrupt system. Each CRC engine has its own set of flag registers. <br>
* @{
*/
/**********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#define XMC_FCE_CRC32_0 FCE_KE0 /**< Kernel 0 <br> */
#define XMC_FCE_CRC32_1 FCE_KE1 /**< Kernel 1 <br> */
#define XMC_FCE_CRC16 FCE_KE2 /**< Kernel 2 <br> */
#define XMC_FCE_CRC8 FCE_KE3 /**< Kernel 3 <br> */
#define XMC_FCE_REFIN_SET (1U) /**< Enables input reflection */
#define XMC_FCE_REFIN_RESET (0U) /**< Disables input reflection */
#define XMC_FCE_REFOUT_SET (1U) /**< Enables output reflection */
#define XMC_FCE_REFOUT_RESET (0U) /**< Disables output reflection */
#define XMC_FCE_INVSEL_SET (1U) /**< Enables output inversion */
#define XMC_FCE_INVSEL_RESET (0U) /**< Disables output inversion */
/**********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* FCE interrupt configuration
*/
typedef enum XMC_FCE_CONFIG_INTERRUPT
{
XMC_FCE_CFG_CONFIG_CMI = FCE_KE_CFG_CMI_Msk, /**< Enables CRC Mismatch interrupt \n*/
XMC_FCE_CFG_CONFIG_CEI = FCE_KE_CFG_CEI_Msk, /**< Enables Configuration error interrupt \n*/
XMC_FCE_CFG_CONFIG_LEI = FCE_KE_CFG_LEI_Msk, /**< Enables Length error interrupt \n*/
XMC_FCE_CFG_CONFIG_BEI = FCE_KE_CFG_BEI_Msk /**< Enables Bus error interrupt \n*/
} XMC_FCE_CONFIG_INTERRUPT_t;
/**
* FCE operation configuration
*/
typedef enum XMC_FCE_CONFIG_OPERATION
{
XMC_FCE_CFG_CONFIG_CCE = FCE_KE_CFG_CCE_Msk, /**< Enables CRC check */
XMC_FCE_CFG_CONFIG_ALR = FCE_KE_CFG_ALR_Msk /**< Enables Automatic length reload */
} XMC_FCE_CONFIG_OPERATION_t;
/**
* FCE algorithm configuration
*/
typedef enum XMC_FCE_CONFIG_ALGO
{
XMC_FCE_CFG_CONFIG_REFIN = FCE_KE_CFG_REFIN_Msk, /**< Enables input byte reflection */
XMC_FCE_CFG_CONFIG_REFOUT = FCE_KE_CFG_REFOUT_Msk, /**< Enables Final CRC reflection */
XMC_FCE_CFG_CONFIG_XSEL = FCE_KE_CFG_XSEL_Msk /**< Enables output inversion */
} XMC_FCE_CONFIG_ALGO_t;
/**
* FCE status flag configuration
*/
typedef enum XMC_FCE_STS_FLAG
{
XMC_FCE_STS_MISMATCH_CRC = FCE_KE_STS_CMF_Msk, /**< CRC Mismatch flag */
XMC_FCE_STS_CONFIG_ERROR = FCE_KE_STS_CEF_Msk, /**< Configuration Error flag */
XMC_FCE_STS_LENGTH_ERROR = FCE_KE_STS_LEF_Msk, /**< Length Error flag */
XMC_FCE_STS_BUS_ERROR = FCE_KE_STS_BEF_Msk /**< Bus Error flag */
} XMC_FCE_STS_FLAG_t;
/**
* FCE control configuration
*/
typedef enum XMC_FCE_CTR_TEST
{
XMC_FCE_CTR_MISMATCH_CRC = FCE_KE_CTR_FCM_Msk, /**< Forces CRC mismatch */
XMC_FCE_CTR_MISMATCH_CFG = FCE_KE_CTR_FRM_CFG_Msk, /**< Forces CFG Register mismatch */
XMC_FCE_CTR_MISMATCH_CHECK = FCE_KE_CTR_FRM_CHECK_Msk /**< Forces CRC Check Register mismatch */
} XMC_FCE_CTR_TEST_t;
/**
* FCE status enumeration
*/
typedef enum XMC_FCE_STATUS
{
XMC_FCE_STATUS_OK = 0, /**< Returns OK on success */
XMC_FCE_STATUS_BUSY, /**< Returns BUSY when API is busy with a previous request */
XMC_FCE_STATUS_ERROR /**< Returns ERROR when API cannot fulfil request */
} XMC_FCE_STATUS_t;
/**********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/**
* FCE kernel
*/
typedef FCE_KE_TypeDef XMC_FCE_Kernel_t;
/* Anonymous structure/union guard start */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__TASKING__)
#pragma warning 586
#endif
/**
* @brief XMC_FCE configuration structure
*/
typedef struct XMC_FCE_CONFIG
{
union
{
uint32_t regval;
struct
{
uint32_t : 8;
uint32_t config_refin : 1; /**< Enables byte-wise reflection */
uint32_t config_refout : 1; /**< Enables bit-wise reflection */
uint32_t config_xsel : 1; /**< Enables output inversion */
uint32_t : 21; /**< Reserved bits */
};
};
} XMC_FCE_CONFIG_t;
/* Anonymous structure/union guard end */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__TASKING__)
#pragma warning restore
#endif
/**
* FCE handler
*/
typedef struct XMC_FCE
{
XMC_FCE_Kernel_t *kernel_ptr; /**< FCE Kernel Pointer */
XMC_FCE_CONFIG_t fce_cfg_update; /**< FCE CFG register update */
uint32_t seedvalue; /**< CRC seed value to be used */
} XMC_FCE_t;
/**********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param None
* @return uint32_t Module revision number
*
* \par<b>Description: </b><br>
* Read FCE module revision number <br>
*
* \par
* The value of a module revision starts with 0x01 (first revision). The current revision
* number is 0x01.
*/
__STATIC_INLINE uint32_t XMC_FCE_ReadModuleRev(void)
{
return (uint32_t)(FCE->ID & FCE_ID_MOD_REV_Msk);
}
/**
* @param None
* @return uint32_t Module type
*
* \par<b>Description: </b><br>
* Read the FCE module type <br>
*
* \par
* The return value is currently 0xC0. It defines the module as a 32-bit module.
*/
__STATIC_INLINE uint32_t XMC_FCE_ReadModuleType(void)
{
return (uint32_t)((FCE->ID & FCE_ID_MOD_TYPE_Msk) >> FCE_ID_MOD_TYPE_Pos);
}
/**
* @param None
* @return uint32_t Module number
*
* \par<b>Description: </b><br>
* Read FCE module number <br>
*
* \par
* The return value for FCE module is currently 0x00CA.
*/
__STATIC_INLINE uint32_t XMC_FCE_ReadModuleNumber(void)
{
return ((uint32_t)((FCE->ID & FCE_ID_MOD_NUMBER_Msk) >> FCE_ID_MOD_NUMBER_Pos));
}
/**
* @param None
* @return bool Disable status
*
*
* \par<b>Description: </b><br>
* Return the disable status <br>
*
* \par
* The function reads the FCE module disable status (DISS) bit. It returns "true" if
* set, "false" otherwise.
*/
__STATIC_INLINE bool XMC_FCE_Get_DisableStatus(void)
{
return (bool)(FCE->CLC &= (uint32_t)~FCE_CLC_DISS_Msk);
}
/**
* @param None
* @return None
*
* \par<b>Description: </b><br>
* Disable the FCE module <br>
*
* \par
* The function asserts the FCE peripheral reset and sets the DISR bit in the CLC
* register.
*
* \par<b>Note: </b><br>
* All pending transactions running on the bus slave interface must be completed before
* entering the disabled state.
*/
void XMC_FCE_Disable(void);
/**
* @param None
* @return None
*
* \par<b>Description: </b><br>
* Enable the FCE module <br>
*
* \par
* The function de-asserts the peripheral reset and clears the DISR bit CLC register.
*/
void XMC_FCE_Enable(void);
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @return ::XMC_FCE_STATUS_t
*
* \par<b>Description: </b><br>
* Initialize the FCE engine <br>
*
* \par
* The function sets to the CFG and CRC registers with the FCE configuration and
* seeds values. The function always returns XMC_FCE_STATUS_SUCCESS.
*
* \par<b>Note: </b><br>
* The software must first ensure that the CRC kernel is properly configured with the
* initial CRC value (seed value).
*/
XMC_FCE_STATUS_t XMC_FCE_Init(const XMC_FCE_t *const engine);
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param seedvalue Initial CRC value
* @return None
*
* \par<b>Description: </b><br>
* Initialize FCE seed value
*
* \par
* The function sets the initial CRC (seed) value in the CRC register.
*/
__STATIC_INLINE void XMC_FCE_InitializeSeedValue(const XMC_FCE_t *const engine, uint32_t seedvalue)
{
engine->kernel_ptr->CRC = seedvalue;
}
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param event OR'd values of ::XMC_FCE_CONFIG_INTERRUPT_t enumeration values
* @return None
*
* \par<b>Description: </b><br>
* Enable FCE event(s) <br>
*
* \par
* The function sets the CFG register to enable FCE event(s).
*/
__STATIC_INLINE void XMC_FCE_EnableEvent(const XMC_FCE_t *const engine, uint32_t event)
{
engine->kernel_ptr->CFG |= (uint32_t)event;
}
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param event OR'd values of ::XMC_FCE_CONFIG_INTERRUPT_t enumeration values
* @return None
*
* \par<b>Description: </b><br>
* Disable FCE event(s) <br>
*
* \par
* The function clears the CFG register to disable FCE event(s).
*/
__STATIC_INLINE void XMC_FCE_DisableEvent(const XMC_FCE_t *const engine, uint32_t event)
{
engine->kernel_ptr->CFG &= ~(uint32_t)event;
}
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param event Event of type ::XMC_FCE_STS_FLAG_t
* @return bool
*
* \par<b>Description: </b><br>
* Return the event status of FCE event <br>
*
* \par
* The function returns the status of a single requested FCE event by reading the
* appropriate bit-fields of the STS register.
*/
__STATIC_INLINE bool XMC_FCE_GetEventStatus(const XMC_FCE_t *const engine, XMC_FCE_STS_FLAG_t event)
{
return (bool) (engine->kernel_ptr->STS & (uint32_t)event);
}
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param event Event of type ::XMC_FCE_STS_FLAG_t
* @return None
*
* \par<b>Description: </b><br>
* Clear an FCE event <br>
*
* \par
* The function clears requested FCE events by setting the bit-fields of the STS
* register.
*/
__STATIC_INLINE void XMC_FCE_ClearEvent(const XMC_FCE_t *const engine, XMC_FCE_STS_FLAG_t event)
{
engine->kernel_ptr->STS |= (uint32_t)event;
}
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param operation FCE operation of type ::XMC_FCE_CONFIG_OPERATION_t
* @return None
*
* \par<b>Description: </b><br>
* Enable CRC operations <br>
*
* \par
* The function enables FRC operations by writing to the CFG register.
*
* \par<b>Note: </b><br>
* CRC comparison check (at the end of message) can be enabled using the CCE bit-field.
* Automatic reload of LENGTH field (at the end of message) can be enabled using the
* ALR bit field.
*/
__STATIC_INLINE void XMC_FCE_EnableOperation(const XMC_FCE_t *const engine, uint32_t operation)
{
engine->kernel_ptr->CFG |= operation;
}
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param operation FCE operation of type ::XMC_FCE_CONFIG_OPERATION_t
* @return None
*
* \par<b>Description: </b><br>
* Disable CRC operations <br>
*
* \par
* The function disables FRC operations by writing to the CFG register.
*
* \par<b>Note: </b><br>
* CRC comparison check (at the end of message) can be disabled using the CCE bit-field.
* Automatic reload of LENGTH field (at the end of message) can be disabled using the
* ALR bit field.
*/
__STATIC_INLINE void XMC_FCE_DisableOperation(const XMC_FCE_t *const engine, uint32_t operation)
{
engine->kernel_ptr->CFG &= ~(uint32_t)operation;
}
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param algo A valid algorithm of type ::XMC_FCE_CONFIG_ALGO_t or a valid combination
* of logically OR'd algorithms
* @return None
*
* \par<b>Description: </b><br>
* Enables CRC algorithm(s) <br>
*
* \par<b>Note: </b><br>
* Options for enabling CRC algorithm: <br>
* REFIN: Input byte wise reflection <br>
* REFOUT: Output bit wise reflection <br>
* XSEL: Value to be XORed with final CRC <br>
*/
__STATIC_INLINE void XMC_FCE_EnableCRCAlgorithm(const XMC_FCE_t *const engine, uint32_t algo)
{
engine->kernel_ptr->CFG |= (uint32_t)algo;
}
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param algo A valid algorithm of type ::XMC_FCE_CONFIG_ALGO_t or a valid combination
* of logically OR'd algorithms
* @return None
*
* \par<b>Description: </b><br>
* Disable CRC algorithm(s) <br>
*
* \par<b>Note: </b><br>
* Options for disabling CRC algorithm: <br>
* REFIN: Input byte wise reflection <br>
* REFOUT: Output bit wise reflection <br>
* XSEL: Value to be XORed with final CRC <br>
*/
__STATIC_INLINE void XMC_FCE_DisableCRCAlgorithm(const XMC_FCE_t *const engine, uint32_t algo)
{
engine->kernel_ptr->CFG &= ~(uint32_t)algo;
}
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param checkvalue Checksum value
* @return None
*
* \par<b>Description: </b><br>
* Updates CRC check value <br>
*
* \par
* When the CFG.CCE bit field is set, every time the IR register is written, the
* LENGTH register is decremented by one until it reaches zero. The hardware monitors
* the transition of the LENGTH register from 1 to 0 to detect the end of the
* message and proceed with the comparison of the result register (RES) value with
* the CHECK register value.
*/
__STATIC_INLINE void XMC_FCE_UpdateCRCCheck(const XMC_FCE_t *const engine, const uint32_t checkvalue)
{
engine->kernel_ptr->CHECK = 0xFACECAFEU;
engine->kernel_ptr->CHECK = checkvalue;
}
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param checklength Checksum length
* @return None <br>
*
* \par<b>Description: </b><br>
* Updates CRC length specified in the input parameter <br>
*
* \par
* When the ALR bit field is set to 1, every write to the IR register decrements
* the value of the LENGTH bit field. The LENGTH field shall be reloaded with its
* configuration value at the end of the cycle where LENGTH reaches 0.
*/
__STATIC_INLINE void XMC_FCE_UpdateLength(const XMC_FCE_t *const engine, const uint32_t checklength)
{
engine->kernel_ptr->LENGTH = 0xFACECAFEU;
engine->kernel_ptr->LENGTH = checklength;
}
/**
* @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address
* @param data Pointer to the data buffer
* @param length Total number of bytes of data buffer
* @param result Pointer to computed CRC result
* @return XMC_FCE_STATUS_ERROR on error
* @return XMC_FCE_STATUS_SUCCESS otherwise.
*
* \par<b>Description: </b><br>
* Calculate and updates the CRC8 checksum in the result pointer <br>
*
* \par<b>Note: </b><br>
* A write to IRm (m = 3) triggers the CRC kernel to update the message checksum
* according to the IR and current CRC register contents. Any write transaction
* is allowed to this IRm register. Only the lower 8-bit of the write transactions
* will be used. ::XMC_FCE_GetCRCResult() should be called after invoking
* ::XMC_FCE_CalculateCRC8() to get final CRC value.
*/
XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine,
const uint8_t *data,
uint32_t length,
uint8_t *result);
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param data Pointer to the data buffer
* @param length Length of data buffer
* @param result Pointer to computed CRC result
* @return XMC_FCE_STATUS_ERROR on error
* @return XMC_FCE_STATUS_SUCCESS otherwise.
*
* \par<b>Description: </b><br>
* Calculate and update the RC16 checksum in the result pointer <br>
*
* \par<b>Note: </b><br>
* A write to Internal Register (IRm m = 2) triggers the CRC kernel to update the
* message checksum according to the IR and current CRC register contents. Only 32-bit
* or 16-bit write transactions are permitted. Any other bus write transaction will
* lead to a bus error. Only the lower 16-bit of the write transactions will be used.
* ::XMC_FCE_GetCRCResult() should be called after ::XMC_FCE_CalculateCRC16() to get
* final CRC value.
*/
XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine,
const uint16_t *data,
uint32_t length,
uint16_t *result);
/**
* @param engine Constant pointer to @ref XMC_FCE_t, pointing to the FCE base address
* @param data Pointer to the data buffer
* @param length Total number of bytes of data buffer
* @param result Pointer to computed CRC result
* @return XMC_FCE_STATUS_ERROR on error
* @return XMC_FCE_STATUS_SUCCESS otherwise.
*
* \par<b>Description</b><br>
* Calculate and update the calculated CRC32 checksum in the result pointer <br>
*
* \par<b>Note:</b><br>
* A write to Internal Register (IRm, m = 0-1) triggers the CRC kernel to update
* the message checksum according to the IR and current CRC register contents. Only
* 32-bit write transactions are permitted. Any other bus write transaction will
* lead to a bus error. ::XMC_FCE_GetCRCResult() should be called after
* ::XMC_FCE_CalculateCRC32() to get final CRC value.
*/
XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32(const XMC_FCE_t *const engine,
const uint32_t *data,
uint32_t length,
uint32_t *result);
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param result Pointer to CRC result
* @return None
*
* \par<b>Description: </b><br>
* Read the final CRC value from RES register <br>
*/
__STATIC_INLINE void XMC_FCE_GetCRCResult(const XMC_FCE_t *const engine, uint32_t *result)
{
*result= engine->kernel_ptr->RES;
}
/**
* @param engine Constant pointer to ::XMC_FCE_t, pointing to the FCE base address
* @param test values of type ::XMC_FCE_CTR_TEST_t
* @return None
*
* \par<b>Description: </b><br>
* Trigger the CTR register to generate a CRC mismatch/register mismatch/check register
* mismatch interrupt <br>
*/
void XMC_FCE_TriggerMismatch(const XMC_FCE_t *const engine, XMC_FCE_CTR_TEST_t test);
/**
* @param inbuffer Pointer to input data buffer
* @param outbuffer Pointer to the output data buffer
* @param length Length of the input buffer
* @return None
*
* \par<b>Description: </b><br>
* Convert input data buffer's endianness from big endian to little endian <br>
*
* \par
* The function stores the converted data in output data buffer.
*
* \par<b>Note: </b><br>
* This function should be invoked before using ::XMC_FCE_CalculateCRC16() to compute
* the CRC value.
*/
void XMC_FCE_LittleEndian16bit(uint8_t* inbuffer, uint16_t* outbuffer, uint16_t length);
/**
* @param inbuffer Pointer to input data buffer
* @param outbuffer Pointer to the output data buffer
* @param length Length of the input buffer
* @return None
*
* \par<b>Description: </b><br>
* Convert input data buffer's endianness from big endian to little endian <br>
*
* \par
* The function stores the converted data in output data buffer.
*
* \par<b>Note: </b><br>
* This function should be invoked before using ::XMC_FCE_CalculateCRC32() to compute
* the CRC value.
*/
void XMC_FCE_LittleEndian32bit(uint8_t* inbuffer, uint32_t* outbuffer, uint16_t length);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* defined (FCE) */
#endif /* XMC_FCE_H */

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/**
* @file xmc_flash.h
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2014-12-10:
* - Initial <br>
* 2015-02-20:
* - Updated for Documentation related changes<br>
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
* @endcond
*
*/
#ifndef XMC_FLASH_H
#define XMC_FLASH_H
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_common.h"
#if UC_FAMILY == XMC1
#include "xmc1_flash.h"
#endif
#if UC_FAMILY == XMC4
#include "xmc4_flash.h"
#endif
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup FLASH
* @brief Flash driver for XMC microcontroller family.
*
* Flash is a non volatile memory module used to store instruction code or constant data.
* The flash low level driver provides support to the following functionalities of flash memory.<BR>
* <OL>
* \if XMC4
* <LI>Provides function to program a page. ( XMC_FLASH_ProgramPage() )</LI><BR>
* <LI>Provides functions to support read and write protection. ( XMC_FLASH_InstallProtection(),
* XMC_FLASH_ConfirmProtection(), XMC_FLASH_VerifyReadProtection(), XMC_FLASH_VerifyWriteProtection() ) </LI><BR>
* <LI>Provides function to erase sector. ( XMC_FLASH_EraseSector() ) </LI><BR>
* \endif
* \if XMC1
* <LI>Provides functions to program and verify pages. ( XMC_FLASH_ProgramPage(), XMC_FLASH_ProgramPages()
* XMC_FLASH_ProgramVerifyPage() )</LI><BR>
* <LI>Provides functions to write and verify blocks. ( XMC_FLASH_WriteBlocks(), XMC_FLASH_VerifyBlocks() )</LI><BR>
* <LI>Provides functions to read data in terms of word and blocks. ( XMC_FLASH_ReadBlocks(), XMC_FLASH_ReadWord() )
* </LI><BR>
* <LI>Provides function to erase page. ( XMC_FLASH_ErasePage() ) </LI><BR>
* \endif
* </OL>
* @{
*/
/*******************************************************************************
* API PROTOTYPE
*******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
*
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC1
* Clears the previous error status by reseting the ECC and VERR error status bits of NVMSTATUS register.\n\n
* Call this API before starting any flash programming / erase related APIs to ensure all previous errors are cleared.
* \endif
* \if XMC4
* Clears the previous error status by reseting the FSR status register.\n\n Call this API before starting any flash
* programming / erase related APIs to ensure all previous errors are cleared.
* \endif
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
void XMC_FLASH_ClearStatus(void);
/**
*
* @param None
*
* @return uint32_t Status of the previous flash operation.
*
* \par<b>Description:</b><br>
* \if XMC1
* Informs the status of flash by reading the NVMSTATUS register.\n\n It indicates the ECC, VERR(verification error),
* WRPERR (Write protocol error) errors as well as the current flash state. After calling the flash read/write/erase
* operation related APIs, call this API to get the verification status. The return value of this API shall be checked
* against the members of @ref XMC_FLASH_STATUS_t enumeration to get the relevant status.
* \endif
* \if XMC4
* Informs the status of flash by reading the FSR register.\n\n It indicates the error status such as PFOPER, SQER,
* PROER, PFDBER, ORIER, VER errors as well as the current flash state. After calling the flash read/write/erase
* operation related APIs, call this API to verify flash status. The return value of this API shall be checked against
* the members of @ref XMC_FLASH_STATUS_t enumeration to get the relevant status.
* \endif
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
uint32_t XMC_FLASH_GetStatus(void);
/**
*
* @param event_msk ORed values of @ref XMC_FLASH_EVENT_t enumeration
*
* @return None
*
* \par<b>Description:</b><br>
* Enables the particular flash events as specified in the input parameter.\n
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_DisableEvent()\n\n\n
*
*/
void XMC_FLASH_EnableEvent(const uint32_t event_msk);
/**
*
* @param event_msk ORed values of @ref XMC_FLASH_EVENT_t enumeration
*
* @return None
*
* \par<b>Description:</b><br>
* Disables the particular flash events as specified in the input parameter.\n
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_EnableEvent()\n\n\n
*
*/
void XMC_FLASH_DisableEvent(const uint32_t event_msk);
/**
*
* @param address Pointer to the starting address of flash page from where the programming starts.
* @param data Pointer to the source address where targeted data is located.
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC1
* Programs a single flash page associated with the specified \a address.\n\n XMC1000 Flash can be programmed with one
* page (256 bytes) using this API. It calls the Flash Firmware routine \a XMC1000_NvmProgVerify(unsigned long pageAddr)
* to perform the programming. Refer XMC1000 reference manual of for more details on flash firmware routines
* (Section 25.3). Call XMC_FLASH_GetStatus() API after calling this API, to verify the programming operation.
* \endif
* \if XMC4
* Programs a single flash page associated with the specified \a address.\n\n XMC4000 flash can be programmed with a
* granularity of 256 bytes page using this API. Before entering into page write process, it clears the error status
* bits inside status register. It starts the write process by issuing the page mode command followed by the load page
* command which loads the targeted \a data blocks into internal assembly buffer. Finally, it issues the write page
* command which programs the \a data into flash. Call XMC_FLASH_GetStatus() API after calling this API, to verify the
* programming operation.\n
* \endif
*
* \par<b>Note:</b><br>
* Flash will be busy state during write is ongoing, hence no operations allowed until it completes.
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data);
/**
*
* @param address Pointer to the starting address of the page to be erased.
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC1
* Erases a complete sector starting from the \a address specified.\n\n XMC1000 Flash can be erased with granularity
* of one page = 16 blocks of 16 Bytes = 256 Bytes using this API. It internally calls XMC_FLASH_ErasePages API 16
* times starting from the first page of the sector.. Call XMC_FLASH_GetStatus() API after calling this API,
* to verify the erase operation.\n
* \endif
*
* \if XMC4
* Erases a sector associated with the specified \a address.\n\n Before erase, it clears the error status bits inside
* FSR status register. Issues the erase sector command sequence with the specified starting \a address to start flash
* erase process. Call XMC_FLASH_GetStatus() API after calling this API, to verify the erase operation.\n
* \endif
* \if XMC1
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_ErasePages() \n\n\n
* \endif
* \if XMC4
* \par<b>Related APIs:</b><BR>
* None
* \endif
*/
void XMC_FLASH_EraseSector(uint32_t *address);
/**
*
* @param None
*
* @return true if flash is in busy state else returns \a false.
*
* \par<b>Description:</b><br>
* Checks whether flash is in busy state or not.\n\n It is checked by calling the XMC_FLASH_GetStatus() API internally.
* Refer XMC_FLASH_GetStatus() for more details.\n
*
* \par<b>Related APIs:</b><BR>
* XMC_FLASH_GetStatus()\n\n\n
*
*/
__STATIC_INLINE bool XMC_FLASH_IsBusy(void)
{
return (bool)(XMC_FLASH_GetStatus() & XMC_FLASH_STATUS_BUSY);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

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/**
* @file xmc_gpio.h
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft<br>
* - Documentation improved <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* @endcond
*
*/
#ifndef XMC_GPIO_H
#define XMC_GPIO_H
/**********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_common.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup GPIO
* @brief General Purpose Input Output (GPIO) driver for the XMC microcontroller family.
*
* GPIO driver provide a generic and very flexible software interface for all standard digital I/O port pins.
* Each port slice has individual interfaces for the operation as General Purpose I/O and it further provides the
* connectivity to the on-chip periphery and the control for the pad characteristics.
*
* The driver is divided into Input and Output mode.
*
* Input mode features:
* -# Configuration structure XMC_GPIO_CONFIG_t and initialization function XMC_GPIO_Init()
* -# Allows the selection of weak pull-up or pull-down device. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode()
* \if XMC1
* -# Allows the selection of input hysteresis. XMC_GPIO_SetInputHysteresis()
* \endif
*
*
* Output mode features:
* -# Allows the selection of push pull/open drain and Alternate output. Configuration structure XMC_GPIO_MODE_t and function XMC_GPIO_SetMode()
* \if XMC4
* -# Allows the selection of pad driver strength. Configuration structure XMC_GPIO_OUTPUT_STRENGTH_t and function XMC_GPIO_SetOutputStrength()
* \endif
*
* -# Allows the selection of initial output level. Configuration structure XMC_GPIO_OUTPUT_LEVEL_t and function XMC_GPIO_SetOutputLevel()
*
*@{
*/
/**********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#define PORT_IOCR_PC_Pos PORT0_IOCR0_PC0_Pos
#define PORT_IOCR_PC_Msk PORT0_IOCR0_PC0_Msk
#define PORT_IOCR_PC_Size (8U)
#define XMC_GPIO_CHECK_OUTPUT_LEVEL(level) ((level == XMC_GPIO_OUTPUT_LEVEL_LOW) || \
(level == XMC_GPIO_OUTPUT_LEVEL_HIGH))
#define XMC_GPIO_CHECK_HWCTRL(hwctrl) ((hwctrl == XMC_GPIO_HWCTRL_DISABLED) || \
(hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL1) || \
(hwctrl == XMC_GPIO_HWCTRL_PERIPHERAL2))
/**********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* Defines output level of a pin. Use type \a XMC_GPIO_OUTPUT_LEVEL_t for this enum.
*/
typedef enum XMC_GPIO_OUTPUT_LEVEL
{
XMC_GPIO_OUTPUT_LEVEL_LOW = 0x10000U, /**< Reset bit */
XMC_GPIO_OUTPUT_LEVEL_HIGH = 0x1U, /**< Set bit */
} XMC_GPIO_OUTPUT_LEVEL_t;
/**
* Defines direct hardware control characteristics of the pin . Use type \a XMC_GPIO_HWCTRL_t for this enum.
*/
typedef enum XMC_GPIO_HWCTRL
{
XMC_GPIO_HWCTRL_DISABLED = 0x0U, /**< Software control only */
XMC_GPIO_HWCTRL_PERIPHERAL1 = 0x1U, /**< HWI0/HWO0 control path can override the software configuration */
XMC_GPIO_HWCTRL_PERIPHERAL2 = 0x2U /**< HWI1/HWO1 control path can override the software configuration */
} XMC_GPIO_HWCTRL_t;
/**********************************************************************************************************************
* DEVICE FAMILY EXTENSIONS
*********************************************************************************************************************/
#if UC_FAMILY == XMC1
#include "xmc1_gpio.h"
#elif UC_FAMILY == XMC4
#include "xmc4_gpio.h"
#else
#error "xmc_gpio.h: family device not supported"
#endif
/**********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param port Constant pointer pointing to GPIO port, to access port registers like Pn_OUT,Pn_OMR,Pn_IOCR etc.
* @param pin Port pin number.
* @param config GPIO configuration data structure. Refer data structure @ref XMC_GPIO_CONFIG_t for details.
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC1
* Initializes input / output mode settings like, pull up / pull down devices,hysteresis, push pull /open drain.
* Also configures alternate function outputs and clears hardware port control for a selected \a port \a and \a pin.
* \a config provides selected I/O settings. It configures hardware registers Pn_IOCR,Pn_OUT, Pn_OMR,Pn_PDISC and Pn_PHCR.
* \endif
* \if XMC4
* Initializes input / output mode settings like, pull up / pull down devices,push pull /open drain, and pad driver mode.
* Also configures alternate function outputs and clears hardware port control for selected \a port and \a pin .
* It configures hardware registers Pn_IOCR,Pn_OUT,Pn_OMR,Pn_PDISC and Pn_PDR.\n
* \endif
*
* \par<b>Related APIs:</b><BR>
* None
*
* \par<b>Note:</b><br>
* This API is called in definition of DAVE_init by code generation and therefore should not be explicitly called
* for the normal operation. Use other APIs only after DAVE_init is called successfully (returns DAVE_STATUS_SUCCESS).
*
*
*/
void XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_CONFIG_t *const config);
/**
*
* @param port Constant pointer pointing to GPIO port, to access hardware register Pn_IOCR.
* @param pin Port pin number.
* @param mode input / output functionality selection. Refer @ref XMC_GPIO_MODE_t for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Sets digital input and output driver functionality and characteristics of a GPIO port pin. It configures hardware
* registers Pn_IOCR. \a mode is initially configured during initialization in XMC_GPIO_Init(). Call this API to alter
* the port direction functionality as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* None
*
*/
void XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_MODE_t mode);
/**
*
* @param port Constant pointer pointing to GPIO port, to access hardware register Pn_OMR.
* @param pin Port pin number.
* @param level output level selection. Refer @ref XMC_GPIO_OUTPUT_LEVEL_t for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Set port pin output level to high or low.It configures hardware registers Pn_OMR.\a level is initially
* configured during initialization in XMC_GPIO_Init(). Call this API to alter output level as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_GPIO_SetOutputHigh(), XMC_GPIO_SetOutputLow().
*
* \par<b>Note:</b><br>
* Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().
*
*/
__STATIC_INLINE void XMC_GPIO_SetOutputLevel(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_OUTPUT_LEVEL_t level)
{
XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));
XMC_ASSERT("XMC_GPIO_SetOutputLevel: Invalid output level", XMC_GPIO_CHECK_OUTPUT_LEVEL(level));
port->OMR = (uint32_t)level << pin;
}
/**
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR.
* @param pin Port pin number.
*
* @return None
*
* \par<b>Description:</b><br>
* Sets port pin output to high. It configures hardware registers Pn_OMR.
*
* \par<b>Related APIs:</b><BR>
* XMC_GPIO_SetOutputLow()
*
* \par<b>Note:</b><br>
* Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().\n
* Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0.
*
*/
__STATIC_INLINE void XMC_GPIO_SetOutputHigh(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_SetOutputHigh: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));
port->OMR = (uint32_t)0x1U << pin;
}
/**
*
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR.
* @param pin port pin number.
*
* @return None
*
*\par<b>Description:</b><br>
* Sets port pin output to low. It configures hardware registers Pn_OMR.\n
*
* \par<b>Related APIs:</b><BR>>
* XMC_GPIO_SetOutputHigh()
*
*\par<b>Note:</b><br>
* Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode().
* Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0.\n
*
*/
__STATIC_INLINE void XMC_GPIO_SetOutputLow(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_SetOutputLow: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));
port->OMR = 0x10000U << pin;
}
/**
*
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_OMR.
* @param pin port pin number.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures port pin output to Toggle. It configures hardware registers Pn_OMR.
*
* \par<b>Related APIs:</b><BR>
* XMC_GPIO_SetOutputHigh(), XMC_GPIO_SetOutputLow().
*
* \par<b>Note:</b><br>
* Prior to this api, user has to configure port pin to output mode using XMC_GPIO_SetMode(). Register Pn_OMR is virtual
* and does not contain any flip-flop. A read action delivers the value of 0.
*
*/
__STATIC_INLINE void XMC_GPIO_ToggleOutput(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_ToggleOutput: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));
port->OMR = 0x10001U << pin;
}
/**
*
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_IN.
* @param pin Port pin number.
*
* @return uint32_t pin logic level status.
*
*\par<b>Description:</b><br>
* Reads the Pn_IN register and returns the current logical value at the GPIO pin.
*
* \par<b>Related APIs:</b><BR>
* None
*
* \par<b>Note:</b><br>
* Prior to this api, user has to configure port pin to input mode using XMC_GPIO_SetMode().
*
*/
__STATIC_INLINE uint32_t XMC_GPIO_GetInput(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_GetInput: Invalid port", XMC_GPIO_CHECK_PORT(port));
return (((port->IN) >> pin) & 0x1U);
}
/**
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS.
* @param pin port pin number.
*
* @return None
*
* \par<b>Description:</b><br>
* Enables pin power save mode and configures Pn_PPS register.This configuration is useful when the controller enters
* Deep Sleep mode.Port pin enabled with power save mode option are set to a defined state and the input Schmitt-Trigger
* as well as the output driver stage are switched off. By default port pin does not react to power save mode request.
*
* \par<b>Related APIs:</b><BR>
* XMC_GPIO_DisablePowerSaveMode()
*
* <b>Note:</b><br>
* Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so
* may result in an undefined behavior of the pin when the device enters the Deep Sleep state.
*
*/
__STATIC_INLINE void XMC_GPIO_EnablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_EnablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port));
port->PPS |= (uint32_t)0x1U << pin;
}
/**
*
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_PPS.
* @param pin port pin number.
*
* @return None
*
* \par<b>Description:</b><br>
* Disables pin power save mode and configures Pn_PPS register.This configuration is useful when the controller enters
* Deep Sleep mode. This configuration enables input Schmitt-Trigger and output driver stage(if pin is enabled power
* save mode previously). By default port \a pin does not react to power save mode request.
*
* \par<b>Related APIs:</b><BR>
* XMC_GPIO_EnablePowerSaveMode()
*
*\par<b>Note:</b><br>
* Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B). Doing so
* may result in an undefined behavior of the pin when the device enters the Deep Sleep state.
*
*/
__STATIC_INLINE void XMC_GPIO_DisablePowerSaveMode(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_DisablePowerSaveMode: Invalid port", XMC_GPIO_CHECK_PORT(port));
port->PPS &= ~(uint32_t)((uint32_t)0x1U << pin);
}
/**
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_HWSEL.
* @param pin port pin number.
* @param hwctrl direct hardware control selection. Refer @ref XMC_GPIO_HWCTRL_t for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Selects direct hard ware control and configures Pn_HWSEL register.This configuration is useful for the port pins
* overlaid with peripheral functions for which the connected peripheral needs hardware control.
*
* \par<b>Related APIs:</b><BR>
* None
*
*\par<b>Note:</b><br>
* Do not enable the Pin Power Save function for pins configured for Hardware Control (Pn_HWSEL.HWx != 00B).
* Doing so may result in an undefined behavior of the pin when the device enters the Deep Sleep state.
*
*/
void XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl);
/**
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDISC.
* @param pin port pin number.
*
* @return None
*
* \par<b>Related APIs:</b><BR>
* None
*
* \par<b>Description:</b><br>
* Enable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only for
* analog port pins.
*
*/
__STATIC_INLINE void XMC_GPIO_EnableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port));
port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin);
}
/**
* @param port constant pointer pointing to GPIO port, to access hardware register Pn_PDISC.
* @param pin port pin number.
*
* @return None
*
* \par<b>Related APIs:</b><BR>
* None
*
* \par<b>Description:</b><br>
* Disable digital input path for analog pins and configures Pn_PDISC register.This configuration is applicable only
* for analog port pins.
*
*/
__STATIC_INLINE void XMC_GPIO_DisableDigitalInput(XMC_GPIO_PORT_t *const port, const uint8_t pin)
{
XMC_ASSERT("XMC_GPIO_EnableDigitalInput: Invalid analog port", XMC_GPIO_CHECK_ANALOG_PORT(port));
port->PDISC |= (uint32_t)0x1U << pin;
}
#ifdef __cplusplus
}
#endif
/**
* @} (end addtogroup GPIO)
*/
/**
* @} (end addtogroup XMClib)
*/
#endif /* XMC_GPIO_H */

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/**
* @file xmc_hrpwm_map.h
* @date 2015-06-20
*
* @cond
**********************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification,are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share
* modifications, enhancements or bug fixes with Infineon Technologies AG
* dave@infineon.com).
**********************************************************************************
*
* Change History
* --------------
*
* 2015-06-20:
* - Updated copyright and change history section.
*
* @endcond
*
*/
/**
*
* @brief HRPWM mapping for XMC4 microcontroller family. <br>
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_hrpwm.h"
#ifndef XMC_HRPWM_MAP_H
#define XMC_HRPWM_MAP_H
#if ((UC_DEVICE == XMC4400) || (UC_DEVICE == XMC4200) || (UC_DEVICE == XMC4100))
/* CSG0 - General input to control Blanking and Switch of the Comparator */
#define XMC_HRPWM_CSG0_BL_P1_4 XMC_HRPWM_CSG_INPUT_SEL_IA
#define XMC_HRPWM_CSG0_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB
#define XMC_HRPWM_CSG0_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC
#define XMC_HRPWM_CSG0_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID
#define XMC_HRPWM_CSG0_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE
#define XMC_HRPWM_CSG0_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF
#define XMC_HRPWM_CSG0_BL_CCU40_ST0 XMC_HRPWM_CSG_INPUT_SEL_IG
#define XMC_HRPWM_CSG0_BL_CCU41_ST0 XMC_HRPWM_CSG_INPUT_SEL_IH
#define XMC_HRPWM_CSG0_BL_HRPWM_QOUT0 XMC_HRPWM_CSG_INPUT_SEL_II
#define XMC_HRPWM_CSG0_BL_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_IJ
#define XMC_HRPWM_CSG0_BL_CCU40_SR0 XMC_HRPWM_CSG_INPUT_SEL_IK
#define XMC_HRPWM_CSG0_BL_CCU41_SR0 XMC_HRPWM_CSG_INPUT_SEL_IL
#define XMC_HRPWM_CSG0_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM
#define XMC_HRPWM_CSG0_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN
#define XMC_HRPWM_CSG0_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO
#define XMC_HRPWM_CSG0_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP
/* CSG0 - General input to control start/stop/trigger for Slope Control Logic */
#define XMC_HRPWM_CSG0_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB
#define XMC_HRPWM_CSG0_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC
#define XMC_HRPWM_CSG0_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID
#define XMC_HRPWM_CSG0_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE
#define XMC_HRPWM_CSG0_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF
#define XMC_HRPWM_CSG0_SC_CCU40_ST0 XMC_HRPWM_CSG_INPUT_SEL_IG
#define XMC_HRPWM_CSG0_SC_CCU41_ST0 XMC_HRPWM_CSG_INPUT_SEL_IH
#define XMC_HRPWM_CSG0_SC_HRPWM_QOUT0 XMC_HRPWM_CSG_INPUT_SEL_II
#define XMC_HRPWM_CSG0_SC_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_IJ
#define XMC_HRPWM_CSG0_SC_CCU40_SR0 XMC_HRPWM_CSG_INPUT_SEL_IK
#define XMC_HRPWM_CSG0_SC_CCU41_SR0 XMC_HRPWM_CSG_INPUT_SEL_IL
#define XMC_HRPWM_CSG0_SC_HRPWM_C0O XMC_HRPWM_CSG_INPUT_SEL_IM
#define XMC_HRPWM_CSG0_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN
#define XMC_HRPWM_CSG0_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO
#define XMC_HRPWM_CSG0_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP
/* CSG1 - General input to control Blanking and Switch of the Comparator */
#define XMC_HRPWM_CSG1_BL_P2_4 XMC_HRPWM_CSG_INPUT_SEL_IA
#define XMC_HRPWM_CSG1_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB
#define XMC_HRPWM_CSG1_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC
#define XMC_HRPWM_CSG1_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID
#define XMC_HRPWM_CSG1_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE
#define XMC_HRPWM_CSG1_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF
#define XMC_HRPWM_CSG1_BL_CCU40_ST1 XMC_HRPWM_CSG_INPUT_SEL_IG
#define XMC_HRPWM_CSG1_BL_CCU41_ST1 XMC_HRPWM_CSG_INPUT_SEL_IH
#define XMC_HRPWM_CSG1_BL_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_II
#define XMC_HRPWM_CSG1_BL_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_IJ
#define XMC_HRPWM_CSG1_BL_CCU40_SR1 XMC_HRPWM_CSG_INPUT_SEL_IK
#define XMC_HRPWM_CSG1_BL_CCU41_SR1 XMC_HRPWM_CSG_INPUT_SEL_IL
#define XMC_HRPWM_CSG1_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM
#define XMC_HRPWM_CSG1_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN
#define XMC_HRPWM_CSG1_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO
#define XMC_HRPWM_CSG1_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP
/* CSG1 - General input to control start/stop/trigger for Slope Control Logic */
#define XMC_HRPWM_CSG1_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB
#define XMC_HRPWM_CSG1_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC
#define XMC_HRPWM_CSG1_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID
#define XMC_HRPWM_CSG1_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE
#define XMC_HRPWM_CSG1_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF
#define XMC_HRPWM_CSG1_SC_CCU40_ST1 XMC_HRPWM_CSG_INPUT_SEL_IG
#define XMC_HRPWM_CSG1_SC_CCU41_ST1 XMC_HRPWM_CSG_INPUT_SEL_IH
#define XMC_HRPWM_CSG1_SC_HRPWM_QOUT1 XMC_HRPWM_CSG_INPUT_SEL_II
#define XMC_HRPWM_CSG1_SC_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_IJ
#define XMC_HRPWM_CSG1_SC_CCU40_SR1 XMC_HRPWM_CSG_INPUT_SEL_IK
#define XMC_HRPWM_CSG1_SC_CCU41_SR1 XMC_HRPWM_CSG_INPUT_SEL_IL
#define XMC_HRPWM_CSG1_SC_HRPWM_C1O XMC_HRPWM_CSG_INPUT_SEL_IM
#define XMC_HRPWM_CSG1_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN
#define XMC_HRPWM_CSG1_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO
#define XMC_HRPWM_CSG1_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP
/* CSG2 - General input to control Blanking and Switch of the Comparator */
#define XMC_HRPWM_CSG2_BL_P2_5 XMC_HRPWM_CSG_INPUT_SEL_IA
#define XMC_HRPWM_CSG2_BL_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB
#define XMC_HRPWM_CSG2_BL_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC
#define XMC_HRPWM_CSG2_BL_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID
#define XMC_HRPWM_CSG2_BL_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE
#define XMC_HRPWM_CSG2_BL_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF
#define XMC_HRPWM_CSG2_BL_CCU40_ST2 XMC_HRPWM_CSG_INPUT_SEL_IG
#define XMC_HRPWM_CSG2_BL_CCU41_ST2 XMC_HRPWM_CSG_INPUT_SEL_IH
#define XMC_HRPWM_CSG2_BL_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_II
#define XMC_HRPWM_CSG2_BL_HRPWM_QOUT3 XMC_HRPWM_CSG_INPUT_SEL_IJ
#define XMC_HRPWM_CSG2_BL_CCU40_SR2 XMC_HRPWM_CSG_INPUT_SEL_IK
#define XMC_HRPWM_CSG2_BL_CCU41_SR2 XMC_HRPWM_CSG_INPUT_SEL_IL
#define XMC_HRPWM_CSG2_BL_HRPWM_SR2 XMC_HRPWM_CSG_INPUT_SEL_IM
#define XMC_HRPWM_CSG2_BL_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN
#define XMC_HRPWM_CSG2_BL_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO
#define XMC_HRPWM_CSG2_BL_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP
/* CSG2 - General input to control start/stop/trigger for Slope Control Logic */
#define XMC_HRPWM_CSG2_SC_SCU_GSHR0 XMC_HRPWM_CSG_INPUT_SEL_IB
#define XMC_HRPWM_CSG2_SC_CCU80_ST0 XMC_HRPWM_CSG_INPUT_SEL_IC
#define XMC_HRPWM_CSG2_SC_CCU80_ST1 XMC_HRPWM_CSG_INPUT_SEL_ID
#define XMC_HRPWM_CSG2_SC_CCU80_ST2 XMC_HRPWM_CSG_INPUT_SEL_IE
#define XMC_HRPWM_CSG2_SC_CCU80_ST3 XMC_HRPWM_CSG_INPUT_SEL_IF
#define XMC_HRPWM_CSG2_SC_CCU40_ST2 XMC_HRPWM_CSG_INPUT_SEL_IG
#define XMC_HRPWM_CSG2_SC_CCU41_ST2 XMC_HRPWM_CSG_INPUT_SEL_IH
#define XMC_HRPWM_CSG2_SC_HRPWM_QOUT2 XMC_HRPWM_CSG_INPUT_SEL_II
#define XMC_HRPWM_CSG2_SC_HRPWM_QOUT3 XMC_HRPWM_CSG_INPUT_SEL_IJ
#define XMC_HRPWM_CSG2_SC_CCU40_SR2 XMC_HRPWM_CSG_INPUT_SEL_IK
#define XMC_HRPWM_CSG2_SC_CCU41_SR2 XMC_HRPWM_CSG_INPUT_SEL_IL
#define XMC_HRPWM_CSG2_SC_HRPWM_C2O XMC_HRPWM_CSG_INPUT_SEL_IM
#define XMC_HRPWM_CSG2_SC_HRPWM_SR3 XMC_HRPWM_CSG_INPUT_SEL_IN
#define XMC_HRPWM_CSG2_SC_ERU1_IOUT0 XMC_HRPWM_CSG_INPUT_SEL_IO
#define XMC_HRPWM_CSG2_SC_ERU1_IOUT1 XMC_HRPWM_CSG_INPUT_SEL_IP
#endif
#endif /* XMC_HRPWM_MAP_H */

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/**
* @file xmc_i2c.h
* @date 2016-05-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
* - Description updated <br>
* - Added XMC_I2C_CH_TriggerServiceRequest() and XMC_I2C_CH_SelectInterruptNodePointer() <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
*
* 2015-08-27:
* - Added APIs for external input for BRG configuration:XMC_I2C_CH_ConfigExternalInputSignalToBRG() <br>
*
* 2015-09-01:
* - Added APIs for enabling or disabling the ACK response to a 0x00 slave address: XMC_I2C_CH_EnableSlaveAcknowledgeTo00() and
* XMC_I2C_CH_DisableSlaveAcknowledgeTo00(). <br>
* - Modified XMC_I2C_CH_SetInputSource() API for avoiding complete DXCR register overwriting. <br>
* - Modified XMC_I2C_CH_EVENT_t enum for supporting XMC_I2C_CH_EnableEvent() and XMC_I2C_CH_DisableEvent()
* for supporting multiple events configuration <br>
*
* 2015-10-02:
* - Fix 10bit addressing
*
* 2015-10-07:
* - Fix register access in XMC_I2C_CH_EnableSlaveAcknowledgeTo00() and XMC_I2C_CH_DisableSlaveAcknowledgeTo00() APIs.
* - Naming of APIs modified: from XMC_I2C_CH_EnableSlaveAcknowledgeTo00() to XMC_I2C_CH_EnableAcknowledgeAddress0()
* and from XMC_I2C_CH_DisableSlaveAcknowledgeTo00() to XMC_I2C_CH_DisableAcknowledgeAddress0().
*
* 2016-05-20:
* - Added XMC_I2C_CH_EnableDataTransmission() and XMC_I2C_CH_DisableDataTransmission()
*
* 2016-08-17:
* - Improved documentation of slave address passing
*
* @endcond
*
*/
#ifndef XMC_I2C_H
#define XMC_I2C_H
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include "xmc_usic.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup I2C
* @brief Inter Integrated Circuit(IIC) driver for the XMC microcontroller family.
*
* USIC IIC Features: <br>
* * Two-wire interface, with one line for shift clock transfer and synchronization (shift clock SCL), the other one for the data transfer (shift data SDA) <br>
* * Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s) <br>
* * Support of 7-bit addressing, as well as 10-bit addressing <br>
* * Master mode operation, where the IIC controls the bus transactions and provides the clock signal. <br>
* * Slave mode operation, where an external master controls the bus transactions and provides the clock signal.<br>
* * Multi-master mode operation, where several masters can be connected to the bus and bus arbitration can take place, i.e. the IIC module can be master or slave. <br>
The master/slave operation of an IIC bus participant can change from frame to frame. <br>
* * Efficient frame handling (low software effort), also allowing DMA transfers <br>
* * Powerful interrupt handling due to multitude of indication flags <br>
* @{
*/
/*******************************************************************************
* MACROS
*******************************************************************************/
#if defined(USIC0)
#define XMC_I2C0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */
#define XMC_I2C0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */
#endif
#if defined(USIC1)
#define XMC_I2C1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */
#define XMC_I2C1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */
#endif
#if defined(USIC2)
#define XMC_I2C2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */
#define XMC_I2C2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */
#endif
#define XMC_I2C_10BIT_ADDR_GROUP (0x7800U) /**< Value to verify the address is 10-bit or not */
/*******************************************************************************
* ENUMS
*******************************************************************************/
/**
* @brief I2C Status
*/
typedef enum XMC_I2C_CH_STATUS
{
XMC_I2C_CH_STATUS_OK, /**< Status OK */
XMC_I2C_CH_STATUS_ERROR, /**< Status ERROR */
XMC_I2C_CH_STATUS_BUSY /**< Status BUSY */
} XMC_I2C_CH_STATUS_t;
/**
* @brief I2C status
*/
typedef enum XMC_I2C_CH_STATUS_FLAG
{
XMC_I2C_CH_STATUS_FLAG_SLAVE_SELECT = USIC_CH_PSR_IICMode_SLSEL_Msk, /**< Slave select status */
XMC_I2C_CH_STATUS_FLAG_WRONG_TDF_CODE_FOUND = USIC_CH_PSR_IICMode_WTDF_Msk, /**< Wrong TDF status */
XMC_I2C_CH_STATUS_FLAG_START_CONDITION_RECEIVED = USIC_CH_PSR_IICMode_SCR_Msk, /**< Start condition received status */
XMC_I2C_CH_STATUS_FLAG_REPEATED_START_CONDITION_RECEIVED = USIC_CH_PSR_IICMode_RSCR_Msk, /**< Repeated start condition received status */
XMC_I2C_CH_STATUS_FLAG_STOP_CONDITION_RECEIVED = USIC_CH_PSR_IICMode_PCR_Msk, /**< Stop condition received status */
XMC_I2C_CH_STATUS_FLAG_NACK_RECEIVED = USIC_CH_PSR_IICMode_NACK_Msk, /**< NACK received status */
XMC_I2C_CH_STATUS_FLAG_ARBITRATION_LOST = USIC_CH_PSR_IICMode_ARL_Msk, /**< Arbitration lost status */
XMC_I2C_CH_STATUS_FLAG_SLAVE_READ_REQUESTED = USIC_CH_PSR_IICMode_SRR_Msk, /**< Slave read requested status */
XMC_I2C_CH_STATUS_FLAG_ERROR = USIC_CH_PSR_IICMode_ERR_Msk, /**< Error status */
XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED = USIC_CH_PSR_IICMode_ACK_Msk, /**< ACK received status */
XMC_I2C_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_IICMode_RSIF_Msk, /**< Receive start indication status */
XMC_I2C_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_IICMode_DLIF_Msk, /**< Data lost indication status */
XMC_I2C_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_IICMode_TSIF_Msk, /**< Transmit shift indication status */
XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_IICMode_TBIF_Msk, /**< Transmit buffer indication status */
XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_IICMode_RIF_Msk, /**< Receive indication status */
XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_IICMode_AIF_Msk, /**< Alternate receive indication status */
XMC_I2C_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_IICMode_BRGIF_Msk /**< Baud rate generator indication status */
} XMC_I2C_CH_STATUS_FLAG_t;
/**
* @brief I2C receiver status. The received data byte is available at the bit
* positions RBUF[7:0], whereas the additional information is monitored at the bit positions
* RBUF[12:8].
*/
typedef enum XMC_I2C_CH_RECEIVER_STATUS_FLAG
{
XMC_I2C_CH_RECEIVER_STATUS_FLAG_ACK = 0x1U, /**< Bit 8: Value of Received Acknowledgement bit */
XMC_I2C_CH_RECEIVER_STATUS_FLAG_FIN = 0x2U, /**< Bit 9: A 1 at this bit position indicates that after a (repeated) start condition
followed by the address reception the first data byte of a new frame has
been received. A 0 at this bit position indicates further data bytes */
XMC_I2C_CH_RECEIVER_STATUS_FLAG_MODE = 0x4U, /**< Bit 10: A 0 at this bit position indicates that the data byte has been received
when the device has been in slave mode, whereas a 1 indicates a reception in master mode */
XMC_I2C_CH_RECEIVER_STATUS_FLAG_ERR = 0x8U, /**< Bit 11: A 1 at this bit position indicates an incomplete/erroneous
data byte in the receive buffer */
XMC_I2C_CH_RECEIVER_STATUS_FLAG_ADR = 0x10 /**< Bit 12: A 0 at this bit position indicates that the programmed address
has been received. A 1 indicates a general call address. */
} XMC_I2C_CH_RECEIVER_STATUS_FLAG_t;
/**
* @brief I2C commands
*/
typedef enum XMC_I2C_CH_CMD
{
XMC_I2C_CH_CMD_WRITE, /**< I2C Command Write */
XMC_I2C_CH_CMD_READ /**< I2C Command Read */
} XMC_I2C_CH_CMD_t;
/**
* @brief I2C events
*/
typedef enum XMC_I2C_CH_EVENT
{
XMC_I2C_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */
XMC_I2C_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */
XMC_I2C_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */
XMC_I2C_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */
XMC_I2C_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */
XMC_I2C_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */
XMC_I2C_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */
XMC_I2C_CH_EVENT_START_CONDITION_RECEIVED = USIC_CH_PCR_IICMode_SCRIEN_Msk, /**< Start condition received event */
XMC_I2C_CH_EVENT_REPEATED_START_CONDITION_RECEIVED = USIC_CH_PCR_IICMode_RSCRIEN_Msk, /**< Repeated start condition received event */
XMC_I2C_CH_EVENT_STOP_CONDITION_RECEIVED = USIC_CH_PCR_IICMode_PCRIEN_Msk, /**< Stop condition received event */
XMC_I2C_CH_EVENT_NACK = USIC_CH_PCR_IICMode_NACKIEN_Msk, /**< NACK received event */
XMC_I2C_CH_EVENT_ARBITRATION_LOST = USIC_CH_PCR_IICMode_ARLIEN_Msk, /**< Arbitration lost event */
XMC_I2C_CH_EVENT_SLAVE_READ_REQUEST = USIC_CH_PCR_IICMode_SRRIEN_Msk, /**< Slave read request event */
XMC_I2C_CH_EVENT_ERROR = USIC_CH_PCR_IICMode_ERRIEN_Msk, /**< Error condition event */
XMC_I2C_CH_EVENT_ACK = USIC_CH_PCR_IICMode_ACKIEN_Msk /**< ACK received event */
} XMC_I2C_CH_EVENT_t;
/**
* @brief I2C input stage selection
*/
typedef enum XMC_I2C_CH_INPUT
{
XMC_I2C_CH_INPUT_SDA = 0U, /**< selection of sda input stage */
#if UC_FAMILY == XMC1
XMC_I2C_CH_INPUT_SDA1 = 3U,
XMC_I2C_CH_INPUT_SDA2 = 5U,
#endif
XMC_I2C_CH_INPUT_SCL = 1U, /**< selection of scl input stage */
#if UC_FAMILY == XMC1
XMC_I2C_CH_INPUT_SCL1 = 4U
#endif
} XMC_I2C_CH_INPUT_t;
/**
* I2C channel interrupt node pointers
*/
typedef enum XMC_I2C_CH_INTERRUPT_NODE_POINTER
{
XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */
XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */
XMC_I2C_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */
XMC_I2C_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */
XMC_I2C_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */
} XMC_I2C_CH_INTERRUPT_NODE_POINTER_t;
/*******************************************************************************
* DATA STRUCTURES
*******************************************************************************/
/**
* @brief I2C_CH configuration structure
*/
typedef struct XMC_I2C_CH_CONFIG
{
uint32_t baudrate; /**< baud rate configuration upto max of 400KHz */
uint16_t address; /**< slave address
A 7-bit address needs to be left shifted it by 1.
A 10-bit address needs to be ORed with XMC_I2C_10BIT_ADDR_GROUP. */
} XMC_I2C_CH_CONFIG_t;
/*******************************************************************************
* API PROTOTYPES
*******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param config Constant pointer to I2C channel config structure of type @ref XMC_I2C_CH_CONFIG_t
*
* @return None<br>
*
* \par<b>Description:</b><br>
* Initializes the I2C \a channel.<br>
*
* \par
* Configures the data format in SCTR register. Sets the slave address, baud rate. Enables transmit data valid, clears status flags
* and disables parity generation.<br>
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_Enable()\n\n
*/
void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param rate baud rate of I2C channel
*
* @return None<br>
*
* \par<b>Description:</b><br>
* Sets the rate of I2C \a channel.
*
* \par<b>Note:</b><br>
* Standard over sampling is considered if rate <= 100KHz and fast over sampling is considered if rate > 100KHz.<br>
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_SetBaudrate()\n\n
*/
XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
*
* @return None<br>
*
* \par<b>Description:</b><br>
* Starts the I2C \a channel.
*
* \par
* Sets the USIC input operation mode to I2C mode using CCR register.
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_SetMode()\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_Start(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_I2C);
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
*
* @return @ref XMC_I2C_CH_STATUS_t<br>
*
* \par<b>Description:</b><br>
* Stops the I2C \a channel.<br>
*
* \par
* Sets the USIC input operation to IDLE mode using CCR register.
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_SetMode()\n\n
*/
XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param service_request Service request number in the range of 0-5
* @return None<br>
*
* \par<b>Description:</b><br>
* Sets the interrupt node for protocol interrupt.<br>
*
* \par
* To generate interrupt for an event, node pointer should be configured with service request number(SR0, SR1..SR5).
* The NVIC node gets linked to the interrupt event by doing so.<br>
*
* \par<b>Note:</b><br>
* NVIC node should be separately enabled to generate the interrupt. After setting the node pointer, desired event must be enabled.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_EnableEvent(), NVIC_SetPriority(), NVIC_EnableIRQ(), XMC_I2C_CH_SetInputSource()<br>
*/
__STATIC_INLINE void XMC_I2C_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
const uint8_t service_request)
{
XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, service_request);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
* @param interrupt_node Interrupt node pointer to be configured. \n
* \b Range: @ref XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
* @ref XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
* @param service_request Service request number.\n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Sets the interrupt node for USIC channel events. \n\n
* For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
* The NVIC node gets linked to the interrupt event by doing so.<br>
* Note: NVIC node should be separately enabled to generate the interrupt.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2C_CH_EnableEvent() \n\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel,
const XMC_I2C_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
const uint32_t service_request)
{
XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node,
(uint32_t)service_request);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
* @param service_request_line service request number of the event to be triggered. \n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Trigger a I2C interrupt service request.\n\n
* When the I2C service request is triggered, the NVIC interrupt associated with it will be
* generated if enabled.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2C_CH_SelectInterruptNodePointer() \n\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line)
{
XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line);
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param input I2C channel input stage of type @ref XMC_I2C_CH_INPUT_t
* @param source Input source select for the input stage(0->DX0A, 1->DX1A, .. 7->DX7G)
* @return None<br>
*
* \par<b>Description:</b><br>
* Sets the input source for I2C \a channel.<br>
* Defines the input stage for the corresponding input line.
*
* @note After configuring the input source for corresponding channel, interrupt node pointer is set.
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_SetInptSource(), XMC_USIC_CH_SetInterruptNodePointer()
*
*/
__STATIC_INLINE void XMC_I2C_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_INPUT_t input, const uint8_t source)
{
channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_INSW_Msk)) | USIC_CH_DX0CR_DSEN_Msk;
XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source);
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param address I2C slave address
* @return None<br>
*
* \par<b>Description:</b><br>
* Sets the I2C \a channel slave address.<br>
*
* \par
* Address is set in PCR_IICMode register by checking if it is in 10-bit address group or 7-bit address group.
* (If first five bits of address are assigned with 0xF0, then address mode is 10-bit mode otherwise it is 7-bit mode)\n
* @note A 7-bit address should include an additional bit at the LSB for read/write indication. For example, address 0x05 should
* be provided as 0x0a. A 10-bit address should be provided with the identifier 0b11110xx at the most significant bits. For example,
* address 0x305 should be provided as 0x7b05(bitwise OR with 0x7800).
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_GetSlaveAddress()\n\n
*/
void XMC_I2C_CH_SetSlaveAddress(XMC_USIC_CH_t *const channel, const uint16_t address);
/**
* @param channel Constant pointer to USIC channel handler of type @ref XMC_USIC_CH_t
* @return uint16_t Slave address<br>
*
* \par<b>Description:</b><br>
* Gets the I2C \a channel slave address.<br>
*
* \par
* Returns the address using PCR_IICMode register by checking if it is in 10-bit address group or 7-bit address group.<br>
* (If first five bits of address are assigned with 0xF0, then address mode is considered as 10-bit mode otherwise it is 7-bit mode)\n
* @note A 7-bit address will include an additional bit at the LSB. For example, address 0x05 will be returned as 0x0a.
* 10-bit address will not include the 10-bit address identifier 0b11110xx at the most signifcant bits.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_SetSlaveAddress()\n\n
*/
uint16_t XMC_I2C_CH_GetSlaveAddress(const XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param addr I2C master address
* @param command read/write command
* @return None<br>
*
* \par<b>Description:</b><br>
* Starts the I2C master \a channel.<br>
*
* \par
* Sends the Start condition with read/write command by updating IN/TBUF register based on FIFO/non-FIFO modes.\n
* @note Address(addr) should reserve an additional bit at the LSB for read/write indication. For example, address 0x05 should
* be provided as 0x0a. If the address is 10-bit, only most significant bits with the 10-bit identifier should be sent using this function.
* For example, if the 10-bit address is 0x305, the address should be provided as 0xf6(prepend with 0b11110, upper two bits of address 0b11,
* followed by 1-bit field for read/write).
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n
*/
void XMC_I2C_CH_MasterStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param addr I2C master address
* @param command read/write command
* @return None<br>
*
* \par<b>Description:</b><br>
* Sends the repeated start condition from I2C master \a channel.<br>
*
* \par
* Sends the repeated start condition with read/write command by updating IN/TBUF register based on FIFO/non-FIFO modes.\n
* @note Address(addr) should reserve an additional bit at the LSB for read/write indication. For example, address 0x05 should
* be provided as 0x0a. If the address is 10-bit, only most significant bits with the 10-bit identifier should be sent using this function.
* For example, if the 10-bit address is 0x305, the address should be provided as 0xf6(prepend with 0b11110, upper two bits of address 0b11,
* followed by 1-bit field for read/write).
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n
*/
void XMC_I2C_CH_MasterRepeatedStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return None<br>
*
* \par<b>Description:</b><br>
* Stops the I2C master \a channel.<br>
*
* \par
* Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Stop command.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit(), XMC_USIC_CH_GetTransmitBufferStatus()\n\n
*/
void XMC_I2C_CH_MasterStop(XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param data data to transmit from I2C \a channel
* @return None<br>
*
* \par<b>Description:</b><br>
* Transmit the data from the I2C master \a channel.<br>
*
* \par
* Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Master Send command.
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_GetTransmitBufferStatus()\n\n
*/
void XMC_I2C_CH_MasterTransmit(XMC_USIC_CH_t *const channel, const uint8_t data);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param data data to transmit from I2C \a channel
* @return None<br>
*
* \par<b>Description:</b><br>
* Transmit the data from the I2C slave \a channel.<br>
*
* \par
* Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Slave Send command.
*
* \par<b>Related APIs:</b><br>
* XMC_USIC_CH_GetTransmitBufferStatus(),XMC_I2C_CH_ClearStatusFlag()\n\n
*/
void XMC_I2C_CH_SlaveTransmit(XMC_USIC_CH_t *const channel, const uint8_t data);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return None<br>
*
* \par<b>Description:</b><br>
* Sends the Ack request from I2C master \a channel.<br>
*
* \par
* Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Master Receive Ack command.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit()\n\n
*/
void XMC_I2C_CH_MasterReceiveAck(XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return None<br>
*
* \par<b>Description:</b><br>
* Sends the Nack request from I2C master \a channel.<br>
*
* \par
* Reads the transmit buffer status is busy or not and thereby updates IN/TBUF register based on FIFO/non-FIFO modes using Master Receive Nack command.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit()\n\n
*/
void XMC_I2C_CH_MasterReceiveNack(XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return uint8_t OUTR/RBUF register data<br>
*
* \par<b>Description:</b><br>
* Reads the data from I2C \a channel.<br>
*
* \par
* Data is read by using OUTR/RBUF register based on FIFO/non-FIFO modes.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit()\n\n
*/
uint8_t XMC_I2C_CH_GetReceivedData(const XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return uint8_t Receiver status flag<br>
*
* \par<b>Description:</b><br>
* Gets the receiver status of I2C \a channel using RBUF register of bits 8-12 which gives information about receiver status.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_MasterTransmit()\n\n
*/
__STATIC_INLINE uint8_t XMC_I2C_CH_GetReceiverStatusFlag(XMC_USIC_CH_t *const channel)
{
return((uint8_t)((channel->RBUF) >> 8U));
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param event ORed values of @ref XMC_I2C_CH_EVENT_t enum
* @return None<br>
*
* \par<b>Description:</b><br>
* Enables the input parameter @ref XMC_I2C_CH_EVENT_t event using PCR_IICMode register.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_DisableEvent()\n\n
*/
void XMC_I2C_CH_EnableEvent(XMC_USIC_CH_t *const channel, uint32_t event);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param event ORed values of @ref XMC_I2C_CH_EVENT_t enum
* @return None<br>
*
* \par<b>Description:</b><br>
* Disables the input parameter @ref XMC_I2C_CH_EVENT_t event using PCR_IICMode register.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_EnableEvent()\n\n
*/
void XMC_I2C_CH_DisableEvent(XMC_USIC_CH_t *const channel, uint32_t event);
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return uint32_t Status byte<br>
*
* \par<b>Description:</b><br>
* Retrieves the status byte of I2C \a channel using PSR_IICMode register.\n
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_ClearStatusFlag()\n\n
*/
__STATIC_INLINE uint32_t XMC_I2C_CH_GetStatusFlag(XMC_USIC_CH_t *const channel)
{
return (channel->PSR_IICMode);
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @param flag Status flag
* @return None<br>
*
* \par<b>Description:</b><br>
* Clears the status flag of I2C \a channel by setting the input parameter \a flag in PSCR register.
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_GetStatusFlag()\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, uint32_t flag)
{
channel->PSCR |= flag;
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
* @param pdiv Desired divider for the external frequency input. \b Range: minimum value = 1, maximum value = 1024 \n
* @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data. \n
* This can be related to the number of samples for each logic state of the data signal. \n
* \b Range: 1 to 32. Value should be chosen based on the protocol used.
* @param combination_mode USIC channel input combination mode \n
*
* @return None
*
* \par<b>Description</b><br>
* Enables the external frequency input for the Baudrate Generator and configures the divider, oversampling and
* the combination mode of the USIC channel. \n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode() \n\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel,
const uint16_t pdiv,
const uint32_t oversampling,
const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode)
{
XMC_USIC_CH_ConfigExternalInputSignalToBRG(channel,pdiv,oversampling,combination_mode);
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return None
*
* \par<b>Description:</b><br>
* Retrieves the status byte of I2C \a channel using PSR_IICMode register.\n
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_DisableAcknowledgeAddress0()\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_EnableAcknowledgeAddress0(XMC_USIC_CH_t *const channel)
{
channel->PCR_IICMode |= USIC_CH_PCR_IICMode_ACK00_Msk;
}
/**
* @param channel Constant pointer to USIC channel structure of type @ref XMC_USIC_CH_t
* @return None
*
* \par<b>Description:</b><br>
* This bit defines that slave device should not be sensitive to the slave address 00H.\n
*
* \par<b>Related APIs:</b><br>
* XMC_I2C_CH_EnableAcknowledgeAddress0()\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_DisableAcknowledgeAddress0(XMC_USIC_CH_t *const channel)
{
channel->PCR_IICMode &= ~USIC_CH_PCR_IICMode_ACK00_Msk;
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Enable data transmission.\n\n
* Use this function in combination with XMC_I2C_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
* FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
* @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
*
* \par<b>Related APIs:</b><BR>
* XMC_I2C_CH_DisableDataTransmission()\n\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2C0_CH0, @ref XMC_I2C0_CH1,@ref XMC_I2C1_CH0,@ref XMC_I2C1_CH1,@ref XMC_I2C2_CH0,@ref XMC_I2C2_CH1 @note Availability of I2C1 and I2C2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Disable data transmission.\n\n
* Use this function in combination with XMC_I2C_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
* FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
*
* \par<b>Related APIs:</b><BR>
* XMC_I2C_CH_EnableDataTransmission()\n\n\n
*/
__STATIC_INLINE void XMC_I2C_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

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/**
* @file xmc_i2s.h
* @date 2016-06-30
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-08-21:
* - Initial <br>
*
* 2015-08-24:
* - Added APIs for enabling/disabling delay compensation XMC_I2S_CH_DisableDelayCompensation() and
* XMC_I2S_CH_EnableDelayCompensation() <br>
*
* 2015-09-01:
* - Modified XMC_I2S_CH_SetInputSource() for avoiding complete DXCR register overwriting. <br>
* - Modified XMC_I2S_CH_EVENT_t enum for supporting XMC_I2S_CH_EnableEvent() and XMC_I2S_CH_DisableEvent() <br>
* for supporting multiple events configuration <br>
*
* 2015-09-14:
* - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length<br>
*
* 2016-05-20:
* - Added XMC_I2S_CH_EnableDataTransmission() and XMC_I2S_CH_DisableDataTransmission()
*
* 2016-06-30:
* - Documentation updates.
*
* @endcond
*
*/
#ifndef XMC_I2S_H_
#define XMC_I2S_H_
/**********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_usic.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup I2S
* @brief (IIS) driver for the XMC microcontroller family.
*
* USIC IIS Features: <br>
* @{
*/
/*******************************************************************************
* MACROS
*******************************************************************************/
#if defined(USIC0)
#define XMC_I2S0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */
#define XMC_I2S0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */
#endif
#if defined(USIC1)
#define XMC_I2S1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */
#define XMC_I2S1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */
#endif
#if defined(USIC2)
#define XMC_I2S2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */
#define XMC_I2S2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */
#endif
/*******************************************************************************
* ENUMS
*******************************************************************************/
/**
* @brief I2S Status
*/
typedef enum XMC_I2S_CH_STATUS
{
XMC_I2S_CH_STATUS_OK, /**< Status OK */
XMC_I2S_CH_STATUS_ERROR, /**< Status ERROR */
XMC_I2S_CH_STATUS_BUSY /**< Status BUSY */
} XMC_I2S_CH_STATUS_t;
/**
* @brief I2S status flag
*/
typedef enum XMC_I2S_CH_STATUS_FLAG
{
XMC_I2S_CH_STATUS_FLAG_WORD_ADDRESS = USIC_CH_PSR_IISMode_WA_Msk, /**< Word Address status */
XMC_I2S_CH_STATUS_FLAG_DX2S = USIC_CH_PSR_IISMode_DX2S_Msk, /**< Status of WA input(DX2) signal*/
XMC_I2S_CH_STATUS_FLAG_DX2T_EVENT_DETECTED = USIC_CH_PSR_IISMode_DX2TEV_Msk, /**< Status for WA input signal transition */
XMC_I2S_CH_STATUS_FLAG_WA_FALLING_EDGE_EVENT = USIC_CH_PSR_IISMode_WAFE_Msk, /**< Falling edge of the WA output
signal has been generated */
XMC_I2S_CH_STATUS_FLAG_WA_RISING_EDGE_EVENT = USIC_CH_PSR_IISMode_WARE_Msk, /**< Rising edge of the WA output
signal has been generated */
XMC_I2S_CH_STATUS_FLAG_WA_GENERATION_END = USIC_CH_PSR_IISMode_END_Msk, /**< The WA generation has ended */
XMC_I2S_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_IISMode_RSIF_Msk, /**< Receive start indication status */
XMC_I2S_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_IISMode_DLIF_Msk, /**< Data lost indication status */
XMC_I2S_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_IISMode_TSIF_Msk, /**< Transmit shift indication status */
XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_IISMode_TBIF_Msk, /**< Transmit buffer indication status */
XMC_I2S_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_IISMode_RIF_Msk, /**< Receive indication status */
XMC_I2S_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_IISMode_AIF_Msk, /**< Alternate receive indication status */
XMC_I2S_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_IISMode_BRGIF_Msk /**< Baud rate generator indication status */
} XMC_I2S_CH_STATUS_FLAG_t;
/**
* @brief I2S Baudrate Generator shift clock output
*/
typedef enum XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT
{
XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK, /**< Baudrate Generator shift clock output: SCLK*/
XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 = XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1 /**< Clock obtained as input from master: DX1*/
} XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t;
/**
* @brief I2S channel interrupt node pointers
*/
typedef enum XMC_I2S_CH_INTERRUPT_NODE_POINTER
{
XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */
XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */
XMC_I2S_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */
XMC_I2S_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */
XMC_I2S_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */
} XMC_I2S_CH_INTERRUPT_NODE_POINTER_t;
/**
* @brief I2S events
*/
typedef enum XMC_I2S_CH_EVENT
{
XMC_I2S_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */
XMC_I2S_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */
XMC_I2S_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */
XMC_I2S_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */
XMC_I2S_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */
XMC_I2S_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */
XMC_I2S_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */
XMC_I2S_CH_EVENT_WA_FALLING_EDGE = USIC_CH_PCR_IISMode_WAFEIEN_Msk << 2U, /**< WA falling edge event */
XMC_I2S_CH_EVENT_WA_RISING_EDGE = USIC_CH_PCR_IISMode_WAREIEN_Msk << 2U, /**< WA rising edge event */
XMC_I2S_CH_EVENT_WA_GENERATION_END = USIC_CH_PCR_IISMode_ENDIEN_Msk << 2U, /**< END event */
XMC_I2S_CH_EVENT_DX2TIEN_ACTIVATED = USIC_CH_PCR_IISMode_DX2TIEN_Msk << 2U /**< WA input signal transition event*/
} XMC_I2S_CH_EVENT_t;
/**
* @brief Defines the Polarity of the WA in the SELO output lines in relation to the internal WA signal.
*/
typedef enum XMC_I2S_CH_WA_POLARITY
{
XMC_I2S_CH_WA_POLARITY_DIRECT = 0x0UL, /**< The SELO outputs have the same polarity
as the WA signal (active high) */
XMC_I2S_CH_WA_POLARITY_INVERTED = 0x1UL << USIC_CH_PCR_IISMode_SELINV_Pos /**< The SELO outputs have the inverted
polarity to the WA signal (active low)*/
} XMC_I2S_CH_WA_POLARITY_t;
/**
* @brief Defines the Polarity of the WA in the SELO output lines in relation to the internal WA signal.
*/
typedef enum XMC_I2S_CH_CHANNEL
{
XMC_I2S_CH_CHANNEL_1_LEFT = 0U, /**< Channel 1 (left) */
XMC_I2S_CH_CHANNEL_2_RIGHT = 1U /**< Channel 2 (right) */
} XMC_I2S_CH_CHANNEL_t;
/**
* @brief I2S input stage selection
*/
typedef enum XMC_I2S_CH_INPUT
{
XMC_I2S_CH_INPUT_DIN0 = 0UL, /**< Data input stage 0 */
XMC_I2S_CH_INPUT_SLAVE_SCLKIN = 1UL, /**< Clock input stage */
XMC_I2S_CH_INPUT_SLAVE_WA = 2UL, /**< WA input stage */
#if UC_FAMILY == XMC1
XMC_I2S_CH_INPUT_DIN1 = 3UL, /**< Data input stage 1 */
XMC_I2S_CH_INPUT_DIN2 = 4UL, /**< Data input stage 2 */
XMC_I2S_CH_INPUT_DIN3 = 5UL /**< Data input stage 3 */
#endif
} XMC_I2S_CH_INPUT_t;
/**
* @brief Defines the I2S bus mode
*/
typedef enum XMC_I2S_CH_BUS_MODE
{
XMC_I2S_CH_BUS_MODE_MASTER, /**< I2S Master */
XMC_I2S_CH_BUS_MODE_SLAVE /**< I2S Slave */
} XMC_I2S_CH_BUS_MODE_t;
/*******************************************************************************
* DATA STRUCTURES
*******************************************************************************/
/**
* @brief I2S_CH configuration structure
*/
typedef struct XMC_I2S_CH_CONFIG
{
uint32_t baudrate; /**< Module baud rate for communication */
uint8_t data_bits; /**< Data word length. A data frame can consists of several data words. \n
Value configured as USIC channel word length. \n
\b Range: minimum= 1, maximum= 16*/
uint8_t frame_length; /**< Number of data bits transferred after a change of signal WA (data frame). \n
Configured as USIC channel frame length. \n
\b Range: minimum= 1, maximum= 63*/
uint8_t data_delayed_sclk_periods; /**< Data delay defined in sclk periods */
XMC_I2S_CH_WA_POLARITY_t wa_inversion; /**< Enable inversion of Slave select signal relative to the internal WA */
XMC_I2S_CH_BUS_MODE_t bus_mode; /**< Bus mode MASTER/SLAVE */
} XMC_I2S_CH_CONFIG_t;
/*******************************************************************************
* API PROTOTYPES
*******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, XMC_I2S0_CH1,XMC_I2S1_CH0, XMC_I2S1_CH1,XMC_I2S2_CH0, XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @param config Constant pointer to I2S configuration structure of type @ref XMC_I2S_CH_CONFIG_t.
* @return XMC_I2S_CH_STATUS_t Status of initializing the USIC channel for I2S protocol.\n
* \b Range: @ref XMC_I2S_CH_STATUS_OK if initialization is successful.\n
* @ref XMC_I2S_CH_STATUS_ERROR if configuration of baudrate failed.
*
* \par<b>Description</b><br>
* Initializes the USIC channel for I2S protocol.\n\n
* During the initialization, USIC channel is enabled and baudrate is configured.
* After each change of the WA signal, a complete data frame is intended to be transferred (frame length <= system word length).
* The number of data bits transferred after a change of signal WA is defined by config->frame_length.
* A data frame can consist of several data words with a data word length defined by config->data_bits.
* The changes of signal WA define the system word length as the number of SCLK cycles between two changes of WA.
* The system word length is set by default to the frame length defined by config->frame_length.
*
* XMC_I2S_CH_Start() should be invoked after the initialization to enable the channel.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_Start(), XMC_I2S_CH_Stop(), XMC_I2S_CH_Transmit(), XMC_I2S_CH_SetSystemWordLength()\n\n\n
*/
void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return None
*
* \par<b>Description:</b><br>
* Set the selected USIC channel to operate in I2S mode, by setting CCR.MODE bits.\n\n
* It should be executed after XMC_I2S_CH_Init() during initialization. By invoking XMC_I2S_CH_Stop(), the MODE is set
* to IDLE state. Call XMC_I2S_CH_Start() to set the I2S mode again, as needed later in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_Init(), XMC_I2S_CH_Stop()
*/
__STATIC_INLINE void XMC_I2S_CH_Start(XMC_USIC_CH_t *const channel)
{
/* USIC channel in I2S mode */
XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_I2S);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for stopping is processed. \n
* XMC_I2S_CH_STATUS_OK- If the USIC channel is successfully put to IDLE mode. \n
* XMC_I2S_CH_STATUS_BUSY- If the USIC channel is busy transmitting data.
*
* \par<b>Description:</b><br>
* Set the selected I2S channel to IDLE mode, by clearing CCR.MODE bits.\n\n
* After calling XMC_I2S_CH_Stop, channel is IDLE mode. So no communication is supported. XMC_I2S_CH_Start() has to be
* invoked to start the communication again.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_Start()
*/
XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param rate Bus speed in bits per second
*
* @return XMC_I2S_CH_STATUS_t Status of the I2S driver after the request for setting baudrate is processed. \n
* XMC_I2S_CH_STATUS_OK- If the baudrate is successfully changed. \n
* XMC_I2S_CH_STATUS_ERROR- If the new baudrate value is out of range.
*
* \par<b>Description:</b><br>
* Sets the bus speed in bits per second
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_Init(), XMC_I2S_CH_Stop()
*/
XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param sclk_cycles_system_word_length system word length in terms of sclk clock cycles.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures the system word length by setting BRG.DCTQ bit field.\n\n
* This value has to be always higher than 1U and lower than the data with (SCTR.FLE)
*
*/
void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_length);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param data Data to be transmitted
* @param channel_number Communication output channel of the I2S, based on this channel selection TCI(Transmit control information)is updated.\n
* Refer @ref XMC_I2S_CH_CHANNEL_t for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Puts the data into FIFO, if FIFO mode is enabled or else into standard buffer, by setting the proper mode.\n\n
* TCI(Transmit Control Information) allows dynamic control of output channel during data transfers. To support this auto
* update, TCSR.WAMD(Automatic WA mode) will be enabled during the initialization using XMC_I2S_CH_Init() for all modes.
*
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_Receive()
*/
void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_I2S_CH_CHANNEL_t channel_number);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param channel_number Communication output channel of the I2S, based on this mode TCI(Transmit control information)is updated.\n
* Refer @ref XMC_I2S_CH_CHANNEL_t for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Transmits a dummy data(FFFFH) to provide clock for slave and receives the data from the slave.\n\n
* XMC_I2S_CH_Receive() receives the data and places it into buffer based on the FIFO selection. After reception of data
* XMC_I2S_CH_GetReceivedData() can be invoked to read the data from the buffers.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_GetReceivedData()
*/
__STATIC_INLINE void XMC_I2S_CH_Receive(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CHANNEL_t channel_number)
{
/* Transmit dummy data */
XMC_I2S_CH_Transmit(channel, (uint16_t)0xffffU , channel_number);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return uint16_t Data read from the receive buffer.
*
* \par<b>Description:</b><br>
* Reads data from the receive buffer based on the FIFO selection.\n\n
* Invocation of XMC_I2S_CH_Receive() receives the data and place it into receive buffer. After receiving the data
* XMC_I2S_CH_GetReceivedData() can be used to read the data from the buffer.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_Receive()
*/
uint16_t XMC_I2S_CH_GetReceivedData(XMC_USIC_CH_t *const channel);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return None
*
* \par<b>Description:</b><br>
* Set the order of data transfer from LSB to MSB, by clearing SCTR.SDIR bit.\n\n
* This is typically based on the slave settings. Invoke XMC_I2S_CH_SetBitOrderLsbFirst() to set direction as needed in
* the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_SetBitOrderMsbFirst()
*/
__STATIC_INLINE void XMC_I2S_CH_SetBitOrderLsbFirst(XMC_USIC_CH_t *const channel)
{
channel->SCTR &= (uint32_t)~USIC_CH_SCTR_SDIR_Msk;
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return None
*
* \par<b>Description:</b><br>
* Set the order of data transfer from MSB to LSB, by setting SCTR.SDIR bit.\n\n
* This is typically based on the slave settings. This is not set during XMC_I2S_CH_Init().
* Invoke XMC_I2S_CH_SetBitOrderMsbFirst() to set direction as needed in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_SetBitOrderLsbFirst()
*/
__STATIC_INLINE void XMC_I2S_CH_SetBitOrderMsbFirst(XMC_USIC_CH_t *const channel)
{
channel->SCTR |= (uint32_t)USIC_CH_SCTR_SDIR_Msk;
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param event Protocol events which have to be enabled.
* Refer @ XMC_I2S_CH_EVENT_t for valid values. <b>OR</b> combinations of these enum items can be used
* as input.
*
* @return None
*
* \par<b>Description:</b><br>
* Enables the I2S protocol specific events, by configuring PCR register.\n\n
* Events can be enabled as needed using XMC_I2S_CH_EnableEvent().
* XMC_I2S_CH_DisableEvent() can be used to disable the events.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_DisableEvent()
*/
void XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param event Protocol events which have to be disabled.
* Refer @ XMC_I2S_CH_EVENT_t for valid values. <b>OR</b> combinations of these enum item can be used
* as input.
*
* @return None
*
* \par<b>Description:</b><br>
* Disables the I2S protocol specific events, by configuring PCR register.\n\n
* After disabling the events, XMC_I2S_CH_EnableEvent() has to be invoked to re-enable the events.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_EnableEvent()
*/
void XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return uint32_t Status of I2S protocol events.
*
* \par<b>Description:</b><br>
* Returns the status of the events, by reading PSR register.\n\n
* This indicates the status of the all the events, for I2S communication.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_ClearStatusFlag()
*/
__STATIC_INLINE uint32_t XMC_I2S_CH_GetStatusFlag(XMC_USIC_CH_t *const channel)
{
return channel->PSR_IISMode;
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param flag Protocol event status to be cleared for detection of next occurence.
* Refer @ XMC_I2S_CH_STATUS_FLAG_t for valid values. <b>OR</b> combinations of these enum item can be used
* as input.
* @return None
*
* \par<b>Description:</b><br>
* Clears the events specified, by setting PSCR register.\n\n
* During communication the events occurred have to be cleared to detect their next occurence.\n
* e.g: During transmission Transmit buffer event occurs to indicating data word transfer has started. This
* event has to be cleared after transmission of each data word. Otherwise next event cannot be recognized.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_GetStatusFlag()
*/
__STATIC_INLINE void XMC_I2S_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag)
{
channel->PSCR |= flag;
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return None
*
* \par<b>Description:</b><br>
* Enables the generation of Master clock by setting PCR.MCLK bit.\n\n
* This clock can be used as a clock reference for external devices. This is not enabled during initialization in
* XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_EnableMasterClock() to enable as needed in the program, or if it is disabled by
* XMC_I2S_CH_DisableMasterClock().
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_DisableMasterClock()
*/
__STATIC_INLINE void XMC_I2S_CH_EnableMasterClock(XMC_USIC_CH_t *const channel)
{
channel->PCR_IISMode |= (uint32_t)USIC_CH_PCR_IISMode_MCLK_Msk;
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
*
* @return None
*
* \par<b>Description:</b><br>
* Disables the generation of Master clock by clearing PCR.MCLK bit.\n\n
* This clock can be enabled by invoking XMC_I2S_CH_EnableMasterClock() as needed in the program.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_EnableMasterClock()
*/
__STATIC_INLINE void XMC_I2S_CH_DisableMasterClock(XMC_USIC_CH_t *const channel)
{
channel->PCR_IISMode &= (uint32_t)~USIC_CH_PCR_IISMode_MCLK_Msk;
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param clock_output shift clock source.\n
* Refer @ref XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t for valid inputs.
*
* @return None
*
* \par<b>Description:</b><br>
* Configures the shift clock source by setting BRG.SCLKOSEL.\n\n
* In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available
* for external slave devices by SCLKOUT signal.\n
* In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.\n
*/
__STATIC_INLINE void XMC_I2S_CH_ConfigureShiftClockOutput(XMC_USIC_CH_t *const channel,
const XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output)
{
XMC_USIC_CH_ConfigureShiftClockOutput(channel, (XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t)0U,
(XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t)clock_output);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param word_length Number of bits to be configured for a data word. \n
* \b Range: 1 to 16.
*
* @return None
*
* \par<b>Description</b><br>
* Defines the data word length.\n\n
* Sets the number of bits to represent a data word. Frame length should be a multiple of word length.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_SetFrameLength()
*/
__STATIC_INLINE void XMC_I2S_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length)
{
XMC_USIC_CH_SetWordLength(channel, word_length);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param frame_length Number of bits in a frame. \n
* \b Range: 1 to 64.
*
* @return None
*
* \par<b>Description</b><br>
* Define the data frame length.\n\n
* Set the number of bits to be serially transmitted in a frame.
* The frame length should be multiples of word length.
*
* \par<b>Related APIs:</b><BR>
* XMC_USIC_CH_SetWordLength()
*/
__STATIC_INLINE void XMC_I2S_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length)
{
XMC_USIC_CH_SetFrameLength(channel, frame_length);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param input I2S channel input stage.\n
* Refer @ref XMC_I2S_CH_INPUT_t for valid values
* @param source Input source select for the input stage.
* Range : [0 to 7]
*
* @return None
*
* \par<b>Description</b><br>
* Selects the data source for I2S input stage, by configuring DXCR.DSEL bits.\n\n
* Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the
* input stages like DX0CR, DX1CR etc. This is not done during initialization. This has to be configured before starting
* the I2S communication.
*/
__STATIC_INLINE void XMC_I2S_CH_SetInputSource(XMC_USIC_CH_t *const channel,
const XMC_I2S_CH_INPUT_t input,
const uint8_t source)
{
channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~USIC_CH_DX0CR_DSEN_Msk)) | USIC_CH_DX0CR_INSW_Msk;
XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param wa_inversion Polarity of the word address signal.\n
* Refer @ref XMC_I2S_CH_WA_POLARITY_t for valid values
*
* @return None
*
* \par<b>Description</b><br>
* Set the polarity of the word address signal, by configuring PCR.SELINV bit.\n\n
* Normally WA signal is active low level signal. This is configured
* in XMC_I2S_CH_Init() during initialization. Invoke XMC_I2S_CH_WordAddressSignalPolarity() with desired settings as
* needed later in the program.
*/
__STATIC_INLINE void XMC_I2S_CH_WordAddressSignalPolarity(XMC_USIC_CH_t *const channel,
const XMC_I2S_CH_WA_POLARITY_t wa_inversion)
{
/* Configuration of Protocol Control Register */
channel->PCR_IISMode = (uint32_t)((channel->PCR_IISMode & (~USIC_CH_PCR_IISMode_SELINV_Msk)) | (uint32_t)wa_inversion);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param input I2S channel input stage.\n
* Refer @ref XMC_I2S_CH_INPUT_t for valid inputs.
*
* @return None
*
* \par<b>Description</b><br>
* Enables the polarity inversion of input data signal, by setting DXyCR.DPOL(where y = \a input).\n\n
* This is not set in XMC_I2S_CH_Init(). Invoke XMC_I2S_CH_EnableInputInversion() as needed later in the program. To
* disable the inversion XMC_I2S_CH_DisableInputInversion() can be invoked.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_DisableInputInversion()
*/
__STATIC_INLINE void XMC_I2S_CH_EnableInputInversion(XMC_USIC_CH_t *const channel,
const XMC_I2S_CH_INPUT_t input)
{
XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param input I2S channel input stage.\n
* Refer @ref XMC_I2S_CH_INPUT_t for valid inputs.
*
* @return None
*
* \par<b>Description</b><br>
* Disables the polarity inversion of input data signal, by clearing DXyCR.DPOL(where y = \a input).\n\n
* Resets the input data polarity. Invoke XMC_I2S_CH_EnableInputInversion() to apply inversion.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_EnableInputInversion()
*/
__STATIC_INLINE void XMC_I2S_CH_DisableInputInversion(XMC_USIC_CH_t *const channel,
const XMC_I2S_CH_INPUT_t input)
{
XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
* @param service_request Service request number.
Range: [0 to 5]
*
* @return None
*
* \par<b>Description</b><br>
* Sets the interrupt node for I2S channel events.\n\n
* For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
* The NVIC node gets linked to the interrupt event by doing so. This is not configured in XMC_I2S_CH_Init() during
* initialization.
*
* \par<b>Note::</b><BR>
* 1. NVIC node should be separately enabled to generate the interrupt.
*
* \par<b>Related APIs:</b><BR>
* XMC_USIC_CH_EnableEvent()
*/
__STATIC_INLINE void XMC_I2S_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
const uint8_t service_request)
{
XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL, (uint32_t)service_request);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @param interrupt_node Interrupt node pointer to be configured. \n
* \b Range: @ref XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
* @ref XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
* @param service_request Service request number.\n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Sets the interrupt node for USIC channel events. \n\n
* For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
* The NVIC node gets linked to the interrupt event by doing so.<br>
* Note: NVIC node should be separately enabled to generate the interrupt.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_EnableEvent() \n\n\n
*/
__STATIC_INLINE void XMC_I2S_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel,
const XMC_I2S_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
const uint32_t service_request)
{
XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node,
(uint32_t)service_request);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @param service_request_line service request number of the event to be triggered. \n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Trigger a I2S interrupt service request.\n\n
* When the I2S service request is triggered, the NVIC interrupt associated with it will be
* generated if enabled.
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_SelectInterruptNodePointer() \n\n\n
*/
__STATIC_INLINE void XMC_I2S_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line)
{
XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Enables delay compensation. \n\n
*
* Delay compensation can be applied to the receive path.
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_DisableDelayCompensation()\n\n\n
*/
__STATIC_INLINE void XMC_I2S_CH_EnableDelayCompensation(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_EnableDelayCompensation(channel);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Disables delay compensation.. \n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_EnableDelayCompensation()\n\n\n
*/
__STATIC_INLINE void XMC_I2S_CH_DisableDelayCompensation(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_DisableDelayCompensation(channel);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Enable data transmission.\n\n
* Use this function in combination with XMC_I2S_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
* FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
* @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_DisableDataTransmission()\n\n\n
*/
__STATIC_INLINE void XMC_I2S_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_I2S0_CH0, @ref XMC_I2S0_CH1,@ref XMC_I2S1_CH0,@ref XMC_I2S1_CH1,@ref XMC_I2S2_CH0,@ref XMC_I2S2_CH1 @note Availability of I2S1 and I2S2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Disable data transmission.\n\n
* Use this function in combination with XMC_I2S_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
* FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
*
* \par<b>Related APIs:</b><BR>
* XMC_I2S_CH_EnableDataTransmission()\n\n\n
*/
__STATIC_INLINE void XMC_I2S_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* XMC_I2S_H_ */

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/**
* @file xmc_rtc.h
* @date 2016-05-19
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial
*
* 2015-05-20:
* - Documentation updates <br>
* - In xmc1_rtc file XMC_RTC_Init function
* is modified by adding the RTC running condition check
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* 2016-05-19:
* - Added XMC_RTC_SetTimeStdFormat() and XMC_RTC_SetAlarmStdFormat()
*
* @endcond
*
*/
#ifndef XMC_RTC_H
#define XMC_RTC_H
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include <xmc_common.h>
#include <time.h>
/**
*
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup RTC
* @brief RTC driver for XMC microcontroller family.
*
* Real-time clock (RTC) is a clock that keeps track of the current time. Precise
* real time keeping is with a 32.768 KHz external crystal clock or a 32.768 KHz
* high precision internal clock. It provides a periodic time based interrupt and
* a programmable alarm interrupt on time match. It also supports wakeup from
* hibernate.
*
* The RTC low level driver provides functions to configure and initialize the RTC
* hardware peripheral.
*
* @{
*/
/*********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
/*********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* Status return values for RTC low level driver
*/
typedef enum XMC_RTC_STATUS
{
XMC_RTC_STATUS_OK = 0U, /**< Operation successful */
XMC_RTC_STATUS_ERROR = 1U, /**< Operation unsuccessful */
XMC_RTC_STATUS_BUSY = 2U /**< Busy with a previous request */
} XMC_RTC_STATUS_t;
/**
* Events which enables interrupt request generation
*/
typedef enum XMC_RTC_EVENT
{
XMC_RTC_EVENT_PERIODIC_SECONDS = RTC_MSKSR_MPSE_Msk, /**< Mask value to enable an event on periodic seconds */
XMC_RTC_EVENT_PERIODIC_MINUTES = RTC_MSKSR_MPMI_Msk, /**< Mask value to enable an event on periodic seconds */
XMC_RTC_EVENT_PERIODIC_HOURS = RTC_MSKSR_MPHO_Msk, /**< Mask value to enable an event on periodic seconds */
XMC_RTC_EVENT_PERIODIC_DAYS = RTC_MSKSR_MPDA_Msk, /**< Mask value to enable an event on periodic seconds */
XMC_RTC_EVENT_PERIODIC_MONTHS = RTC_MSKSR_MPMO_Msk, /**< Mask value to enable an event on periodic seconds */
XMC_RTC_EVENT_PERIODIC_YEARS = RTC_MSKSR_MPYE_Msk, /**< Mask value to enable an event on periodic seconds */
XMC_RTC_EVENT_ALARM = RTC_MSKSR_MAI_Msk /**< Mask value to enable an event on periodic seconds */
} XMC_RTC_EVENT_t;
/**
* Months used to program the date
*/
typedef enum XMC_RTC_MONTH
{
XMC_RTC_MONTH_JANUARY = 0U,
XMC_RTC_MONTH_FEBRUARY = 1U,
XMC_RTC_MONTH_MARCH = 2U,
XMC_RTC_MONTH_APRIL = 3U,
XMC_RTC_MONTH_MAY = 4U,
XMC_RTC_MONTH_JUNE = 5U,
XMC_RTC_MONTH_JULY = 6U,
XMC_RTC_MONTH_AUGUST = 7U,
XMC_RTC_MONTH_SEPTEMBER = 8U,
XMC_RTC_MONTH_OCTOBER = 9U,
XMC_RTC_MONTH_NOVEMBER = 10U,
XMC_RTC_MONTH_DECEMBER = 11U
} XMC_RTC_MONTH_t;
/**
* Week days used program the date
*/
typedef enum XMC_RTC_WEEKDAY
{
XMC_RTC_WEEKDAY_SUNDAY = 0U,
XMC_RTC_WEEKDAY_MONDAY = 1U,
XMC_RTC_WEEKDAY_TUESDAY = 2U,
XMC_RTC_WEEKDAY_WEDNESDAY = 3U,
XMC_RTC_WEEKDAY_THURSDAY = 4U,
XMC_RTC_WEEKDAY_FRIDAY = 5U,
XMC_RTC_WEEKDAY_SATURDAY = 6U
} XMC_RTC_WEEKDAY_t;
/*********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/*Anonymous structure/union guard start*/
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined(__TASKING__)
#pragma warning 586
#endif
/**
* Alarm time values of RTC <br>
*
* The structure presents a convenient way to set/obtain the
* alarm time values for seconds, minutes, hours, days, month and year of RTC.
* The XMC_RTC_SetAlarm() and XMC_RTC_GetAlarm() can be
* used to populate the structure with the alarm time value of
* RTC
*/
typedef struct XMC_RTC_ALARM
{
union
{
uint32_t raw0;
struct
{
uint32_t seconds : 6; /**< Alarm seconds compare value (0-59: Above this causes this bitfield to be set with 0)*/
uint32_t : 2;
uint32_t minutes : 6; /**< Alarm minutes compare value (0-59: Above this causes this bitfield to be set with 0)*/
uint32_t : 2;
uint32_t hours : 5; /**< Alarm hours compare value (0-23: Above this causes this bitfield to be set with 0)*/
uint32_t : 3;
uint32_t days : 5; /**< Alarm days compare value (0-Actual days of month: Above this causes this bitfield to be set with 0)*/
uint32_t : 3;
};
};
union
{
uint32_t raw1;
struct
{
uint32_t : 8;
uint32_t month : 4; /**< Alarm month compare value (0-11: Above this causes this bitfield to be set with 0) */
uint32_t : 4;
uint32_t year : 16; /**< Alarm year compare value */
};
};
} XMC_RTC_ALARM_t;
/**
* Time values of RTC <br>
*
* The structure presents a convenient way to set/obtain the
* time values for seconds, minutes, hours, days, month and year of RTC.
* The XMC_RTC_SetTime() and XMC_RTC_GetTime() can be
* used to populate the structure with the time value of
* RTC
*/
typedef struct XMC_RTC_TIME
{
union
{
uint32_t raw0;
struct
{
uint32_t seconds : 6; /**< Seconds time value (0-59: Above this causes this bitfield to be set with 0) */
uint32_t : 2;
uint32_t minutes : 6; /**< Minutes time value (0-59: Above this causes this bitfield to be set with 0) */
uint32_t : 2;
uint32_t hours : 5; /**< Hours time value (0-23: Above this causes this bitfield to be set with 0) */
uint32_t : 3;
uint32_t days : 5; /**< Days time value (0-Actual days of month: Above this causes this bitfield to be set with 0)*/
uint32_t : 3;
};
};
union
{
uint32_t raw1;
struct
{
uint32_t daysofweek : 3; /**< Days of week time value (0-6: Above this causes this bitfield to be set with 0) */
uint32_t : 5;
uint32_t month : 4; /**< Month time value (0-11: Above this causes this bitfield to be set with 0) */
uint32_t : 4;
uint32_t year : 16; /**< Year time value */
};
};
} XMC_RTC_TIME_t;
/*Anonymous structure/union guard end*/
#if defined(__CC_ARM)
#pragma pop
#elif defined(__TASKING__)
#pragma warning restore
#endif
/**
* RTC initialization with time, alarm and clock divider(prescaler) configurations <br>
*
* The structure presents a convenient way to set/obtain the time and alarm configurations
* for RTC. The XMC_RTC_Init() can be used to populate the structure with the time and alarm
* values of RTC.
*/
typedef struct XMC_RTC_CONFIG
{
XMC_RTC_TIME_t time;
XMC_RTC_ALARM_t alarm;
uint16_t prescaler;
} XMC_RTC_CONFIG_t;
/*******************************************************************************
* EXTENSIONS
*******************************************************************************/
#if UC_FAMILY == XMC1
#include "xmc1_rtc.h"
#endif
#if UC_FAMILY == XMC4
#include "xmc4_rtc.h"
#endif
/*******************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param config Constant pointer to a constant ::XMC_RTC_CONFIG_t structure containing the
* time, alarm time and clock divider(prescaler) configuration.
* @return XMC_RTC_STATUS_t Always returns XMC_RTC_STATUS_OK (It contains only register assignment statements)
*
* \par<b>Description: </b><br>
* Initialize the RTC peripheral <br>
*
* \par \if XMC4
* The function enables the hibernate domain for accessing RTC peripheral registers, configures
* internal clock divider, time and alarm values by writing to the CTR.DIV, TIM0, TIM1, ATIM0 and
* ATIM1 registers.
* \endif
*
* \if XMC1
* The function ungates the peripheral clock for RTC, configures
* internal clock divider, time and alarm values by writing to the CTR.DIV, TIM0, TIM1, ATIM0 and
* ATIM1 registers.
* \endif
*/
XMC_RTC_STATUS_t XMC_RTC_Init(const XMC_RTC_CONFIG_t *const config);
/**
* @return None
*
* \par<b>Description</b><br>
* Enables RTC peripheral for programming its registers <br>
*
* \par \if XMC4
* Enables the hibernate domain for accessing RTC peripheral registers.
* \endif
*
* \if XMC1
* Ungates the peripheral clock.
* \endif
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Disable(), XMC_SCU_RESET_DeassertPeripheralReset()
*/
void XMC_RTC_Enable(void);
/**
* @return None
*
* \par<b>Description</b><br>
* Disables RTC peripheral for programming its registers <br>
*
* \par \if XMC4
* Empty function (Hibernate domain is not disabled).
* \endif
*
* \if XMC1
* Gates the peripheral clock.
* \endif
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Enable(), XMC_SCU_RESET_AssertPeripheralReset()
*/
void XMC_RTC_Disable(void);
/**
* @return None
*
* \par<b>Description</b><br>
* Checks RTC peripheral is enabled for programming its registers <br>
*
* \par \if XMC4
* Checks the hibernate domain is enabled or not.
* \endif
*
* \if XMC1
* Checks peripheral clock is ungated or not.
* \endif
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Enable(), XMC_RTC_Disable(), XMC_SCU_RESET_DeassertPeripheralReset(),
* XMC_SCU_RESET_AssertPeripheralReset()
*/
bool XMC_RTC_IsEnabled(void);
/**
* @return None
*
* \par<b>Description</b><br>
* Enables RTC peripheral to start counting time <br>
*
* \par
* The function starts the RTC for counting time by setting
* CTR.ENB bit. Before starting the RTC, it should not be in
* running mode and also hibernate domain should be enabled.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Enable(), XMC_RTC_Stop(), XMC_SCU_RESET_DeassertPeripheralReset()
*/
void XMC_RTC_Start(void);
/**
* @return None
*
* \par<b>Description</b><br>
* Disables RTC peripheral to start counting time <br>
*
* \par
* The function stops the RTC for counting time by resetting
* CTR.ENB. Before stopping the RTC, hibernate domain should be enabled.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Enable(), XMC_RTC_Start(), XMC_SCU_RESET_AssertPeripheralReset()
*/
void XMC_RTC_Stop(void);
/**
* @param prescaler Prescaler value to be set
* @return None
*
* \par<b>Description: </b><br>
* Sets the RTC module prescaler value <br>
*
* \par
* The function sets the CTR.DIV bitfield to configure the prescalar value.
* The default value for the prescalar with the 32.768kHz crystal (or the internal clock)
* is 7FFFH for a time interval of 1 sec. Before setting the prescaler value RTC should be
* in stop mode and hibernate domain should be enabled.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Stop(), XMC_RTC_Enable(), XMC_RTC_GetPrescaler()
*/
void XMC_RTC_SetPrescaler(uint16_t prescaler);
/**
* @return None
*
* \par<b>Description: </b><br>
* Gets the RTC module prescaler value <br>
*
* \par
* The function reads the CTR.DIV bitfield to get the prescalar value. The default value
* for the prescalar with the 32.768kHz crystal (or the internal clock) is 7FFFH for a
* time interval of 1 sec.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetPrescaler()
*/
__STATIC_INLINE uint32_t XMC_RTC_GetPrescaler(void)
{
return (uint32_t)(((uint32_t)RTC->CTR & (uint32_t)RTC_CTR_DIV_Msk) >> (uint32_t)RTC_CTR_DIV_Pos);
}
/**
* @param timeval Contstant pointer to a constant ::XMC_RTC_TIME_t structure containing the
* time parameters seconds, minutes, hours, days, daysofweek, month and year.
* @return None
*
* \par<b>Description: </b><br>
* Sets the RTC module time values <br>
*
* \par
* The function sets the TIM0, TIM1 registers with time values.
* The values can only be written when RTC is disabled.
* See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters. <br>
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_GetTime(), XMC_RTC_Stop()
*/
void XMC_RTC_SetTime(const XMC_RTC_TIME_t *const timeval);
/**
* @param time Pointer to a constant ::XMC_RTC_TIME_t structure containing the time parameters
* seconds, minutes, hours, days, daysofweek, month and year.
* @return None
*
* \par<b>Description: </b><br>
* Gets the RTC module time value <br>
*
* \par
* The function gets the time values from TIM0, TIM1 registers.
* See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters. <br>
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetTime()
*/
void XMC_RTC_GetTime(XMC_RTC_TIME_t *const time);
/**
* @param stdtime Pointer to a ::tm structure containing the time parameters seconds,
* minutes, hours, days, daysofweek, month, year(since 1900) and days in a
* year in standard format.
* @return None
*
* \par<b>Description: </b><br>
* Sets the RTC module time value in standard format <br>
*
* \par
* The function sets the time values from TIM0, TIM1 registers.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetTime(), XMC_RTC_GetTime()
*/
void XMC_RTC_SetTimeStdFormat(const struct tm *const stdtime);
/**
* @param stdtime Pointer to a constant ::tm structure containing the time parameters seconds,
* minutes, hours, days, daysofweek, month, year(since 1900) and days in a
* year in standard format.
* @return None
*
* \par<b>Description: </b><br>
* Gets the RTC module time value in standard format <br>
*
* \par
* The function gets the time values from TIM0, TIM1 registers.
* See the structure ::XMC_RTC_TIME_t for the valid range of time value parameters. <br>
* For days the valid range is (1 - Actual days of month), year (since 1900) and
* daysinyear (0 -365).
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetTime(), XMC_RTC_GetTime()
*/
void XMC_RTC_GetTimeStdFormat(struct tm *const stdtime);
/**
* @param alarm Constant pointer to a constant ::XMC_RTC_ALARM_t structure containing the
* alarm time parameters alarm seconds, alarm minutes, alarm hours, alarm days,
* alarm daysofweek, alarm month and alarm year.
* @return None
*
* \par<b>Description: </b><br>
* Sets the RTC module alarm time value <br>
*
* \par
* The function sets the ATIM0, ATIM1 registers with alarm time values.
* See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters. <br>
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_GetAlarm()
*/
void XMC_RTC_SetAlarm(const XMC_RTC_ALARM_t *const alarm);
/**
* @param alarm Pointer to a constant ::XMC_RTC_ALARM_t structure containing the
* time parameters alarm seconds, alarm minutes, alarm hours, alarm days,
* alarm daysofweek, alarm month and alarm year.
* @return None
*
* \par<b>Description: </b><br>
* Gets the RTC module alarm time value <br>
*
* \par
* The function gets the alarm time values from ATIM0, ATIM1 registers.
* See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters. <br>
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetAlarm()
*/
void XMC_RTC_GetAlarm(XMC_RTC_ALARM_t *const alarm);
/**
* @param stdtime Pointer to a ::tm structure containing the time parameters alarm seconds,
* alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month,
* alarm year(since 1900) and alarm days in a year in standard format.
* @return None
*
* \par<b>Description: </b><br>
* Sets the RTC module alarm time value in standard format <br>
*
* \par
* The function sets the alarm time values from ATIM0, ATIM1 registers.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetAlarm(), XMC_RTC_GetAlarm()
*/
void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime);
/**
* @param stdtime Pointer to a constant ::tm structure containing the time parameters alarm seconds,
* alarm minutes, alarm hours, alarm days, alarm daysofweek, alarm month,
* alarm year(since 1900) and alarm days in a year in standard format.
* @return None
*
* \par<b>Description: </b><br>
* Gets the RTC module alarm time value in standard format <br>
*
* \par
* The function gets the alarm time values from ATIM0, ATIM1 registers.
* See the structure ::XMC_RTC_ALARM_t for the valid range of alarm time value parameters. <br>
* For days the valid range is (1 - Actual days of month), year (since 1900) and
* daysinyear (0 -365).
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_SetAlarm(), XMC_RTC_GetAlarm()
*/
void XMC_RTC_GetAlarmStdFormat(struct tm *const stdtime);
/**
* @param event A valid RTC event (::XMC_RTC_EVENT_t) or a valid combination of
* logically OR'd events
* @return None
*
* \par<b>Description: </b><br>
* Enable RTC periodic and alarm event(s) <br>
*
* \par
* The function sets the bitfields of MSKSR register to enable interrupt generation
* for requested RTC event(s).
* Setting the masking value for the event(s) containing in the ::XMC_RTC_EVENT_t leads
* to a generation of the interrupt.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_DisableEvent()
*/
void XMC_RTC_EnableEvent(const uint32_t event);
/**
* @param event A valid RTC event (::XMC_RTC_EVENT_t) or a valid combination of
* logically OR'd events
* @return None
*
* \par<b>Description: </b><br>
* Disable RTC periodic and alarm event(s) <br>
*
* \par
* The function resets the bitfields of MSKSR register to disable interrupt generation
* for requested RTC event(s).
* Resetting the masking value for the the event(s) containing in the ::XMC_RTC_EVENT_t blocks
* the generation of the interrupt.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_EnableEvent()
*/
void XMC_RTC_DisableEvent(const uint32_t event);
/**
* @param event A valid RTC event (::XMC_RTC_EVENT_t) or a valid combination of
* logically OR'd events
* @return None
*
* \par<b>Description: </b><br>
* Clears periodic and alarm event(s) status <br>
*
* \par
* The function sets the bitfields of CLRSR register to clear status bits in RAWSTAT and STSSR registers.
* Setting the value for the the RTC event(s) containing in the ::XMC_RTC_EVENT_t clears the
* corresponding status bits in RAWSTAT and STSSR registers.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_GetEventStatus()
*/
void XMC_RTC_ClearEvent(const uint32_t event);
/**
* @return None
*
* \par<b>Description: </b><br>
* Gets the RTC periodic and alarm event(s) status <br>
*
* \par
* The function reads the bitfields of STSSR register
* to get the status of RTC events.
* Reading the value of the register STSSR gives the status of the event(s) containing in the ::XMC_RTC_EVENT_t.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_ClearEvent()
*/
uint32_t XMC_RTC_GetEventStatus(void);
/**
* @return bool true if RTC is running
* false if RTC is not running
*
* \par<b>Description: </b><br>
* Checks the running status of the RTC <br>
*
* \par
* The function reads the bitfield ENB of CTR register
* to get the running status of RTC.
*
* \par<b>Related APIs:</b><br>
* XMC_RTC_Start(), XMC_RTC_Stop()
*/
__STATIC_INLINE bool XMC_RTC_IsRunning(void)
{
return (bool)(RTC->CTR & RTC_CTR_ENB_Msk);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* XMC_RTC_H */

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/**
* @file xmc_scu.h
* @date 2016-03-09
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
* - Documentation improved <br>
* - XMC_ASSERT() hanging issues have fixed for XMC4 devices. <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
* - Removed STATIC_INLINE property for the below APIs and declared as void
* XMC_SCU_INTERRUPT_EnableEvent, XMC_SCU_INTERRUPT_DisableEvent,
* XMC_SCU_INTERRUPT_TriggerEvent, XMC_SCU_INTERUPT_GetEventStatus,
* XMC_SCU_INTERUPT_ClearEventStatus
*
* 2015-11-30:
* - Documentation improved <br>
*
* 2016-03-09:
* - Optimization of write only registers
*
* @endcond
*
*/
#ifndef XMC_SCU_H
#define XMC_SCU_H
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_common.h>
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup SCU
* @brief System Control Unit(SCU) driver for XMC microcontroller family.
*
* System control unit is the SoC power, reset and a clock manager with additional responsibility of
* providing system stability protection and other auxiliary functions.<br>
* SCU provides the following features,
* -# Power control
\if XMC4
* -# Hibernate control
\endif
* -# Reset control
* -# Clock control
* -# Miscellaneous control(boot mode, system interrupts etc.)<br><br>
*
* The SCU driver is divided in to clock control logic, reset control logic, system interrupt control logic
\if XMC4
* , hibernate control logic, trap control logic, parity control logic
\endif
* and miscellaneous control logic.<br>
*
* Clock driver features:
* -# Allows clock configuration using the structure XMC_SCU_CLOCK_CONFIG_t and API XMC_SCU_CLOCK_Init()
\if XMC4
* -# Provides structure XMC_SCU_CLOCK_SYSPLL_CONFIG_t for configuring the system PLL
* -# Allows selection of clock source for system PLL, XMC_SCU_CLOCK_GetSystemPllClockSource()
* -# Provides APIs for configuring different module clock frequencies XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetUsbClockDivider()
* -# Allows selection of clock source for external output, XMC_SCU_CLOCK_SetExternalOutputClockSource()
* -# Provides APIs for enabling external high power oscillator and ultra low power oscillator, XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_EnableLowPowerOscillator()
* -# Provides APIs for getting various clock frequencies XMC_SCU_CLOCK_GetPeripheralClockFrequency(),
XMC_SCU_CLOCK_GetCpuClockFrequency(), XMC_SCU_CLOCK_GetSystemClockFrequency()<br>
\endif
\if XMC1
* -# Allows selection of peripheral clock frequency, XMC_SCU_CLOCK_SetFastPeripheralClockSource()
* -# Provides API to get the peripheral clock frequency, XMC_SCU_CLOCK_GetFastPeripheralClockFrequency()
\endif
*
* Reset driver features:
\if XMC4
* -# Allows to handle peripheral reset XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset()
* -# Allows configuration of NMI generation for selected events, XMC_SCU_INTERRUPT_EnableNmiRequest()
\endif
\if XMC1
* -# Allows to trigger device reset XMC_SCU_RESET_AssertMasterReset()
* -# Allows to configure multiple sources for reset, XMC_SCU_RESET_EnableResetRequest()
\endif <br>
*
* Interrupt driver features:
* -# Provides APIs for enabling/ disabling interrupt event generation XMC_SCU_INTERRUPT_EnableEvent(),
XMC_SCU_INTERRUPT_DisableEvent()
* -# Provides API for registering callback function for events XMC_SCU_INTERRUPT_SetEventHandler()<br>
*
\if XMC4
* Hibernate driver features:
* -# Allows configuration of hibernate domain XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_DisableHibernateDomain()
* -# Allows selection of standby clock source, XMC_SCU_HIB_SetStandbyClockSource()
* -# Allows selection of RTC clock source, XMC_SCU_HIB_SetRtcClockSource()
* -# Provides API for enabling slow internal clock used for backup clock, XMC_SCU_HIB_EnableInternalSlowClock()<br>
*
* Trap driver features:
* -# Allows handling of trap XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_GetStatus(), XMC_SCU_TRAP_Trigger()<br>
*
* Parity driver features:
* -# Parity error generated by on-chip RAM can be monitored, XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_GetStatus()
* -# Allows configuration of trap generation on detection of parity error, XMC_SCU_PARITY_EnableTrapGeneration()
*
* Power driver features:
* -# Allows to power the USB module XMC_SCU_POWER_EnableUsb(), XMC_SCU_POWER_DisableUsb()
\endif
*
* Miscellaneous features:
* -# Allows to trigger multiple capture compare unit(CCU) channels to be started together XMC_SCU_SetCcuTriggerHigh()
\if XMC4
* -# Enables configuration of out of range comparator (ORC) XMC_SCU_EnableOutOfRangeComparator()
* -# Enables configuration of die temperature sensor XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor()
* -# Enables configuration of device boot mode XMC_SCU_SetBootMode()<br>
\endif
\if XMC1
* -# Enables configuration of die temperature sensor XMC_SCU_StartTempMeasurement(), XMC_SCU_SetRawTempLimits()
* -# Allows configuring supply monitor unit using the structure XMC_SCU_SUPPLYMONITOR_t and API XMC_SCU_SupplyMonitorInit()
* -# Allows handling of protected bits XMC_SCU_LockProtectedBits(), XMC_SCU_UnlockProtectedBits()<br>
\endif
* @{
*/
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/**
* Defines the status of SCU API execution, used to verify the SCU related API calls.
*/
typedef enum XMC_SCU_STATUS
{
XMC_SCU_STATUS_OK = 0UL, /**< SCU related operation successfully completed.*/
XMC_SCU_STATUS_ERROR, /**< SCU related operation failed. When API cannot fulfill request, this value is returned. */
XMC_SCU_STATUS_BUSY, /**< Cannot execute the SCU related operation request because
another operation is in progress. \a XMC_SCU_STATUS_BUSY is returned when API is busy
processing another request. */
} XMC_SCU_STATUS_t;
/*********************************************************************************************************************
* DATA TYPES
********************************************************************************************************************/
/**
* Function pointer type used for registering callback functions on SCU event occurrence.
*/
typedef void (*XMC_SCU_INTERRUPT_EVENT_HANDLER_t)(void);
/*********************************************************************************************************************
* DEVICE EXTENSIONS
********************************************************************************************************************/
#if (UC_FAMILY == XMC1)
#include <xmc1_scu.h>
#elif (UC_FAMILY == XMC4)
#include <xmc4_scu.h>
#else
#error "Unspecified chipset"
#endif
/*********************************************************************************************************************
* API Prototypes
********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
*
* @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits
* in the register CCUCON. <br>
* \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be
* combined using \a OR operation.
*
* @return None
*
* \par<b>Description</b><br>
* Generates active edge(low to high) trigger for multiple CCU units at the same time.\n\n
* Before executing this API, all the required CCU timers should configure external start.
* The edge of the start signal should be selected as active edge.
* The input signal for the CCU slice should be selected as SCU input.
* The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig().
* CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering
* the timer using this API.<BR>
* \par<b>Related APIs:</b><BR>
* XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerLow()\n\n\n
*/
__STATIC_INLINE void XMC_SCU_SetCcuTriggerHigh(const uint32_t trigger)
{
SCU_GENERAL->CCUCON |= (uint32_t)trigger;
}
/**
*
* @param trigger CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits
* in the register CCUCON. <br>
* \b Range: Use type @ref XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be
* combined using \a OR operation.
*
* @return None
*
* \par<b>Description</b><br>
* Generates passive edge(high to low) trigger for multiple CCU units at the same time.\n\n
* Before executing this API, all the required CCU timers should configure external start.
* The edge of the start signal should be selected as passive edge.
* The input signal for the CCU slice should be selected as SCU input.
* The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig().
* CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering
* the timer using this API.<BR>
* \par<b>Related APIs:</b><BR>
* XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerHigh()\n\n\n
*/
__STATIC_INLINE void XMC_SCU_SetCcuTriggerLow(const uint32_t trigger)
{
SCU_GENERAL->CCUCON &= (uint32_t)~trigger;
}
/**
*
* @param config Pointer to structure holding the clock prescaler values and divider values for
* configuring clock generators and clock tree.\n
* \b Range: Configure the members of structure @ref XMC_SCU_CLOCK_CONFIG_t for various
* parameters of clock setup.
*
* @return None
*
* \par<b>Description</b><br>
* Initializes clock generators and clock tree.\n\n
* \if XMC1
* Peripheral clock and system clock are configured based on the input configuration \a config.
* The system clock frequency is tuned by configuring the FDIV and IDIV values of CLKCR register.
* The values of FDIV and IDIV can be provided as part of input configuration.
* The PCLK divider determines the ratio of peripheral clock to the system clock.
* The source of RTC clock is set based on the input configuration.
* \a SystemCoreClock variable will be updated with the value of
* system clock frequency. Access to protected bit fields are handled internally.
* \endif
* \if XMC4
* Enables the high precision oscillator(fOHP) input and configures the system and peripheral clock frequencies.
* Based on the system clock source selected in \a config, either fPLL or fOFI will be chosen as system clock.
* Based on PLL mode(normal or prescaler mode) used, PLL ramps up in steps to achieve target frequency.
* The clock dividers for CPU, CCU and peripheral clocks will be set based on the input configuration.
* The \a SystemCoreClock variable is set with the value of system clock frequency.
* \endif
* \par<b>Related APIs:</b><BR>
* XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GetCpuClockFrequency() \n\n\n
*/
void XMC_SCU_CLOCK_Init(const XMC_SCU_CLOCK_CONFIG_t *const config);
/**
*
* @param event Bit mask of the event to enable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t
* for providing the input value. Multiple events can be combined using the \a OR operation.
*
* @return None
*
* \par<b>Description</b><br>
* Enables the generation of interrupt for the input events.\n\n
* The events are enabled by setting the respective bit fields in the SRMSK register. \n
* Note: User should separately enable the NVIC node responsible for handling the SCU interrupt.
* The interrupt will be generated when the respective event occurs.
* \par<b>Related APIs:</b><BR>
* NVIC_EnableIRQ(), XMC_SCU_INTERRUPT_DisableEvent()\n\n\n
*/
void XMC_SCU_INTERRUPT_EnableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
/**
*
* @param event Bit mask of the event to disable. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t
* for providing the input value. Multiple events can be combined using the \a OR operation.
*
* @return None
*
* \par<b>Description</b><br>
* Disables generation of interrupt on occurrence of the input event.\n\n
* The events are disabled by resetting the respective bit fields in the SRMSK register. \n
* \par<b>Related APIs:</b><BR>
* NVIC_DisableIRQ(), XMC_SCU_INTERRUPT_EnableEvent()\n\n\n
*/
void XMC_SCU_INTERRUPT_DisableEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
/**
*
* @param event Bit mask of the event to be triggered. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t
* for providing the input value. Multiple events can be combined using the \a OR operation.
*
* @return None
*
* \par<b>Description</b><br>
* Triggers the event as if the hardware raised it.\n\n
* Event will be triggered by setting the respective bitfield in the SRSET register.\n
* Note: User should enable the NVIC node that handles the respective event for interrupt generation.
* \par<b>Related APIs:</b><BR>
* NVIC_EnableIRQ(), XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_ClearEventStatus() \n\n\n
*/
void XMC_SCU_INTERRUPT_TriggerEvent(const XMC_SCU_INTERRUPT_EVENT_t event);
/**
* @return uint32_t Status of the SCU events.
*
* \par<b>Description</b><br>
* Provides the status of all SCU events.\n\n
* The status is read from the SRRAW register. To check the status of a particular
* event, the returned value should be masked with the bit mask of the event. The bitmask
* of events can be obtained using the type @ref XMC_SCU_INTERRUPT_EVENT_t. Multiple events'
* status can be checked by combining the bit masks using \a OR operation.
* After detecting the event, the event status should be cleared using software to detect the event again.
* \par<b>Related APIs:</b><BR>
* XMC_SCU_INTERRUPT_ClearEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n
*/
XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus(void);
/**
*
* @param event Bit mask of the events to clear. \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t
* for providing the input value. Multiple events can be combined using the \a OR operation.
*
* @return None
*
* \par<b>Description</b><br>
* Clears the event status bit in SRRAW register.\n\n
* The events are cleared by writing value 1 to their bit positions in the SRCLR register.
* The API can be used when polling method is used. After detecting the event, the event status
* should be cleared using software to detect the event again.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent() \n\n\n
*/
void XMC_SCU_INTERRUPT_ClearEventStatus(const XMC_SCU_INTERRUPT_EVENT_t event);
/**
*
* @return uint32_t Status representing the reason for device reset.
*
* \par<b>Description</b><br>
* Provides the value representing the reason for device reset.\n\n
* The return value is an encoded word, which can indicate multiple reasons for the last reset. Each bit position of the
* returned word is representative of a last reset cause. The returned value should be appropriately masked to check
* the cause of reset.
* The cause of the last reset gets automatically stored in
* the \a SCU_RSTSTAT register. The reset status shall be reset after each
* startup in order to ensure consistent source indication after the next reset.
* \b Range: The type @ref XMC_SCU_RESET_REASON_t can be used to get the bit masks of the reset cause.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_RESET_ClearDeviceResetReason() \n\n\n
*/
__STATIC_INLINE uint32_t XMC_SCU_RESET_GetDeviceResetReason(void)
{
return ((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_RSTSTAT_Msk);
}
/**
* @return None
*
* \par<b>Description</b><br>
* Clears the reset reason bits in the reset status register. \n\n
* Clearing of the reset status information in the \a SCU_RSTSTAT register via register bit \a RSTCLR.RSCLR is strongly
* recommended to ensure a clear indication of the cause of next reset.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_RESET_GetDeviceResetReason() \n\n\n
*/
__STATIC_INLINE void XMC_SCU_RESET_ClearDeviceResetReason(void)
{
/* Clear RSTSTAT.RSTSTAT bitfield */
SCU_RESET->RSTCLR = (uint32_t)SCU_RESET_RSTCLR_RSCLR_Msk;
}
/**
* @return uint32_t Value of CPU clock frequency.
*
* \par<b>Description</b><br>
* Provides the vlaue of CPU clock frequency.\n\n
* The value is stored in a global variable \a \b SystemCoreClock.
* It is updated when the clock configuration is done using the SCU LLD APIs.
* The value represents the frequency of clock used for CPU operation.
* \b Range: Value is of type uint32_t, and gives the value of frequency in Hertz.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
*/
__STATIC_INLINE uint32_t XMC_SCU_CLOCK_GetCpuClockFrequency(void)
{
return SystemCoreClock;
}
/**
* @return uint32_t Value of peripheral clock frequency in Hertz.
*
* \par<b>Description</b><br>
* Provides the vlaue of clock frequency at which the peripherals are working.\n\n
* The value is derived from the CPU frequency. \b Range: Value is of type uint32_t. It is represented in Hertz.
* \par<b>Related APIs:</b><BR>
* XMC_SCU_CLOCK_GetCpuClockFrequency(),XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
*/
uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency(void);
#if(UC_SERIES != XMC45)
/**
*
* @param peripheral The peripheral for which the clock has to be gated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t
* to identify the peripheral clock to be gated.
*
* @return None
*
* \par<b>Description</b><br>
* Blocks the supply of clock to the selected peripheral.\n\n
* Clock gating helps in reducing the power consumption. User can selectively gate the clocks of unused peripherals.
* \if XMC1
* fPCLK is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks
* the clock supply for the selected peripheral.
* Software can request for individual gating of such peripheral clocks by enabling the \a SCU_CGATSET0
* register bit field. Every bit in \a SCU_CGATSET0 register is protected by the bit protection scheme. Access to protected
* bit fields are handled internally.
* \endif
* \if XMC4
* fPERI is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks
* the clock supply for the selected peripheral.
* Software can request for individual gating of such peripheral clocks by enabling one of the \a
* SCU_CGATSET0, \a SCU_CGATSET1 or \a SCU_CGATSET2 register bitfields.
*
* \endif
* Note: Clock gating shall not be activated unless the module is in reset state. So use \a
* XMC_SCU_CLOCK_IsPeripheralClockGated() API before enabling the gating of any peripheral.
* \par<b>Related APIs:</b><BR>
* XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_UngatePeripheralClock() \n\n\n
*/
void XMC_SCU_CLOCK_GatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);
/**
*
* @param peripheral The peripheral for which the clock has to be ungated. \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t
* to identify the peripheral.
*
* @return None
*
* \par<b>Description</b><br>
* Enables the supply of clock to the selected peripheral.\n\n
* By default when the device powers on, the peripheral clock will be gated for the
* peripherals that support clock gating.
* The peripheral clock should be enabled before using it for any functionality.
* \if XMC1
* fPCLK is the source of clock to various peripherals. Some peripherals support clock gate.
* Software can request for individual ungating of such peripheral clocks by setting respective bits
* in the \a SCU_CGATCLR0 register.
* \endif
* \if XMC4
* fPERI is the source of clock to various peripherals. Some peripherals support clock gate.
* Software can request for individual ungating of such peripheral clocks by setting the respective bits in one of \a
* SCU_CGATCLR0, \a SCU_CGATCLR1 or \a SCU_CGATCLR2 registers.
* \endif
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
*/
void XMC_SCU_CLOCK_UngatePeripheralClock(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);
/**
*
* @param peripheral The peripheral for which the check for clock gating has to be done.
* \b Range: Use type @ref XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral.
*
* @return bool Status of the peripheral clock gating. \b Range: true if the peripheral clock is gated.
* false if the peripheral clock ungated(gate de-asserted).
*
* \par<b>Description</b><br>
* Gives the status of peripheral clock gating.\n\n
* \if XMC1
* Checks the status of peripheral clock gating using the register CGATSTAT0.
* \endif
* \if XMC4
* Checks the status of peripheral clock gating using one of CGATSTAT0, CGATSTAT1 or CGATSTAT2 registers.
* \endif
* It is recommended to use this API before
* enabling the gating of any peripherals through \a XMC_SCU_CLOCK_GatePeripheralClock() API.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_CLOCK_UngatePeripheralClock(), XMC_SCU_CLOCK_GatePeripheralClock() \n\n\n
*/
bool XMC_SCU_CLOCK_IsPeripheralClockGated(const XMC_SCU_PERIPHERAL_CLOCK_t peripheral);
#endif
/**
* @return uint32_t Status of the register mirror update.\n
* \b Range: Use the bit mask of the SCU_GENERAL_MIRRSTS register for the mirror update event of
* interest. e.g.: SCU_GENERAL_MIRRSTS_RTC_CTR_Msk. Multiple update events can be combined
* using \a OR operation.
*
* \par<b>Description</b><br>
* Provides the status of hibernate domain register update, when the respective mirror registers are changed. \n\n
* The hibernate domain is connected to the core domain via SPI serial communication. MIRRSTS is a status register
* representing the communication of changed value of a mirror register to its corresponding register in the
* hibernate domain. The bit fields of the register indicate
* that a corresponding register of the hibernate domain is ready to accept a write or that the communication interface
* is busy with executing the previous operation.\n
* Note: There is no hibernate domain in XMC1x devices. This register is retained for legacy purpose.
*/
__STATIC_INLINE uint32_t XMC_SCU_GetMirrorStatus(void)
{
return(SCU_GENERAL->MIRRSTS);
}
/**
* @param event The event for which the interrupt handler is to be configured. \n
* \b Range: Use type @ref XMC_SCU_INTERRUPT_EVENT_t for identifying the event.
* @param handler Name of the function to be executed when the event if detected. \n
* \b Range: The function accepts no arguments and returns no value.
* @return XMC_SCU_STATUS_t Status of configuring the event handler function for the selected event.\n
* \b Range: \a XMC_SCU_STATUS_OK if the event handler is successfully configured.\n
* \a XMC_SCU_STATUS_ERROR if the input event is invalid.\n
* \par<b>Description</b><br>
* Assigns the event handler function to be executed on occurrence of the selected event.\n\n
* If the input event is valid, the handler function will be assigned to a table to be executed
* when the interrupt is generated and the event status is set in the event status register. By using this API,
* polling for a particular event can be avoided. This way the CPU utilization will be optimized. Multiple SCU events
* can generate a common interrupt. When the interrupt is generated, a common interrupt service routine is executed.
* It checks for status flags of events which can generate the interrupt. The handler function will be executed if the
* event flag is set.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERUPT_GetEventStatus() \n\n\n
*/
XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler(const XMC_SCU_INTERRUPT_EVENT_t event, const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler);
/**
* @param sr_num Service request number identifying the SCU interrupt generated.\n
* \b Range: 0 to 2. XMC4x devices have one common SCU interrupt, so the value should be 0.\n
* But XMC1x devices support 3 interrupt nodes.
* @return None
* \par<b>Description</b><br>
* A common function to execute callback functions for multiple events.\n\n
* It checks for the status of events which can generate the interrupt with the selected service request.
* If the event is set, the corresponding callback function will be executed. It also clears the event status bit.\n
* \b Note: This is an internal function. It should not be called by the user application.
*
* \par<b>Related APIs:</b><BR>
* XMC_SCU_INTERRUPT_SetEventHandler() \n\n\n
*/
void XMC_SCU_IRQHandler(uint32_t sr_num);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* SCU_H */

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/**
* @file xmc_uart.h
* @date 2016-05-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial
*
* 2015-05-20:
* - Description updated <br>
* - Added XMC_UART_CH_TriggerServiceRequest() and XMC_UART_CH_SelectInterruptNodePointer <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
*
* 2015-09-01:
* - Modified XMC_UART_CH_SetInputSource() for avoiding complete DXCR register overwriting. <br>
* - Modified XMC_UART_CH_EVENT_t enum for supporting XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent()
* for supporting multiple events configuration <br>
*
* 2016-05-20:
* - Added XMC_UART_CH_EnableDataTransmission() and XMC_UART_CH_DisableDataTransmission()
*
* @endcond
*
*/
#ifndef XMC_UART_H
#define XMC_UART_H
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_usic.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup UART
* @brief Universal Asynchronous Receiver/Transmitter (UART) driver for XMC microcontroller family.
*
* The UART driver uses Universal Serial Interface Channel(USIC) module to implement UART protocol.
* It provides APIs to configure USIC channel for UART communication. The driver enables the user
* in getting the status of UART protocol events, configuring interrupt service requests, protocol
* related parameter configuration etc.
*
* UART driver features:
* -# Configuration structure XMC_UART_CH_CONFIG_t and initialization function XMC_UART_CH_Init()
* -# Enumeration of events with their bit masks @ref XMC_UART_CH_EVENT_t, @ref XMC_UART_CH_STATUS_FLAG_t
* -# Allows the selection of input source for the DX0 input stage using the API XMC_UART_CH_SetInputSource()
* -# Allows configuration of baudrate using XMC_UART_CH_SetBaudrate() and configuration of data length using
XMC_UART_CH_SetWordLength() and XMC_UART_CH_SetFrameLength()
* -# Provides the status of UART protocol events, XMC_UART_CH_GetStatusFlag()
* -# Allows transmission of data using XMC_UART_CH_Transmit() and gets received data using XMC_UART_CH_GetReceivedData()
*
* @{
*/
/*********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#if defined(USIC0)
#define XMC_UART0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */
#define XMC_UART0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */
#endif
#if defined(USIC1)
#define XMC_UART1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */
#define XMC_UART1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */
#endif
#if defined(USIC2)
#define XMC_UART2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */
#define XMC_UART2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */
#endif
/*********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* UART driver status
*/
typedef enum XMC_UART_CH_STATUS
{
XMC_UART_CH_STATUS_OK, /**< UART driver status : OK*/
XMC_UART_CH_STATUS_ERROR, /**< UART driver status : ERROR */
XMC_UART_CH_STATUS_BUSY /**< UART driver status : BUSY */
} XMC_UART_CH_STATUS_t;
/**
* UART portocol status. The enum values can be used for getting the status of UART channel.
*
*/
typedef enum XMC_UART_CH_STATUS_FLAG
{
XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE = USIC_CH_PSR_ASCMode_TXIDLE_Msk, /**< UART Protocol Status transmit IDLE*/
XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE = USIC_CH_PSR_ASCMode_RXIDLE_Msk, /**< UART Protocol Status receive IDLE*/
XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED = USIC_CH_PSR_ASCMode_SBD_Msk, /**< UART Protocol Status synchronization break detected*/
XMC_UART_CH_STATUS_FLAG_COLLISION_DETECTED = USIC_CH_PSR_ASCMode_COL_Msk, /**< UART Protocol Status collision detected*/
XMC_UART_CH_STATUS_FLAG_RECEIVER_NOISE_DETECTED = USIC_CH_PSR_ASCMode_RNS_Msk, /**< UART Protocol Status receiver noise detected */
XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_0 = USIC_CH_PSR_ASCMode_FER0_Msk, /**< UART Protocol Status format error in stop bit 0 */
XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_1 = USIC_CH_PSR_ASCMode_FER1_Msk, /**< UART Protocol Status format error in stop bit 1 */
XMC_UART_CH_STATUS_FLAG_RECEIVE_FRAME_FINISHED = USIC_CH_PSR_ASCMode_RFF_Msk, /**< UART Protocol Status receive frame finished */
XMC_UART_CH_STATUS_FLAG_TRANSMITTER_FRAME_FINISHED = USIC_CH_PSR_ASCMode_TFF_Msk, /**< UART Protocol Status transmit frame finished */
XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY = USIC_CH_PSR_ASCMode_BUSY_Msk, /**< UART Protocol Status transfer status busy */
XMC_UART_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_ASCMode_RSIF_Msk, /**< UART Protocol Status receive start indication flag*/
XMC_UART_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_ASCMode_DLIF_Msk, /**< UART Protocol Status data lost indication flag*/
XMC_UART_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_ASCMode_TSIF_Msk, /**< UART Protocol Status transmit shift indication flag*/
XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_ASCMode_TBIF_Msk, /**< UART Protocol Status transmit buffer indication flag*/
XMC_UART_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_ASCMode_RIF_Msk, /**< UART Protocol Status receive indication flag*/
XMC_UART_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_ASCMode_AIF_Msk, /**< UART Protocol Status alternative receive indication flag*/
XMC_UART_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION = USIC_CH_PSR_ASCMode_BRGIF_Msk /**< UART Protocol Status baudrate generator indication flag*/
} XMC_UART_CH_STATUS_FLAG_t;
/**
* UART configuration events. The enums can be used for configuring events using the CCR register.
*/
typedef enum XMC_CH_UART_EVENT
{
XMC_UART_CH_EVENT_RECEIVE_START = USIC_CH_CCR_RSIEN_Msk, /**< Receive start event */
XMC_UART_CH_EVENT_DATA_LOST = USIC_CH_CCR_DLIEN_Msk, /**< Data lost event */
XMC_UART_CH_EVENT_TRANSMIT_SHIFT = USIC_CH_CCR_TSIEN_Msk, /**< Transmit shift event */
XMC_UART_CH_EVENT_TRANSMIT_BUFFER = USIC_CH_CCR_TBIEN_Msk, /**< Transmit buffer event */
XMC_UART_CH_EVENT_STANDARD_RECEIVE = USIC_CH_CCR_RIEN_Msk, /**< Receive event */
XMC_UART_CH_EVENT_ALTERNATIVE_RECEIVE = USIC_CH_CCR_AIEN_Msk, /**< Alternate receive event */
XMC_UART_CH_EVENT_BAUD_RATE_GENERATOR = USIC_CH_CCR_BRGIEN_Msk, /**< Baudrate generator event */
XMC_UART_CH_EVENT_SYNCHRONIZATION_BREAK = USIC_CH_PCR_ASCMode_SBIEN_Msk, /**< Event synchronization break */
XMC_UART_CH_EVENT_COLLISION = USIC_CH_PCR_ASCMode_CDEN_Msk, /**< Event collision */
XMC_UART_CH_EVENT_RECEIVER_NOISE = USIC_CH_PCR_ASCMode_RNIEN_Msk, /**< Event receiver noise */
XMC_UART_CH_EVENT_FORMAT_ERROR = USIC_CH_PCR_ASCMode_FEIEN_Msk, /**< Event format error */
XMC_UART_CH_EVENT_FRAME_FINISHED = USIC_CH_PCR_ASCMode_FFIEN_Msk /**< Event frame finished */
} XMC_UART_CH_EVENT_t;
/**
* UART Input sampling frequency options
*/
typedef enum XMC_UART_CH_INPUT_SAMPLING_FREQ
{
XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH = XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH, /**< Sampling frequency input fperiph*/
XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER = XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER /**< Sampling frequency input fractional divider*/
} XMC_UART_CH_INPUT_SAMPLING_FREQ_t;
/**
* UART input stages
*/
typedef enum XMC_UART_CH_INPUT
{
XMC_UART_CH_INPUT_RXD = 0UL /**< UART input stage DX0*/
#if UC_FAMILY == XMC1
,
XMC_UART_CH_INPUT_RXD1 = 3UL, /**< UART input stage DX3*/
XMC_UART_CH_INPUT_RXD2 = 5UL /**< UART input stage DX5*/
#endif
} XMC_UART_CH_INPUT_t;
/**
* UART channel interrupt node pointers
*/
typedef enum XMC_UART_CH_INTERRUPT_NODE_POINTER
{
XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit shift interrupt */
XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER = XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit buffer interrupt */
XMC_UART_CH_INTERRUPT_NODE_POINTER_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive interrupt */
XMC_UART_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE = XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for alternate receive interrupt */
XMC_UART_CH_INTERRUPT_NODE_POINTER_PROTOCOL = XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol related interrupts */
} XMC_UART_CH_INTERRUPT_NODE_POINTER_t;
/*********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/**
* UART initialization structure
*/
typedef struct XMC_UART_CH_CONFIG
{
uint32_t baudrate; /**< Desired baudrate. \b Range: minimum= 100, maximum= (fPERIPH * 1023)/(1024 * oversampling) */
uint8_t data_bits; /**< Number of bits for the data field. Value configured as USIC channel word length. \n
\b Range: minimum= 1, maximum= 16*/
uint8_t frame_length; /**< Indicates nmber of bits in a frame. Configured as USIC channel frame length. \n
\b Range: minimum= 1, maximum= 63*/
uint8_t stop_bits; /**< Number of stop bits. \b Range: minimum= 1, maximum= 2 */
uint8_t oversampling; /**< Number of samples for a symbol(DCTQ).\b Range: minimum= 1, maximum= 32*/
XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Parity mode. \b Range: @ref XMC_USIC_CH_PARITY_MODE_NONE, @ref XMC_USIC_CH_PARITY_MODE_EVEN, \n
@ref XMC_USIC_CH_PARITY_MODE_ODD*/
} XMC_UART_CH_CONFIG_t;
/*********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1,XMC_UART1_CH0, XMC_UART1_CH1,XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param config Constant pointer to UART configuration structure of type @ref XMC_UART_CH_CONFIG_t.
* @return XMC_UART_CH_STATUS_t Status of initializing the USIC channel for UART protocol.\n
* \b Range: @ref XMC_UART_CH_STATUS_OK if initialization is successful.\n
* @ref XMC_UART_CH_STATUS_ERROR if configuration of baudrate failed.
*
* \par<b>Description</b><br>
* Initializes the USIC channel for UART protocol.\n\n
* During the initialization, USIC channel is enabled, baudrate is configured with the defined oversampling value
* in the intialization structure. If the oversampling value is set to 0 in the structure, the default oversampling of 16
* is considered. Sampling point for each symbol is configured at the half of sampling period. Symbol value is decided by the
* majority decision among 3 samples.
* Word length is configured with the number of data bits. If the value of \a frame_length is 0, then USIC channel frame length
* is set to the same value as word length. If \a frame_length is greater than 0, it is set as the USIC channel frame length.
* Parity mode is set to the value configured for \a parity_mode.
* The USIC channel should be set to UART mode by calling the XMC_UART_CH_Start() API after the initialization.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_Start(), XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n
*/
void XMC_UART_CH_Init(XMC_USIC_CH_t *const channel, const XMC_UART_CH_CONFIG_t *const config);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Sets the USIC channel operation mode to UART mode.\n\n
* CCR register bitfield \a Mode is set to 2(UART mode). This API should be called after configuring
* the USIC channel. Transmission and reception can happen only when the UART mode is set.
* This is an inline function.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_Start(XMC_USIC_CH_t *const channel)
{
channel->CCR = (uint32_t)(((channel->CCR) & (~USIC_CH_CCR_MODE_Msk)) | (uint32_t)XMC_USIC_CH_OPERATING_MODE_UART);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @return XMC_UART_CH_STATUS_t Status to indicate if the communication channel is stopped successfully.\n
* @ref XMC_UART_CH_STATUS_OK if the communication channel is stopped.
* @ref XMC_UART_CH_STATUS_BUSY if the communication channel is busy.
*
* \par<b>Description</b><br>
* Stops the UART communication.\n\n
* CCR register bitfield \a Mode is reset. This disables the communication.
* Before starting the communication again, the channel has to be reconfigured.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_Init() \n\n\n
*/
XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, XMC_UART0_CH1 ,XMC_UART1_CH0, XMC_UART1_CH1, XMC_UART2_CH0, XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param rate Desired baudrate. \n
* \b Range: minimum value = 100, maximum value depends on the peripheral clock frequency\n
* and \a oversampling. Maximum baudrate can be derived using the formula: (fperiph * 1023)/(1024 * oversampling)
* @param oversampling Required oversampling. The value indicates the number of time quanta for one symbol of data.\n
* This can be related to the number of samples for each logic state of the data signal.\n
* \b Range: 4 to 32. Value should be chosen based on the protocol used.
* @return XMC_UART_CH_STATUS_t Status indicating the baudrate configuration.\n
* \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully configured,
* @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or oversampling is invalid.
*
* \par<b>Description:</b><br>
* Sets the bus speed in bits per second.\n\n
* Derives the values of \a STEP and PDIV to arrive at the optimum realistic speed possible.
* \a oversampling is the number of samples to be taken for each symbol of UART protocol.
* Default \a oversampling of 16 is considered if the input \a oversampling is less than 4. It is recommended to keep
* a minimum oversampling of 4 for UART.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_Init(), XMC_UART_CH_Stop()
*/
XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param data Data to be transmitted. \n
* \b Range: 16 bit unsigned data within the range 0 to 65535. Actual size of
* data transmitted depends on the configured number of bits for the UART protocol in the register SCTR.
* @return None
*
* \par<b>Description</b><br>
* Transmits data over serial communication channel using UART protocol.\n\n
* Based on the channel configuration, data is either put to the transmit FIFO or to TBUF register.
* Before putting data to TBUF, the API waits for TBUF to finish shifting its contents to shift register.
* So user can continuously execute the API without checking for TBUF busy status. Based on the number of
* data bits configured, the lower significant bits will be extracted for transmission.
*
* Note: When FIFO is not configured, the API waits for the TBUF to be available.
* This makes the execution a blocking call.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_GetReceivedData() \n\n\n
*/
void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @return uint16_t Received data over UART communication channel.
* \par<b>Description</b><br>
* Provides one word of data received over UART communication channel.\n\n
* Based on the channel configuration, data is either read from the receive FIFO or RBUF register.
* Before returning the value, there is no check for data validity. User should check the appropriate
* data receive flags(standard receive/alternative receive/FIFO standard receive/FIFO alternative receive)
* before executing the API. Reading from an empty receive FIFO can generate a receive error event.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_GetStatusFlag(), XMC_UART_CH_Transmit() \n\n\n
*/
uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param word_length Data word length. \n
* \b Range: minimum= 1, maximum= 16.
* @return None
*
* \par<b>Description</b><br>
* Sets the data word length in number of bits.\n\n
* Word length can range from 1 to 16. It indicates the number of data bits in a data word.
* The value of \a word_length will be decremented by 1 before setting the value to \a SCTR register.
* If the UART data bits is more than 16, then the frame length should be set to the actual number of bits and
* word length should be configured with the number of bits expected in each transaction. For example, if number of data bits
* for UART communication is 20 bits, then the frame length should be set as 20. Word length can be set based on the
* transmit and receive handling. If data is stored as 8bit array, then the word length can be set to 8. In this case,
* a full message of UART data should be transmitted/ received as 3 data words.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_SetFrameLength() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SetWordLength(XMC_USIC_CH_t *const channel, const uint8_t word_length)
{
XMC_USIC_CH_SetWordLength(channel, word_length);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param frame_length Number of data bits in each UART frame. \n
* \b Range: minimum= 1, maximum= 64.
* @return None
*
* \par<b>Description</b><br>
* Sets the number of data bits for UART communication.\n\n
* The frame length is configured by setting the input value to \a SCTR register.
* The value of \a frame_length will be decremented by 1, before setting it to the register.
* Frame length should not be set to 64 for UART communication.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_SetWordLength() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const uint8_t frame_length)
{
XMC_USIC_CH_SetFrameLength(channel, frame_length);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param event Event bitmasks to enable. Use the type @ref XMC_UART_CH_EVENT_t for naming events. \n
* \b Range: @ref XMC_UART_CH_EVENT_RECEIVE_START, @ref XMC_UART_CH_EVENT_DATA_LOST,
* @ref XMC_UART_CH_EVENT_TRANSMIT_SHIFT, @ref XMC_UART_CH_EVENT_TRANSMIT_BUFFER,
* etc.
* @return None
*
* \par<b>Description</b><br>
* Enables interrupt events for UART communication.\n\n
* Multiple events can be combined using the bitwise OR operation and configured in one function call.
* @ref XMC_UART_CH_EVENT_t enumerates multiple event bitmasks. These enumerations can be used as input to the API.
* Events are configured by setting bits in the CCR register.
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_DisableEvent(), XMC_UART_CH_SetInterruptNodePointer(), XMC_UART_CH_GetStatusFlag() \n\n\n
*/
void XMC_UART_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param event Bitmask of events to disable. Use the type @ref XMC_UART_CH_EVENT_t for naming events.\n
* \b Range: @ref XMC_UART_CH_EVENT_RECEIVE_START, @ref XMC_UART_CH_EVENT_DATA_LOST,
* @ref XMC_UART_CH_EVENT_TRANSMIT_SHIFT, @ref XMC_UART_CH_EVENT_TRANSMIT_BUFFER,
* etc.
* @return None
*
* \par<b>Description</b><br>
* Disables the interrupt events by clearing the bits in CCR register.\n\n
* Multiple events can be combined using the bitwise OR operation and configured in one function call.
* XMC_UART_CH_EVENT_FLAG_t enumerates multiple event bitmasks. These enumerations can be used as input to the API.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_ClearStatusFlag(), XMC_UART_CH_EnableEvent() \n\n\n
*/
void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param service_request Service request number for generating protocol interrupts.\n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Sets the interrupt node for UART channel protocol events.\n\n
* For all the protocol events enlisted in the enumeration XMC_UART_CH_EVENT_t, one common
* interrupt gets generated. The service request connects the interrupt node to the UART
* protocol events.
* Note: NVIC node should be separately enabled to generate the interrupt.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableEvent() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
const uint8_t service_request)
{
XMC_USIC_CH_SetInterruptNodePointer(channel, XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL,
(uint32_t)service_request);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param interrupt_node Interrupt node pointer to be configured. \n
* \b Range: @ref XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
* @ref XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
* @param service_request Service request number.\n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Sets the interrupt node for USIC channel events. \n\n
* For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5).
* The NVIC node gets linked to the interrupt event by doing so.<br>
* Note: NVIC node should be separately enabled to generate the interrupt.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableEvent() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const channel,
const XMC_UART_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
const uint32_t service_request)
{
XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)interrupt_node,
(uint32_t)service_request);
}
/**
* @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param service_request_line service request number of the event to be triggered. \n
* \b Range: 0 to 5.
* @return None
*
* \par<b>Description</b><br>
* Trigger a UART interrupt service request.\n\n
* When the UART service request is triggered, the NVIC interrupt associated with it will be
* generated if enabled.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_SelectInterruptNodePointer() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel, const uint32_t service_request_line)
{
XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @return Status of UART channel events. \n
* \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for
* event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE, @ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE,
* @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc.
*
* \par<b>Description</b><br>
* Provides the status of UART channel events.\n\n
* Status provided by the API represents the status of multiple events at their bit positions. The bitmasks can be
* obtained using the enumeration XMC_UART_CH_STATUS_FLAG_t. Event status is obtained by reading
* the register PSR_ASCMode.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableEvent(), XMC_UART_CH_ClearStatusFlag()\n\n\n
*/
__STATIC_INLINE uint32_t XMC_UART_CH_GetStatusFlag(XMC_USIC_CH_t *const channel)
{
return channel->PSR_ASCMode;
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param flag UART events to be cleared. \n
* \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for
* event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE, @ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE,
* @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc.
* @return None
*
* \par<b>Description</b><br>
* Clears the status of UART channel events.\n\n
* Multiple events can be combined using the bitwise OR operation and configured in one function call.
* XMC_UART_CH_STATUS_FLAG_t enumerates multiple event bitmasks. These enumerations can be used as input to the API.
* Events are cleared by setting the bitmask to the PSCR register.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_DisableEvent(), XMC_UART_CH_GetStatusFlag()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const uint32_t flag)
{
channel->PSCR = flag;
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @param source Input source select for the input stage. The table provided below maps the decimal value with the input source.
* <table><tr><td>0</td><td>DXnA</td></tr><tr><td>1</td><td>DXnB</td></tr><tr><td>2</td><td>DXnC</td></tr><tr><td>3</td><td>DXnD</td></tr>
* <tr><td>4</td><td>DXnE</td></tr><tr><td>5</td><td>DXnF</td></tr><tr><td>6</td><td>DXnG</td></tr><tr><td>7</td><td>Always 1</td>
* </tr></table>
* @return None
*
* \par<b>Description</b><br>
* Sets input soource for the UART communication.\n\n
* It is used for configuring the input stage for data reception.
* Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage.
* The API can be used for the input stages DX0, DX3 and DX5.
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputInversion() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SetInputSource(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input, const uint8_t source)
{
channel->DXCR[input] = (uint32_t)(channel->DXCR[input] & (~(USIC_CH_DX0CR_INSW_Msk|USIC_CH_DX0CR_DSEN_Msk)));
XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param pulse_length Length of the zero pulse in number of time quanta. \n
* \b Range: 0 to 7.
* @return None
*
* \par<b>Description</b><br>
* Sets the length of zero pulse in number of time quanta. Value 0 indicates one time quanta.\n\n
* Maximum possible is 8 time quanta with the value configured as 7.\n
* The value is set to PCR_ASCMode register.
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n
*
*/
__STATIC_INLINE void XMC_UART_CH_SetPulseLength(XMC_USIC_CH_t *const channel, const uint8_t pulse_length)
{
channel->PCR_ASCMode = (uint32_t)(channel->PCR_ASCMode & (~USIC_CH_PCR_ASCMode_PL_Msk)) |
((uint32_t)pulse_length << USIC_CH_PCR_ASCMode_PL_Pos);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param sample_point Sample point among the number of samples. \n
* \b Range: minimum= 0, maximum= \a oversampling (DCTQ).
* @return None
*
* \par<b>Description</b><br>
* Sets the sample point among the multiple samples for each UART symbol.\n\n
* The sample point is the one sample among number of samples set as oversampling. The value should be less than
* the oversampling value. XMC_UART_CH_Init() sets the sample point to the sample at the centre. For
* example if the oversampling is 16, then the sample point is set to 9.
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SetSamplePoint(XMC_USIC_CH_t *const channel, const uint32_t sample_point)
{
channel->PCR_ASCMode = (uint32_t)((channel->PCR_ASCMode & (uint32_t)(~USIC_CH_PCR_ASCMode_SP_Msk)) |
(sample_point << USIC_CH_PCR_ASCMode_SP_Pos));
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @return None
*
* \par<b>Description</b><br>
* Enables input inversion for UART input data signal.\n\n
* Polarity of the input source can be changed to provide inverted data input.
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_DisableInputInversion()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_EnableInputInversion(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
{
XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @return None
*
* \par<b>Description</b><br>
* Disables input inversion for UART input data signal.\n\n
* Resets the input data polarity for the UART input data signal.
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputInversion()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_DisableInputInversion(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
{
XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @return None
*
* \par<b>Description</b><br>
* Enables the digital filter for UART input stage.\n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_DisableInputDigitalFilter()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_EnableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
{
XMC_USIC_CH_EnableInputDigitalFilter(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @return None
*
* \par<b>Description</b><br>
* Disables the digital filter for UART input stage.\n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
{
XMC_USIC_CH_DisableInputDigitalFilter(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @return None
* \par<b>Description</b><br>
* Enables synchronous input for the UART input stage.\n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_DisableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_EnableInputSync(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
{
XMC_USIC_CH_EnableInputSync(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @return None
*
* \par<b>Description</b><br>
* Disables synchronous input for the UART input stage.\n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_DisableInputSync(XMC_USIC_CH_t *const channel, const XMC_UART_CH_INPUT_t input)
{
XMC_USIC_CH_DisableInputSync(channel, (XMC_USIC_CH_INPUT_t)input);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
* \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
* @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref XMC_UART_CH_INPUT_RXD2 (for DX5).
* @param sampling_freq Input sampling frequency. \n
* \b Range: @ref XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH, @ref XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER.
* @return None
*
* \par<b>Description</b><br>
* Sets the sampling frequency for the UART input stage.\n\n
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const channel,
const XMC_UART_CH_INPUT_t input,
const XMC_UART_CH_INPUT_SAMPLING_FREQ_t sampling_freq)
{
XMC_USIC_CH_SetInputSamplingFreq(channel, (XMC_USIC_CH_INPUT_t)input, (XMC_USIC_CH_INPUT_SAMPLING_FREQ_t)sampling_freq);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Enable data transmission.\n\n
* Use this function in combination with XMC_UART_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
* FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
* @note If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_DisableDataTransmission()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_EnableDataTransmission(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_ON_TDV);
}
/**
* @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t \n
* \b Range: @ref XMC_UART0_CH0, @ref XMC_UART0_CH1,@ref XMC_UART1_CH0,@ref XMC_UART1_CH1,@ref XMC_UART2_CH0,@ref XMC_UART2_CH1 @note Availability of UART1 and UART2 depends on device selection
* @return None
*
* \par<b>Description</b><br>
* Disable data transmission.\n\n
* Use this function in combination with XMC_UART_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission.
* FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().
*
* \par<b>Related APIs:</b><BR>
* XMC_UART_CH_EnableDataTransmission()\n\n\n
*/
__STATIC_INLINE void XMC_UART_CH_DisableDataTransmission(XMC_USIC_CH_t *const channel)
{
XMC_USIC_CH_SetStartTransmisionMode(channel, XMC_USIC_CH_START_TRANSMISION_DISABLED);
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

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/**
* @file xmc_usbd.h
* @date 2015-06-20
*
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-16:
* - Initial Version.<br>
* 2015-03-18:
* - Updated the doxygen comments for documentation. <br>
* - Updated the XMC_USBD_PATCH_VERSION to 4. <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API.<br>
* - Updated the doxygen comments for API XMC_USBD_IsEnumDone().<br>
* - Updated the copy right in the file header.<br>
*
* @endcond
*
*/
#ifndef XMC_USBD_H
#define XMC_USBD_H
/**********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_common.h"
#if defined(USB0)
#include <stdlib.h>
#include <string.h>
#include "xmc_usbd_regs.h"
#include "xmc_scu.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup USBD
* @brief Universal Serial Bus Device (USBD) driver for the XMC4000 microcontroller family.
*
* The USBD is the device driver for the USB0 hardware module on XMC4000 family of microcontrollers.
* The USB0 module can be used to establish a USB interface between outside world and XMC4000 family of controllers.
* The USB module includes the following features in device mode:
* -# Complies with the USB 2.0 Specification.
* -# Support for the Full-Speed (12-Mbps) mode.
* -# Supports up to 7 bidirectional endpoints, including control endpoint 0.
* -# Supports SOFs in Full-Speed modes.
* -# Supports clock gating for power saving.
* -# Supports USB suspend/resume.
* -# Supports USB soft disconnect.
* -# Supports DMA mode.
* -# Supports FIFO mode.
*
* The below figure shows the overview of USB0 module in XMC4 microntroller.
* @image html USB_module_overview.png
* @image latex ../images/USB_module_overview.png
*
* The below figure shows the USB device connection of USB0 module.
* @image html USB_device_connection.png
* @image latex ../images/USB_device_connection.png
*
* The USBD device driver supports the following features:\n
* -# Initialize/Uninitialize the USB0 module on XMC4000 device.
* -# Connect the USB device to host.
* -# Get USB device state.
* -# Set the USB device address.
* -# Configure/Unconfigure the USB endpoints.
* -# Stall/Abort the USB endpoints.
* -# USB IN transfers on EP0 and non EP0 endpoints.
* -# USB OUT transfers on EP0 and non EP0 endpoints.
*
* The USBD device driver provides the configuration structure ::XMC_USBD_t which user need to configure before initializing the USB.\n
* The following elements of configuration structure need to be initialized before calling the ::XMC_USBD_Init API:
* -# cb_xmc_device_event of type ::XMC_USBD_SignalDeviceEvent_t.
* -# cb_endpoint_event of type ::XMC_USBD_SignalEndpointEvent_t.
* -# usbd_max_num_eps of type ::XMC_USBD_MAX_NUM_EPS_t.
* -# usbd_transfer_mode of type ::XMC_USBD_TRANSFER_MODE_t.
*
* @{
*/
/**********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#define XMC_USBD_NUM_TX_FIFOS (7U) /**< Number of hardware transmission endpoint fifos */
#define XMC_USBD_MAX_FIFO_SIZE (2048U) /**< Maximum USBD endpoint fifo size */
#define XMC_USBD_NUM_EPS (7U) /**< Number of hardware endpoints */
#define XMC_USBD_MAX_PACKET_SIZE (64U) /**< Maximum packet size for all endpoints
(including ep0) */
/**< Maximum transfer size for endpoints.
*
* It's based on the maximum payload, due to the fact,
* that we only can transfer 2^10 - 1 packets and this is less than the
* transfer size field can hold.
*/
#define XMC_USBD_MAX_TRANSFER_SIZE (((uint32_t)((uint32_t)1U << (uint32_t)10U) - 1U) * (uint32_t)XMC_USBD_MAX_PACKET_SIZE)
#define XMC_USBD_MAX_TRANSFER_SIZE_EP0 (64U) /**< Maximum transfer size for endpoint 0*/
#define XMC_USBD_SETUP_COUNT (3U) /**< The number of USB setup packets */
#define XMC_USBD_SETUP_SIZE (8U) /**< The size of USB setup data */
#define XMC_USBD_EP_NUM_MASK (0x0FU) /**< USB Endpoint number mask. */
#define XMC_USBD_EP_DIR_MASK (0x80U) /**< USB Endpoint direction mask */
#define XMC_USBD_DCFG_DEVSPD_FS (0x3U) /*USB Full Speed device flag in DCFG register */
#define XMC_USBD_TX_FIFO_REG_OFFSET (0x1000U)/* First endpoint fifo register offset from base address */
#define XMC_USBD_TX_FIFO_OFFSET (0x1000U)/* Offset for each fifo register */
#define XMC_USBD_ENDPOINT_NUMBER_MASK (0x0FU) /**< USB Endpoint number mask to get the EP number from address. */
#define XMC_USBD_ENDPOINT_DIRECTION_MASK (0x80U) /**< USB Endpoint direction mask to get the EP direction from address. */
#define XMC_USBD_ENDPOINT_MAX_PACKET_SIZE_MASK (0x07FFU)/**< USB Endpoint Maximum Packet Size mask */
#define XMC_USBD_ENDPOINT_MFRAME_TR_MASK (0x1800U)/* USB Endpoint micro frame TR mask */
#define XMC_USBD_ENDPOINT_MFRAME_TR_1 (0x0000U)/* Selects USB Endpoint micro frame TR1 */
#define XMC_USBD_ENDPOINT_MFRAME_TR_2 (0x0800U)/* Selects USB Endpoint micro frame TR2 */
#define XMC_USBD_ENDPOINT_MFRAME_TR_3 (0x1000U)/* Selects USB Endpoint micro frame TR3 */
#define XMC_USBD_SPEED_FULL (1U) /**< Speed Mode. Full Speed */
#define XMC_USBD_EP0_BUFFER_SIZE (64U) /* Endpoint 0 buffer size */
#define XMC_USBD_EP1_BUFFER_SIZE (64U) /* Endpoint 1 buffer size */
#define XMC_USBD_EP2_BUFFER_SIZE (64U) /* Endpoint 2 buffer size */
#define XMC_USBD_EP3_BUFFER_SIZE (64U) /* Endpoint 3 buffer size */
#define XMC_USBD_EP4_BUFFER_SIZE (64U) /* Endpoint 4 buffer size */
#define XMC_USBD_EP5_BUFFER_SIZE (64U) /* Endpoint 5 buffer size */
#define XMC_USBD_EP6_BUFFER_SIZE (64U) /* Endpoint 6 buffer size */
/**********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
/**
* Defines the options for the global receive fifo packet status.
* Use type ::XMC_USBD_GRXSTS_PKTSTS_t for this enum.
* */
typedef enum XMC_USBD_GRXSTS_PKTSTS {
XMC_USBD_GRXSTS_PKTSTS_GOUTNAK = 0x1U, /**< Global out nack send ( triggers an interrupt ) */
XMC_USBD_GRXSTS_PKTSTS_OUTDATA = 0x2U, /**< OUT data packet received */
XMC_USBD_GRXSTS_PKTSTS_OUTCMPL = 0x3U, /**< OUT transfer completed (triggers an interrupt) */
XMC_USBD_GRXSTS_PKTSTS_SETUPCMPL = 0x4U, /**< SETUP transaction completed (triggers an interrupt) */
XMC_USBD_GRXSTS_PKTSTS_SETUP = 0x6U /**< SETUP data packet received */
} XMC_USBD_GRXSTS_PKTSTS_t;
/**
* Defines the options for the USB endpoint type. The values are from the USB 2.0 specification.
* Use type ::XMC_USBD_ENDPOINT_TYPE_t for this enum.
*/
typedef enum XMC_USBD_ENDPOINT_TYPE {
XMC_USBD_ENDPOINT_TYPE_CONTROL = 0x0U, /**< Control endpoint */
XMC_USBD_ENDPOINT_TYPE_ISOCHRONOUS = 0x01U, /**< Isochronous endpoint */
XMC_USBD_ENDPOINT_TYPE_BULK = 0x02U, /**< Bulk endpoint */
XMC_USBD_ENDPOINT_TYPE_INTERRUPT = 0x03U /**< Interrupt endpoint */
} XMC_USBD_ENDPOINT_TYPE_t;
/**
* Defines the options for USB device state while setting the address.
* Use type ::XMC_USBD_SET_ADDRESS_STAGE_t for this enum.
*/
typedef enum XMC_USBD_SET_ADDRESS_STAGE {
XMC_USBD_SET_ADDRESS_STAGE_SETUP, /**< Setup address */
XMC_USBD_SET_ADDRESS_STAGE_STATUS /**< Status address */
} XMC_USBD_SET_ADDRESS_STAGE_t;
/**
* Defines the USB Device Status of executed operation.
* Use type ::XMC_USBD_STATUS_t for this enum.
*/
typedef enum XMC_USBD_STATUS {
XMC_USBD_STATUS_OK = 0U, /**< USBD Status: Operation succeeded*/
XMC_USBD_STATUS_BUSY = 2U, /**< Driver is busy and cannot handle request */
XMC_USBD_STATUS_ERROR = 1U /**< USBD Status: Unspecified error*/
} XMC_USBD_STATUS_t;
/**
* Defines the USB Device events.
* Use type ::XMC_USBD_EVENT_t for this enum.
*/
typedef enum XMC_USBD_EVENT {
XMC_USBD_EVENT_POWER_ON, /**< USB Device Power On */
XMC_USBD_EVENT_POWER_OFF, /**< USB Device Power Off */
XMC_USBD_EVENT_CONNECT, /**< USB Device connected */
XMC_USBD_EVENT_DISCONNECT, /**< USB Device disconnected */
XMC_USBD_EVENT_RESET, /**< USB Reset occurred */
XMC_USBD_EVENT_HIGH_SPEED, /**< USB switch to High Speed occurred */
XMC_USBD_EVENT_SUSPEND, /**< USB Suspend occurred */
XMC_USBD_EVENT_RESUME, /**< USB Resume occurred */
XMC_USBD_EVENT_REMOTE_WAKEUP, /**< USB Remote wakeup */
XMC_USBD_EVENT_SOF, /**< USB Start of frame event */
XMC_USBD_EVENT_EARLYSUSPEND, /**< USB Early suspend */
XMC_USBD_EVENT_ENUMDONE, /**< USB enumeration done */
XMC_USBD_EVENT_ENUMNOTDONE, /**< USB enumeration not done */
XMC_USBD_EVENT_OUTEP, /**< USB OUT endpoint */
XMC_USBD_EVENT_INEP /**< USB IN endpoint */
} XMC_USBD_EVENT_t;
/**
* Defines the USB IN endpoint events.
* Use type ::XMC_USBD_EVENT_IN_EP_t for this enum.
*/
typedef enum XMC_USBD_EVENT_IN_EP {
XMC_USBD_EVENT_IN_EP_TX_COMPLET = 1U, /**< USB IN ep transmission complete */
XMC_USBD_EVENT_IN_EP_DISABLED = 2U, /**< USB IN ep disabled */
XMC_USBD_EVENT_IN_EP_AHB_ERROR = 4U, /**< USB IN ep AHB error */
XMC_USBD_EVENT_IN_EP_TIMEOUT = 8U, /**< USB IN ep timeout */
} XMC_USBD_EVENT_IN_EP_t;
/**
* Defines the USB OUT endpoint events.
* Use type ::XMC_USBD_EVENT_OUT_EP_t for this enum.
*/
typedef enum XMC_USBD_EVENT_OUT_EP {
XMC_USBD_EVENT_OUT_EP_TX_COMPLET = 1U, /**< USB OUT ep transmission complete */
XMC_USBD_EVENT_OUT_EP_DISABLED = 2U, /**< USB OUT ep disabled */
XMC_USBD_EVENT_OUT_EP_AHB_ERROR = 4U, /**< USB OUT ep AHB error */
XMC_USBD_EVENT_OUT_EP_SETUP = 8U, /**< USB OUT ep setup */
} XMC_USBD_EVENT_OUT_EP_t;
/**
* Defines the generic USB endpoint events.
* Use type ::XMC_USBD_EP_EVENT_t for this enum.
*/
typedef enum XMC_USBD_EP_EVENT {
XMC_USBD_EP_EVENT_SETUP, /**< SETUP packet*/
XMC_USBD_EP_EVENT_OUT, /**< OUT packet*/
XMC_USBD_EP_EVENT_IN /**< IN packet*/
} XMC_USBD_EP_EVENT_t;
/**
* Defines the options for the USB data transfer modes.
* Use type ::XMC_USBD_TRANSFER_MODE_t for this enum.
*/
typedef enum XMC_USBD_TRANSFER_MODE {
XMC_USBD_USE_DMA, /**< Transfer by DMA*/
XMC_USBD_USE_FIFO /**< Transfer by FIFO*/
} XMC_USBD_TRANSFER_MODE_t;
/**
* Defines the options for the maximum number of endpoints used.
* Use type ::XMC_USBD_MAX_NUM_EPS_t for this enum.
*/
typedef enum XMC_USBD_MAX_NUM_EPS {
XMC_USBD_MAX_NUM_EPS_1 = 1U, /**< Maximum 1 endpoint used*/
XMC_USBD_MAX_NUM_EPS_2 = 2U, /**< Maximum 2 endpoints used*/
XMC_USBD_MAX_NUM_EPS_3 = 3U, /**< Maximum 3 endpoints used*/
XMC_USBD_MAX_NUM_EPS_4 = 4U, /**< Maximum 4 endpoints used*/
XMC_USBD_MAX_NUM_EPS_5 = 5U, /**< Maximum 5 endpoints used*/
XMC_USBD_MAX_NUM_EPS_6 = 6U, /**< Maximum 6 endpoints used*/
XMC_USBD_MAX_NUM_EPS_7 = 7U /**< Maximum 2 endpoints used*/
} XMC_USBD_MAX_NUM_EPS_t;
/**
* USB device/endpoint event function pointers
*/
typedef void (*XMC_USBD_SignalDeviceEvent_t) (XMC_USBD_EVENT_t event);/**< Pointer to USB device event call back.
Uses type ::XMC_USBD_EVENT_t as the argument of callback.*/
typedef void (*XMC_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, XMC_USBD_EP_EVENT_t ep_event);/**< Pointer to USB endpoint event call back.
Uses type ::XMC_USBD_EP_EVENT_t and EP address as the argument of callback.*/
/**********************************************************************************************************************
* DATA STRUCTURES
*********************************************************************************************************************/
/**
* Describes the USB Device Driver Capabilities.
*/
typedef struct XMC_USBD_CAPABILITIES {
uint32_t event_power_on : 1; /**< Signal Power On event*/
uint32_t event_power_off : 1; /**< Signal Power Off event*/
uint32_t event_connect : 1; /**< Signal Connect event*/
uint32_t event_disconnect : 1; /**< Signal Disconnect event*/
uint32_t event_reset : 1; /**< Signal Reset event*/
uint32_t event_high_speed : 1; /**< Signal switch to High-speed event*/
uint32_t event_suspend : 1; /**< Signal Suspend event*/
uint32_t event_resume : 1; /**< Signal Resume event*/
uint32_t event_remote_wakeup : 1; /**< Signal Remote Wake up event*/
uint32_t reserved : 23; /**< Reserved for future use*/
} XMC_USBD_CAPABILITIES_t;
/**
* Describes the current USB Device State.
*/
typedef struct XMC_USBD_STATE {
uint32_t powered : 1; /**< USB Device powered flag*/
uint32_t connected : 1; /**< USB Device connected flag*/
uint32_t active : 1; /**< USB Device active lag*/
uint32_t speed : 2; /**< USB Device speed */
} XMC_USBD_STATE_t;
/**
* Describes a USB endpoint<BR>
*
* All information to control an endpoint is stored in this structure.
* It contains information about the endpoints and the status of the device.
*/
typedef struct {
union {
uint32_t address : 8; /**< The endpoint address including the direction */
struct {
uint32_t number : 4; /**< The endpoint number.It can be from 0 to 6 */
uint32_t pading : 3; /**< Padding between number and direction */
uint32_t direction : 1; /**< The endpoint direction */
} address_st;
} address_u;
uint32_t type : 2; /**< The endpoint type */
uint32_t isConfigured : 1; /**< The flag showing, if the endpoint is configured */
volatile uint32_t inInUse : 1; /**< Sets if the selected USB IN endpoint is currently in use */
volatile uint32_t outInUse : 1; /**< Sets if the selected USB OUT endpoint is currently in use */
uint32_t isStalled : 1; /**< Sets if the selected USB endpoint is stalled. */
uint32_t txFifoNum : 4; /**< Endpoint transmit Fifo Number */
uint32_t sendZeroLengthPacket : 1; /**< If set, a zero length packet will be send at the end of the transfer */
uint32_t maxPacketSize : 7; /**< The maximum size of packet for USB endpoint ( due to FS Speed device only 64 Byte )*/
uint32_t maxTransferSize : 19; /**< The maximum amount of data the core can send at once.*/
uint8_t *outBuffer; /**< The buffer for operation as OUT endpoint */
uint32_t outBytesAvailable; /**< The number of bytes available in the EP OUT buffer */
uint32_t outBufferSize; /**< The size of the EP OUT buffer */
uint32_t outOffset; /**< The read offset of the EP OUT buffer */
uint8_t *inBuffer; /**< The buffer for operation as IN endpoint */
uint32_t inBufferSize; /**< The size of the EP IN buffer */
uint8_t *xferBuffer; /**< The buffer of the current transfer */
uint32_t xferLength; /**< The length of the current transfer */
uint32_t xferCount; /**< Bytes transfered of the current USB data transfer */
uint32_t xferTotal; /**< The length of total data in buffer */
} XMC_USBD_EP_t;
/**
* Describes the XMC USB device<BR>
*
* All information to control an XMC USB device is stored in
* this structure. It contains register, callbacks, information
* about the endpoints and the status of the device.
*/
typedef struct XMC_USBD_DEVICE {
XMC_USBD_EP_t ep[8]; /**< Endpoints of the USB device. It is of type ::XMC_USBD_EP_t */
dwc_otg_core_global_regs_t *global_register; /**< Global register interface */
dwc_otg_device_global_regs_t *device_register; /**< Device register interface */
dwc_otg_dev_in_ep_regs_t *endpoint_in_register[(uint8_t)XMC_USBD_NUM_EPS];/**< IN Endpoint register interface */
dwc_otg_dev_out_ep_regs_t *endpoint_out_register[(uint8_t)XMC_USBD_NUM_EPS];/**< OUT Endpoint register interface */
volatile uint32_t *fifo[(uint8_t)XMC_USBD_NUM_TX_FIFOS]; /**< Transmit fifo interface */
uint16_t txfifomsk; /**< Mask of used TX fifos */
uint32_t IsConnected : 1; /**< Sets if device is connected */
uint32_t IsActive : 1; /**< Sets if device is currently active */
uint32_t IsPowered : 1; /**< Sets if device is powered by Vbus */
XMC_USBD_SignalDeviceEvent_t DeviceEvent_cb; /**< The USB device event callback. */
XMC_USBD_SignalEndpointEvent_t EndpointEvent_cb; /**< The USB endpoint event callback. */
} XMC_USBD_DEVICE_t;
/**
* USB device initialization structure
*/
typedef struct XMC_USBD_OBJ
{
USB0_GLOBAL_TypeDef *const usbd; /**< USB Module Pointer. The USB0 module base address. */
XMC_USBD_SignalDeviceEvent_t cb_xmc_device_event; /**< USB device event callback. Use ::XMC_USBD_SignalDeviceEvent_t type of function pointer. */
XMC_USBD_SignalEndpointEvent_t cb_endpoint_event; /**< USB endpoint event callback. Use ::XMC_USBD_SignalEndpointEvent_t type of function pointer.*/
XMC_USBD_MAX_NUM_EPS_t usbd_max_num_eps; /**< Maximum number of end points used. The maximum range can be 7.*/
XMC_USBD_TRANSFER_MODE_t usbd_transfer_mode; /**< USB data transfer mode.Use ::XMC_USBD_TRANSFER_MODE_t type to specify the transfer mode. */
} XMC_USBD_t;
/**
* Defines the access structure of the USB Device Driver.
*/
typedef struct XMC_USBD_DRIVER {
XMC_USBD_CAPABILITIES_t (*GetCapabilities) (void); /**< Pointer to @ref XMC_USBD_GetCapabilities : Get driver capabilities.*/
XMC_USBD_STATUS_t (*Initialize) (XMC_USBD_t *obj); /**< Pointer to @ref XMC_USBD_Init : Initialize USB Device Interface.*/
XMC_USBD_STATUS_t (*Uninitialize) (void); /**< Pointer to @ref XMC_USBD_Uninitialize : De-initialize USB Device Interface.*/
XMC_USBD_STATUS_t (*DeviceConnect) (void); /**< Pointer to @ref XMC_USBD_DeviceConnect : Connect USB Device.*/
XMC_USBD_STATUS_t (*DeviceDisconnect) (void); /**< Pointer to @ref XMC_USBD_DeviceDisconnect : Disconnect USB Device.*/
XMC_USBD_STATE_t (*DeviceGetState) (const XMC_USBD_t *const obj); /**< Pointer to @ref XMC_USBD_DeviceGetState : Get current USB Device State.*/
XMC_USBD_STATUS_t (*DeviceSetAddress) (uint8_t dev_addr, XMC_USBD_SET_ADDRESS_STAGE_t stage);/**< Pointer to @ref XMC_USBD_DeviceSetAddress : Set USB Device Address.*/
XMC_USBD_STATUS_t (*EndpointConfigure) (uint8_t ep_addr,XMC_USBD_ENDPOINT_TYPE_t ep_type, uint16_t ep_max_packet_size);/**< Pointer to @ref XMC_USBD_EndpointConfigure : Configure USB Endpoint.*/
XMC_USBD_STATUS_t (*EndpointUnconfigure)(uint8_t ep_addr); /**< Pointer to @ref XMC_USBD_EndpointUnconfigure : Unconfigure USB Endpoint.*/
XMC_USBD_STATUS_t (*EndpointStall) (uint8_t ep_addr, bool stall); /**< Pointer to @ref XMC_USBD_EndpointStall : Set/Clear Stall for USB Endpoint.*/
XMC_USBD_STATUS_t (*EndpointReadStart) (uint8_t ep_addr, uint32_t len); /**< Pointer to @ref XMC_USBD_EndpointReadStart : Start USB Endpoint Read operation.*/
int32_t (*EndpointRead) (uint8_t ep_addr, uint8_t *buf, uint32_t len);/**< Pointer to @ref XMC_USBD_EndpointRead : Read data from USB Endpoint.*/
int32_t (*EndpointWrite) (uint8_t ep_addr, const uint8_t *buf, uint32_t len); /**< Pointer to @ref XMC_USBD_EndpointWrite : Write data to USB Endpoint.*/
XMC_USBD_STATUS_t (*EndpointAbort) (uint8_t ep_addr); /**< Pointer to @ref XMC_USBD_EndpointAbort : Abort current USB Endpoint transfer.*/
uint16_t (*GetFrameNumber) (void); /**< Pointer to @ref XMC_USBD_GetFrameNumber : Get current USB Frame Number.*/
uint32_t (*IsEnumDone) (void); /**< Pointer to @ref XMC_USBD_IsEnumDone : Is enumeration done in Host?.*/
} const XMC_USBD_DRIVER_t;
/**
* Defines the driver interface function table.
* To access the XMC device controller driver interface use this table of functions.
**/
extern const XMC_USBD_DRIVER_t Driver_USBD0;
/**
* Defines the XMC USB device data
* The instance of ::XMC_USBD_DEVICE_t structure describing the XMC device.
**/
extern XMC_USBD_DEVICE_t xmc_device;
/**********************************************************************************************************************
* API PROTOTYPES
*********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param None.
*
* @return None.
*
* \par<b>Description:</b><BR>
* Enables the USB module in the XMC controller.<BR>
* It de-asserts the peripheral reset on USB0 module and enables the USB power.
*
* \par<b>Note:</b><BR>
* This API is called inside the XMC_USBD_Init().\n
*
* \par<b>Related APIs:</b><BR>
* XMC_USBD_Disable()\n
**/
void XMC_USBD_Enable(void);
/**
* @param None.
*
* @return None.
*
* \par<b>Description:</b><BR>
* Disables the USB module in the XMC controller.<BR>
* It asserts the peripheral reset on USB0 module and disables the USB power.
*
* \par<b>Related APIs:</b><BR>
* XMC_USBD_Enable()\n
**/
void XMC_USBD_Disable(void);
/**
* @param event The single event that needs to be cleared. Use ::XMC_USBD_EVENT_t as argument.\n
*
* @return None.
*
* \par<b>Description:</b><BR>
* Clears the selected USBD \a event.<BR>
* It clears the event by writing to the GINTSTS register.
*
* \par<b>Note:</b><BR>
* This API is called inside the USB interrupt handler to clear the event XMC_USBD_EVENT_t
* and maintain the device state machine.\n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_ClearEventOUTEP(),::XMC_USBD_ClearEventINEP()\n
**/
void XMC_USBD_ClearEvent(XMC_USBD_EVENT_t event);
/**
* @param event The single event or multiple events that need to be cleared.
*
* @param ep_num The IN endpoint number on which the events to be cleared.
*
* @return None.
*
* \par<b>Description:</b><BR>
* Clears the single event or multiple events of the selected IN endpoint.<BR>
* The multiple events can be selected by the bitwise OR operation of ::XMC_USBD_EVENT_IN_EP_t elements.\n
* It clears the event by programming DIEPINT register.\n
*
* \par<b>Note:</b><BR>
* This API is called inside the USB IN EP interrupt handler to clear the ::XMC_USBD_EVENT_IN_EP_t event
* and maintain the device state machine.\n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_ClearEventOUTEP()\n
**/
void XMC_USBD_ClearEventINEP(uint32_t event,uint8_t ep_num);
/**
* @param event The single event or multiple events that need to be cleared.
*
* @param ep_num The OUT endpoint number on which the events to be cleared.
*
* @return None.
*
* \par<b>Description:</b><BR>
* Clears the single \a event or multiple events of the selected OUT endpoint.<BR>
* The multiple events can be selected by the bitwise OR operation of ::XMC_USBD_EVENT_OUT_EP_t elements.
* It clears the event by writing to DOEPINT register.
*
* \par<b>Note:</b><BR>
* This API is called inside the USB OUT EP interrupt handler to clear the ::XMC_USBD_EVENT_OUT_EP_t event
* and maintain the device state machine.\n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_ClearEventINEP()\n
**/
void XMC_USBD_ClearEventOUTEP(uint32_t event,uint8_t ep_num);
/**
* @param event The single event or multiple events that need to be enabled.
*
* @return None.
*
* \par<b>Description:</b><BR>
* Enables the event or multiple events of the OUT endpoints.<BR>
* The multiple events can be selected by the bitwise OR operation of ::XMC_USBD_EVENT_OUT_EP_t elements.
* It enables the event by programming DOEPMSK register.
*
* \par<b>Note:</b><BR>
* This API is called inside the ::XMC_USBD_Init() to enable the OUT EP interrupts.\n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_EnableEventINEP()\n
**/
void XMC_USBD_EnableEventOUTEP(uint32_t event);
/**
* @param event The single event or multiple events that need to be enabled.
*
* @return None.
*
* \par<b>Description:</b><BR>
* Enables the \a event or multiple events of the USB IN endpoints.<BR>
* The multiple events can be selected by the bitwise OR operation of ::XMC_USBD_EVENT_IN_EP_t elements.
* It enables the event by programming DIEPMSK register.
*
* \par<b>Note:</b><BR>
* This API is called inside the ::XMC_USBD_Init() to enable the IN EP interrupts.\n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_EnableEventOUTEP()\n
**/
void XMC_USBD_EnableEventINEP(uint32_t event);
/**
* @param None.
*
* @return ::XMC_USBD_CAPABILITIES_t.
*
* \par<b>Description:</b><BR>
* Retrieves the USB device capabilities of type \a XMC_USBD_CAPABILITIES_t<BR>
* The USB device capabilities supported by the USBD driver, like power on/off, connect/disconnect,
* reset,suspend/resume,USB speed etc are retrieved.
*
* It can be called after initializing the USB device to get the information on the USBD capabilities.
*
**/
XMC_USBD_CAPABILITIES_t XMC_USBD_GetCapabilities(void);
/**
* @param obj The pointer to the USB device handle ::XMC_USBD_t.
*
* @return XMC_USBD_STATUS_t The USB device status of type ::XMC_USBD_STATUS_t.
*
* \par<b>Description:</b><BR>
* Initializes the USB device to get ready for connect to USB host.<BR>
* Enables the USB module,sets the EP buffer sizes,registers the device and EP event call backs.
* Initializes the global,device and FIFO register base addresses.
* Configures the global AHB,enables the global interrupt and DMA by programming GAHBCFG register.
* Configures the USB in to device mode and enables the session request protocol by programming GUSBCFG register.
* Configures the USB device speed to full speed by programming DCFG register.
* Disconnects the USB device by programming DCTL register.
* Enables the USB common and device interrupts by programming GINTMSK register.
*
* \par<b>Note:</b><BR>
* This API makes the USB device ready to connect to host.The user has to explicitly call
* the ::XMC_USBD_DeviceConnect() after the USB initialization to connect to USB host.\n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_DeviceConnect()\n
**/
XMC_USBD_STATUS_t XMC_USBD_Init(XMC_USBD_t *obj);
/**
* @param None.
*
* @return ::XMC_USBD_STATUS_t.
*
* \par<b>Description:</b><BR>
* Uninitialises the USB device.<BR>
* Disconnects the USB device by programming DCTL register and resets the XMC USB device data.
*
* \par<b>Note:</b><BR>
* Once this API is called, USB device will not be accessible from host.\n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_Init()\n
**/
XMC_USBD_STATUS_t XMC_USBD_Uninitialize(void);
/**
* @param None.
*
* @return ::XMC_USBD_STATUS_t.
*
* \par<b>Description:</b><BR>
* Connects the USB device to host and triggers the USB enumeration.<BR>
* Connects the USB device to host by programming DCTL register.\n
* It resets the soft disconnect bit, which activates the speed pull up at d+ line of USB.
* ::XMC_USBD_Init() should be called before calling this API.
*
* \par<b>Note:</b><BR>
* Once this API is called, USB host starts the enumeration process and the device should
* handle the descriptor requests.\n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_Init()\n
**/
XMC_USBD_STATUS_t XMC_USBD_DeviceConnect(void);
/**
* @param None.
*
* @return ::XMC_USBD_STATUS_t.
*
* \par<b>Description:</b><BR>
* Disconnects the USB device from host.<BR>
* By programming DCTL register, it sets the soft disconnect bit, which deactivates\n
* the speed pull up at d+ line of USB.
*
* \par<b>Note:</b><BR>
* Once this API is called, USB device will not be accessible from host.\n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_DeviceConnect()\n
**/
XMC_USBD_STATUS_t XMC_USBD_DeviceDisconnect(void);
/**
* @param obj The pointer to the USB device handle structure \a XMC_USBD_t.
*
* @return ::XMC_USBD_STATE_t.
*
* \par<b>Description:</b><BR>
* Retrieves the current USB device state.<BR>
* Power,active,speed and connection status data are retrieved.\n
*
* \par<b>Note:</b><BR>
* Before calling this API, USB should be initialized with ::XMC_USBD_Init.\n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_Init()\n
**/
XMC_USBD_STATE_t XMC_USBD_DeviceGetState(const XMC_USBD_t *const obj);
/**
* @param address The address to be set for the USB device .
* @param stage The device request stage-setup or status ::XMC_USBD_SET_ADDRESS_STAGE_t.
*
* @return ::XMC_USBD_STATUS_t.
*
* \par<b>Description:</b><BR>
* Sets the USB device address.<BR>
* The device address is programmed in the DCFG register.<BR>
*
* The address should be more than 0; as 0 is the default USB device address at the starting of enumeration.
* As part of enumeration, host sends the control request to the device to set the USB address; and in turn,\n
* in the USB device event call back handler, user has to set the address using this API for the set address request.<BR>
*
* The stage parameter should be XMC_USBD_SET_ADDRESS_STAGE_SETUP from the enum ::XMC_USBD_SET_ADDRESS_STAGE_t.
*
* \par<b>Note:</b><BR>
* Before calling this API, USB should be initialized with ::XMC_USBD_Init () and connected to
* USB host using ::XMC_USBD_DeviceConnect() \n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_Init(), ::XMC_USBD_DeviceConnect()\n
**/
XMC_USBD_STATUS_t XMC_USBD_DeviceSetAddress(uint8_t address,XMC_USBD_SET_ADDRESS_STAGE_t stage);
/**
* @param ep_addr The address of the USB endpoint, which needs to be configured.
* @param ep_type The ::XMC_USBD_ENDPOINT_TYPE_t.
* @param ep_max_packet_size The maximum packet size of endpoint in USB full speed.
*
* @return ::XMC_USBD_STATUS_t.
*
* \par<b>Description:</b><BR>
* Configures the USB endpoint.<BR>
* The endpoint is configured by programming the DAINT,DIEPCTL and DOEPCTL registers.<BR>
*
* Configures the EP type, FIFO number,maximum packet size, enables endpoint and sets the DATA0 PID.
* This function also initializes the internal buffer handling for the specified endpoint,
* but does not start any transfers.<BR>
*
* As part of enumeration, host sends the control request to the device to set the configuration; and in turn,\n
* in the USB device event call back handler, user has to set the configuration and configure the endpoints \n
* required for the device.\n
*
* \par<b>Note:</b><BR>
* This API should only be used as part of enumeration.\n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_Init(),::XMC_USBD_DeviceConnect(),::XMC_USBD_EndpointUnconfigure()\n
**/
XMC_USBD_STATUS_t XMC_USBD_EndpointConfigure(uint8_t ep_addr,
XMC_USBD_ENDPOINT_TYPE_t ep_type,
uint16_t ep_max_packet_size);
/**
* @param ep_addr The address of the USB endpoint, which needs to be unconfigured.
*
* @return ::XMC_USBD_STATUS_t.
*
* \par<b>Description:</b><BR>
* Unconfigures the USB endpoint.<BR>
* The endpoint is unconfigured by programming the DAINT,DIEPCTL and DOEPCTL registers.\n
* Disables the endpoint, unassign the fifo, deactivate it and only send nacks.\n
* Waits until the endpoint has finished operation and disables it. All (eventuallly) allocated buffers gets freed.
* Forces the endpoint to stop immediately, any pending transfers are killed(Can cause device reset).
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_EndpointConfigure()\n
**/
XMC_USBD_STATUS_t XMC_USBD_EndpointUnconfigure(uint8_t ep_addr);
/**
* @param ep_addr The address of the USB endpoint, on which stall needs to be set or cleared.
* @param stall The boolean variable to decide on set or clear of stall on EP.
*
* @return ::XMC_USBD_STATUS_t.
*
* \par<b>Description:</b><BR>
* Set or Clear stall on the USB endpoint \a ep_addr, based on \a stall parameter.<BR>
*
* By programming stall bit in the doepctl and diepctl, it sets or clears the stall on the endpoint.
* The endpoint can be stalled when a non supported request comes from the USB host.
* The XMC_USBD_EndpointStall() should be called with \a stall set to 0, in the clear feature standard request
* in the USB device event call back handler. *
*
* \par<b>Note:</b><BR>
* The host should clear the stall set on the endpoint by sending the clear feature standard
* request on the non EP0 endpoints. On EP0, the stall will automatically gets cleared on the next control request.\n
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_EndpointAbort()\n
**/
XMC_USBD_STATUS_t XMC_USBD_EndpointStall(uint8_t ep_addr, bool stall);
/**
* @param ep_addr The address of the USB endpoint, from which data need to be read.
* @param size The number of bytes to be read.
*
* @return ::XMC_USBD_STATUS_t.
*
* \par<b>Description:</b><BR>
* Prepares an endpoint to receive OUT tokens from the USB host.<BR>
* The selected endpoint gets configured, so that it receives the specified amount of data from the host.
* As part of streaming of OUT data, after reading the current OUT buffer using ::XMC_USBD_EndpointRead(),\n
* user can prepare endpoint for the next OUT packet by using ::XMC_USBD_EndpointReadStart().
*
* The registers DOEPDMA,DOEPTSIZ and DOEPCTL are programmed to start a new read request.
*
* \par<b>Note:</b><BR>
* For the data received on OUT EP buffer, use ::XMC_USBD_EndpointRead().\n
*
* \par<b>Related APIs:</b><BR>
* XMC_USBD_EndpointRead()\n
**/
XMC_USBD_STATUS_t XMC_USBD_EndpointReadStart(const uint8_t ep_addr, uint32_t size);
/**
* @param ep_addr The address of the USB OUT endpoint, from which data need to be read.
* @param buffer The pointer to the user buffer,in which data need to be received.
* @param length The number of bytes to be read from OUT EP.
*
* @return <BR>
* The actual number of bytes received.
*
* \par<b>Description:</b><BR>
* Read \a length number of bytes from an OUT endpoint \a ep_addr.<BR>
* If data has been received for this endpoint, it gets copied into the user buffer until its full
* or no data is left in the driver buffer.
*
* \par<b>Note:</b><BR>
* For preparing the next OUT token, use ::XMC_USBD_EndpointReadStart() after ::XMC_USBD_EndpointRead().\n
*
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_EndpointReadStart()\n
**/
int32_t XMC_USBD_EndpointRead(const uint8_t ep_addr,uint8_t * buffer, uint32_t length);
/**
* @param ep_addr The address of the USB IN endpoint, on which data should be sent.
* @param buffer The pointer to the data buffer, to write to the endpoint.
* @param length The number of bytes to be written to IN EP.
*
* @return <BR>
* The actual amount of data written to the endpoint buffer.
*
* \par<b>Description:</b><BR>
* Write the \a length bytes of data to an IN endpoint \a ep_addr.<BR>
* The User data gets copied into the driver buffer or will be send directly based on the buffer concept
* selected in the ::XMC_USBD_TRANSFER_MODE_t configuration.
*
* Then the endpoint is set up to transfer the data to the host.\n
* DIEPDMA,DIEPTSIZ and DIEPCTL registers are programmed to start the IN transfer.
*
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_EndpointRead()\n
**/
int32_t XMC_USBD_EndpointWrite(const uint8_t ep_addr,const uint8_t * buffer,uint32_t length);
/**
* @param ep_addr The address of the USB endpoint, on which the data need to be aborted.
*
* @return ::XMC_USBD_STATUS_t
*
* \par<b>Description:</b><BR>
* Abort the transfer on endpoint \a ep_addr.<BR>
* On any failure with the USB transmission user can reset the endpoint into default state and clear all
* assigned buffers, to start from a clean point. The endpoint will not be unconfigured or disabled.
*
* \par<b>Related APIs:</b><BR>
* ::XMC_USBD_EndpointUnconfigure()\n
**/
XMC_USBD_STATUS_t XMC_USBD_EndpointAbort(uint8_t ep_addr);
/**
* @param None.
*
* @return The 16 bit current USB frame number.
*
* \par<b>Description:</b><BR>
* Read the current USB frame number.<BR> *
* Reads the device status register (DSTS) and returns the SOFFN field.
*
**/
uint16_t XMC_USBD_GetFrameNumber(void);
/**
* @param None.
*
* @return Returns 1, if the speed enumeration is done and 0 otherwise.
*
* \par<b>Description:</b><BR>
* Gets the speed enumeration completion status of the USB device.<BR>
*
* \par<b>Note:</b><BR>
* This should not be used for the actual USB enumeration completion status. For the actual USB enumeration status,
* the application layer should check for the completion of USB standard request 'Set configuration'.\n
*
**/
uint32_t XMC_USBD_IsEnumDone(void);
/**
* @param obj The pointer to the USB device handle structure.
*
* @return None.
*
* \par<b>Description:</b><BR>
* USB device default IRQ handler.<BR>
* USBD Peripheral LLD provides default implementation of ISR.
* The user needs to explicitly either use our default implementation or use its own one using the LLD APIs.
*
* For example:
* XMC_USBD_t *obj;
* void USB0_0_IRQHandler(void)
* {
* XMC_USBD_IRQHandler(obj);
* }
*
* \par<b>Note:</b><BR>
* The user should initialize the XMC USB device configuration structure before calling
* ::XMC_USBD_IRQHandler() in the actual USB0 IRQ handler.
*
**/
void XMC_USBD_IRQHandler(const XMC_USBD_t *const obj);
#ifdef __cplusplus
}
#endif
/**
* MISRA C 2004 Deviations
*
* 1. Function like macro- defined- MISRA Advisory Rule 19.7
* 2. usage of unions - MISRA Required Rule 18.4
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(USB0) */
#endif /* XMC_USBD_H */

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/**
* @file xmc_usbh.h
* @date 2016-06-30
*
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2016-06-30:
* - Initial Version.<br>
* 2016-09-01:
* - Removed Keil specific inclusions and macros<br>
*
* @endcond
*
*/
#ifndef XMC_USBH_H
#define XMC_USBH_H
#include <stdint.h>
#include "xmc_common.h"
#include "xmc_scu.h"
#include "xmc_gpio.h"
#if((UC_SERIES == XMC45) || (UC_SERIES == XMC44) || (UC_SERIES == XMC43) || (UC_SERIES == XMC47) || (UC_SERIES == XMC48) || defined(DOXYGEN))
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup USBH
* @brief Universal Serial Bus Host (USBH) driver for the XMC4000 microcontroller family.
*
* The USBH is the host mode device driver for the USB0 hardware module on XMC4000 family of microcontrollers.
* The USB0 module can be used to establish a USB interface between outside world and XMC4000 family of controllers.
* The USB module includes the following features in host mode:
* -# Complies with the USB 2.0 Specification.
* -# Supports up to 14 bidirectional pipes, including control pipe 0.
* -# Supports SOFs in Full-Speed modes.
* -# Supports clock gating for power saving.
* -# Supports FIFO mode data transaction.
*
* The below figure shows the overview of USB0 module in XMC4 microntroller.
* @image html USB_module_overview.png
* @image latex ../images/USB_module_overview.png
*
*
* The USBH device driver supports the following features:\n
* -# Initialize/Uninitialize the USB0 module on XMC4000 device.
* -# Control VBUS state.
* -# Reset USB port.
* -# Set the USB device address.
* -# Allocate pipe for new endpoint communication.
* -# Modify an existing pipe.
* -# Transfer data on selected pipe.
* -# Abort ongoing data transaction.
* -# Handle multi packet data transaction by updating toggle information.
*
* The USBH device driver expects registration of callback functions ::XMC_USBH_SignalPortEvent_t and ::XMC_USBH_SignalPipeEvent_t to be executed
* when there is port event interrupt and pipe event interrupt respectively.\n
* The USBH driver is CMSIS API compatible. Please use Driver_USBH0 to access the USBH API.\n
* For example, to initialize the USB host controller, use Driver_USBH0.Initialize().\n
*
* @{
*/
/**********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
/*Drive VBUS*/
#define XMC_USB_DRIVE_PORT1 P3_2 /**< Default port(PORT3, pin 2) used to enable VBUS voltage regulator on the board */
#define XMC_USB_DRIVE_PORT2 P0_1 /**< Alternate port that can be used to enable VBUS voltage regulator(PORT0, pin 1) */
#ifndef USBH0_MAX_PIPE_NUM
#define USBH0_MAX_PIPE_NUM (14U) /**< Representation of number of pipes available */
#endif
#if (USBH0_MAX_PIPE_NUM > 14U)
#error Too many Pipes, maximum Pipes that this driver supports is 14 !!!
#endif
#define XMC_USBH_CLOCK_GATING_ENABLE 1 /**< Used to enable clock gating when the driver is powered down*/
#define XMC_USBH_CLOCK_GATING_DISABLE 0 /**< Used to disable clock gating when the driver is fully powered*/
#define USB_CH_HCCHARx_MPS(x) (((uint32_t) x ) & (uint32_t)USB_CH_HCCHAR_MPS_Msk) /**< Masks maximum packet size information from the HCCHAR register value provided as input */
#define USB_CH_HCCHARx_EPNUM(x) (((uint32_t) x << USB_CH_HCCHAR_EPNum_Pos) & (uint32_t)USB_CH_HCCHAR_EPNum_Msk) /**< Shifts the value to the position of endpoint number(EPNum) in the HCCHAR register*/
#define USB_CH_HCCHARx_EPTYPE(x) (((uint32_t) x << USB_CH_HCCHAR_EPType_Pos) & (uint32_t)USB_CH_HCCHAR_EPType_Msk) /**< Shifts the value to the position of endpoint type(EPType) in the HCCHAR register*/
#define USB_CH_HCCHARx_MCEC(x) (((uint32_t) x << USB_CH_HCCHAR_MC_EC_Pos) & (uint32_t)USB_CH_HCCHAR_MC_EC_Msk) /**< Shifts the value to the position of multi-count(MC_EC) field in the HCCHAR register*/
#define USB_CH_HCCHARx_DEVADDR(x) (((uint32_t) x << USB_CH_HCCHAR_DevAddr_Pos) & (uint32_t)USB_CH_HCCHAR_DevAddr_Msk) /**< Shifts the value to the position of endpoint type(EPType) in the HCCHAR register*/
#define USB_CH_HCCHARx_EPDIR(x) (((uint32_t) x << USB_CH_HCCHAR_EPDir_Pos) & (uint32_t)USB_CH_HCCHAR_EPDir_Msk) /**< Shifts the value to the position of endpoint direction(EPDir) in the HCCHAR register*/
#define USB_CH_HCCHAR_LSDEV_Msk (((uint32_t) 0x1 << 15U) & 0x1U)
#define USB_CH_HCTSIZx_DPID(x) (((uint32_t) x << USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos) & (uint32_t)USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk) /**< Shifts the value to the position of packet ID (PID) in the HCTSIZ register*/
#define USB_CH_HCTSIZx_DPID_DATA0 (USB_CH_HCTSIZx_DPID(0U)) /**< Represents DATA toggle DATA0 as in HCTSIZ register*/
#define USB_CH_HCTSIZx_DPID_DATA2 (USB_CH_HCTSIZx_DPID(1U)) /**< Represents DATA toggle DATA2 as in HCTSIZ register*/
#define USB_CH_HCTSIZx_DPID_DATA1 (USB_CH_HCTSIZx_DPID(2U)) /**< Represents DATA toggle DATA1 as in HCTSIZ register*/
#define USB_CH_HCTSIZx_DPID_MDATA (USB_CH_HCTSIZx_DPID(3U)) /**< Represents DATA toggle MDATA as in HCTSIZ register*/
#define USB_CH_HCTSIZx_DPID_SETUP (USB_CH_HCTSIZx_DPID(3U)) /**< Represents SETUP token as in HCTSIZ register*/
#define USB_GRXSTSR_HOSTMODE_PktSts_IN_DATA_PKT 0x2 /**< Represents IN data token as in receive status pop register(GRXSTSP)*/
#define USB_GRXSTSR_HOSTMODE_PktSts_IN_TRSF_CPL 0x3 /**< Represents paket status information as in receive status pop register(GRXSTSP)*/
#define USB_CH_HCFG_FSLSSUP(x) (((uint32_t) x << USB_HCFG_FSLSSupp_Pos) & USB_HCFG_FSLSSupp_Msk) /**< Provides register value to update USB full speed related mask FLSSupp of register HCFG*/
#define USB_CH_HCFG_FSLSPCS(x) (((uint32_t) x ) & USB_HCFG_FSLSPclkSel_Msk) /**< Provides register value to update PHY clock selection in register HCFG*/
#define USB_CH_HCINTx_ALL (USB_CH_HCINTMSK_XferComplMsk_Msk | \
USB_CH_HCINTMSK_ChHltdMsk_Msk | \
USB_CH_HCINTMSK_StallMsk_Msk | \
USB_CH_HCINTMSK_NakMsk_Msk | \
USB_CH_HCINTMSK_AckMsk_Msk | \
USB_CH_HCINTMSK_XactErrMsk_Msk | \
USB_CH_HCINTMSK_BblErrMsk_Msk | \
USB_CH_HCINTMSK_FrmOvrunMsk_Msk | \
USB_CH_HCINTMSK_DataTglErrMsk_Msk) /**< Mask for selecting all channel related events*/
#define USB_CH_HCINTx_ERRORS (USB_CH_HCINTMSK_XactErrMsk_Msk | \
USB_CH_HCINTMSK_BblErrMsk_Msk | \
USB_CH_HCINTMSK_FrmOvrunMsk_Msk | \
USB_CH_HCINTMSK_DataTglErrMsk_Msk) /**< Mask for selecting all channel error related events*/
/*Macro to find pipe index using handle*/
#define USBH_PIPE_GET_INDEX(handle) (((uint32_t)handle - (uint32_t)USB0_CH0_BASE)/(0x20U)) /**< Macro provides index of the USB channel based on its base address*/
#define XMC_USBH_API_VERSION ((uint16_t)((uint16_t)XMC_LIB_MAJOR_VERSION << 8U) |XMC_LIB_MINOR_VERSION) /**< USBH low level driver API version */
/* General return codes */
#define XMC_USBH_DRIVER_OK 0 /**< Operation succeeded */
#define XMC_USBH_DRIVER_ERROR -1 /**< Unspecified error */
#define XMC_USBH_DRIVER_ERROR_BUSY -2 /**< Driver is busy*/
#define XMC_USBH_DRIVER_ERROR_TIMEOUT -3 /**< Timeout occurred */
#define XMC_USBH_DRIVER_ERROR_UNSUPPORTED -4 /**< Operation not supported*/
#define XMC_USBH_DRIVER_ERROR_PARAMETER -5 /**< Parameter error*/
#define XMC_USBH_DRIVER_ERROR_SPECIFIC -6 /**< Start of driver specific errors*/
/* USB Speed */
#define XMC_USBH_SPEED_LOW 0U /**< Low-speed USB*/
#define XMC_USBH_SPEED_FULL 1U /**< Full-speed USB*/
#define XMC_USBH_SPEED_HIGH 2U /**< High-speed USB*/
/* USB Endpoint Type */
#define XMC_USBH_ENDPOINT_CONTROL 0 /**< Control Endpoint*/
#define XMC_USBH_ENDPOINT_ISOCHRONOUS 1 /**< Isochronous Endpoint*/
#define XMC_USBH_ENDPOINT_BULK 2 /**< Bulk Endpoint*/
#define XMC_USBH_ENDPOINT_INTERRUPT 3 /**< Interrupt Endpoint*/
#define XMC_USBH_SignalEndpointEvent_t XMC_USBH_SignalPipeEvent_t /**< Legacy name for the pipe event handler*/
/****** USB Host Packet Information *****/
#define XMC_USBH_PACKET_TOKEN_Pos 0 /**< Packet token position*/
#define XMC_USBH_PACKET_TOKEN_Msk (0x0FUL << XMC_USBH_PACKET_TOKEN_Pos) /**< Packet token mask*/
#define XMC_USBH_PACKET_SETUP (0x01UL << XMC_USBH_PACKET_TOKEN_Pos) /**< SETUP Packet*/
#define XMC_USBH_PACKET_OUT (0x02UL << XMC_USBH_PACKET_TOKEN_Pos) /**< OUT Packet*/
#define XMC_USBH_PACKET_IN (0x03UL << XMC_USBH_PACKET_TOKEN_Pos) /**< IN Packet*/
#define XMC_USBH_PACKET_PING (0x04UL << XMC_USBH_PACKET_TOKEN_Pos) /**< PING Packet*/
#define XMC_USBH_PACKET_DATA_Pos 4 /**< Packet data PID position*/
#define XMC_USBH_PACKET_DATA_Msk (0x0FUL << XMC_USBH_PACKET_DATA_Pos) /**< Packet data PID mask*/
#define XMC_USBH_PACKET_DATA0 (0x01UL << XMC_USBH_PACKET_DATA_Pos) /**< DATA0 PID */
#define XMC_USBH_PACKET_DATA1 (0x02UL << XMC_USBH_PACKET_DATA_Pos) /**< DATA1 PID */
#define XMC_USBH_PACKET_SPLIT_Pos 8
#define XMC_USBH_PACKET_SPLIT_Msk (0x0FUL << XMC_USBH_PACKET_SPLIT_Pos)
#define XMC_USBH_PACKET_SSPLIT (0x08UL << XMC_USBH_PACKET_SPLIT_Pos) /**< SSPLIT Packet */
#define XMC_USBH_PACKET_SSPLIT_S (0x09UL << XMC_USBH_PACKET_SPLIT_Pos) /**< SSPLIT Packet: Data Start */
#define XMC_USBH_PACKET_SSPLIT_E (0x0AUL << XMC_USBH_PACKET_SPLIT_Pos) /**< SSPLIT Packet: Data End */
#define XMC_USBH_PACKET_SSPLIT_S_E (0x0BUL << XMC_USBH_PACKET_SPLIT_Pos) /**< SSPLIT Packet: Data All */
#define XMC_USBH_PACKET_CSPLIT (0x0CUL << XMC_USBH_PACKET_SPLIT_Pos) /**< CSPLIT Packet */
#define XMC_USBH_PACKET_PRE (1UL << 12) /**< PRE Token */
/****** USB Host Port Event *****/
#define XMC_USBH_EVENT_CONNECT (1UL << 0) /**< USB Device Connected to Port */
#define XMC_USBH_EVENT_DISCONNECT (1UL << 1) /**< USB Device Disconnected from Port */
#define XMC_USBH_EVENT_OVERCURRENT (1UL << 2) /**< USB Device caused Overcurrent */
#define XMC_USBH_EVENT_RESET (1UL << 3) /**< USB Reset completed */
#define XMC_USBH_EVENT_SUSPEND (1UL << 4) /**< USB Suspend occurred */
#define XMC_USBH_EVENT_RESUME (1UL << 5) /**< USB Resume occurred */
#define XMC_USBH_EVENT_REMOTE_WAKEUP (1UL << 6) /**< USB Device activated Remote Wakeup */
/****** USB Host Pipe Event *****/
#define XMC_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0) /**< Transfer completed */
#define XMC_USBH_EVENT_HANDSHAKE_NAK (1UL << 1) /**< NAK Handshake received */
#define XMC_USBH_EVENT_HANDSHAKE_NYET (1UL << 2) /**< NYET Handshake received */
#define XMC_USBH_EVENT_HANDSHAKE_MDATA (1UL << 3) /**< MDATA Handshake received */
#define XMC_USBH_EVENT_HANDSHAKE_STALL (1UL << 4) /**< STALL Handshake received */
#define XMC_USBH_EVENT_HANDSHAKE_ERR (1UL << 5) /**< ERR Handshake received */
#define XMC_USBH_EVENT_BUS_ERROR (1UL << 6) /**< Bus Error detected */
/*******************************************************************************
* ENUMS
*******************************************************************************/
/**
* @brief General power states of USB peripheral driver
*/
typedef enum XMC_USBH_POWER_STATE {
XMC_USBH_POWER_OFF, /**< Power off: no operation possible */
XMC_USBH_POWER_LOW, /**< Low Power mode: retain state, detect and signal wake-up events */
XMC_USBH_POWER_FULL /**< Power on: full operation at maximum performance */
} XMC_USBH_POWER_STATE_t;
/*******************************************************************************
* DATA STRUCTURES
*******************************************************************************/
/**
* @brief USB host Driver Version
*/
typedef struct XMC_USBH_DRIVER_VERSION {
uint16_t api; /**< API version */
uint16_t drv; /**< Driver version */
} XMC_USBH_DRIVER_VERSION_t;
/**
* @brief USB Host Port State
*/
typedef struct XMC_USBH_PORT_STATE {
uint32_t connected : 1; /**< USB Host Port connected flag */
uint32_t overcurrent : 1; /**< USB Host Port overcurrent flag */
uint32_t speed : 2; /**< USB Host Port speed setting (ARM_USB_SPEED_xxx) */
} XMC_USBH_PORT_STATE_t;
/**
* @brief USB Host Pipe Handle. It represents the physical address of a USB channel
*/
typedef uint32_t XMC_USBH_PIPE_HANDLE;
#define XMC_USBH_EP_HANDLE XMC_USBH_PIPE_HANDLE /**< Legacy name for pipe handle used by CMSIS*/
/**
* @brief USB Host Driver Capabilities.
*/
typedef struct XMC_USBH_CAPABILITIES {
uint32_t port_mask : 15; /**< Root HUB available Ports Mask */
uint32_t auto_split : 1; /**< Automatic SPLIT packet handling */
uint32_t event_connect : 1; /**< Signal Connect event */
uint32_t event_disconnect : 1; /**< Signal Disconnect event */
uint32_t event_overcurrent : 1; /**< Signal Overcurrent event */
} XMC_USBH_CAPABILITIES_t;
typedef void (*XMC_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event); /**< Pointer to \ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event. */
typedef void (*XMC_USBH_SignalPipeEvent_t) (XMC_USBH_PIPE_HANDLE pipe_hndl, uint32_t event); /**< Pointer to \ref ARM_USBH_SignalPipeEvent : Signal Pipe Event. */
/**
* @brief Access structure of USB Host Driver.
*/
typedef struct XMC_USBH_DRIVER {
XMC_USBH_DRIVER_VERSION_t (*GetVersion) (void); /**< Pointer to \ref ARM_USBH_GetVersion : Get driver version. */
XMC_USBH_CAPABILITIES_t (*GetCapabilities) (void); /**< Pointer to \ref ARM_USBH_GetCapabilities : Get driver capabilities. */
int32_t (*Initialize) (XMC_USBH_SignalPortEvent_t cb_port_event,
XMC_USBH_SignalPipeEvent_t cb_pipe_event); /**< Pointer to \ref ARM_USBH_Initialize : Initialize USB Host Interface. */
int32_t (*Uninitialize) (void); /**< Pointer to \ref ARM_USBH_Uninitialize : De-initialize USB Host Interface. */
int32_t (*PowerControl) (XMC_USBH_POWER_STATE_t state); /**< Pointer to \ref ARM_USBH_PowerControl : Control USB Host Interface Power. */
int32_t (*PortVbusOnOff) (uint8_t port, bool vbus); /**< Pointer to \ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off. */
int32_t (*PortReset) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortReset : Do Root HUB Port Reset. */
int32_t (*PortSuspend) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs). */
int32_t (*PortResume) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs). */
XMC_USBH_PORT_STATE_t (*PortGetState) (uint8_t port); /**< Pointer to \ref ARM_USBH_PortGetState : Get current Root HUB Port State. */
XMC_USBH_PIPE_HANDLE (*PipeCreate) (uint8_t dev_addr,
uint8_t dev_speed,
uint8_t hub_addr,
uint8_t hub_port,
uint8_t ep_addr,
uint8_t ep_type,
uint16_t ep_max_packet_size,
uint8_t ep_interval); /**< Pointer to \ref ARM_USBH_PipeCreate : Create Pipe in System. */
int32_t (*PipeModify) (XMC_USBH_PIPE_HANDLE pipe_hndl,
uint8_t dev_addr,
uint8_t dev_speed,
uint8_t hub_addr,
uint8_t hub_port,
uint16_t ep_max_packet_size); /**< Pointer to \ref ARM_USBH_PipeModify : Modify Pipe in System. */
int32_t (*PipeDelete) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeDelete : Delete Pipe from System. */
int32_t (*PipeReset) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeReset : Reset Pipe. */
int32_t (*PipeTransfer) (XMC_USBH_PIPE_HANDLE pipe_hndl,
uint32_t packet,
uint8_t *data,
uint32_t num); /**< Pointer to \ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe. */
uint32_t (*PipeTransferGetResult) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer. */
int32_t (*PipeTransferAbort) (XMC_USBH_PIPE_HANDLE pipe_hndl); /**< Pointer to \ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer. */
uint16_t (*GetFrameNumber) (void); /**< Pointer to \ref ARM_USBH_GetFrameNumber : Get current USB Frame Number. */
} const XMC_USBH_DRIVER_t;
/**
* @brief Structure to handle various states of USB host driver. An instance exists for each USB channel
*/
typedef struct XMC_USBH0_pipe {
uint32_t packet; /**< Holds packet token and PID information of ongoing data packet transaction*/
uint8_t *data; /**< Holds address of data buffer. It represents source buffer for OUT or SETUP transfer and
destination address for IN transfer*/
uint32_t num; /**< Number of bytes of data to be transmitted*/
uint32_t num_transferred_total; /**< Number of bytes transmitted or received at the moment*/
uint32_t num_transferring; /**< Number of bytes being transmitted currently*/
uint16_t ep_max_packet_size; /**< Maximum packet size for the selected pipe*/
uint16_t interval_reload; /**< For INTERRUPT or ISOCHRONOUS pipe, it represents the period for repeated transfer*/
uint16_t interval; /**< For INTERRUPT or ISOCHRONOUS pipe, it represents the decrementing count to reach 0 for initiating retransmission*/
uint8_t ep_type; /**< Endpoint type for selected pipe*/
uint8_t in_use; /**< Set to true when transfer is in progress and reset only after the /ref num of bytes is transferred*/
uint8_t transfer_active; /**< Set to true when a transfer has been initiated and reset when event for transfer complete occurs*/
uint8_t interrupt_triggered; /**< For INTERRUPT or ISOCHRONOUS pipe, indicates if retransmit timeout has occurred*/
uint8_t event; /**< Holds pipe specific event flags*/
} XMC_USBH0_pipe_t;
typedef struct xmc_usb_host_device {
USB0_GLOBAL_TypeDef *global_register; /**< Global register interface */
USB0_CH_TypeDef *host_channel_registers; /**< Host channel interface */
XMC_USBH_SignalPortEvent_t SignalPortEvent_cb; /**< Port event callback; set during init */
XMC_USBH_SignalPipeEvent_t SignalPipeEvent_cb; /**< Pipe event callback; set during init */
bool init_done; /**< init status */
XMC_USBH_POWER_STATE_t power_state; /**< USB Power status */
bool port_reset_active; /**< Port reset state */
} XMC_USBH0_DEVICE_t;
/*******************************************************************************
* API PROTOTYPES
*******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param gintsts USB global interrupt status.
* @return None.
*
* \par<b>Description:</b><br>
* Updates logical state of the USB host driver based on the input status value. It handles port interrupt
* and channel interrupt. It responsible for updating data toggle information for multi-packet data transmission.
* It executes the callback function on transfer completion and reception of data. It also does error management and
* calls the relevant callback functions to indicate it to the application.
*/
void XMC_USBH_HandleIrq (uint32_t gintsts);
/**
* @param ms Delay in milliseconds.
* @return uint8_t Value has no significance for the low level driver.
*
* \par<b>Description:</b><br>
* Function implements time delay logic. The USB host low level driver provides a weak definition
* for delay which has to re-implemented with time delay logic. The low level driver expects blocking
* implementation of the delay.
*/
uint8_t XMC_USBH_osDelay(uint32_t ms);
/**
* @param port Address of the port which has the pin used to enable VBUS charge pump.
* @param pin Pin number in the port selected in previous argument using which the VBUS charge pump has to be enabled.
* @return None
*
* \par<b>Description:</b><br>
* Configures the port pin with alternate output function 1. VBUS enabling pins work with alternate output function 1. \n
* <i>Note:</i>The input port pin should support USB VBUS as an alternate function. \n
* Typical ports that support VBUS enable are: P3_2 and P0_1.
*
*/
void XMC_USBH_Select_VBUS(XMC_GPIO_PORT_t* port, uint32_t pin);
/**
* @return USB host mode interrupt status. Bit field USB0_BASE->GINTSTS_HOSTMODE
*
* \par<b>Description:</b><br>
* Provides USB host global interrupt status. \n
* This value can be used to provide interrupt status to the IRQ handler function XMC_USBH_HandleIrq().
*
*/
uint32_t XMC_USBH_GetInterruptStatus(void);
/**
* @return None
*
* \par<b>Description:</b><br>
* De-asserts resume bit. \n
* The function shall be called 20ms after detecting port remote wakeup event. \n
*
*/
void XMC_USBH_TurnOffResumeBit(void);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif
#endif /* XMC_USBH_H */

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/**
* @file xmc_vadc_map.h
* @date 2016-11-17
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-15:
* - Initial version
*
* 2015-12-01:
* - Added:
* - XMC4300 device supported
*
* - Fixed:
* - Wrong MACRO name corrected for XMC4200/4100 devices.
* XMC_VADC_G3_SAMPLE renamed to XMC_VADC_G1_SAMPLE
*
* 2016-11-17:
* - Fixed: Add missing support for XMC47000
* - Fixed: Renamed XMC_CCU_41_ST2 to XMC_CCU_41_ST3
* - Added: New macros equivalent to th existing ones but with better naming.
* Old macros are kept for backward compatibility but they deprecated.
* - Added: ECAT support for XMC48/43
*
* @endcond
*
*/
#ifndef XMC_ADC_MAP_H
#define XMC_ADC_MAP_H
#ifdef __cplusplus
extern "C" {
#endif
/**********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#if ( UC_FAMILY == XMC1 )
/* Group request source Gating input connection mappings */
#define XMC_CCU_40_ST3 XMC_VADC_REQ_GT_A /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST3 */
#define XMC_CCU_40_ST2 XMC_VADC_REQ_GT_B /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST2 */
#define XMC_CCU_40_ST1 XMC_VADC_REQ_GT_C /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST1 */
#define XMC_CCU_40_ST0 XMC_VADC_REQ_GT_D /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST0 */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_CCU_80_ST3_A XMC_VADC_REQ_GT_E /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3A */
#define XMC_CCU_81_ST3 XMC_VADC_REQ_GT_F /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3 */
#endif
#if (UC_SERIES != XMC13 && UC_SERIES != XMC11)
#define XMC_LEDTS0_FN XMC_VADC_REQ_GT_I /**< @deprecated use instead XMC_VADC_REQ_GT_LEDTS0_FN */
#define XMC_LEDTS1_FN XMC_VADC_REQ_GT_J /**< @deprecated use instead XMC_VADC_REQ_GT_LEDTS1_FN */
#endif
#define XMC_ERU_0_PDOUT2 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT2 */
#define XMC_ERU_0_PDOUT3 XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT3 */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_CCU_80_ST0 XMC_VADC_REQ_GT_M /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST0 */
#define XMC_CCU_80_ST1 XMC_VADC_REQ_GT_N /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST1 */
#endif
#define XMC_ERU_0_PDOUT0 XMC_VADC_REQ_GT_O /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT0 */
#define XMC_ERU_0_PDOUT1 XMC_VADC_REQ_GT_P /**< @deprecated use instead XMC_VADC_REQ_GT_ERU0_PDOUT1 */
/* Group request source Trigger input connection mappings */
#define XMC_CCU_40_SR2 XMC_VADC_REQ_TR_A /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR2 */
#define XMC_CCU_40_SR3 XMC_VADC_REQ_TR_B /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR3 */
#if (UC_SERIES != XMC11)
#define XMC_BCCU0_TRIGOUT XMC_VADC_REQ_TR_F /**< @deprecated use instead XMC_VADC_REQ_TR_BCCU0_TRIGOUT0, XMC_VADC_REQ_TR_G0_BCCU0_TRIGOUT0 or XMC_VADC_REQ_TR_G1_BCCU0_TRIGOUT1 */
#endif
#define XMC_ERU_0_IOUT2 XMC_VADC_REQ_TR_G /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT2 */
#define XMC_ERU_0_IOUT3 XMC_VADC_REQ_TR_H /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT3 */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_CCU_80_SR2 XMC_VADC_REQ_TR_I /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR2 */
#define XMC_CCU_80_SR3 XMC_VADC_REQ_TR_J /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR3 */
#endif
#define XMC_ERU_0_IOUT0 XMC_VADC_REQ_TR_M /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT0 */
#define XMC_ERU_0_IOUT1 XMC_VADC_REQ_TR_N /**< @deprecated use instead XMC_VADC_REQ_TR_ERU0_IOUT1 */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_POSIF_0_SR1 XMC_VADC_REQ_TR_O /**< @deprecated use instead XMC_VADC_REQ_TR_POSIF0_SR1 */
#endif
#define XMC_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< @deprecated use instead XMC_VADC_REQ_TR_REQ_GT_SEL */
/* Group request source Gating input connection mappings */
#define XMC_VADC_REQ_GT_CCU40_ST3 XMC_VADC_REQ_GT_A /**< VADC Gating input A */
#define XMC_VADC_REQ_GT_CCU40_ST2 XMC_VADC_REQ_GT_B /**< VADC Gating input B */
#define XMC_VADC_REQ_GT_CCU40_ST1 XMC_VADC_REQ_GT_C /**< VADC Gating input C */
#define XMC_VADC_REQ_GT_CCU40_ST0 XMC_VADC_REQ_GT_D /**< VADC Gating input D */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_VADC_REQ_GT_CCU80_ST3A XMC_VADC_REQ_GT_E /**< VADC Gating input E */
#define XMC_VADC_REQ_GT_CCU80_ST3 XMC_VADC_REQ_GT_F /**< VADC Gating input F */
#endif
#if (UC_SERIES != XMC13 && UC_SERIES != XMC11)
#define XMC_VADC_REQ_GT_LEDTS0_FN XMC_VADC_REQ_GT_I /**< VADC Gating input I */
#define XMC_VADC_REQ_GT_LEDTS1_FN XMC_VADC_REQ_GT_J /**< VADC Gating input J */
#endif
#define XMC_VADC_REQ_GT_ERU0_PDOUT2 XMC_VADC_REQ_GT_K /**< VADC Gating input K */
#define XMC_VADC_REQ_GT_ERU0_PDOUT3 XMC_VADC_REQ_GT_L /**< VADC Gating input L */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_VADC_REQ_GT_CCU80_ST0 XMC_VADC_REQ_GT_M /**< VADC Gating input M */
#define XMC_VADC_REQ_GT_CCU80_ST1 XMC_VADC_REQ_GT_N /**< VADC Gating input N */
#endif
#define XMC_VADC_REQ_GT_ERU0_PDOUT0 XMC_VADC_REQ_GT_O /**< VADC Gating input O */
#define XMC_VADC_REQ_GT_ERU0_PDOUT1 XMC_VADC_REQ_GT_P /**< VADC Gating input P */
/* Group request source Trigger input connection mappings */
#define XMC_VADC_REQ_TR_CCU40_SR2 XMC_VADC_REQ_TR_A /**< VADC Trigger input A */
#define XMC_VADC_REQ_TR_CCU40_SR3 XMC_VADC_REQ_TR_B /**< VADC Trigger input B */
#if (UC_SERIES != XMC11)
#define XMC_VADC_REQ_TR_BCCU0_TRIGOUT0 XMC_VADC_REQ_TR_F /**< VADC Global Background Source Trigger input F */
#define XMC_VADC_REQ_TR_G0_BCCU0_TRIGOUT0 XMC_VADC_REQ_TR_F /**< VADC Group 0 Trigger input F */
#define XMC_VADC_REQ_TR_G1_BCCU0_TRIGOUT1 XMC_VADC_REQ_TR_F /**< VADC Group1 Trigger input F */
#endif
#define XMC_VADC_REQ_TR_ERU0_IOUT2 XMC_VADC_REQ_TR_G /**< VADC Trigger input G */
#define XMC_VADC_REQ_TR_ERU0_IOUT3 XMC_VADC_REQ_TR_H /**< VADC Trigger input H */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_VADC_REQ_TR_CCU80_SR2 XMC_VADC_REQ_TR_I /**< VADC Trigger input I */
#define XMC_VADC_REQ_TR_CCU80_SR3 XMC_VADC_REQ_TR_J /**< VADC Trigger input J */
#endif
#define XMC_VADC_REQ_TR_ERU0_IOUT0 XMC_VADC_REQ_TR_M /**< VADC Trigger input M */
#define XMC_VADC_REQ_TR_ERU0_IOUT1 XMC_VADC_REQ_TR_N /**< VADC Trigger input N */
#if (UC_SERIES != XMC12 && UC_SERIES != XMC11)
#define XMC_VADC_REQ_TR_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Trigger input O */
#endif
#define XMC_VADC_REQ_TR_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< VADC Trigger input P */
#endif
#if ( UC_FAMILY == XMC4 )
/* Group request source Gating input connection mappings */
#define XMC_CCU_40_ST3 XMC_VADC_REQ_GT_A /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST3 */
#define XMC_CCU_41_ST3 XMC_VADC_REQ_GT_B /**< @deprecated use instead XMC_VADC_REQ_GT_CCU41_ST3 */
#define XMC_CCU_40_SR0 XMC_VADC_REQ_GT_C /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_SR0 */
#define XMC_CCU_41_SR1 XMC_VADC_REQ_GT_D /**< @deprecated use instead XMC_VADC_REQ_GT_CCU41_SR1 */
#define XMC_CCU_80_ST3_A XMC_VADC_REQ_GT_E /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3A */
#define XMC_CCU_80_ST3_B XMC_VADC_REQ_GT_F /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_ST3B */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_CCU_81_ST3_A XMC_VADC_REQ_GT_G /**< @deprecated use instead XMC_VADC_REQ_GT_CCU81_ST3A */
#define XMC_CCU_81_ST3_B XMC_VADC_REQ_GT_H /**< @deprecated use instead XMC_VADC_REQ_GT_CCU81_ST3B */
#endif
#define XMC_DAC_0_SGN XMC_VADC_REQ_GT_I /**< @deprecated use instead XMC_VADC_REQ_GT_DAC0_SGN, XMC_VADC_REQ_GT_G0_DAC0_SGN or XMC_VADC_REQ_GT_G2_DAC0_SGN */
#define XMC_DAC_1_SGN XMC_VADC_REQ_GT_I /**< @deprecated use instead XMC_VADC_REQ_GT_DAC0_SGN, XMC_VADC_REQ_GT_G1_DAC1_SGN or XMC_VADC_REQ_GT_G3_DAC1_SGN */
#define XMC_LEDTS_FN XMC_VADC_REQ_GT_J /**< @deprecated use instead XMC_VADC_REQ_GT_LEDTS_FN */
#define XMC_VADC_G0_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G0_VADC_G1BFLOUT0 */
#define XMC_VADC_G1_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G1_VADC_G0BFLOUT0 */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_G2_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G2_VADC_G3BFLOUT0 */
#define XMC_VADC_G3_BLOUT0 XMC_VADC_REQ_GT_K /**< @deprecated use instead XMC_VADC_REQ_GT_VADC_G1BFLOUT0 or XMC_VADC_REQ_GT_G3_VADC_G2BFLOUT0 */
#endif
#define XMC_VADC_G0_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G0_VADC_G3SAMPLE */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_G1_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G1_VADC_G0SAMPLE */
#define XMC_VADC_G2_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G2_VADC_G1SAMPLE */
#define XMC_VADC_G3_SAMPLE XMC_VADC_REQ_GT_L /**< @deprecated use instead XMC_VADC_REQ_GT_G3_VADC_G2SAMPLE */
#endif
#define XMC_CCU_80_SR0 XMC_VADC_REQ_GT_M /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_SR0 */
#define XMC_CCU_80_SR1 XMC_VADC_REQ_GT_N /**< @deprecated use instead XMC_VADC_REQ_GT_CCU80_SR1 */
#define XMC_ERU_1_PDOUT0 XMC_VADC_REQ_GT_O /**< @deprecated use instead XMC_VADC_REQ_GT_ERU1_PDOUT0 */
#define XMC_ERU_1_PDOUT1 XMC_VADC_REQ_GT_P /**< @deprecated use instead XMC_VADC_REQ_GT_ERU1_PDOUT1 */
/* Group request source Trigger input connection mappings */
#define XMC_CCU_40_SR2 XMC_VADC_REQ_TR_A /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR2 */
#define XMC_CCU_40_SR3 XMC_VADC_REQ_TR_B /**< @deprecated use instead XMC_VADC_REQ_TR_CCU40_SR3 */
#define XMC_CCU_41_SR2 XMC_VADC_REQ_TR_C /**< @deprecated use instead XMC_VADC_REQ_TR_CCU41_SR2 */
#define XMC_CCU_41_SR3 XMC_VADC_REQ_TR_D /**< @deprecated use instead XMC_VADC_REQ_TR_CCU41_SR3 */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_CCU_42_SR3 XMC_VADC_REQ_TR_E /**< @deprecated use instead XMC_VADC_REQ_TR_CCU42_SR3 */
#define XMC_CCU_43_SR3 XMC_VADC_REQ_TR_F /**< @deprecated use instead XMC_VADC_REQ_TR_CCU43_SR3 */
#endif
#define XMC_CCU_80_SR2 XMC_VADC_REQ_TR_I /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR2 */
#define XMC_CCU_80_SR3 XMC_VADC_REQ_TR_J /**< @deprecated use instead XMC_VADC_REQ_TR_CCU80_SR3 */
#define XMC_CCU_81_SR2 XMC_VADC_REQ_TR_K /**< @deprecated use instead XMC_VADC_REQ_TR_CCU81_SR2 */
#define XMC_CCU_81_SR3 XMC_VADC_REQ_TR_L /**< @deprecated use instead XMC_VADC_REQ_TR_CCU81_SR3 */
#define XMC_ERU_1_IOUT0 XMC_VADC_REQ_TR_M /**< @deprecated use instead XMC_VADC_REQ_TR_ERU1_IOUT0 */
#define XMC_ERU_1_IOUT1 XMC_VADC_REQ_TR_N /**< @deprecated use instead XMC_VADC_REQ_TR_ERU1_IOUT1, XMC_VADC_REQ_TR_G0_ERU1_IOUT1 or XMC_VADC_REQ_TR_G1_ERU1_IOUT1 */
#define XMC_ERU_1_IOUT2 XMC_VADC_REQ_TR_N /**< @deprecated use instead XMC_VADC_REQ_TR_ERU1_IOUT1, XMC_VADC_REQ_TR_G2_ERU1_IOUT2 or XMC_VADC_REQ_TR_G3_ERU1_IOUT1 */
#if ( (UC_SERIES != XMC43) )
#define XMC_POSIF_0_SR1 XMC_VADC_REQ_TR_O /**< @deprecated use instead XMC_VADC_REQ_TR_POSIF0_SR1, XMC_VADC_REQ_TR_G0_POSIF0_SR1 or XMC_VADC_REQ_TR_G2_POSIF0_SR1 */
#endif
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_POSIF_1_SR1 XMC_VADC_REQ_TR_O /**< @deprecated use instead XMC_VADC_REQ_TR_POSIF0_SR1, XMC_VADC_REQ_TR_G1_POSIF0_SR1 or XMC_VADC_REQ_TR_G3_POSIF0_SR1 */
#endif
#define XMC_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< @deprecated use instead XMC_VADC_REQ_GT_CCU40_ST3 */
/* Group request source Gating input connection mappings */
#define XMC_VADC_REQ_GT_CCU40_ST3 XMC_VADC_REQ_GT_A /**< VADC Gating input A */
#define XMC_VADC_REQ_GT_CCU41_ST3 XMC_VADC_REQ_GT_B /**< VADC Gating input B */
#define XMC_VADC_REQ_GT_CCU40_SR0 XMC_VADC_REQ_GT_C /**< VADC Gating input C */
#define XMC_VADC_REQ_GT_CCU41_SR1 XMC_VADC_REQ_GT_D /**< VADC Gating input D */
#define XMC_VADC_REQ_GT_CCU80_ST3A XMC_VADC_REQ_GT_E /**< VADC Gating input E */
#define XMC_VADC_REQ_GT_CCU80_ST3B XMC_VADC_REQ_GT_F /**< VADC Gating input F */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_REQ_GT_CCU81_ST3A XMC_VADC_REQ_GT_G /**< VADC Gating input G */
#define XMC_VADC_REQ_GT_CCU81_ST3B XMC_VADC_REQ_GT_H /**< VADC Gating input H */
#endif
#define XMC_VADC_REQ_GT_DAC0_SGN XMC_VADC_REQ_GT_I /**< VADC Global Background Source Gating input I */
#define XMC_VADC_REQ_GT_G0_DAC0_SGN XMC_VADC_REQ_GT_I /**< VADC Group 0 Gating input I */
#define XMC_VADC_REQ_GT_G1_DAC1_SGN XMC_VADC_REQ_GT_I /**< VADC Group 1 Gating input I */
#define XMC_VADC_REQ_GT_G2_DAC0_SGN XMC_VADC_REQ_GT_I /**< VADC Group 2 Gating input I */
#define XMC_VADC_REQ_GT_G3_DAC1_SGN XMC_VADC_REQ_GT_I /**< VADC Group 3 Gating input I */
#define XMC_VADC_REQ_GT_LEDTS_FN XMC_VADC_REQ_GT_J /**< VADC Gating input J */
#define XMC_VADC_REQ_GT_VADC_G1BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Global Background Source Gating input K */
#define XMC_VADC_REQ_GT_G0_VADC_G1BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 0 Gating input K */
#define XMC_VADC_REQ_GT_G1_VADC_G0BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 1 Gating input K */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_REQ_GT_G2_VADC_G3BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 2 Gating input K */
#define XMC_VADC_REQ_GT_G3_VADC_G2BFLOUT0 XMC_VADC_REQ_GT_K /**< VADC Group 3 Gating input K */
#endif
#define XMC_VADC_REQ_GT_G0_VADC_G3SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 0 Gating input L */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_REQ_GT_G1_VADC_G0SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 1 Gating input L */
#define XMC_VADC_REQ_GT_G2_VADC_G1SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 2 Gating input L */
#define XMC_VADC_REQ_GT_G3_VADC_G2SAMPLE XMC_VADC_REQ_GT_L /**< VADC Group 3 Gating input L */
#endif
#define XMC_VADC_REQ_GT_CCU80_SR0 XMC_VADC_REQ_GT_M /**< VADC Gating input M */
#define XMC_VADC_REQ_GT_CCU80_SR1 XMC_VADC_REQ_GT_N /**< VADC Gating input N */
#define XMC_VADC_REQ_GT_ERU1_PDOUT0 XMC_VADC_REQ_GT_O /**< VADC Gating input O */
#define XMC_VADC_REQ_GT_ERU1_PDOUT1 XMC_VADC_REQ_GT_P /**< VADC Gating input P */
/* Group request source Trigger input connection mappings */
#define XMC_VADC_REQ_TR_CCU40_SR2 XMC_VADC_REQ_TR_A /**< VADC Trigger input A */
#define XMC_VADC_REQ_TR_CCU40_SR3 XMC_VADC_REQ_TR_B /**< VADC Trigger input B */
#define XMC_VADC_REQ_TR_CCU41_SR2 XMC_VADC_REQ_TR_C /**< VADC Trigger input C */
#define XMC_VADC_REQ_TR_CCU41_SR3 XMC_VADC_REQ_TR_D /**< VADC Trigger input D */
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_REQ_TR_CCU42_SR3 XMC_VADC_REQ_TR_E /**< VADC Trigger input E */
#define XMC_VADC_REQ_TR_CCU43_SR3 XMC_VADC_REQ_TR_F /**< VADC Trigger input F */
#endif
#if ((UC_SERIES == XMC48) || (UC_SERIES == XMC43))
#define XMC_VADC_REQ_TR_ECAT_SYNC0 XMC_VADC_REQ_TR_G /**< VADC Trigger input G */
#define XMC_VADC_REQ_TR_ECAT_SYNC1 XMC_VADC_REQ_TR_H /**< VADC Trigger input H */
#endif
#define XMC_VADC_REQ_TR_CCU80_SR2 XMC_VADC_REQ_TR_I /**< VADC Trigger input I */
#define XMC_VADC_REQ_TR_CCU80_SR3 XMC_VADC_REQ_TR_J /**< VADC Trigger input J */
#define XMC_VADC_REQ_TR_CCU81_SR2 XMC_VADC_REQ_TR_K /**< VADC Trigger input K */
#define XMC_VADC_REQ_TR_CCU81_SR3 XMC_VADC_REQ_TR_L /**< VADC Trigger input L */
#define XMC_VADC_REQ_TR_ERU1_IOUT0 XMC_VADC_REQ_TR_M /**< VADC Trigger input M */
#define XMC_VADC_REQ_TR_ERU1_IOUT1 XMC_VADC_REQ_TR_M /**< VADC Global Background Source Trigger input N */
#define XMC_VADC_REQ_TR_G0_ERU1_IOUT1 XMC_VADC_REQ_TR_N /**< VADC Group 0 Trigger input N */
#define XMC_VADC_REQ_TR_G1_ERU1_IOUT1 XMC_VADC_REQ_TR_N /**< VADC Group 1 Trigger input N */
#define XMC_VADC_REQ_TR_G2_ERU1_IOUT2 XMC_VADC_REQ_TR_N /**< VADC Group 2 Trigger input N */
#define XMC_VADC_REQ_TR_G3_ERU1_IOUT2 XMC_VADC_REQ_TR_N /**< VADC Group 3 Trigger input N */
#if ( (UC_SERIES != XMC43) )
#define XMC_VADC_REQ_TR_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Global Background Source Trigger input O */
#define XMC_VADC_REQ_TR_G0_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 0 Trigger input O */
#define XMC_VADC_REQ_TR_G1_POSIF1_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 1 Trigger input O */
#endif
#if ( (UC_SERIES != XMC43) && (UC_SERIES != XMC42) && (UC_SERIES != XMC41))
#define XMC_VADC_REQ_TR_G2_POSIF0_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 2 Trigger input O */
#define XMC_VADC_REQ_TR_G3_POSIF1_SR1 XMC_VADC_REQ_TR_O /**< VADC Group 3 Trigger input O */
#endif
#define XMC_VADC_REQ_TR_REQ_GT_SEL XMC_VADC_REQ_TR_P /**< VADC Trigger input P */
#endif
#ifdef __cplusplus
}
#endif
#endif

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/**
* @file xmc_wdt.h
* @date 2015-08-06
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
* - Documentation updates <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
*
* 2015-08-06:
* - Bug fix in XMC_WDT_SetDebugMode() API, Wrong register is being configured.<br>
* @endcond
*/
#ifndef XMC_WDT_H
#define XMC_WDT_H
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_common.h"
#include "xmc_scu.h"
/**
* @addtogroup XMClib XMC Peripheral Library
* @{
*/
/**
* @addtogroup WDT
* @brief Watchdog driver for the XMC microcontroller family.
*
* The watchdog unit (WDT) improves the system integrity, by triggering the system reset request to bring the system
* back from the unresponsive state to normal operation.
*
* This LLD provides the Configuration structure XMC_WDT_CONFIG_t and initialization function XMC_WDT_Init().\n
* It can be used to:
* -# Start or Stop the watchdog timer. (XMC_WDT_Start() and XMC_WDT_Stop())
* -# Service the watchdog timer. (XMC_WDT_Service())
* -# Configure the service window upper bound and lower bound timing values. (XMC_WDT_SetWindowBounds())
* -# Enable the generation of the pre-warning event for the first overflow of the timer. (XMC_WDT_SetMode())
* -# Clear the pre-warning alarm event. It is mandatory to clear the flag during pre-warning alarm ISR, to stop
generating reset request for the second overflow of the timer. (XMC_WDT_ClearAlarm())
* -# Suspend the watchdog timer during Debug HALT mode. (XMC_WDT_SetDebugMode())
* -# Configure service indication pulse width.(XMC_WDT_SetServicePulseWidth())
*
* @{
*/
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_WDT_MAGIC_WORD (0xABADCAFEU) /* Magic word to be written in Service Register (SRV),
to service or feed the watchdog. */
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/**
* Defines working modes for watchdog. Use type XMC_WDT_MODE_t for this enum.
*/
typedef enum XMC_WDT_MODE
{
XMC_WDT_MODE_TIMEOUT = (uint32_t)0x0 << WDT_CTR_PRE_Pos, /**< Generates reset request as soon as the timer overflow
occurs. */
XMC_WDT_MODE_PREWARNING = (uint32_t)0x1 << WDT_CTR_PRE_Pos /**< Generates an alarm event for the first overflow. And
reset request after subsequent overflow, if not
serviced after first overflow. */
} XMC_WDT_MODE_t;
/**
* Defines debug behaviour of watchdog when the CPU enters HALT mode. Use type XMC_WDT_DEBUG_MODE_t for this enum.
*/
typedef enum XMC_WDT_DEBUG_MODE
{
XMC_WDT_DEBUG_MODE_STOP = (uint32_t)0x0 << WDT_CTR_DSP_Pos, /**< Watchdog counter is paused during debug halt. */
XMC_WDT_DEBUG_MODE_RUN = (uint32_t)0x1 << WDT_CTR_DSP_Pos /**< Watchdog counter is not paused during debug halt. */
} XMC_WDT_DEBUG_MODE_t;
/*********************************************************************************************************************
* DATA STRUCTURES
********************************************************************************************************************/
/* Anonymous structure/union guard start */
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined(__TASKING__)
#pragma warning 586
#endif
/**
* Structure for initializing watchdog timer. Use type XMC_WDT_CONFIG_t for this structure.
*/
typedef struct XMC_WDT_CONFIG
{
uint32_t window_upper_bound; /**< Upper bound for service window (WUB). Reset request is generated up on overflow of
timer. ALways upper bound value has to be more than lower bound value. If it is set
lower than WLB, triggers a system reset after timer crossed upper bound value.\n
Range: [0H to FFFFFFFFH] */
uint32_t window_lower_bound; /**< Lower bound for servicing window (WLB). Setting the lower bound to 0H disables the
window mechanism.\n
Range: [0H to FFFFFFFFH] */
union
{
struct
{
uint32_t : 1;
uint32_t prewarn_mode : 1; /**< Pre-warning mode (PRE). This accepts boolean values as input. */
uint32_t : 2;
uint32_t run_in_debug_mode : 1; /**< Watchdog timer behaviour during debug (DSP). This accepts boolean values as input. */
uint32_t : 3;
uint32_t service_pulse_width : 8; /**< Service Indication Pulse Width (SPW). Generated Pulse width is of (SPW+1),
in fwdt cycles.\n
Range: [0H to FFH] */
uint32_t : 16;
};
uint32_t wdt_ctr; /* Value of operation mode control register (CTR). It’s bit fields are represented by above
union members. */
};
} XMC_WDT_CONFIG_t;
/* Anonymous structure/union guard end */
#if defined(__CC_ARM)
#pragma pop
#elif defined(__TASKING__)
#pragma warning restore
#endif
/*********************************************************************************************************************
* API PROTOTYPES
********************************************************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC4
* Enables watchdog clock and releases watchdog reset.\n
* \endif
* \if XMC1
* Enables watchdog clock.\n
* \endif
* \par
* This API is invoked by XMC_WDT_Init() and therefore no need to call it explicitly during watchdog initialization
* sequence. Invoke this API to enable watchdog once again if the watchdog is disabled by invoking XMC_WDT_Disable().
*
* \par<b>Note:</b><br>
* \if XMC4
* 1. It is required to configure the watchdog, again after invoking XMC_WDT_Disable(). Since all the registers are
* reset with default values.
* \endif
* \if XMC1
* 1. Not required to configure the watchdog again after invoking XMC_WDT_Disable(). Since the registers retains with
* the configured values.
* \endif
* \par<b>Related APIs:</b><BR>
* XMC_WDT_Init(), XMC_WDT_Disable()
*/
void XMC_WDT_Enable(void);
/**
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* \if XMC4
* Disables the clock and resets watchdog timer.\n
* \endif
* \if XMC1
* Disables the clock to the watchdog timer.\n
* \endif
*
* \par<b>Note:</b><br>
* \if XMC4
* 1. Resets the registers with default values. So XMC_WDT_Init() has to be invoked again to configure the watchdog.
* \endif
* \if XMC1
* 1. After invoking XMC_WDT_Disable(), all register values are displayed with 0F in debugger. Once enabled by
calling XMC_WDT_Enable(), previous configured register values are displayed. No need to invoke XMC_WDT_Init()
again.
* \endif
* \par<b>Related APIs:</b><BR>
* XMC_WDT_Enable()
*/
void XMC_WDT_Disable(void);
/**
* @param config pointer to a constant watchdog configuration data structure. Refer data structure XMC_WDT_CONFIG_t
* for detail.
*
* @return None
*
* \par<b>Description:</b><br>
* Initializes and configures watchdog with configuration data pointed by \a config.\n
* \par
* It invokes XMC_WDT_Enable() to enable clock and release reset. Then configures the lower and upper window bounds,
* working mode (timeout/pre-warning), debug behaviour and service request indication pulse width.
*
* \par<b>Note:</b><br>
* 1. With out invoking this XMC_WDT_Init() or XMC_WDT_Enable(), invocation of other APIs like XMC_WDT_SetWindowBounds(),
* XMC_WDT_SetMode(), XMC_WDT_SetServicePulseWidth(), XMC_WDT_SetDebugMode(), XMC_WDT_Start(), XMC_WDT_GetCounter(),
* XMC_WDT_Service(), XMC_WDT_ClearAlarm() has no affect.
*/
void XMC_WDT_Init(const XMC_WDT_CONFIG_t *const config);
/**
* @param lower_bound specifies watchdog window lower bound in terms of watchdog clock (fWDT) cycles.
* Range: [0H to FFFFFFFFH].
* @param upper_bound specifies watchdog window upper bound in terms of watchdog clock (fWDT) cycles.
* Range: [0H to FFFFFFFFH].
*
* @return None
*
* \par<b>Description:</b><br>
* Sets watchdog window lower and upper bounds by updating WLB and WUB registers.\n
* \par
* Window lower and upper bounds are set during initialization in XMC_WDT_Init(). Invoke this API to alter the values as
* needed later in the program. This upper bound and lower bound can be calculated by using the below formula\n
* upper_bound or lower_bound = desired_boundary_time(sec) * fwdt(hz)
*
* \par<b>Note:</b>
* 1. Always ensure that upper_bound is greater than the lower_bound value. If not, whenever timer crosses the
* upper_bound value it triggers the reset(wdt_rst_req) of the controller.
*/
__STATIC_INLINE void XMC_WDT_SetWindowBounds(uint32_t lower_bound, uint32_t upper_bound)
{
WDT->WLB = lower_bound;
WDT->WUB = upper_bound;
}
/**
* @param mode is one of the working modes of the watchdog timer, i.e timeout or pre-warning. Refer @ref XMC_WDT_MODE_t
* for valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Sets watchdog working mode (timeout or pre-warning) by updating PRE bit of CTR register.\n
* \par
* The working mode is set during initialization in XMC_WDT_Init(). Invoke this API to alter the mode as needed later in
* the program.
*/
__STATIC_INLINE void XMC_WDT_SetMode(XMC_WDT_MODE_t mode)
{
WDT->CTR = (WDT->CTR & (uint32_t)~WDT_CTR_PRE_Msk) | (uint32_t)mode;
}
/**
* @param service_pulse_width specifies Service indication pulse width in terms of fwdt.
* Range: [0H – FFH].
* @return None
*
* \par<b>Description:</b><br>
* Sets service indication pulse width by updating SPW bit field of CTR register.\n
* \par
* The service indication pulse (with width service_pulse_width + 1 in fwdt cycles) is generated on successful servicing
* or feeding of watchdog. The pulse width is initially set during initialization in XMC_WDT_Init(). Invoke this API to
* alter the width as needed later in the program.
*/
__STATIC_INLINE void XMC_WDT_SetServicePulseWidth(uint8_t service_pulse_width)
{
WDT->CTR = (WDT->CTR & (uint32_t)~WDT_CTR_SPW_Msk) | ((uint32_t)service_pulse_width << WDT_CTR_SPW_Pos);
}
/**
* @param debug_mode running state of watchdog during debug halt mode. Refer @ref XMC_WDT_DEBUG_MODE_t for
* valid values.
*
* @return None
*
* \par<b>Description:</b><br>
* Sets debug behaviour of watchdog by modifying DSP bit of CTR register.\n
* \par
* Depending upon DSP bit, the watchdog timer stops when CPU is in HALT mode. The debug behaviour is initially set as
* XMC_WDT_DEBUG_MODE_STOP during initialization in XMC_WDT_Init(). Invoke this API to change the debug behaviour as
* needed later in the program.
*/
__STATIC_INLINE void XMC_WDT_SetDebugMode(const XMC_WDT_DEBUG_MODE_t debug_mode)
{
WDT->CTR = (WDT->CTR & (uint32_t)~WDT_CTR_DSP_Msk) | (uint32_t)debug_mode;
}
/**
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Start the watchdog timer by setting ENB bit of CTR register.\n
* \par
* Invoke this API to start the watchdog after initialization, or to resume the watchdog when
* paused by invoking XMC_WDT_Stop().
*
* \par<b>Related APIs:</b><BR>
* XMC_WDT_Init(), XMC_WDT_Stop()
*/
__STATIC_INLINE void XMC_WDT_Start(void)
{
WDT->CTR |= (uint32_t)WDT_CTR_ENB_Msk;
}
/**
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Pauses watchdog timer by resetting ENB bit of CTR register.\n
* \par
* Invoke this API to pause the watchdog as needed in the program e.g. debugging through software control.
*
* \par<b>Related APIs:</b><BR>
* XMC_WDT_Init(), XMC_WDT_Stop()
*/
__STATIC_INLINE void XMC_WDT_Stop(void)
{
WDT->CTR &= (uint32_t)~WDT_CTR_ENB_Msk;
}
/**
* @param None
*
* @return uint32_t Current count value of watchdog timer register (TIM).
* Range: [0H to FFFFFFFFH]
*
* \par<b>Description:</b><br>
* Reads current count of timer register (TIM).\n
* \par
* Invoke this API before servicing or feeding the watchdog to check whether count is between lower and upper
* window bounds.
*
* \par<b>Related APIs:</b><BR>
* XMC_WDT_Service()
*/
__STATIC_INLINE uint32_t XMC_WDT_GetCounter(void)
{
return WDT->TIM;
}
/**
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Services or feeds the watchdog by writing the Magic word in SRV register.\n
* \par
* Service watchdog when count value of watchdog timer is between lower and upper window bounds. Successful servicing
* will reset watchdog timer (TIM register) to 0H and generate service indication pulse.
*
* \par<b>Note:</b><br>
* 1. invoking this API when count value of watchdog timer is less than window lower bound results
* wrong servicing and immediately triggers reset request.
*
* \par<b>Related APIs:</b><BR>
* XMC_WDT_GetCounter(), XMC_WDT_SetWindowBounds(), XMC_WDT_SetServicePulseWidth()
*/
__STATIC_INLINE void XMC_WDT_Service(void)
{
WDT->SRV = XMC_WDT_MAGIC_WORD;
}
/**
* @param None
*
* @return None
*
* \par<b>Description:</b><br>
* Clears pre-warning alarm by setting ALMC bit in WDTCLR register.\n
* \par
* In pre-warning mode, first overflow of the timer upper window bound fires the pre-warning alarm. XMC_WDT_ClearAlarm()
* must be invoked to clear the alarm alarm. After clearing of the alarm, watchdog timer must be serviced within valid
* time window. Otherwise watchdog timer triggers the reset request up on crossing the upper bound value in a subsequent
* cycle.
*
* \par<b>Related APIs:</b><BR>
* XMC_WDT_Service(), XMC_WDT_SetMode()
*/
__STATIC_INLINE void XMC_WDT_ClearAlarm(void)
{
WDT->WDTCLR = WDT_WDTCLR_ALMC_Msk;
}
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* XMC_WDT_H */

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/**
* @file xmc4_eru.c
* @date 2015-02-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* @endcond
*/
#include "xmc_eru.h"
#if UC_FAMILY == XMC4
#include "xmc_scu.h"
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/* Enable the clock and De-assert the ERU module from the reset state. */
void XMC_ERU_Enable(XMC_ERU_t *const eru)
{
#if defined(XMC_ERU1)
if (eru == XMC_ERU1)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ERU1);
#endif
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ERU1);
}
#else
XMC_UNUSED_ARG(eru);
#endif
}
/* Disable the clock and Reset the ERU module. */
void XMC_ERU_Disable(XMC_ERU_t *const eru)
{
#if defined(XMC_ERU1)
if (eru == XMC_ERU1)
{
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ERU1);
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ERU1);
#endif
}
#else
XMC_UNUSED_ARG(eru);
#endif
}
#endif /* if( UC_FAMILY == XMC1 ) */

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/**
* @file xmc4_flash.c
* @date 2016-01-08
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-10:
* - Initial <br>
*
* 2015-06-20:
* - Removed definition of GetDriverVersion API
*
* 2015-08-17:
* - Added the below API's to the public interface.
* 1. XMC_FLASH_Reset
* 2. XMC_FLASH_ErasePhysicalSector
* 3. XMC_FLASH_EraseUCB
* 4. XMC_FLASH_ResumeProtection
* 5. XMC_FLASH_RepairPhysicalSector
*
* 2016-01-08:
* - Wait until operation is finished for the next functions:
* 1. XMC_FLASH_InstallProtection
* 2. XMC_FLASH_ConfirmProtection
* 3. XMC_FLASH_ProgramPage
* 4. XMC_FLASH_EraseSector
* 5. XMC_FLASH_ErasePhysicalSector
* 6. XMC_FLASH_EraseUCB
* - Fix XMC_FLASH_VerifyReadProtection and XMC_FLASH_VerifyWriteProtection
*
* @endcond
*
*/
#include "xmc_flash.h"
#if UC_FAMILY == XMC4
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_FLASH_PROTECTION_CONFIGURATION_WORDS (8UL) /* Used to upadte the assembly buffer during protection
configuration */
#define XMC_FLASH_PROT_CONFIRM_OFFSET (512UL) /* Offset address for UCB page */
#define XMC_FLASH_PROT_CONFIRM_WORDS (4UL)
#define XMC_FLASH_PROT_CONFIRM_CODE (0x8AFE15C3UL)
/*********************************************************************************************************************
* LOCAL FUNCTIONS
********************************************************************************************************************/
void XMC_FLASH_lEnterPageModeCommand(void);
void XMC_FLASH_lLoadPageCommand(uint32_t low_word, uint32_t high_word);
void XMC_FLASH_lWritePageCommand(uint32_t *page_start_address);
void XMC_FLASH_lWriteUCBPageCommand(uint32_t *page_start_address);
void XMC_FLASH_lEraseSectorCommand(uint32_t *sector_start_address);
void XMC_FLASH_lDisableSectorWriteProtectionCommand(uint32_t user, uint32_t password_0, uint32_t password_1);
void XMC_FLASH_lDisableReadProtectionCommand(uint32_t password_0, uint32_t password_1);
void XMC_FLASH_lRepairPhysicalSectorCommand(void);
void XMC_FLASH_lErasePhysicalSectorCommand(uint32_t *sector_start_address);
void XMC_FLASH_lClearStatusCommand(void);
/*
* Command to program the PFLASH in to page mode, so that assembly buffer is used
*/
void XMC_FLASH_lEnterPageModeCommand(void)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = (uint32_t)0x50U;
}
/*
* Command to load the data into the page assembly buffer
*/
void XMC_FLASH_lLoadPageCommand(uint32_t low_word, uint32_t high_word)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x55f0U);
*address = low_word;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x55f4U);
*address = high_word;
}
/*
* Command to start the programming of one page with data from the assembly buffer
*/
void XMC_FLASH_lWritePageCommand(uint32_t *page_start_address)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xaaU;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = 0x55U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xa0U;
address = page_start_address;
*address = 0xaaU;
}
/*
* Command to start the programming of UCB page with data from the assembly buffer
*/
void XMC_FLASH_lWriteUCBPageCommand(uint32_t *page_start_address)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xaaU;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = 0x55U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xc0U;
address = page_start_address;
*address = 0xaaU;
}
/*
* Command to erase sector which is starting with the specified address
*/
void XMC_FLASH_lEraseSectorCommand(uint32_t *sector_start_address)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xaaU;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = 0x55U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0x80U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xaaU;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = 0x55U;
address = sector_start_address;
*address = 0x30U;
}
/*
* Command to temporarily disables the write protection belonging to the the USER specified, when passwords match with their
* configured values
*/
void XMC_FLASH_lDisableSectorWriteProtectionCommand(uint32_t user, uint32_t password_0, uint32_t password_1)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xaaU;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = 0x55U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x553cU);
*address = user;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = password_0;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = password_1;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5558U);
*address = 0x05U;
}
/*
* Command to temporarily disables the read protection along with write protection, when passwords match with their
* configured values
*/
void XMC_FLASH_lDisableReadProtectionCommand(uint32_t password_0, uint32_t password_1)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xaaU;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = 0x55U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x553cU);
*address = 0x00U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = password_0;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = password_1;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5558U);
*address = 0x08U;
}
/*
* Command to clear FSR.PROG and FSR.ERASE and the error flags in FSR such as PFOPER, SQER, PROER, PFDBER, ORIER, VER
*/
void XMC_FLASH_lClearStatusCommand(void)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xf5U;
}
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/*
* This API shall clear Program, erase and error flags(PFOPER, SQER, PROER, PFDBER, ORIER, VER) of FSR register.
*/
void XMC_FLASH_ClearStatus(void)
{
XMC_FLASH_lClearStatusCommand();
}
/*
* This API returns the FSR register value
*/
uint32_t XMC_FLASH_GetStatus(void)
{
return FLASH0->FSR;
}
/*
* This API enables the events which required to trigger the ISR
*/
void XMC_FLASH_EnableEvent(const uint32_t event_msk)
{
FLASH0->FCON |= event_msk;
}
/*
* This API disables the event generation
*/
void XMC_FLASH_DisableEvent(const uint32_t event_msk)
{
FLASH0->FCON &= ~event_msk;
}
/*
* This API write the PFLASH page
*/
void XMC_FLASH_ProgramPage(uint32_t *address, const uint32_t *data)
{
uint32_t idx;
XMC_FLASH_lClearStatusCommand();
XMC_FLASH_lEnterPageModeCommand();
for (idx = 0U; idx < XMC_FLASH_WORDS_PER_PAGE; idx += 2U)
{
XMC_FLASH_lLoadPageCommand(data[idx], data[idx + 1U]);
}
XMC_FLASH_lWritePageCommand(address);
/* wait until the operation is completed */
while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){}
}
/*
* This API erase the logical sector
*/
void XMC_FLASH_EraseSector(uint32_t *address)
{
XMC_FLASH_lClearStatusCommand();
XMC_FLASH_lEraseSectorCommand(address);
/* wait until the operation is completed */
while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){}
}
/*
* Command to erase physical sector which is starting with the specified address
*/
void XMC_FLASH_lErasePhysicalSectorCommand(uint32_t *sector_start_address)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xaaU;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = 0x55U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0x80U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xaaU;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = 0x55U;
address = sector_start_address;
*address = 0x40U;
}
/*
* Command to erase physical sector-4 which is starting with the specified address
* This command is only available if PROCON1.PRS = 1.
*/
void XMC_FLASH_lRepairPhysicalSectorCommand(void)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xaaU;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = 0x55U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0x80U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xaaU;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = 0x55U;
address = XMC_FLASH_PHY_SECTOR_4;
*address = 0x40U;
}
/*
* This API erase the physical sector
*/
void XMC_FLASH_ErasePhysicalSector(uint32_t *address)
{
XMC_FLASH_lClearStatusCommand();
XMC_FLASH_lErasePhysicalSectorCommand(address);
/* wait until the operation is completed */
while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){}
}
/*
* This API repair the physical sector
*/
void XMC_FLASH_RepairPhysicalSector(void)
{
XMC_FLASH_lClearStatusCommand();
XMC_FLASH_lRepairPhysicalSectorCommand();
}
/*
* Command to erase UCB sector which is starting with the specified address
*/
void XMC_FLASH_EraseUCB(uint32_t *ucb_sector_start_address)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xaaU;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = 0x55U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0x80U;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xaaU;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0xaaa8U);
*address = 0x55U;
address = ucb_sector_start_address;
*address = 0xc0U;
/* wait until the operation is completed */
while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){}
}
/*
* Command to reset the status of the PFLASH
*/
void XMC_FLASH_Reset(void)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0xf0U;
}
/*
* This API install the global read and sector write protection for the specified user
*/
void XMC_FLASH_InstallProtection(uint8_t user,
uint32_t protection_mask,
uint32_t password_0,
uint32_t password_1)
{
uint32_t idx;
XMC_ASSERT(" XMC_FLASH_ConfigureProtection: User level out of range", (user < 3U))
XMC_FLASH_lEnterPageModeCommand();
XMC_FLASH_lLoadPageCommand(protection_mask, 0UL);
XMC_FLASH_lLoadPageCommand(protection_mask, 0UL);
XMC_FLASH_lLoadPageCommand(password_0, password_1);
XMC_FLASH_lLoadPageCommand(password_0, password_1);
for (idx = 0U; idx < (XMC_FLASH_WORDS_PER_PAGE - XMC_FLASH_PROTECTION_CONFIGURATION_WORDS); idx += 2U)
{
XMC_FLASH_lLoadPageCommand(0UL, 0UL);
}
XMC_FLASH_lWriteUCBPageCommand((uint32_t *)((uint32_t)XMC_FLASH_UCB0 + (user * XMC_FLASH_BYTES_PER_UCB)));
/* wait until the operation is completed */
while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){}
}
/*
* This API confirm the protection. So that This sectors are locked with the specified protection.
*/
void XMC_FLASH_ConfirmProtection(uint8_t user)
{
uint32_t idx;
XMC_ASSERT(" XMC_FLASH_ConfirmProtection: User level out of range", (user < 3U))
XMC_FLASH_lEnterPageModeCommand();
XMC_FLASH_lLoadPageCommand(XMC_FLASH_PROT_CONFIRM_CODE, 0U);
XMC_FLASH_lLoadPageCommand(XMC_FLASH_PROT_CONFIRM_CODE, 0U);
/* Fill the rest of page buffer with zeros*/
for (idx = 0UL; idx < (XMC_FLASH_WORDS_PER_PAGE - XMC_FLASH_PROT_CONFIRM_WORDS); idx += 2U)
{
XMC_FLASH_lLoadPageCommand(0UL, 0UL);
}
XMC_FLASH_lWriteUCBPageCommand((uint32_t *)((uint32_t)XMC_FLASH_UCB0 +
(user * XMC_FLASH_BYTES_PER_UCB) + XMC_FLASH_PROT_CONFIRM_OFFSET));
/* wait until the operation is completed */
while ((FLASH0->FSR & (uint32_t)FLASH_FSR_PBUSY_Msk) != 0U){}
}
/*
* This API verify read protection configuration. And returns true if passwords are matching.
*/
bool XMC_FLASH_VerifyReadProtection(uint32_t password_0, uint32_t password_1)
{
bool status = false;
/* Check if read protection is installed */
if ((XMC_FLASH_GetStatus() & (uint32_t)XMC_FLASH_STATUS_READ_PROTECTION_INSTALLED) != 0U)
{
XMC_FLASH_lClearStatusCommand();
XMC_FLASH_lDisableReadProtectionCommand(password_0, password_1);
status = (bool)(XMC_FLASH_GetStatus() & (uint32_t)XMC_FLASH_STATUS_READ_PROTECTION_DISABLED_STATE);
}
return status;
}
/*
* This API verify sector write protection configuration. And returns true if passwords are matching for the
* specified user.
*/
bool XMC_FLASH_VerifyWriteProtection(uint32_t user,
uint32_t protection_mask,
uint32_t password_0,
uint32_t password_1)
{
bool status = false;
uint32_t *flash_procon_ptr = (uint32_t *)(void*)(&(FLASH0->PROCON0) + user);
XMC_ASSERT(" XMC_FLASH_VerifyWriteProtection: User level out of range", (user < 2U))
/* Check if write protection for selected user is installed */
if ((XMC_FLASH_GetStatus() & (uint32_t)((uint32_t)1U << (uint32_t)((uint32_t)FLASH_FSR_WPROIN0_Pos + user))) != 0U)
{
XMC_FLASH_lClearStatusCommand();
XMC_FLASH_lDisableSectorWriteProtectionCommand(user, password_0, password_1);
status = (bool)((XMC_FLASH_GetStatus() & (uint32_t)((uint32_t)1U << (uint32_t)((uint32_t)FLASH_FSR_WPRODIS0_Pos + user)))) &&
(*flash_procon_ptr == (protection_mask & (uint32_t)(~(uint32_t)XMC_FLASH_PROTECTION_READ_GLOBAL)));
}
return status;
}
/*
* Command to enables the protection as it was configured
*/
void XMC_FLASH_ResumeProtection(void)
{
volatile uint32_t *address;
address = (uint32_t *)(XMC_FLASH_UNCACHED_BASE + 0x5554U);
*address = 0x5eU;
}
#endif

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/**
* @file xmc4_gpio.c
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* @endcond
*
*/
#include "xmc_gpio.h"
#if UC_FAMILY == XMC4
/*******************************************************************************
* MACROS
*******************************************************************************/
#define PORT_PDR_Msk PORT0_PDR0_PD0_Msk
#define PORT_PDR_Size (4U)
#define PORT_HWSEL_Msk PORT0_HWSEL_HW0_Msk
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
void XMC_GPIO_Init(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_CONFIG_t *const config)
{
XMC_ASSERT("XMC_GPIO_Init: Invalid port", XMC_GPIO_CHECK_PORT(port));
XMC_ASSERT("XMC_GPIO_Init: Invalid mode", XMC_GPIO_IsModeValid(config->mode));
/* Switch to input */
port->IOCR[pin >> 2U] &= (uint32_t)~(PORT_IOCR_PC_Msk << (PORT_IOCR_PC_Size * (pin & 0x3U)));
/* HW port control is disabled */
port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U));
/* Enable digital input */
if (XMC_GPIO_CHECK_ANALOG_PORT(port))
{
port->PDISC &= ~(uint32_t)((uint32_t)0x1U << pin);
}
else
{
/* Set output level */
port->OMR = (uint32_t)config->output_level << pin;
/* Set output driver strength */
port->PDR[pin >> 3U] &= (uint32_t)~(PORT_PDR_Msk << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U)));
port->PDR[pin >> 3U] |= (uint32_t)config->output_strength << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U));
}
/* Set mode */
port->IOCR[pin >> 2U] |= (uint32_t)config->mode << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U));
}
void XMC_GPIO_SetOutputStrength(XMC_GPIO_PORT_t *const port, const uint8_t pin, XMC_GPIO_OUTPUT_STRENGTH_t strength)
{
XMC_ASSERT("XMC_GPIO_Init: Invalid port", XMC_GPIO_CHECK_OUTPUT_PORT(port));
XMC_ASSERT("XMC_GPIO_Init: Invalid output strength", XMC_GPIO_CHECK_OUTPUT_STRENGTH(strength));
port->PDR[pin >> 3U] &= (uint32_t)~((uint32_t)PORT_PDR_Msk << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U)));
port->PDR[pin >> 3U] |= (uint32_t)strength << ((uint32_t)PORT_PDR_Size * ((uint32_t)pin & 0x7U));
}
#endif /* UC_FAMILY == XMC4 */

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/**
* @file xmc4_rtc.c
* @date 2016-03-09
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2016-03-09:
* - Optimize write only registers
*
* @endcond
*
*/
/**
* @brief RTC driver for XMC microcontroller family.
*
*/
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include <xmc_rtc.h>
#if UC_FAMILY == XMC4
#include <xmc_scu.h>
/*********************************************************************************************************************
* API IMPLEMENTATION
*********************************************************************************************************************/
/*
* Enables RTC peripheral for programming its registers
*/
void XMC_RTC_Enable(void)
{
XMC_SCU_HIB_EnableHibernateDomain();
}
/*
* Disables RTC peripheral for programming its registers
*/
void XMC_RTC_Disable(void)
{
/*
* Empty because disabling the hibernate
* domain is not done intentionally.
*/
}
/*
* Checks RTC peripheral is enabled for programming to its registers
*/
bool XMC_RTC_IsEnabled(void)
{
return XMC_SCU_HIB_IsHibernateDomainEnabled();
}
/*
* Initialize the RTC peripheral
*/
XMC_RTC_STATUS_t XMC_RTC_Init(const XMC_RTC_CONFIG_t *const config)
{
if (XMC_RTC_IsRunning() == false)
{
if (XMC_SCU_HIB_IsHibernateDomainEnabled() == false)
{
XMC_SCU_HIB_EnableHibernateDomain();
}
XMC_RTC_SetPrescaler(config->prescaler);
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->TIM0 = config->time.raw0;
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->TIM1 = config->time.raw1;
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->ATIM0 = config->alarm.raw0;
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->ATIM1 = config->alarm.raw1;
}
return XMC_RTC_STATUS_OK;
}
/*
* Enable RTC periodic and alarm event(s)
*/
void XMC_RTC_EnableEvent(const uint32_t event)
{
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->MSKSR |= event;
}
/*
* Disable RTC periodic and alarm event(s)
*/
void XMC_RTC_DisableEvent(const uint32_t event)
{
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->MSKSR &= ~event;
}
/*
* Clear RTC periodic and alarm event(s)
*/
void XMC_RTC_ClearEvent(const uint32_t event)
{
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->CLRSR = event;
}
#endif /* UC_FAMILY == XMC4 */

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/**
* @file xmc_can.c
* @date 2016-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft <br>
*
* 2015-05-20:
* - New API added: XMC_CAN_MO_ReceiveData() <br>
* - XMC_CAN_MO_Config() signature has changed <br>
* - Minor fix in XMC_CAN_TXFIFO_ConfigMOSlaveObject(). <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* 2015-09-01:
* - Removed fCANB clock support <br>
*
* 2015-09-08:
* - Fixed bug in XMC_CAN_Init() <br>
*
* 2016-06-07:
* - Changed XMC_CAN_AllocateMOtoNodeList to wait for ready status of list controller
*
* 2015-06-20:
* - Fixed bug in XMC_CAN_MO_Config() <br>
* @endcond
*
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include "xmc_can.h"
#if defined(CAN)
#include "xmc_scu.h"
__STATIC_INLINE uint32_t max(uint32_t a, uint32_t b)
{
return (a > b) ? a : b;
}
__STATIC_INLINE uint32_t min(uint32_t a, uint32_t b)
{
return (a < b) ? a : b;
}
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
/* Baudrate Configuration */
void XMC_CAN_NODE_NominalBitTimeConfigure (XMC_CAN_NODE_t *const can_node,
const XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t *const can_bit_time)
{
uint32_t temp_brp = 12U ;
uint32_t temp_tseg1 = 12U;
uint32_t best_brp = 0U;
uint32_t best_tseg1 = 1U;
uint32_t best_tseg2 = 0U;
uint32_t best_tbaud = 0U;
uint32_t best_error = 10000U;
XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: rate not supported", (can_bit_time->baudrate < 1000000U) ||
(can_bit_time->baudrate >= 100000U));
XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: fCAN not supported",
can_bit_time->can_frequency <= 120000000U);
XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: fCAN not supported",
can_bit_time->can_frequency > 5000000U);
XMC_ASSERT("XMC_CAN_NODE_NOMINAL_BIT_TIME_Configure: sample point not supported",
(can_bit_time->sample_point < 10000U) && ((can_bit_time->sample_point > 0U)));
/*
* Bit timing & sampling
* Tq = (BRP+1)/Fcan if DIV8 = 0
* Tq = 8*(BRP+1)/Fcan if DIV8 = 1
* TSync = 1.Tq
* TSeg1 = (TSEG1+1)*Tq >= 3Tq
* TSeg2 = (TSEG2+1)*Tq >= 2Tq
* Bit Time = TSync + TSeg1 + TSeg2 >= 8Tq
*
* Resynchronization:
*
* Tsjw = (SJW + 1)*Tq
* TSeg1 >= Tsjw + Tprop
* TSeg2 >= Tsjw
*/
/* search for best baudrate */
for (temp_brp = 1U; temp_brp <= 64U; temp_brp++)
{
uint32_t f_quanta = (uint32_t)((can_bit_time->can_frequency * 10U) / temp_brp);
uint32_t temp_tbaud = (uint32_t)(f_quanta / (can_bit_time->baudrate));
uint32_t temp_baudrate;
uint32_t error;
if((temp_tbaud % 10U) > 5U)
{
temp_tbaud = (uint32_t)(temp_tbaud / 10U);
temp_tbaud++;
}
else
{
temp_tbaud = (uint32_t)(temp_tbaud / 10U);
}
if(temp_tbaud > 0U)
{
temp_baudrate = (uint32_t) (f_quanta / (temp_tbaud * 10U));
}
else
{
temp_baudrate = f_quanta / 10U;
temp_tbaud = 1;
}
if(temp_baudrate >= can_bit_time->baudrate)
{
error = temp_baudrate - can_bit_time->baudrate;
}
else
{
error = can_bit_time->baudrate - temp_baudrate;
}
if ((temp_tbaud <= 20U) && (best_error > error))
{
best_brp = temp_brp;
best_tbaud = temp_tbaud;
best_error = (error);
if (error < 1000U)
{
break;
}
}
}
/* search for best sample point */
best_error = 10000U;
for (temp_tseg1 = 64U; temp_tseg1 >= 3U; temp_tseg1--)
{
uint32_t tempSamplePoint = ((temp_tseg1 + 1U) * 10000U) / best_tbaud;
uint32_t error;
if (tempSamplePoint >= can_bit_time->sample_point)
{
error = tempSamplePoint - can_bit_time->sample_point;
}
else
{
error = can_bit_time->sample_point - tempSamplePoint;
}
if (best_error > error)
{
best_tseg1 = temp_tseg1;
best_error = error;
}
if (tempSamplePoint < (can_bit_time->sample_point))
{
break;
}
}
best_tseg2 = best_tbaud - best_tseg1 - 1U;
XMC_CAN_NODE_EnableConfigurationChange(can_node);
/* Configure bit timing register */
can_node->NBTR = (((uint32_t)(best_tseg2 - 1u) << CAN_NODE_NBTR_TSEG2_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG2_Msk) |
((((uint32_t)((uint32_t)(can_bit_time->sjw)-1U) << CAN_NODE_NBTR_SJW_Pos)) & (uint32_t)CAN_NODE_NBTR_SJW_Msk)|
(((uint32_t)(best_tseg1-1U) << CAN_NODE_NBTR_TSEG1_Pos) & (uint32_t)CAN_NODE_NBTR_TSEG1_Msk)|
(((uint32_t)(best_brp - 1U) << CAN_NODE_NBTR_BRP_Pos) & (uint32_t)CAN_NODE_NBTR_BRP_Msk)|
(((uint32_t)0U << CAN_NODE_NBTR_DIV8_Pos) & (uint32_t)CAN_NODE_NBTR_DIV8_Msk);
XMC_CAN_NODE_DisableConfigurationChange(can_node);
}
/* Function to allocate message object from free list to node list */
void XMC_CAN_AllocateMOtoNodeList(XMC_CAN_t *const obj, const uint8_t node_num, const uint8_t mo_num)
{
/* wait while panel operation is in progress. */
while (XMC_CAN_IsPanelControlReady(obj) == false)
{
/*Do nothing*/
};
/* Panel Command for allocation of MO to node list */
XMC_CAN_PanelControl(obj, XMC_CAN_PANCMD_STATIC_ALLOCATE,mo_num,(node_num + 1U));
}
/* Disable XMC_CAN Peripheral */
void XMC_CAN_Disable(XMC_CAN_t *const obj)
{
/* Disable CAN Module */
obj->CLC = CAN_CLC_DISR_Msk;
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_MCAN);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_MCAN);
#endif
}
/* Enable XMC_CAN Peripheral */
void XMC_CAN_Enable(XMC_CAN_t *const obj)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_MCAN);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_MCAN);
#endif
/* Enable CAN Module */
obj->CLC &= ~(uint32_t)CAN_CLC_DISR_Msk;
while (obj->CLC & CAN_CLC_DISS_Msk)
{
/*Do nothing*/
};
}
#if defined(MULTICAN_PLUS)
uint32_t XMC_CAN_GetBaudrateClockFrequency(XMC_CAN_t *const obj)
{
uint32_t frequency;
switch(XMC_CAN_GetBaudrateClockSource(obj))
{
#if UC_FAMILY == XMC4
case XMC_CAN_CANCLKSRC_FPERI:
frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency();
break;
#else
case XMC_CAN_CANCLKSRC_MCLK:
frequency = XMC_SCU_CLOCK_GetPeripheralClockFrequency();
break;
#endif
case XMC_CAN_CANCLKSRC_FOHP:
frequency = OSCHP_GetFrequency();
break;
default:
frequency = 0;
break;
}
return frequency;
}
void XMC_CAN_Init(XMC_CAN_t *const obj, XMC_CAN_CANCLKSRC_t clksrc, uint32_t can_frequency)
{
uint32_t step_n, step_f;
bool normal_divider;
uint32_t freq_n, freq_f;
uint32_t step;
uint32_t can_frequency_khz;
uint32_t peripheral_frequency_khz;
XMC_CAN_DM_t can_divider_mode;
uint32_t peripheral_frequency;
/*Enabling the module*/
XMC_CAN_Enable(obj);
XMC_CAN_SetBaudrateClockSource(obj, clksrc);
peripheral_frequency = XMC_CAN_GetBaudrateClockFrequency(obj);
XMC_ASSERT("XMC_CAN_Init: frequency not supported", can_frequency <= peripheral_frequency);
/* Normal divider mode */
step_n = (uint32_t)min(max(0U, (1024U - (peripheral_frequency / can_frequency))), 1023U);
freq_n = (uint32_t) (peripheral_frequency / (1024U - step_n));
/* Fractional divider mode */
can_frequency_khz = (uint32_t) (can_frequency >> 6);
peripheral_frequency_khz = (uint32_t)(peripheral_frequency >> 6);
step_f = (uint32_t)(min( (((1024U * can_frequency_khz) / peripheral_frequency_khz) ), 1023U ));
freq_f = (uint32_t)((peripheral_frequency_khz * step_f) / 1024U);
freq_f = freq_f << 6;
normal_divider = (uint32_t)(can_frequency - freq_n) <= (can_frequency - freq_f);
step = (normal_divider != 0U) ? step_n : step_f;
can_divider_mode = (normal_divider != 0U) ? XMC_CAN_DM_NORMAL : XMC_CAN_DM_FRACTIONAL;
obj->FDR &= (uint32_t) ~(CAN_FDR_DM_Msk | CAN_FDR_STEP_Msk);
obj->FDR |= ((uint32_t)can_divider_mode << CAN_FDR_DM_Pos) | ((uint32_t)step << CAN_FDR_STEP_Pos);
}
void XMC_CAN_SetBaudrateClockSource(XMC_CAN_t *const obj,const XMC_CAN_CANCLKSRC_t source)
{
obj->MCR = (obj->MCR & ~CAN_MCR_CLKSEL_Msk) | source ;
}
XMC_CAN_CANCLKSRC_t XMC_CAN_GetBaudrateClockSource(XMC_CAN_t *const obj)
{
return ((XMC_CAN_CANCLKSRC_t)((obj->MCR & CAN_MCR_CLKSEL_Msk) >> CAN_MCR_CLKSEL_Pos));
}
#else
/* Initialization of XMC_CAN GLOBAL Object */
void XMC_CAN_Init(XMC_CAN_t *const obj, uint32_t can_frequency)
{
uint32_t step_n, step_f;
bool normal_divider;
uint32_t freq_n, freq_f;
uint32_t step;
uint32_t can_frequency_khz;
uint32_t peripheral_frequency_khz;
XMC_CAN_DM_t can_divider_mode;
uint32_t peripheral_frequency = (XMC_SCU_CLOCK_GetPeripheralClockFrequency());
XMC_ASSERT("XMC_CAN_Init: frequency not supported", can_frequency <= peripheral_frequency);
/*Enabling the module*/
XMC_CAN_Enable(obj);
/* Normal divider mode */
step_n = (uint32_t)min(max(0U, (1024U - (peripheral_frequency / can_frequency))), 1023U);
freq_n = (uint32_t) (peripheral_frequency / (1024U - step_n));
/* Fractional divider mode */
can_frequency_khz = (uint32_t) (can_frequency >> 6);
peripheral_frequency_khz = (uint32_t)(peripheral_frequency >> 6);
step_f = (uint32_t)(min( (((1024U * can_frequency_khz) / peripheral_frequency_khz) ), 1023U ));
freq_f = (uint32_t)((peripheral_frequency_khz * step_f) / 1024U);
freq_f = freq_f << 6;
normal_divider = (uint32_t)(can_frequency - freq_n) <= (can_frequency - freq_f);
step = (normal_divider != 0U) ? step_n : step_f;
can_divider_mode = (normal_divider != 0U) ? XMC_CAN_DM_NORMAL : XMC_CAN_DM_FRACTIONAL;
obj->FDR &= (uint32_t) ~(CAN_FDR_DM_Msk | CAN_FDR_STEP_Msk);
obj->FDR |= ((uint32_t)can_divider_mode << CAN_FDR_DM_Pos) | ((uint32_t)step << CAN_FDR_STEP_Pos);
}
#endif
/* Sets the Identifier of the MO */
void XMC_CAN_MO_SetIdentifier(XMC_CAN_MO_t *const can_mo, const uint32_t can_identifier)
{
if ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk)
{
can_mo->can_mo_ptr->MOAR = ((can_mo->can_mo_ptr->MOAR) & ~(uint32_t)(CAN_MO_MOAR_ID_Msk)) |
((can_identifier << XMC_CAN_MO_MOAR_STDID_Pos) & (uint32_t)CAN_MO_MOAR_ID_Msk);
}
else
{
can_mo->can_mo_ptr->MOAR = ((can_mo->can_mo_ptr->MOAR) & ~(uint32_t)(CAN_MO_MOAR_ID_Msk)) |
(can_identifier & (uint32_t)CAN_MO_MOAR_ID_Msk);
}
can_mo->can_identifier = can_identifier;
}
/* Gets the Identifier of the MO */
uint32_t XMC_CAN_MO_GetIdentifier(const XMC_CAN_MO_t *const can_mo)
{
uint32_t identifier;
if ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk)
{
identifier = ((can_mo->can_mo_ptr->MOAR) & (uint32_t)(CAN_MO_MOAR_ID_Msk)) >> XMC_CAN_MO_MOAR_STDID_Pos;
}
else
{
identifier = ((can_mo->can_mo_ptr->MOAR) & (uint32_t)(CAN_MO_MOAR_ID_Msk));
}
return identifier;
}
/* Gets the acceptance mask for the CAN MO. */
uint32_t XMC_CAN_MO_GetAcceptanceMask(const XMC_CAN_MO_t *const can_mo)
{
uint32_t identifier_mask;
if (((can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) != (uint32_t)CAN_MO_MOAMR_MIDE_Msk)
&& ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk))
{
identifier_mask = ((can_mo->can_mo_ptr->MOAMR) & (uint32_t)(CAN_MO_MOAMR_AM_Msk)) >> XMC_CAN_MO_MOAR_STDID_Pos;
}
else
{
identifier_mask = ((can_mo->can_mo_ptr->MOAMR) & (uint32_t)(CAN_MO_MOAMR_AM_Msk));
}
return identifier_mask;
}
/* Gets the acceptance mask of the MO */
void XMC_CAN_MO_SetAcceptanceMask(XMC_CAN_MO_t *const can_mo,const uint32_t can_id_mask)
{
if (((can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) != (uint32_t)CAN_MO_MOAMR_MIDE_Msk)
&& ((can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_IDE_Msk) != (uint32_t)CAN_MO_MOAR_IDE_Msk))
{
can_mo->can_mo_ptr->MOAMR = ((can_mo->can_mo_ptr->MOAMR) & ~(uint32_t)(CAN_MO_MOAMR_AM_Msk)) |
(can_id_mask << XMC_CAN_MO_MOAR_STDID_Pos);
}
else
{
can_mo->can_mo_ptr->MOAMR = ((can_mo->can_mo_ptr->MOAMR) & ~(uint32_t)(CAN_MO_MOAMR_AM_Msk)) |
(can_id_mask & (uint32_t)CAN_MO_MOAMR_AM_Msk);
}
can_mo->can_id_mask = can_id_mask;
}
/* Initialization of XMC_CAN MO Object */
void XMC_CAN_MO_Config(const XMC_CAN_MO_t *const can_mo)
{
uint32_t reg;
/* Configure MPN */
uint32_t num = ((uint32_t)(can_mo->can_mo_ptr) - CAN_BASE - 0x1000U)/0x0020U;
uint32_t set = (((uint32_t)(num/32) << (CAN_MO_MOIPR_MPN_Pos + 5U)) | ((uint32_t)(num%32) << CAN_MO_MOIPR_MPN_Pos));
can_mo->can_mo_ptr->MOIPR &= ~(CAN_MO_MOIPR_MPN_Msk);
can_mo->can_mo_ptr->MOIPR |= set;
if (((can_mo->can_id_mode != (uint32_t) XMC_CAN_FRAME_TYPE_STANDARD_11BITS) &&
(can_mo->can_id_mode != (uint32_t) XMC_CAN_FRAME_TYPE_EXTENDED_29BITS)) ||
((can_mo->can_mo_type != XMC_CAN_MO_TYPE_RECMSGOBJ) &&
(can_mo->can_mo_type != XMC_CAN_MO_TYPE_TRANSMSGOBJ)))
{
; /*Do nothing*/
}
else
{
/* Disable Message object */
can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESMSGVAL_Msk;
if (can_mo->can_id_mode == (uint32_t)XMC_CAN_FRAME_TYPE_STANDARD_11BITS)
{
reg = can_mo->mo_ar;
reg &= (uint32_t) ~(CAN_MO_MOAR_ID_Msk);
reg |= (can_mo->can_identifier << XMC_CAN_MO_MOAR_STDID_Pos);
can_mo->can_mo_ptr->MOAR = reg;
reg = can_mo->mo_amr;
reg &= (uint32_t) ~(CAN_MO_MOAMR_AM_Msk);
reg |= (can_mo->can_id_mask << XMC_CAN_MO_MOAR_STDID_Pos);
can_mo->can_mo_ptr->MOAMR = reg;
}
else
{
can_mo->can_mo_ptr->MOAR = can_mo->mo_ar;
can_mo->can_mo_ptr->MOAMR = can_mo->mo_amr;
}
/* Check whether message object is transmit message object */
if (can_mo->can_mo_type == XMC_CAN_MO_TYPE_TRANSMSGOBJ)
{
/* Set MO as Transmit message object */
XMC_CAN_MO_UpdateData(can_mo);
can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_SETDIR_Msk;
}
else
{
/* Set MO as Receive message object and set RXEN bit */
can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESDIR_Msk;
}
/* Reset RTSEL and Set MSGVAL ,TXEN0 and TXEN1 bits */
can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk | CAN_MO_MOCTR_SETMSGVAL_Msk |
CAN_MO_MOCTR_SETRXEN_Msk | CAN_MO_MOCTR_RESRTSEL_Msk);
}
}
/* Update of XMC_CAN Object */
XMC_CAN_STATUS_t XMC_CAN_MO_UpdateData(const XMC_CAN_MO_t *const can_mo)
{
XMC_CAN_STATUS_t error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE;
/* Check whether message object is transmit message object */
if (can_mo->can_mo_type == XMC_CAN_MO_TYPE_TRANSMSGOBJ)
{
can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESMSGVAL_Msk;
/* Configure data length */
can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR) & ~(uint32_t)(CAN_MO_MOFCR_DLC_Msk)) |
(((uint32_t) can_mo->can_data_length << CAN_MO_MOFCR_DLC_Pos) & (uint32_t)CAN_MO_MOFCR_DLC_Msk);
/* Configure Data registers*/
can_mo->can_mo_ptr->MODATAL = can_mo->can_data[0];
can_mo->can_mo_ptr->MODATAH = can_mo->can_data[1];
/* Reset RTSEL and Set MSGVAL ,TXEN0 and TXEN1 bits */
can_mo->can_mo_ptr->MOCTR = (CAN_MO_MOCTR_SETNEWDAT_Msk| CAN_MO_MOCTR_SETMSGVAL_Msk |CAN_MO_MOCTR_RESRTSEL_Msk);
error = XMC_CAN_STATUS_SUCCESS;
}
else
{
error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE;
}
return error;
}
/* This function is will put a transmit request to transmit message object */
XMC_CAN_STATUS_t XMC_CAN_MO_Transmit(const XMC_CAN_MO_t *const can_mo)
{
XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR;
uint32_t mo_type = (uint32_t)(((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_MSGVAL_Msk) >> CAN_MO_MOSTAT_MSGVAL_Pos);
uint32_t mo_transmission_ongoing = (uint32_t) ((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_TXRQ_Msk) >> CAN_MO_MOSTAT_TXRQ_Pos;
/* check if message is disabled */
if (mo_type == 0U)
{
error = XMC_CAN_STATUS_MO_DISABLED;
}
/* check if transmission is ongoing on message object */
else if (mo_transmission_ongoing == 1U)
{
error = XMC_CAN_STATUS_BUSY;
}
else
{
/* set TXRQ bit */
can_mo->can_mo_ptr-> MOCTR = CAN_MO_MOCTR_SETTXRQ_Msk | CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk;
error = XMC_CAN_STATUS_SUCCESS;
}
return error;
}
/* This function is will read the message object data bytes */
XMC_CAN_STATUS_t XMC_CAN_MO_ReceiveData (XMC_CAN_MO_t *can_mo)
{
XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR;
uint8_t rx_pnd = 0U;
uint8_t new_data = 0U;
uint32_t mo_type = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_DIR_Msk) >> CAN_MO_MOSTAT_DIR_Pos;
uint32_t mo_recepcion_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos;
/* check if message object is a receive message object */
if (mo_type != (uint32_t)XMC_CAN_MO_TYPE_RECMSGOBJ)
{
error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE;
}
/* check if reception is ongoing on message object */
else if (mo_recepcion_ongoing == 1U)
{
error = XMC_CAN_STATUS_BUSY;
}
else
{
/* read message parameters */
do
{
can_mo->can_data[0] = can_mo->can_mo_ptr->MODATAL;
can_mo->can_data[1] = can_mo->can_mo_ptr->MODATAH;
rx_pnd = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos);
new_data = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_NEWDAT_Msk) >> CAN_MO_MOSTAT_NEWDAT_Pos);
} while ((rx_pnd != 0U) && (new_data != 0U));
error = XMC_CAN_STATUS_SUCCESS;
}
return error;
}
/* This function is will read the message object data bytes */
XMC_CAN_STATUS_t XMC_CAN_MO_Receive (XMC_CAN_MO_t *can_mo)
{
XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR;
uint8_t rx_pnd = 0U;
uint8_t new_data = 0U;
uint32_t mo_type = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_DIR_Msk) >> CAN_MO_MOSTAT_DIR_Pos;
uint32_t mo_recepcion_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos;
/* check if message object is a receive message object */
if (mo_type != (uint32_t)XMC_CAN_MO_TYPE_RECMSGOBJ)
{
error = XMC_CAN_STATUS_MO_NOT_ACCEPTABLE;
}
/* check if reception is ongoing on message object */
else if (mo_recepcion_ongoing == 1U)
{
error = XMC_CAN_STATUS_BUSY;
}
else
{
/* read message parameters */
do
{
can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_RESNEWDAT_Msk;
if ((((can_mo->can_mo_ptr->MOAR) & CAN_MO_MOAR_IDE_Msk) >> CAN_MO_MOAR_IDE_Pos) == 0U)
{
can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_STANDARD_11BITS;
can_mo->can_identifier = (can_mo->can_mo_ptr->MOAR & XMC_CAN_MO_MOAR_STDID_Msk) >> XMC_CAN_MO_MOAR_STDID_Pos;
can_mo->can_ide_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) >> CAN_MO_MOAMR_MIDE_Pos;
if(can_mo->can_ide_mask == 1U)
{
can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & XMC_CAN_MO_MOAR_STDID_Msk) >> XMC_CAN_MO_MOAR_STDID_Pos;
}
else
{
can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_AM_Msk);
}
}
else
{
can_mo->can_id_mode = (uint32_t)XMC_CAN_FRAME_TYPE_EXTENDED_29BITS;
can_mo->can_identifier = (can_mo->can_mo_ptr->MOAR & CAN_MO_MOAR_ID_Msk);
can_mo->can_id_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_AM_Msk);
can_mo->can_ide_mask = (uint32_t)(can_mo->can_mo_ptr->MOAMR & CAN_MO_MOAMR_MIDE_Msk) >> CAN_MO_MOAMR_MIDE_Pos;
}
can_mo->can_data_length = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOFCR) & CAN_MO_MOFCR_DLC_Msk) >> CAN_MO_MOFCR_DLC_Pos);
can_mo->can_data[0] = can_mo->can_mo_ptr->MODATAL;
can_mo->can_data[1] = can_mo->can_mo_ptr->MODATAH;
rx_pnd = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_RXUPD_Msk) >> CAN_MO_MOSTAT_RXUPD_Pos);
new_data = (uint8_t)((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_NEWDAT_Msk) >> CAN_MO_MOSTAT_NEWDAT_Pos);
} while ((rx_pnd != 0U) && (new_data != 0U));
can_mo->can_mo_type = XMC_CAN_MO_TYPE_RECMSGOBJ;
error = XMC_CAN_STATUS_SUCCESS;
}
return error;
}
/* Function to enable node event */
void XMC_CAN_NODE_EnableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event)
{
if(event != XMC_CAN_NODE_EVENT_CFCIE)
{
can_node->NCR |= (uint32_t)event;
}
else
{
can_node->NFCR |= (uint32_t)event;
}
}
/* Function to disable node event */
void XMC_CAN_NODE_DisableEvent(XMC_CAN_NODE_t *const can_node, const XMC_CAN_NODE_EVENT_t event)
{
if(event != XMC_CAN_NODE_EVENT_CFCIE)
{
can_node->NCR &= ~(uint32_t)event;
}
else
{
can_node->NFCR &= ~(uint32_t)event;
}
}
/* Function to transmit MO from the FIFO */
XMC_CAN_STATUS_t XMC_CAN_TXFIFO_Transmit(const XMC_CAN_MO_t *const can_mo)
{
XMC_CAN_STATUS_t error = XMC_CAN_STATUS_ERROR;
uint32_t mo_type = ((uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_MSGVAL_Msk) >> CAN_MO_MOSTAT_MSGVAL_Pos);
uint32_t mo_transmission_ongoing = (uint32_t)((can_mo->can_mo_ptr->MOSTAT) & CAN_MO_MOSTAT_TXRQ_Msk) >> CAN_MO_MOSTAT_TXRQ_Pos;
uint32_t mo_cur = (uint32_t)(can_mo->can_mo_ptr-> MOFGPR & CAN_MO_MOFGPR_CUR_Msk) >> CAN_MO_MOFGPR_CUR_Pos;
CAN_MO_TypeDef* mo = (CAN_MO_TypeDef *)(CAN_BASE + 0x1000UL + (mo_cur * 0x0020UL));
/* check if message is disabled */
if (mo_type == 0U)
{
error = XMC_CAN_STATUS_MO_DISABLED;
}
/* check if transmission is ongoing on message object */
else if (mo_transmission_ongoing == 1U)
{
error = XMC_CAN_STATUS_BUSY;
}
else
{
mo->MOCTR = CAN_MO_MOCTR_SETTXRQ_Msk | CAN_MO_MOCTR_SETTXEN0_Msk | CAN_MO_MOCTR_SETTXEN1_Msk;
error = XMC_CAN_STATUS_SUCCESS;
}
return error;
}
/* Function to initialize the transmit FIFO MO base object */
void XMC_CAN_TXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo)
{
can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) |
(((uint32_t)0x2U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk);
can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_BOT_Msk |
CAN_MO_MOFGPR_TOP_Msk |
CAN_MO_MOFGPR_CUR_Msk)) |
(((uint32_t)can_fifo.fifo_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) |
(((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t) CAN_MO_MOFGPR_CUR_Msk) |
(((uint32_t)can_fifo.fifo_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t) CAN_MO_MOFGPR_TOP_Msk);
}
/* Function to Initialize the receive FIFO MO base object */
void XMC_CAN_RXFIFO_ConfigMOBaseObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo)
{
can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) |
(((uint32_t)0x1U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk);
can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~( uint32_t)(CAN_MO_MOFGPR_BOT_Msk |
CAN_MO_MOFGPR_TOP_Msk |
CAN_MO_MOFGPR_CUR_Msk)) |
(((uint32_t)can_fifo.fifo_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) |
(((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk) |
(((uint32_t)can_fifo.fifo_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t)CAN_MO_MOFGPR_TOP_Msk);
}
/* Function to Initialize the FIFO MO slave object */
void XMC_CAN_TXFIFO_ConfigMOSlaveObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_FIFO_CONFIG_t can_fifo)
{
can_mo->can_mo_ptr->MOFCR = ((can_mo->can_mo_ptr->MOFCR ) & ~(uint32_t)(CAN_MO_MOFCR_MMC_Msk)) |
(((uint32_t)0x3U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk);
can_mo->can_mo_ptr->MOFGPR = ((can_mo->can_mo_ptr->MOFGPR ) & ~(uint32_t)(CAN_MO_MOFGPR_CUR_Msk)) |
(((uint32_t)can_fifo.fifo_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk);
can_mo->can_mo_ptr->MOCTR = CAN_MO_MOCTR_SETTXEN0_Msk|
CAN_MO_MOCTR_RESTXEN1_Msk;
}
/* Function to Initialize the Gateway Source Object */
void XMC_CAN_GATEWAY_InitSourceObject(const XMC_CAN_MO_t *const can_mo,const XMC_CAN_GATEWAY_CONFIG_t can_gateway)
{
can_mo->can_mo_ptr->MOFCR = (((uint32_t)0x4U << CAN_MO_MOFCR_MMC_Pos) & (uint32_t)CAN_MO_MOFCR_MMC_Msk) |
((((uint32_t)can_gateway.gateway_data_frame_send) << CAN_MO_MOFCR_GDFS_Pos) & (uint32_t)CAN_MO_MOFCR_GDFS_Msk) |
((((uint32_t)can_gateway.gateway_data_length_code_copy) << CAN_MO_MOFCR_DLCC_Pos) & (uint32_t)CAN_MO_MOFCR_DLCC_Msk) |
((((uint32_t)can_gateway.gateway_identifier_copy) << CAN_MO_MOFCR_IDC_Pos) & (uint32_t)CAN_MO_MOFCR_IDC_Msk) |
((((uint32_t)can_gateway.gateway_data_copy) << CAN_MO_MOFCR_DATC_Pos) & (uint32_t)CAN_MO_MOFCR_DATC_Msk) ;
can_mo->can_mo_ptr->MOFGPR = (uint32_t)((((uint32_t)can_gateway.gateway_bottom << CAN_MO_MOFGPR_BOT_Pos) & (uint32_t)CAN_MO_MOFGPR_BOT_Msk) |
(((uint32_t)can_gateway.gateway_base << CAN_MO_MOFGPR_CUR_Pos) & (uint32_t)CAN_MO_MOFGPR_CUR_Msk) |
(((uint32_t)can_gateway.gateway_top << CAN_MO_MOFGPR_TOP_Pos) & (uint32_t)CAN_MO_MOFGPR_TOP_Msk));
}
#endif /* XMC_CAN_H */

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/**
* @file xmc_common.c
* @date 2017-02-25
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2017-02-25:
* - Remove the need to define XMC_USER_ASSERT_FUNCTION
* - XMC_AssertHandler fixed compilation warnings
*
* @endcond
*
*/
#include "xmc_common.h"
/*******************************************************************************
* DATA STRUCTURES
*******************************************************************************/
struct list
{
struct list *next;
};
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
#if defined(XMC_ASSERT_ENABLE)
__WEAK void XMC_AssertHandler(const char *const msg, const char *const file, uint32_t line)
{
XMC_UNUSED_ARG(msg);
XMC_UNUSED_ARG(file);
XMC_UNUSED_ARG(line);
while(1)
{
/* Endless loop */
}
}
#endif
void XMC_LIST_Init(XMC_LIST_t *list)
{
*list = NULL;
}
void *XMC_LIST_GetHead(XMC_LIST_t *list)
{
return *list;
}
void *XMC_LIST_GetTail(XMC_LIST_t *list)
{
struct list *tail;
if (*list == NULL)
{
tail = NULL;
}
else
{
for (tail = (struct list *)*list; tail->next != NULL; tail = tail->next)
{
/* Loop through the list */
}
}
return tail;
}
void XMC_LIST_Add(XMC_LIST_t *list, void *item)
{
struct list *tail;
((struct list *)item)->next = NULL;
tail = (struct list *)XMC_LIST_GetTail(list);
if (tail == NULL)
{
*list = item;
}
else
{
tail->next = (struct list *)item;
}
}
void XMC_LIST_Remove(XMC_LIST_t *list, void *item)
{
struct list *right, *left;
if (*list != NULL)
{
left = NULL;
for(right = (struct list *)*list; right != NULL; right = right->next)
{
if(right == item)
{
if(left == NULL)
{
/* First on list */
*list = right->next;
}
else
{
/* Not first on list */
left->next = right->next;
}
right->next = NULL;
break;
}
left = right;
}
}
}
void XMC_LIST_Insert(XMC_LIST_t *list, void *prev_item, void *new_item)
{
if (prev_item == NULL)
{
((struct list *)new_item)->next = (struct list *)*list;
*list = new_item;
}
else
{
((struct list *)new_item)->next = ((struct list *)prev_item)->next;
((struct list *)prev_item)->next = (struct list *)new_item;
}
}
void XMC_PRIOARRAY_Init(XMC_PRIOARRAY_t *prioarray)
{
XMC_ASSERT("XMC_PRIOARRAY_Init: NULL pointer", prioarray != NULL);
/* Initialize head, next points to tail, previous to NULL and the priority is MININT */
prioarray->items[prioarray->size].next = prioarray->size + 1;
prioarray->items[prioarray->size].previous = -1;
prioarray->items[prioarray->size].priority = INT32_MAX;
/* Initialize tail, next points to NULL, previous is the head and the priority is MAXINT */
prioarray->items[prioarray->size + 1].next = -1;
prioarray->items[prioarray->size + 1].previous = prioarray->size;
prioarray->items[prioarray->size + 1].priority = INT32_MIN;
}
void XMC_PRIOARRAY_Add(XMC_PRIOARRAY_t *prioarray, int32_t item, int32_t priority)
{
int32_t next;
int32_t previous;
XMC_ASSERT("XMC_PRIOARRAY_Add: item out of range", (item >= 0) && (item < prioarray->size));
next = XMC_PRIOARRAY_GetHead(prioarray);
while (XMC_PRIOARRAY_GetItemPriority(prioarray, next) > priority)
{
next = XMC_PRIOARRAY_GetItemNext(prioarray, next);
}
previous = prioarray->items[next].previous;
prioarray->items[item].next = next;
prioarray->items[item].previous = previous;
prioarray->items[item].priority = priority;
prioarray->items[previous].next = item;
prioarray->items[next].previous = item;
}
void XMC_PRIOARRAY_Remove(XMC_PRIOARRAY_t *prioarray, int32_t item)
{
int32_t next;
int32_t previous;
XMC_ASSERT("XMC_PRIOARRAY_Add: item out of range", (item >= 0) && (item < prioarray->size));
next = prioarray->items[item].next;
previous = prioarray->items[item].previous;
prioarray->items[previous].next = next;
prioarray->items[next].previous = previous;
}

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/**
* @file xmc_dac.c
* @date 2015-06-19
*
* @cond
**********************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification,are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share
* modifications, enhancements or bug fixes with Infineon Technologies AG
* dave@infineon.com).
**********************************************************************************
*
* Change History
* --------------
*
* 2015-02-18:
* - Initial version
*
* 2015-06-19:
* - Removed GetDriverVersion API
* @endcond
*
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include <xmc_dac.h>
#include <xmc_scu.h>
/* DAC peripheral is not available on XMC1X devices. */
#if defined(DAC)
/*******************************************************************************
* MACROS
*******************************************************************************/
#define XMC_DAC_MIN_FREQ_DIVIDER (16U)
#define XMC_DAC_MAX_FREQ_DIVIDER (1048576U)
#define XMC_DAC_DAC0PATL_PAT_BITSIZE (5U)
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
/* API to enable the DAC module */
void XMC_DAC_Enable(XMC_DAC_t *const dac)
{
XMC_UNUSED_ARG(dac);
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DAC);
#endif
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_DAC);
}
/* API to disable the DAC module */
void XMC_DAC_Disable(XMC_DAC_t *const dac)
{
XMC_UNUSED_ARG(dac);
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_DAC);
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DAC);
#endif
}
/* API to check whether DAC is enabled */
bool XMC_DAC_IsEnabled(const XMC_DAC_t *const dac)
{
bool status;
XMC_UNUSED_ARG(dac);
status = XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DAC);
if(status == true)
{
status = false;
}
else
{
status = true;
}
return (status);
}
/* API to initialize DAC channel configuration */
void XMC_DAC_CH_Init(XMC_DAC_t *const dac, const uint8_t channel, const XMC_DAC_CH_CONFIG_t *const config)
{
XMC_DAC_Enable(dac);
dac->DACCFG[channel].low = config->cfg0;
dac->DACCFG[channel].high = config->cfg1;
if (channel < XMC_DAC_NO_CHANNELS)
{
XMC_DAC_CH_EnableOutput(dac, channel);
}
}
/* API to set the waveform frequency except in Ramp and Pattern generation mode. */
XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetFrequency(XMC_DAC_t *const dac,
const uint8_t channel,
const uint32_t frequency)
{
uint32_t divider;
XMC_DAC_CH_STATUS_t status;
XMC_ASSERT("XMC_DAC_CH_SetFrequency: frequency must be greater than zero", frequency > 0U);
divider = XMC_SCU_CLOCK_GetPeripheralClockFrequency() / frequency;
if (divider < XMC_DAC_MIN_FREQ_DIVIDER)
{
status = XMC_DAC_CH_STATUS_ERROR_FREQ2HIGH;
}
else if (divider >= XMC_DAC_MAX_FREQ_DIVIDER)
{
status = XMC_DAC_CH_STATUS_ERROR_FREQ2LOW;
}
else {
dac->DACCFG[channel].low = (dac->DACCFG[channel].low & (uint32_t)(~DAC_DAC0CFG0_FREQ_Msk)) |
(divider << DAC_DAC0CFG0_FREQ_Pos);
status = XMC_DAC_CH_STATUS_OK;
}
return status;
}
/* API to set the waveform frequency in Ramp Mode. */
XMC_DAC_CH_STATUS_t XMC_DAC_CH_SetRampFrequency(XMC_DAC_t *const dac,
const uint8_t channel,
const uint32_t frequency)
{
uint32_t stop;
uint32_t start;
start = dac->DACDATA[channel];
stop = (dac->DAC01DATA >> (channel * DAC_DAC01DATA_DATA1_Pos)) & (uint32_t)DAC_DAC01DATA_DATA0_Msk;
return XMC_DAC_CH_SetFrequency(dac, channel, frequency * ((stop - start) + 1U));
}
/* API to start the operation in Single Value Mode. */
XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartSingleValueMode(XMC_DAC_t *const dac, const uint8_t channel)
{
XMC_ASSERT("XMC_DAC_CH_StartSingleValueMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac));
XMC_ASSERT("XMC_DAC_CH_StartSingleValueMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel));
XMC_ASSERT("XMC_DAC_CH_StartSingleValueMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac));
XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_SINGLE);
return XMC_DAC_CH_STATUS_OK;
}
/* API to start the operation in Data Mode. */
XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartDataMode(XMC_DAC_t *const dac,
const uint8_t channel,
const XMC_DAC_CH_TRIGGER_t trigger,
const uint32_t frequency)
{
XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK;
XMC_ASSERT("XMC_DAC_CH_StartDataMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac));
XMC_ASSERT("XMC_DAC_CH_StartDataMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel));
XMC_ASSERT("XMC_DAC_CH_StartDataMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac));
XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_IDLE);
if (trigger == XMC_DAC_CH_TRIGGER_INTERNAL)
{
status = XMC_DAC_CH_SetFrequency(dac, channel, frequency);
}
if (status == XMC_DAC_CH_STATUS_OK)
{
XMC_DAC_CH_SetTrigger(dac, channel, trigger);
XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_DATA);
}
return status;
}
/* API to start the operation in Ramp Mode. */
XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartRampMode(XMC_DAC_t *const dac,
const uint8_t channel,
const uint16_t start,
const uint16_t stop,
const XMC_DAC_CH_TRIGGER_t trigger,
const uint32_t frequency)
{
XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK;
XMC_ASSERT("XMC_DAC_CH_StartRampMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac));
XMC_ASSERT("XMC_DAC_CH_StartRampMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel));
XMC_ASSERT("XMC_DAC_CH_StartRampMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac));
XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_IDLE);
XMC_DAC_CH_SetRampStart(dac, channel, start);
XMC_DAC_CH_SetRampStop(dac, channel, stop);
XMC_DAC_CH_SetTrigger(dac, channel, trigger);
if (trigger == XMC_DAC_CH_TRIGGER_INTERNAL)
{
status = XMC_DAC_CH_SetRampFrequency(dac, channel, frequency);
}
if (status == XMC_DAC_CH_STATUS_OK)
{
XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_RAMP);
}
return status;
}
/* API to start the operation in Pattern Mode. */
XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartPatternMode(XMC_DAC_t *const dac,
const uint8_t channel,
const uint8_t *const pattern,
const XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t sign_output,
const XMC_DAC_CH_TRIGGER_t trigger,
const uint32_t frequency)
{
XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK;
XMC_ASSERT("XMC_DAC_CH_StartPatternMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac));
XMC_ASSERT("XMC_DAC_CH_StartPatternMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel));
XMC_ASSERT("XMC_DAC_CH_StartPatternMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac));
XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_IDLE);
if (trigger == XMC_DAC_CH_TRIGGER_INTERNAL)
{
status = XMC_DAC_CH_SetFrequency(dac, channel, frequency * XMC_DAC_SAMPLES_PER_PERIOD);
}
if (status == XMC_DAC_CH_STATUS_OK)
{
XMC_DAC_CH_SetPattern(dac, channel, pattern);
if (XMC_DAC_CH_PATTERN_SIGN_OUTPUT_ENABLED == sign_output)
{
XMC_DAC_CH_EnablePatternSignOutput(dac, channel);
}
else
{
XMC_DAC_CH_DisablePatternSignOutput(dac, channel);
}
XMC_DAC_CH_SetTrigger(dac, channel, trigger);
XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_PATTERN);
}
return status;
}
/* API to start the operation in Noise Mode. */
XMC_DAC_CH_STATUS_t XMC_DAC_CH_StartNoiseMode(XMC_DAC_t *const dac,
const uint8_t channel,
const XMC_DAC_CH_TRIGGER_t trigger,
const uint32_t frequency)
{
XMC_DAC_CH_STATUS_t status = XMC_DAC_CH_STATUS_OK;
XMC_ASSERT("XMC_DAC_CH_StartNoiseMode: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac));
XMC_ASSERT("XMC_DAC_CH_StartNoiseMode: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel));
XMC_ASSERT("XMC_DAC_CH_StartNoiseMode: dac module not enabled\n", XMC_DAC_IsEnabled(dac));
XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_IDLE);
if (trigger == XMC_DAC_CH_TRIGGER_INTERNAL)
{
status = XMC_DAC_CH_SetFrequency(dac, channel, frequency);
}
if (status == XMC_DAC_CH_STATUS_OK)
{
XMC_DAC_CH_SetTrigger(dac, channel, trigger);
XMC_DAC_CH_SetMode(dac, channel, XMC_DAC_CH_MODE_NOISE);
}
return status;
}
/* API to write the pattern data table. */
void XMC_DAC_CH_SetPattern(XMC_DAC_t *const dac, uint8_t channel, const uint8_t *const data)
{
uint32_t index;
uint32_t temp;
XMC_ASSERT("XMC_DAC_CH_SetPattern: dac parameter not valid\n", XMC_DAC_IS_DAC_VALID(dac));
XMC_ASSERT("XMC_DAC_CH_SetPattern: channel parameter not valid\n", XMC_DAC_IS_CHANNEL_VALID(channel));
XMC_ASSERT("XMC_DAC_CH_SetPattern: dac module not enabled\n", XMC_DAC_IsEnabled(dac));
temp = data[0U];
for(index = 1U; index < 6U; ++index)
{
temp |= (uint32_t)data[index] << (index * XMC_DAC_DAC0PATL_PAT_BITSIZE);
}
dac->DACPAT[channel].low = temp;
temp = data[6U];
for(index = 1U; index < 6U; ++index)
{
temp |= (uint32_t)data[index + 6U] << (index * XMC_DAC_DAC0PATL_PAT_BITSIZE);
}
dac->DACPAT[channel].high = temp;
}
#endif /* defined(DAC) */

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/**
* @file xmc_dma.c
* @date 2016-04-08
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
* - Add the declarations for the following APIs: <br>
* XMC_DMA_DisableRequestLine, XMC_DMA_ClearRequestLine, <br>
* XMC_DMA_CH_ClearSourcePeripheralRequest, <br>
* XMC_DMA_CH_ClearDestinationPeripheralRequest <br>
* - Remove PRIOARRAY <br>
* - Documentation updates <br>
*
* 2015-06-20:
* - Removed GetDriverVersion API <br>
* - Updated XMC_DMA_CH_Init() to support scatter/gather functionality (only
* on advanced DMA channels) <br>
* - Updated XMC_DMA_CH_Disable() <br>
*
* 2016-03-09:
* - Optimize write only registers
*
* 2016-04-08:
* - Update XMC_DMA_CH_EnableEvent and XMC_DMA_CH_DisableEvent.
* Write optimization of MASKCHEV
* - Fix XMC_DMA_IRQHandler, clear channel event status before processing the event handler.
* It corrects event losses if the DMA triggered in the event handler finished before returning from handler.
*
* @endcond
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include "xmc_dma.h"
#if defined (GPDMA0)
#include "xmc_scu.h"
/*******************************************************************************
* MACROS
*******************************************************************************/
#define DLR_SRSEL_RS_MSK (0xfUL)
#define DLR_SRSEL_RS_BITSIZE (4UL)
#define DMA_EVENT_MAX (5UL)
#define GPDMA_CH_CFGH_DEST_PER_Pos GPDMA0_CH_CFGH_DEST_PER_Pos
#define GPDMA_CH_CFGH_SRC_PER_Pos GPDMA0_CH_CFGH_SRC_PER_Pos
#define GPDMA0_CH_CFGH_PER_Msk (0x7U)
#define GPDMA1_CH_CFGH_PER_Msk (0x3U)
#define GPDMA_CH_CFGH_PER_BITSIZE (4U)
#define GPDMA_CH_CTLL_INT_EN_Msk GPDMA0_CH_CTLL_INT_EN_Msk
/*******************************************************************************
* LOCAL DATA
*******************************************************************************/
#if defined (GPDMA0)
XMC_DMA_CH_EVENT_HANDLER_t dma0_event_handlers[XMC_DMA0_NUM_CHANNELS];
#endif
#if defined (GPDMA1)
XMC_DMA_CH_EVENT_HANDLER_t dma1_event_handlers[XMC_DMA1_NUM_CHANNELS];
#endif
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
/* Initialize GPDMA */
void XMC_DMA_Init(XMC_DMA_t *const dma)
{
XMC_DMA_Enable(dma);
}
/* Enable GPDMA module */
void XMC_DMA_Enable(XMC_DMA_t *const dma)
{
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA0);
#endif
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA0);
#if defined(GPDMA1)
}
else
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA1);
#endif
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA1);
}
#endif
dma->DMACFGREG = 0x1U;
}
/* Disable GPDMA module */
void XMC_DMA_Disable(XMC_DMA_t *const dma)
{
dma->DMACFGREG = 0x0U;
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA0);
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA0);
#endif
#if defined(GPDMA1)
}
else
{
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_GPDMA1);
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_GPDMA1);
#endif
}
#endif
}
/* Check is the GPDMA peripheral is enabled */
bool XMC_DMA_IsEnabled(const XMC_DMA_t *const dma)
{
bool status;
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
status = !XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_GPDMA0);
#if defined(CLOCK_GATING_SUPPORTED)
status = status && !XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_GPDMA0);
#endif
#if defined(GPDMA1)
}
else
{
status = !XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_GPDMA1);
#if defined(CLOCK_GATING_SUPPORTED)
status = status && !XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_GPDMA1);
#endif
}
#endif
/* DMA reset is not asserted and peripheral clock is not gated */
if (status == true)
{
status = status && (dma->DMACFGREG != 0U);
}
return status;
}
/* Enable request line */
void XMC_DMA_EnableRequestLine(XMC_DMA_t *const dma, uint8_t line, uint8_t peripheral)
{
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
DLR->SRSEL0 = ((DLR->SRSEL0 & (uint32_t)~(DLR_SRSEL_RS_MSK << (line * DLR_SRSEL_RS_BITSIZE))) |
((uint32_t)peripheral << (line * DLR_SRSEL_RS_BITSIZE)));
DLR->LNEN |= (0x1UL << (line & GPDMA0_CH_CFGH_PER_Msk));
#if defined(GPDMA1)
}
else
{
DLR->SRSEL1 = ((DLR->SRSEL1 & (uint32_t)~(DLR_SRSEL_RS_MSK << (line * DLR_SRSEL_RS_BITSIZE))) |
((uint32_t)peripheral << (line * DLR_SRSEL_RS_BITSIZE)));
DLR->LNEN |= (0x100UL << line);
}
#endif
}
void XMC_DMA_DisableRequestLine(XMC_DMA_t *const dma, uint8_t line)
{
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
DLR->LNEN &= ~(0x1UL << line);
#if defined(GPDMA1)
}
else
{
DLR->LNEN &= ~(0x100UL << line);
}
#endif
}
void XMC_DMA_ClearRequestLine(XMC_DMA_t *const dma, uint8_t line)
{
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
DLR->LNEN &= ~(0x1UL << line);
DLR->LNEN |= 0x1UL << line;
#if defined(GPDMA1)
}
else
{
DLR->LNEN &= ~(0x100UL << line);
DLR->LNEN |= 0x100UL << line;
}
#endif
}
/* Get DMA DLR overrun status */
bool XMC_DMA_GetOverrunStatus(XMC_DMA_t *const dma, uint8_t line)
{
bool status;
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
status = (bool)(DLR->OVRSTAT & (0x1UL << line));
#if defined(GPDMA1)
}
else
{
status = (bool)(DLR->OVRSTAT & (0x100UL << line));
}
#endif
return status;
}
/* Clear DMA DLR overrun status */
void XMC_DMA_ClearOverrunStatus(XMC_DMA_t *const dma, const uint8_t line)
{
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
DLR->OVRCLR = (uint32_t)(0x1UL << line);
#if defined(GPDMA1)
}
else
{
DLR->OVRCLR = (uint32_t)(0x100UL << line);
}
#endif
}
/* Disable DMA channel */
void XMC_DMA_CH_Disable(XMC_DMA_t *const dma, const uint8_t channel)
{
dma->CHENREG = (uint32_t)(0x100UL << channel);
while((dma->CHENREG & (uint32_t)(0x1UL << channel)) != 0U)
{
/* wait until channel is disabled */
}
}
/* Check if a DMA channel is enabled */
bool XMC_DMA_CH_IsEnabled(XMC_DMA_t *const dma, const uint8_t channel)
{
return (bool)(dma->CHENREG & ((uint32_t)1U << channel));
}
/* Initialize DMA channel */
XMC_DMA_CH_STATUS_t XMC_DMA_CH_Init(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_CONFIG_t *const config)
{
XMC_DMA_CH_STATUS_t status;
uint8_t line;
uint8_t peripheral;
if (XMC_DMA_IsEnabled(dma) == true)
{
if (XMC_DMA_CH_IsEnabled(dma, channel) == false)
{
dma->CH[channel].SAR = config->src_addr;
dma->CH[channel].DAR = config->dst_addr;
dma->CH[channel].LLP = (uint32_t)config->linked_list_pointer;
dma->CH[channel].CTLH = (uint32_t)config->block_size;
dma->CH[channel].CTLL = config->control;
dma->CH[channel].CFGL = (uint32_t)((uint32_t)config->priority |
(uint32_t)GPDMA0_CH_CFGL_HS_SEL_SRC_Msk |
(uint32_t)GPDMA0_CH_CFGL_HS_SEL_DST_Msk);
if ((dma == XMC_DMA0) && (channel < (uint8_t)2))
{
/* Configure scatter and gather */
dma->CH[channel].SGR = config->src_gather_control;
dma->CH[channel].DSR = config->dst_scatter_control;
}
if (config->dst_handshaking == XMC_DMA_CH_DST_HANDSHAKING_HARDWARE)
{
/* Hardware handshaking interface configuration */
if ((config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA) ||
(config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2P_DMA))
{
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
line = config->dst_peripheral_request & GPDMA0_CH_CFGH_PER_Msk;
#if defined(GPDMA1)
}
else
{
line = config->dst_peripheral_request & GPDMA1_CH_CFGH_PER_Msk;
}
#endif
peripheral = config->dst_peripheral_request >> GPDMA_CH_CFGH_PER_BITSIZE;
dma->CH[channel].CFGH |= (uint32_t)((uint32_t)line << GPDMA0_CH_CFGH_DEST_PER_Pos);
XMC_DMA_EnableRequestLine(dma, line, peripheral);
dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_HS_SEL_DST_Msk;
}
}
if (config->src_handshaking == XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE)
{
if ((config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA) ||
(config->transfer_flow == (uint32_t)XMC_DMA_CH_TRANSFER_FLOW_P2P_DMA))
{
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
line = config->src_peripheral_request & GPDMA0_CH_CFGH_PER_Msk;
#if defined(GPDMA1)
}
else
{
line = config->src_peripheral_request & GPDMA1_CH_CFGH_PER_Msk;
}
#endif
peripheral = config->src_peripheral_request >> GPDMA_CH_CFGH_PER_BITSIZE;
dma->CH[channel].CFGH |= (uint32_t)((uint32_t)line << GPDMA0_CH_CFGH_SRC_PER_Pos);
XMC_DMA_EnableRequestLine(dma, line, peripheral);
dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_HS_SEL_SRC_Msk;
}
}
XMC_DMA_CH_ClearEventStatus(dma, channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_ERROR));
switch (config->transfer_type)
{
case XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK:
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_RELOAD:
dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk;
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_CONTIGUOUS:
dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk;
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD:
dma->CH[channel].CFGL |= (uint32_t)((uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk |
(uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk);
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_LINKED:
dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_DST_EN_Msk;
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED:
dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk;
dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_DST_EN_Msk;
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_CONTIGUOUS:
dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_SRC_EN_Msk;
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_RELOAD:
dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk;
dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_LLP_SRC_EN_Msk;
break;
case XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_LINKED:
dma->CH[channel].CTLL |= (uint32_t)((uint32_t)GPDMA0_CH_CTLL_LLP_SRC_EN_Msk |
(uint32_t)GPDMA0_CH_CTLL_LLP_DST_EN_Msk);
break;
default:
break;
}
status = XMC_DMA_CH_STATUS_OK;
}
else
{
status = XMC_DMA_CH_STATUS_BUSY;
}
}
else
{
status = XMC_DMA_CH_STATUS_ERROR;
}
return status;
}
/* Suspend DMA channel transfer */
void XMC_DMA_CH_Suspend(XMC_DMA_t *const dma, const uint8_t channel)
{
dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_CH_SUSP_Msk;
}
/* Resume DMA channel transfer */
void XMC_DMA_CH_Resume(XMC_DMA_t *const dma, const uint8_t channel)
{
dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_CH_SUSP_Msk;
}
/* Check if a DMA channel is suspended */
bool XMC_DMA_CH_IsSuspended(XMC_DMA_t *const dma, const uint8_t channel)
{
return (bool)(dma->CH[channel].CFGL & (uint32_t)GPDMA0_CH_CFGL_CH_SUSP_Msk);
}
/* Enable GPDMA event */
void XMC_DMA_CH_EnableEvent(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event)
{
uint32_t event_idx;
for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx)
{
if (event & ((uint32_t)0x1UL << event_idx))
{
dma->MASKCHEV[event_idx * 2UL] = ((uint32_t)0x101UL << channel);
}
}
}
/* Disable GPDMA event */
void XMC_DMA_CH_DisableEvent(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event)
{
uint32_t event_idx;
for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx)
{
if (event & ((uint32_t)0x1UL << event_idx))
{
dma->MASKCHEV[event_idx * 2UL] = ((uint32_t)0x100UL << channel);
}
}
}
/* Clear GPDMA event */
void XMC_DMA_CH_ClearEventStatus(XMC_DMA_t *const dma, const uint8_t channel, const uint32_t event)
{
uint32_t event_idx;
for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx)
{
if (event & (uint32_t)((uint32_t)0x1UL << event_idx))
{
dma->CLEARCHEV[event_idx * 2UL] = ((uint32_t)0x1UL << channel);
}
}
}
/* Get GPDMA event status */
uint32_t XMC_DMA_CH_GetEventStatus(XMC_DMA_t *const dma, const uint8_t channel)
{
uint32_t event_idx;
uint32_t status = 0UL;
for(event_idx = 0UL; event_idx < DMA_EVENT_MAX; ++event_idx)
{
status |= (uint32_t)((dma->STATUSCHEV[event_idx * 2UL] & (uint32_t)((uint32_t)0x1UL << (uint32_t)channel)) ?
((uint32_t)0x1UL << event_idx) : (uint32_t)0UL);
}
return status;
}
/* Enable source gather */
void XMC_DMA_CH_EnableSourceGather(XMC_DMA_t *const dma, const uint8_t channel, uint32_t interval, uint16_t count)
{
dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk;
dma->CH[channel].SGR = ((uint32_t)interval << GPDMA0_CH_SGR_SGI_Pos) | ((uint32_t)count << GPDMA0_CH_SGR_SGC_Pos);
}
/* Disable source gather */
void XMC_DMA_CH_DisableSourceGather(XMC_DMA_t *const dma, const uint8_t channel)
{
dma->CH[channel].CTLL &= (uint32_t)~GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk;
}
/* Enable destination scatter */
void XMC_DMA_CH_EnableDestinationScatter(XMC_DMA_t *const dma, const uint8_t channel, uint32_t interval, uint16_t count)
{
dma->CH[channel].CTLL |= (uint32_t)GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk;
dma->CH[channel].DSR = ((uint32_t)interval << GPDMA0_CH_DSR_DSI_Pos) | ((uint32_t)count << GPDMA0_CH_DSR_DSC_Pos);
}
/* Disable destination scatter */
void XMC_DMA_CH_DisableDestinationScatter(XMC_DMA_t *const dma, const uint8_t channel)
{
dma->CH[channel].CTLL &= (uint32_t)~GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk;
}
/* Trigger source request */
void XMC_DMA_CH_TriggerSourceRequest(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_TRANSACTION_TYPE_t type, bool last)
{
if ((uint32_t)type == (uint32_t)XMC_DMA_CH_TRANSACTION_TYPE_SINGLE)
{
dma->SGLREQSRCREG = ((uint32_t)0x101UL << channel);
}
if (last == true)
{
dma->LSTSRCREG = (uint32_t)0x101UL << channel;
}
dma->REQSRCREG = (uint32_t)0x101UL << channel;
}
/* Trigger destination request */
void XMC_DMA_CH_TriggerDestinationRequest(XMC_DMA_t *const dma, const uint8_t channel, const XMC_DMA_CH_TRANSACTION_TYPE_t type, bool last)
{
if(type == XMC_DMA_CH_TRANSACTION_TYPE_SINGLE)
{
dma->SGLREQDSTREG = (uint32_t)0x101UL << channel;
}
if (last == true)
{
dma->LSTDSTREG = (uint32_t)0x101UL << channel;
}
dma->REQDSTREG = (uint32_t)0x101UL << channel;
}
/* Enable source address reload */
void XMC_DMA_CH_EnableSourceAddressReload(XMC_DMA_t *const dma, const uint8_t channel)
{
dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_SRC_Msk;
}
/* Disable source address reload */
void XMC_DMA_CH_DisableSourceAddressReload(XMC_DMA_t *const dma, const uint8_t channel)
{
dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_RELOAD_SRC_Msk;
}
/* Enable destination address reload */
void XMC_DMA_CH_EnableDestinationAddressReload(XMC_DMA_t *const dma, const uint8_t channel)
{
dma->CH[channel].CFGL |= (uint32_t)GPDMA0_CH_CFGL_RELOAD_DST_Msk;
}
/* Disable destination address reload */
void XMC_DMA_CH_DisableDestinationAddressReload(XMC_DMA_t *const dma, const uint8_t channel)
{
dma->CH[channel].CFGL &= (uint32_t)~GPDMA0_CH_CFGL_RELOAD_DST_Msk;
}
/* Request last multi-block transfer */
void XMC_DMA_CH_RequestLastMultiblockTransfer(XMC_DMA_t *const dma, const uint8_t channel)
{
dma->CH[channel].CFGL &= (uint32_t)~(GPDMA0_CH_CFGL_RELOAD_SRC_Msk | GPDMA0_CH_CFGL_RELOAD_DST_Msk);
}
/* Set event handler */
void XMC_DMA_CH_SetEventHandler(XMC_DMA_t *const dma, const uint8_t channel, XMC_DMA_CH_EVENT_HANDLER_t event_handler)
{
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
dma0_event_handlers[channel] = event_handler;
#if defined(GPDMA1)
}
else
{
dma1_event_handlers[channel] = event_handler;
}
#endif
}
void XMC_DMA_CH_ClearSourcePeripheralRequest(XMC_DMA_t *const dma, uint8_t channel)
{
uint32_t line;
line = (dma->CH[channel].CFGH & GPDMA0_CH_CFGH_SRC_PER_Msk) >> GPDMA0_CH_CFGH_SRC_PER_Pos;
XMC_DMA_ClearRequestLine(dma, (uint8_t)line);
}
void XMC_DMA_CH_ClearDestinationPeripheralRequest(XMC_DMA_t *const dma, uint8_t channel)
{
uint32_t line;
line = (dma->CH[channel].CFGH & GPDMA0_CH_CFGH_DEST_PER_Msk) >> GPDMA0_CH_CFGH_DEST_PER_Pos;
XMC_DMA_ClearRequestLine(dma, (uint8_t)line);
}
/* Default DMA IRQ handler */
void XMC_DMA_IRQHandler(XMC_DMA_t *const dma)
{
uint32_t event;
int32_t channel;
uint32_t mask;
XMC_DMA_CH_EVENT_HANDLER_t *dma_event_handlers;
XMC_DMA_CH_EVENT_HANDLER_t event_handler;
#if defined(GPDMA1)
if (dma == XMC_DMA0)
{
#endif
dma_event_handlers = dma0_event_handlers;
#if defined(GPDMA1)
}
else
{
dma_event_handlers = dma1_event_handlers;
}
#endif
event = XMC_DMA_GetEventStatus(dma);
channel = 0;
if ((event & (uint32_t)XMC_DMA_CH_EVENT_ERROR) != (uint32_t)0UL)
{
event = XMC_DMA_GetChannelsErrorStatus(dma);
while (event != 0)
{
mask = (uint32_t)1U << channel;
if ((event & mask) != 0)
{
XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_ERROR);
/* Call user callback to handle event */
event_handler = dma_event_handlers[channel];
if (event_handler != NULL)
{
event_handler(XMC_DMA_CH_EVENT_ERROR);
}
break;
}
++channel;
}
}
else if ((event & (uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE) != (uint32_t)0UL)
{
event = XMC_DMA_GetChannelsTransferCompleteStatus(dma);
while (event != 0)
{
mask = (uint32_t)1U << channel;
if (event & mask)
{
XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_TRANSFER_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE));
/* Call user callback to handle event */
event_handler = dma_event_handlers[channel];
if (event_handler != NULL)
{
event_handler(XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);
}
break;
}
++channel;
}
}
else if ((event & (uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE) != (uint32_t)0UL)
{
event = XMC_DMA_GetChannelsBlockCompleteStatus(dma);
while (event != 0)
{
mask = (uint32_t)1U << channel;
if (event & mask)
{
XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)((uint32_t)XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE |
(uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE));
/* Call user callback to handle event */
event_handler = dma_event_handlers[channel];
if (event_handler != NULL)
{
event_handler(XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE);
}
break;
}
++channel;
}
}
else if ((event & (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE) != (uint32_t)0UL)
{
event = XMC_DMA_GetChannelsSourceTransactionCompleteStatus(dma);
while (event != 0)
{
mask = (uint32_t)1U << channel;
if (event & mask)
{
XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE);
/* Call user callback to handle event */
event_handler = dma_event_handlers[channel];
if (event_handler != NULL)
{
event_handler(XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE);
}
break;
}
++channel;
}
}
else if ((event & (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE) != (uint32_t)0UL)
{
event = XMC_DMA_GetChannelsDestinationTransactionCompleteStatus(dma);
while (event != 0)
{
mask = (uint32_t)1U << channel;
if (event & mask)
{
XMC_DMA_CH_ClearEventStatus(dma, (uint8_t)channel, (uint32_t)XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE);
/* Call user callback to handle event */
event_handler = dma_event_handlers[channel];
if (event_handler != NULL)
{
event_handler(XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE);
}
break;
}
++channel;
}
}
else
{
/* no active interrupt was found? */
}
}
#endif /* GPDMA0 */

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Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Libraries/XMCLib/src/xmc_dsd.c Normal file
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@ -0,0 +1,369 @@
/**
* @file xmc_dsd.c
* @date 2015-09-18
*
* @cond
**********************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification,are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share
* modifications, enhancements or bug fixes with Infineon Technologies AG
* dave@infineon.com).
**********************************************************************************
*
* Change History
* --------------
*
* 2015-03-30:
* - Initial version
*
* 2015-06-19:
* - Removed GetDriverVersion API <BR>
*
* 2015-09-18:
* - Support added for XMC4800 microcontroller family <BR>
* @endcond
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_dsd.h"
#if defined(DSD)
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_DSD_MIN_FILTER_START (4U)
#define XMC_DSD_MIN_DECIMATION_FACTOR (4U)
#define XMC_DSD_MAX_DECIMATION_FACTOR (256U)
#define XMC_DSD_MAX_DECIMATION_FACTOR_AUX (32U)
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/*Enable the DSD Module*/
void XMC_DSD_Enable(XMC_DSD_t *const dsd)
{
XMC_ASSERT("XMC_DSD_Enable:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd));
XMC_UNUSED_ARG(dsd);
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DSD);
#endif
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_DSD);
}
/*Disable the DSD Module*/
void XMC_DSD_Disable(XMC_DSD_t *const dsd)
{
XMC_ASSERT("XMC_DSD_Disable:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd));
XMC_UNUSED_ARG(dsd);
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_DSD);
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_DSD);
#endif
}
/* Enable the module clock*/
void XMC_DSD_EnableClock(XMC_DSD_t *const dsd)
{
XMC_ASSERT("XMC_DSD_EnableClock:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd));
/* Enable the module clock */
dsd->CLC &= ~(uint32_t)DSD_CLC_DISR_Msk;
/* enable internal module clock */
dsd ->GLOBCFG |= (uint32_t)0x01;
}
void XMC_DSD_DisableClock(XMC_DSD_t *const dsd)
{
XMC_ASSERT("XMC_DSD_DisableClock:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd));
/* disable internal module clock */
dsd->GLOBCFG &= ~(uint32_t)DSD_GLOBCFG_MCSEL_Msk;
/* stop the module clock */
dsd->CLC |= (uint32_t)DSD_CLC_DISR_Msk;
}
/* Enable the DSD module and clock */
void XMC_DSD_Init(XMC_DSD_t *const dsd)
{
XMC_ASSERT("XMC_DSD_Init:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd));
XMC_DSD_Enable(dsd);
XMC_DSD_EnableClock(dsd);
}
bool XMC_DSD_IsEnabled(XMC_DSD_t *const dsd)
{
bool status;
XMC_ASSERT("XMC_DSD_Disable:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd));
XMC_UNUSED_ARG(dsd);
#if ((UC_SERIES == XMC44) || (UC_SERIES == XMC48)||(UC_SERIES == XMC47))
if(XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DSD) == false)
{
if(XMC_SCU_CLOCK_IsPeripheralClockGated(XMC_SCU_PERIPHERAL_CLOCK_DSD) == false)
{
status = true;
}
else
{
status = false;
}
}
else
{
status = false;
}
#else
if(XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_DSD) == false)
{
status = true;
}
else
{
status = false;
}
#endif
return (status);
}
/*Initializes the Waveform Generator*/
void XMC_DSD_Generator_Init(XMC_DSD_t *const dsd, const XMC_DSD_GENERATOR_CONFIG_t *const config)
{
XMC_ASSERT("XMC_DSD_GENERATOR_Init:Invalid module pointer", XMC_DSD_CHECK_MODULE_PTR(dsd));
XMC_ASSERT("XMC_DSD_GENERATOR_Init:NULL Pointer", (config != (XMC_DSD_GENERATOR_CONFIG_t *)NULL) );
/* Reset Generator */
dsd ->CGCFG &= ~((uint32_t)DSD_CGCFG_CGMOD_Msk | (uint32_t)DSD_CGCFG_BREV_Msk | (uint32_t)DSD_CGCFG_SIGPOL_Msk | (uint32_t)DSD_CGCFG_DIVCG_Msk);
/* Generator configuration */
dsd ->CGCFG = config->generator_conf;
}
/* Initialize main filter,auxiliary filter,integrator, rectifier and timestamp of DSD*/
XMC_DSD_STATUS_t XMC_DSD_CH_Init( XMC_DSD_CH_t *const channel, const XMC_DSD_CH_CONFIG_t *const config)
{
XMC_DSD_STATUS_t status;
XMC_ASSERT("XMC_DSD_CH_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel));
XMC_ASSERT("XMC_DSD_CH_Init:NULL Pointer", (config != (XMC_DSD_CH_CONFIG_t *)NULL) );
if (config->filter != (XMC_DSD_CH_FILTER_CONFIG_t*)NULL)
{
XMC_DSD_CH_MainFilter_Init(channel, config->filter);
if (config->aux != (XMC_DSD_CH_AUX_FILTER_CONFIG_t*)NULL)
{
XMC_DSD_CH_AuxFilter_Init(channel, config->aux);
}
if (config->integrator != (XMC_DSD_CH_INTEGRATOR_CONFIG_t*)NULL)
{
XMC_DSD_CH_Integrator_Init(channel, config->integrator);
}
if (config->rectify != (XMC_DSD_CH_RECTIFY_CONFIG_t*)NULL)
{
XMC_DSD_CH_Rectify_Init(channel, config->rectify);
}
if (config->timestamp != (XMC_DSD_CH_TIMESTAMP_CONFIG_t*)NULL)
{
XMC_DSD_CH_Timestamp_Init(channel, config->timestamp);
}
status = XMC_DSD_STATUS_OK;
}
else
{
status = XMC_DSD_STATUS_ERROR;
}
return (status);
}
/* Initialize main filter of DSD */
void XMC_DSD_CH_MainFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_FILTER_CONFIG_t *const config)
{
uint32_t decimation_factor_temp;
uint32_t filter_start_value_temp;
XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel));
XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:NULL Pointer", (config != (XMC_DSD_CH_FILTER_CONFIG_t *)NULL) );
XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid Filter Start Value", (config->filter_start_value >= XMC_DSD_MIN_FILTER_START));
XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid Filter Start Value", (config->filter_start_value <= config->decimation_factor));
XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid Decimation Factor",
((config->decimation_factor >= XMC_DSD_MIN_DECIMATION_FACTOR) && (config->decimation_factor <= XMC_DSD_MAX_DECIMATION_FACTOR)));
XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid divider",(((uint32_t)config->clock_divider <= XMC_DSD_CH_CLK_DIV_32)));
/*Set Channel frequency*/
channel->MODCFG = ((uint32_t)config->clock_divider << DSD_CH_MODCFG_DIVM_Pos) | (uint32_t)DSD_CH_MODCFG_DWC_Msk;
/* Input Data/Clk */
channel->DICFG = config->demodulator_conf | (uint32_t)DSD_CH_DICFG_DSWC_Msk | (uint32_t)DSD_CH_DICFG_SCWC_Msk;
/*The decimation factor of the Main CIC filter is CFMDF + 1.*/
decimation_factor_temp = config->decimation_factor-1U;
filter_start_value_temp = config->filter_start_value-1U;
/* Filter setup*/
channel->FCFGC = (decimation_factor_temp |
(filter_start_value_temp << (uint32_t)DSD_CH_FCFGC_CFMSV_Pos)|
config->main_filter_conf|
(uint32_t)DSD_CH_FCFGC_CFEN_Msk);
/* Offset */
channel->OFFM = (uint16_t)config->offset;
}
/* Initialize timestamp mode of DSD */
void XMC_DSD_CH_Timestamp_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_TIMESTAMP_CONFIG_t *const config)
{
uint32_t temp;
XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel));
XMC_ASSERT("XMC_DSD_MAIN_FILTER_Init:NULL Pointer", (config != (XMC_DSD_CH_TIMESTAMP_CONFIG_t *)NULL) );
temp = (channel->DICFG | (uint32_t)DSD_CH_DICFG_TRWC_Msk);
temp &= ~((uint32_t)DSD_CH_DICFG_TSTRMODE_Msk|(uint32_t)DSD_CH_DICFG_TRSEL_Msk);
temp |= config->timestamp_conf;
channel->DICFG = temp;
}
/* Initialize auxiliary filter of DSD */
void XMC_DSD_CH_AuxFilter_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_AUX_FILTER_CONFIG_t *const config)
{
uint32_t decimation_factor_temp;
XMC_ASSERT("XMC_DSD_AUX_FILTER_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel));
XMC_ASSERT("XMC_DSD_AUX_FILTER_Init:NULL Pointer", (config != (XMC_DSD_CH_AUX_FILTER_CONFIG_t *)NULL) );
XMC_ASSERT("XMC_DSD_AUX_FILTER_Init:Invalid Decimation Factor",
((config->decimation_factor >= XMC_DSD_MIN_DECIMATION_FACTOR) && (config->decimation_factor <= XMC_DSD_MAX_DECIMATION_FACTOR_AUX)));
channel->BOUNDSEL = config->boundary_conf;
/*The decimation factor of the Aux CIC filter is CFMDF + 1.*/
decimation_factor_temp = config->decimation_factor-1U;
channel->FCFGA = (decimation_factor_temp | config->aux_filter_conf);
}
/* Integrator initialization of DSD */
void XMC_DSD_CH_Integrator_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_INTEGRATOR_CONFIG_t *const config)
{
uint32_t temp;
XMC_ASSERT("XMC_DSD_INTEGRATOR_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel));
XMC_ASSERT("XMC_DSD_INTEGRATOR_Init:NULL Pointer", (config != (XMC_DSD_CH_INTEGRATOR_CONFIG_t *)NULL) );
XMC_ASSERT("XMC_DSD_INTEGRATOR_Init:Invalid integration_loop", (config->integration_loop > 0U ));
XMC_ASSERT("XMC_DSD_INTEGRATOR_Init:Invalid counted_values", (config->counted_values > 0U ));
channel->IWCTR = ((config->integration_loop - 1U) << DSD_CH_IWCTR_REPVAL_Pos)
| (config->discarded_values << DSD_CH_IWCTR_NVALDIS_Pos)
| (config->stop_condition << DSD_CH_IWCTR_IWS_Pos)
| ((config->counted_values - 1U) << DSD_CH_IWCTR_NVALINT_Pos);
/*To ensure proper operation, ensure that bit field ITRMODE is zero before selecting any other trigger mode.*/
temp = (channel->DICFG & ~((uint32_t)DSD_CH_DICFG_ITRMODE_Msk|(uint32_t)DSD_CH_DICFG_TRSEL_Msk)) | (uint32_t)DSD_CH_DICFG_TRWC_Msk;
channel->DICFG = temp;
temp |= config->integrator_trigger;
channel->DICFG = temp;
}
/* Rectifier initialization of DSD */
void XMC_DSD_CH_Rectify_Init(XMC_DSD_CH_t *const channel, const XMC_DSD_CH_RECTIFY_CONFIG_t *const config)
{
XMC_ASSERT("XMC_DSD_RECTIFY_Init:Invalid module pointer", XMC_DSD_CHECK_CHANNEL_PTR(channel));
XMC_ASSERT("XMC_DSD_RECTIFY_Init:NULL Pointer", (config != (XMC_DSD_CH_RECTIFY_CONFIG_t *)NULL));
XMC_ASSERT("XMC_DSD_RECTIFY_Init:NULL Pointer", (((uint16_t)config->delay + (uint16_t)config->half_cycle) <= 0xFF));
channel->RECTCFG = config->rectify_config | (uint32_t)DSD_CH_RECTCFG_RFEN_Msk;
channel->CGSYNC = (((uint32_t) config->delay << (uint32_t)DSD_CH_CGSYNC_SDPOS_Pos)
| (((uint32_t)config->delay + (uint32_t)config->half_cycle) << (uint32_t)DSD_CH_CGSYNC_SDNEG_Pos));
}
/* API to get the result of the last conversion */
void XMC_DSD_CH_GetResult_TS(XMC_DSD_CH_t* const channel,
int16_t* dsd_result,
uint8_t* dsd_filter_count,
uint8_t* dsd_integration_count)
{
uint32_t timestamp;
uint16_t result;
timestamp = channel->TSTMP;
result = (uint16_t)((uint32_t)timestamp & DSD_CH_TSTMP_RESULT_Msk);
*dsd_result = (int16_t)(result);
*dsd_filter_count = (uint8_t) ((timestamp & (uint32_t)DSD_CH_TSTMP_CFMDCNT_Msk)>>(uint32_t)DSD_CH_TSTMP_CFMDCNT_Pos);
*dsd_integration_count = (uint8_t) ((timestamp & (uint32_t)DSD_CH_TSTMP_NVALCNT_Msk)>>(uint32_t)DSD_CH_TSTMP_NVALCNT_Pos);
}
/* API to get the result of the last conversion with the time */
void XMC_DSD_CH_GetResult_TS_Time(XMC_DSD_CH_t* const channel, int16_t* dsd_Result, uint32_t* time)
{
uint32_t timestamp;
uint16_t filter_count;
uint16_t integrator_count;
uint16_t decimation;
uint16_t result;
timestamp = channel->TSTMP;
decimation = (uint16_t)(channel->FCFGC & DSD_CH_FCFGC_CFMDF_Msk);
filter_count = (uint16_t)((timestamp & DSD_CH_TSTMP_CFMDCNT_Msk)>>DSD_CH_TSTMP_CFMDCNT_Pos);
/* Integration enabled? */
if ((channel->IWCTR & DSD_CH_IWCTR_INTEN_Msk))
{
integrator_count = (uint16_t) ((timestamp & DSD_CH_TSTMP_NVALCNT_Msk)>>DSD_CH_TSTMP_NVALCNT_Pos);
/*See Errata number: xxyy */
if (filter_count == decimation)
{
integrator_count++;
}
*time = (uint32_t)(((uint32_t) integrator_count * ((uint32_t) decimation + 1U)) + (uint32_t) ((uint32_t)decimation - filter_count));
}
else
{
*time = (uint32_t) ((uint32_t)decimation - filter_count);
}
result = (uint16_t)((uint32_t)timestamp & DSD_CH_TSTMP_RESULT_Msk);
*dsd_Result = (int16_t)(result);
}
#endif /*DSD*/

122
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/**
* @file xmc_ebu.c
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-06-20:
* - Removed GetDriverVersion API
* @endcond
*
*/
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include <xmc_ebu.h>
#if defined(EBU)
/*********************************************************************************************************************
* API IMPLEMENTATION
*********************************************************************************************************************/
/*
* Initialize the EBU peripheral
*/
XMC_EBU_STATUS_t XMC_EBU_Init(XMC_EBU_t *const ebu,const XMC_EBU_CONFIG_t *const config)
{
XMC_ASSERT("XMC_EBU_Init: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
XMC_ASSERT("XMC_EBU_Init:Null Pointer", (config != (XMC_EBU_CONFIG_t *)NULL));
/* Enable EBU */
XMC_EBU_Enable(ebu);
/* Clock configuration */
ebu->CLC = config->ebu_clk_config.raw0;
/*EBU Mode Configuration */
ebu->MODCON = config->ebu_mode_config.raw0;
/* Address Bits available for GPIO function */
ebu->USERCON = config->ebu_free_pins_to_gpio.raw0;
return XMC_EBU_STATUS_OK;
}
/*
* Configures the SDRAM with operating modes and refresh parameters
*/
void XMC_EBU_ConfigureSdram(XMC_EBU_t *const ebu,const XMC_EBU_SDRAM_CONFIG_t *const config)
{
XMC_ASSERT("XMC_EBU_Init: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
XMC_ASSERT("XMC_EBU_Init:Null Pointer", (config != (XMC_EBU_SDRAM_CONFIG_t *)NULL));
/* EBU SDRAM Refresh Configuration Parameters */
ebu->SDRMREF = config->raw2;
/* EBU SDRAM General Configuration Parameters */
ebu->SDRMCON = config->raw0;
/* EBU SDRAM Operation Mode Configuration Parameters */
ebu->SDRMOD = config->raw1;
}
/*
* Configures the SDRAM region for read and write operation
*/
void XMC_EBU_ConfigureRegion(XMC_EBU_t *const ebu,const XMC_EBU_REGION_t *const region)
{
XMC_ASSERT("XMC_EBU_Init: Invalid module pointer", XMC_EBU_CHECK_MODULE_PTR(ebu));
XMC_ASSERT("XMC_EBU_Init:Null Pointer", (region != (XMC_EBU_REGION_t *)NULL));
/* Read configuration of the region*/
ebu->BUS[region->read_config.ebu_region_no].RDCON = region->read_config.ebu_bus_read_config.raw0;
/* Read parameters of the region*/
ebu->BUS[region->read_config.ebu_region_no].RDAPR = region->read_config.ebu_bus_read_config.raw1;
/* Write configuration of the region*/
ebu->BUS[region->write_config.ebu_region_no].WRCON = region->write_config.ebu_bus_write_config.raw0;
/* Write parameters of the region*/
ebu->BUS[region->write_config.ebu_region_no].WRAPR = region->write_config.ebu_bus_write_config.raw1;
}
#endif /* defined(EBU) */

198
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/**
* @file xmc_ecat.c
* @date 2015-10-21
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-12-27:
* - Add clock gating control in enable/disable APIs
*
* 2015-10-21:
* - Initial Version
*
* @endcond
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include <xmc_ecat.h>
#if defined (ECAT0)
#include <xmc_scu.h>
/*******************************************************************************
* MACROS
*******************************************************************************/
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
/* The function defines the access state to the MII management for the PDI interface*/
__STATIC_INLINE void XMC_ECAT_lRequestPhyAccessToMII(void)
{
ECAT0->MII_PDI_ACS_STATE |= 0x01;
}
/* EtherCAT module clock ungating and deassert reset API (Enables ECAT) */
void XMC_ECAT_Enable(void)
{
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ECAT0);
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ECAT0);
while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == true){}
}
/* EtherCAT module clock gating and assert reset API (Disables ECAT)*/
void XMC_ECAT_Disable(void)
{
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ECAT0);
while (XMC_SCU_RESET_IsPeripheralResetAsserted(XMC_SCU_PERIPHERAL_RESET_ECAT0) == false){}
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ECAT0);
}
/* EtherCAT initialization function */
void XMC_ECAT_Init(XMC_ECAT_CONFIG_t *const config)
{
XMC_ECAT_Enable();
/* The process memory is not accessible until the ESC Configuration Area is loaded successfully. */
/* words 0x0-0x3 */
ECAT0->EEP_DATA[0U] = config->dword[0U];
ECAT0->EEP_DATA[1U] = config->dword[1U];
ECAT0->EEP_CONT_STAT |= (uint16_t)((uint16_t)0x4U << (uint16_t)ECAT_EEP_CONT_STAT_CMD_REG_Pos);
/* words 0x4-0x7 */
ECAT0->EEP_DATA[0U] = config->dword[2U];
ECAT0->EEP_DATA[1U] = config->dword[3U];
ECAT0->EEP_CONT_STAT |= (uint16_t)((uint16_t)0x4U << (uint16_t)ECAT_EEP_CONT_STAT_CMD_REG_Pos);
while (ECAT0->EEP_CONT_STAT & ECAT_EEP_CONT_STAT_L_STAT_Msk)
{
/* Wait until the EEPROM_Loaded signal is active */
}
}
/* EtherCAT application event enable API */
void XMC_ECAT_EnableEvent(uint32_t event)
{
ECAT0->AL_EVENT_MASK |= event;
}
/* EtherCAT application event disable API */
void XMC_ECAT_DisableEvent(uint32_t event)
{
ECAT0->AL_EVENT_MASK &= ~event;
}
/* EtherCAT application event status reading API */
uint32_t XMC_ECAT_GetEventStatus(void)
{
return (ECAT0->AL_EVENT_REQ);
}
/* EtherCAT SyncManager channel disable function*/
void XMC_ECAT_DisableSyncManChannel(const uint8_t channel)
{
((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR |= 0x1U;
}
/* EtherCAT SyncManager channel enable function*/
void XMC_ECAT_EnableSyncManChannel(const uint8_t channel)
{
((ECAT0_SM_Type *)(void*)((uint8_t *)(void*)ECAT0_SM0 + (channel * 8U)))->SM_PDI_CTR &= (uint8_t)(~0x1U);
}
/* EtherCAT PHY register read function*/
XMC_ECAT_STATUS_t XMC_ECAT_ReadPhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
{
XMC_ECAT_STATUS_t status;
XMC_ECAT_lRequestPhyAccessToMII();
ECAT0->MII_PHY_ADR = phy_addr;
ECAT0->MII_PHY_REG_ADR = reg_addr;
ECAT0->MII_CONT_STAT |= 0x0100U; /* read instruction */
while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U){}
if ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_ERROR_Msk) != 0U)
{
ECAT0->MII_CONT_STAT &= ~ECAT_MII_CONT_STAT_CMD_REG_Msk; /* Clear error */
status = XMC_ECAT_STATUS_ERROR;
}
else
{
*data = (uint16_t)ECAT0->MII_PHY_DATA;
status = XMC_ECAT_STATUS_OK;
}
return status;
}
/* EtherCAT PHY register write function*/
XMC_ECAT_STATUS_t XMC_ECAT_WritePhy(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
{
XMC_ECAT_STATUS_t status;
XMC_ECAT_lRequestPhyAccessToMII();
ECAT0->MII_PHY_ADR = phy_addr;
ECAT0->MII_PHY_REG_ADR = reg_addr;
ECAT0->MII_PHY_DATA = data;
ECAT0->MII_CONT_STAT |= 0x0200U; /* write instruction */
while ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_BUSY_Msk) != 0U){}
if ((ECAT0->MII_CONT_STAT & ECAT_MII_CONT_STAT_ERROR_Msk) != 0U)
{
ECAT0->MII_CONT_STAT &= ~ECAT_MII_CONT_STAT_CMD_REG_Msk; /* Clear error */
status = XMC_ECAT_STATUS_ERROR;
}
else
{
status = XMC_ECAT_STATUS_OK;
}
return status;
}
#endif

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/**
* @file xmc_eru.c
* @date 2016-03-10
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-06-20:
* - Removed definition of GetDriverVersion API <br>
*
* 2016-03-10:
* - XMC_ERU_ETL_GetEdgeDetection() API is added to get the configured edge for event generation. <br>
*
* @endcond
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_eru.h"
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define ERU_EXISEL_BITSIZE (4UL) /* Used to set the input for path A and path B based on the channel */
#define ERU_EXISEL_INPUT_BITSIZE (2UL)
#define XMC_ERU_ETL_CHECK_INPUT_A(input) \
((input == XMC_ERU_ETL_INPUT_A0) || \
(input == XMC_ERU_ETL_INPUT_A1) || \
(input == XMC_ERU_ETL_INPUT_A2) || \
(input == XMC_ERU_ETL_INPUT_A3))
#define XMC_ERU_ETL_CHECK_INPUT_B(input) \
((input == XMC_ERU_ETL_INPUT_B0) || \
(input == XMC_ERU_ETL_INPUT_B1) || \
(input == XMC_ERU_ETL_INPUT_B2) || \
(input == XMC_ERU_ETL_INPUT_B3))
#define XMC_ERU_ETL_CHECK_STATUS_FLAG_MODE(mode) \
((mode == XMC_ERU_ETL_STATUS_FLAG_MODE_SWCTRL) || \
(mode == XMC_ERU_ETL_STATUS_FLAG_MODE_HWCTRL))
#define XMC_ERU_ETL_CHECK_EVENT_SOURCE(source) \
((source == XMC_ERU_ETL_SOURCE_A) || \
(source == XMC_ERU_ETL_SOURCE_B) || \
(source == XMC_ERU_ETL_SOURCE_A_OR_B) || \
(source == XMC_ERU_ETL_SOURCE_A_AND_B) || \
(source == XMC_ERU_ETL_SOURCE_NOT_A) || \
(source == XMC_ERU_ETL_SOURCE_NOT_A_OR_B) || \
(source == XMC_ERU_ETL_SOURCE_NOT_A_AND_B) || \
(source == XMC_ERU_ETL_SOURCE_NOT_B) || \
(source == XMC_ERU_ETL_SOURCE_A_OR_NOT_B) || \
(source == XMC_ERU_ETL_SOURCE_A_AND_NOT_B) || \
(source == XMC_ERU_ETL_SOURCE_NOT_A_OR_NOT_B) || \
(source == XMC_ERU_ETL_SOURCE_NOT_A_AND_NOT_B))
#define XMC_ERU_ETL_CHECK_TRIGGER_EDGE(edge) \
((edge == XMC_ERU_ETL_EDGE_DETECTION_DISABLED) || \
(edge == XMC_ERU_ETL_EDGE_DETECTION_RISING) || \
(edge == XMC_ERU_ETL_EDGE_DETECTION_FALLING) || \
(edge == XMC_ERU_ETL_EDGE_DETECTION_BOTH))
#define XMC_ERU_ETL_CHECK_TRIGGER_CHANNEL(channel) \
((channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL0) || \
(channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL1) || \
(channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL2) || \
(channel == XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL3))
#define XMC_ERU_OGU_CHECK_PATTERN_INPUT(input) \
((input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT0) || \
(input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT1) || \
(input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT2) || \
(input == XMC_ERU_OGU_PATTERN_DETECTION_INPUT3))
#define XMC_ERU_OGU_CHECK_PERIPHERAL_TRIGGER(trigger) \
((trigger == XMC_ERU_OGU_PERIPHERAL_TRIGGER1) || \
(trigger == XMC_ERU_OGU_PERIPHERAL_TRIGGER2) || \
(trigger == XMC_ERU_OGU_PERIPHERAL_TRIGGER3))
#define XMC_ERU_OGU_CHECK_SERIVCE_REQUEST(service) \
((service == XMC_ERU_OGU_SERVICE_REQUEST_DISABLED) || \
(service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER) || \
(service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MATCH) || \
(service == XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MISMATCH))
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/* Initializes the selected ERU_ETLx channel with the config structure. */
void XMC_ERU_ETL_Init(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_CONFIG_t *const config)
{
XMC_ASSERT("XMC_ERU_ETL_Init:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_Init:Invalid Channel Number", (channel < 4U));
XMC_ERU_Enable(eru);
eru->EXISEL = (eru->EXISEL &
~((uint32_t)(ERU_EXISEL_EXS0A_Msk | ERU_EXISEL_EXS0B_Msk) << (channel * ERU_EXISEL_BITSIZE))) |
(config->input << (channel * (uint32_t)ERU_EXISEL_BITSIZE));
eru->EXICON[channel] = config->raw;
}
/* Initializes the selected ERU_OGUy channel with the config structure. */
void XMC_ERU_OGU_Init(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_CONFIG_t *const config)
{
XMC_ASSERT("XMC_ERU_OGU_Init:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_Init:Invalid Channel Number", (channel < 4U));
XMC_ERU_Enable(eru);
eru->EXOCON[channel] = config->raw;
}
/* Configures the event source for path A and path B, with selected input_a and input_b respectively.*/
void XMC_ERU_ETL_SetInput(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_INPUT_A_t input_a,
const XMC_ERU_ETL_INPUT_B_t input_b)
{
XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid A", XMC_ERU_ETL_CHECK_INPUT_A(input_a));
XMC_ASSERT("XMC_ERU_ETL_SetInput:Invalid B", XMC_ERU_ETL_CHECK_INPUT_B(input_b));
eru->EXISEL = (eru->EXISEL & ~((uint32_t)(ERU_EXISEL_EXS0A_Msk | ERU_EXISEL_EXS0B_Msk) << (channel * ERU_EXISEL_BITSIZE))) |
(((uint32_t)input_a | (uint32_t)(input_b << ERU_EXISEL_INPUT_BITSIZE)) << (channel * ERU_EXISEL_BITSIZE));
}
/* Select input path combination along with polarity for event generation by setting (SS, NA, NB) bits of
EXICONx(x = [0 to 3]) register */
void XMC_ERU_ETL_SetSource(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_SOURCE_t source)
{
XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_ETL_SetSource:Invalid Source", XMC_ERU_ETL_CHECK_EVENT_SOURCE(source));
eru->EXICON_b[channel].SS = (uint8_t)source;
}
/* Configure event trigger edge/s by setting (RE, FE) bits of EXICONx(x = [0 to 3]) register.*/
void XMC_ERU_ETL_SetEdgeDetection(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_EDGE_DETECTION_t edge_detection)
{
XMC_ASSERT("XMC_ERU_ETL_SetEdgeDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_SetEdgeDetection:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_ETL_SetEdgeDetection:Invalid Trigger Edge", XMC_ERU_ETL_CHECK_TRIGGER_EDGE(edge_detection));
eru->EXICON_b[channel].ED = (uint8_t)edge_detection;
}
/* Returns the configured event trigger edge/s by reading (RE, FE) bits of EXICONx(x = [0 to 3]) register. */
XMC_ERU_ETL_EDGE_DETECTION_t XMC_ERU_ETL_GetEdgeDetection(XMC_ERU_t *const eru, const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_ETL_GetEdgeDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_GetEdgeDetection:Invalid Channel Number", (channel < 4U));
return ((XMC_ERU_ETL_EDGE_DETECTION_t)(eru->EXICON_b[channel].ED));
}
/* Set the status flag bit(FL) in EXICONx(x = [0 to 3]). */
void XMC_ERU_ETL_SetStatusFlagMode(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_STATUS_FLAG_MODE_t mode)
{
XMC_ASSERT("XMC_ERU_ETL_SetStatusFlagMode:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_SetStatusFlagMode:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_ETL_SetStatusFlagMode:Invalid Status Flag Mode", XMC_ERU_ETL_CHECK_STATUS_FLAG_MODE(mode));
eru->EXICON_b[channel].LD = (uint8_t)mode;
}
/* Configure which Channel of OGUy(Output gating unit y = [0 to 3]) to be mapped by the trigger pulse generated by
* ETLx(Event Trigger Logic, x = [0 to 3]) by setting (OCS and PE) bit fields. */
void XMC_ERU_ETL_EnableOutputTrigger(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t trigger)
{
XMC_ASSERT("XMC_ERU_ETL_EnableOutputTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_EnableOutputTrigger:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_ETL_EnableOutputTrigger:Invalid Output Channel", XMC_ERU_ETL_CHECK_TRIGGER_CHANNEL(trigger));
eru->EXICON_b[channel].OCS = (uint8_t)trigger;
eru->EXICON_b[channel].PE = (uint8_t)true;
}
/* Disables the trigger pulse generation by clearing the (PE) of the EXICONx(x = [0 to 3]). */
void XMC_ERU_ETL_DisableOutputTrigger(XMC_ERU_t *const eru, const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_ETL_DisableOutputTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_ETL_DisableOutputTrigger:Invalid Channel Number", (channel < 4U));
eru->EXICON_b[channel].PE = false;
}
/* Configures ERU_ETLx(x = [0 to 3]) for pattern match detection by setting IPENx(x = [0 to 3) and GEEN bits. */
void XMC_ERU_OGU_EnablePatternDetection(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t input)
{
XMC_ASSERT("XMC_ERU_OGU_EnablePatternDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_EnablePatternDetection:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_OGU_EnablePatternDetection:Invalid Pattern input", XMC_ERU_OGU_CHECK_PATTERN_INPUT(input));
eru->EXOCON_b[channel].IPEN = (uint8_t)input;
eru->EXOCON_b[channel].GEEN = true;
}
/* Disable the pattern detection by clearing (GEEN) bit. */
void XMC_ERU_OGU_DisablePatternDetection(XMC_ERU_t *const eru, const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_OGU_DisablePatternDetection:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_DisablePatternDetection:Invalid Channel Number", (channel < 4U));
eru->EXOCON_b[channel].GEEN = false;
}
/* Configures peripheral trigger input, by setting (ISS) bit. */
void XMC_ERU_OGU_EnablePeripheralTrigger(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_PERIPHERAL_TRIGGER_t peripheral_trigger)
{
XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_OGU_EnablePeripheralTrigger:Invalid Peripheral Trigger Input",
XMC_ERU_OGU_CHECK_PERIPHERAL_TRIGGER(peripheral_trigger));
eru->EXOCON_b[channel].ISS = (uint8_t)peripheral_trigger;
}
/* Disables event generation based on peripheral trigger by clearing (ISS) bit. */
void XMC_ERU_OGU_DisablePeripheralTrigger(XMC_ERU_t *const eru,
const uint8_t channel)
{
XMC_ASSERT("XMC_ERU_OGU_DisablePeripheralTrigger:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_DisablePeripheralTrigger:Invalid Channel Number", (channel < 4U));
eru->EXOCON_b[channel].ISS = (uint8_t)0;
}
/* Configures the gating scheme for service request generation by setting (GP) bit. */
void XMC_ERU_OGU_SetServiceRequestMode(XMC_ERU_t *const eru,
const uint8_t channel,
const XMC_ERU_OGU_SERVICE_REQUEST_t mode)
{
XMC_ASSERT("XMC_ERU_OGU_SetServiceRequestMode:Invalid Module Pointer", XMC_ERU_CHECK_MODULE_PTR(eru));
XMC_ASSERT("XMC_ERU_OGU_SetServiceRequestMode:Invalid Channel Number", (channel < 4U));
XMC_ASSERT("XMC_ERU_OGU_SetServiceRequestMode:Invalid Service Request Mode", XMC_ERU_OGU_CHECK_SERIVCE_REQUEST(mode));
eru->EXOCON_b[channel].GP = (uint8_t)mode;
}

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/**
* @file xmc_eth_mac.c
* @date 2017-04-17
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-06-20:
* - Initial
*
* 2015-09-01:
* - Add clock gating control in enable/disable APIs
* - Add transmit polling if run out of buffers
*
* 2015-11-30:
* - Fix XMC_ETH_MAC_GetRxFrameSize return value in case of errors
*
* 2016-03-16:
* - Fix XMC_ETH_MAC_DisableEvent
*
* 2016-05-19:
* - Changed XMC_ETH_MAC_ReturnTxDescriptor and XMC_ETH_MAC_ReturnRxDescriptor
*
* 2016-08-30:
* - Changed XMC_ETH_MAC_Init() to disable MMC interrupt events
*
* 2016-11-22:
* - Changed XMC_ETH_MAC_Init() to optimize access to bus
*
* 2017-02-25:
* - XMC_ETH_MAC_Enable() and XMC_ETH_MAC_Disable(), fixed compilation warnings
*
* 2017-03-27:
* - Changed XMC_ETH_MAC_Init() to disable PMT and timestamp interrupt events
*
* 2017-04-02:
* - Added XMC_ETH_MAC_InitPTPEx()
* - Added XMC_ETH_MAC_SetPTPTime()
* - Added XMC_ETH_MAC_UpdateAddend()
* - Fixed XMC_ETH_MAC_InitPTP(), XMC_ETH_MAC_UpdatePTPTime(), XMC_ETH_MAC_SetPTPAlarm()
* - nanoseconds initializazion
* - added polling to wait for setup
*
* 2017-04-04:
* - Changed XMC_ETH_MAC_Init() to disable MMC IPC receive interrupt events
*
* 2017-04-11:
* - Fixed XMC_ETH_MAC_SetPTPAlarm() nanoseconds conversion
*
* 2017-04-17:
* - Changed XMC_ETH_MAC_GetTxTimeStamp() and XMC_ETH_MAC_GetRxTimeStamp() return the timestamp depending on status bit in descriptor
*
* @endcond
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include <xmc_eth_mac.h>
#if defined (ETH0)
#include <stdlib.h>
#include <xmc_scu.h>
/*******************************************************************************
* MACROS
*******************************************************************************/
/**
* ETH MAC clock speed
*/
#define XMC_ETH_MAC_CLK_SPEED_35MHZ (35000000U) /**< ETH MAC clock speed 35 MHZ */
#define XMC_ETH_MAC_CLK_SPEED_60MHZ (60000000U) /**< ETH MAC clock speed 60 MHZ */
#define XMC_ETH_MAC_CLK_SPEED_100MHZ (100000000U) /**< ETH MAC clock speed 100 MHZ */
#define XMC_ETH_MAC_CLK_SPEED_150MHZ (150000000U) /**< ETH MAC clock speed 150 MHZ */
#define XMC_ETH_MAC_CLK_SPEED_200MHZ (200000000U) /**< ETH MAC clock speed 200 MHZ */
#define XMC_ETH_MAC_CLK_SPEED_250MHZ (250000000U) /**< ETH MAC clock speed 250 MHZ */
/**
* ETH MAC MDC divider
*/
#define XMC_ETH_MAC_MDC_DIVIDER_16 (2U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/16 */
#define XMC_ETH_MAC_MDC_DIVIDER_26 (3U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/26 */
#define XMC_ETH_MAC_MDC_DIVIDER_42 (0U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/42 */
#define XMC_ETH_MAC_MDC_DIVIDER_62 (1U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/62 */
#define XMC_ETH_MAC_MDC_DIVIDER_102 (4U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/102 */
#define XMC_ETH_MAC_MDC_DIVIDER_124 (5U << ETH_GMII_ADDRESS_CR_Pos) /**< MDC clock: ETH clock/124 */
/**
* RDES1 Descriptor RX Packet Control
*/
#define ETH_MAC_DMA_RDES1_RBS2 (0x1FFF0000U) /**< Receive buffer 2 size */
#define ETH_MAC_DMA_RDES1_RER (0x00008000U) /**< Receive end of ring */
#define ETH_MAC_DMA_RDES1_RCH (0x00004000U) /**< Second address chained */
#define ETH_MAC_DMA_RDES1_RBS1 (0x00001FFFU) /**< Receive buffer 1 size */
/**
* Interrupt masking
*/
#define ETH_MAC_DISABLE_MMC_INTERRUPT_MSK (0x03ffffffU) /**< Bit mask to disable MMMC transmit and receive interrupts */
#define ETH_MAC_DISABLE_MMC_IPC_RECEIVE_INTERRUPT_MSK (0x3fff3fffU) /**< Bit mask to disable MMC IPC Receive Checksum Offload Interrupt Mask */
/**
* Normal MAC events
*/
#define ETH_MAC_EVENT_NORMAL (XMC_ETH_MAC_EVENT_TRANSMIT |\
XMC_ETH_MAC_EVENT_TRANSMIT_BUFFER_UNAVAILABLE |\
XMC_ETH_MAC_EVENT_RECEIVE |\
XMC_ETH_MAC_EVENT_EARLY_RECEIVE)
/**
* Abnormal MAC events
*/
#define ETH_MAC_EVENT_ABNORMAL (XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED |\
XMC_ETH_MAC_EVENT_TRANSMIT_JABBER_TIMEOUT |\
XMC_ETH_MAC_EVENT_RECEIVE_OVERFLOW |\
XMC_ETH_MAC_EVENT_TRANSMIT_UNDERFLOW |\
XMC_ETH_MAC_EVENT_RECEIVE_BUFFER_UNAVAILABLE |\
XMC_ETH_MAC_EVENT_RECEIVE_PROCESS_STOPPED |\
XMC_ETH_MAC_EVENT_RECEIVE_WATCHDOG_TIMEOUT |\
XMC_ETH_MAC_EVENT_EARLY_TRANSMIT |\
XMC_ETH_MAC_EVENT_BUS_ERROR)
/* Definition needed in case of device header file previous to v1.5.1*/
#ifndef ETH_BUS_MODE_ATDS_Msk
#define ETH_BUS_MODE_ATDS_Msk (0x00000080UL)
#endif
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
/* Check if the event passed is a normal event */
__STATIC_INLINE bool XCM_ETH_MAC_IsNormalEvent(uint32_t event)
{
return (bool)((event & ((uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT |
(uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_BUFFER_UNAVAILABLE |
(uint32_t)XMC_ETH_MAC_EVENT_RECEIVE |
(uint32_t)XMC_ETH_MAC_EVENT_EARLY_RECEIVE)) != (uint32_t)0);
}
/* Check if the event passed is an abnormal event */
__STATIC_INLINE bool XCM_ETH_MAC_IsAbnormalEvent(uint32_t event)
{
return (bool)((event & ((uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED |
(uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_JABBER_TIMEOUT |
(uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_OVERFLOW |
(uint32_t)XMC_ETH_MAC_EVENT_TRANSMIT_UNDERFLOW |
(uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_BUFFER_UNAVAILABLE |
(uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_PROCESS_STOPPED |
(uint32_t)XMC_ETH_MAC_EVENT_RECEIVE_WATCHDOG_TIMEOUT |
(uint32_t)XMC_ETH_MAC_EVENT_EARLY_TRANSMIT |
(uint32_t)XMC_ETH_MAC_EVENT_BUS_ERROR)) != (uint32_t)0);
}
#ifdef XMC_ASSERT_ENABLE
/* Check if the passed argument is a valid ETH module */
__STATIC_INLINE bool XMC_ETH_MAC_IsValidModule(ETH_GLOBAL_TypeDef *const eth)
{
return (eth == ETH0);
}
#endif
/* ETH MAC initialize */
XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_Init(XMC_ETH_MAC_t *const eth_mac)
{
XMC_ETH_MAC_STATUS_t status;
XMC_ASSERT("XMC_ETH_MAC_Init: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
XMC_ETH_MAC_Enable(eth_mac);
XMC_ETH_MAC_Reset(eth_mac);
status = XMC_ETH_MAC_SetManagmentClockDivider(eth_mac);
XMC_ETH_MAC_SetAddress(eth_mac, eth_mac->address);
/* Initialize MAC configuration */
eth_mac->regs->MAC_CONFIGURATION = (uint32_t)ETH_MAC_CONFIGURATION_IPC_Msk;
/* Initialize Filter registers */
eth_mac->regs->FLOW_CONTROL = ETH_FLOW_CONTROL_DZPQ_Msk; /* Disable Zero Quanta Pause */
eth_mac->regs->OPERATION_MODE = (uint32_t)ETH_OPERATION_MODE_RSF_Msk |
(uint32_t)ETH_OPERATION_MODE_TSF_Msk |
(uint32_t)ETH_OPERATION_MODE_OSF_Msk;
/* Increase enhanced descriptor to 8 WORDS, required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled */
eth_mac->regs->BUS_MODE = (uint32_t)ETH_BUS_MODE_ATDS_Msk |
(uint32_t)ETH_BUS_MODE_AAL_Msk | /* the AHB interface generates all bursts aligned to the start address LS bits */
(uint32_t)ETH_BUS_MODE_FB_Msk | /* DMA attempts to execute fixed-length Burst transfers on the AHB Master interface */
(uint32_t)(0x20 << ETH_BUS_MODE_PBL_Pos); /* maximum Burst length */
/* Initialize DMA Descriptors */
XMC_ETH_MAC_InitRxDescriptors(eth_mac);
XMC_ETH_MAC_InitTxDescriptors(eth_mac);
/* Clear interrupts */
eth_mac->regs->STATUS = 0xFFFFFFFFUL;
/* Disable MMC interrupt events */
eth_mac->regs->MMC_TRANSMIT_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_INTERRUPT_MSK;
eth_mac->regs->MMC_RECEIVE_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_INTERRUPT_MSK;
eth_mac->regs->MMC_IPC_RECEIVE_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_IPC_RECEIVE_INTERRUPT_MSK;
/* Disable PMT and timestamp interrupt events */
eth_mac->regs->INTERRUPT_MASK = ETH_INTERRUPT_MASK_PMTIM_Msk | ETH_INTERRUPT_MASK_TSIM_Msk;
eth_mac->frame_end = NULL;
return status;
}
/* Initialize RX descriptors */
void XMC_ETH_MAC_InitRxDescriptors(XMC_ETH_MAC_t *const eth_mac)
{
uint32_t i;
uint32_t next;
XMC_ASSERT("XMC_ETH_MAC_InitRxDescriptors: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
/*
* Chained structure (ETH_MAC_DMA_RDES1_RCH), second address in the descriptor
* (buffer2) is the next descriptor address
*/
for (i = 0U; i < eth_mac->num_rx_buf; ++i)
{
eth_mac->rx_desc[i].status = (uint32_t)ETH_MAC_DMA_RDES0_OWN;
eth_mac->rx_desc[i].length = (uint32_t)ETH_MAC_DMA_RDES1_RCH | (uint32_t)XMC_ETH_MAC_BUF_SIZE;
eth_mac->rx_desc[i].buffer1 = (uint32_t)&(eth_mac->rx_buf[i * XMC_ETH_MAC_BUF_SIZE]);
next = i + 1U;
if (next == eth_mac->num_rx_buf)
{
next = 0U;
}
eth_mac->rx_desc[i].buffer2 = (uint32_t)&(eth_mac->rx_desc[next]);
}
eth_mac->regs->RECEIVE_DESCRIPTOR_LIST_ADDRESS = (uint32_t)&(eth_mac->rx_desc[0]);
eth_mac->rx_index = 0U;
}
/* Initialize TX descriptors */
void XMC_ETH_MAC_InitTxDescriptors(XMC_ETH_MAC_t *const eth_mac)
{
uint32_t i;
uint32_t next;
XMC_ASSERT("XMC_ETH_MAC_InitTxDescriptors: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
/* Chained structure (ETH_MAC_DMA_TDES0_TCH), second address in the descriptor (buffer2) is the next descriptor address */
for (i = 0U; i < eth_mac->num_tx_buf; ++i)
{
eth_mac->tx_desc[i].status = ETH_MAC_DMA_TDES0_TCH | ETH_MAC_DMA_TDES0_LS | ETH_MAC_DMA_TDES0_FS;
eth_mac->tx_desc[i].buffer1 = (uint32_t)&(eth_mac->tx_buf[i * XMC_ETH_MAC_BUF_SIZE]);
next = i + 1U;
if (next == eth_mac->num_tx_buf)
{
next = 0U;
}
eth_mac->tx_desc[i].buffer2 = (uint32_t)&(eth_mac->tx_desc[next]);
}
eth_mac->regs->TRANSMIT_DESCRIPTOR_LIST_ADDRESS = (uint32_t)&(eth_mac->tx_desc[0]);
eth_mac->tx_index = 0U;
}
/* Set address perfect filter */
void XMC_ETH_MAC_SetAddressPerfectFilter(XMC_ETH_MAC_t *const eth_mac,
uint8_t index,
const uint64_t addr,
uint32_t flags)
{
__IO uint32_t *reg;
XMC_ASSERT("XMC_ETH_MAC_SetAddressPerfectFilter: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
XMC_ASSERT("XMC_ETH_MAC_SetAddressFilter: index is out of range", ((index > 0) && (index < 4)));
reg = &(eth_mac->regs->MAC_ADDRESS0_HIGH);
reg[index] = (uint32_t)(addr >> 32U) | flags;
reg[index + 1U] = (uint32_t)addr;
}
/* Set address hash filter */
void XMC_ETH_MAC_SetAddressHashFilter(XMC_ETH_MAC_t *const eth_mac, const uint64_t hash)
{
eth_mac->regs->HASH_TABLE_HIGH = (uint32_t)(hash >> 32);
eth_mac->regs->HASH_TABLE_LOW = (uint32_t)hash;
}
/* Send frame */
XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SendFrame(XMC_ETH_MAC_t *const eth_mac, const uint8_t *frame, uint32_t len, uint32_t flags)
{
XMC_ETH_MAC_STATUS_t status;
uint8_t *dst;
uint32_t ctrl;
XMC_ASSERT("XMC_ETH_MAC_SendFrame:", eth_mac != NULL);
XMC_ASSERT("XMC_ETH_MAC_SendFrame:", eth_mac->regs == ETH0);
XMC_ASSERT("XMC_ETH_MAC_SendFrame:", (frame != NULL) && (len > 0));
dst = eth_mac->frame_end;
if (eth_mac->tx_desc[eth_mac->tx_index].status & ETH_MAC_DMA_TDES0_OWN)
{
/* Transmitter is busy, wait */
status = XMC_ETH_MAC_STATUS_BUSY;
if (eth_mac->regs->STATUS & ETH_STATUS_TU_Msk)
{
/* Receive buffer unavailable, resume DMA */
eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_TU_Msk;
eth_mac->regs->TRANSMIT_POLL_DEMAND = 0U;
}
}
else
{
if (dst == NULL)
{
/* Start of a new transmit frame */
dst = (uint8_t *)eth_mac->tx_desc[eth_mac->tx_index].buffer1;
eth_mac->tx_desc[eth_mac->tx_index].length = len;
}
else
{
/* Sending data fragments in progress */
eth_mac->tx_desc[eth_mac->tx_index].length += len;
}
memcpy(dst, frame, len);
if (flags & (uint32_t)XMC_ETH_MAC_TX_FRAME_FRAGMENT)
{
/* More data to come, remember current write position */
eth_mac->frame_end = dst;
}
else
{
/* Frame is now ready, send it to DMA */
ctrl = eth_mac->tx_desc[eth_mac->tx_index].status | ETH_MAC_DMA_TDES0_CIC;
ctrl &= ~(ETH_MAC_DMA_TDES0_IC | ETH_MAC_DMA_TDES0_TTSE);
if (flags & (uint32_t)XMC_ETH_MAC_TX_FRAME_EVENT)
{
ctrl |= ETH_MAC_DMA_TDES0_IC;
}
if (flags & (uint32_t)XMC_ETH_MAC_TX_FRAME_TIMESTAMP)
{
ctrl |= ETH_MAC_DMA_TDES0_TTSE;
}
eth_mac->tx_ts_index = eth_mac->tx_index;
eth_mac->tx_desc[eth_mac->tx_index].status = ctrl | ETH_MAC_DMA_TDES0_OWN;
eth_mac->tx_index++;
if (eth_mac->tx_index == eth_mac->num_tx_buf)
{
eth_mac->tx_index = 0U;
}
eth_mac->frame_end = NULL;
/* Start frame transmission */
eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_TPS_Msk;
eth_mac->regs->TRANSMIT_POLL_DEMAND = 0U;
}
status = XMC_ETH_MAC_STATUS_OK;
}
return status;
}
/* Read frame */
uint32_t XMC_ETH_MAC_ReadFrame(XMC_ETH_MAC_t *const eth_mac, uint8_t *frame, uint32_t len)
{
uint8_t const *src;
XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", eth_mac != NULL);
XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", eth_mac->regs == ETH0);
XMC_ASSERT("XMC_ETH_MAC_ReadFrame:", (frame != NULL) && (len > 0));
/* Fast-copy data to packet buffer */
src = (uint8_t const *)eth_mac->rx_desc[eth_mac->rx_index].buffer1;
memcpy(frame, src, len);
/* Return this block back to DMA */
eth_mac->rx_desc[eth_mac->rx_index].status = ETH_MAC_DMA_RDES0_OWN;
eth_mac->rx_index++;
if (eth_mac->rx_index == eth_mac->num_rx_buf)
{
eth_mac->rx_index = 0U;
}
if (eth_mac->regs->STATUS & ETH_STATUS_RU_Msk)
{
/* Receive buffer unavailable, resume DMA */
eth_mac->regs->STATUS = (uint32_t)ETH_STATUS_RU_Msk;
eth_mac->regs->RECEIVE_POLL_DEMAND = 0U;
}
return (len);
}
/* Get RX frame size */
uint32_t XMC_ETH_MAC_GetRxFrameSize(XMC_ETH_MAC_t *const eth_mac)
{
uint32_t status;
uint32_t len = 0U;
status = eth_mac->rx_desc[eth_mac->rx_index].status;
if (status & ETH_MAC_DMA_RDES0_OWN)
{
/* Owned by DMA */
len = 0U;
}
else if (((status & ETH_MAC_DMA_RDES0_ES) != 0U) ||
((status & ETH_MAC_DMA_RDES0_FS) == 0U) ||
((status & ETH_MAC_DMA_RDES0_LS) == 0U))
{
/* Error, this block is invalid */
len = 0xFFFFFFFFU;
}
else
{
/* Subtract CRC */
len = ((status & ETH_MAC_DMA_RDES0_FL) >> 16U) - 4U;
}
return len;
}
/* Set management clock divider */
XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_SetManagmentClockDivider(XMC_ETH_MAC_t *const eth_mac)
{
uint32_t eth_mac_clk;
XMC_ETH_MAC_STATUS_t status;
__IO uint32_t *reg;
eth_mac_clk = XMC_SCU_CLOCK_GetEthernetClockFrequency();
status = XMC_ETH_MAC_STATUS_OK;
reg = &(eth_mac->regs->GMII_ADDRESS);
if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_35MHZ)
{
*reg = XMC_ETH_MAC_MDC_DIVIDER_16;
}
else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_60MHZ)
{
*reg = XMC_ETH_MAC_MDC_DIVIDER_26;
}
else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_100MHZ)
{
*reg = XMC_ETH_MAC_MDC_DIVIDER_42;
}
else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_150MHZ)
{
*reg = XMC_ETH_MAC_MDC_DIVIDER_62;
}
else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_200MHZ)
{
*reg = XMC_ETH_MAC_MDC_DIVIDER_102;
}
else if (eth_mac_clk <= XMC_ETH_MAC_CLK_SPEED_250MHZ)
{
*reg = XMC_ETH_MAC_MDC_DIVIDER_124;
}
else
{
status = XMC_ETH_MAC_STATUS_ERROR;
}
return status;
}
/* ETH MAC enable */
void XMC_ETH_MAC_Enable(XMC_ETH_MAC_t *const eth_mac)
{
XMC_UNUSED_ARG(eth_mac);
XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_ETH);
#if UC_DEVICE != XMC4500
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ETH0);
#endif
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ETH0);
}
/* ETH MAC disable */
void XMC_ETH_MAC_Disable(XMC_ETH_MAC_t *const eth_mac)
{
XMC_UNUSED_ARG(eth_mac);
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_ETH0);
#if UC_DEVICE != XMC4500
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_ETH0);
#endif
XMC_SCU_CLOCK_DisableClock(XMC_SCU_CLOCK_ETH);
}
/* Read physical layer and obtain status */
XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_ReadPhy(XMC_ETH_MAC_t *eth_mac, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
{
uint32_t retries;
XMC_ASSERT("XMC_ETH_MAC_PhyRead: Parameter error", data != NULL);
eth_mac->regs->GMII_ADDRESS = (uint32_t)((eth_mac->regs->GMII_ADDRESS & (uint32_t)ETH_GMII_ADDRESS_CR_Msk) |
(uint32_t)ETH_GMII_ADDRESS_MB_Msk |
(uint32_t)((uint32_t)phy_addr << ETH_GMII_ADDRESS_PA_Pos) |
(uint32_t)((uint32_t)reg_addr << ETH_GMII_ADDRESS_MR_Pos));
/* Poll busy bit during max PHY_TIMEOUT time */
retries = 0U;
do
{
if ((eth_mac->regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) == 0U)
{
*data = (uint16_t)(eth_mac->regs->GMII_DATA & ETH_GMII_DATA_MD_Msk);
return XMC_ETH_MAC_STATUS_OK;
}
++retries;
} while (retries < XMC_ETH_MAC_PHY_MAX_RETRIES);
return XMC_ETH_MAC_STATUS_ERROR;
}
/* Write physical layer and return status */
XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_WritePhy(XMC_ETH_MAC_t *eth_mac, uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
{
uint32_t retries;
eth_mac->regs->GMII_DATA = data;
eth_mac->regs->GMII_ADDRESS = (uint32_t)((eth_mac->regs->GMII_ADDRESS & (uint32_t)ETH_GMII_ADDRESS_CR_Msk) |
(uint32_t)ETH_GMII_ADDRESS_MB_Msk |
(uint32_t)ETH_GMII_ADDRESS_MW_Msk |
(uint32_t)((uint32_t)phy_addr << ETH_GMII_ADDRESS_PA_Pos) |
(uint32_t)((uint32_t)reg_addr << ETH_GMII_ADDRESS_MR_Pos));
/* Poll busy bit during max PHY_TIMEOUT time */
retries = 0U;
do
{
if ((eth_mac->regs->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) == 0U)
{
return XMC_ETH_MAC_STATUS_OK;
}
++retries;
} while (retries < XMC_ETH_MAC_PHY_MAX_RETRIES);
return XMC_ETH_MAC_STATUS_ERROR;
}
/* Flush TX */
void XMC_ETH_MAC_FlushTx(XMC_ETH_MAC_t *const eth_mac)
{
eth_mac->regs->OPERATION_MODE &= (uint32_t)~ETH_OPERATION_MODE_ST_Msk;
XMC_ETH_MAC_InitTxDescriptors(eth_mac);
eth_mac->regs->OPERATION_MODE |= (uint32_t)ETH_OPERATION_MODE_ST_Msk;
}
/* Flush RX */
void XMC_ETH_MAC_FlushRx(XMC_ETH_MAC_t *const eth_mac)
{
eth_mac->regs->OPERATION_MODE &= (uint32_t)~ETH_OPERATION_MODE_SR_Msk;
XMC_ETH_MAC_InitRxDescriptors(eth_mac);
eth_mac->regs->OPERATION_MODE |= (uint32_t)ETH_OPERATION_MODE_SR_Msk;
}
/* Set wakeup frame filter */
void XMC_ETH_MAC_SetWakeUpFrameFilter(XMC_ETH_MAC_t *const eth_mac,
const uint32_t (*const filter)[XMC_ETH_WAKEUP_REGISTER_LENGTH])
{
uint32_t i = 0U;
/* Fill Remote Wake-up frame filter register with buffer data */
for (i = 0U; i < XMC_ETH_WAKEUP_REGISTER_LENGTH; i++)
{
/* Write each time to the same register */
eth_mac->regs->REMOTE_WAKE_UP_FRAME_FILTER = (*filter)[i];
}
}
/* Enable event */
void XMC_ETH_MAC_EnableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event)
{
XMC_ASSERT("XMC_ETH_MAC_EnableDMAEvent: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
eth_mac->regs->INTERRUPT_MASK &= ~(event >> 16U);
event &= (uint16_t)0x7fffU;
if (XCM_ETH_MAC_IsNormalEvent(event))
{
event |= (uint32_t)ETH_INTERRUPT_ENABLE_NIE_Msk;
}
if (XCM_ETH_MAC_IsAbnormalEvent(event))
{
event |= (uint32_t)ETH_INTERRUPT_ENABLE_AIE_Msk;
}
eth_mac->regs->INTERRUPT_ENABLE |= event;
}
/* Disable event */
void XMC_ETH_MAC_DisableEvent(XMC_ETH_MAC_t *const eth_mac, uint32_t event)
{
XMC_ASSERT("XMC_ETH_MAC_DisableDMAEvent: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
eth_mac->regs->INTERRUPT_MASK |= event >> 16U;
event &= 0x7fffU;
eth_mac->regs->INTERRUPT_ENABLE &= ~event;
}
/* Clear event status */
void XMC_ETH_MAC_ClearEventStatus(XMC_ETH_MAC_t *const eth_mac, uint32_t event)
{
XMC_ASSERT("XMC_ETH_MAC_ClearEventStatus: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
if ((eth_mac->regs->STATUS & ETH_STATUS_NIS_Msk) != 0U)
{
event |= (uint32_t)ETH_STATUS_NIS_Msk;
}
if ((eth_mac->regs->STATUS & ETH_STATUS_AIS_Msk) != 0U)
{
event |= (uint32_t)ETH_STATUS_AIS_Msk;
}
eth_mac->regs->STATUS = event & 0x0001FFFFU;
}
/* Obtain event status */
uint32_t XMC_ETH_MAC_GetEventStatus(const XMC_ETH_MAC_t *const eth_mac)
{
uint32_t temp_status = 0;
XMC_ASSERT("XMC_ETH_MAC_GetEventStatus: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
temp_status = (eth_mac->regs->STATUS & (uint32_t)0x7ffUL);
return ((uint32_t)((eth_mac->regs->INTERRUPT_STATUS & (ETH_INTERRUPT_MASK_PMTIM_Msk | ETH_INTERRUPT_MASK_TSIM_Msk)) << 16U) |
temp_status);
}
/* Return RX descriptor */
void XMC_ETH_MAC_ReturnRxDescriptor(XMC_ETH_MAC_t *const eth_mac)
{
eth_mac->rx_desc[eth_mac->rx_index].status |= ETH_MAC_DMA_RDES0_OWN;
eth_mac->rx_index++;
if (eth_mac->rx_index == eth_mac->num_rx_buf)
{
eth_mac->rx_index = 0U;
}
}
/* Return TX descriptor */
void XMC_ETH_MAC_ReturnTxDescriptor(XMC_ETH_MAC_t *const eth_mac)
{
eth_mac->tx_ts_index = eth_mac->tx_index;
eth_mac->tx_desc[eth_mac->tx_index].status |= ETH_MAC_DMA_TDES0_CIC |ETH_MAC_DMA_TDES0_OWN;
eth_mac->tx_index++;
if (eth_mac->tx_index == eth_mac->num_tx_buf)
{
eth_mac->tx_index = 0U;
}
eth_mac->frame_end = NULL;
}
/* Set VLAN tag */
void XMC_ETH_MAC_SetVLANTag(XMC_ETH_MAC_t *const eth_mac, uint16_t tag)
{
XMC_ASSERT("XMC_ETH_MAC_SetVLANTag: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
eth_mac->regs->VLAN_TAG = (uint32_t)tag;
}
/* Initialize PTP */
void XMC_ETH_MAC_InitPTP(XMC_ETH_MAC_t *const eth_mac, uint32_t config)
{
XMC_ASSERT("XMC_ETH_MAC_InitPTP: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
/* Mask the time stamp interrupt */
eth_mac->regs->INTERRUPT_MASK |= (uint32_t)ETH_INTERRUPT_MASK_TSIM_Msk;
/* Enable time stamp */
eth_mac->regs->TIMESTAMP_CONTROL = ETH_TIMESTAMP_CONTROL_TSENA_Msk;
/* Program sub-second increment register based on PTP clock frequency = fSYS/2 */
/* the nanoseconds register has a resolution of ~0.465ns. */
eth_mac->regs->SUB_SECOND_INCREMENT = (uint32_t)((0x80000000U / (float)(XMC_SCU_CLOCK_GetSystemClockFrequency() / 2)) + 0.5F);
if ((config & (uint32_t)XMC_ETH_MAC_TIMESTAMP_CONFIG_FINE_UPDATE) != 0U)
{
/* Program addend register to obtain fSYS/2 from reference clock (fSYS) */
eth_mac->regs->TIMESTAMP_ADDEND = (uint32_t)0x80000000U;
/* Addend register update */
eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk;
/* Poll the Timestamp Control register until the bit TSADDREG is cleared */
while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk);
}
eth_mac->regs->TIMESTAMP_CONTROL |= config | (uint32_t)ETH_TIMESTAMP_CONTROL_TSINIT_Msk;
while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk);
}
/* Initialize PTP using a given time */
void XMC_ETH_MAC_InitPTPEx(XMC_ETH_MAC_t *const eth_mac, uint32_t config, XMC_ETH_MAC_TIME_t *const time)
{
XMC_ASSERT("XMC_ETH_MAC_InitPTP: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
/* Mask the time stamp interrupt */
eth_mac->regs->INTERRUPT_MASK |= (uint32_t)ETH_INTERRUPT_MASK_TSIM_Msk;
/* Enable time stamp */
eth_mac->regs->TIMESTAMP_CONTROL = ETH_TIMESTAMP_CONTROL_TSENA_Msk;
/* Program sub-second increment register based on PTP clock frequency = fSYS/2 */
/* the nanoseconds register has a resolution of ~0.465ns. */
eth_mac->regs->SUB_SECOND_INCREMENT = (uint32_t)((0x80000000U / (float)(XMC_SCU_CLOCK_GetSystemClockFrequency() / 2)) + 0.5F);
if ((config & (uint32_t)XMC_ETH_MAC_TIMESTAMP_CONFIG_FINE_UPDATE) != 0U)
{
/* Program addend register to obtain fSYS/2 from reference clock (fSYS) */
eth_mac->regs->TIMESTAMP_ADDEND = (uint32_t)0x80000000U;
/* Addend register update */
eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk;
/* Poll the Timestamp Control register until the bit TSADDREG is cleared */
while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk);
}
/* Initialize the system time */
eth_mac->regs->SYSTEM_TIME_NANOSECONDS_UPDATE = time->nanoseconds;
eth_mac->regs->SYSTEM_TIME_SECONDS_UPDATE = time->seconds;
eth_mac->regs->TIMESTAMP_CONTROL |= config | (uint32_t)ETH_TIMESTAMP_CONTROL_TSINIT_Msk;
while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk);
}
/* Get PTP time */
void XMC_ETH_MAC_GetPTPTime(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time)
{
XMC_ASSERT("XMC_ETH_MAC_GetPTPTime: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
time->nanoseconds = (uint32_t)(eth_mac->regs->SYSTEM_TIME_NANOSECONDS * (1000000000.0F / 0x80000000U)); /* accuracy of 0.46 ns */
time->seconds = eth_mac->regs->SYSTEM_TIME_SECONDS;
}
/* Set PTP time */
void XMC_ETH_MAC_SetPTPTime(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time)
{
XMC_ASSERT("XMC_ETH_MAC_GetPTPTime: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
eth_mac->regs->SYSTEM_TIME_SECONDS_UPDATE = time->seconds;
eth_mac->regs->SYSTEM_TIME_NANOSECONDS_UPDATE = time->nanoseconds;
/* Initialize precision timer */
ETH0->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSINIT_Msk;
while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk);
}
/* Update PTP time */
void XMC_ETH_MAC_UpdatePTPTime(XMC_ETH_MAC_t *const eth_mac, const XMC_ETH_MAC_TIME_t *const time)
{
uint32_t temp;
XMC_ASSERT("XMC_ETH_MAC_UpdatePTPTime: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
XMC_ASSERT("XMC_ETH_MAC_UpdatePTPTime: time.time_stamp_nanoseconds not in range", (time->nanoseconds < 1000000000.0F));
temp = (uint32_t)(abs(time->nanoseconds) * (0x80000000U / 1000000000.0F));
if (time->nanoseconds < 0)
{
temp |= (uint32_t)ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Msk;
}
eth_mac->regs->SYSTEM_TIME_NANOSECONDS_UPDATE = temp;
eth_mac->regs->SYSTEM_TIME_SECONDS_UPDATE = time->seconds;
eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSUPDT_Msk;
}
/* Set PTP alarm */
void XMC_ETH_MAC_SetPTPAlarm(XMC_ETH_MAC_t *const eth_mac, const XMC_ETH_MAC_TIME_t *const time)
{
XMC_ASSERT("XMC_ETH_MAC_SetPTPAlarm: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
XMC_ASSERT("XMC_ETH_MAC_SetPTPAlarm: time.time_stamp_nanoseconds not in range", (time->nanoseconds < 1000000000.0F));
eth_mac->regs->TARGET_TIME_NANOSECONDS = (uint32_t)(time->nanoseconds * (0x80000000U / 1000000000.0F));
eth_mac->regs->TARGET_TIME_SECONDS = time->seconds;
}
/* Adjust PTP clock */
void XMC_ETH_MAC_AdjustPTPClock(XMC_ETH_MAC_t *const eth_mac, uint32_t correction)
{
XMC_ASSERT("XMC_ETH_MAC_AdjustPTPClock: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
/* Correction factor is Q31 (0x80000000 = 1.000000000) */
eth_mac->regs->TIMESTAMP_ADDEND = (uint32_t)(((uint64_t)correction * eth_mac->regs->TIMESTAMP_ADDEND) >> 31U);
/* Update addend register */
eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk;
/* Poll the Timestamp Control register until the bit TSADDREG is cleared */
while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk);
}
/* Update Addend */
void XMC_ETH_MAC_UpdateAddend(XMC_ETH_MAC_t *const eth_mac, uint32_t addend)
{
XMC_ASSERT("XMC_ETH_MAC_AdjustPTPClock: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
eth_mac->regs->TIMESTAMP_ADDEND = addend;
/* Update addend register */
eth_mac->regs->TIMESTAMP_CONTROL |= (uint32_t)ETH_TIMESTAMP_CONTROL_TSADDREG_Msk;
/* Poll the Timestamp Control register until the bit TSADDREG is cleared */
while (eth_mac->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk);
}
/* Set PTP status */
uint32_t XMC_ETH_MAC_GetPTPStatus(const XMC_ETH_MAC_t *const eth_mac)
{
XMC_ASSERT("XMC_ETH_MAC_GetPTPStatus: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
return (eth_mac->regs->TIMESTAMP_STATUS);
}
/* Get TX time-stamp */
XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_GetRxTimeStamp(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time)
{
XMC_ETH_MAC_DMA_DESC_t *rx_desc;
XMC_ETH_MAC_STATUS_t status;
XMC_ASSERT("XMC_ETH_MAC_GetRxTimeStamp: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
XMC_ASSERT("XMC_ETH_MAC_GetRxTimeStamp: time is invalid", time != NULL);
rx_desc = &eth_mac->rx_desc[eth_mac->rx_index];
if (rx_desc->status & ETH_MAC_DMA_RDES0_OWN)
{
status = XMC_ETH_MAC_STATUS_BUSY;
}
else
{
if ((rx_desc->status & (ETH_MAC_DMA_RDES0_TSA | ETH_MAC_DMA_RDES0_LS)) == (ETH_MAC_DMA_RDES0_TSA | ETH_MAC_DMA_RDES0_LS))
{
time->nanoseconds = (int32_t)rx_desc->time_stamp_nanoseconds;
time->seconds = rx_desc->time_stamp_seconds;
status = XMC_ETH_MAC_STATUS_OK;
}
else
{
status = XMC_ETH_MAC_STATUS_ERROR;
}
}
return status;
}
/* Get TX time-stamp */
XMC_ETH_MAC_STATUS_t XMC_ETH_MAC_GetTxTimeStamp(XMC_ETH_MAC_t *const eth_mac, XMC_ETH_MAC_TIME_t *const time)
{
XMC_ETH_MAC_DMA_DESC_t *tx_desc;
XMC_ETH_MAC_STATUS_t status;
XMC_ASSERT("XMC_ETH_MAC_GetTxTimeStamp: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs));
XMC_ASSERT("XMC_ETH_MAC_GetTxTimeStamp: time is invalid", time != NULL);
tx_desc = &eth_mac->tx_desc[eth_mac->tx_ts_index];
if (tx_desc->status & ETH_MAC_DMA_TDES0_OWN)
{
status = XMC_ETH_MAC_STATUS_BUSY;
}
else
{
if ((tx_desc->status & (ETH_MAC_DMA_TDES0_TTSS | ETH_MAC_DMA_TDES0_LS)) == (ETH_MAC_DMA_TDES0_TTSS | ETH_MAC_DMA_TDES0_LS))
{
time->nanoseconds = (int32_t)tx_desc->time_stamp_nanoseconds;
time->seconds = tx_desc->time_stamp_seconds;
status = XMC_ETH_MAC_STATUS_OK;
}
else
{
status = XMC_ETH_MAC_STATUS_ERROR;
}
}
return status;
}
#endif

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/**
* @file xmc_eth_phy_dp83848.c
* @date 2015-12-15
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-06-20:
* - Initial <br>
*
* 2015-12-15:
* - Added Reset and exit power down
* - Reset function called in Init function
*
* @endcond
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#if defined(XMC_ETH_PHY_DP83848C)
#include <xmc_eth_phy.h>
/*******************************************************************************
* MACROS
*******************************************************************************/
/* Basic Registers */
#define REG_BMCR (0x00U) /* Basic Mode Control Register */
#define REG_BMSR (0x01U) /* Basic Mode Status Register */
#define REG_PHYIDR1 (0x02U) /* PHY Identifier 1 */
#define REG_PHYIDR2 (0x03U) /* PHY Identifier 2 */
#define REG_ANAR (0x04U) /* Auto-Negotiation Advertisement */
#define REG_ANLPAR (0x05U) /* Auto-Neg. Link Partner Abitily */
#define REG_ANER (0x06U) /* Auto-Neg. Expansion Register */
#define REG_ANNPTR (0x07U) /* Auto-Neg. Next Page TX */
#define REG_RBR (0x17U) /* RMII and Bypass Register */
/* Extended Registers */
#define REG_PHYSTS (0x10U) /* Status Register */
/* Basic Mode Control Register */
#define BMCR_RESET (0x8000U) /* Software Reset */
#define BMCR_LOOPBACK (0x4000U) /* Loopback mode */
#define BMCR_SPEED_SEL (0x2000U) /* Speed Select (1=100Mb/s) */
#define BMCR_ANEG_EN (0x1000U) /* Auto Negotiation Enable */
#define BMCR_POWER_DOWN (0x0800U) /* Power Down */
#define BMCR_ISOLATE (0x0400U) /* Isolate Media interface */
#define BMCR_REST_ANEG (0x0200U) /* Restart Auto Negotiation */
#define BMCR_DUPLEX (0x0100U) /* Duplex Mode (1=Full duplex) */
#define BMCR_COL_TEST (0x0080U) /* Collision Test */
/* Basic Mode Status Register */
#define BMSR_100B_T4 (0x8000U) /* 100BASE-T4 Capable */
#define BMSR_100B_TX_FD (0x4000U) /* 100BASE-TX Full Duplex Capable */
#define BMSR_100B_TX_HD (0x2000U) /* 100BASE-TX Half Duplex Capable */
#define BMSR_10B_T_FD (0x1000U) /* 10BASE-T Full Duplex Capable */
#define BMSR_10B_T_HD (0x0800U) /* 10BASE-T Half Duplex Capable */
#define BMSR_MF_PRE_SUP (0x0040U) /* Preamble suppression Capable */
#define BMSR_ANEG_COMPL (0x0020U) /* Auto Negotiation Complete */
#define BMSR_REM_FAULT (0x0010U) /* Remote Fault */
#define BMSR_ANEG_ABIL (0x0008U) /* Auto Negotiation Ability */
#define BMSR_LINK_STAT (0x0004U) /* Link Status (1=established) */
#define BMSR_JABBER_DET (0x0002U) /* Jaber Detect */
#define BMSR_EXT_CAPAB (0x0001U) /* Extended Capability */
/* RMII and Bypass Register */
#define RBR_RMII_MODE (0x0020U) /* Reduced MII Mode */
/* PHY Identifier Registers */
#define PHY_ID1 0x2000 /* DP83848C Device Identifier MSB */
#define PHY_ID2 0x5C90 /* DP83848C Device Identifier LSB */
/* PHY Status Register */
#define PHYSTS_MDI_X 0x4000 /* MDI-X mode enabled by Auto-Negot. */
#define PHYSTS_REC_ERR 0x2000 /* Receive Error Latch */
#define PHYSTS_POL_STAT 0x1000 /* Polarity Status */
#define PHYSTS_FC_SENSE 0x0800 /* False Carrier Sense Latch */
#define PHYSTS_SIG_DET 0x0400 /* 100Base-TX Signal Detect */
#define PHYSTS_DES_LOCK 0x0200 /* 100Base-TX Descrambler Lock */
#define PHYSTS_PAGE_REC 0x0100 /* Link Code Word Page Received */
#define PHYSTS_MII_INT 0x0080 /* MII Interrupt Pending */
#define PHYSTS_REM_FAULT 0x0040 /* Remote Fault */
#define PHYSTS_JABBER_DET 0x0020 /* Jabber Detect */
#define PHYSTS_ANEG_COMPL 0x0010 /* Auto Negotiation Complete */
#define PHYSTS_LOOPBACK 0x0008 /* Loopback Status */
#define PHYSTS_DUPLEX 0x0004 /* Duplex Status (1=Full duplex) */
#define PHYSTS_SPEED 0x0002 /* Speed10 Status (1=10MBit/s) */
#define PHYSTS_LINK_STAT 0x0001 /* Link Status (1=established) */
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
/* Check if the device identifier is valid */
static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t phy_id1;
uint16_t phy_id2;
XMC_ETH_PHY_STATUS_t status;
/* Check Device Identification. */
if ((XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR1, &phy_id1) == XMC_ETH_MAC_STATUS_OK) &&
(XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR2, &phy_id2) == XMC_ETH_MAC_STATUS_OK))
{
if ((phy_id1 == PHY_ID1) && ((phy_id2 & (uint16_t)0xfff0) == PHY_ID2))
{
status = XMC_ETH_PHY_STATUS_OK;
}
else
{
status = XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID;
}
}
else
{
status = XMC_ETH_PHY_STATUS_ERROR_TIMEOUT;
}
return (int32_t)status;
}
/* PHY initialize */
int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config)
{
int32_t status;
uint16_t reg_val;
status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
status = XMC_ETH_PHY_Reset(eth_mac, phy_addr);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
reg_val = 0U;
if (config->speed == XMC_ETH_LINK_SPEED_100M)
{
reg_val |= BMCR_SPEED_SEL;
}
if (config->duplex == XMC_ETH_LINK_DUPLEX_FULL)
{
reg_val |= BMCR_DUPLEX;
}
if (config->enable_auto_negotiate == true)
{
reg_val |= BMCR_ANEG_EN;
}
if (config->enable_loop_back == true)
{
reg_val |= BMCR_LOOPBACK;
}
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_val);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
/* Configure interface mode */
switch (config->interface)
{
case XMC_ETH_LINK_INTERFACE_MII:
reg_val = 0x0001;
break;
case XMC_ETH_LINK_INTERFACE_RMII:
reg_val = RBR_RMII_MODE | 0x0001;
break;
}
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_RBR, reg_val);
}
}
}
return status;
}
/* Reset */
int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
int32_t status;
uint16_t reg_bmcr;
/* Reset PHY*/
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
/* Wait for the reset to complete */
do
{
status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, &reg_bmcr);
} while ((reg_bmcr & BMCR_RESET) != 0);
}
return status;
}
/* Initiate power down */
int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
int32_t status;
uint16_t reg_bmcr;
status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, &reg_bmcr);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
reg_bmcr |= BMCR_POWER_DOWN;
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
}
return status;
}
/* Exit power down */
int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
int32_t status;
uint16_t reg_bmcr;
status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, &reg_bmcr);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
reg_bmcr &= ~BMCR_POWER_DOWN;
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
}
return status;
}
/* Get link status */
XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t val;
XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val);
return (XMC_ETH_LINK_STATUS_t)((val & BMSR_LINK_STAT) ? XMC_ETH_LINK_STATUS_UP : XMC_ETH_LINK_STATUS_DOWN);
}
/* Get link speed */
XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t val;
XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYSTS, &val);
return (XMC_ETH_LINK_SPEED_t)((val & PHYSTS_SPEED) ? XMC_ETH_LINK_SPEED_10M : XMC_ETH_LINK_SPEED_100M);
}
/* Get link duplex settings */
XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t val;
XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYSTS, &val);
return (XMC_ETH_LINK_DUPLEX_t)((val & PHYSTS_DUPLEX) ? XMC_ETH_LINK_DUPLEX_FULL : XMC_ETH_LINK_DUPLEX_HALF);
}
bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t val;
XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val);
return ((val & BMSR_ANEG_COMPL) == BMSR_ANEG_COMPL);
}
#endif // defined(XMC_ETH_PHY_DP83848C)

267
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/**
* @file xmc_eth_phy_ksz8031ml.c
* @date 2015-12-15
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-06-20:
* - Initial
*
* 2015-12-15:
* - Added Reset and exit power down
* - Reset function called in Init function
*
* @endcond
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#if defined(XMC_ETH_PHY_KSZ8031RNL)
#include <xmc_eth_phy.h>
/*******************************************************************************
* MACROS
*******************************************************************************/
/* Basic Registers */
#define REG_BMCR (0x00U) /* Basic Mode Control Register */
#define REG_BMSR (0x01U) /* Basic Mode Status Register */
#define REG_PHYIDR1 (0x02U) /* PHY Identifier 1 */
#define REG_PHYIDR2 (0x03U) /* PHY Identifier 2 */
#define REG_ANAR (0x04U) /* Auto-Negotiation Advertisement */
#define REG_ANLPAR (0x05U) /* Auto-Neg. Link Partner Abitily */
#define REG_ANER (0x06U) /* Auto-Neg. Expansion Register */
#define REG_ANNPTR (0x07U) /* Auto-Neg. Next Page TX */
/* Extended Registers */
#define REG_PHYCTRL1 (0x1eU) /* PHY control 1 Register */
/* Basic Mode Control Register */
#define BMCR_RESET (0x8000U) /* Software Reset */
#define BMCR_LOOPBACK (0x4000U) /* Loopback mode */
#define BMCR_SPEED_SEL (0x2000U) /* Speed Select (1=100Mb/s) */
#define BMCR_ANEG_EN (0x1000U) /* Auto Negotiation Enable */
#define BMCR_POWER_DOWN (0x0800U) /* Power Down */
#define BMCR_ISOLATE (0x0400U) /* Isolate Media interface */
#define BMCR_REST_ANEG (0x0200U) /* Restart Auto Negotiation */
#define BMCR_DUPLEX (0x0100U) /* Duplex Mode (1=Full duplex) */
#define BMCR_COL_TEST (0x0080U) /* Collision Test */
/* Basic Mode Status Register */
#define BMSR_100B_T4 (0x8000U) /* 100BASE-T4 Capable */
#define BMSR_100B_TX_FD (0x4000U) /* 100BASE-TX Full Duplex Capable */
#define BMSR_100B_TX_HD (0x2000U) /* 100BASE-TX Half Duplex Capable */
#define BMSR_10B_T_FD (0x1000U) /* 10BASE-T Full Duplex Capable */
#define BMSR_10B_T_HD (0x0800U) /* 10BASE-T Half Duplex Capable */
#define BMSR_MF_PRE_SUP (0x0040U) /* Preamble suppression Capable */
#define BMSR_ANEG_COMPL (0x0020U) /* Auto Negotiation Complete */
#define BMSR_REM_FAULT (0x0010U) /* Remote Fault */
#define BMSR_ANEG_ABIL (0x0008U) /* Auto Negotiation Ability */
#define BMSR_LINK_STAT (0x0004U) /* Link Status (1=established) */
#define BMSR_JABBER_DET (0x0002U) /* Jaber Detect */
#define BMSR_EXT_CAPAB (0x0001U) /* Extended Capability */
/* PHY control 1 Register */
#define PHYCTRL1_OPMODE_SPEED (0x0003U)
#define PHYCTRL1_OPMODE_DUPLEX (0x0004U)
/* PHY Identifier Registers */
#define PHY_ID1 (0x0022U) /* KSZ8031 Device Identifier MSB */
#define PHY_ID2 (0x1550U) /* KSZ8031 Device Identifier LSB */
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
/* Check if the device identifier is valid */
static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t phy_id1;
uint16_t phy_id2;
XMC_ETH_PHY_STATUS_t status;
/* Check Device Identification. */
if ((XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR1, &phy_id1) == XMC_ETH_MAC_STATUS_OK) &&
(XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR2, &phy_id2) == XMC_ETH_MAC_STATUS_OK))
{
if ((phy_id1 == PHY_ID1) && ((phy_id2 & (uint16_t)0xfff0) == PHY_ID2))
{
status = XMC_ETH_PHY_STATUS_OK;
}
else
{
status = XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID;
}
}
else
{
status = XMC_ETH_PHY_STATUS_ERROR_TIMEOUT;
}
return (int32_t)status;
}
/* PHY initialize */
int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config)
{
int32_t status;
uint16_t reg_bmcr;
status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
status = XMC_ETH_PHY_Reset(eth_mac, phy_addr);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
reg_bmcr = 0U;
if (config->speed == XMC_ETH_LINK_SPEED_100M)
{
reg_bmcr |= BMCR_SPEED_SEL;
}
if (config->duplex == XMC_ETH_LINK_DUPLEX_FULL)
{
reg_bmcr |= BMCR_DUPLEX;
}
if (config->enable_auto_negotiate == true)
{
reg_bmcr |= BMCR_ANEG_EN;
}
if (config->enable_loop_back == true)
{
reg_bmcr |= BMCR_LOOPBACK;
}
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
}
}
return status;
}
/* Reset */
int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
int32_t status;
uint16_t reg_bmcr;
/* Reset PHY*/
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
/* Wait for the reset to complete */
do
{
status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, &reg_bmcr);
} while ((reg_bmcr & BMCR_RESET) != 0);
}
return status;
}
/* Initiate power down */
int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
int32_t status;
uint16_t reg_bmcr;
status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, &reg_bmcr);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
reg_bmcr |= BMCR_POWER_DOWN;
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
}
return status;
}
/* Exit power down */
int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
int32_t status;
uint16_t reg_bmcr;
status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, &reg_bmcr);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
reg_bmcr &= ~BMCR_POWER_DOWN;
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
}
return status;
}
/* Get link status */
XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t val;
XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val);
return (XMC_ETH_LINK_STATUS_t)((val & BMSR_LINK_STAT) ? XMC_ETH_LINK_STATUS_UP : XMC_ETH_LINK_STATUS_DOWN);
}
/* Get link speed */
XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t val;
XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val);
return (XMC_ETH_LINK_SPEED_t)(((val & PHYCTRL1_OPMODE_SPEED) - 1U) ? XMC_ETH_LINK_SPEED_100M : XMC_ETH_LINK_SPEED_10M);
}
/* Get link duplex settings */
XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t val;
XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val);
return (XMC_ETH_LINK_DUPLEX_t)((val & PHYCTRL1_OPMODE_DUPLEX) ? XMC_ETH_LINK_DUPLEX_FULL : XMC_ETH_LINK_DUPLEX_HALF);
}
bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t val;
XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val);
return ((val & BMSR_ANEG_COMPL) == BMSR_ANEG_COMPL);
}
#endif // defined(XMC_ETH_PHY_KSZ8031RNL)

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/**
* @file xmc_eth_phy_ksz8081rnb.c
* @date 2015-12-15
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-06-20:
* - Initial
*
* 2015-12-15:
* - Added Reset and exit power down
* - Reset function called in Init function
*
* @endcond
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#if defined(XMC_ETH_PHY_KSZ8081RNB)
#include <xmc_eth_phy.h>
/*******************************************************************************
* MACROS
*******************************************************************************/
/* Basic Registers */
#define REG_BMCR (0x00U) /* Basic Mode Control Register */
#define REG_BMSR (0x01U) /* Basic Mode Status Register */
#define REG_PHYIDR1 (0x02U) /* PHY Identifier 1 */
#define REG_PHYIDR2 (0x03U) /* PHY Identifier 2 */
#define REG_ANAR (0x04U) /* Auto-Negotiation Advertisement */
#define REG_ANLPAR (0x05U) /* Auto-Neg. Link Partner Abitily */
#define REG_ANER (0x06U) /* Auto-Neg. Expansion Register */
#define REG_ANNPTR (0x07U) /* Auto-Neg. Next Page TX */
/* Extended Registers */
#define REG_PHYCTRL1 (0x1eU) /* PHY control 1 Register */
/* Basic Mode Control Register */
#define BMCR_RESET (0x8000U) /* Software Reset */
#define BMCR_LOOPBACK (0x4000U) /* Loopback mode */
#define BMCR_SPEED_SEL (0x2000U) /* Speed Select (1=100Mb/s) */
#define BMCR_ANEG_EN (0x1000U) /* Auto Negotiation Enable */
#define BMCR_POWER_DOWN (0x0800U) /* Power Down */
#define BMCR_ISOLATE (0x0400U) /* Isolate Media interface */
#define BMCR_REST_ANEG (0x0200U) /* Restart Auto Negotiation */
#define BMCR_DUPLEX (0x0100U) /* Duplex Mode (1=Full duplex) */
#define BMCR_COL_TEST (0x0080U) /* Collision Test */
/* Basic Mode Status Register */
#define BMSR_100B_T4 (0x8000U) /* 100BASE-T4 Capable */
#define BMSR_100B_TX_FD (0x4000U) /* 100BASE-TX Full Duplex Capable */
#define BMSR_100B_TX_HD (0x2000U) /* 100BASE-TX Half Duplex Capable */
#define BMSR_10B_T_FD (0x1000U) /* 10BASE-T Full Duplex Capable */
#define BMSR_10B_T_HD (0x0800U) /* 10BASE-T Half Duplex Capable */
#define BMSR_MF_PRE_SUP (0x0040U) /* Preamble suppression Capable */
#define BMSR_ANEG_COMPL (0x0020U) /* Auto Negotiation Complete */
#define BMSR_REM_FAULT (0x0010U) /* Remote Fault */
#define BMSR_ANEG_ABIL (0x0008U) /* Auto Negotiation Ability */
#define BMSR_LINK_STAT (0x0004U) /* Link Status (1=established) */
#define BMSR_JABBER_DET (0x0002U) /* Jaber Detect */
#define BMSR_EXT_CAPAB (0x0001U) /* Extended Capability */
/* PHY control 1 Register */
#define PHYCTRL1_OPMODE_SPEED (0x0003U)
#define PHYCTRL1_OPMODE_DUPLEX (0x0004U)
/* PHY Identifier Registers */
#define PHY_ID1 (0x0022U) /* KSZ8031 Device Identifier MSB */
#define PHY_ID2 (0x1560U) /* KSZ8031 Device Identifier LSB */
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
/* Check if the device identifier is valid */
static int32_t XMC_ETH_PHY_IsDeviceIdValid(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t phy_id1;
uint16_t phy_id2;
XMC_ETH_PHY_STATUS_t status;
/* Check Device Identification. */
if ((XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR1, &phy_id1) == XMC_ETH_MAC_STATUS_OK) &&
(XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYIDR2, &phy_id2) == XMC_ETH_MAC_STATUS_OK))
{
if ((phy_id1 == PHY_ID1) && ((phy_id2 & (uint16_t)0xfff0) == PHY_ID2))
{
status = XMC_ETH_PHY_STATUS_OK;
}
else
{
status = XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID;
}
}
else
{
status = XMC_ETH_PHY_STATUS_ERROR_TIMEOUT;
}
return (int32_t)status;
}
/* PHY initialize */
int32_t XMC_ETH_PHY_Init(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr, const XMC_ETH_PHY_CONFIG_t *const config)
{
int32_t status;
uint16_t reg_bmcr;
status = XMC_ETH_PHY_IsDeviceIdValid(eth_mac, phy_addr);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
status = XMC_ETH_PHY_Reset(eth_mac, phy_addr);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
reg_bmcr = 0U;
if (config->speed == XMC_ETH_LINK_SPEED_100M)
{
reg_bmcr |= BMCR_SPEED_SEL;
}
if (config->duplex == XMC_ETH_LINK_DUPLEX_FULL)
{
reg_bmcr |= BMCR_DUPLEX;
}
if (config->enable_auto_negotiate == true)
{
reg_bmcr |= BMCR_ANEG_EN;
}
if (config->enable_loop_back == true)
{
reg_bmcr |= BMCR_LOOPBACK;
}
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
}
}
return status;
}
/* Reset */
int32_t XMC_ETH_PHY_Reset(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
int32_t status;
uint16_t reg_bmcr;
/* Reset PHY*/
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, BMCR_RESET);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
/* Wait for the reset to complete */
do
{
status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, &reg_bmcr);
} while ((reg_bmcr & BMCR_RESET) != 0);
}
return status;
}
/* Initiate power down */
int32_t XMC_ETH_PHY_PowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
int32_t status;
uint16_t reg_bmcr;
status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, &reg_bmcr);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
reg_bmcr |= BMCR_POWER_DOWN;
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
}
return status;
}
/* Exit power down */
int32_t XMC_ETH_PHY_ExitPowerDown(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
int32_t status;
uint16_t reg_bmcr;
status = XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMCR, &reg_bmcr);
if (status == (int32_t)XMC_ETH_PHY_STATUS_OK)
{
reg_bmcr &= ~BMCR_POWER_DOWN;
status = (int32_t)XMC_ETH_MAC_WritePhy(eth_mac, phy_addr, REG_BMCR, reg_bmcr);
}
return status;
}
/* Get link status */
XMC_ETH_LINK_STATUS_t XMC_ETH_PHY_GetLinkStatus(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t val;
XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val);
return (XMC_ETH_LINK_STATUS_t)((val & BMSR_LINK_STAT) ? XMC_ETH_LINK_STATUS_UP : XMC_ETH_LINK_STATUS_DOWN);
}
/* Get link speed */
XMC_ETH_LINK_SPEED_t XMC_ETH_PHY_GetLinkSpeed(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t val;
XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val);
return (XMC_ETH_LINK_SPEED_t)(((val & PHYCTRL1_OPMODE_SPEED) - 1U) ? XMC_ETH_LINK_SPEED_100M : XMC_ETH_LINK_SPEED_10M);
}
/* Get link duplex settings */
XMC_ETH_LINK_DUPLEX_t XMC_ETH_PHY_GetLinkDuplex(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t val;
XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_PHYCTRL1, &val);
return (XMC_ETH_LINK_DUPLEX_t)((val & PHYCTRL1_OPMODE_DUPLEX) ? XMC_ETH_LINK_DUPLEX_FULL : XMC_ETH_LINK_DUPLEX_HALF);
}
bool XMC_ETH_PHY_IsAutonegotiationCompleted(XMC_ETH_MAC_t *const eth_mac, uint8_t phy_addr)
{
uint16_t val;
XMC_ETH_MAC_ReadPhy(eth_mac, phy_addr, REG_BMSR, &val);
return ((val & BMSR_ANEG_COMPL) == BMSR_ANEG_COMPL);
}
#endif // XMC_ETH_PHY_KSZ8081RNB

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/**
* @file xmc_fce.c
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-06-20:
* - Removed GetDriverVersion API
* @endcond
*
*/
/**********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include <xmc_fce.h>
#if defined (FCE)
#include <xmc_scu.h>
/*******************************************************************************
* API IMPLEMENTATION
*********************************************************************************************************************/
/*
* Initialize the FCE peripheral:
* Update FCE configuration and initialize seed value
*/
XMC_FCE_STATUS_t XMC_FCE_Init(const XMC_FCE_t *const engine)
{
engine->kernel_ptr->CFG = engine->fce_cfg_update.regval;
engine->kernel_ptr->CRC = engine->seedvalue;
return XMC_FCE_STATUS_OK;
}
/* Disable FCE */
void XMC_FCE_Disable(void)
{
FCE->CLC |= (uint32_t)FCE_CLC_DISR_Msk;
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_FCE);
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_FCE);
#endif
}
/* Enable FCE */
void XMC_FCE_Enable(void)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_FCE);
#endif
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_FCE);
FCE->CLC &= (uint32_t)~FCE_CLC_DISR_Msk;
}
/* Calculate and return the SAE J1850 CRC8 checksum */
XMC_FCE_STATUS_t XMC_FCE_CalculateCRC8(const XMC_FCE_t *const engine,
const uint8_t *data,
uint32_t length,
uint8_t *result)
{
XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK;
XMC_ASSERT("XMC_FCE_CalculateCRC8: Wrong FCE kernel used", (engine -> kernel_ptr == XMC_FCE_CRC8));
if (length == 0UL)
{
status = XMC_FCE_STATUS_ERROR;
}
else
{
while (0UL != length)
{
engine->kernel_ptr->IR = *data;
data++;
length -= 1U;
}
*result = (uint8_t)engine->kernel_ptr->CRC;
}
return status;
}
/* Calculate and return calculated CCITT CRC16 checksum */
XMC_FCE_STATUS_t XMC_FCE_CalculateCRC16(const XMC_FCE_t *const engine,
const uint16_t *data,
uint32_t length,
uint16_t *result)
{
XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK;
XMC_ASSERT("XMC_FCE_CalculateCRC16: Wrong FCE kernel used", (engine -> kernel_ptr == XMC_FCE_CRC16));
XMC_ASSERT("XMC_FCE_CalculateCRC16: Length field is empty", (length != 0));
XMC_ASSERT("XMC_FCE_CalculateCRC16: Length is not aligned", ((length & 0x01) == 0));
XMC_ASSERT("XMC_FCE_CalculateCRC16: Buffer is not aligned", (((uint32_t)data % 2U) == 0));
/* Check if data and length are word aligned */
if (((length & 0x01U) != 0U) || (((uint32_t)length % 2U) != 0U))
{
status = XMC_FCE_STATUS_ERROR;
}
else
{
while (0UL != length)
{
engine->kernel_ptr->IR = *data;
data++;
length -= 2U;
}
*result = (uint16_t)engine->kernel_ptr->CRC;
}
return status;
}
/* Calculate and return the IEEE 802.3 Ethernet CRC32 checksum */
XMC_FCE_STATUS_t XMC_FCE_CalculateCRC32(const XMC_FCE_t *const engine,
const uint32_t *data,
uint32_t length,
uint32_t *result)
{
XMC_FCE_STATUS_t status = XMC_FCE_STATUS_OK;
XMC_ASSERT("XMC_FCE_CalculateCRC32: Wrong FCE kernel used", ((engine->kernel_ptr == XMC_FCE_CRC32_0) ||
(engine->kernel_ptr == XMC_FCE_CRC32_1)));
XMC_ASSERT("XMC_FCE_CalculateCRC32: Length field is empty", (length != 0));
XMC_ASSERT("XMC_FCE_CalculateCRC32: Length is not aligned", ((length & 0x03) == 0));
XMC_ASSERT("XMC_FCE_CalculateCRC32: Buffer is not aligned", (((uint32_t)data % 4U) == 0));
/* Check if data and length are word aligned */
if (((length & 0x03U) != 0U) || (((uint32_t)length % 4U) != 0U))
{
status = XMC_FCE_STATUS_ERROR;
}
else
{
while (0UL != length)
{
engine->kernel_ptr->IR = *data;
data++;
length -= 4U;
}
*result = engine->kernel_ptr->CRC;
}
return status;
}
/* Trigger mismatch in the CRC registers */
void XMC_FCE_TriggerMismatch(const XMC_FCE_t *const engine, XMC_FCE_CTR_TEST_t test)
{
/* Create a 0 to 1 transition and clear to 0 once it is done */
engine->kernel_ptr->CTR &= ~((uint32_t)test);
engine->kernel_ptr->CTR |= (uint32_t)test;
engine->kernel_ptr->CTR &= ~((uint32_t)test);
}
/* Change endianness of 16-bit input buffer */
void XMC_FCE_LittleEndian16bit(uint8_t* inbuffer, uint16_t* outbuffer, uint16_t length)
{
uint16_t counter = 0U;
uint16_t bytecounter = 0U;
if ((length & 0x01U) == 0)
{
for (counter = 0U; counter < (length >> 1); counter++)
{
outbuffer[counter] = 0U;
}
outbuffer[counter] = 0U;
counter = 0U;
while (length)
{
outbuffer[counter] = ((uint16_t)((uint16_t)inbuffer[bytecounter] << 8U) |
(inbuffer[bytecounter + 1U]));
counter += 1U;
bytecounter += 2U;
length -= 2U;
}
}
}
/* Change endianness of 32-bit input buffer */
void XMC_FCE_LittleEndian32bit(uint8_t* inbuffer, uint32_t* outbuffer, uint16_t length)
{
uint16_t counter = 0U;
uint16_t bytecounter = 0U;
if ((length & 0x03U) == 0)
{
for (counter = 0U; counter < (length >> 2U); counter++)
{
outbuffer[counter] = 0U;
}
outbuffer[counter] = 0U;
counter = 0U;
while (length)
{
outbuffer[counter] = ((uint32_t)inbuffer[bytecounter] << 24U) |
((uint32_t)inbuffer[bytecounter + 1U] << 16U) |
((uint32_t)inbuffer[bytecounter + 2U] << 8U) |
(inbuffer[bytecounter + 3U]);
counter += 1U;
bytecounter += 4U;
length -= 4U;
}
}
}
#endif

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/**
* @file xmc_gpio.c
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* @endcond
*
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include <xmc_gpio.h>
/*******************************************************************************
* MACROS
*******************************************************************************/
#define PORT_HWSEL_Msk PORT0_HWSEL_HW0_Msk
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
void XMC_GPIO_SetMode(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_MODE_t mode)
{
XMC_ASSERT("XMC_GPIO_SetMode: Invalid port", XMC_GPIO_CHECK_PORT(port));
XMC_ASSERT("XMC_GPIO_SetMode: Invalid mode", XMC_GPIO_IsModeValid(mode));
port->IOCR[(uint32_t)pin >> 2U] &= ~(uint32_t)((uint32_t)PORT_IOCR_PC_Msk << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U)));
port->IOCR[(uint32_t)pin >> 2U] |= (uint32_t)mode << ((uint32_t)PORT_IOCR_PC_Size * ((uint32_t)pin & 0x3U));
}
void XMC_GPIO_SetHardwareControl(XMC_GPIO_PORT_t *const port, const uint8_t pin, const XMC_GPIO_HWCTRL_t hwctrl)
{
XMC_ASSERT("XMC_GPIO_SetHardwareControl: Invalid port", XMC_GPIO_CHECK_PORT(port));
XMC_ASSERT("XMC_GPIO_SetHardwareControl: Invalid hwctrl", XMC_GPIO_CHECK_HWCTRL(hwctrl));
port->HWSEL &= ~(uint32_t)((uint32_t)PORT_HWSEL_Msk << ((uint32_t)pin << 1U));
port->HWSEL |= (uint32_t)hwctrl << ((uint32_t)pin << 1U);
}

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@ -0,0 +1,591 @@
/**
* @file xmc_hrpwm.c
* @date 2015-07-14
*
* @cond
**********************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification,are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share
* modifications, enhancements or bug fixes with Infineon Technologies AG
* dave@infineon.com).
**********************************************************************************
*
* Change History
* --------------
*
* 2015-02-18:
* - Variable g_hrpwm_char_data[] defined in startup file is used in place of trim data macro<br>
*
* 2015-05-12:
* - XMC_HRPWM_CSG_SelClampingInput() api is added to select the clamping input.<br>
* - In XMC_HRPWM_Init() api macros used to check 'ccu_clock' frequency are renamed for readability<br>
* - 80MHz HRC operation would need a minimum of 70 Mhz CCU clock.<br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
* - Updated copyright and change history section.<br>
*
* 2015-07-06:
* - CSG trimming data assignment is corrected.<br>
*
* 2015-07-14:
* - Redundant code removed in XMC_HRPWM_HRC_ConfigSourceSelect0() and XMC_HRPWM_HRC_ConfigSourceSelect1() API's.<br>
* - Enums and masks are type casted to uint32_t type.
*
* @endcond
*
*/
/**
*
* @brief HRPWM low level driver API prototype definition for XMC family of microcontrollers <br>
*
* <b>Detailed description of file</b> <br>
* APIs provided in this file cover the following functional blocks of HRPWM: <br>
* -- High Resolution Channel (APIs prefixed with XMC_HRPWM_HRC_) <br>
* -- Comparator and Slope Generator (APIs prefixed with XMC_HRPWM_CSG_) <br>
*
*/
/***********************************************************************************************************************
* HEADER FILES
**********************************************************************************************************************/
#include <xmc_hrpwm.h>
#if defined(HRPWM0)
#include <xmc_scu.h>
/***********************************************************************************************************************
* MACROS
**********************************************************************************************************************/
/* 70MHz is considered as the minimum range for 80MHz HRC operation */
#define XMC_HRPWM_70MHZ_FREQUENCY 70000000U
/* 100MHz is considered as the maximum range for 80MHz HRC operation */
#define XMC_HRPWM_100MHZ_FREQUENCY 100000000U
/* 150MHz is considered as the maximum range for 120MHz HRC operation */
#define XMC_HRPWM_150MHZ_FREQUENCY 150000000U
/* 200MHz is considered as the maximum range for 180MHz HRC operation */
#define XMC_HRPWM_200MHZ_FREQUENCY 200000000U
#if (UC_SERIES == XMC44)
#define XMC_HRPWM_DELAY_CNT (28800U) /* Provides ~2.8 msec delay @ 220MHz frequency */
#elif (UC_SERIES == XMC42)
#define XMC_HRPWM_DELAY_CNT (19200U) /* Provides ~2.8 msec delay @ 150MHz frequency */
#else
#define XMC_HRPWM_DELAY_CNT (36000U) /* Provides ~5.3 msec delay @ 150MHz frequency */
#endif
/*********************************************************************************************************************
* LOCAL ROUTINES
********************************************************************************************************************/
static void XMC_HRPWM_lDelay(void);
/***********************************************************************************************************************
* API IMPLEMENTATION - GENERAL
**********************************************************************************************************************/
/* Delay */
void XMC_HRPWM_lDelay(void)
{
volatile uint32_t i;
for (i = 0U; i <= XMC_HRPWM_DELAY_CNT; i++) /* Wait more than 2 microseconds */
{
__NOP();
}
}
/***********************************************************************************************************************
* API IMPLEMENTATION - HRPWM GLOBAL
**********************************************************************************************************************/
/* Initializes HRPWM global registers */
XMC_HRPWM_STATUS_t XMC_HRPWM_Init(XMC_HRPWM_t *const hrpwm)
{
uint32_t *csg_memory;
uint32_t ccu_clock;
uint32_t clkc;
XMC_HRPWM_STATUS_t status;
XMC_ASSERT("XMC_HRPWM_Init:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm));
status = XMC_HRPWM_STATUS_ERROR;
/* Apply reset to HRPWM module */
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_HRPWM0);
/* Release reset for HRPWM module */
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_HRPWM0);
/* Ungate clock */
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_HRPWM0);
hrpwm->GLBANA = (uint32_t)0x00004A4E; /* Initialization sequence */
hrpwm->HRBSC |= (uint32_t)HRPWM0_HRBSC_HRBE_Msk; /* Enable Bias Generator of HRPWM */
/* Update CSG0 memory data */
csg_memory = (uint32_t *)XMC_HRPWM_CSG0_MEMORY_ADDRESS;
*csg_memory = g_hrpwm_char_data[0];
/* write csg memory bits[14:11] with 0b1100 */
*csg_memory &= (uint32_t)(0xFFFF87FF);
*csg_memory |= (uint32_t)(0x00006000);
/* Update CSG1 trimming data */
csg_memory = (uint32_t *)XMC_HRPWM_CSG1_MEMORY_ADDRESS;
*csg_memory = g_hrpwm_char_data[1];
/* write csg memory bits[14:11] with 0b1100 */
*csg_memory &= (uint32_t)(0xFFFF87FF);
*csg_memory |= (uint32_t)(0x00006000);
/* Update CSG2 trimming data */
csg_memory = (uint32_t *)XMC_HRPWM_CSG2_MEMORY_ADDRESS;
*csg_memory = g_hrpwm_char_data[2];
/* write csg memory bits[14:11] with 0b1100 */
*csg_memory &= (uint32_t)(0xFFFF87FF);
*csg_memory |= (uint32_t)(0x00006000);
/* Set CSG units to high speed mode */
hrpwm->CSGCFG = (uint32_t)(0x0000003F);
/* Read CCU clock frequency */
ccu_clock = XMC_SCU_CLOCK_GetCcuClockFrequency();
if ((ccu_clock > XMC_HRPWM_70MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_100MHZ_FREQUENCY))
{
clkc = 3U; /* Clock frequency range 70MHz+ - 100MHz is considered as 80MHz HRC operation */
}
else if ((ccu_clock > XMC_HRPWM_100MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_150MHZ_FREQUENCY))
{
clkc = 2U; /* Clock frequency range 100MHz+ - 150MHz is considered as 120MHz HRC operation */
}
else if ((ccu_clock > XMC_HRPWM_150MHZ_FREQUENCY) && (ccu_clock <= XMC_HRPWM_200MHZ_FREQUENCY))
{
clkc = 1U; /* Clock frequency range 150MHz+ - 200MHz is considered as 180MHz HRC operation */
}
else
{
clkc = 0U; /* Invalid frequency for HRC operation: Clock frequency <= 60MHz & Clock frequency > 200MHz */
}
if (clkc != 0U) /* Enter the loop only if the clock frequency is valid */
{
/* Program HRC clock configuration with clock frequency information */
hrpwm->HRCCFG |= (clkc << HRPWM0_HRCCFG_CLKC_Pos);
hrpwm->HRCCFG |= (uint32_t)HRPWM0_HRCCFG_HRCPM_Msk; /* Release HR generation from power down mode */
XMC_HRPWM_lDelay(); /* As per Initialization sequence */
/* Enable global high resolution generation / Force charge pump down */
hrpwm->GLBANA |= (uint32_t)HRPWM0_GLBANA_GHREN_Msk;
XMC_HRPWM_lDelay();
/* Check High resolution ready bit field */
if ((hrpwm->HRGHRS & HRPWM0_HRGHRS_HRGR_Msk) == 1U)
{
/* High resolution logic unit is ready */
status = XMC_HRPWM_STATUS_OK;
}
}
else
{
status = XMC_HRPWM_STATUS_ERROR; /* Clock frequency is invalid */
}
return (status);
}
/* Enable global high resolution generation */
void XMC_HRPWM_EnableGlobalHR(XMC_HRPWM_t *const hrpwm)
{
XMC_ASSERT("XMC_HRPWM_EnableGlobalHR:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm));
/* Enable global high resolution generation / Force charge pump down */
hrpwm->GLBANA |= (uint32_t)HRPWM0_GLBANA_GHREN_Msk;
XMC_HRPWM_lDelay(); /* Elapse startup time */
}
/* Disable global high resolution generation */
void XMC_HRPWM_DisableGlobalHR(XMC_HRPWM_t *const hrpwm)
{
XMC_ASSERT("XMC_HRPWM_DisableGlobalHR:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm));
/* Enable global high resolution generation / Force charge pump down */
hrpwm->GLBANA &= ~((uint32_t)HRPWM0_GLBANA_GHREN_Msk);
}
/***********************************************************************************************************************
* API IMPLEMENTATION - HRPWM HRC GLOBAL
**********************************************************************************************************************/
/* Checks and returns high resolution generation working status */
XMC_HRPWM_HR_LOGIC_t XMC_HRPWM_GetHRGenReadyStatus(XMC_HRPWM_t *const hrpwm)
{
XMC_HRPWM_HR_LOGIC_t status;
XMC_ASSERT("XMC_HRPWM_GetHRGenReadyStatus:Invalid module pointer", XMC_HRPWM_CHECK_MODULE_PTR(hrpwm));
if (hrpwm->HRGHRS)
{
status = XMC_HRPWM_HR_LOGIC_WORKING;
}
else
{
status = XMC_HRPWM_HR_LOGIC_NOT_WORKING;
}
return status;
}
/***********************************************************************************************************************
* API IMPLEMENTATION - HRPWM HRC CHANNEL
**********************************************************************************************************************/
/* Initialize HRPWM HRC channel */
void XMC_HRPWM_HRC_Init(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_CONFIG_t *const config)
{
XMC_ASSERT("XMC_HRPWM_HRC_Init:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc));
/* Setting of HRCy mode configuration */
hrc->GC = config->gc;
/* Passive level configuration */
hrc->PL = config->psl;
}
/* Configure Source selector 0 */
void XMC_HRPWM_HRC_ConfigSourceSelect0(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config)
{
uint32_t reg;
XMC_ASSERT("XMC_HRPWM_HRC_ConfigSourceSelect0:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc));
/* HRC mode config for source selector 0 */
hrc->GC &= ~((uint32_t)HRPWM0_HRC_GC_HRM0_Msk);
hrc->GC |= ((uint32_t)config->high_res_mode) << HRPWM0_HRC_GC_HRM0_Pos;
/*****************************************************************************
* HRCy global control selection (HRCyGSEL)
****************************************************************************/
reg = 0U;
if(config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG)
{
reg = ((uint32_t)config->cmp_set) << HRPWM0_HRC_GSEL_C0SS_Pos;
reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_S0M_Pos; /* comparator output controls the set config */
}
if (config->clear_config == XMC_HRPWM_HRC_SRC_INPUT_CSG)
{
reg |= ((uint32_t)config->cmp_clear) << HRPWM0_HRC_GSEL_C0CS_Pos;
reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_C0M_Pos; /* comparator output controls the clear config */
}
reg |= ((uint32_t)config->set_edge_config) << HRPWM0_HRC_GSEL_S0ES_Pos;
reg |= ((uint32_t)config->clear_edge_config) << HRPWM0_HRC_GSEL_C0ES_Pos;
hrc->GSEL &= (uint32_t)0xFFFF0000;
hrc->GSEL |= reg;
/*****************************************************************************
* HRCy timer selection (HRCyTSEL)
****************************************************************************/
reg = (uint32_t)config->timer_sel;
reg |= ((uint32_t)config->src_trap_enable) << HRPWM0_HRC_TSEL_TS0E_Pos;
hrc->TSEL &= (uint32_t)0xFFFEFFF8;
hrc->TSEL |= reg;
}
/* Configure Source selector 1 */
void XMC_HRPWM_HRC_ConfigSourceSelect1(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config)
{
uint32_t reg;
XMC_ASSERT("XMC_HRPWM_HRC_ConfigSourceSelect1:Invalid HRC pointer", XMC_HRPWM_CHECK_HRC_PTR(hrc));
/* HRC mode config for source selector 1 */
hrc->GC &= ~((uint32_t)HRPWM0_HRC_GC_HRM1_Msk);
hrc->GC |= ((uint32_t)config->high_res_mode) << HRPWM0_HRC_GC_HRM1_Pos;
/*****************************************************************************
* HRCy global control selection (HRCyGSEL)
****************************************************************************/
reg = 0U;
if(config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG)
{
reg = ((uint32_t)config->cmp_set) << HRPWM0_HRC_GSEL_C1SS_Pos;
reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_S1M_Pos; /* comparator output controls the set config*/
}
if (config->clear_config == XMC_HRPWM_HRC_SRC_INPUT_CSG)
{
reg |= ((uint32_t)config->cmp_clear) << HRPWM0_HRC_GSEL_C1CS_Pos;
reg |= ((uint32_t)XMC_HRPWM_HRC_SRC_INPUT_CSG) << HRPWM0_HRC_GSEL_C1M_Pos; /* comparator output controls the clear config */
}
reg |= ((uint32_t)config->set_edge_config) << HRPWM0_HRC_GSEL_S1ES_Pos;
reg |= ((uint32_t)config->clear_edge_config) << HRPWM0_HRC_GSEL_C1ES_Pos;
hrc->GSEL &= (uint32_t)0x0000FFFF;
hrc->GSEL |= reg;
/*****************************************************************************
* HRCy timer selection (HRCyTSEL)
****************************************************************************/
reg = (uint32_t)config->timer_sel;
reg |= ((uint32_t)config->src_trap_enable) << HRPWM0_HRC_TSEL_TS1E_Pos;
hrc->TSEL &= (uint32_t)0xFFFDFFC7;
hrc->TSEL |= reg;
}
/***********************************************************************************************************************
* API IMPLEMENTATION - HRPWM CSG GLOBAL
**********************************************************************************************************************/
/* No api's for CSG GLOBAL in xmc_hrpwm.c file */
/***********************************************************************************************************************
* API IMPLEMENTATION - HRPWM CSG SLICE
**********************************************************************************************************************/
/* Initialization of CSG slice */
void XMC_HRPWM_CSG_Init(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CONFIG_t *const config)
{
uint32_t reg;
XMC_ASSERT("XMC_HRPWM_CSG_Init:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
/* Passive level configuration */
csg->PLC = config->cmp_config.plc;
/* DAC Reference values */
csg->SDSV1 = config->dac_config.dac_dsv1;
csg->DSV2 = config->dac_config.dac_dsv2;
/* Pulse Swallow value */
csg->SPC = config->sgen_config.pulse_swallow_val;
/* Slope generation control (CSGySC) */
if(config->sgen_config.ctrl_mode != (uint32_t) XMC_HRPWM_CSG_SLOPE_CTRL_MODE_STATIC)
{
/* Dynamic Slope Generation */
csg->SC = config->sgen_config.sc;
}
else
{
/* Static Mode */
csg->SC = ((uint32_t)config->sgen_config.static_mode_ist_enable) << HRPWM0_CSG_SC_IST_Pos;
}
reg = ((uint32_t)config->dac_config.start_mode) << HRPWM0_CSG_SC_SWSM_Pos;
csg->SC |= reg;
/* Comparator Initialization */
csg->CC = config->cmp_config.cc;
/* Blanking value */
csg->BLV = config->cmp_config.blanking_val;
}
/* Set either CINA or CINB as inverting input of the comparator */
void XMC_HRPWM_CSG_SetCMPInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CMP_INPUT_t input)
{
XMC_ASSERT("XMC_HRPWM_CSG_SetCMPInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
if (input == XMC_HRPWM_CSG_CMP_INPUT_CINA)
{
/* Inverting comparator input connected to CINA */
csg->CC &= ~((uint32_t)HRPWM0_CSG_CC_IMCS_Msk);
}
else
{
/* Inverting comparator input connected to CINB */
csg->CC |= (uint32_t)HRPWM0_CSG_CC_IMCS_Msk;
}
}
/* Configure input selection for Blanking function */
void XMC_HRPWM_CSG_SelBlankingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
{
uint32_t reg;
XMC_ASSERT("XMC_HRPWM_CSG_SelBlankingInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
reg = csg->CC;
if ((reg & HRPWM0_CSG_CC_EBE_Msk) != 0U) /* external blanking trigger enabled? */
{
reg &= ~((uint32_t)HRPWM0_CSG_CC_IBS_Msk);
reg |= (uint32_t) config->mapped_input;
}
reg &= ~((uint32_t)HRPWM0_CSG_CC_BLMC_Msk);
reg |= ((uint32_t) config->edge) << HRPWM0_CSG_CC_BLMC_Pos;
csg->CC = reg;
}
/* Configure input selection for Clamping */
void XMC_HRPWM_CSG_SelClampingInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
{
uint32_t reg;
XMC_ASSERT("XMC_HRPWM_CSG_SelClampingInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
reg = csg->PLC;
reg &= ~((uint32_t)HRPWM0_CSG_PLC_IPLS_Msk);
reg |= (uint32_t) config->mapped_input;
reg &= ~((uint32_t)HRPWM0_CSG_PLC_PLCL_Msk);
reg |= ((uint32_t) config->level) << HRPWM0_CSG_PLC_PLCL_Pos;
csg->PLC = reg;
}
/* Configure input selection to start slope generation function */
void XMC_HRPWM_CSG_StartSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
{
XMC_ASSERT("XMC_HRPWM_CSG_StartSlopeGenConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STRIS_Msk);
csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STRIS_Pos;
csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STRES_Msk);
csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STRES_Pos;
}
/* Configure input selection to stop slope generation function */
void XMC_HRPWM_CSG_StopSlopeGenConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
{
XMC_ASSERT("XMC_HRPWM_CSG_StopSlopeGenConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STPIS_Msk);
csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STPIS_Pos;
csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STPES_Msk);
csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STPES_Pos;
}
/* Configure input selection for triggering DAC conversion */
void XMC_HRPWM_CSG_TriggerDACConvConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
{
XMC_ASSERT("XMC_HRPWM_CSG_TriggerDACConvConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_TRGIS_Msk);
csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_TRGIS_Pos;
csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_TRGES_Msk);
csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_TRGES_Pos;
}
/* Configure input selection for triggering shadow transfer */
void XMC_HRPWM_CSG_TriggerShadowXferConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
{
XMC_ASSERT("XMC_HRPWM_CSG_TriggerShadowXferConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_STIS_Msk);
csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_STIS_Pos;
csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_STES_Msk);
csg->IES |= ((uint32_t)config->edge) << HRPWM0_CSG_IES_STES_Pos;
}
/* Configure input selection to trigger a switch in DAC reference value. This is only applicable to DAC in static mode */
void XMC_HRPWM_CSG_DACRefValSwitchingConfig(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_INPUT_CONFIG_t *const config)
{
XMC_ASSERT("XMC_HRPWM_CSG_DACRefValSwitchingConfig:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_SVIS_Msk);
csg->DCI |= ((uint32_t)config->mapped_input) << HRPWM0_CSG0_DCI_SVIS_Pos;
csg->IES &= ~((uint32_t)HRPWM0_CSG_IES_SVLS_Msk);
csg->IES |= ((uint32_t)config->level) << HRPWM0_CSG_IES_SVLS_Pos;
}
/* Configure input selection for clock selection used in slope generation */
void XMC_HRPWM_CSG_SelSlopeGenClkInput(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_CLK_INPUT_t input_clk)
{
XMC_ASSERT("XMC_HRPWM_CSG_SelSlopeGenClkInput:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
csg->DCI &= ~((uint32_t)HRPWM0_CSG0_DCI_SCS_Msk);
csg->DCI |= ((uint32_t)input_clk) << HRPWM0_CSG0_DCI_SCS_Pos;
}
/* Set the service request interrupt node */
void XMC_HRPWM_CSG_SetSRNode(XMC_HRPWM_CSG_t *const csg, const XMC_HRPWM_CSG_IRQ_ID_t event,
const XMC_HRPWM_CSG_IRQ_SR_LINE_t sr)
{
XMC_ASSERT("XMC_HRPWM_CSG_SetSRNode:Invalid CSG pointer", XMC_HRPWM_CHECK_CSG_PTR(csg));
switch (event)
{
case (XMC_HRPWM_CSG_IRQ_ID_VLS1):
csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_VLS1S_Msk);
csg->SRS |= (uint32_t)sr;
break;
case (XMC_HRPWM_CSG_IRQ_ID_VLS2):
csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_VLS2S_Msk);
csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_VLS2S_Pos;
break;
case (XMC_HRPWM_CSG_IRQ_ID_TRGS):
csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_TRLS_Msk);
csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_TRLS_Pos;
break;
case (XMC_HRPWM_CSG_IRQ_ID_STRS):
case (XMC_HRPWM_CSG_IRQ_ID_STPS):
csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_SSLS_Msk);
csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_SSLS_Pos;
break;
case (XMC_HRPWM_CSG_IRQ_ID_STD):
csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_STLS_Msk);
csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_STLS_Pos;
break;
case (XMC_HRPWM_CSG_IRQ_ID_CRSE):
case (XMC_HRPWM_CSG_IRQ_ID_CFSE):
csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_CRFLS_Msk);
csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_CRFLS_Pos;
break;
case (XMC_HRPWM_CSG_IRQ_ID_CSEE):
csg->SRS &= ~((uint32_t)HRPWM0_CSG_SRS_CSLS_Msk);
csg->SRS |= ((uint32_t)sr) << HRPWM0_CSG_SRS_CSLS_Pos;
break;
default:
break;
}
}
#endif /* #if defined(HRPWM0) */

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/**
* @file xmc_i2c.c
* @date 2015-10-02
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
- Modified XMC_I2C_CH_Stop() API for not setting to IDLE the channel if it is busy <br>
*
* 2015-06-20:
* - Removed GetDriverVersion API <br>
*
* 2015-08-14:
* - updated the XMC_I2C_CH_SetBaudrate API to support dynamic change from 400K to low frequencies <br>
*
* 2015-09-01:
* - Modified XMC_I2C_CH_EnableEvent() and XMC_I2C_CH_DisableEvent() for supporting multiple events configuration <br>
*
* 2015-10-02:
* - Fixed 10bit addressing
*
* @endcond
*
*/
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include <xmc_i2c.h>
/*********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#define XMC_I2C_7BIT_ADDR_Pos (8U) /**< 7-bit address position */
#define TRANSMISSION_MODE (3U) /**< The shift control signal is considered active
without referring to the actual signal level. Data
frame transfer is possible after each edge of the signal.*/
#define WORDLENGTH (7U) /**< Word length */
#define SET_TDV (1U) /**< Transmission data valid */
#define XMC_I2C_10BIT_ADDR_MASK (0x7C00U) /**< Address mask for 10-bit mode */
/*********************************************************************************************************************
* ENUMS
*********************************************************************************************************************/
typedef enum XMC_I2C_CH_TDF
{
XMC_I2C_CH_TDF_MASTER_SEND = 0U,
XMC_I2C_CH_TDF_SLAVE_SEND = (uint32_t)1U << 8U,
XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK = (uint32_t)2U << 8U,
XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK = (uint32_t)3U << 8U,
XMC_I2C_CH_TDF_MASTER_START = (uint32_t)4U << 8U,
XMC_I2C_CH_TDF_MASTER_RESTART = (uint32_t)5U << 8U,
XMC_I2C_CH_TDF_MASTER_STOP = (uint32_t)6U << 8U
} XMC_I2C_CH_TDF_t;
typedef enum XMC_I2C_CH_MAX_SPEED
{
XMC_I2C_CH_MAX_SPEED_STANDARD = 100000U,
XMC_I2C_CH_MAX_SPEED_FAST = 400000U
} XMC_I2C_CH_MAX_SPEED_t;
typedef enum XMC_I2C_CH_CLOCK_OVERSAMPLING
{
XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD = 10U,
XMC_I2C_CH_CLOCK_OVERSAMPLING_FAST = 25U
} XMC_I2C_CH_CLOCK_OVERSAMPLINGS_t;
/*********************************************************************************************************************
* API IMPLEMENTATION
*********************************************************************************************************************/
/* Initializes the USIC channel by setting the data format, slave address, baudrate, transfer buffer */
void XMC_I2C_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2C_CH_CONFIG_t *const config)
{
XMC_USIC_CH_Enable(channel);
/* Data format configuration */
channel->SCTR = ((uint32_t)TRANSMISSION_MODE << (uint32_t)USIC_CH_SCTR_TRM_Pos) | /* Transmision mode */
((uint32_t)WORDLENGTH << (uint32_t)USIC_CH_SCTR_WLE_Pos) | /* 8 data bits */
USIC_CH_SCTR_FLE_Msk | /* unlimited data flow */
USIC_CH_SCTR_SDIR_Msk | /* MSB shifted first */
USIC_CH_SCTR_PDL_Msk; /* Passive Data Level */
XMC_I2C_CH_SetSlaveAddress(channel, config->address);
(void)XMC_I2C_CH_SetBaudrate(channel, config->baudrate);
/* Enable transfer buffer */
channel->TCSR = ((uint32_t)SET_TDV << (uint32_t)USIC_CH_TCSR_TDEN_Pos) | USIC_CH_TCSR_TDSSM_Msk;
/* Clear status flags */
channel->PSCR = 0xFFFFFFFFU;
/* Disable parity generation */
channel->CCR = 0x0U;
}
/* Sets the slave address */
void XMC_I2C_CH_SetSlaveAddress(XMC_USIC_CH_t *const channel, const uint16_t address)
{
if ((address & XMC_I2C_10BIT_ADDR_MASK) == XMC_I2C_10BIT_ADDR_GROUP)
{
channel->PCR_IICMode = (address & 0xffU) | ((address << 1) & 0xfe00U);
}
else
{
channel->PCR_IICMode = ((uint32_t)address) << XMC_I2C_7BIT_ADDR_Pos;
}
}
/* Read the slave address */
uint16_t XMC_I2C_CH_GetSlaveAddress(const XMC_USIC_CH_t *const channel)
{
uint32_t address = channel->PCR_IICMode & (uint32_t)USIC_CH_PCR_IICMode_SLAD_Msk;
if ((address & 0xffU) == 0U)
{
address = address >> XMC_I2C_7BIT_ADDR_Pos;
}
else
{
address = (address & 0xffU) | ((address >> 1) & 0x0300U);
}
return (uint16_t)address;
}
/* Sets the baudrate and oversampling based on standard speed or fast speed */
XMC_I2C_CH_STATUS_t XMC_I2C_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate)
{
XMC_I2C_CH_STATUS_t status;
status = XMC_I2C_CH_STATUS_ERROR;
if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_STANDARD)
{
channel->PCR_IICMode &= (uint32_t)~USIC_CH_PCR_IICMode_STIM_Msk;
if (XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_STANDARD) == XMC_USIC_CH_STATUS_OK)
{
status = XMC_I2C_CH_STATUS_OK;
}
}
else if (rate <= (uint32_t)XMC_I2C_CH_MAX_SPEED_FAST)
{
channel->PCR_IICMode |= (uint32_t)USIC_CH_PCR_IICMode_STIM_Msk;
if (XMC_USIC_CH_SetBaudrate(channel, rate, (uint32_t)XMC_I2C_CH_CLOCK_OVERSAMPLING_FAST) == XMC_USIC_CH_STATUS_OK)
{
status = XMC_I2C_CH_STATUS_OK;
}
}
else
{
status = XMC_I2C_CH_STATUS_ERROR;
}
return status;
}
/* Sends master start condition along with read/write command to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_MasterStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command)
{
uint32_t temp;
temp = addr | (uint32_t)XMC_I2C_CH_TDF_MASTER_START;
if (command == XMC_I2C_CH_CMD_READ)
{
temp |= 0x1U;
}
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = temp;
}
else
{
channel->IN[0U] = temp;
}
}
/* Sends master repeated start condition along with read/write command to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_MasterRepeatedStart(XMC_USIC_CH_t *const channel, const uint16_t addr, const XMC_I2C_CH_CMD_t command)
{
uint32_t tmp;
tmp = addr | (uint32_t)XMC_I2C_CH_TDF_MASTER_RESTART;
if (command == XMC_I2C_CH_CMD_READ)
{
tmp |= 0x1U;
}
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = tmp;
}
else
{
channel->IN[0U] = tmp;
}
}
/* Sends master stop command to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_MasterStop(XMC_USIC_CH_t *const channel)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_STOP;
}
else
{
channel->IN[0U] = (uint32_t)XMC_I2C_CH_TDF_MASTER_STOP;
}
}
/* Sends master send command along with data to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_MasterTransmit(XMC_USIC_CH_t *const channel, const uint8_t data)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while (XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_SEND | data;
}
else
{
channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_SEND | data;
}
}
/* Sends slave send command along with data to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_SlaveTransmit(XMC_USIC_CH_t *const channel, const uint8_t data)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_SLAVE_SEND | data;
}
else
{
channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_SLAVE_SEND | data;
}
}
/* Sends master receive ack command to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_MasterReceiveAck(XMC_USIC_CH_t *const channel)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK;
}
else
{
channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_ACK;
}
}
/* Sends master receive nack command to IN/TBUF register based on FIFO/non-FIFO modes. */
void XMC_I2C_CH_MasterReceiveNack(XMC_USIC_CH_t *const channel)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
/* check TDV, wait until TBUF is ready */
}
/* clear PSR_TBIF */
XMC_I2C_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK;
}
else
{
channel->IN[0] = (uint32_t)XMC_I2C_CH_TDF_MASTER_RECEIVE_NACK;
}
}
/* Reads the data from RBUF if FIFO size is 0 otherwise from OUTR. */
uint8_t XMC_I2C_CH_GetReceivedData(const XMC_USIC_CH_t *const channel)
{
uint8_t retval;
/* Check FIFO size */
if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U)
{
retval = (uint8_t)channel->RBUF;
}
else
{
retval = (uint8_t)channel->OUTR;
}
return retval;
}
/* Sets the operating mode of USIC to IDLE */
XMC_I2C_CH_STATUS_t XMC_I2C_CH_Stop(XMC_USIC_CH_t *const channel)
{
XMC_I2C_CH_STATUS_t status = XMC_I2C_CH_STATUS_OK;
if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U)
{
status = XMC_I2C_CH_STATUS_BUSY;
}
else
{
/* USIC channel in IDLE mode */
XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
}
return status;
}
void XMC_I2C_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR |= (event&0x1fc00U);
channel->PCR_IICMode |= ((event) & 0x41fc0000U);
}
void XMC_I2C_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR &= (uint32_t)~(event&0x1fc00U);
channel->PCR_IICMode &= (uint32_t)~((event) & 0x41fc0000U);
}

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/**
* @file xmc_i2s.c
* @date 2015-06-30
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-08-21:
* - Initial <br>
*
* 2015-09-01:
* - Modified XMC_I2S_CH_EnableEvent() and XMC_I2S_CH_DisableEvent() for supporting multiple events configuration<br>
*
* 2015-09-14:
* - Modified XMC_I2S_CH_SetSystemWordLength for supporting up to 63 system word length.
* - Removed parity configuration<br>
*
* 2015-09-28:
* - Fixed bugs in the XMC_I2S_CH_Init() and in the ASSERTs <br>
*
* 2015-11-04:
* - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_I2S_CH_Transmit() API <br>
*
* 2016-06-30:
* - Modified XMC_I2S_CH_Init:
* + change default passive level to 0
* + Call XMC_I2S_CH_SetSystemWordLength() to set the system frame length equal to the frame length.
* - Modified XMC_I2S_CH_SetBaudrate:
* + Optional Master clock output signal generated with a fixed phase relation to SCLK.
*
* @endcond
*
*/
/**
*
* @brief I2S driver for XMC microcontroller family
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_scu.h>
#include <xmc_i2s.h>
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
/* To take into account the SCLK divider by 2 and the PPPEN divider (see Divider Mode Counter figure in RM) */
#define XMC_I2S_CH_OVERSAMPLING (4UL)
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/* Initializes the selected I2S channel with the config structure. */
void XMC_I2S_CH_Init(XMC_USIC_CH_t *const channel, const XMC_I2S_CH_CONFIG_t *const config)
{
XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid",(config->data_delayed_sclk_periods > 0U) &&
(config->data_delayed_sclk_periods < config->frame_length));
XMC_USIC_CH_Enable(channel);
if(config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER)
{
/* Configure baud rate */
(void)XMC_I2S_CH_SetBaudrate(channel, config->baudrate);
}
/* Configuration of USIC Shift Control */
/* Transmission Mode (TRM) = 1 */
channel->SCTR = (uint32_t)(0x3UL << USIC_CH_SCTR_TRM_Pos) |
(uint32_t)((config->frame_length -1U) << USIC_CH_SCTR_FLE_Pos) |
(uint32_t)((config->data_bits - 1U) << USIC_CH_SCTR_WLE_Pos) |
USIC_CH_SCTR_SDIR_Msk;
/* Configuration of USIC Transmit Control/Status Register */
/* TBUF Data Enable (TDEN) = 1 */
/* TBUF Data Single Shot Mode (TDSSM) = 1 */
/* WA mode enabled(WAMD) = 1 */
channel->TCSR = (uint32_t)((channel->TCSR & (~(USIC_CH_TCSR_WLEMD_Msk |
USIC_CH_TCSR_SELMD_Msk |
USIC_CH_TCSR_FLEMD_Msk |
USIC_CH_TCSR_HPCMD_Msk))) |
USIC_CH_TCSR_WAMD_Msk |
(0x01UL << USIC_CH_TCSR_TDEN_Pos) |
USIC_CH_TCSR_TDSSM_Msk);
if(config->bus_mode == XMC_I2S_CH_BUS_MODE_MASTER)
{
/* Configuration of Protocol Control Register */
channel->PCR_IISMode = (uint32_t)USIC_CH_PCR_IISMode_WAGEN_Msk;
}
/* Configuration of Protocol Control Register */
channel->PCR_IISMode |= (uint32_t)(USIC_CH_PCR_IISMode_DTEN_Msk |
(uint32_t)config->wa_inversion) |
((uint32_t)((uint32_t)config->data_delayed_sclk_periods - 1U) << USIC_CH_PCR_IISMode_TDEL_Pos);
XMC_I2S_CH_SetSystemWordLength(channel, config->frame_length);
/* Clear protocol status */
channel->PSCR = 0xFFFFFFFFUL;
}
XMC_I2S_CH_STATUS_t XMC_I2S_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate)
{
XMC_I2S_CH_STATUS_t status;
status = XMC_I2S_CH_STATUS_ERROR;
if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U))
{
if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_I2S_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK)
{
channel->BRG = (uint32_t)((channel->BRG & ~(USIC_CH_BRG_CTQSEL_Msk)) |
(0x2UL << USIC_CH_BRG_CTQSEL_Pos)) |
USIC_CH_BRG_PPPEN_Msk;
status = XMC_I2S_CH_STATUS_OK;
}
}
return status;
}
void XMC_I2S_CH_SetSystemWordLength(XMC_USIC_CH_t *const channel,uint32_t sclk_cycles_system_word_length)
{
uint32_t sclk_cycles_system_word_length_temp;
uint8_t dctq_temp;
uint8_t pctq_temp;
uint8_t dctq = 1U;
uint8_t pctq = 1U;
uint8_t best_error = 64U;
uint8_t error;
XMC_ASSERT("XMC_I2S_CH_Init: data_delayed_sclk_periods value not valid",(sclk_cycles_system_word_length > 0U) && (sclk_cycles_system_word_length < 65U));
for (dctq_temp =1U; dctq_temp < 33U ; dctq_temp++)
{
for (pctq_temp =1U; pctq_temp < 5U ; pctq_temp++)
{
sclk_cycles_system_word_length_temp = ((uint32_t)dctq_temp) * ((uint32_t)pctq_temp);
if(sclk_cycles_system_word_length_temp == sclk_cycles_system_word_length)
{
dctq = dctq_temp;
pctq = pctq_temp;
break;
}
if (sclk_cycles_system_word_length_temp > sclk_cycles_system_word_length)
{
error = (uint8_t)(sclk_cycles_system_word_length_temp - sclk_cycles_system_word_length);
}
else
{
error = (uint8_t)(sclk_cycles_system_word_length - sclk_cycles_system_word_length_temp);
}
if(error < best_error)
{
best_error = error;
dctq = dctq_temp;
pctq = pctq_temp;
}
}
}
channel->BRG = (uint32_t)((channel->BRG & ~((uint32_t)(USIC_CH_BRG_DCTQ_Msk |
USIC_CH_BRG_PCTQ_Msk))) |
(uint32_t)((uint32_t)((uint32_t)((uint32_t)dctq- 1U) << USIC_CH_BRG_DCTQ_Pos) |
(uint32_t)((uint32_t)((uint32_t)pctq- 1U) << USIC_CH_BRG_PCTQ_Pos)));
}
/* Puts the data into FIFO if FIFO mode is enabled or else into standard buffers, by setting the proper mode. */
void XMC_I2S_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_I2S_CH_CHANNEL_t channel_number)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY)
{
}
XMC_I2S_CH_ClearStatusFlag(channel, (uint32_t)XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[(uint32_t)channel_number << 4] = data;
}
else
{
channel->IN[(uint32_t)channel_number << 4] = data;
}
}
/* Reads the data from the buffers based on the FIFO mode selection. */
uint16_t XMC_I2S_CH_GetReceivedData(XMC_USIC_CH_t *const channel)
{
uint16_t retval;
/* Check FIFO size */
if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U)
{
retval = (uint16_t)channel->RBUF;
}
else
{
retval = (uint16_t)channel->OUTR;
}
return retval;
}
XMC_I2S_CH_STATUS_t XMC_I2S_CH_Stop(XMC_USIC_CH_t *const channel)
{
XMC_I2S_CH_STATUS_t status = XMC_I2S_CH_STATUS_OK;
if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U)
{
status = XMC_I2S_CH_STATUS_BUSY;
}
else
{
/* USIC channel in IDLE mode */
XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
}
return status;
}
void XMC_I2S_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR |= (event&0x1fc00U);
channel->PCR_IISMode |= ((event >> 2U) & 0x8070U);
}
void XMC_I2S_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR &= (uint32_t)~(event&0x1fc00U);
channel->PCR_IISMode &= (uint32_t)~((event >> 2U) & 0x8070U);
}

383
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/**
* @file xmc_ledts.c
* @date 2017-02-25
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft <br>
* - New API added: XMC_LEDTS_SetActivePADNo() <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API
*
* 2017-02-25:
* - XMC_LEDTS_InitGlobal() fixed compilation warnings
*
* <b>Detailed description of file:</b><br>
* APIs for the functional blocks of LEDTS have been defined:<br>
* -- GLOBAL (APIs prefixed with LEDTS_GLOBAL_) <br>
* -- Clock configuration, Function/Event configuration, Interrupt configuration
*
* @endcond
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_ledts.h>
#if defined(LEDTS0)
#include "xmc_scu.h"
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_LEDTS_CLOCK_NOT_RUNNING 0U
/*********************************************************************************************************************
* ENUMS
********************************************************************************************************************/
/*********************************************************************************************************************
* DATA STRUCTURES
********************************************************************************************************************/
/*********************************************************************************************************************
* GLOBAL DATA
********************************************************************************************************************/
/*********************************************************************************************************************
* LOCAL/UTILITY ROUTINES
********************************************************************************************************************/
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/**
* Initialization of global register
*/
XMC_LEDTS_STATUS_t XMC_LEDTS_InitGlobal(XMC_LEDTS_t *const ledts, const XMC_LEDTS_GLOBAL_CONFIG_t *config)
{
XMC_ASSERT("XMC_LEDTS_InitGlobal:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
XMC_ASSERT("XMC_LEDTS_InitGlobal:Null Pointer", (config != (XMC_LEDTS_GLOBAL_CONFIG_t *)NULL));
if (ledts == XMC_LEDTS0)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS0);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS0);
#endif
}
#if defined(LEDTS1)
else if (ledts == XMC_LEDTS1)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS1);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS1);
#endif
}
#endif
#if defined(LEDTS2)
else if (ledts == XMC_LEDTS2)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_LEDTS2);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_LEDTS2);
#endif
}
#endif
else
{
XMC_ASSERT("XMC_LEDTS_InitGlobal:Invalid Module Pointer", 0);
}
if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING)
{
return XMC_LEDTS_STATUS_RUNNING;
}
ledts->GLOBCTL = config->globctl;
return XMC_LEDTS_STATUS_SUCCESS;
}
/**
* Initialization of registers for LED-driving function
*/
XMC_LEDTS_STATUS_t XMC_LEDTS_InitLED(XMC_LEDTS_t *const ledts, const XMC_LEDTS_LED_CONFIG_t *config)
{
XMC_ASSERT("XMC_LEDTS_LED_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
XMC_ASSERT("XMC_LEDTS_LED_Init:Null Pointer", (config != (XMC_LEDTS_LED_CONFIG_t *)NULL));
if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING)
{
return XMC_LEDTS_STATUS_RUNNING;
}
ledts->FNCTL &= ~(LEDTS_FNCTL_COLLEV_Msk | LEDTS_FNCTL_NR_LEDCOL_Msk);
ledts->FNCTL |= (config->fnctl);
/* Enable LED function */
ledts->GLOBCTL |= LEDTS_GLOBCTL_LD_EN_Msk;
return XMC_LEDTS_STATUS_SUCCESS;
}
/**
* Initialization of registers for basic Touch-Sense control function
*/
XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSBasic(XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_BASIC_t *config)
{
uint32_t reg;
XMC_ASSERT("XMC_LEDTS_TS_Basic_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
XMC_ASSERT("XMC_LEDTS_TS_Basic_Init:Null Pointer", (config != (XMC_LEDTS_TS_CONFIG_BASIC_t *)NULL));
if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING)
{
return XMC_LEDTS_STATUS_RUNNING;
}
reg = ~(LEDTS_FNCTL_ACCCNT_Msk | LEDTS_FNCTL_TSCCMP_Msk | LEDTS_FNCTL_TSCTRR_Msk | LEDTS_FNCTL_TSCTRSAT_Msk |
LEDTS_FNCTL_NR_TSIN_Msk);
ledts->FNCTL &= (reg);
ledts->FNCTL |= (config->fnctl);
/* Enable TS function */
ledts->GLOBCTL |= LEDTS_GLOBCTL_TS_EN_Msk;
return XMC_LEDTS_STATUS_SUCCESS;
}
/**
* Initialization of registers for advanced Touch-Sense control function
*/
XMC_LEDTS_STATUS_t XMC_LEDTS_InitTSAdvanced (XMC_LEDTS_t *const ledts, const XMC_LEDTS_TS_CONFIG_ADVANCED_t *config)
{
uint32_t reg;
XMC_ASSERT("XMC_LEDTS_TS_Advanced_Init:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
XMC_ASSERT("XMC_LEDTS_TS_Advanced_Init:Null Pointer", (config != (XMC_LEDTS_TS_CONFIG_ADVANCED_t *)NULL));
if((ledts->GLOBCTL & LEDTS_GLOBCTL_CLK_PS_Msk) != XMC_LEDTS_CLOCK_NOT_RUNNING)
{
return XMC_LEDTS_STATUS_RUNNING;
}
reg = ~(LEDTS_GLOBCTL_MASKVAL_Msk | LEDTS_GLOBCTL_FENVAL_Msk);
ledts->GLOBCTL &= (reg);
ledts->GLOBCTL |= (config->globctl);
reg = ~(LEDTS_FNCTL_PADT_Msk | LEDTS_FNCTL_PADTSW_Msk | LEDTS_FNCTL_EPULL_Msk | LEDTS_FNCTL_TSOEXT_Msk);
ledts->FNCTL &= (reg);
ledts->FNCTL |= (config->fnctl);
return XMC_LEDTS_STATUS_SUCCESS;
}
/**
* Starts LEDTS-counter
*/
void XMC_LEDTS_StartCounter(XMC_LEDTS_t *const ledts, const uint16_t prescaler)
{
XMC_ASSERT("XMC_LEDTS_Start_Counter:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
ledts->GLOBCTL |= prescaler<<16U;
}
/**
* Stops LEDTS-counter
*/
void XMC_LEDTS_StopCounter(XMC_LEDTS_t *const ledts)
{
XMC_ASSERT("XMC_LEDTS_Stop_Counter:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
ledts->GLOBCTL &= 0x0000FFFF;
}
/**
* Reads time interrupt flags
*/
uint32_t XMC_LEDTS_ReadInterruptFlag(XMC_LEDTS_t *const ledts)
{
XMC_ASSERT("XMC_LEDTS_ReadInterruptFlag:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
return (ledts->EVFR & 0xF);
}
/**
* Set the active pad number
*/
void XMC_LEDTS_SetActivePADNo(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_TS_INPUT_t pad_num)
{
uint32_t reg;
XMC_ASSERT("XMC_LEDTS_SetActivePADNo:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
reg = ledts->FNCTL;
reg &= ~(LEDTS_FNCTL_PADT_Msk);
reg |= (uint32_t)pad_num;
ledts->FNCTL = reg;
}
/**
* Clears interrupt indication flags
*/
void XMC_LEDTS_ClearInterruptFlag(XMC_LEDTS_t *const ledts, uint32_t interrupt_mask)
{
XMC_ASSERT("XMC_LEDTS_ClearInterruptFlag:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
ledts->EVFR = (interrupt_mask << LEDTS_EVFR_CTSF_Pos);
}
/**
* Programming of registers to output pattern on an LED column in LED matrix
*/
void XMC_LEDTS_SetLEDLinePattern(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUMN_t column, const uint8_t pattern)
{
uint32_t reg;
uint8_t reg_index = ((uint8_t)column) >> 2;
uint8_t bit_shift_count = ((uint8_t)column & 0x03) * 8;
XMC_ASSERT("XMC_LEDTS_Set_LED_Line_Pattern:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
reg = ledts->LINE[reg_index];
reg &= (~(0xff << bit_shift_count));
reg |= pattern << bit_shift_count;
ledts->LINE[reg_index] = reg;
}
/**
* Programming of registers to adjust brightness of an LED column in LED matrix
*/
void XMC_LEDTS_SetColumnBrightness(XMC_LEDTS_t *const ledts, XMC_LEDTS_LED_COLUMN_t column, const uint8_t brightness)
{
uint32_t reg;
uint8_t reg_index = ((uint8_t)column) >> 2;
uint8_t bit_shift_count = ((uint8_t)column & 0x03) * 8;
XMC_ASSERT("XMC_LEDTS_Set_Column_Brightness:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
reg = ledts->LDCMP[reg_index];
reg &= (~(0xff << bit_shift_count));
reg |= brightness << bit_shift_count;
ledts->LDCMP[reg_index] = reg;
}
/**
* Programming of registers to set common oscillation window size for touch-sense inputs
*/
void XMC_LEDTS_SetCommonOscillationWindow(XMC_LEDTS_t *const ledts, const uint8_t common_size)
{
uint32_t reg;
XMC_ASSERT("XMC_LEDTS_Set_Common_Oscillation_Window:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
reg = ledts->LDCMP[1];
reg &= ~LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk;
reg |= (common_size << LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos);
ledts->LDCMP[1] = reg;
}
/**
* Checking the previous active function or LED column status
*/
uint32_t XMC_LEDTS_ReadFNCOL(XMC_LEDTS_t *const ledts)
{
uint32_t fncol_read;
XMC_ASSERT("XMC_LEDTS_Read_FNCOL:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
fncol_read = ledts->FNCTL & LEDTS_FNCTL_FNCOL_Msk;
fncol_read >>= LEDTS_FNCTL_FNCOL_Pos;
return fncol_read;
}
/**
* Set the number of LED column Enabled
*/
void XMC_LEDTS_SetNumOfLEDColumns(XMC_LEDTS_t *const ledts, uint8_t count)
{
XMC_ASSERT("XMC_LEDTS_SetNumOfLEDColumns:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
ledts->FNCTL &= ~(LEDTS_FNCTL_NR_LEDCOL_Msk);
ledts->FNCTL |= (count << LEDTS_FNCTL_NR_LEDCOL_Pos);
}
/**
* Reading recorded number of oscillation counts
*/
uint16_t XMC_LEDTS_ReadTSVAL(XMC_LEDTS_t *const ledts)
{
uint16_t no_of_oscillations;
XMC_ASSERT("XMC_LEDTS_Read_TSVAL:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
no_of_oscillations = (ledts->TSVAL & 0xFFFF);
return no_of_oscillations;
}
/**
* Programming of registers to adjust the size of oscillation window
*/
void XMC_LEDTS_SetOscillationWindow(XMC_LEDTS_t *const ledts, XMC_LEDTS_NUMBER_TS_INPUT_t touchpad, const uint8_t size)
{
uint32_t reg;
uint8_t reg_index = ((uint8_t)touchpad) >> 2;
uint8_t bit_shift_count = ((uint8_t)touchpad & 0x03) * 8;
XMC_ASSERT("XMC_LEDTS_Set_Oscillation_Window:Wrong Module Pointer", XMC_LEDTS_CHECK_KERNEL_PTR(ledts));
reg = ledts->TSCMP[reg_index];
reg &= (~(0xff << bit_shift_count));
reg |= size << bit_shift_count;
ledts->TSCMP[reg_index] = reg;
}
#endif /* LEDTS0 */

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/**
* @file xmc_posif.c
* @date 2017-02-25
*
* @cond
**********************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification,are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share
* modifications, enhancements or bug fixes with Infineon Technologies AG
* dave@infineon.com).
**********************************************************************************
*
* Change History
* --------------
*
* 2015-02-18:
* - Initial version
*
* 2015-02-20:
* - Driver description added <BR>
*
* 2015-04-30:
* - XMC_POSIF_Enable and XMC_POSIF_Disable APIs updated for POSIF1 peripheral check <BR>
*
* 2015-06-19:
* - Removed GetDriverVersion API <BR>
*
* 2017-02-25:
* - XMC_POSIF_Enable() and XMC_POSIF_Disable() fixed compilation warnings
*
* @endcond
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_posif.h>
/* POSIF is not available on XMC1100 and XMC1200 */
#if defined(POSIF0)
#include <xmc_scu.h>
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_POSIF_PCONF_INSEL_Msk (0x3fUL << POSIF_PCONF_INSEL0_Pos) /*< Mask for input pins selection */
#define XMC_POSIF_INSEL_MAX (4U) /*< Maximum possible input selector */
/*********************************************************************************************************************
* LOCAL ROUTINES
********************************************************************************************************************/
#ifdef XMC_ASSERT_ENABLE
__STATIC_INLINE bool XMC_POSIF_IsPeripheralValid(const XMC_POSIF_t *const peripheral)
{
bool tmp;
tmp = (peripheral == POSIF0);
#if defined(POSIF1)
tmp |= (peripheral == POSIF1);
#endif
return tmp;
}
#endif
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/* API to enable the POSIF module */
void XMC_POSIF_Enable(XMC_POSIF_t *const peripheral)
{
#if UC_FAMILY == XMC4
XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_CCU);
#endif
if (peripheral == POSIF0)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0);
#endif
}
#if defined(POSIF1)
else if (peripheral == POSIF1)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1);
#endif
}
#endif
else
{
XMC_ASSERT("XMC_POSIF_Disable:Invalid module pointer", 0);
}
}
/* API to disable the POSIF module */
void XMC_POSIF_Disable(XMC_POSIF_t *const peripheral)
{
if (peripheral == POSIF0)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0);
#endif
}
#if defined(POSIF1)
else if (peripheral == POSIF1)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF1);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF1);
#endif
}
#endif
else
{
XMC_ASSERT("XMC_POSIF_Disable:Invalid module pointer", 0);
}
}
/* API to initialize POSIF global resources */
void XMC_POSIF_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_CONFIG_t *const config)
{
XMC_ASSERT("XMC_POSIF_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral));
XMC_ASSERT("XMC_POSIF_Init:NULL Pointer", (config != (XMC_POSIF_CONFIG_t *)NULL) );
/* Enable the POSIF module */
XMC_POSIF_Enable(peripheral);
/* Stop POSIF */
XMC_POSIF_Stop(peripheral);
/* Program the operational mode, input selectors and debounce filter */
peripheral->PCONF = config->pconf;
}
/* API to initialize hall sensor interface */
XMC_POSIF_STATUS_t XMC_POSIF_HSC_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_HSC_CONFIG_t * const config)
{
XMC_POSIF_STATUS_t retval;
XMC_ASSERT("XMC_POSIF_HSC_Init:Invalid module pointer\n", XMC_POSIF_IsPeripheralValid(peripheral));
XMC_ASSERT("XMC_POSIF_HSC_Init:NULL Pointer\n", (config != (XMC_POSIF_HSC_CONFIG_t *)NULL) );
if (XMC_POSIF_MODE_HALL_SENSOR == (XMC_POSIF_MODE_t)((peripheral->PCONF) & (uint32_t)POSIF_PCONF_FSEL_Msk) )
{
peripheral->PCONF |= config->hall_config;
retval = XMC_POSIF_STATUS_OK;
}
else
{
retval = XMC_POSIF_STATUS_ERROR;
}
return retval;
}
/* API to initialize quadrature decoder interface */
XMC_POSIF_STATUS_t XMC_POSIF_QD_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_QD_CONFIG_t * const config)
{
uint8_t reg;
XMC_POSIF_STATUS_t retval;
XMC_ASSERT("XMC_POSIF_QD_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral));
XMC_ASSERT("XMC_POSIF_QD_Init:NULL Pointer", (config != (XMC_POSIF_QD_CONFIG_t *)NULL) );
reg = (uint8_t)((peripheral->PCONF) & (uint32_t)POSIF_PCONF_FSEL_Msk);
if (((uint32_t)XMC_POSIF_MODE_QD == reg) || ((uint32_t)XMC_POSIF_MODE_MCM_QD == reg))
{
/* Program the quadrature mode */
peripheral->PCONF |= (uint32_t)(config->mode) << POSIF_PCONF_QDCM_Pos;
peripheral->QDC = config->qdc;
retval = XMC_POSIF_STATUS_OK;
}
else
{
retval = XMC_POSIF_STATUS_ERROR;
}
return retval;
}
/* API to initialize multi-channel mode.
* This is used in Hall mode, standalone multi-channel mode and quadrature with multi-channel mode
*/
XMC_POSIF_STATUS_t XMC_POSIF_MCM_Init(XMC_POSIF_t *const peripheral, const XMC_POSIF_MCM_CONFIG_t * const config)
{
XMC_POSIF_STATUS_t retval;
XMC_ASSERT("XMC_POSIF_MCM_Init:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral));
XMC_ASSERT("XMC_POSIF_MCM_Init:NULL Pointer", (config != (XMC_POSIF_MCM_CONFIG_t *)NULL) );
if ((XMC_POSIF_MODE_t)((peripheral->PCONF) & (uint32_t)POSIF_PCONF_FSEL_Msk) != XMC_POSIF_MODE_QD)
{
peripheral->PCONF |= config->mcm_config;
retval = XMC_POSIF_STATUS_OK;
}
else
{
retval = XMC_POSIF_STATUS_ERROR;
}
return retval;
}
/* API to configure input source */
void XMC_POSIF_SelectInputSource (XMC_POSIF_t *const peripheral, const XMC_POSIF_INPUT_PORT_t input0,
const XMC_POSIF_INPUT_PORT_t input1, const XMC_POSIF_INPUT_PORT_t input2)
{
uint32_t reg;
XMC_ASSERT("XMC_POSIF_SelectInputSource:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral));
XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input0", (input0 < XMC_POSIF_INSEL_MAX));
XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input1", (input1 < XMC_POSIF_INSEL_MAX));
XMC_ASSERT("XMC_POSIF_SelectInputSource:Wrong input port input2", (input2 < XMC_POSIF_INSEL_MAX));
reg = (uint32_t)((((uint32_t)input0 << POSIF_PCONF_INSEL0_Pos) & (uint32_t)POSIF_PCONF_INSEL0_Msk) |
(((uint32_t)input1 << POSIF_PCONF_INSEL1_Pos) & (uint32_t)POSIF_PCONF_INSEL1_Msk) |
(((uint32_t)input2 << POSIF_PCONF_INSEL2_Pos) & (uint32_t)POSIF_PCONF_INSEL2_Msk));
peripheral->PCONF = ((peripheral->PCONF & ~(uint32_t)XMC_POSIF_PCONF_INSEL_Msk) | reg);
}
/* API to select an interrupt node */
void XMC_POSIF_SetInterruptNode(XMC_POSIF_t *const peripheral, const XMC_POSIF_IRQ_EVENT_t event, const XMC_POSIF_SR_ID_t sr)
{
uint32_t reg;
XMC_ASSERT("XMC_POSIF_SetInterruptNode:Invalid module pointer", XMC_POSIF_IsPeripheralValid(peripheral));
XMC_ASSERT("XMC_POSIF_SetInterruptNode:Wrong IRQ event", (event <= XMC_POSIF_IRQ_EVENT_PCLK) );
XMC_ASSERT("XMC_POSIF_SetInterruptNode:Wrong SR ID", (sr <= XMC_POSIF_SR_ID_1) );
reg = peripheral->PFLGE;
reg &= ~((uint32_t)1 << ((uint32_t)event + (uint32_t)POSIF_PFLGE_CHESEL_Pos));
reg |= (uint32_t)sr << ((uint32_t)event + (uint32_t)POSIF_PFLGE_CHESEL_Pos);
peripheral->PFLGE = reg;
}
#endif /* #if defined(POSIF0) */

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/**
* @file xmc_rtc.c
* @date 2015-05-19
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-06-20:
* - Removed GetDriverVersion API
*
* 2016-05-19:
* - Added XMC_RTC_SetTimeStdFormat() and XMC_RTC_SetAlarmStdFormat()
*
* @endcond
*
*/
/**
*
* @brief RTC driver for XMC microcontroller family.
*
*/
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include "xmc_scu.h"
#include "xmc_rtc.h"
/*********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#define XMC_RTC_MAXSECONDS (59U) /**< RTC time : Maximum seconds */
#define XMC_RTC_MAXMINUTES (59U) /**< RTC time : Maximum minutes */
#define XMC_RTC_MAXHOURS (23U) /**< RTC time : Maximum hours */
#define XMC_RTC_MAXDAYS (31U) /**< RTC time : Maximum days */
#define XMC_RTC_MAXDAYSOFWEEK (7U) /**< RTC time : Maximum days of week */
#define XMC_RTC_MAXMONTH (12U) /**< RTC time : Maximum month */
#define XMC_RTC_MAXYEAR (0xFFFFU) /**< RTC time : Maximum year */
#define XMC_RTC_MAXPRESCALER (0xFFFFU) /**< RTC time : Maximum prescaler */
#define XMC_RTC_YEAR_OFFSET (1900U) /**< RTC year offset : Year offset */
#if (UC_FAMILY == XMC4)
#define XMC_RTC_INIT_SEQUENCE (1U)
#endif
#if (UC_FAMILY == XMC1)
#define XMC_RTC_INIT_SEQUENCE (0U)
#endif
/*********************************************************************************************************************
* API IMPLEMENTATION
*********************************************************************************************************************/
/*
* Enables RTC peripheral to start counting time
*/
void XMC_RTC_Start(void)
{
while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->CTR |= (uint32_t)RTC_CTR_ENB_Msk;
}
/*
* Disables RTC peripheral to start counting time
*/
void XMC_RTC_Stop(void)
{
while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->CTR &= ~(uint32_t)RTC_CTR_ENB_Msk;
}
/*
* Sets the RTC module prescaler value
*/
void XMC_RTC_SetPrescaler(uint16_t prescaler)
{
XMC_ASSERT("XMC_RTC_SetPrescaler:Wrong prescaler value", (prescaler < XMC_RTC_MAXPRESCALER));
while((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_CTR_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->CTR = (RTC->CTR & ~(uint32_t)RTC_CTR_DIV_Msk) |
((uint32_t)prescaler << (uint32_t)RTC_CTR_DIV_Pos);
}
/*
* Sets the RTC_TIM0, RTC_TIM1 registers with time values
*/
void XMC_RTC_SetTime(const XMC_RTC_TIME_t *const time)
{
XMC_ASSERT("XMC_RTC_SetTime:Wrong seconds value", ((uint32_t)time->seconds < XMC_RTC_MAXSECONDS));
XMC_ASSERT("XMC_RTC_SetTime:Wrong minutes value", ((uint32_t)time->minutes < XMC_RTC_MAXMINUTES));
XMC_ASSERT("XMC_RTC_SetTime:Wrong hours value", ((uint32_t)time->hours < XMC_RTC_MAXHOURS));
XMC_ASSERT("XMC_RTC_SetTime:Wrong month day value", ((uint32_t)time->days < XMC_RTC_MAXDAYS));
XMC_ASSERT("XMC_RTC_SetTime:Wrong week day value", ((uint32_t)time->daysofweek < XMC_RTC_MAXDAYSOFWEEK));
XMC_ASSERT("XMC_RTC_SetTime:Wrong month value", ((uint32_t)time->month < XMC_RTC_MAXMONTH));
XMC_ASSERT("XMC_RTC_SetTime:Wrong year value", ((uint32_t)time->year < XMC_RTC_MAXYEAR));
#if (XMC_RTC_INIT_SEQUENCE == 1U)
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->TIM0 = time->raw0;
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->TIM1 = time->raw1;
#endif
#if (XMC_RTC_INIT_SEQUENCE == 0U)
while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk)) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->TIM0 = time->raw0;
RTC->TIM1 = time->raw1; ;
#endif
}
/*
* Gets the RTC module time value
*/
void XMC_RTC_GetTime(XMC_RTC_TIME_t *const time)
{
time->raw0 = RTC->TIM0;
time->raw1 = RTC->TIM1;
}
/*
* Sets the RTC module time values in standard format
*/
void XMC_RTC_SetTimeStdFormat(const struct tm *const stdtime)
{
XMC_RTC_TIME_t time;
time.seconds = stdtime->tm_sec;
time.minutes = stdtime->tm_min;
time.hours = stdtime->tm_hour;
time.days = stdtime->tm_mday - 1;
time.month = stdtime->tm_mon;
time.year = stdtime->tm_year + XMC_RTC_YEAR_OFFSET;
time.daysofweek = stdtime->tm_wday;
XMC_RTC_SetTime(&time);
}
/*
* Gets the RTC module time values in standard format
*/
void XMC_RTC_GetTimeStdFormat(struct tm *const stdtime)
{
XMC_RTC_TIME_t time;
time.raw0 = RTC->TIM0;
time.raw1 = RTC->TIM1;
stdtime->tm_sec = (int8_t)time.seconds;
stdtime->tm_min = (int8_t)time.minutes;
stdtime->tm_hour = (int8_t)time.hours;
stdtime->tm_mday = ((int8_t)time.days + (int8_t)1);
stdtime->tm_mon = (int8_t)time.month;
stdtime->tm_year = (int32_t)time.year - (int32_t)XMC_RTC_YEAR_OFFSET;
stdtime->tm_wday = (int8_t)time.daysofweek;
}
/*
* Sets the RTC module alarm time value
*/
void XMC_RTC_SetAlarm(const XMC_RTC_ALARM_t *const alarm)
{
XMC_ASSERT("XMC_RTC_SetAlarm:Wrong seconds value", ((uint32_t)alarm->seconds < XMC_RTC_MAXSECONDS));
XMC_ASSERT("XMC_RTC_SetAlarm:Wrong minutes value", ((uint32_t)alarm->minutes < XMC_RTC_MAXMINUTES));
XMC_ASSERT("XMC_RTC_SetAlarm:Wrong hours value", ((uint32_t)alarm->hours < XMC_RTC_MAXHOURS));
XMC_ASSERT("XMC_RTC_SetAlarm:Wrong days value", ((uint32_t)alarm->days < XMC_RTC_MAXDAYS));
XMC_ASSERT("XMC_RTC_SetAlarm:Wrong month value", ((uint32_t)alarm->month < XMC_RTC_MAXMONTH));
XMC_ASSERT("XMC_RTC_SetAlarm:Wrong year value", ((uint32_t)alarm->year < XMC_RTC_MAXYEAR));
#if (XMC_RTC_INIT_SEQUENCE == 1U)
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->ATIM0 = alarm->raw0;
while ((XMC_SCU_GetMirrorStatus() & SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->ATIM1 = alarm->raw1;
#endif
#if (XMC_RTC_INIT_SEQUENCE == 0U)
while ((XMC_SCU_GetMirrorStatus() & (SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk | SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk)) != 0U)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
RTC->ATIM0 = alarm->raw0;
RTC->ATIM1 = alarm->raw1;
#endif
}
/*
* Gets the RTC module alarm time value
*/
void XMC_RTC_GetAlarm(XMC_RTC_ALARM_t *const alarm)
{
alarm->raw0 = RTC->ATIM0;
alarm->raw1 = RTC->ATIM1;
}
/*
* Sets the RTC module alarm time value in standard format
*/
void XMC_RTC_SetAlarmStdFormat(const struct tm *const stdtime)
{
XMC_RTC_ALARM_t alarm;
alarm.seconds = stdtime->tm_sec;
alarm.minutes = stdtime->tm_min;
alarm.hours = stdtime->tm_hour;
alarm.days = stdtime->tm_mday - 1;
alarm.month = stdtime->tm_mon;
alarm.year = stdtime->tm_year + XMC_RTC_YEAR_OFFSET;
XMC_RTC_SetAlarm(&alarm);
}
/*
* Gets the RTC module alarm time value in standard format
*/
void XMC_RTC_GetAlarmStdFormat(struct tm *const stdtime)
{
XMC_RTC_ALARM_t alarm;
alarm.raw0 = RTC->ATIM0;
alarm.raw1 = RTC->ATIM1;
stdtime->tm_sec = (int8_t)alarm.seconds;
stdtime->tm_min = (int8_t)alarm.minutes;
stdtime->tm_hour = (int8_t)alarm.hours;
stdtime->tm_mday = ((int8_t)alarm.days + (int8_t)1);
stdtime->tm_mon = (int8_t)alarm.month;
stdtime->tm_year = (int32_t)alarm.year - (int32_t)XMC_RTC_YEAR_OFFSET;
}
/*
* Gets the RTC periodic and alarm event(s) status
*/
uint32_t XMC_RTC_GetEventStatus(void)
{
return RTC->STSSR;
}

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/**
* @file xmc_sdmmc.c
* @date 2016-07-11
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
* - Removed GetDriverVersion API <br>
*
* 2015-06-20:
* - Removed definition of GetDriverVersion API <br>
*
* 2016-03-14:
* - Values are directly assigned to the int status registers <br>
*
* 2016-07-11:
* - XMC_SDMMC_SetDataTransferMode() shall not invoke SetDateLineTimeout() <br>
*
* @endcond
*/
/**
* @addtogroup XMClib
* @{
*/
/**
* @addtogroup SDMMC
* @brief SDMMC driver
* @{
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include "xmc_sdmmc.h"
/*
* The SDMMC peripheral is only available on the
* XMC4500. The SDMMC definition can be found in
* the XMC4500.h (device header file).
*/
#if defined (SDMMC)
#include "xmc_scu.h"
/*******************************************************************************
* MACROS
*******************************************************************************/
/*
* Check for valid SDMMC error events <br>
*
* This macro is used in the LLD for assertion checks (XMC_ASSERT).
*/
#define XMC_SDMMC_CHECK_ERROR_EVENT(e)\
((e == XMC_SDMMC_CMD_TIMEOUT_ERR) ||\
(e == XMC_SDMMC_CMD_CRC_ERR) ||\
(e == XMC_SDMMC_CMD_END_BIT_ERR) ||\
(e == XMC_SDMMC_CMD_IND_ERR) ||\
(e == XMC_SDMMC_DATA_TIMEOUT_ERR) ||\
(e == XMC_SDMMC_DATA_CRC_ERR) ||\
(e == XMC_SDMMC_DATA_END_BIT_ERR) ||\
(e == XMC_SDMMC_CURRENT_LIMIT_ERR) ||\
(e == XMC_SDMMC_ACMD_ERR) ||\
(e == XMC_SDMMC_TARGET_RESP_ERR))
/*
* Check for valid SDMMC normal events <br>
*
* This macro is used in the LLD for assertion checks (XMC_ASSERT).
*/
#define XMC_SDMMC_CHECK_NORMAL_EVENT(e)\
((e == XMC_SDMMC_CMD_COMPLETE) ||\
(e == XMC_SDMMC_TX_COMPLETE) ||\
(e == XMC_SDMMC_BLOCK_GAP_EVENT) ||\
(e == XMC_SDMMC_BUFFER_WRITE_READY) ||\
(e == XMC_SDMMC_BUFFER_READ_READY) ||\
(e == XMC_SDMMC_CARD_INS) ||\
(e == XMC_SDMMC_CARD_REMOVAL) ||\
(e == XMC_SDMMC_CARD_INT))
/*
* Check for both normal and error events <br>
*
* This macro is used in the LLD for assertion checks (XMC_ASSERT).
*/
#define XMC_SDMMC_CHECK_EVENT(e)\
((XMC_SDMMC_CHECK_NORMAL_EVENT(e)) ||\
(XMC_SDMMC_CHECK_ERROR_EVENT(e)))
/*
* Check for valid SDMMC wakeup events <br>
*
* This macro is used in the LLD for assertion checks (XMC_ASSERT).
*/
#define XMC_SDMMC_CHECK_WAKEUP_EVENT(w)\
((w == XMC_SDMMC_WAKEUP_EN_CARD_INT) ||\
(w == XMC_SDMMC_WAKEUP_EN_CARD_INS) ||\
(w == XMC_SDMMC_WAKEUP_EN_CARD_REM))
/*
* Check for valid SDMMC software reset modes <br>
*
* This macro is used in the LLD for assertion checks (XMC_ASSERT).
*/
#define XMC_SDMMC_CHECK_SW_RESET_MODE(m)\
((m == XMC_SDMMC_SW_RESET_ALL) ||\
(m == XMC_SDMMC_SW_RST_CMD_LINE) ||\
(m == XMC_SDMMC_SW_RST_DAT_LINE))
/*
* Check for valid SDMMC transfer modes <br>
*
* This macro is used in the LLD for assertion checks (XMC_ASSERT).
*/
#define XMC_SDMMC_CHECK_TRANSFER_MODE(m)\
((m == XMC_SDMMC_TRANSFER_MODE_TYPE_SINGLE) ||\
(m == XMC_SDMMC_TRANSFER_MODE_TYPE_INFINITE) ||\
(m == XMC_SDMMC_TRANSFER_MODE_TYPE_MULTIPLE) ||\
(m == XMC_SDMMC_TRANSFER_MODE_TYPE_STOP_MULTIPLE))
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
/* Get power status of the SDMMC peripheral */
bool XMC_SDMMC_GetPowerStatus(XMC_SDMMC_t *const sdmmc)
{
XMC_ASSERT("XMC_SDMMC_GetPowerStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
return (bool)(sdmmc->POWER_CTRL & SDMMC_POWER_CTRL_SD_BUS_POWER_Msk);
}
/*
* De-assert the peripheral reset. The SDMMC peripheral
* needs to be initialized
*/
void XMC_SDMMC_Enable(XMC_SDMMC_t *const sdmmc)
{
XMC_ASSERT("XMC_SDMMC_Enable: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_SDMMC);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_SDMMC);
#endif
}
/* Assert the peripheral reset */
void XMC_SDMMC_Disable(XMC_SDMMC_t *const sdmmc)
{
XMC_ASSERT("XMC_SDMMC_Disable: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_SDMMC);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_SDMMC);
#endif
}
/* Initialize SDMMC peripheral */
XMC_SDMMC_STATUS_t XMC_SDMMC_Init(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_CONFIG_t *config)
{
XMC_ASSERT("XMC_SDMMC_Init: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
XMC_ASSERT("XMC_SDMMC_Init: Invalid clock divider value", XMC_SDMMC_CHECK_SDCLK_FREQ(config->clock_divider));
XMC_ASSERT("XMC_SDMMC_Init: Invalid bus width", XMC_SDMMC_CHECK_DATA_LINES(config->bus_width));
/* Enable SDMMC peripheral */
XMC_SDMMC_Enable(sdmmc);
/* Write internal clock divider register */
sdmmc->CLOCK_CTRL |= (uint16_t)((uint32_t)config->clock_divider << SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos);
/* Set bus width */
sdmmc->HOST_CTRL = (uint8_t)((sdmmc->HOST_CTRL & (uint8_t)~SDMMC_HOST_CTRL_DATA_TX_WIDTH_Msk) |
((uint8_t)config->bus_width << SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos));
return XMC_SDMMC_STATUS_SUCCESS;
}
/* Enable event status */
void XMC_SDMMC_EnableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event)
{
XMC_ASSERT("XMC_SDMMC_EnableEventStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
/* Set INT status enable register */
sdmmc->EN_INT_STATUS_NORM |= (uint16_t)event;
sdmmc->EN_INT_STATUS_ERR |= (uint16_t)(event >> 16U);
}
/* Disable event status */
void XMC_SDMMC_DisableEventStatus(XMC_SDMMC_t *const sdmmc, uint32_t event)
{
XMC_ASSERT("XMC_SDMMC_DisableEventStatus: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
/* Clear INT status enable register */
sdmmc->EN_INT_STATUS_NORM &= (uint16_t)~event;
sdmmc->EN_INT_STATUS_ERR &= (uint16_t)~(event >> 16U);
}
/* Enable SDMMC event */
void XMC_SDMMC_EnableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event)
{
XMC_ASSERT("XMC_SDMMC_EnableEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
XMC_SDMMC_EnableEventStatus(sdmmc, event);
sdmmc->EN_INT_SIGNAL_NORM |= (uint16_t)event;
sdmmc->EN_INT_SIGNAL_ERR |= (uint16_t)(event >> 16U);
}
/* Disable SDMMC event without disabling event status */
void XMC_SDMMC_DisableEvent(XMC_SDMMC_t *const sdmmc, uint32_t event)
{
XMC_ASSERT("XMC_SDMMC_DisableEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
/* Clear INT signal enable register */
sdmmc->EN_INT_SIGNAL_NORM &= (uint16_t)~event;
sdmmc->EN_INT_SIGNAL_ERR &= (uint16_t)~(event >> 16U);
}
/* Clear SDMMC event(s) */
void XMC_SDMMC_ClearEvent(XMC_SDMMC_t *const sdmmc, uint32_t event)
{
XMC_ASSERT("XMC_SDMMC_ClearEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
XMC_ASSERT("XMC_SDMMC_ClearEvent: Invalid bit-field", !(event & XMC_SDMMC_TARGET_RESP_ERR));
sdmmc->INT_STATUS_NORM = (uint16_t)event;
sdmmc->INT_STATUS_ERR = (uint16_t)(event >> 16U);
}
/* Get the status of an SDMMC event */
bool XMC_SDMMC_GetEvent(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_EVENT_t event)
{
bool status;
XMC_ASSERT("XMC_SDMMC_GetEvent: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
XMC_ASSERT("XMC_SDMMC_GetEvent: Invalid SDMMC event", XMC_SDMMC_CHECK_EVENT(event));
if (event < XMC_SDMMC_CMD_TIMEOUT_ERR)
{
status = (bool)(sdmmc->INT_STATUS_NORM & (uint16_t)event);
}
else
{
status = (bool)(sdmmc->INT_STATUS_ERR & (uint16_t)((uint32_t)event >> 16U));
}
return status;
}
/* Read R2 response (CID, CSD register) */
void XMC_SDMMC_GetR2Response(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_RESPONSE_t *const response)
{
XMC_ASSERT("XMC_SDMMC_GetR2Response: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
response->response_0 = sdmmc->RESPONSE[0];
response->response_2 = sdmmc->RESPONSE[1];
response->response_4 = sdmmc->RESPONSE[2];
response->response_6 = sdmmc->RESPONSE[3];
}
/* Send SDMMC command */
XMC_SDMMC_STATUS_t XMC_SDMMC_SendCommand(XMC_SDMMC_t *const sdmmc, const XMC_SDMMC_COMMAND_t *cmd, uint32_t arg)
{
XMC_ASSERT("XMC_SDMMC_SendCommand: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
sdmmc->ARGUMENT1 = arg;
sdmmc->COMMAND = (uint16_t)(*(uint16_t *)cmd);
return XMC_SDMMC_STATUS_SUCCESS;
}
/* Set data transfer mode */
void XMC_SDMMC_SetDataTransferMode(XMC_SDMMC_t *const sdmmc, XMC_SDMMC_TRANSFER_MODE_t *const response)
{
XMC_ASSERT("XMC_SDMMC_SetDataTransferMode: Invalid module pointer", XMC_SDMMC_CHECK_MODULE_PTR(sdmmc));
XMC_ASSERT("XMC_SDMMC_SetDataTransferMode: Invalid transfer type", XMC_SDMMC_CHECK_TRANSFER_MODE(response->type));
/* Block size */
sdmmc->BLOCK_SIZE = (uint16_t)(response->block_size);
/* Number of blocks */
sdmmc->BLOCK_COUNT = (uint16_t)(response->num_blocks);
/* Type of data transfer: single, infinite, multiple or stop multiple */
sdmmc->TRANSFER_MODE = (uint16_t)((sdmmc->TRANSFER_MODE & (uint16_t)~SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Msk) |
((uint16_t)response->type));
/*
* Clear block count enable bit; that's only valid for
* a multi-block transfer
*/
if (response->type == XMC_SDMMC_TRANSFER_MODE_TYPE_SINGLE)
{
sdmmc->TRANSFER_MODE &= (uint16_t)~SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Msk;
}
/* Auto CMD configuration */
sdmmc->TRANSFER_MODE = (uint16_t)((sdmmc->TRANSFER_MODE & (uint16_t)~SDMMC_TRANSFER_MODE_ACMD_EN_Msk) |
((uint16_t)response->auto_cmd << SDMMC_TRANSFER_MODE_ACMD_EN_Pos));
}
#endif /* #if defined (SDMMC) */
/**
* @}
*/
/**
* @}
*/

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/**
* @file xmc_spi.c
* @date 2015-11-04
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
* - Modified XMC_SPI_CH_Stop() API for not setting to IDLE the channel if it is busy
* - Modified XMC_SPI_CH_SetInterwordDelay() implementation in order to gain accuracy <br>
*
* 2015-06-20:
* - Removed GetDriverVersion API <br>
*
* 2015-09-01:
* - Modified XMC_SPI_CH_EnableEvent() and XMC_SPI_CH_DisableEvent() for supporting multiple events configuration <br>
*
* 2015-11-04:
* - Modified the check of XMC_USIC_CH_GetTransmitBufferStatus() in the XMC_SPI_CH_Transmit() flag <br>
* @endcond
*
*/
/**
*
* @brief SPI driver for XMC microcontroller family
*
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include <xmc_scu.h>
#include <xmc_spi.h>
/*********************************************************************************************************************
* MACROS
********************************************************************************************************************/
#define XMC_SPI_CH_OVERSAMPLING (2UL)
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/* Initializes the selected SPI channel with the config structure. */
void XMC_SPI_CH_Init(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_CONFIG_t *const config)
{
XMC_USIC_CH_Enable(channel);
if(config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER)
{
/* Configure baud rate */
(void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, XMC_SPI_CH_OVERSAMPLING);
}
/* Configuration of USIC Shift Control */
/* Transmission Mode (TRM) = 1 */
/* Passive Data Level (PDL) = 1 */
channel->SCTR = USIC_CH_SCTR_PDL_Msk |
(0x1UL << USIC_CH_SCTR_TRM_Pos) |
(0x3fUL << USIC_CH_SCTR_FLE_Pos)|
(0x7UL << USIC_CH_SCTR_WLE_Pos);
/* Configuration of USIC Transmit Control/Status Register */
/* TBUF Data Enable (TDEN) = 1 */
/* TBUF Data Single Shot Mode (TDSSM) = 1 */
channel->TCSR = (uint32_t)(USIC_CH_TCSR_HPCMD_Msk |
(0x01UL << USIC_CH_TCSR_TDEN_Pos) |
USIC_CH_TCSR_TDSSM_Msk);
if(config->bus_mode == XMC_SPI_CH_BUS_MODE_MASTER)
{
/* Configuration of Protocol Control Register */
channel->PCR_SSCMode = (uint32_t)(USIC_CH_PCR_SSCMode_MSLSEN_Msk |
USIC_CH_PCR_SSCMode_SELCTR_Msk |
(uint32_t)config->selo_inversion |
USIC_CH_PCR_SSCMode_FEM_Msk);
}
/* Clear protocol status */
channel->PSCR = 0xFFFFFFFFUL;
/* Set parity settings */
channel->CCR = (uint32_t)config->parity_mode;
}
XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate(XMC_USIC_CH_t *const channel, const uint32_t rate)
{
XMC_SPI_CH_STATUS_t status;
status = XMC_SPI_CH_STATUS_ERROR;
if (rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 1U))
{
if (XMC_USIC_CH_SetBaudrate(channel, rate, XMC_SPI_CH_OVERSAMPLING) == XMC_USIC_CH_STATUS_OK)
{
status = XMC_SPI_CH_STATUS_OK;
}
}
return status;
}
/* Enable the selected slave signal by setting (SELO) bits in PCR register. */
void XMC_SPI_CH_EnableSlaveSelect(XMC_USIC_CH_t *const channel, const XMC_SPI_CH_SLAVE_SELECT_t slave)
{
/* Configuration of Protocol Control Register */
channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SELO_Msk;
channel->PCR_SSCMode |= (uint32_t)slave;
}
/* Disable the slave signals by clearing (SELO) bits in PCR register. */
void XMC_SPI_CH_DisableSlaveSelect(XMC_USIC_CH_t *const channel)
{
XMC_SPI_CH_ClearStatusFlag(channel, (uint32_t)XMC_SPI_CH_STATUS_FLAG_MSLS);
/* Configuration of Protocol Control Register */
channel->PCR_SSCMode &= (uint32_t)~USIC_CH_PCR_SSCMode_SELO_Msk;
}
/* Puts the data into FIFO if FIFO mode is enabled or else into standard buffers, by setting the proper mode. */
void XMC_SPI_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_SPI_CH_MODE_t mode)
{
channel->CCR = (channel->CCR & (uint32_t)(~USIC_CH_CCR_HPCEN_Msk)) |
(((uint32_t) mode << USIC_CH_CCR_HPCEN_Pos) & (uint32_t)USIC_CH_CCR_HPCEN_Msk);
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0U)
{
while((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) == (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY)
{
}
XMC_SPI_CH_ClearStatusFlag(channel, (uint32_t)XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
channel->TBUF[mode] = data;
}
else
{
channel->IN[mode] = data;
}
}
/* Reads the data from the buffers based on the FIFO mode selection. */
uint16_t XMC_SPI_CH_GetReceivedData(XMC_USIC_CH_t *const channel)
{
uint16_t retval;
/* Check FIFO size */
if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U)
{
retval = (uint16_t)channel->RBUF;
}
else
{
retval = (uint16_t)channel->OUTR;
}
return retval;
}
/* Configures the inter word delay by setting PCR.PCTQ1, PCR.DCTQ1 bit fields. */
void XMC_SPI_CH_SetInterwordDelay(XMC_USIC_CH_t *const channel,uint32_t tinterword_delay_us)
{
uint32_t peripheral_clock;
uint32_t pdiv;
uint32_t step;
uint32_t fFD;
uint32_t fpdiv;
uint32_t divider_factor1 = 0U;
uint32_t divider_factor2 = 32U;
uint32_t divider_factor1_int = 0U;
uint32_t divider_factor1_int_min = 4U;
uint32_t divider_factor1_frac_min =100U;
uint32_t divider_factor1_frac = 0U;
uint32_t divider_factor2_temp = 0U;
peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency();
pdiv = (uint32_t)(channel->BRG & USIC_CH_BRG_PDIV_Msk) >> USIC_CH_BRG_PDIV_Pos;
step = (uint32_t)(channel->FDR & USIC_CH_FDR_STEP_Msk) >> USIC_CH_FDR_STEP_Pos;
fFD = (uint32_t)((peripheral_clock >> 10U) * step);
fpdiv= fFD/(1U+pdiv);
if(tinterword_delay_us < (128000000/fpdiv))
{
for(divider_factor2_temp = 32U; divider_factor2_temp > 0U; --divider_factor2_temp)
{
divider_factor1 = (tinterword_delay_us*fpdiv)/(divider_factor2_temp*10000);
divider_factor1_frac = divider_factor1%100U;
if(divider_factor1_frac > 50)
{
divider_factor1_int = (divider_factor1/100U)+1;
divider_factor1_frac = (divider_factor1_int*100)-divider_factor1;
}
else
{
divider_factor1_int = (divider_factor1/100U);
}
if ((divider_factor1_int < 5U) && (divider_factor1_int > 0) && (divider_factor1_frac < divider_factor1_frac_min))
{
divider_factor1_frac_min = divider_factor1_frac;
divider_factor1_int_min = divider_factor1_int;
divider_factor2= divider_factor2_temp;
}
}
}
channel->PCR_SSCMode = (uint32_t)((channel->PCR_SSCMode) & (~(USIC_CH_PCR_SSCMode_DCTQ1_Msk |
USIC_CH_PCR_SSCMode_PCTQ1_Msk |
USIC_CH_PCR_SSCMode_CTQSEL1_Msk))) |
(((divider_factor1_int_min - 1) << USIC_CH_PCR_SSCMode_PCTQ1_Pos) & (uint32_t)USIC_CH_PCR_SSCMode_PCTQ1_Msk) |
(((divider_factor2 - 1 ) << USIC_CH_PCR_SSCMode_DCTQ1_Pos) & (uint32_t)USIC_CH_PCR_SSCMode_DCTQ1_Msk);
}
XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop(XMC_USIC_CH_t *const channel)
{
XMC_SPI_CH_STATUS_t status = XMC_SPI_CH_STATUS_OK;
if (((uint32_t)XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t)XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U)
{
status = XMC_SPI_CH_STATUS_BUSY;
}
else
{
/* USIC channel in IDLE mode */
XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
}
return status;
}
void XMC_SPI_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR |= (event&0x1fc00U);
channel->PCR_SSCMode |= ((event << 13U) & 0xe000U);
}
void XMC_SPI_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR &= (uint32_t)~(event&0x1fc00U);
channel->PCR_SSCMode &= (uint32_t)~((event << 13U) & 0xe000U);
}

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/**
* @file xmc_uart.c
* @date 2016-07-22
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-05-20:
* - xmc_uart_ch_stop API implementation corrected.
* - Modified XMC_UART_CH_Stop() API for not setting to IDLE the channel if it is busy <br>
*
* 2015-06-20:
* - Removed GetDriverVersion API <br>
*
* 2015-09-01:
* - Modified XMC_UART_CH_EnableEvent() and XMC_UART_CH_DisableEvent() for supporting multiple events configuration <br>
*
* 2016-07-22:
* - Modified XMC_UART_CH_Init() to enable transfer status BUSY
* - Modified XMC_UART_CH_Stop() to check for transfer status
*
* @endcond
*
*/
/*********************************************************************************************************************
* HEADER FILES
*********************************************************************************************************************/
#include <xmc_scu.h>
#include <xmc_uart.h>
/*********************************************************************************************************************
* MACROS
*********************************************************************************************************************/
#define XMC_UART_CH_OVERSAMPLING (16UL)
#define XMC_UART_CH_OVERSAMPLING_MIN_VAL (4UL)
/*********************************************************************************************************************
* API IMPLEMENTATION
*********************************************************************************************************************/
void XMC_UART_CH_Init(XMC_USIC_CH_t *channel, const XMC_UART_CH_CONFIG_t *const config)
{
uint32_t oversampling = XMC_UART_CH_OVERSAMPLING;
/* USIC channel switched on*/
XMC_USIC_CH_Enable(channel);
if(config->oversampling != 0U)
{
oversampling = (uint32_t)config->oversampling;
}
/* Configure baud rate */
(void)XMC_USIC_CH_SetBaudrate(channel, config->baudrate, oversampling);
/* Configure frame format
* Configure the number of stop bits
* Pulse length is set to 0 to have standard UART signaling,
* i.e. the 0 level is signaled during the complete bit time
* Sampling point set equal to the half of the oversampling period
* Enable Sample Majority Decision
* Enable Transfer Status BUSY
*/
channel->PCR_ASCMode = (uint32_t)(((config->stop_bits - 1UL) << USIC_CH_PCR_ASCMode_STPB_Pos) |
(((oversampling >> 1UL) + 1UL) << USIC_CH_PCR_ASCMode_SP_Pos) |
USIC_CH_PCR_ASCMode_SMD_Msk |
USIC_CH_PCR_ASCMode_RSTEN_Msk | USIC_CH_PCR_ASCMode_TSTEN_Msk);
/* Set passive data level, high
Set word length. Data bits - 1
If frame length is > 0, frame_lemgth-1; else, FLE = WLE (Data bits - 1)
Transmission Mode: The shift control signal is considered active if it
is at 1-level. This is the setting to be programmed to allow data transfers */
channel->SCTR = (uint32_t)((((uint32_t)config->data_bits - 1UL) << USIC_CH_SCTR_WLE_Pos) |
((0x1UL << USIC_CH_SCTR_TRM_Pos) | USIC_CH_SCTR_PDL_Msk));
if (config->frame_length != 0U)
{
channel->SCTR |= (uint32_t)(((uint32_t)config->frame_length - 1UL) << USIC_CH_SCTR_FLE_Pos);
}
else
{
channel->SCTR |= (uint32_t)(((uint32_t)config->data_bits - 1UL) << USIC_CH_SCTR_FLE_Pos);
}
/* Enable transfer buffer */
channel->TCSR = (0x1UL << USIC_CH_TCSR_TDEN_Pos) |
USIC_CH_TCSR_TDSSM_Msk;
/* Clear protocol status */
channel->PSCR = 0xFFFFFFFFUL;
/* Set parity settings */
channel->CCR = (uint32_t)config->parity_mode;
}
XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling)
{
XMC_UART_CH_STATUS_t status;
status = XMC_UART_CH_STATUS_ERROR;
if ((rate <= (XMC_SCU_CLOCK_GetPeripheralClockFrequency() >> 2U)) && (oversampling >= XMC_UART_CH_OVERSAMPLING_MIN_VAL))
{
if (XMC_USIC_CH_SetBaudrate(channel, rate, oversampling) == XMC_USIC_CH_STATUS_OK)
{
status = XMC_UART_CH_STATUS_OK;
}
}
return status;
}
void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data)
{
/* Check FIFO size */
if ((channel->TBCTR & USIC_CH_TBCTR_SIZE_Msk) == 0UL)
{
/* Wait till the Transmit Buffer is free for transmission */
while(XMC_USIC_CH_GetTransmitBufferStatus(channel) == XMC_USIC_CH_TBUF_STATUS_BUSY)
{
}
/* Clear the Transmit Buffer indication flag */
XMC_UART_CH_ClearStatusFlag(channel, (uint32_t)XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION);
/*Transmit data */
channel->TBUF[0U] = data;
}
else
{
channel->IN[0U] = data;
}
}
uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel)
{
uint16_t retval;
/* Check FIFO size */
if ((channel->RBCTR & USIC_CH_RBCTR_SIZE_Msk) == 0U)
{
retval = (uint16_t)channel->RBUF;
}
else
{
retval = (uint16_t)channel->OUTR;
}
return retval;
}
XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel)
{
XMC_UART_CH_STATUS_t status = XMC_UART_CH_STATUS_OK;
if (((XMC_USIC_CH_GetTransmitBufferStatus(channel) & (uint32_t) XMC_USIC_CH_TBUF_STATUS_BUSY) != 0U) ||
((XMC_UART_CH_GetStatusFlag(channel) & XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY) != 0))
{
status = XMC_UART_CH_STATUS_BUSY;
}
else
{
/* USIC channel in IDLE mode */
XMC_USIC_CH_SetMode(channel, XMC_USIC_CH_OPERATING_MODE_IDLE);
}
return status;
}
void XMC_UART_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR |= (event&0x1fc00U);
channel->PCR_ASCMode |= (event&0xf8U);
}
void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event)
{
channel->CCR &= (uint32_t)~(event&0x1fc00U);
channel->PCR_ASCMode &= (uint32_t)~(event&0xf8U);
}

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/**
* @file xmc_usic.c
* @date 2015-09-01
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial draft <br>
* - Documentation improved <br>
*
* 2015-05-08:
* - Clearing bit fields PDIV, PCTQ, PPPEN in XMC_USIC_CH_SetBaudrate() API <br>
*
* 2015-06-20:
* - Removed version macros and declaration of GetDriverVersion API <br>
*
* 2015-08-27:
* - Added APIs for external input for BRG configuration:XMC_USIC_CH_ConfigExternalInputSignalToBRG() <br>
*
* 2015-08-28:
* - Added asserts to XMC_USIC_CH_ConfigExternalInputSignalToBRG() <br>
*
* 2015-09-01:
* - Fixed warning in the asserts <br>
*
* @endcond
*
*/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include "xmc_usic.h"
#include "xmc_scu.h"
/*******************************************************************************
* MACROS
*******************************************************************************/
#define USIC_CH_INPR_Msk (0x7UL)
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
void XMC_USIC_CH_Enable(XMC_USIC_CH_t *const channel)
{
XMC_ASSERT("XMC_USIC_CH_Enable: channel not valid", XMC_USIC_IsChannelValid(channel));
if ((channel == XMC_USIC0_CH0) || (channel == XMC_USIC0_CH1))
{
XMC_USIC_Enable(XMC_USIC0);
}
#if defined(USIC1)
else if((channel == XMC_USIC1_CH0) || (channel == XMC_USIC1_CH1))
{
XMC_USIC_Enable(XMC_USIC1);
}
#endif
#if defined(USIC2)
else if((channel == XMC_USIC2_CH0) || (channel == XMC_USIC2_CH1))
{
XMC_USIC_Enable(XMC_USIC2);
}
#endif
else
{
XMC_ASSERT("USIC module not available", 0U/*Always*/);
}
/* USIC channel switched on*/
channel->KSCFG = (USIC_CH_KSCFG_MODEN_Msk | USIC_CH_KSCFG_BPMODEN_Msk);
while ((channel->KSCFG & USIC_CH_KSCFG_MODEN_Msk) == 0U)
{
/* Wait till the channel is enabled */
}
/* Set USIC channel in IDLE mode */
channel->CCR &= (uint32_t)~USIC_CH_CCR_MODE_Msk;
}
void XMC_USIC_CH_Disable(XMC_USIC_CH_t *const channel)
{
channel->KSCFG = (uint32_t)((channel->KSCFG & (~USIC_CH_KSCFG_MODEN_Msk)) | USIC_CH_KSCFG_BPMODEN_Msk);
}
XMC_USIC_CH_STATUS_t XMC_USIC_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t rate, uint32_t oversampling)
{
XMC_USIC_CH_STATUS_t status;
uint32_t peripheral_clock;
uint32_t clock_divider;
uint32_t clock_divider_min;
uint32_t pdiv;
uint32_t pdiv_int;
uint32_t pdiv_int_min;
uint32_t pdiv_frac;
uint32_t pdiv_frac_min;
/* The rate and peripheral clock are divided by 100 to be able to use only 32bit arithmetic */
if ((rate >= 100U) && (oversampling != 0U))
{
peripheral_clock = XMC_SCU_CLOCK_GetPeripheralClockFrequency() / 100U;
rate = rate / 100U;
clock_divider_min = 1U;
pdiv_int_min = 1U;
pdiv_frac_min = 0x3ffU;
for(clock_divider = 1023U; clock_divider > 0U; --clock_divider)
{
pdiv = ((peripheral_clock * clock_divider) / (rate * oversampling));
pdiv_int = pdiv >> 10U;
pdiv_frac = pdiv & 0x3ffU;
if ((pdiv_int < 1024U) && (pdiv_frac < pdiv_frac_min))
{
pdiv_frac_min = pdiv_frac;
pdiv_int_min = pdiv_int;
clock_divider_min = clock_divider;
}
}
channel->FDR = XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL |
(clock_divider_min << USIC_CH_FDR_STEP_Pos);
channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk |
USIC_CH_BRG_PDIV_Msk |
USIC_CH_BRG_PCTQ_Msk |
USIC_CH_BRG_PPPEN_Msk)) |
((oversampling - 1U) << USIC_CH_BRG_DCTQ_Pos) |
((pdiv_int_min - 1U) << USIC_CH_BRG_PDIV_Pos);
status = XMC_USIC_CH_STATUS_OK;
}
else
{
status = XMC_USIC_CH_STATUS_ERROR;
}
return status;
}
void XMC_USIC_CH_ConfigExternalInputSignalToBRG(XMC_USIC_CH_t *const channel,
const uint16_t pdiv,
const uint32_t oversampling,
const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode)
{
XMC_ASSERT("XMC_USIC_CH_ConfigExternalInputSignalToBRG: Divider out of range", ((1U < pdiv) || (pdiv < 1024U)));
XMC_ASSERT("XMC_USIC_CH_ConfigExternalInputSignalToBRG: Oversampling out of range", ((1U < oversampling) || (oversampling < 32U)));
/* Setting the external input frequency source through DX1 */
XMC_USIC_CH_SetBRGInputClockSource(channel, XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T);
/* Setting the trigger combination mode */
XMC_USIC_CH_SetInputTriggerCombinationMode(channel,XMC_USIC_CH_INPUT_DX1,combination_mode);
/* Configuring the dividers and oversampling */
channel->BRG = (channel->BRG & ~(USIC_CH_BRG_DCTQ_Msk |
USIC_CH_BRG_PDIV_Msk |
USIC_CH_BRG_PCTQ_Msk |
USIC_CH_BRG_PPPEN_Msk)) |
(((oversampling) - 1U) << USIC_CH_BRG_DCTQ_Pos) |
(((pdiv) - 1U) << USIC_CH_BRG_PDIV_Pos);
}
void XMC_USIC_CH_TXFIFO_Configure(XMC_USIC_CH_t *const channel,
const uint32_t data_pointer,
const XMC_USIC_CH_FIFO_SIZE_t size,
const uint32_t limit)
{
/* Disable FIFO */
channel->TBCTR &= (uint32_t)~USIC_CH_TBCTR_SIZE_Msk;
/* LOF = 0, A standard transmit buffer event occurs when the filling level equals the limit value and gets
* lower due to transmission of a data word
* STBTEN = 0, the trigger of the standard transmit buffer event is based on the transition of the fill level
* from equal to below the limit, not the fact being below
*/
channel->TBCTR = (uint32_t)(channel->TBCTR & (uint32_t)~(USIC_CH_TBCTR_LIMIT_Msk |
USIC_CH_TBCTR_DPTR_Msk |
USIC_CH_TBCTR_SIZE_Msk)) |
(uint32_t)((limit << USIC_CH_TBCTR_LIMIT_Pos) |
(data_pointer << USIC_CH_TBCTR_DPTR_Pos) |
((uint32_t)size << USIC_CH_TBCTR_SIZE_Pos));
}
void XMC_USIC_CH_RXFIFO_Configure(XMC_USIC_CH_t *const channel,
const uint32_t data_pointer,
const XMC_USIC_CH_FIFO_SIZE_t size,
const uint32_t limit)
{
/* Disable FIFO */
channel->RBCTR &= (uint32_t)~USIC_CH_RBCTR_SIZE_Msk;
/* LOF = 1, A standard receive buffer event occurs when the filling level equals the limit value and gets bigger
* due to the reception of a new data word
*/
channel->RBCTR = (uint32_t)((channel->RBCTR & (uint32_t)~(USIC_CH_RBCTR_LIMIT_Msk |
USIC_CH_RBCTR_DPTR_Msk |
USIC_CH_RBCTR_LOF_Msk)) |
((limit << USIC_CH_RBCTR_LIMIT_Pos) |
(data_pointer << USIC_CH_RBCTR_DPTR_Pos) |
((uint32_t)size << USIC_CH_RBCTR_SIZE_Pos) |
(uint32_t)USIC_CH_RBCTR_LOF_Msk));
}
void XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel,
const XMC_USIC_CH_FIFO_SIZE_t size,
const uint32_t limit)
{
/* Disable FIFO */
channel->TBCTR &= (uint32_t)~USIC_CH_TBCTR_SIZE_Msk;
/* STBTEN = 0, the trigger of the standard transmit buffer event is based on the transition of the fill level
* from equal to below the limit, not the fact being below
*/
channel->TBCTR = (uint32_t)((uint32_t)(channel->TBCTR & (uint32_t)~USIC_CH_TBCTR_LIMIT_Msk) |
(limit << USIC_CH_TBCTR_LIMIT_Pos) |
((uint32_t)size << USIC_CH_TBCTR_SIZE_Pos));
}
void XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(XMC_USIC_CH_t *const channel,
const XMC_USIC_CH_FIFO_SIZE_t size,
const uint32_t limit)
{
/* Disable FIFO */
channel->RBCTR &= (uint32_t)~USIC_CH_RBCTR_SIZE_Msk;
channel->RBCTR = (uint32_t)((uint32_t)(channel->RBCTR & (uint32_t)~USIC_CH_RBCTR_LIMIT_Msk) |
(limit << USIC_CH_RBCTR_LIMIT_Pos) |
((uint32_t)size << USIC_CH_RBCTR_SIZE_Pos));
}
void XMC_USIC_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
const XMC_USIC_CH_INTERRUPT_NODE_POINTER_t interrupt_node,
const uint32_t service_request)
{
channel->INPR = (uint32_t)((channel->INPR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) |
(service_request << (uint32_t)interrupt_node));
}
void XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
const XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node,
const uint32_t service_request)
{
channel->TBCTR = (uint32_t)((channel->TBCTR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) |
(service_request << (uint32_t)interrupt_node));
}
void XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
const XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t interrupt_node,
const uint32_t service_request)
{
channel->RBCTR = (uint32_t)((channel->RBCTR & (~(uint32_t)(USIC_CH_INPR_Msk << (uint32_t)interrupt_node))) |
(service_request << (uint32_t)interrupt_node));
}
void XMC_USIC_Enable(XMC_USIC_t *const usic)
{
if (usic == USIC0)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC0);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC0);
#endif
}
#if defined(USIC1)
else if (usic == USIC1)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC1);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC1);
#endif
}
#endif
#if defined(USIC2)
else if (usic == USIC2)
{
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC2);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC2);
#endif
}
#endif
else
{
XMC_ASSERT("USIC module not available", 0/*Always*/);
}
}
void XMC_USIC_Disable(XMC_USIC_t *const usic)
{
if (usic == (XMC_USIC_t *)USIC0)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC0);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC0);
#endif
}
#if defined(USIC1)
else if (usic == (XMC_USIC_t *)USIC1)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC1);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC1);
#endif
}
#endif
#if defined(USIC2)
else if (usic == (XMC_USIC_t *)USIC2)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USIC2);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USIC2);
#endif
}
#endif
else
{
XMC_ASSERT("USIC module not available", 0/*Always*/);
}
}

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/**
* @file xmc_wdt.c
* @date 2015-06-20
*
* @cond
*********************************************************************************************************************
* XMClib v2.1.12 - XMC Peripheral Driver Library
*
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
* Change History
* --------------
*
* 2015-02-20:
* - Initial <br>
*
* 2015-06-20:
* - Removed definition of GetDriverVersion API <br>
*
* @endcond
*/
/*********************************************************************************************************************
* HEADER FILES
********************************************************************************************************************/
#include "xmc_wdt.h"
#include "xmc_scu.h"
/*********************************************************************************************************************
* API IMPLEMENTATION
********************************************************************************************************************/
/* Enables watchdog clock and releases watchdog reset. */
void XMC_WDT_Enable(void)
{
#if UC_FAMILY == XMC4
XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_WDT);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_WDT);
#endif
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_WDT);
#endif
}
/* Disables watchdog clock and resets watchdog. */
void XMC_WDT_Disable(void)
{
#if defined(PERIPHERAL_RESET_SUPPORTED)
XMC_SCU_RESET_AssertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_WDT);
#endif
#if defined(CLOCK_GATING_SUPPORTED)
XMC_SCU_CLOCK_GatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_WDT);
#endif
#if UC_FAMILY == XMC4
XMC_SCU_CLOCK_DisableClock(XMC_SCU_CLOCK_WDT);
#endif
}
/* Initializes and configures watchdog with configuration data pointed by \a config. */
void XMC_WDT_Init(const XMC_WDT_CONFIG_t *const config)
{
XMC_WDT_Enable();
WDT->CTR = config->wdt_ctr;
WDT->WLB = config->window_lower_bound;
WDT->WUB = config->window_upper_bound;
}

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/*********************************************************************************************************************
* @file startup_XMC4700.S
* @brief CMSIS Core Device Startup File for Infineon XMC4700 Device Series
* @version V1.1
* @date 05 Jan 2016
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2015-2016, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
**************************** Change history ********************************
* V1.0,Sep, 03, 2015 JFT:Initial version
* V1.1,Jan, 05, 2016 JFT:Fix .reset section attributes
*
* @endcond
*/
/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */
.macro Entry Handler
.long \Handler
.endm
.macro Insert_ExceptionHandler Handler_Func
.weak \Handler_Func
.thumb_set \Handler_Func, Default_Handler
.endm
/* =============END : MACRO DEFINITION MACRO DEFINITION ================== */
/* ================== START OF VECTOR TABLE DEFINITION ====================== */
/* Vector Table - This gets programed into VTOR register by onchip BootROM */
.syntax unified
.section .reset, "a", %progbits
.align 2
.globl __Vectors
.type __Vectors, %object
__Vectors:
.long __initial_sp /* Top of Stack */
.long Reset_Handler /* Reset Handler */
Entry NMI_Handler /* NMI Handler */
Entry HardFault_Handler /* Hard Fault Handler */
Entry MemManage_Handler /* MPU Fault Handler */
Entry BusFault_Handler /* Bus Fault Handler */
Entry UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
Entry SVC_Handler /* SVCall Handler */
Entry DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
Entry PendSV_Handler /* PendSV Handler */
Entry SysTick_Handler /* SysTick Handler */
/* Interrupt Handlers for Service Requests (SR) from XMC4700 Peripherals */
Entry SCU_0_IRQHandler /* Handler name for SR SCU_0 */
Entry ERU0_0_IRQHandler /* Handler name for SR ERU0_0 */
Entry ERU0_1_IRQHandler /* Handler name for SR ERU0_1 */
Entry ERU0_2_IRQHandler /* Handler name for SR ERU0_2 */
Entry ERU0_3_IRQHandler /* Handler name for SR ERU0_3 */
Entry ERU1_0_IRQHandler /* Handler name for SR ERU1_0 */
Entry ERU1_1_IRQHandler /* Handler name for SR ERU1_1 */
Entry ERU1_2_IRQHandler /* Handler name for SR ERU1_2 */
Entry ERU1_3_IRQHandler /* Handler name for SR ERU1_3 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry PMU0_0_IRQHandler /* Handler name for SR PMU0_0 */
.long 0 /* Not Available */
Entry VADC0_C0_0_IRQHandler /* Handler name for SR VADC0_C0_0 */
Entry VADC0_C0_1_IRQHandler /* Handler name for SR VADC0_C0_1 */
Entry VADC0_C0_2_IRQHandler /* Handler name for SR VADC0_C0_1 */
Entry VADC0_C0_3_IRQHandler /* Handler name for SR VADC0_C0_3 */
Entry VADC0_G0_0_IRQHandler /* Handler name for SR VADC0_G0_0 */
Entry VADC0_G0_1_IRQHandler /* Handler name for SR VADC0_G0_1 */
Entry VADC0_G0_2_IRQHandler /* Handler name for SR VADC0_G0_2 */
Entry VADC0_G0_3_IRQHandler /* Handler name for SR VADC0_G0_3 */
Entry VADC0_G1_0_IRQHandler /* Handler name for SR VADC0_G1_0 */
Entry VADC0_G1_1_IRQHandler /* Handler name for SR VADC0_G1_1 */
Entry VADC0_G1_2_IRQHandler /* Handler name for SR VADC0_G1_2 */
Entry VADC0_G1_3_IRQHandler /* Handler name for SR VADC0_G1_3 */
Entry VADC0_G2_0_IRQHandler /* Handler name for SR VADC0_G2_0 */
Entry VADC0_G2_1_IRQHandler /* Handler name for SR VADC0_G2_1 */
Entry VADC0_G2_2_IRQHandler /* Handler name for SR VADC0_G2_2 */
Entry VADC0_G2_3_IRQHandler /* Handler name for SR VADC0_G2_3 */
Entry VADC0_G3_0_IRQHandler /* Handler name for SR VADC0_G3_0 */
Entry VADC0_G3_1_IRQHandler /* Handler name for SR VADC0_G3_1 */
Entry VADC0_G3_2_IRQHandler /* Handler name for SR VADC0_G3_2 */
Entry VADC0_G3_3_IRQHandler /* Handler name for SR VADC0_G3_3 */
Entry DSD0_0_IRQHandler /* Handler name for SR DSD0_0 */
Entry DSD0_1_IRQHandler /* Handler name for SR DSD0_1 */
Entry DSD0_2_IRQHandler /* Handler name for SR DSD0_2 */
Entry DSD0_3_IRQHandler /* Handler name for SR DSD0_3 */
Entry DSD0_4_IRQHandler /* Handler name for SR DSD0_4 */
Entry DSD0_5_IRQHandler /* Handler name for SR DSD0_5 */
Entry DSD0_6_IRQHandler /* Handler name for SR DSD0_6 */
Entry DSD0_7_IRQHandler /* Handler name for SR DSD0_7 */
Entry DAC0_0_IRQHandler /* Handler name for SR DAC0_0 */
Entry DAC0_1_IRQHandler /* Handler name for SR DAC0_0 */
Entry CCU40_0_IRQHandler /* Handler name for SR CCU40_0 */
Entry CCU40_1_IRQHandler /* Handler name for SR CCU40_1 */
Entry CCU40_2_IRQHandler /* Handler name for SR CCU40_2 */
Entry CCU40_3_IRQHandler /* Handler name for SR CCU40_3 */
Entry CCU41_0_IRQHandler /* Handler name for SR CCU41_0 */
Entry CCU41_1_IRQHandler /* Handler name for SR CCU41_1 */
Entry CCU41_2_IRQHandler /* Handler name for SR CCU41_2 */
Entry CCU41_3_IRQHandler /* Handler name for SR CCU41_3 */
Entry CCU42_0_IRQHandler /* Handler name for SR CCU42_0 */
Entry CCU42_1_IRQHandler /* Handler name for SR CCU42_1 */
Entry CCU42_2_IRQHandler /* Handler name for SR CCU42_2 */
Entry CCU42_3_IRQHandler /* Handler name for SR CCU42_3 */
Entry CCU43_0_IRQHandler /* Handler name for SR CCU43_0 */
Entry CCU43_1_IRQHandler /* Handler name for SR CCU43_1 */
Entry CCU43_2_IRQHandler /* Handler name for SR CCU43_2 */
Entry CCU43_3_IRQHandler /* Handler name for SR CCU43_3 */
Entry CCU80_0_IRQHandler /* Handler name for SR CCU80_0 */
Entry CCU80_1_IRQHandler /* Handler name for SR CCU80_1 */
Entry CCU80_2_IRQHandler /* Handler name for SR CCU80_2 */
Entry CCU80_3_IRQHandler /* Handler name for SR CCU80_3 */
Entry CCU81_0_IRQHandler /* Handler name for SR CCU81_0 */
Entry CCU81_1_IRQHandler /* Handler name for SR CCU81_1 */
Entry CCU81_2_IRQHandler /* Handler name for SR CCU81_2 */
Entry CCU81_3_IRQHandler /* Handler name for SR CCU81_3 */
Entry POSIF0_0_IRQHandler /* Handler name for SR POSIF0_0 */
Entry POSIF0_1_IRQHandler /* Handler name for SR POSIF0_1 */
Entry POSIF1_0_IRQHandler /* Handler name for SR POSIF1_0 */
Entry POSIF1_1_IRQHandler /* Handler name for SR POSIF1_1 */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
.long 0 /* Not Available */
Entry CAN0_0_IRQHandler /* Handler name for SR CAN0_0 */
Entry CAN0_1_IRQHandler /* Handler name for SR CAN0_1 */
Entry CAN0_2_IRQHandler /* Handler name for SR CAN0_2 */
Entry CAN0_3_IRQHandler /* Handler name for SR CAN0_3 */
Entry CAN0_4_IRQHandler /* Handler name for SR CAN0_4 */
Entry CAN0_5_IRQHandler /* Handler name for SR CAN0_5 */
Entry CAN0_6_IRQHandler /* Handler name for SR CAN0_6 */
Entry CAN0_7_IRQHandler /* Handler name for SR CAN0_7 */
Entry USIC0_0_IRQHandler /* Handler name for SR USIC0_0 */
Entry USIC0_1_IRQHandler /* Handler name for SR USIC0_1 */
Entry USIC0_2_IRQHandler /* Handler name for SR USIC0_2 */
Entry USIC0_3_IRQHandler /* Handler name for SR USIC0_3 */
Entry USIC0_4_IRQHandler /* Handler name for SR USIC0_4 */
Entry USIC0_5_IRQHandler /* Handler name for SR USIC0_5 */
Entry USIC1_0_IRQHandler /* Handler name for SR USIC1_0 */
Entry USIC1_1_IRQHandler /* Handler name for SR USIC1_1 */
Entry USIC1_2_IRQHandler /* Handler name for SR USIC1_2 */
Entry USIC1_3_IRQHandler /* Handler name for SR USIC1_3 */
Entry USIC1_4_IRQHandler /* Handler name for SR USIC1_4 */
Entry USIC1_5_IRQHandler /* Handler name for SR USIC1_5 */
Entry USIC2_0_IRQHandler /* Handler name for SR USIC2_0 */
Entry USIC2_1_IRQHandler /* Handler name for SR USIC2_1 */
Entry USIC2_2_IRQHandler /* Handler name for SR USIC2_2 */
Entry USIC2_3_IRQHandler /* Handler name for SR USIC2_3 */
Entry USIC2_4_IRQHandler /* Handler name for SR USIC2_4 */
Entry USIC2_5_IRQHandler /* Handler name for SR USIC2_5 */
Entry LEDTS0_0_IRQHandler /* Handler name for SR LEDTS0_0 */
.long 0 /* Not Available */
Entry FCE0_0_IRQHandler /* Handler name for SR FCE0_0 */
Entry GPDMA0_0_IRQHandler /* Handler name for SR GPDMA0_0 */
Entry SDMMC0_0_IRQHandler /* Handler name for SR SDMMC0_0 */
Entry USB0_0_IRQHandler /* Handler name for SR USB0_0 */
Entry ETH0_0_IRQHandler /* Handler name for SR ETH0_0 */
.long 0 /* Not Available */
Entry GPDMA1_0_IRQHandler /* Handler name for SR GPDMA1_0 */
.long 0 /* Not Available */
.size __Vectors, . - __Vectors
/* ================== END OF VECTOR TABLE DEFINITION ======================= */
/* ================== START OF VECTOR ROUTINES ============================= */
.align 1
.thumb
/* Reset Handler */
.thumb_func
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp,=__initial_sp
#ifndef __SKIP_SYSTEM_INIT
ldr r0, =SystemInit
blx r0
#endif
/* Initialize data
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
/* Zero initialized data
* Between symbol address __zero_table_start__ and __zero_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*
* Define __SKIP_BSS_CLEAR to disable zeroing uninitialzed data in startup.
*/
#ifndef __SKIP_BSS_CLEAR
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#endif /* __SKIP_BSS_CLEAR */
#ifndef __SKIP_LIBC_INIT_ARRAY
ldr r0, =__libc_init_array
blx r0
#endif
ldr r0, =main
blx r0
.align 2
__copy_table_start__:
.long __data_load, __data_start, __data_size
.long __ram_code_load, __ram_code_start, __ram_code_size
__copy_table_end__:
__zero_table_start__:
.long __bss_start, __bss_size
.long USB_RAM_start, USB_RAM_size
.long ETH_RAM_start, ETH_RAM_size
__zero_table_end__:
.pool
.size Reset_Handler,.-Reset_Handler
/* ======================================================================== */
/* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */
/* Default exception Handlers - Users may override this default functionality by
defining handlers of the same name in their C code */
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
Insert_ExceptionHandler NMI_Handler
Insert_ExceptionHandler HardFault_Handler
Insert_ExceptionHandler MemManage_Handler
Insert_ExceptionHandler BusFault_Handler
Insert_ExceptionHandler UsageFault_Handler
Insert_ExceptionHandler SVC_Handler
Insert_ExceptionHandler DebugMon_Handler
Insert_ExceptionHandler PendSV_Handler
Insert_ExceptionHandler SysTick_Handler
Insert_ExceptionHandler SCU_0_IRQHandler
Insert_ExceptionHandler ERU0_0_IRQHandler
Insert_ExceptionHandler ERU0_1_IRQHandler
Insert_ExceptionHandler ERU0_2_IRQHandler
Insert_ExceptionHandler ERU0_3_IRQHandler
Insert_ExceptionHandler ERU1_0_IRQHandler
Insert_ExceptionHandler ERU1_1_IRQHandler
Insert_ExceptionHandler ERU1_2_IRQHandler
Insert_ExceptionHandler ERU1_3_IRQHandler
Insert_ExceptionHandler PMU0_0_IRQHandler
Insert_ExceptionHandler VADC0_C0_0_IRQHandler
Insert_ExceptionHandler VADC0_C0_1_IRQHandler
Insert_ExceptionHandler VADC0_C0_2_IRQHandler
Insert_ExceptionHandler VADC0_C0_3_IRQHandler
Insert_ExceptionHandler VADC0_G0_0_IRQHandler
Insert_ExceptionHandler VADC0_G0_1_IRQHandler
Insert_ExceptionHandler VADC0_G0_2_IRQHandler
Insert_ExceptionHandler VADC0_G0_3_IRQHandler
Insert_ExceptionHandler VADC0_G1_0_IRQHandler
Insert_ExceptionHandler VADC0_G1_1_IRQHandler
Insert_ExceptionHandler VADC0_G1_2_IRQHandler
Insert_ExceptionHandler VADC0_G1_3_IRQHandler
Insert_ExceptionHandler VADC0_G2_0_IRQHandler
Insert_ExceptionHandler VADC0_G2_1_IRQHandler
Insert_ExceptionHandler VADC0_G2_2_IRQHandler
Insert_ExceptionHandler VADC0_G2_3_IRQHandler
Insert_ExceptionHandler VADC0_G3_0_IRQHandler
Insert_ExceptionHandler VADC0_G3_1_IRQHandler
Insert_ExceptionHandler VADC0_G3_2_IRQHandler
Insert_ExceptionHandler VADC0_G3_3_IRQHandler
Insert_ExceptionHandler DSD0_0_IRQHandler
Insert_ExceptionHandler DSD0_1_IRQHandler
Insert_ExceptionHandler DSD0_2_IRQHandler
Insert_ExceptionHandler DSD0_3_IRQHandler
Insert_ExceptionHandler DSD0_4_IRQHandler
Insert_ExceptionHandler DSD0_5_IRQHandler
Insert_ExceptionHandler DSD0_6_IRQHandler
Insert_ExceptionHandler DSD0_7_IRQHandler
Insert_ExceptionHandler DAC0_0_IRQHandler
Insert_ExceptionHandler DAC0_1_IRQHandler
Insert_ExceptionHandler CCU40_0_IRQHandler
Insert_ExceptionHandler CCU40_1_IRQHandler
Insert_ExceptionHandler CCU40_2_IRQHandler
Insert_ExceptionHandler CCU40_3_IRQHandler
Insert_ExceptionHandler CCU41_0_IRQHandler
Insert_ExceptionHandler CCU41_1_IRQHandler
Insert_ExceptionHandler CCU41_2_IRQHandler
Insert_ExceptionHandler CCU41_3_IRQHandler
Insert_ExceptionHandler CCU42_0_IRQHandler
Insert_ExceptionHandler CCU42_1_IRQHandler
Insert_ExceptionHandler CCU42_2_IRQHandler
Insert_ExceptionHandler CCU42_3_IRQHandler
Insert_ExceptionHandler CCU43_0_IRQHandler
Insert_ExceptionHandler CCU43_1_IRQHandler
Insert_ExceptionHandler CCU43_2_IRQHandler
Insert_ExceptionHandler CCU43_3_IRQHandler
Insert_ExceptionHandler CCU80_0_IRQHandler
Insert_ExceptionHandler CCU80_1_IRQHandler
Insert_ExceptionHandler CCU80_2_IRQHandler
Insert_ExceptionHandler CCU80_3_IRQHandler
Insert_ExceptionHandler CCU81_0_IRQHandler
Insert_ExceptionHandler CCU81_1_IRQHandler
Insert_ExceptionHandler CCU81_2_IRQHandler
Insert_ExceptionHandler CCU81_3_IRQHandler
Insert_ExceptionHandler POSIF0_0_IRQHandler
Insert_ExceptionHandler POSIF0_1_IRQHandler
Insert_ExceptionHandler POSIF1_0_IRQHandler
Insert_ExceptionHandler POSIF1_1_IRQHandler
Insert_ExceptionHandler CAN0_0_IRQHandler
Insert_ExceptionHandler CAN0_1_IRQHandler
Insert_ExceptionHandler CAN0_2_IRQHandler
Insert_ExceptionHandler CAN0_3_IRQHandler
Insert_ExceptionHandler CAN0_4_IRQHandler
Insert_ExceptionHandler CAN0_5_IRQHandler
Insert_ExceptionHandler CAN0_6_IRQHandler
Insert_ExceptionHandler CAN0_7_IRQHandler
Insert_ExceptionHandler USIC0_0_IRQHandler
Insert_ExceptionHandler USIC0_1_IRQHandler
Insert_ExceptionHandler USIC0_2_IRQHandler
Insert_ExceptionHandler USIC0_3_IRQHandler
Insert_ExceptionHandler USIC0_4_IRQHandler
Insert_ExceptionHandler USIC0_5_IRQHandler
Insert_ExceptionHandler USIC1_0_IRQHandler
Insert_ExceptionHandler USIC1_1_IRQHandler
Insert_ExceptionHandler USIC1_2_IRQHandler
Insert_ExceptionHandler USIC1_3_IRQHandler
Insert_ExceptionHandler USIC1_4_IRQHandler
Insert_ExceptionHandler USIC1_5_IRQHandler
Insert_ExceptionHandler USIC2_0_IRQHandler
Insert_ExceptionHandler USIC2_1_IRQHandler
Insert_ExceptionHandler USIC2_2_IRQHandler
Insert_ExceptionHandler USIC2_3_IRQHandler
Insert_ExceptionHandler USIC2_4_IRQHandler
Insert_ExceptionHandler USIC2_5_IRQHandler
Insert_ExceptionHandler LEDTS0_0_IRQHandler
Insert_ExceptionHandler FCE0_0_IRQHandler
Insert_ExceptionHandler GPDMA0_0_IRQHandler
Insert_ExceptionHandler SDMMC0_0_IRQHandler
Insert_ExceptionHandler USB0_0_IRQHandler
Insert_ExceptionHandler ETH0_0_IRQHandler
Insert_ExceptionHandler GPDMA1_0_IRQHandler
/* ============= END OF INTERRUPT HANDLER DEFINITION ====================== */
.end

734
Target/Demo/ARMCM4_XMC4_XMC4700_Relax_Kit_GCC/Boot/Startup/system_XMC4700.c Normal file
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@ -0,0 +1,734 @@
/*********************************************************************************************************************
* @file system_XMC4700.c
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the Infineon XMC4700 Device Series
* @version V1.0.3
* @date 09. Feb 2017
*
* @cond
*********************************************************************************************************************
* Copyright (c) 2015-2017, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG dave@infineon.com).
*********************************************************************************************************************
*
********************** Version History ***************************************
* V1.0.0, 03. Sep 2015, Initial version
* V1.0.1, 26. Jan 2016, Disable trap generation from clock unit
* V1.0.2, 01. Jun 2016, Fix masking of OSCHPCTRL value
* V1.0.3, 09. Feb 2017, Fix activation of USBPLL when SDMMC clock is enabled
******************************************************************************
* @endcond
*/
/*******************************************************************************
* Default clock initialization
* fPLL = 288MHz => fSYS = 144MHz => fCPU = 144MHz
* => fPB = 144MHz
* => fCCU = 144MHz
* => fETH = 72MHz
* => fUSB = 48MHz
* => fEBU = 72MHz
*
* fUSBPLL Disabled, only enabled if SCU_CLK_USBCLKCR_USBSEL_USBPLL is selected
*
* fOFI = 24MHz => fWDT = 24MHz
*******************************************************************************/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include <string.h>
#include <XMC4700.h>
#include "system_XMC4700.h"
/*******************************************************************************
* MACROS
*******************************************************************************/
#define CHIPID_LOC ((uint8_t *)0x20000000UL)
/* Define WEAK attribute */
#if !defined(__WEAK)
#if defined ( __CC_ARM )
#define __WEAK __attribute__ ((weak))
#elif defined ( __ICCARM__ )
#define __WEAK __weak
#elif defined ( __GNUC__ )
#define __WEAK __attribute__ ((weak))
#elif defined ( __TASKING__ )
#define __WEAK __attribute__ ((weak))
#endif
#endif
#define PMU_FLASH_WS (0x4U)
#define FOSCREF (2500000U)
#define DELAY_CNT_50US_50MHZ (2500UL)
#define DELAY_CNT_150US_50MHZ (7500UL)
#define DELAY_CNT_50US_48MHZ (2400UL)
#define DELAY_CNT_50US_72MHZ (3600UL)
#define DELAY_CNT_50US_96MHZ (4800UL)
#define DELAY_CNT_50US_120MHZ (6000UL)
#define DELAY_CNT_50US_144MHZ (7200UL)
#define SCU_PLL_PLLSTAT_OSC_USABLE (SCU_PLL_PLLSTAT_PLLHV_Msk | \
SCU_PLL_PLLSTAT_PLLLV_Msk | \
SCU_PLL_PLLSTAT_PLLSP_Msk)
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*
// <h> Clock configuration
*/
/*
// <o> External crystal frequency [Hz]
// <8000000=> 8MHz
// <12000000=> 12MHz
// <16000000=> 16MHz
// <i> Defines external crystal frequency
// <i> Default: 8MHz
*/
#define OSCHP_FREQUENCY (12000000U)
/* USB PLL settings, fUSBPLL = 48MHz and fUSBPLLVCO = 384 MHz */
/* Note: Implicit divider of 2 and fUSBPLLVCO >= 260 MHz and fUSBPLLVCO <= 520 MHz*/
#if OSCHP_FREQUENCY == 8000000U
#define USB_PDIV (1U)
#define USB_NDIV (95U)
#elif OSCHP_FREQUENCY == 12000000U
#define USB_PDIV (1U)
#define USB_NDIV (63U)
#elif OSCHP_FREQUENCY == 16000000U
#define USB_PDIV (1U)
#define USB_NDIV (47U)
#else
#error "External crystal frequency not supported"
#endif
/*
// <o> Backup clock calibration mode
// <0=> Factory calibration
// <1=> Automatic calibration
// <i> Default: Automatic calibration
*/
#define FOFI_CALIBRATION_MODE 1
#define FOFI_CALIBRATION_MODE_FACTORY 0
#define FOFI_CALIBRATION_MODE_AUTOMATIC 1
/*
// <o> Standby clock (fSTDBY) source selection
// <0=> Internal slow oscillator (32768Hz)
// <1=> External crystal (32768Hz)
// <i> Default: Internal slow oscillator (32768Hz)
*/
#define STDBY_CLOCK_SRC 0
#define STDBY_CLOCK_SRC_OSI 0
#define STDBY_CLOCK_SRC_OSCULP 1
/*
// <o> PLL clock source selection
// <0=> External crystal
// <1=> Internal fast oscillator
// <i> Default: External crystal
*/
#define PLL_CLOCK_SRC 0
#define PLL_CLOCK_SRC_EXT_XTAL 0
#define PLL_CLOCK_SRC_OFI 1
/* PLL settings, fPLL = 288MHz */
#if PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL
#if OSCHP_FREQUENCY == 8000000U
#define PLL_PDIV (1U)
#define PLL_NDIV (71U)
#define PLL_K2DIV (0U)
#elif OSCHP_FREQUENCY == 12000000U
#define PLL_PDIV (1U)
#define PLL_NDIV (47U)
#define PLL_K2DIV (0U)
#elif OSCHP_FREQUENCY == 16000000U
#define PLL_PDIV (1U)
#define PLL_NDIV (35U)
#define PLL_K2DIV (0U)
#else
#error "External crystal frequency not supported"
#endif
#define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
#else /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL */
#define PLL_PDIV (1U)
#define PLL_NDIV (23U)
#define PLL_K2DIV (0U)
#define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
#endif /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_OFI */
#define PLL_K2DIV_24MHZ ((VCO / OFI_FREQUENCY) - 1UL)
#define PLL_K2DIV_48MHZ ((VCO / 48000000U) - 1UL)
#define PLL_K2DIV_72MHZ ((VCO / 72000000U) - 1UL)
#define PLL_K2DIV_96MHZ ((VCO / 96000000U) - 1UL)
#define PLL_K2DIV_120MHZ ((VCO / 120000000U) - 1UL)
#define SCU_CLK_CLKCLR_ENABLE_USBCLK SCU_CLK_CLKCLR_USBCDI_Msk
#define SCU_CLK_CLKCLR_ENABLE_MMCCLK SCU_CLK_CLKCLR_MMCCDI_Msk
#define SCU_CLK_CLKCLR_ENABLE_ETHCLK SCU_CLK_CLKCLR_ETH0CDI_Msk
#define SCU_CLK_CLKCLR_ENABLE_EBUCLK SCU_CLK_CLKCLR_EBUCDI_Msk
#define SCU_CLK_CLKCLR_ENABLE_CCUCLK SCU_CLK_CLKCLR_CCUCDI_Msk
#define SCU_CLK_CLKCLR_ENABLE_WDTCLK SCU_CLK_CLKCLR_WDTCDI_Msk
#define SCU_CLK_SYSCLKCR_SYSSEL_OFI (0U << SCU_CLK_SYSCLKCR_SYSSEL_Pos)
#define SCU_CLK_SYSCLKCR_SYSSEL_PLL (1U << SCU_CLK_SYSCLKCR_SYSSEL_Pos)
#define SCU_CLK_USBCLKCR_USBSEL_USBPLL (0U << SCU_CLK_USBCLKCR_USBSEL_Pos)
#define SCU_CLK_USBCLKCR_USBSEL_PLL (1U << SCU_CLK_USBCLKCR_USBSEL_Pos)
#define SCU_CLK_WDTCLKCR_WDTSEL_OFI (0U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
#define SCU_CLK_WDTCLKCR_WDTSEL_STANDBY (1U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
#define SCU_CLK_WDTCLKCR_WDTSEL_PLL (2U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
#define SCU_CLK_EXTCLKCR_ECKSEL_SYS (0U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
#define SCU_CLK_EXTCLKCR_ECKSEL_USBPLL (2U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
#define SCU_CLK_EXTCLKCR_ECKSEL_PLL (3U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
#define EXTCLK_PIN_P0_8 (1)
#define EXTCLK_PIN_P1_15 (2)
/*
// <h> Clock tree
// <o1.16> System clock source selection
// <0=> fOFI
// <1=> fPLL
// <i> Default: fPLL
// <o1.0..7> System clock divider <1-256><#-1>
// <i> Default: 2
// <o2.0> CPU clock divider
// <0=> fCPU = fSYS
// <1=> fCPU = fSYS / 2
// <i> Default: fCPU = fSYS
// <o3.0> Peripheral clock divider
// <0=> fPB = fCPU
// <1=> fPB = fCPU / 2
// <i> Default: fPB = fCPU
// <o4.0> CCU clock divider
// <0=> fCCU = fCPU
// <1=> fCCU = fCPU / 2
// <i> Default: fCCU = fCPU
// <e.5> Enable WDT clock
// <o5.16..17> WDT clock source <0=> fOFI
// <1=> fSTDBY
// <2=> fPLL
// <i> Default: fOFI
// <o5.0..7> WDT clock divider <1-256><#-1>
// <i> Default: 1
// </e>
// <e.3> Enable EBU clock
// <o6.0..5> EBU clock divider <1-64><#-1>
// <i> Default: 4
// </e>
// <e.2> Enable ETH clock
// </e>
// <e.1> Enable MMC clock
// </e>
// <e.0> Enable USB clock
// <o7.16> USB clock source <0=> fUSBPLL
// <1=> fPLL
// <i> Default: fPLL
// </e>
// <e8> Enable external clock
// <o8.0..1> External Clock Source Selection
// <0=> fSYS
// <2=> fUSB
// <3=> fPLL
// <i> Default: fPLL
// <o8.16..24> External Clock divider <1-512><#-1>
// <i> Default: 288
// <i> Only valid for USB PLL and PLL clocks
// <o9.0> External Clock Pin Selection
// <0=> Disabled
// <1=> P0.8
// <2=> P1.15
// <i> Default: Disabled
// </e>
// </h>
*/
#define __CLKSET (0x00000000UL)
#define __SYSCLKCR (0x00010001UL)
#define __CPUCLKCR (0x00000000UL)
#define __PBCLKCR (0x00000000UL)
#define __CCUCLKCR (0x00000000UL)
#define __WDTCLKCR (0x00000000UL)
#define __EBUCLKCR (0x00000003UL)
#define __USBCLKCR (0x00010000UL)
#define __EXTCLKCR (0x01200003UL)
#define __EXTCLKPIN (0U)
/*
// </h>
*/
/*
//-------- <<< end of configuration section >>> ------------------
*/
#define ENABLE_PLL \
(((__SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) == SCU_CLK_SYSCLKCR_SYSSEL_PLL) || \
((__CLKSET & SCU_CLK_CLKSET_EBUCEN_Msk) != 0) || \
(((__CLKSET & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_PLL)) || \
(((__CLKSET & SCU_CLK_CLKSET_WDTCEN_Msk) != 0) && ((__WDTCLKCR & SCU_CLK_WDTCLKCR_WDTSEL_Msk) == SCU_CLK_WDTCLKCR_WDTSEL_PLL)))
#define ENABLE_USBPLL \
((((__CLKSET & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL)) || \
(((__CLKSET & SCU_CLK_CLKSET_MMCCEN_Msk) != 0) && ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL)))
#if ((__USBCLKCR & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL)
#define USB_DIV (3U)
#else
#define USB_DIV (5U)
#endif
/*******************************************************************************
* GLOBAL VARIABLES
*******************************************************************************/
#if defined ( __CC_ARM )
#if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048)
uint32_t SystemCoreClock __attribute__((at(0x2003FFC0)));
uint8_t g_chipid[16] __attribute__((at(0x2003FFC4)));
#elif defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536)
uint32_t SystemCoreClock __attribute__((at(0x2002CFC0)));
uint8_t g_chipid[16] __attribute__((at(0x2002CFC4)));
#else
#error "system_XMC4700.c: device not supported"
#endif
#elif defined ( __ICCARM__ )
#if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048) || \
defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536)
__no_init uint32_t SystemCoreClock;
__no_init uint8_t g_chipid[16];
#else
#error "system_XMC4700.c: device not supported"
#endif
#elif defined ( __GNUC__ )
#if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048) || \
defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536)
uint32_t SystemCoreClock __attribute__((section(".no_init")));
uint8_t g_chipid[16] __attribute__((section(".no_init")));
#else
#error "system_XMC4700.c: device not supported"
#endif
#elif defined ( __TASKING__ )
#if defined(XMC4700_E196x2048) || defined(XMC4700_F144x2048) || defined(XMC4700_F100x2048)
uint32_t SystemCoreClock __at( 0x2003FFC0 );
uint8_t g_chipid[16] __at( 0x2003FFC4 );
#elif defined(XMC4700_E196x1536) || defined(XMC4700_F144x1536) || defined(XMC4700_F100x1536)
uint32_t SystemCoreClock __at( 0x2002CFC0 );
uint8_t g_chipid[16] __at( 0x2002CFC4 );
#else
#error "system_XMC4700.c: device not supported"
#endif
#else
#error "system_XMC4700.c: compiler not supported"
#endif
extern uint32_t __Vectors;
/*******************************************************************************
* LOCAL FUNCTIONS
*******************************************************************************/
static void delay(uint32_t cycles)
{
volatile uint32_t i;
for(i = 0UL; i < cycles ;++i)
{
__NOP();
}
}
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
__WEAK void SystemInit(void)
{
memcpy(g_chipid, CHIPID_LOC, 16);
SystemCoreSetup();
SystemCoreClockSetup();
}
__WEAK void SystemCoreSetup(void)
{
uint32_t temp;
/* relocate vector table */
__disable_irq();
SCB->VTOR = (uint32_t)(&__Vectors);
__DSB();
__enable_irq();
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
temp = FLASH0->FCON;
temp &= ~FLASH_FCON_WSPFLASH_Msk;
temp |= PMU_FLASH_WS;
FLASH0->FCON = temp;
}
__WEAK void SystemCoreClockSetup(void)
{
#if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY
/* Enable factory calibration */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk;
#else
/* Automatic calibration uses the fSTDBY */
/* Enable HIB domain */
/* Power up HIB domain if and only if it is currently powered down */
if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
{
SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk;
while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
{
/* wait until HIB domain is enabled */
}
}
/* Remove the reset only if HIB domain were in a state of reset */
if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk)
{
SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk;
delay(DELAY_CNT_150US_50MHZ);
}
#if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP
/* Enable OSC_ULP */
if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL)
{
/*enable OSC_ULP*/
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk;
/* Check if the clock is OK using OSCULP Oscillator Watchdog*/
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
/* wait till clock is stable */
do
{
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
delay(DELAY_CNT_50US_50MHZ);
} while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL);
}
/* now OSC_ULP is running and can be used*/
/* Select OSC_ULP as the clock source for RTC and STDBY*/
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
#endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */
/* Enable automatic calibration of internal fast oscillator */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
#endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */
delay(DELAY_CNT_50US_50MHZ);
#if ENABLE_PLL
/* enable PLL */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
#if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI
/* enable OSC_HP */
if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
{
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
/* select OSC_HP clock as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
{
/* wait till OSC_HP output frequency is usable */
}
}
#else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */
/* select backup clock as PLL input */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
#endif
/* Go to bypass the Main PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
/* disconnect Oscillator from PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
/* Setup divider settings for main PLL */
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
(PLL_K2DIV_24MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) |
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
/* Set OSCDISCDIS */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/* connect Oscillator to PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
{
/* wait for PLL Lock at 24MHz*/
}
/* Disable bypass- put PLL clock back */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U)
{
/* wait for normal mode */
}
#endif /* ENABLE_PLL */
/* Before scaling to final frequency we need to setup the clock dividers */
SCU_CLK->SYSCLKCR = __SYSCLKCR;
SCU_CLK->PBCLKCR = __PBCLKCR;
SCU_CLK->CPUCLKCR = __CPUCLKCR;
SCU_CLK->CCUCLKCR = __CCUCLKCR;
SCU_CLK->WDTCLKCR = __WDTCLKCR;
SCU_CLK->EBUCLKCR = __EBUCLKCR;
SCU_CLK->USBCLKCR = __USBCLKCR | USB_DIV;
SCU_CLK->EXTCLKCR = __EXTCLKCR;
#if ENABLE_PLL
/* PLL frequency stepping...*/
/* Reset OSCDISCDIS */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
(PLL_K2DIV_48MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) |
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
delay(DELAY_CNT_50US_48MHZ);
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
(PLL_K2DIV_72MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) |
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
delay(DELAY_CNT_50US_72MHZ);
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
(PLL_K2DIV_96MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) |
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
delay(DELAY_CNT_50US_96MHZ);
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
(PLL_K2DIV_120MHZ << SCU_PLL_PLLCON1_K2DIV_Pos) |
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
delay(DELAY_CNT_50US_120MHZ);
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
(PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) |
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
delay(DELAY_CNT_50US_144MHZ);
#endif /* ENABLE_PLL */
#if ENABLE_USBPLL
/* enable USB PLL first */
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
/* USB PLL uses as clock input the OSC_HP */
/* check and if not already running enable OSC_HP */
if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
{
/* check if Main PLL is switched on for OSC WDG*/
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL)
{
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Msk);
SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
{
/* wait till OSC_HP output frequency is usable */
}
}
/* Setup USB PLL */
/* Go to bypass the USB PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
/* disconnect Oscillator from USB PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
/* Setup Divider settings for USB PLL */
SCU_PLL->USBPLLCON = ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) |
(USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos));
/* Set OSCDISCDIS */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
/* connect Oscillator to USB PLL */
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U)
{
/* wait for PLL Lock */
}
#endif
/* Enable selected clocks */
SCU_CLK->CLKSET = __CLKSET;
#if __EXTCLKPIN != 0
#if __EXTCLKPIN == EXTCLK_PIN_P1_15
/* P1.15 */
PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk;
PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT0_IOCR12_PC15_Msk) | (0x11U << PORT0_IOCR12_PC15_Pos);
#else
/* P0.8 */
PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk;
PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk;
PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos);
#endif
#endif /* ENABLE_EXTCLK == 1 */
SystemCoreClockUpdate();
}
__WEAK void SystemCoreClockUpdate(void)
{
uint32_t pdiv;
uint32_t ndiv;
uint32_t kdiv;
uint32_t temp;
if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk)
{
/* fPLL is clock source for fSYS */
if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk)
{
/* PLL input clock is the backup clock (fOFI) */
temp = OFI_FREQUENCY;
}
else
{
/* PLL input clock is the high performance osicllator (fOSCHP) */
temp = OSCHP_GetFrequency();
}
/* check if PLL is locked */
if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)
{
/* PLL normal mode */
/* read back divider settings */
pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1;
ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1;
kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1;
temp = (temp / (pdiv * kdiv)) * ndiv;
}
else
{
/* PLL prescalar mode */
/* read back divider settings */
kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1;
temp = (temp / kdiv);
}
}
else
{
/* fOFI is clock source for fSYS */
temp = OFI_FREQUENCY;
}
temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1);
temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1);
SystemCoreClock = temp;
}
__WEAK uint32_t OSCHP_GetFrequency(void)
{
return OSCHP_FREQUENCY;
}

175
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/************************************************************************************//**
* \file Demo\ARMCM4_XMC4_XMC4700_Relax_Kit_GCC\Boot\blt_conf.h
* \brief Bootloader configuration header file.
* \ingroup Boot_ARMCM4_XMC4_XMC4700_Relax_Kit_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BLT_CONF_H
#define BLT_CONF_H
/****************************************************************************************
* C P U D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* To properly initialize the baudrate clocks of the communication interface, typically
* the speed of the crystal oscillator and/or the speed at which the system runs is
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
* little endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
/** \brief Frequency of the external crystal oscillator. */
#define BOOT_CPU_XTAL_SPEED_KHZ (12000)
/** \brief Desired system speed. */
#define BOOT_CPU_SYSTEM_SPEED_KHZ (144000)
/** \brief Motorola or Intel style byte ordering. */
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
/** \brief Enable/disable hook function call right before user program start. */
#define BOOT_CPU_USER_PROGRAM_START_HOOK (1)
/****************************************************************************************
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
****************************************************************************************/
/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
* configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
* in bits/second. Two CAN messages are reserved for communication with the host. The
* message identifier for sending data from the target to the host is configured with
* BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
* BOOT_COM_CAN_RXMSG_ID. The maximum amount of data bytes in a message for data
* transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
* BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
* than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
* CAN controller channel.
*
*/
/** \brief Enable/disable CAN transport layer. */
#define BOOT_COM_CAN_ENABLE (1)
/** \brief Configure the desired CAN baudrate. */
#define BOOT_COM_CAN_BAUDRATE (500000)
/** \brief Configure CAN message ID target->host. */
#define BOOT_COM_CAN_TX_MSG_ID (0x7E1)
/** \brief Configure number of bytes in the target->host CAN message. */
#define BOOT_COM_CAN_TX_MAX_DATA (8)
/** \brief Configure CAN message ID host->target. */
#define BOOT_COM_CAN_RX_MSG_ID (0x667)
/** \brief Configure number of bytes in the host->target CAN message. */
#define BOOT_COM_CAN_RX_MAX_DATA (8)
/** \brief Select the desired CAN peripheral as a zero based index. */
#define BOOT_COM_CAN_CHANNEL_INDEX (1)
/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
* configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
* in bits/second. The maximum amount of data bytes in a message for data transmission
* and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
* respectively. It is common for a microcontroller to have more than 1 UART interface
* on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
*
*/
/** \brief Enable/disable UART transport layer. */
#define BOOT_COM_UART_ENABLE (1)
/** \brief Configure the desired communication speed. */
#define BOOT_COM_UART_BAUDRATE (57600)
/** \brief Configure number of bytes in the target->host data packet. */
#define BOOT_COM_UART_TX_MAX_DATA (64)
/** \brief Configure number of bytes in the host->target data packet. */
#define BOOT_COM_UART_RX_MAX_DATA (64)
/** \brief Select the desired UART peripheral as a zero based index. */
#define BOOT_COM_UART_CHANNEL_INDEX (0)
/****************************************************************************************
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
****************************************************************************************/
/* It is possible to implement an application specific method to force the bootloader to
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
* situations where the user program does not run properly and therefore cannot
* reactivate the bootloader. By enabling these hook functions, the application can
* implement the backdoor, which overrides the default backdoor entry that is programmed
* into the bootloader. When desired for security purposes, these hook functions can
* also be implemented in a way that disables the backdoor entry altogether.
*/
/** \brief Enable/disable the backdoor override hook functions. */
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The NVM driver typically supports erase and program operations of the internal memory
* present on the microcontroller. Through these hook functions the NVM driver can be
* extended to support additional memory types such as external flash memory and serial
* eeproms. The size of the internal memory in kilobytes is specified with configurable
* BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
* be overridden with a application specific method by enabling configuration switch
* BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
*/
/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
#define BOOT_NVM_HOOKS_ENABLE (0)
/** \brief Configure the size of the default memory device (typically flash EEPROM). */
#define BOOT_NVM_SIZE_KB (2048)
/** \brief Enable/disable hooks functions to override the user program checksum handling. */
#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
/****************************************************************************************
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The COP driver cannot be configured internally in the bootloader, because its use
* and configuration is application specific. The bootloader does need to service the
* watchdog in case it is used. When the application requires the use of a watchdog,
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
* hook functions.
*/
/** \brief Enable/disable the hook functions for controlling the watchdog. */
#define BOOT_COP_HOOKS_ENABLE (1)
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N
****************************************************************************************/
/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
* rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
* operations can be performed, access to this resource need to be unlocked.
* In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
* implements the unlocking algorithm. The demo programs are configured for the (simple)
* algorithm in "FeaserKey.dll". The source code for this DLL is available so it can be
* customized to your needs.
* During the unlock sequence, Microboot requests a seed from the bootloader, which is in
* the format of a byte array. Using this seed the unlock algorithm in the DLL computes
* a key, which is also a byte array, and sends this back to the bootloader. The
* bootloader then verifies this key to determine if programming and erase operations are
* permitted.
* After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
* are called by the bootloader to obtain the seed and to verify the key, respectively.
*/
#define BOOT_XCP_SEED_KEY_ENABLE (0)
#endif /* BLT_CONF_H */
/*********************************** end of blt_conf.h *********************************/

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